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// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2017/07/30 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_1_V
`define SKY130_FD_SC_LS__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_1_V
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module ila_0 (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20
);
input clk;
input [63 : 0] probe0;
input [63 : 0] probe1;
input [0 : 0] probe2;
input [0 : 0] probe3;
input [0 : 0] probe4;
input [0 : 0] probe5;
input [0 : 0] probe6;
input [63 : 0] probe7;
input [0 : 0] probe8;
input [0 : 0] probe9;
input [0 : 0] probe10;
input [0 : 0] probe11;
input [63 : 0] probe12;
input [0 : 0] probe13;
input [0 : 0] probe14;
input [0 : 0] probe15;
input [0 : 0] probe16;
input [0 : 0] probe17;
input [7 : 0] probe18;
input [7 : 0] probe19;
input [0 : 0] probe20;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: dtysky:user:CONTROL_UNIT:1.0
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MIPS_CPU_CONTROL_UNIT_0_1 (
op,
func,
z,
wreg,
regrt,
jal,
m2reg,
shfit,
aluimm,
sext,
wmem,
aluc,
pcsource
);
input wire [5 : 0] op;
input wire [5 : 0] func;
input wire z;
output wire wreg;
output wire regrt;
output wire jal;
output wire m2reg;
output wire shfit;
output wire aluimm;
output wire sext;
output wire wmem;
output wire [3 : 0] aluc;
output wire [1 : 0] pcsource;
CONTROL_UNIT #(
.cmd_add(6'B100000),
.cmd_sub(6'B100010),
.cmd_and(6'B100100),
.cmd_or(6'B100101),
.cmd_xor(6'B100110),
.cmd_sll(6'B000000),
.cmd_srl(6'B000010),
.cmd_sra(6'B000011),
.cmd_jr(6'B001000),
.cmd_addi(6'B001000),
.cmd_andi(6'B001100),
.cmd_ori(6'B001101),
.cmd_xori(6'B001110),
.cmd_lw(6'B100011),
.cmd_sw(6'B101011),
.cmd_beq(6'B000100),
.cmd_bne(6'B000101),
.cmd_lui(6'B001111),
.cmd_j(6'B000010),
.cmd_jal(6'B000011)
) inst (
.op(op),
.func(func),
.z(z),
.wreg(wreg),
.regrt(regrt),
.jal(jal),
.m2reg(m2reg),
.shfit(shfit),
.aluimm(aluimm),
.sext(sext),
.wmem(wmem),
.aluc(aluc),
.pcsource(pcsource)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_2_V
`define SKY130_FD_SC_LS__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_2_V
|
// -- (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (C_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (C_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate constant addition in vector range, and rhs.
//
//
module main ();
reg ['d4 + 'b110 : 0] val1;
reg [10'h1+ 'd9 : 0 ] val2 ;
initial
begin
val1 = 11'h1 + 'd4;
val2 = 11'h2 + 6;
if((val1 === 11'h5) && (val2 === 11'h8))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module rmii
(
input wire reset,
// PHY Interface
input wire phy_ref_clk,
output reg [1:0] phy_txd,
output wire phy_tx_en,
input wire [1:0] phy_rxd,
input wire phy_rx_er,
input wire phy_crs_dv,
// MAC Interface
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output reg [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
);
reg [1:0] tx_index;
reg [1:0] rx_index;
assign phy_tx_er = mac_tx_er;
assign phy_tx_en = mac_tx_en;
assign mac_col = phy_crs_dv & mac_tx_en;
assign mac_rx_er = phy_rx_er;
assign mac_crs = phy_crs_dv;
assign mac_rx_dv = phy_crs_dv;
clock_divider #(.DIVIDER(4)) clk_div
(
.reset(reset),
.clock_in(phy_ref_clk),
.clock_out(mac_tx_clk)
);
assign mac_rx_clk = mac_tx_clk;
always @(posedge phy_ref_clk)
begin
if (reset)
begin
tx_index <= 0;
end
else if (mac_tx_en && tx_index < 3)
begin
tx_index <= tx_index + 1;
end
else
begin
tx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
phy_txd <= 0;
end
else
begin
phy_txd <= mac_txd[tx_index*2+:2];
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
rx_index <= 0;
end
else if (phy_crs_dv && rx_index < 3)
begin
rx_index <= rx_index + 1;
end
else
begin
rx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
mac_rxd <= 0;
end
else
begin
mac_rxd[rx_index*2+:2] <= phy_rxd;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_clsm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_clsm(clk ,deltabit ,sz ,to_csr ,z_post ,we_csr ,
from_csr ,d ,synced_upd_imped ,updclk ,hard_reset_n ,adv_sgn ,si_l
,config_pmos ,se ,freeze ,so_l ,above ,bypass ,global_reset_n );
output [7:0] to_csr ;
output [7:0] z_post ;
output [7:0] d ;
input [7:0] sz ;
input [7:0] from_csr ;
output deltabit ;
output so_l ;
input clk ;
input we_csr ;
input synced_upd_imped ;
input updclk ;
input hard_reset_n ;
input adv_sgn ;
input si_l ;
input config_pmos ;
input se ;
input freeze ;
input above ;
input bypass ;
input global_reset_n ;
supply0 vss ;
wire [7:0] net0228 ;
wire [7:0] net0225 ;
wire [7:0] net0237 ;
wire [7:0] mz ;
wire [7:0] scan_data ;
wire [7:0] net0201 ;
wire [7:0] net0247 ;
wire [7:0] net0207 ;
wire [7:0] precnt ;
wire [7:0] net0209 ;
wire [7:0] net0189 ;
wire [7:0] net0186 ;
wire [7:0] net0246 ;
wire [7:0] net0204 ;
wire [7:0] net0146 ;
wire [7:0] net0212 ;
wire [7:0] net0192 ;
wire [7:0] net0198 ;
wire [7:0] z ;
wire [7:0] net0213 ;
wire [7:0] zbuf ;
wire [7:0] net0221 ;
wire [7:0] net0222 ;
wire net0174 ;
wire net087 ;
wire net088 ;
wire net186 ;
wire net189 ;
wire chose_z ;
wire down_cond ;
wire net192 ;
wire net195 ;
wire chose_z_n ;
wire net0154 ;
wire net0156 ;
wire net94 ;
wire net97 ;
wire cofgp_n ;
wire net0130 ;
wire net0134 ;
wire net0234 ;
wire updclkbuf ;
wire net0140 ;
wire net0141 ;
wire net0240 ;
wire net0243 ;
wire net0145 ;
wire net164 ;
wire net166 ;
wire net0216 ;
wire scan_in ;
wire net0417 ;
wire chzn ;
wire net170 ;
wire net0122 ;
wire net172 ;
wire net174 ;
wire net0323 ;
wire net0128 ;
wire scan_out ;
wire up_cond ;
bw_u1_inv_2x I128 (
.z (net164 ),
.a (global_reset_n ) );
bw_u1_nand2_4x I223_5_ (
.z (net0192[2] ),
.a (net0207[2] ),
.b (net0189[2] ) );
bw_u1_soffm2_4x I166_0_ (
.q (z[0] ),
.so (scan_out ),
.ck (clk ),
.d0 (precnt[0] ),
.d1 (net0192[7] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[1] ) );
bw_u1_nand2_2x I265_2_ (
.z (net0209[5] ),
.a (net0221[5] ),
.b (net0145 ) );
bw_u1_nand2_2x I225_1_ (
.z (net0189[6] ),
.a (synced_upd_imped ),
.b (sz[1] ) );
bw_u1_nand2_2x I264_0_ (
.z (net0212[7] ),
.a (freeze ),
.b (zbuf[0] ) );
bw_u1_nand2_2x I224_7_ (
.z (net0207[0] ),
.a (mz[7] ),
.b (net0174 ) );
bw_u1_nand2_2x I229_1_ (
.z (net0204[6] ),
.a (net0128 ),
.b (zbuf[0] ) );
bw_u1_nand2_2x I266_4_ (
.z (mz[4] ),
.a (net0209[3] ),
.b (net0212[3] ) );
bw_u1_inv_5x I269_2_ (
.z (zbuf[2] ),
.a (net0146[5] ) );
bw_u1_nand2_2x I228_7_ (
.z (net0246[0] ),
.a (net0247[0] ),
.b (net087 ) );
bw_u1_nand2_4x I235_1_ (
.z (net0247[6] ),
.a (net0213[6] ),
.b (net0186[6] ) );
bw_u1_nand2_2x I230_7_ (
.z (net0221[0] ),
.a (net0246[0] ),
.b (net0204[0] ) );
bw_u1_nand2_2x I233_5_ (
.z (net0186[2] ),
.a (net0141 ),
.b (z[6] ) );
bw_u1_nand2_4x I239_1_ (
.z (precnt[1] ),
.a (net0225[6] ),
.b (net0222[6] ) );
bw_u1_nand2_2x I237_5_ (
.z (net0222[2] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I234_7_ (
.z (net0213[0] ),
.a (z[7] ),
.b (net088 ) );
bw_u1_nand2_2x I238_7_ (
.z (net0225[0] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I241_1_ (
.z (net0237[6] ),
.a (net0154 ),
.b (zbuf[2] ) );
bw_u1_nor2_2x I131 (
.z (net97 ),
.a (net170 ),
.b (freeze ) );
bw_u1_nand2_4x I243_5_ (
.z (d[5] ),
.a (net0228[2] ),
.b (net0237[2] ) );
bw_u1_inv_4x I132 (
.z (net174 ),
.a (net189 ) );
bw_u1_nand2_2x I242_3_ (
.z (net0228[4] ),
.a (zbuf[3] ),
.b (chose_z ) );
bw_u1_nand2_4x I246_3_ (
.z (z_post[3] ),
.a (net0198[4] ),
.b (net0201[4] ) );
bw_u1_nand2_2x I133 (
.z (net189 ),
.a (net94 ),
.b (net97 ) );
bw_u1_nand2_2x I247_5_ (
.z (net0198[2] ),
.a (from_csr[5] ),
.b (we_csr ) );
bw_u1_nand3_4x I231 (
.z (net087 ),
.a (updclkbuf ),
.b (chose_z ),
.c (up_cond ) );
bw_u1_nand2_4x I134 (
.z (net186 ),
.a (updclkbuf ),
.b (net0417 ) );
bw_u1_nand2_2x I248_7_ (
.z (net0201[0] ),
.a (net0130 ),
.b (zbuf[7] ) );
bw_u1_inv_5x I232 (
.z (net0128 ),
.a (net087 ) );
bw_u1_inv_2x I135 (
.z (net170 ),
.a (net186 ) );
bw_u1_inv_4x I215_0_ (
.z (net0146[7] ),
.a (z[0] ) );
bw_u1_inv_8x I214_6_ (
.z (to_csr[6] ),
.a (net0146[1] ) );
bw_u1_inv_2x I137 (
.z (net172 ),
.a (above ) );
bw_u1_inv_4x I236 (
.z (net0134 ),
.a (config_pmos ) );
bw_u1_inv_2x I138 (
.z (net166 ),
.a (adv_sgn ) );
bw_u1_nand2_4x I223_4_ (
.z (net0192[3] ),
.a (net0207[3] ),
.b (net0189[3] ) );
bw_u1_nand2_2x I265_1_ (
.z (net0209[6] ),
.a (net0221[6] ),
.b (net0145 ) );
bw_u1_nand2_2x I224_6_ (
.z (net0207[1] ),
.a (mz[6] ),
.b (net0174 ) );
bw_u1_nand2_2x I225_0_ (
.z (net0189[7] ),
.a (synced_upd_imped ),
.b (sz[0] ) );
bw_u1_soffm2_4x I166_7_ (
.q (z[7] ),
.so (scan_data[7] ),
.ck (clk ),
.d0 (precnt[7] ),
.d1 (net0192[0] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[0] ) );
bw_u1_nand2_2x I228_6_ (
.z (net0246[1] ),
.a (net0247[1] ),
.b (net087 ) );
bw_u1_nand2_2x I229_0_ (
.z (net0204[7] ),
.a (net0128 ),
.b (cofgp_n ) );
bw_u1_nand2_2x I266_3_ (
.z (mz[3] ),
.a (net0209[4] ),
.b (net0212[4] ) );
bw_u1_nand2_2x I264_7_ (
.z (net0212[0] ),
.a (freeze ),
.b (zbuf[7] ) );
bw_u1_inv_5x I269_1_ (
.z (zbuf[1] ),
.a (net0146[6] ) );
bw_u1_nand2_2x I230_6_ (
.z (net0221[1] ),
.a (net0246[1] ),
.b (net0204[1] ) );
bw_u1_nand2_4x I235_0_ (
.z (net0247[7] ),
.a (net0213[7] ),
.b (net0186[7] ) );
bw_u1_nand2_2x I234_6_ (
.z (net0213[1] ),
.a (z[6] ),
.b (net088 ) );
bw_u1_nand2_2x I233_4_ (
.z (net0186[3] ),
.a (net0141 ),
.b (z[5] ) );
bw_u1_nand2_4x I239_0_ (
.z (precnt[0] ),
.a (net0225[7] ),
.b (net0222[7] ) );
bw_u1_nand2_2x I238_6_ (
.z (net0225[1] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I237_4_ (
.z (net0222[3] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I141 (
.z (net192 ),
.a (updclkbuf ),
.b (net0323 ) );
bw_u1_nand2_2x I241_0_ (
.z (net0237[7] ),
.a (net0154 ),
.b (zbuf[1] ) );
bw_u1_nand2_2x I242_2_ (
.z (net0228[5] ),
.a (zbuf[2] ),
.b (chose_z ) );
bw_u1_nand2_4x I243_4_ (
.z (d[4] ),
.a (net0228[3] ),
.b (net0237[3] ) );
bw_u1_nand2_4x I142 (
.z (net195 ),
.a (net192 ),
.b (chose_z ) );
bw_u1_nand2_4x I246_2_ (
.z (z_post[2] ),
.a (net0198[5] ),
.b (net0201[5] ) );
bw_u1_inv_8x I240 (
.z (net0154 ),
.a (chose_z ) );
bw_u1_nand2_2x I248_6_ (
.z (net0201[1] ),
.a (net0130 ),
.b (zbuf[6] ) );
bw_u1_nand2_2x I247_4_ (
.z (net0198[3] ),
.a (from_csr[4] ),
.b (we_csr ) );
bw_u1_inv_8x I214_5_ (
.z (to_csr[5] ),
.a (net0146[2] ) );
bw_u1_inv_4x I215_7_ (
.z (net0146[0] ),
.a (z[7] ) );
bw_u1_inv_8x I245 (
.z (net0130 ),
.a (we_csr ) );
bw_u1_nand2_4x I223_3_ (
.z (net0192[4] ),
.a (net0207[4] ),
.b (net0189[4] ) );
bw_u1_soffm2_4x I166_6_ (
.q (z[6] ),
.so (scan_data[6] ),
.ck (clk ),
.d0 (precnt[6] ),
.d1 (net0192[1] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[7] ) );
bw_u1_nand2_2x I265_0_ (
.z (net0209[7] ),
.a (net0221[7] ),
.b (net0145 ) );
bw_u1_nand2_2x I224_5_ (
.z (net0207[2] ),
.a (mz[5] ),
.b (net0174 ) );
bw_u1_nand2_2x I266_2_ (
.z (mz[2] ),
.a (net0209[5] ),
.b (net0212[5] ) );
bw_u1_nand2_2x I264_6_ (
.z (net0212[1] ),
.a (freeze ),
.b (zbuf[6] ) );
bw_u1_nand2_2x I228_5_ (
.z (net0246[2] ),
.a (net0247[2] ),
.b (net087 ) );
bw_u1_nand2_2x I225_7_ (
.z (net0189[0] ),
.a (synced_upd_imped ),
.b (sz[7] ) );
bw_u1_inv_5x I269_0_ (
.z (zbuf[0] ),
.a (net0146[7] ) );
bw_u1_nand2_2x I229_7_ (
.z (net0204[0] ),
.a (net0128 ),
.b (zbuf[6] ) );
bw_u1_nand2_2x I230_5_ (
.z (net0221[2] ),
.a (net0246[2] ),
.b (net0204[2] ) );
bw_u1_nand2_2x I234_5_ (
.z (net0213[2] ),
.a (z[5] ),
.b (net088 ) );
bw_u1_nand2_2x I233_3_ (
.z (net0186[4] ),
.a (net0141 ),
.b (z[4] ) );
bw_u1_nand2_4x I235_7_ (
.z (net0247[0] ),
.a (net0213[0] ),
.b (net0186[0] ) );
bw_u1_nand2_2x I238_5_ (
.z (net0225[2] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I237_3_ (
.z (net0222[4] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_4x I239_7_ (
.z (precnt[7] ),
.a (net0225[0] ),
.b (net0222[0] ) );
bw_u1_nand2_2x I242_1_ (
.z (net0228[6] ),
.a (zbuf[1] ),
.b (chose_z ) );
bw_u1_nand2_4x I243_3_ (
.z (d[3] ),
.a (net0228[4] ),
.b (net0237[4] ) );
bw_u1_nand2_4x I246_1_ (
.z (z_post[1] ),
.a (net0198[6] ),
.b (net0201[6] ) );
bw_u1_nand2_2x I241_7_ (
.z (net0237[0] ),
.a (net0154 ),
.b (config_pmos ) );
bw_u1_nand2_2x I248_5_ (
.z (net0201[2] ),
.a (net0130 ),
.b (zbuf[5] ) );
bw_u1_nand2_2x I247_3_ (
.z (net0198[4] ),
.a (from_csr[3] ),
.b (we_csr ) );
bw_u1_nand2_2x I252 (
.z (net0234 ),
.a (adv_sgn ),
.b (net0156 ) );
bw_u1_nand2_2x I253 (
.z (net0216 ),
.a (bypass ),
.b (net172 ) );
bw_u1_inv_4x I215_6_ (
.z (net0146[1] ),
.a (z[6] ) );
bw_u1_inv_2x I254 (
.z (net0156 ),
.a (bypass ) );
bw_u1_inv_8x I214_4_ (
.z (to_csr[4] ),
.a (net0146[3] ) );
bw_u1_nand2_2x I255 (
.z (net0240 ),
.a (net166 ),
.b (net0122 ) );
bw_u1_nand2_2x I256 (
.z (net0243 ),
.a (bypass ),
.b (above ) );
bw_u1_nand2_4x I223_2_ (
.z (net0192[5] ),
.a (net0207[5] ),
.b (net0189[5] ) );
bw_u1_inv_2x I257 (
.z (net0122 ),
.a (bypass ) );
bw_u1_soffm2_4x I166_5_ (
.q (z[5] ),
.so (scan_data[5] ),
.ck (clk ),
.d0 (precnt[5] ),
.d1 (net0192[2] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[6] ) );
bw_u1_nand2_2x I224_4_ (
.z (net0207[3] ),
.a (mz[4] ),
.b (net0174 ) );
bw_u1_nand2_2x I225_6_ (
.z (net0189[1] ),
.a (synced_upd_imped ),
.b (sz[6] ) );
bw_u1_nand2_2x I266_1_ (
.z (mz[1] ),
.a (net0209[6] ),
.b (net0212[6] ) );
bw_u1_nand2_2x I264_5_ (
.z (net0212[2] ),
.a (freeze ),
.b (zbuf[5] ) );
bw_u1_nand2_5x I258 (
.z (up_cond ),
.a (net0240 ),
.b (net0243 ) );
bw_u1_inv_4x I259 (
.z (net0323 ),
.a (up_cond ) );
bw_u1_nand2_2x I228_4_ (
.z (net0246[3] ),
.a (net0247[3] ),
.b (net087 ) );
bw_u1_nand2_2x I265_7_ (
.z (net0209[0] ),
.a (net0221[0] ),
.b (net0145 ) );
bw_u1_nand2_2x I229_6_ (
.z (net0204[1] ),
.a (net0128 ),
.b (zbuf[5] ) );
bw_u1_inv_5x I269_7_ (
.z (zbuf[7] ),
.a (net0146[0] ) );
bw_u1_nand2_2x I230_4_ (
.z (net0221[3] ),
.a (net0246[3] ),
.b (net0204[3] ) );
bw_u1_nand2_2x I233_2_ (
.z (net0186[5] ),
.a (net0141 ),
.b (z[3] ) );
bw_u1_nand2_4x I235_6_ (
.z (net0247[1] ),
.a (net0213[1] ),
.b (net0186[1] ) );
bw_u1_nand2_2x I237_2_ (
.z (net0222[5] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I234_4_ (
.z (net0213[3] ),
.a (z[4] ),
.b (net088 ) );
bw_u1_nand2_4x I239_6_ (
.z (precnt[6] ),
.a (net0225[1] ),
.b (net0222[1] ) );
bw_u1_nand2_2x I238_4_ (
.z (net0225[3] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_4x I243_2_ (
.z (d[2] ),
.a (net0228[5] ),
.b (net0237[5] ) );
bw_u1_nand2_2x I241_6_ (
.z (net0237[1] ),
.a (net0154 ),
.b (zbuf[7] ) );
bw_u1_nand2_2x I242_0_ (
.z (net0228[7] ),
.a (zbuf[0] ),
.b (chose_z ) );
bw_u1_nand2_4x I246_0_ (
.z (z_post[0] ),
.a (net0198[7] ),
.b (net0201[7] ) );
bw_u1_nand2_2x I247_2_ (
.z (net0198[5] ),
.a (from_csr[2] ),
.b (we_csr ) );
bw_u1_nand2_5x I260 (
.z (down_cond ),
.a (net0234 ),
.b (net0216 ) );
bw_u1_nand2_2x I248_4_ (
.z (net0201[3] ),
.a (net0130 ),
.b (zbuf[4] ) );
bw_u1_inv_2x I261 (
.z (net0417 ),
.a (down_cond ) );
bw_u1_inv_8x I262 (
.z (deltabit ),
.a (chzn ) );
bw_u1_inv_4x I215_5_ (
.z (net0146[2] ),
.a (z[5] ) );
bw_u1_inv_8x I214_3_ (
.z (to_csr[3] ),
.a (net0146[4] ) );
bw_u1_nand2_4x I223_1_ (
.z (net0192[6] ),
.a (net0207[6] ),
.b (net0189[6] ) );
bw_u1_inv_8x I267 (
.z (net0145 ),
.a (freeze ) );
bw_u1_soffm2_4x I166_4_ (
.q (z[4] ),
.so (scan_data[4] ),
.ck (clk ),
.d0 (precnt[4] ),
.d1 (net0192[3] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[5] ) );
bw_u1_nand2_2x I265_6_ (
.z (net0209[1] ),
.a (net0221[1] ),
.b (net0145 ) );
bw_u1_nand2_2x I224_3_ (
.z (net0207[4] ),
.a (mz[3] ),
.b (net0174 ) );
bw_u1_nand2_2x I225_5_ (
.z (net0189[2] ),
.a (synced_upd_imped ),
.b (sz[5] ) );
bw_u1_nand2_2x I266_0_ (
.z (mz[0] ),
.a (net0209[7] ),
.b (net0212[7] ) );
bw_u1_nand2_2x I264_4_ (
.z (net0212[3] ),
.a (freeze ),
.b (zbuf[4] ) );
bw_u1_nand2_2x I228_3_ (
.z (net0246[4] ),
.a (net0247[4] ),
.b (net087 ) );
bw_u1_nand2_2x I229_5_ (
.z (net0204[2] ),
.a (net0128 ),
.b (zbuf[4] ) );
bw_u1_inv_5x I269_6_ (
.z (zbuf[6] ),
.a (net0146[1] ) );
bw_u1_nand2_2x I230_3_ (
.z (net0221[4] ),
.a (net0246[4] ),
.b (net0204[4] ) );
bw_u1_nand2_2x I233_1_ (
.z (net0186[6] ),
.a (net0141 ),
.b (z[2] ) );
bw_u1_nand2_4x I235_5_ (
.z (net0247[2] ),
.a (net0213[2] ),
.b (net0186[2] ) );
bw_u1_nand2_2x I237_1_ (
.z (net0222[6] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I234_3_ (
.z (net0213[4] ),
.a (z[3] ),
.b (net088 ) );
bw_u1_nand2_4x I239_5_ (
.z (precnt[5] ),
.a (net0225[2] ),
.b (net0222[2] ) );
bw_u1_nand2_2x I238_3_ (
.z (net0225[4] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_4x I243_1_ (
.z (d[1] ),
.a (net0228[6] ),
.b (net0237[6] ) );
bw_u1_soffr_4x I171 (
.q (chose_z_n ),
.so (scan_data[0] ),
.ck (clk ),
.d (net195 ),
.se (se ),
.sd (scan_in ),
.r_l (net174 ) );
bw_u1_nand2_2x I241_5_ (
.z (net0237[2] ),
.a (net0154 ),
.b (zbuf[6] ) );
bw_u1_nand2_2x I242_7_ (
.z (net0228[0] ),
.a (zbuf[7] ),
.b (chose_z ) );
bw_u1_nand2_2x I247_1_ (
.z (net0198[6] ),
.a (from_csr[1] ),
.b (we_csr ) );
bw_u1_inv_2x I270 (
.z (net0140 ),
.a (updclk ) );
bw_u1_nand2_4x I246_7_ (
.z (z_post[7] ),
.a (net0198[0] ),
.b (net0201[0] ) );
bw_u1_nand2_2x I248_3_ (
.z (net0201[4] ),
.a (net0130 ),
.b (zbuf[3] ) );
bw_u1_inv_5x I271 (
.z (updclkbuf ),
.a (net0140 ) );
bw_u1_inv_8x I214_2_ (
.z (to_csr[2] ),
.a (net0146[5] ) );
bw_u1_inv_4x I215_4_ (
.z (net0146[3] ),
.a (z[4] ) );
bw_u1_nand2_4x I223_0_ (
.z (net0192[7] ),
.a (net0207[7] ),
.b (net0189[7] ) );
bw_u1_nand2_2x I224_2_ (
.z (net0207[5] ),
.a (mz[2] ),
.b (net0174 ) );
bw_u1_soffm2_4x I166_3_ (
.q (z[3] ),
.so (scan_data[3] ),
.ck (clk ),
.d0 (precnt[3] ),
.d1 (net0192[4] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[4] ) );
bw_u1_nand2_2x I228_2_ (
.z (net0246[5] ),
.a (net0247[5] ),
.b (net087 ) );
bw_u1_nand2_2x I265_5_ (
.z (net0209[2] ),
.a (net0221[2] ),
.b (net0145 ) );
bw_u1_nand2_2x I225_4_ (
.z (net0189[3] ),
.a (synced_upd_imped ),
.b (sz[4] ) );
bw_u1_nand2_2x I264_3_ (
.z (net0212[4] ),
.a (freeze ),
.b (zbuf[3] ) );
bw_u1_nand2_2x I229_4_ (
.z (net0204[3] ),
.a (net0128 ),
.b (zbuf[3] ) );
bw_u1_nand2_2x I266_7_ (
.z (mz[7] ),
.a (net0209[0] ),
.b (net0212[0] ) );
bw_u1_inv_5x I269_5_ (
.z (zbuf[5] ),
.a (net0146[2] ) );
bw_u1_nand2_2x I230_2_ (
.z (net0221[5] ),
.a (net0246[5] ),
.b (net0204[5] ) );
bw_u1_nand2_2x I234_2_ (
.z (net0213[5] ),
.a (z[2] ),
.b (net088 ) );
bw_u1_nand2_2x I233_0_ (
.z (net0186[7] ),
.a (net0141 ),
.b (z[1] ) );
bw_u1_nand2_4x I235_4_ (
.z (net0247[3] ),
.a (net0213[3] ),
.b (net0186[3] ) );
bw_u1_nand2_2x I238_2_ (
.z (net0225[5] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I237_0_ (
.z (net0222[7] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_4x I239_4_ (
.z (precnt[4] ),
.a (net0225[3] ),
.b (net0222[3] ) );
bw_u1_nand2_4x I243_0_ (
.z (d[0] ),
.a (net0228[7] ),
.b (net0237[7] ) );
bw_u1_nand2_2x I241_4_ (
.z (net0237[3] ),
.a (net0154 ),
.b (zbuf[5] ) );
bw_u1_nand2_2x I242_6_ (
.z (net0228[1] ),
.a (zbuf[6] ),
.b (chose_z ) );
bw_u1_nand2_4x I246_6_ (
.z (z_post[6] ),
.a (net0198[1] ),
.b (net0201[1] ) );
bw_u1_nand2_2x I248_2_ (
.z (net0201[5] ),
.a (net0130 ),
.b (zbuf[2] ) );
bw_u1_nand2_2x I247_0_ (
.z (net0198[7] ),
.a (from_csr[0] ),
.b (we_csr ) );
bw_u1_inv_8x I214_1_ (
.z (to_csr[1] ),
.a (net0146[6] ) );
bw_u1_inv_4x I215_3_ (
.z (net0146[4] ),
.a (z[3] ) );
bw_u1_soffm2_4x I166_2_ (
.q (z[2] ),
.so (scan_data[2] ),
.ck (clk ),
.d0 (precnt[2] ),
.d1 (net0192[5] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[3] ) );
bw_u1_nand2_2x I224_1_ (
.z (net0207[6] ),
.a (mz[1] ),
.b (net0174 ) );
bw_u1_nand2_2x I264_2_ (
.z (net0212[5] ),
.a (freeze ),
.b (zbuf[2] ) );
bw_u1_inv_10x I37 (
.z (chose_z ),
.a (chose_z_n ) );
bw_u1_nand2_4x I223_7_ (
.z (net0192[0] ),
.a (net0207[0] ),
.b (net0189[0] ) );
bw_u1_inv_4x I38 (
.z (chzn ),
.a (chose_z ) );
bw_u1_nand2_2x I228_1_ (
.z (net0246[6] ),
.a (net0247[6] ),
.b (net087 ) );
bw_u1_nand2_2x I265_4_ (
.z (net0209[3] ),
.a (net0221[3] ),
.b (net0145 ) );
bw_u1_nand2_2x I225_3_ (
.z (net0189[4] ),
.a (synced_upd_imped ),
.b (sz[3] ) );
bw_u1_nand2_2x I266_6_ (
.z (mz[6] ),
.a (net0209[1] ),
.b (net0212[1] ) );
bw_u1_nand2_2x I229_3_ (
.z (net0204[4] ),
.a (net0128 ),
.b (zbuf[2] ) );
bw_u1_inv_5x I269_4_ (
.z (zbuf[4] ),
.a (net0146[3] ) );
bw_u1_nand2_2x I230_1_ (
.z (net0221[6] ),
.a (net0246[6] ),
.b (net0204[6] ) );
bw_u1_nand2_2x I234_1_ (
.z (net0213[6] ),
.a (z[1] ),
.b (net088 ) );
bw_u1_nand2_4x I235_3_ (
.z (net0247[4] ),
.a (net0213[4] ),
.b (net0186[4] ) );
bw_u1_nand2_2x I238_1_ (
.z (net0225[6] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I233_7_ (
.z (net0186[0] ),
.a (net0141 ),
.b (config_pmos ) );
bw_u1_nand2_4x I239_3_ (
.z (precnt[3] ),
.a (net0225[4] ),
.b (net0222[4] ) );
bw_u1_nand2_2x I237_7_ (
.z (net0222[0] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I241_3_ (
.z (net0237[4] ),
.a (net0154 ),
.b (zbuf[4] ) );
bw_u1_nand2_2x I242_5_ (
.z (net0228[2] ),
.a (zbuf[5] ),
.b (chose_z ) );
bw_u1_nand2_4x I243_7_ (
.z (d[7] ),
.a (net0228[0] ),
.b (net0237[0] ) );
bw_u1_nand2_4x I246_5_ (
.z (z_post[5] ),
.a (net0198[2] ),
.b (net0201[2] ) );
bw_u1_nand2_2x I248_1_ (
.z (net0201[6] ),
.a (net0130 ),
.b (zbuf[1] ) );
bw_u1_nand2_2x I247_7_ (
.z (net0198[0] ),
.a (from_csr[7] ),
.b (we_csr ) );
bw_u1_nand3_4x I193 (
.z (net088 ),
.a (updclk ),
.b (chzn ),
.c (down_cond ) );
bw_u1_inv_5x I194 (
.z (net0141 ),
.a (net088 ) );
bw_u1_inv_4x I215_2_ (
.z (net0146[5] ),
.a (z[2] ) );
bw_u1_inv_8x I214_0_ (
.z (to_csr[0] ),
.a (net0146[7] ) );
bw_u1_inv_4x I196 (
.z (cofgp_n ),
.a (config_pmos ) );
bw_u1_inv_4x I197 (
.z (so_l ),
.a (scan_out ) );
bw_u1_nand2_4x I223_6_ (
.z (net0192[1] ),
.a (net0207[1] ),
.b (net0189[1] ) );
bw_u1_inv_4x I199 (
.z (scan_in ),
.a (si_l ) );
bw_u1_soffm2_4x I166_1_ (
.q (z[1] ),
.so (scan_data[1] ),
.ck (clk ),
.d0 (precnt[1] ),
.d1 (net0192[6] ),
.s (hard_reset_n ),
.se (se ),
.sd (scan_data[2] ) );
bw_u1_nand2_2x I224_0_ (
.z (net0207[7] ),
.a (mz[0] ),
.b (net0174 ) );
bw_u1_nand2_2x I225_2_ (
.z (net0189[5] ),
.a (synced_upd_imped ),
.b (sz[2] ) );
bw_u1_nand2_2x I264_1_ (
.z (net0212[6] ),
.a (freeze ),
.b (zbuf[1] ) );
bw_u1_nand2_2x I228_0_ (
.z (net0246[7] ),
.a (net0247[7] ),
.b (net087 ) );
bw_u1_nand2_2x I265_3_ (
.z (net0209[4] ),
.a (net0221[4] ),
.b (net0145 ) );
bw_u1_nand2_2x I229_2_ (
.z (net0204[5] ),
.a (net0128 ),
.b (zbuf[1] ) );
bw_u1_nand2_2x I266_5_ (
.z (mz[5] ),
.a (net0209[2] ),
.b (net0212[2] ) );
bw_u1_inv_5x I269_3_ (
.z (zbuf[3] ),
.a (net0146[4] ) );
bw_u1_nand2_2x I230_0_ (
.z (net0221[7] ),
.a (net0246[7] ),
.b (net0204[7] ) );
bw_u1_nand2_4x I235_2_ (
.z (net0247[5] ),
.a (net0213[5] ),
.b (net0186[5] ) );
bw_u1_nand2_2x I234_0_ (
.z (net0213[7] ),
.a (z[0] ),
.b (net088 ) );
bw_u1_nand2_2x I233_6_ (
.z (net0186[1] ),
.a (net0141 ),
.b (z[7] ) );
bw_u1_nand2_4x I239_2_ (
.z (precnt[2] ),
.a (net0225[5] ),
.b (net0222[5] ) );
bw_u1_nand2_2x I238_0_ (
.z (net0225[7] ),
.a (vss ),
.b (config_pmos ) );
bw_u1_nand2_2x I237_6_ (
.z (net0222[1] ),
.a (net0134 ),
.b (vss ) );
bw_u1_nand2_2x I241_2_ (
.z (net0237[5] ),
.a (net0154 ),
.b (zbuf[3] ) );
bw_u1_nand2_4x I243_6_ (
.z (d[6] ),
.a (net0228[1] ),
.b (net0237[1] ) );
bw_u1_nand2_2x I242_4_ (
.z (net0228[3] ),
.a (zbuf[4] ),
.b (chose_z ) );
bw_u1_nand2_4x I246_4_ (
.z (z_post[4] ),
.a (net0198[3] ),
.b (net0201[3] ) );
bw_u1_nand2_2x I248_0_ (
.z (net0201[7] ),
.a (net0130 ),
.b (zbuf[0] ) );
bw_u1_nand2_2x I247_6_ (
.z (net0198[1] ),
.a (from_csr[6] ),
.b (we_csr ) );
bw_u1_inv_4x I222 (
.z (net0174 ),
.a (synced_upd_imped ) );
bw_u1_inv_4x I215_1_ (
.z (net0146[6] ),
.a (z[1] ) );
bw_u1_inv_8x I214_7_ (
.z (to_csr[7] ),
.a (net0146[0] ) );
bw_u1_nor2_2x I127 (
.z (net94 ),
.a (synced_upd_imped ),
.b (net164 ) );
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module Altera_UP_Audio_Bit_Counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [4:0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//
// Copyright (c) 2001 Ed Schwartz ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Verify PR142 - Added something to print PASSED..
module testit;
reg clk;
reg [2:0] cnt;
always
begin
# 50 clk = ~clk;
end // always begin
task idle;
input [15:0] waitcnt;
begin: idletask
// begin
integer i;
for (i=0; i < waitcnt; i = i + 1)
begin
@ (posedge clk);
end // for (i=0; i < waitcnt; i = i + 1)
end
endtask // idle
initial begin
clk = 0;
cnt = 0;
$display ("One");
cnt = cnt + 1;
idle(3);
cnt = cnt + 1;
$display ("Two");
if(cnt === 2)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
reg SD_DMA_CLKMASKr = 1'b1;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 2'b11;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 2'b11;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_CLKMASKr ? 1'bZ : SD_CLKr[1];
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_CLKMASKr <= 1'b0;
end
else if (SD_DMA_DONEr) begin
SD_DMA_CLKMASKr <= 1'b1;
end
end
always @(posedge CLK) begin
if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1:
SD_DMA_NEXTADDRr <= 1'b0;
3'h2:
if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_case_huge_sub2 (/*AUTOARG*/
// Outputs
outa,
// Inputs
index
);
input [9:0] index;
output [9:0] outa;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [3:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [3:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {4{1'b0}};
assign cnt_one = cnt == {{3{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {4{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{3{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_ram.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "UNUSED",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 512,
// the_altsyncram.numwords_a = 512,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 9;
//
//synthesis read_comments_as_HDL off
endmodule
|
// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// per Widmer and Franaszek
module decode (datain, dispin, dataout, dispout, code_err, disp_err) ;
input [9:0] datain ;
input dispin ;
output [8:0] dataout ;
output dispout ;
output code_err ;
output disp_err ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire ii = datain[5] ;
wire fi = datain[6] ;
wire gi = datain[7] ;
wire hi = datain[8] ;
wire ji = datain[9] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire p22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire p13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire p31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
wire p40 = ai & bi & ci & di ;
wire p04 = !ai & !bi & !ci & !di ;
wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31.
wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits
wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits
wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
(ei & ii & di)) & (ei | ii | di)) ;
// The 5B/6B decoding special cases where ABCDE != abcde
wire p22bceeqi = p22 & bi & ci & (ei == ii) ;
wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ;
wire p13in = p13 & !ii ;
wire p31i = p31 & ii ;
wire p13dei = p13 & di & ei & ii ;
wire p22aceeqi = p22 & ai & ci & (ei == ii) ;
wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ;
wire p13en = p13 & !ei ;
wire anbnenin = !ai & !bi & !ei & !ii ;
wire abei = ai & bi & ei & ii ;
wire cdei = ci & di & ei & ii ;
wire cndnenin = !ci & !di & !ei & !ii ;
// non-zero disparity cases:
wire p22enin = p22 & !ei & !ii ;
wire p22ei = p22 & ei & ii ;
//wire p13in = p12 & !ii ;
//wire p31i = p31 & ii ;
wire p31dnenin = p31 & !di & !ei & !ii ;
//wire p13dei = p13 & di & ei & ii ;
wire p31e = p31 & ei ;
wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
p13en | abei | cndnenin ;
wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire ao = ai ^ compa ;
wire bo = bi ^ compb ;
wire co = ci ^ compc ;
wire do = di ^ compd ;
wire eo = ei ^ compe ;
wire feqg = (fi & gi) | (!fi & !gi) ;
wire heqj = (hi & ji) | (!hi & !ji) ;
wire fghj22 = (fi & gi & !hi & !ji) |
(!fi & !gi & hi & ji) |
( !feqg & !heqj) ;
wire fghjp13 = ( !feqg & !hi & !ji) |
( !heqj & !fi & !gi) ;
wire fghjp31 = ( (!feqg) & hi & ji) |
( !heqj & fi & gi) ;
wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
(p13 & !ei & ii & gi & hi & ji) |
(p31 & ei & !ii & !gi & !hi & !ji)) ;
wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1
((dispin & ci & di & !ei & !ii) | ko |
(dispin & !ci & di & !ei & !ii))) |
(!fi & gi & hi & // 0111 cases, where disp6b is 0
(( !dispin & !ci & !di & ei & ii) | ko |
( !dispin & ci & !di & ei & ii))) ;
wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ;
// k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
wire k28p = ! (ci | di | ei | ii) ;
wire fo = (ji & !fi & (hi | !gi | k28p)) |
(fi & !ji & (!hi | gi | !k28p)) |
(k28p & gi & hi) |
(!k28p & !gi & !hi) ;
wire go = (ji & !fi & (hi | !gi | !k28p)) |
(fi & !ji & (!hi | gi |k28p)) |
(!k28p & gi & hi) |
(k28p & !gi & !hi) ;
wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
(fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
(!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ;
wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ;
wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ;
wire disp4p = fghjp31 ;
wire disp4n = fghjp13 ;
assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
(p13 & !ei & !ii) | (p31 & ei & ii) |
(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
(ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
(!p31 & ei & !ii & !gi & !hi & !ji) |
(!p13 & !ei & ii & gi & hi & ji) |
(((ei & ii & !gi & !hi & !ji) |
(!ei & !ii & gi & hi & ji)) &
! ((ci & di & ei) | (!ci & !di & !ei))) |
(disp6p & disp4p) | (disp6n & disp4n) |
(ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
(!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
(fi & gi & !hi & !ji & disp6p) |
(!fi & !gi & hi & ji & disp6n) |
(ci & di & ei & ii & !fi & !gi & !hi) |
(!ci & !di & !ei & !ii & fi & gi & hi) ;
assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ;
// my disp err fires for any legal codes that violate disparity, may fire for illegal codes
assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
(dispin & !disp6n & fi & gi) |
(dispin & ai & bi & ci) |
(dispin & !disp6n & disp4p) |
(!dispin & !disp6p & !fi & !gi) |
(!dispin & !ai & !bi & !ci) |
(!dispin & !disp6p & disp4n) |
(disp6p & disp4p) | (disp6n & disp4n)) ;
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Wed Nov 28 10:34:57 EST 2012
//
//
// Ports:
// Name I/O size props
// wci_s_0_SResp O 2 const
// wci_s_0_SData O 32 const
// wci_s_0_SThreadBusy O 1 const
// wci_s_0_SFlag O 2 const
// wci_s_1_SResp O 2 const
// wci_s_1_SData O 32 const
// wci_s_1_SThreadBusy O 1 const
// wci_s_1_SFlag O 2 const
// wci_s_2_SResp O 2 reg
// wci_s_2_SData O 32 reg
// wci_s_2_SThreadBusy O 1
// wci_s_2_SFlag O 2
// wci_s_3_SResp O 2 reg
// wci_s_3_SData O 32 reg
// wci_s_3_SThreadBusy O 1
// wci_s_3_SFlag O 2
// wci_s_4_SResp O 2 reg
// wci_s_4_SData O 32 reg
// wci_s_4_SThreadBusy O 1
// wci_s_4_SFlag O 2
// wci_s_5_SResp O 2 const
// wci_s_5_SData O 32 const
// wci_s_5_SThreadBusy O 1 const
// wci_s_5_SFlag O 2 const
// wci_s_6_SResp O 2 const
// wci_s_6_SData O 32 const
// wci_s_6_SThreadBusy O 1 const
// wci_s_6_SFlag O 2 const
// wci_s_7_SResp O 2 const
// wci_s_7_SData O 32 const
// wci_s_7_SThreadBusy O 1 const
// wci_s_7_SFlag O 2 const
// wti_s_0_SThreadBusy O 1 const
// wti_s_0_SReset_n O 1 const
// wti_s_1_SThreadBusy O 1 const
// wti_s_1_SReset_n O 1 const
// wti_s_2_SThreadBusy O 1 const
// wti_s_2_SReset_n O 1 const
// wmiM0_MCmd O 3
// wmiM0_MReqLast O 1
// wmiM0_MReqInfo O 1
// wmiM0_MAddrSpace O 1
// wmiM0_MAddr O 14
// wmiM0_MBurstLength O 12
// wmiM0_MDataValid O 1
// wmiM0_MDataLast O 1
// wmiM0_MData O 32
// wmiM0_MDataByteEn O 4
// wmiM0_MFlag O 32
// wmiM0_MReset_n O 1
// wmiM1_MCmd O 3
// wmiM1_MReqLast O 1
// wmiM1_MReqInfo O 1
// wmiM1_MAddrSpace O 1
// wmiM1_MAddr O 14
// wmiM1_MBurstLength O 12
// wmiM1_MDataValid O 1
// wmiM1_MDataLast O 1
// wmiM1_MData O 32
// wmiM1_MDataByteEn O 4
// wmiM1_MFlag O 32
// wmiM1_MReset_n O 1
// wmemiM0_MCmd O 3 const
// wmemiM0_MReqLast O 1 const
// wmemiM0_MAddr O 36 const
// wmemiM0_MBurstLength O 12 const
// wmemiM0_MDataValid O 1 const
// wmemiM0_MDataLast O 1 const
// wmemiM0_MData O 128 const
// wmemiM0_MDataByteEn O 16 const
// wmemiM0_MReset_n O 1 const
// wsi_s_adc_SThreadBusy O 1
// wsi_s_adc_SReset_n O 1
// wsi_m_dac_MCmd O 3
// wsi_m_dac_MReqLast O 1
// wsi_m_dac_MBurstPrecise O 1
// wsi_m_dac_MBurstLength O 12
// wsi_m_dac_MData O 32 reg
// wsi_m_dac_MByteEn O 4 reg
// wsi_m_dac_MReqInfo O 8
// wsi_m_dac_MReset_n O 1
// uuid O 512 const
// RST_N_rst_0 I 1 unused
// RST_N_rst_1 I 1 unused
// RST_N_rst_2 I 1 reset
// RST_N_rst_3 I 1 reset
// RST_N_rst_4 I 1 reset
// RST_N_rst_5 I 1 unused
// RST_N_rst_6 I 1 unused
// RST_N_rst_7 I 1 unused
// CLK I 1 clock
// RST_N I 1 unused
// wci_s_0_MCmd I 3 unused
// wci_s_0_MAddrSpace I 1 unused
// wci_s_0_MByteEn I 4 unused
// wci_s_0_MAddr I 32 unused
// wci_s_0_MData I 32 unused
// wci_s_0_MFlag I 2 unused
// wci_s_1_MCmd I 3 unused
// wci_s_1_MAddrSpace I 1 unused
// wci_s_1_MByteEn I 4 unused
// wci_s_1_MAddr I 32 unused
// wci_s_1_MData I 32 unused
// wci_s_1_MFlag I 2 unused
// wci_s_2_MCmd I 3
// wci_s_2_MAddrSpace I 1
// wci_s_2_MByteEn I 4
// wci_s_2_MAddr I 32
// wci_s_2_MData I 32
// wci_s_2_MFlag I 2 unused
// wci_s_3_MCmd I 3
// wci_s_3_MAddrSpace I 1
// wci_s_3_MByteEn I 4
// wci_s_3_MAddr I 32
// wci_s_3_MData I 32
// wci_s_3_MFlag I 2 unused
// wci_s_4_MCmd I 3
// wci_s_4_MAddrSpace I 1
// wci_s_4_MByteEn I 4
// wci_s_4_MAddr I 32
// wci_s_4_MData I 32
// wci_s_4_MFlag I 2 unused
// wci_s_5_MCmd I 3 unused
// wci_s_5_MAddrSpace I 1 unused
// wci_s_5_MByteEn I 4 unused
// wci_s_5_MAddr I 32 unused
// wci_s_5_MData I 32 unused
// wci_s_5_MFlag I 2 unused
// wci_s_6_MCmd I 3 unused
// wci_s_6_MAddrSpace I 1 unused
// wci_s_6_MByteEn I 4 unused
// wci_s_6_MAddr I 32 unused
// wci_s_6_MData I 32 unused
// wci_s_6_MFlag I 2 unused
// wci_s_7_MCmd I 3 unused
// wci_s_7_MAddrSpace I 1 unused
// wci_s_7_MByteEn I 4 unused
// wci_s_7_MAddr I 32 unused
// wci_s_7_MData I 32 unused
// wci_s_7_MFlag I 2 unused
// wti_s_0_MCmd I 3 unused
// wti_s_0_MData I 64 unused
// wti_s_1_MCmd I 3 unused
// wti_s_1_MData I 64 unused
// wti_s_2_MCmd I 3 unused
// wti_s_2_MData I 64 unused
// wmiM0_SResp I 2
// wmiM0_SData I 32
// wmiM0_SFlag I 32 reg
// wmiM1_SResp I 2
// wmiM1_SData I 32
// wmiM1_SFlag I 32 reg
// wmemiM0_SResp I 2 unused
// wmemiM0_SData I 128 unused
// wsi_s_adc_MCmd I 3
// wsi_s_adc_MBurstLength I 12
// wsi_s_adc_MData I 32
// wsi_s_adc_MByteEn I 4
// wsi_s_adc_MReqInfo I 8
// wmiM0_SThreadBusy I 1 reg
// wmiM0_SDataThreadBusy I 1 reg
// wmiM0_SRespLast I 1 unused
// wmiM0_SReset_n I 1 reg
// wmiM1_SThreadBusy I 1 reg
// wmiM1_SDataThreadBusy I 1 reg
// wmiM1_SRespLast I 1 unused
// wmiM1_SReset_n I 1 reg
// wmemiM0_SRespLast I 1 unused
// wmemiM0_SCmdAccept I 1 unused
// wmemiM0_SDataAccept I 1 unused
// wsi_s_adc_MReqLast I 1
// wsi_s_adc_MBurstPrecise I 1
// wsi_s_adc_MReset_n I 1 reg
// wsi_m_dac_SThreadBusy I 1 reg
// wsi_m_dac_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkOCApp4B(RST_N_rst_0,
RST_N_rst_1,
RST_N_rst_2,
RST_N_rst_3,
RST_N_rst_4,
RST_N_rst_5,
RST_N_rst_6,
RST_N_rst_7,
CLK,
RST_N,
wci_s_0_MCmd,
wci_s_0_MAddrSpace,
wci_s_0_MByteEn,
wci_s_0_MAddr,
wci_s_0_MData,
wci_s_0_SResp,
wci_s_0_SData,
wci_s_0_SThreadBusy,
wci_s_0_SFlag,
wci_s_0_MFlag,
wci_s_1_MCmd,
wci_s_1_MAddrSpace,
wci_s_1_MByteEn,
wci_s_1_MAddr,
wci_s_1_MData,
wci_s_1_SResp,
wci_s_1_SData,
wci_s_1_SThreadBusy,
wci_s_1_SFlag,
wci_s_1_MFlag,
wci_s_2_MCmd,
wci_s_2_MAddrSpace,
wci_s_2_MByteEn,
wci_s_2_MAddr,
wci_s_2_MData,
wci_s_2_SResp,
wci_s_2_SData,
wci_s_2_SThreadBusy,
wci_s_2_SFlag,
wci_s_2_MFlag,
wci_s_3_MCmd,
wci_s_3_MAddrSpace,
wci_s_3_MByteEn,
wci_s_3_MAddr,
wci_s_3_MData,
wci_s_3_SResp,
wci_s_3_SData,
wci_s_3_SThreadBusy,
wci_s_3_SFlag,
wci_s_3_MFlag,
wci_s_4_MCmd,
wci_s_4_MAddrSpace,
wci_s_4_MByteEn,
wci_s_4_MAddr,
wci_s_4_MData,
wci_s_4_SResp,
wci_s_4_SData,
wci_s_4_SThreadBusy,
wci_s_4_SFlag,
wci_s_4_MFlag,
wci_s_5_MCmd,
wci_s_5_MAddrSpace,
wci_s_5_MByteEn,
wci_s_5_MAddr,
wci_s_5_MData,
wci_s_5_SResp,
wci_s_5_SData,
wci_s_5_SThreadBusy,
wci_s_5_SFlag,
wci_s_5_MFlag,
wci_s_6_MCmd,
wci_s_6_MAddrSpace,
wci_s_6_MByteEn,
wci_s_6_MAddr,
wci_s_6_MData,
wci_s_6_SResp,
wci_s_6_SData,
wci_s_6_SThreadBusy,
wci_s_6_SFlag,
wci_s_6_MFlag,
wci_s_7_MCmd,
wci_s_7_MAddrSpace,
wci_s_7_MByteEn,
wci_s_7_MAddr,
wci_s_7_MData,
wci_s_7_SResp,
wci_s_7_SData,
wci_s_7_SThreadBusy,
wci_s_7_SFlag,
wci_s_7_MFlag,
wti_s_0_MCmd,
wti_s_0_MData,
wti_s_0_SThreadBusy,
wti_s_0_SReset_n,
wti_s_1_MCmd,
wti_s_1_MData,
wti_s_1_SThreadBusy,
wti_s_1_SReset_n,
wti_s_2_MCmd,
wti_s_2_MData,
wti_s_2_SThreadBusy,
wti_s_2_SReset_n,
wmiM0_MCmd,
wmiM0_MReqLast,
wmiM0_MReqInfo,
wmiM0_MAddrSpace,
wmiM0_MAddr,
wmiM0_MBurstLength,
wmiM0_MDataValid,
wmiM0_MDataLast,
wmiM0_MData,
wmiM0_MDataByteEn,
wmiM0_SResp,
wmiM0_SData,
wmiM0_SThreadBusy,
wmiM0_SDataThreadBusy,
wmiM0_SRespLast,
wmiM0_SFlag,
wmiM0_MFlag,
wmiM0_MReset_n,
wmiM0_SReset_n,
wmiM1_MCmd,
wmiM1_MReqLast,
wmiM1_MReqInfo,
wmiM1_MAddrSpace,
wmiM1_MAddr,
wmiM1_MBurstLength,
wmiM1_MDataValid,
wmiM1_MDataLast,
wmiM1_MData,
wmiM1_MDataByteEn,
wmiM1_SResp,
wmiM1_SData,
wmiM1_SThreadBusy,
wmiM1_SDataThreadBusy,
wmiM1_SRespLast,
wmiM1_SFlag,
wmiM1_MFlag,
wmiM1_MReset_n,
wmiM1_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n,
wsi_s_adc_MCmd,
wsi_s_adc_MReqLast,
wsi_s_adc_MBurstPrecise,
wsi_s_adc_MBurstLength,
wsi_s_adc_MData,
wsi_s_adc_MByteEn,
wsi_s_adc_MReqInfo,
wsi_s_adc_SThreadBusy,
wsi_s_adc_SReset_n,
wsi_s_adc_MReset_n,
wsi_m_dac_MCmd,
wsi_m_dac_MReqLast,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MBurstLength,
wsi_m_dac_MData,
wsi_m_dac_MByteEn,
wsi_m_dac_MReqInfo,
wsi_m_dac_SThreadBusy,
wsi_m_dac_MReset_n,
wsi_m_dac_SReset_n,
uuid);
parameter [0 : 0] hasDebugLogic = 1'b0;
input RST_N_rst_0;
input RST_N_rst_1;
input RST_N_rst_2;
input RST_N_rst_3;
input RST_N_rst_4;
input RST_N_rst_5;
input RST_N_rst_6;
input RST_N_rst_7;
input CLK;
input RST_N;
// action method wci_s_0_mCmd
input [2 : 0] wci_s_0_MCmd;
// action method wci_s_0_mAddrSpace
input wci_s_0_MAddrSpace;
// action method wci_s_0_mByteEn
input [3 : 0] wci_s_0_MByteEn;
// action method wci_s_0_mAddr
input [31 : 0] wci_s_0_MAddr;
// action method wci_s_0_mData
input [31 : 0] wci_s_0_MData;
// value method wci_s_0_sResp
output [1 : 0] wci_s_0_SResp;
// value method wci_s_0_sData
output [31 : 0] wci_s_0_SData;
// value method wci_s_0_sThreadBusy
output wci_s_0_SThreadBusy;
// value method wci_s_0_sFlag
output [1 : 0] wci_s_0_SFlag;
// action method wci_s_0_mFlag
input [1 : 0] wci_s_0_MFlag;
// action method wci_s_1_mCmd
input [2 : 0] wci_s_1_MCmd;
// action method wci_s_1_mAddrSpace
input wci_s_1_MAddrSpace;
// action method wci_s_1_mByteEn
input [3 : 0] wci_s_1_MByteEn;
// action method wci_s_1_mAddr
input [31 : 0] wci_s_1_MAddr;
// action method wci_s_1_mData
input [31 : 0] wci_s_1_MData;
// value method wci_s_1_sResp
output [1 : 0] wci_s_1_SResp;
// value method wci_s_1_sData
output [31 : 0] wci_s_1_SData;
// value method wci_s_1_sThreadBusy
output wci_s_1_SThreadBusy;
// value method wci_s_1_sFlag
output [1 : 0] wci_s_1_SFlag;
// action method wci_s_1_mFlag
input [1 : 0] wci_s_1_MFlag;
// action method wci_s_2_mCmd
input [2 : 0] wci_s_2_MCmd;
// action method wci_s_2_mAddrSpace
input wci_s_2_MAddrSpace;
// action method wci_s_2_mByteEn
input [3 : 0] wci_s_2_MByteEn;
// action method wci_s_2_mAddr
input [31 : 0] wci_s_2_MAddr;
// action method wci_s_2_mData
input [31 : 0] wci_s_2_MData;
// value method wci_s_2_sResp
output [1 : 0] wci_s_2_SResp;
// value method wci_s_2_sData
output [31 : 0] wci_s_2_SData;
// value method wci_s_2_sThreadBusy
output wci_s_2_SThreadBusy;
// value method wci_s_2_sFlag
output [1 : 0] wci_s_2_SFlag;
// action method wci_s_2_mFlag
input [1 : 0] wci_s_2_MFlag;
// action method wci_s_3_mCmd
input [2 : 0] wci_s_3_MCmd;
// action method wci_s_3_mAddrSpace
input wci_s_3_MAddrSpace;
// action method wci_s_3_mByteEn
input [3 : 0] wci_s_3_MByteEn;
// action method wci_s_3_mAddr
input [31 : 0] wci_s_3_MAddr;
// action method wci_s_3_mData
input [31 : 0] wci_s_3_MData;
// value method wci_s_3_sResp
output [1 : 0] wci_s_3_SResp;
// value method wci_s_3_sData
output [31 : 0] wci_s_3_SData;
// value method wci_s_3_sThreadBusy
output wci_s_3_SThreadBusy;
// value method wci_s_3_sFlag
output [1 : 0] wci_s_3_SFlag;
// action method wci_s_3_mFlag
input [1 : 0] wci_s_3_MFlag;
// action method wci_s_4_mCmd
input [2 : 0] wci_s_4_MCmd;
// action method wci_s_4_mAddrSpace
input wci_s_4_MAddrSpace;
// action method wci_s_4_mByteEn
input [3 : 0] wci_s_4_MByteEn;
// action method wci_s_4_mAddr
input [31 : 0] wci_s_4_MAddr;
// action method wci_s_4_mData
input [31 : 0] wci_s_4_MData;
// value method wci_s_4_sResp
output [1 : 0] wci_s_4_SResp;
// value method wci_s_4_sData
output [31 : 0] wci_s_4_SData;
// value method wci_s_4_sThreadBusy
output wci_s_4_SThreadBusy;
// value method wci_s_4_sFlag
output [1 : 0] wci_s_4_SFlag;
// action method wci_s_4_mFlag
input [1 : 0] wci_s_4_MFlag;
// action method wci_s_5_mCmd
input [2 : 0] wci_s_5_MCmd;
// action method wci_s_5_mAddrSpace
input wci_s_5_MAddrSpace;
// action method wci_s_5_mByteEn
input [3 : 0] wci_s_5_MByteEn;
// action method wci_s_5_mAddr
input [31 : 0] wci_s_5_MAddr;
// action method wci_s_5_mData
input [31 : 0] wci_s_5_MData;
// value method wci_s_5_sResp
output [1 : 0] wci_s_5_SResp;
// value method wci_s_5_sData
output [31 : 0] wci_s_5_SData;
// value method wci_s_5_sThreadBusy
output wci_s_5_SThreadBusy;
// value method wci_s_5_sFlag
output [1 : 0] wci_s_5_SFlag;
// action method wci_s_5_mFlag
input [1 : 0] wci_s_5_MFlag;
// action method wci_s_6_mCmd
input [2 : 0] wci_s_6_MCmd;
// action method wci_s_6_mAddrSpace
input wci_s_6_MAddrSpace;
// action method wci_s_6_mByteEn
input [3 : 0] wci_s_6_MByteEn;
// action method wci_s_6_mAddr
input [31 : 0] wci_s_6_MAddr;
// action method wci_s_6_mData
input [31 : 0] wci_s_6_MData;
// value method wci_s_6_sResp
output [1 : 0] wci_s_6_SResp;
// value method wci_s_6_sData
output [31 : 0] wci_s_6_SData;
// value method wci_s_6_sThreadBusy
output wci_s_6_SThreadBusy;
// value method wci_s_6_sFlag
output [1 : 0] wci_s_6_SFlag;
// action method wci_s_6_mFlag
input [1 : 0] wci_s_6_MFlag;
// action method wci_s_7_mCmd
input [2 : 0] wci_s_7_MCmd;
// action method wci_s_7_mAddrSpace
input wci_s_7_MAddrSpace;
// action method wci_s_7_mByteEn
input [3 : 0] wci_s_7_MByteEn;
// action method wci_s_7_mAddr
input [31 : 0] wci_s_7_MAddr;
// action method wci_s_7_mData
input [31 : 0] wci_s_7_MData;
// value method wci_s_7_sResp
output [1 : 0] wci_s_7_SResp;
// value method wci_s_7_sData
output [31 : 0] wci_s_7_SData;
// value method wci_s_7_sThreadBusy
output wci_s_7_SThreadBusy;
// value method wci_s_7_sFlag
output [1 : 0] wci_s_7_SFlag;
// action method wci_s_7_mFlag
input [1 : 0] wci_s_7_MFlag;
// action method wti_s_0_mCmd
input [2 : 0] wti_s_0_MCmd;
// action method wti_s_0_mData
input [63 : 0] wti_s_0_MData;
// value method wti_s_0_sThreadBusy
output wti_s_0_SThreadBusy;
// value method wti_s_0_sReset_n
output wti_s_0_SReset_n;
// action method wti_s_1_mCmd
input [2 : 0] wti_s_1_MCmd;
// action method wti_s_1_mData
input [63 : 0] wti_s_1_MData;
// value method wti_s_1_sThreadBusy
output wti_s_1_SThreadBusy;
// value method wti_s_1_sReset_n
output wti_s_1_SReset_n;
// action method wti_s_2_mCmd
input [2 : 0] wti_s_2_MCmd;
// action method wti_s_2_mData
input [63 : 0] wti_s_2_MData;
// value method wti_s_2_sThreadBusy
output wti_s_2_SThreadBusy;
// value method wti_s_2_sReset_n
output wti_s_2_SReset_n;
// value method wmiM0_mCmd
output [2 : 0] wmiM0_MCmd;
// value method wmiM0_mReqLast
output wmiM0_MReqLast;
// value method wmiM0_mReqInfo
output wmiM0_MReqInfo;
// value method wmiM0_mAddrSpace
output wmiM0_MAddrSpace;
// value method wmiM0_mAddr
output [13 : 0] wmiM0_MAddr;
// value method wmiM0_mBurstLength
output [11 : 0] wmiM0_MBurstLength;
// value method wmiM0_mDataValid
output wmiM0_MDataValid;
// value method wmiM0_mDataLast
output wmiM0_MDataLast;
// value method wmiM0_mData
output [31 : 0] wmiM0_MData;
// value method wmiM0_mDataInfo
// value method wmiM0_mDataByteEn
output [3 : 0] wmiM0_MDataByteEn;
// action method wmiM0_sResp
input [1 : 0] wmiM0_SResp;
// action method wmiM0_sData
input [31 : 0] wmiM0_SData;
// action method wmiM0_sThreadBusy
input wmiM0_SThreadBusy;
// action method wmiM0_sDataThreadBusy
input wmiM0_SDataThreadBusy;
// action method wmiM0_sRespLast
input wmiM0_SRespLast;
// action method wmiM0_sFlag
input [31 : 0] wmiM0_SFlag;
// value method wmiM0_mFlag
output [31 : 0] wmiM0_MFlag;
// value method wmiM0_mReset_n
output wmiM0_MReset_n;
// action method wmiM0_sReset_n
input wmiM0_SReset_n;
// value method wmiM1_mCmd
output [2 : 0] wmiM1_MCmd;
// value method wmiM1_mReqLast
output wmiM1_MReqLast;
// value method wmiM1_mReqInfo
output wmiM1_MReqInfo;
// value method wmiM1_mAddrSpace
output wmiM1_MAddrSpace;
// value method wmiM1_mAddr
output [13 : 0] wmiM1_MAddr;
// value method wmiM1_mBurstLength
output [11 : 0] wmiM1_MBurstLength;
// value method wmiM1_mDataValid
output wmiM1_MDataValid;
// value method wmiM1_mDataLast
output wmiM1_MDataLast;
// value method wmiM1_mData
output [31 : 0] wmiM1_MData;
// value method wmiM1_mDataInfo
// value method wmiM1_mDataByteEn
output [3 : 0] wmiM1_MDataByteEn;
// action method wmiM1_sResp
input [1 : 0] wmiM1_SResp;
// action method wmiM1_sData
input [31 : 0] wmiM1_SData;
// action method wmiM1_sThreadBusy
input wmiM1_SThreadBusy;
// action method wmiM1_sDataThreadBusy
input wmiM1_SDataThreadBusy;
// action method wmiM1_sRespLast
input wmiM1_SRespLast;
// action method wmiM1_sFlag
input [31 : 0] wmiM1_SFlag;
// value method wmiM1_mFlag
output [31 : 0] wmiM1_MFlag;
// value method wmiM1_mReset_n
output wmiM1_MReset_n;
// action method wmiM1_sReset_n
input wmiM1_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// action method wsi_s_adc_mCmd
input [2 : 0] wsi_s_adc_MCmd;
// action method wsi_s_adc_mReqLast
input wsi_s_adc_MReqLast;
// action method wsi_s_adc_mBurstPrecise
input wsi_s_adc_MBurstPrecise;
// action method wsi_s_adc_mBurstLength
input [11 : 0] wsi_s_adc_MBurstLength;
// action method wsi_s_adc_mData
input [31 : 0] wsi_s_adc_MData;
// action method wsi_s_adc_mByteEn
input [3 : 0] wsi_s_adc_MByteEn;
// action method wsi_s_adc_mReqInfo
input [7 : 0] wsi_s_adc_MReqInfo;
// action method wsi_s_adc_mDataInfo
// value method wsi_s_adc_sThreadBusy
output wsi_s_adc_SThreadBusy;
// value method wsi_s_adc_sReset_n
output wsi_s_adc_SReset_n;
// action method wsi_s_adc_mReset_n
input wsi_s_adc_MReset_n;
// value method wsi_m_dac_mCmd
output [2 : 0] wsi_m_dac_MCmd;
// value method wsi_m_dac_mReqLast
output wsi_m_dac_MReqLast;
// value method wsi_m_dac_mBurstPrecise
output wsi_m_dac_MBurstPrecise;
// value method wsi_m_dac_mBurstLength
output [11 : 0] wsi_m_dac_MBurstLength;
// value method wsi_m_dac_mData
output [31 : 0] wsi_m_dac_MData;
// value method wsi_m_dac_mByteEn
output [3 : 0] wsi_m_dac_MByteEn;
// value method wsi_m_dac_mReqInfo
output [7 : 0] wsi_m_dac_MReqInfo;
// value method wsi_m_dac_mDataInfo
// action method wsi_m_dac_sThreadBusy
input wsi_m_dac_SThreadBusy;
// value method wsi_m_dac_mReset_n
output wsi_m_dac_MReset_n;
// action method wsi_m_dac_sReset_n
input wsi_m_dac_SReset_n;
// value method uuid
output [511 : 0] uuid;
// signals for module outputs
wire [511 : 0] uuid;
wire [127 : 0] wmemiM0_MData;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wci_s_0_SData,
wci_s_1_SData,
wci_s_2_SData,
wci_s_3_SData,
wci_s_4_SData,
wci_s_5_SData,
wci_s_6_SData,
wci_s_7_SData,
wmiM0_MData,
wmiM0_MFlag,
wmiM1_MData,
wmiM1_MFlag,
wsi_m_dac_MData;
wire [15 : 0] wmemiM0_MDataByteEn;
wire [13 : 0] wmiM0_MAddr, wmiM1_MAddr;
wire [11 : 0] wmemiM0_MBurstLength,
wmiM0_MBurstLength,
wmiM1_MBurstLength,
wsi_m_dac_MBurstLength;
wire [7 : 0] wsi_m_dac_MReqInfo;
wire [3 : 0] wmiM0_MDataByteEn, wmiM1_MDataByteEn, wsi_m_dac_MByteEn;
wire [2 : 0] wmemiM0_MCmd, wmiM0_MCmd, wmiM1_MCmd, wsi_m_dac_MCmd;
wire [1 : 0] wci_s_0_SFlag,
wci_s_0_SResp,
wci_s_1_SFlag,
wci_s_1_SResp,
wci_s_2_SFlag,
wci_s_2_SResp,
wci_s_3_SFlag,
wci_s_3_SResp,
wci_s_4_SFlag,
wci_s_4_SResp,
wci_s_5_SFlag,
wci_s_5_SResp,
wci_s_6_SFlag,
wci_s_6_SResp,
wci_s_7_SFlag,
wci_s_7_SResp;
wire wci_s_0_SThreadBusy,
wci_s_1_SThreadBusy,
wci_s_2_SThreadBusy,
wci_s_3_SThreadBusy,
wci_s_4_SThreadBusy,
wci_s_5_SThreadBusy,
wci_s_6_SThreadBusy,
wci_s_7_SThreadBusy,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wmiM0_MAddrSpace,
wmiM0_MDataLast,
wmiM0_MDataValid,
wmiM0_MReqInfo,
wmiM0_MReqLast,
wmiM0_MReset_n,
wmiM1_MAddrSpace,
wmiM1_MDataLast,
wmiM1_MDataValid,
wmiM1_MReqInfo,
wmiM1_MReqLast,
wmiM1_MReset_n,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MReqLast,
wsi_m_dac_MReset_n,
wsi_s_adc_SReset_n,
wsi_s_adc_SThreadBusy,
wti_s_0_SReset_n,
wti_s_0_SThreadBusy,
wti_s_1_SReset_n,
wti_s_1_SThreadBusy,
wti_s_2_SReset_n,
wti_s_2_SThreadBusy;
// inlined wires
wire [31 : 0] tieOff0_wci_Es_mAddr_w$wget,
tieOff0_wci_Es_mData_w$wget,
tieOff1_wci_Es_mAddr_w$wget,
tieOff1_wci_Es_mData_w$wget,
tieOff5_wci_Es_mAddr_w$wget,
tieOff5_wci_Es_mData_w$wget,
tieOff6_wci_Es_mAddr_w$wget,
tieOff6_wci_Es_mData_w$wget,
tieOff7_wci_Es_mAddr_w$wget,
tieOff7_wci_Es_mData_w$wget;
wire [3 : 0] tieOff0_wci_Es_mByteEn_w$wget,
tieOff1_wci_Es_mByteEn_w$wget,
tieOff5_wci_Es_mByteEn_w$wget,
tieOff6_wci_Es_mByteEn_w$wget,
tieOff7_wci_Es_mByteEn_w$wget;
wire [2 : 0] tieOff0_wci_Es_mCmd_w$wget,
tieOff1_wci_Es_mCmd_w$wget,
tieOff5_wci_Es_mCmd_w$wget,
tieOff6_wci_Es_mCmd_w$wget,
tieOff7_wci_Es_mCmd_w$wget;
wire tieOff0_wci_Es_mAddrSpace_w$wget,
tieOff0_wci_Es_mAddrSpace_w$whas,
tieOff0_wci_Es_mAddr_w$whas,
tieOff0_wci_Es_mByteEn_w$whas,
tieOff0_wci_Es_mCmd_w$whas,
tieOff0_wci_Es_mData_w$whas,
tieOff1_wci_Es_mAddrSpace_w$wget,
tieOff1_wci_Es_mAddrSpace_w$whas,
tieOff1_wci_Es_mAddr_w$whas,
tieOff1_wci_Es_mByteEn_w$whas,
tieOff1_wci_Es_mCmd_w$whas,
tieOff1_wci_Es_mData_w$whas,
tieOff5_wci_Es_mAddrSpace_w$wget,
tieOff5_wci_Es_mAddrSpace_w$whas,
tieOff5_wci_Es_mAddr_w$whas,
tieOff5_wci_Es_mByteEn_w$whas,
tieOff5_wci_Es_mCmd_w$whas,
tieOff5_wci_Es_mData_w$whas,
tieOff6_wci_Es_mAddrSpace_w$wget,
tieOff6_wci_Es_mAddrSpace_w$whas,
tieOff6_wci_Es_mAddr_w$whas,
tieOff6_wci_Es_mByteEn_w$whas,
tieOff6_wci_Es_mCmd_w$whas,
tieOff6_wci_Es_mData_w$whas,
tieOff7_wci_Es_mAddrSpace_w$wget,
tieOff7_wci_Es_mAddrSpace_w$whas,
tieOff7_wci_Es_mAddr_w$whas,
tieOff7_wci_Es_mByteEn_w$whas,
tieOff7_wci_Es_mCmd_w$whas,
tieOff7_wci_Es_mData_w$whas;
// ports of submodule appW2
wire [31 : 0] appW2$wciS0_MAddr,
appW2$wciS0_MData,
appW2$wciS0_SData,
appW2$wmiM0_MData,
appW2$wmiM0_MFlag,
appW2$wmiM0_SData,
appW2$wmiM0_SFlag,
appW2$wsiM0_MData,
appW2$wsiS0_MData;
wire [13 : 0] appW2$wmiM0_MAddr;
wire [11 : 0] appW2$wmiM0_MBurstLength,
appW2$wsiM0_MBurstLength,
appW2$wsiS0_MBurstLength;
wire [7 : 0] appW2$wsiM0_MReqInfo, appW2$wsiS0_MReqInfo;
wire [3 : 0] appW2$wciS0_MByteEn,
appW2$wmiM0_MDataByteEn,
appW2$wsiM0_MByteEn,
appW2$wsiS0_MByteEn;
wire [2 : 0] appW2$wciS0_MCmd,
appW2$wmiM0_MCmd,
appW2$wsiM0_MCmd,
appW2$wsiS0_MCmd;
wire [1 : 0] appW2$wciS0_MFlag,
appW2$wciS0_SFlag,
appW2$wciS0_SResp,
appW2$wmiM0_SResp;
wire appW2$wciS0_MAddrSpace,
appW2$wciS0_SThreadBusy,
appW2$wmiM0_MAddrSpace,
appW2$wmiM0_MDataLast,
appW2$wmiM0_MDataValid,
appW2$wmiM0_MReqInfo,
appW2$wmiM0_MReqLast,
appW2$wmiM0_MReset_n,
appW2$wmiM0_SDataThreadBusy,
appW2$wmiM0_SReset_n,
appW2$wmiM0_SRespLast,
appW2$wmiM0_SThreadBusy,
appW2$wsiM0_MBurstPrecise,
appW2$wsiM0_MReqLast,
appW2$wsiM0_MReset_n,
appW2$wsiM0_SReset_n,
appW2$wsiM0_SThreadBusy,
appW2$wsiS0_MBurstPrecise,
appW2$wsiS0_MReqLast,
appW2$wsiS0_MReset_n,
appW2$wsiS0_SReset_n,
appW2$wsiS0_SThreadBusy;
// ports of submodule appW3
wire [31 : 0] appW3$wciS0_MAddr,
appW3$wciS0_MData,
appW3$wciS0_SData,
appW3$wsiM0_MData,
appW3$wsiS0_MData;
wire [11 : 0] appW3$wsiM0_MBurstLength, appW3$wsiS0_MBurstLength;
wire [7 : 0] appW3$wsiM0_MReqInfo, appW3$wsiS0_MReqInfo;
wire [3 : 0] appW3$wciS0_MByteEn, appW3$wsiM0_MByteEn, appW3$wsiS0_MByteEn;
wire [2 : 0] appW3$wciS0_MCmd, appW3$wsiM0_MCmd, appW3$wsiS0_MCmd;
wire [1 : 0] appW3$wciS0_MFlag, appW3$wciS0_SFlag, appW3$wciS0_SResp;
wire appW3$wciS0_MAddrSpace,
appW3$wciS0_SThreadBusy,
appW3$wsiM0_MBurstPrecise,
appW3$wsiM0_MReqLast,
appW3$wsiM0_MReset_n,
appW3$wsiM0_SReset_n,
appW3$wsiM0_SThreadBusy,
appW3$wsiS0_MBurstPrecise,
appW3$wsiS0_MReqLast,
appW3$wsiS0_MReset_n,
appW3$wsiS0_SReset_n,
appW3$wsiS0_SThreadBusy;
// ports of submodule appW4
wire [31 : 0] appW4$wciS0_MAddr,
appW4$wciS0_MData,
appW4$wciS0_SData,
appW4$wmiM0_MData,
appW4$wmiM0_MFlag,
appW4$wmiM0_SData,
appW4$wmiM0_SFlag,
appW4$wsiM0_MData,
appW4$wsiS0_MData;
wire [13 : 0] appW4$wmiM0_MAddr;
wire [11 : 0] appW4$wmiM0_MBurstLength,
appW4$wsiM0_MBurstLength,
appW4$wsiS0_MBurstLength;
wire [7 : 0] appW4$wsiM0_MReqInfo, appW4$wsiS0_MReqInfo;
wire [3 : 0] appW4$wciS0_MByteEn,
appW4$wmiM0_MDataByteEn,
appW4$wsiM0_MByteEn,
appW4$wsiS0_MByteEn;
wire [2 : 0] appW4$wciS0_MCmd,
appW4$wmiM0_MCmd,
appW4$wsiM0_MCmd,
appW4$wsiS0_MCmd;
wire [1 : 0] appW4$wciS0_MFlag,
appW4$wciS0_SFlag,
appW4$wciS0_SResp,
appW4$wmiM0_SResp;
wire appW4$wciS0_MAddrSpace,
appW4$wciS0_SThreadBusy,
appW4$wmiM0_MAddrSpace,
appW4$wmiM0_MDataLast,
appW4$wmiM0_MDataValid,
appW4$wmiM0_MReqInfo,
appW4$wmiM0_MReqLast,
appW4$wmiM0_MReset_n,
appW4$wmiM0_SDataThreadBusy,
appW4$wmiM0_SReset_n,
appW4$wmiM0_SRespLast,
appW4$wmiM0_SThreadBusy,
appW4$wsiM0_MBurstPrecise,
appW4$wsiM0_MReqLast,
appW4$wsiM0_MReset_n,
appW4$wsiM0_SReset_n,
appW4$wsiM0_SThreadBusy,
appW4$wsiS0_MBurstPrecise,
appW4$wsiS0_MReqLast,
appW4$wsiS0_MReset_n,
appW4$wsiS0_SReset_n,
appW4$wsiS0_SThreadBusy;
// ports of submodule id
wire [511 : 0] id$uuid;
// value method wci_s_0_sResp
assign wci_s_0_SResp = 2'd0 ;
// value method wci_s_0_sData
assign wci_s_0_SData = 32'hAAAAAAAA ;
// value method wci_s_0_sThreadBusy
assign wci_s_0_SThreadBusy = 1'd1 ;
// value method wci_s_0_sFlag
assign wci_s_0_SFlag = 2'b0 ;
// value method wci_s_1_sResp
assign wci_s_1_SResp = 2'd0 ;
// value method wci_s_1_sData
assign wci_s_1_SData = 32'hAAAAAAAA ;
// value method wci_s_1_sThreadBusy
assign wci_s_1_SThreadBusy = 1'd1 ;
// value method wci_s_1_sFlag
assign wci_s_1_SFlag = 2'b0 ;
// value method wci_s_2_sResp
assign wci_s_2_SResp = appW2$wciS0_SResp ;
// value method wci_s_2_sData
assign wci_s_2_SData = appW2$wciS0_SData ;
// value method wci_s_2_sThreadBusy
assign wci_s_2_SThreadBusy = appW2$wciS0_SThreadBusy ;
// value method wci_s_2_sFlag
assign wci_s_2_SFlag = appW2$wciS0_SFlag ;
// value method wci_s_3_sResp
assign wci_s_3_SResp = appW3$wciS0_SResp ;
// value method wci_s_3_sData
assign wci_s_3_SData = appW3$wciS0_SData ;
// value method wci_s_3_sThreadBusy
assign wci_s_3_SThreadBusy = appW3$wciS0_SThreadBusy ;
// value method wci_s_3_sFlag
assign wci_s_3_SFlag = appW3$wciS0_SFlag ;
// value method wci_s_4_sResp
assign wci_s_4_SResp = appW4$wciS0_SResp ;
// value method wci_s_4_sData
assign wci_s_4_SData = appW4$wciS0_SData ;
// value method wci_s_4_sThreadBusy
assign wci_s_4_SThreadBusy = appW4$wciS0_SThreadBusy ;
// value method wci_s_4_sFlag
assign wci_s_4_SFlag = appW4$wciS0_SFlag ;
// value method wci_s_5_sResp
assign wci_s_5_SResp = 2'd0 ;
// value method wci_s_5_sData
assign wci_s_5_SData = 32'hAAAAAAAA ;
// value method wci_s_5_sThreadBusy
assign wci_s_5_SThreadBusy = 1'd1 ;
// value method wci_s_5_sFlag
assign wci_s_5_SFlag = 2'b0 ;
// value method wci_s_6_sResp
assign wci_s_6_SResp = 2'd0 ;
// value method wci_s_6_sData
assign wci_s_6_SData = 32'hAAAAAAAA ;
// value method wci_s_6_sThreadBusy
assign wci_s_6_SThreadBusy = 1'd1 ;
// value method wci_s_6_sFlag
assign wci_s_6_SFlag = 2'b0 ;
// value method wci_s_7_sResp
assign wci_s_7_SResp = 2'd0 ;
// value method wci_s_7_sData
assign wci_s_7_SData = 32'hAAAAAAAA ;
// value method wci_s_7_sThreadBusy
assign wci_s_7_SThreadBusy = 1'd1 ;
// value method wci_s_7_sFlag
assign wci_s_7_SFlag = 2'b0 ;
// value method wti_s_0_sThreadBusy
assign wti_s_0_SThreadBusy = 1'h0 ;
// value method wti_s_0_sReset_n
assign wti_s_0_SReset_n = 1'h0 ;
// value method wti_s_1_sThreadBusy
assign wti_s_1_SThreadBusy = 1'h0 ;
// value method wti_s_1_sReset_n
assign wti_s_1_SReset_n = 1'h0 ;
// value method wti_s_2_sThreadBusy
assign wti_s_2_SThreadBusy = 1'h0 ;
// value method wti_s_2_sReset_n
assign wti_s_2_SReset_n = 1'h0 ;
// value method wmiM0_mCmd
assign wmiM0_MCmd = appW2$wmiM0_MCmd ;
// value method wmiM0_mReqLast
assign wmiM0_MReqLast = appW2$wmiM0_MReqLast ;
// value method wmiM0_mReqInfo
assign wmiM0_MReqInfo = appW2$wmiM0_MReqInfo ;
// value method wmiM0_mAddrSpace
assign wmiM0_MAddrSpace = appW2$wmiM0_MAddrSpace ;
// value method wmiM0_mAddr
assign wmiM0_MAddr = appW2$wmiM0_MAddr ;
// value method wmiM0_mBurstLength
assign wmiM0_MBurstLength = appW2$wmiM0_MBurstLength ;
// value method wmiM0_mDataValid
assign wmiM0_MDataValid = appW2$wmiM0_MDataValid ;
// value method wmiM0_mDataLast
assign wmiM0_MDataLast = appW2$wmiM0_MDataLast ;
// value method wmiM0_mData
assign wmiM0_MData = appW2$wmiM0_MData ;
// value method wmiM0_mDataByteEn
assign wmiM0_MDataByteEn = appW2$wmiM0_MDataByteEn ;
// value method wmiM0_mFlag
assign wmiM0_MFlag = appW2$wmiM0_MFlag ;
// value method wmiM0_mReset_n
assign wmiM0_MReset_n = appW2$wmiM0_MReset_n ;
// value method wmiM1_mCmd
assign wmiM1_MCmd = appW4$wmiM0_MCmd ;
// value method wmiM1_mReqLast
assign wmiM1_MReqLast = appW4$wmiM0_MReqLast ;
// value method wmiM1_mReqInfo
assign wmiM1_MReqInfo = appW4$wmiM0_MReqInfo ;
// value method wmiM1_mAddrSpace
assign wmiM1_MAddrSpace = appW4$wmiM0_MAddrSpace ;
// value method wmiM1_mAddr
assign wmiM1_MAddr = appW4$wmiM0_MAddr ;
// value method wmiM1_mBurstLength
assign wmiM1_MBurstLength = appW4$wmiM0_MBurstLength ;
// value method wmiM1_mDataValid
assign wmiM1_MDataValid = appW4$wmiM0_MDataValid ;
// value method wmiM1_mDataLast
assign wmiM1_MDataLast = appW4$wmiM0_MDataLast ;
// value method wmiM1_mData
assign wmiM1_MData = appW4$wmiM0_MData ;
// value method wmiM1_mDataByteEn
assign wmiM1_MDataByteEn = appW4$wmiM0_MDataByteEn ;
// value method wmiM1_mFlag
assign wmiM1_MFlag = appW4$wmiM0_MFlag ;
// value method wmiM1_mReset_n
assign wmiM1_MReset_n = appW4$wmiM0_MReset_n ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = 3'h2 ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = 1'h0 ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = 36'hAAAAAAAAA ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = 12'hAAA ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = 1'h0 ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = 1'h0 ;
// value method wmemiM0_mData
assign wmemiM0_MData = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = 16'hAAAA ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = 1'h0 ;
// value method wsi_s_adc_sThreadBusy
assign wsi_s_adc_SThreadBusy = appW2$wsiS0_SThreadBusy ;
// value method wsi_s_adc_sReset_n
assign wsi_s_adc_SReset_n = appW2$wsiS0_SReset_n ;
// value method wsi_m_dac_mCmd
assign wsi_m_dac_MCmd = appW4$wsiM0_MCmd ;
// value method wsi_m_dac_mReqLast
assign wsi_m_dac_MReqLast = appW4$wsiM0_MReqLast ;
// value method wsi_m_dac_mBurstPrecise
assign wsi_m_dac_MBurstPrecise = appW4$wsiM0_MBurstPrecise ;
// value method wsi_m_dac_mBurstLength
assign wsi_m_dac_MBurstLength = appW4$wsiM0_MBurstLength ;
// value method wsi_m_dac_mData
assign wsi_m_dac_MData = appW4$wsiM0_MData ;
// value method wsi_m_dac_mByteEn
assign wsi_m_dac_MByteEn = appW4$wsiM0_MByteEn ;
// value method wsi_m_dac_mReqInfo
assign wsi_m_dac_MReqInfo = appW4$wsiM0_MReqInfo ;
// value method wsi_m_dac_mReset_n
assign wsi_m_dac_MReset_n = appW4$wsiM0_MReset_n ;
// value method uuid
assign uuid = id$uuid ;
// submodule appW2
mkSMAdapter4B #(.smaCtrlInit(32'h00000001),
.hasDebugLogic(hasDebugLogic)) appW2(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_2),
.wciS0_MAddr(appW2$wciS0_MAddr),
.wciS0_MAddrSpace(appW2$wciS0_MAddrSpace),
.wciS0_MByteEn(appW2$wciS0_MByteEn),
.wciS0_MCmd(appW2$wciS0_MCmd),
.wciS0_MData(appW2$wciS0_MData),
.wciS0_MFlag(appW2$wciS0_MFlag),
.wmiM0_SData(appW2$wmiM0_SData),
.wmiM0_SFlag(appW2$wmiM0_SFlag),
.wmiM0_SResp(appW2$wmiM0_SResp),
.wsiS0_MBurstLength(appW2$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW2$wsiS0_MByteEn),
.wsiS0_MCmd(appW2$wsiS0_MCmd),
.wsiS0_MData(appW2$wsiS0_MData),
.wsiS0_MReqInfo(appW2$wsiS0_MReqInfo),
.wmiM0_SThreadBusy(appW2$wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(appW2$wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(appW2$wmiM0_SRespLast),
.wmiM0_SReset_n(appW2$wmiM0_SReset_n),
.wsiM0_SThreadBusy(appW2$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW2$wsiM0_SReset_n),
.wsiS0_MReqLast(appW2$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW2$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW2$wsiS0_MReset_n),
.wciS0_SResp(appW2$wciS0_SResp),
.wciS0_SData(appW2$wciS0_SData),
.wciS0_SThreadBusy(appW2$wciS0_SThreadBusy),
.wciS0_SFlag(appW2$wciS0_SFlag),
.wmiM0_MCmd(appW2$wmiM0_MCmd),
.wmiM0_MReqLast(appW2$wmiM0_MReqLast),
.wmiM0_MReqInfo(appW2$wmiM0_MReqInfo),
.wmiM0_MAddrSpace(appW2$wmiM0_MAddrSpace),
.wmiM0_MAddr(appW2$wmiM0_MAddr),
.wmiM0_MBurstLength(appW2$wmiM0_MBurstLength),
.wmiM0_MDataValid(appW2$wmiM0_MDataValid),
.wmiM0_MDataLast(appW2$wmiM0_MDataLast),
.wmiM0_MData(appW2$wmiM0_MData),
.wmiM0_MDataByteEn(appW2$wmiM0_MDataByteEn),
.wmiM0_MFlag(appW2$wmiM0_MFlag),
.wmiM0_MReset_n(appW2$wmiM0_MReset_n),
.wsiM0_MCmd(appW2$wsiM0_MCmd),
.wsiM0_MReqLast(appW2$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW2$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW2$wsiM0_MBurstLength),
.wsiM0_MData(appW2$wsiM0_MData),
.wsiM0_MByteEn(appW2$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW2$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW2$wsiM0_MReset_n),
.wsiS0_SThreadBusy(appW2$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW2$wsiS0_SReset_n));
// submodule appW3
mkDDCWorker #(.ddcCtrlInit(32'h0),
.hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_3),
.wciS0_MAddr(appW3$wciS0_MAddr),
.wciS0_MAddrSpace(appW3$wciS0_MAddrSpace),
.wciS0_MByteEn(appW3$wciS0_MByteEn),
.wciS0_MCmd(appW3$wciS0_MCmd),
.wciS0_MData(appW3$wciS0_MData),
.wciS0_MFlag(appW3$wciS0_MFlag),
.wsiS0_MBurstLength(appW3$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW3$wsiS0_MByteEn),
.wsiS0_MCmd(appW3$wsiS0_MCmd),
.wsiS0_MData(appW3$wsiS0_MData),
.wsiS0_MReqInfo(appW3$wsiS0_MReqInfo),
.wsiS0_MReqLast(appW3$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW3$wsiS0_MReset_n),
.wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW3$wsiM0_SReset_n),
.wciS0_SResp(appW3$wciS0_SResp),
.wciS0_SData(appW3$wciS0_SData),
.wciS0_SThreadBusy(appW3$wciS0_SThreadBusy),
.wciS0_SFlag(appW3$wciS0_SFlag),
.wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW3$wsiS0_SReset_n),
.wsiM0_MCmd(appW3$wsiM0_MCmd),
.wsiM0_MReqLast(appW3$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW3$wsiM0_MBurstLength),
.wsiM0_MData(appW3$wsiM0_MData),
.wsiM0_MByteEn(appW3$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW3$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW3$wsiM0_MReset_n));
// submodule appW4
mkSMAdapter4B #(.smaCtrlInit(32'h00000002),
.hasDebugLogic(hasDebugLogic)) appW4(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_4),
.wciS0_MAddr(appW4$wciS0_MAddr),
.wciS0_MAddrSpace(appW4$wciS0_MAddrSpace),
.wciS0_MByteEn(appW4$wciS0_MByteEn),
.wciS0_MCmd(appW4$wciS0_MCmd),
.wciS0_MData(appW4$wciS0_MData),
.wciS0_MFlag(appW4$wciS0_MFlag),
.wmiM0_SData(appW4$wmiM0_SData),
.wmiM0_SFlag(appW4$wmiM0_SFlag),
.wmiM0_SResp(appW4$wmiM0_SResp),
.wsiS0_MBurstLength(appW4$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW4$wsiS0_MByteEn),
.wsiS0_MCmd(appW4$wsiS0_MCmd),
.wsiS0_MData(appW4$wsiS0_MData),
.wsiS0_MReqInfo(appW4$wsiS0_MReqInfo),
.wmiM0_SThreadBusy(appW4$wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(appW4$wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(appW4$wmiM0_SRespLast),
.wmiM0_SReset_n(appW4$wmiM0_SReset_n),
.wsiM0_SThreadBusy(appW4$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW4$wsiM0_SReset_n),
.wsiS0_MReqLast(appW4$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW4$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW4$wsiS0_MReset_n),
.wciS0_SResp(appW4$wciS0_SResp),
.wciS0_SData(appW4$wciS0_SData),
.wciS0_SThreadBusy(appW4$wciS0_SThreadBusy),
.wciS0_SFlag(appW4$wciS0_SFlag),
.wmiM0_MCmd(appW4$wmiM0_MCmd),
.wmiM0_MReqLast(appW4$wmiM0_MReqLast),
.wmiM0_MReqInfo(appW4$wmiM0_MReqInfo),
.wmiM0_MAddrSpace(appW4$wmiM0_MAddrSpace),
.wmiM0_MAddr(appW4$wmiM0_MAddr),
.wmiM0_MBurstLength(appW4$wmiM0_MBurstLength),
.wmiM0_MDataValid(appW4$wmiM0_MDataValid),
.wmiM0_MDataLast(appW4$wmiM0_MDataLast),
.wmiM0_MData(appW4$wmiM0_MData),
.wmiM0_MDataByteEn(appW4$wmiM0_MDataByteEn),
.wmiM0_MFlag(appW4$wmiM0_MFlag),
.wmiM0_MReset_n(appW4$wmiM0_MReset_n),
.wsiM0_MCmd(appW4$wsiM0_MCmd),
.wsiM0_MReqLast(appW4$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW4$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW4$wsiM0_MBurstLength),
.wsiM0_MData(appW4$wsiM0_MData),
.wsiM0_MByteEn(appW4$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW4$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW4$wsiM0_MReset_n),
.wsiS0_SThreadBusy(appW4$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW4$wsiS0_SReset_n));
// submodule id
mkUUID id(.uuid(id$uuid));
// inlined wires
assign tieOff0_wci_Es_mCmd_w$wget = wci_s_0_MCmd ;
assign tieOff0_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mAddrSpace_w$wget = wci_s_0_MAddrSpace ;
assign tieOff0_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mByteEn_w$wget = wci_s_0_MByteEn ;
assign tieOff0_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mAddr_w$wget = wci_s_0_MAddr ;
assign tieOff0_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mData_w$wget = wci_s_0_MData ;
assign tieOff0_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff1_wci_Es_mCmd_w$wget = wci_s_1_MCmd ;
assign tieOff1_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff1_wci_Es_mAddrSpace_w$wget = wci_s_1_MAddrSpace ;
assign tieOff1_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff1_wci_Es_mByteEn_w$wget = wci_s_1_MByteEn ;
assign tieOff1_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff1_wci_Es_mAddr_w$wget = wci_s_1_MAddr ;
assign tieOff1_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff1_wci_Es_mData_w$wget = wci_s_1_MData ;
assign tieOff1_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mCmd_w$wget = wci_s_5_MCmd ;
assign tieOff5_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mAddrSpace_w$wget = wci_s_5_MAddrSpace ;
assign tieOff5_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mByteEn_w$wget = wci_s_5_MByteEn ;
assign tieOff5_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mAddr_w$wget = wci_s_5_MAddr ;
assign tieOff5_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mData_w$wget = wci_s_5_MData ;
assign tieOff5_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mCmd_w$wget = wci_s_6_MCmd ;
assign tieOff6_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mAddrSpace_w$wget = wci_s_6_MAddrSpace ;
assign tieOff6_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mByteEn_w$wget = wci_s_6_MByteEn ;
assign tieOff6_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mAddr_w$wget = wci_s_6_MAddr ;
assign tieOff6_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mData_w$wget = wci_s_6_MData ;
assign tieOff6_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mCmd_w$wget = wci_s_7_MCmd ;
assign tieOff7_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mAddrSpace_w$wget = wci_s_7_MAddrSpace ;
assign tieOff7_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mByteEn_w$wget = wci_s_7_MByteEn ;
assign tieOff7_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mAddr_w$wget = wci_s_7_MAddr ;
assign tieOff7_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mData_w$wget = wci_s_7_MData ;
assign tieOff7_wci_Es_mData_w$whas = 1'd1 ;
// submodule appW2
assign appW2$wciS0_MAddr = wci_s_2_MAddr ;
assign appW2$wciS0_MAddrSpace = wci_s_2_MAddrSpace ;
assign appW2$wciS0_MByteEn = wci_s_2_MByteEn ;
assign appW2$wciS0_MCmd = wci_s_2_MCmd ;
assign appW2$wciS0_MData = wci_s_2_MData ;
assign appW2$wciS0_MFlag = wci_s_2_MFlag ;
assign appW2$wmiM0_SData = wmiM0_SData ;
assign appW2$wmiM0_SFlag = wmiM0_SFlag ;
assign appW2$wmiM0_SResp = wmiM0_SResp ;
assign appW2$wsiS0_MBurstLength = wsi_s_adc_MBurstLength ;
assign appW2$wsiS0_MByteEn = wsi_s_adc_MByteEn ;
assign appW2$wsiS0_MCmd = wsi_s_adc_MCmd ;
assign appW2$wsiS0_MData = wsi_s_adc_MData ;
assign appW2$wsiS0_MReqInfo = wsi_s_adc_MReqInfo ;
assign appW2$wmiM0_SThreadBusy = wmiM0_SThreadBusy ;
assign appW2$wmiM0_SDataThreadBusy = wmiM0_SDataThreadBusy ;
assign appW2$wmiM0_SRespLast = wmiM0_SRespLast ;
assign appW2$wmiM0_SReset_n = wmiM0_SReset_n ;
assign appW2$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ;
assign appW2$wsiM0_SReset_n = appW3$wsiS0_SReset_n ;
assign appW2$wsiS0_MReqLast = wsi_s_adc_MReqLast ;
assign appW2$wsiS0_MBurstPrecise = wsi_s_adc_MBurstPrecise ;
assign appW2$wsiS0_MReset_n = wsi_s_adc_MReset_n ;
// submodule appW3
assign appW3$wciS0_MAddr = wci_s_3_MAddr ;
assign appW3$wciS0_MAddrSpace = wci_s_3_MAddrSpace ;
assign appW3$wciS0_MByteEn = wci_s_3_MByteEn ;
assign appW3$wciS0_MCmd = wci_s_3_MCmd ;
assign appW3$wciS0_MData = wci_s_3_MData ;
assign appW3$wciS0_MFlag = wci_s_3_MFlag ;
assign appW3$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ;
assign appW3$wsiS0_MByteEn = appW2$wsiM0_MByteEn ;
assign appW3$wsiS0_MCmd = appW2$wsiM0_MCmd ;
assign appW3$wsiS0_MData = appW2$wsiM0_MData ;
assign appW3$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ;
assign appW3$wsiS0_MReqLast = appW2$wsiM0_MReqLast ;
assign appW3$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ;
assign appW3$wsiS0_MReset_n = appW2$wsiM0_MReset_n ;
assign appW3$wsiM0_SThreadBusy = appW4$wsiS0_SThreadBusy ;
assign appW3$wsiM0_SReset_n = appW4$wsiS0_SReset_n ;
// submodule appW4
assign appW4$wciS0_MAddr = wci_s_4_MAddr ;
assign appW4$wciS0_MAddrSpace = wci_s_4_MAddrSpace ;
assign appW4$wciS0_MByteEn = wci_s_4_MByteEn ;
assign appW4$wciS0_MCmd = wci_s_4_MCmd ;
assign appW4$wciS0_MData = wci_s_4_MData ;
assign appW4$wciS0_MFlag = wci_s_4_MFlag ;
assign appW4$wmiM0_SData = wmiM1_SData ;
assign appW4$wmiM0_SFlag = wmiM1_SFlag ;
assign appW4$wmiM0_SResp = wmiM1_SResp ;
assign appW4$wsiS0_MBurstLength = appW3$wsiM0_MBurstLength ;
assign appW4$wsiS0_MByteEn = appW3$wsiM0_MByteEn ;
assign appW4$wsiS0_MCmd = appW3$wsiM0_MCmd ;
assign appW4$wsiS0_MData = appW3$wsiM0_MData ;
assign appW4$wsiS0_MReqInfo = appW3$wsiM0_MReqInfo ;
assign appW4$wmiM0_SThreadBusy = wmiM1_SThreadBusy ;
assign appW4$wmiM0_SDataThreadBusy = wmiM1_SDataThreadBusy ;
assign appW4$wmiM0_SRespLast = wmiM1_SRespLast ;
assign appW4$wmiM0_SReset_n = wmiM1_SReset_n ;
assign appW4$wsiM0_SThreadBusy = wsi_m_dac_SThreadBusy ;
assign appW4$wsiM0_SReset_n = wsi_m_dac_SReset_n ;
assign appW4$wsiS0_MReqLast = appW3$wsiM0_MReqLast ;
assign appW4$wsiS0_MBurstPrecise = appW3$wsiM0_MBurstPrecise ;
assign appW4$wsiS0_MReset_n = appW3$wsiM0_MReset_n ;
endmodule // mkOCApp4B
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_BEHAVIORAL_V
`define SKY130_FD_SC_HS__HA_BEHAVIORAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire and0_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire xor0_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_BEHAVIORAL_V |
// This tests unalligned write/read access to packed structures
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test;
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word_t;
// Declare word* as a VARIABLE
wire word_t word_se0, word_se1, word_se2, word_se3;
wire word_t word_sw0, word_sw1, word_sw2, word_sw3;
wire word_t word_sp0, word_sp1, word_sp2, word_sp3;
wire word_t word_ep0, word_ep1, word_ep2, word_ep3;
// error counter
bit err = 0;
// access to structure elements
assign word_se1.high = {8+0{1'b1}};
assign word_se1.low = {8+0{1'b0}};
assign word_se2.high = {8+1{1'b1}};
assign word_se2.low = {8+1{1'b0}};
assign word_se3.high = {8-1{1'b1}};
assign word_se3.low = {8-1{1'b0}};
// access to whole structure
assign word_sw1 = {16+0{1'b1}};
assign word_sw2 = {16+1{1'b1}};
assign word_sw3 = {16-1{1'b1}};
// access to parts of structure elements
assign word_ep1.high [3:0] = {4+0{1'b1}};
assign word_ep1.low [3:0] = {4+0{1'b0}};
assign word_ep2.high [3:0] = {4+1{1'b1}};
assign word_ep2.low [3:0] = {4+1{1'b0}};
assign word_ep3.high [3:0] = {4-1{1'b1}};
assign word_ep3.low [3:0] = {4-1{1'b0}};
// access to parts of the whole structure
assign word_sp1 [11:4] = {8+0{1'b1}};
assign word_sp2 [11:4] = {8+1{1'b1}};
assign word_sp3 [11:4] = {8-1{1'b1}};
initial begin
#1;
// access to structure elements
if (word_se0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_se0 = 'b%b", word_se0 ); err=1; end
if (word_se1 !== 16'b11111111_00000000) begin $display("FAILED -- word_se1 = 'b%b", word_se1 ); err=1; end
if (word_se1.high !== 8'b11111111 ) begin $display("FAILED -- word_se1.high = 'b%b", word_se1.high); err=1; end
if (word_se1.low !== 8'b00000000 ) begin $display("FAILED -- word_se1.low = 'b%b", word_se1.low ); err=1; end
if (word_se2 !== 16'b11111111_00000000) begin $display("FAILED -- word_se2 = 'b%b", word_se2 ); err=1; end
if (word_se2.high !== 8'b11111111 ) begin $display("FAILED -- word_se2.high = 'b%b", word_se2.high); err=1; end
if (word_se2.low !== 8'b00000000 ) begin $display("FAILED -- word_se2.low = 'b%b", word_se2.low ); err=1; end
if (word_se3 !== 16'b01111111_00000000) begin $display("FAILED -- word_se3 = 'b%b", word_se3 ); err=1; end
if (word_se3.high !== 8'b01111111 ) begin $display("FAILED -- word_se3.high = 'b%b", word_se3.high); err=1; end
if (word_se3.low !== 8'b00000000 ) begin $display("FAILED -- word_se3.low = 'b%b", word_se3.low ); err=1; end
// access to whole structure
if (word_sw0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sw0 = 'b%b", word_sw0 ); err=1; end
if (word_sw1 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw1 = 'b%b", word_sw1 ); err=1; end
if (word_sw2 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw2 = 'b%b", word_sw2 ); err=1; end
if (word_sw3 !== 16'b01111111_11111111) begin $display("FAILED -- word_sw3 = 'b%b", word_sw3 ); err=1; end
// access to parts of structure elements
if (word_ep0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_ep0 = 'b%b", word_ep0 ); err=1; end
if (word_ep1 !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep1 = 'b%b", word_ep1 ); err=1; end
if (word_ep1.high !== 8'bzzzz1111 ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end
if (word_ep1.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep1.low = 'b%b", word_ep1.low ); err=1; end
if (word_ep2 !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep2 = 'b%b", word_ep2 ); err=1; end
if (word_ep2.high !== 8'bzzzz1111 ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end
if (word_ep2.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep2.low = 'b%b", word_ep2.low ); err=1; end
if (word_ep3 !== 16'bzzzz0111_zzzz0000) begin $display("FAILED -- word_ep3 = 'b%b", word_ep3 ); err=1; end
if (word_ep3.high !== 8'bzzzz0111 ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end
if (word_ep3.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep3.low = 'b%b", word_ep3.low ); err=1; end
// access to parts of the whole structure
if (word_sp0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sp0 = 'b%b", word_sp0 ); err=1; end
if (word_sp1 !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp1 = 'b%b", word_sp1 ); err=1; end
if (word_sp2 !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp2 = 'b%b", word_sp2 ); err=1; end
if (word_sp3 !== 16'bzzzz0111_1111zzzz) begin $display("FAILED -- word_sp3 = 'b%b", word_sp3 ); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:35 08/11/2009
// Design Name:
// Module Name: STATUS_IN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////
///// Decode four patterns for specific states\
///// Idle 00000000
///// Reset 01010101
///// FIFO full 00001111
///// Training_done 00110011
/////
/////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_STATUS_IN(
input CLK,
input MODULE_RST,
output reg RESET, //output indicating reset state
output reg FIFO_FULL, //output indicating full state
output reg TRAINING_DONE, //output indicating done state
input STATUS,
output reg status_error // indicates error if ambiguous status lasts longer than 8 cycles
// output reg IDLE_RESET // Jiansong: why we need IDLE_RESET?
);
/////////////////////////////////////////////////////////////////////////////////
// input CLK;
// input MODULE_RST;
// input STATUS;
// output RESET,
// FIFO_FULL,
// TRAINING_DONE,
// IDLE_RESET;
/////////////////////////////////////////////////////////////////////////////////
// reg RESET,
// FIFO_FULL,
// TRAINING_DONE,
reg IDLE_RESET;
reg IDLE_FLAG; // why we need this flag?
reg ambiguity; // indicates ambiguous status
reg [2:0] error_cnt;
reg [7:0] shift_reg;
parameter RST = 2'b00;
parameter FULL = 2'b01;
parameter DONE = 2'b10;
parameter IDLE = 2'b11;
reg [1:0] INT_SAT;
/////////////////////////////////////////////////////////////////////////////////
always @ ( negedge CLK ) begin
if ( MODULE_RST == 1'b1 ) begin
shift_reg <= 8'h00;
end
else begin
shift_reg <= {shift_reg[6:0], STATUS};
end
end
/////////////////////////////////////////////////////////////////////////////////
/// Pattern Recognition
// Modified by Jiansong, 2010-5-25, remove ambiguity
always @ ( negedge CLK ) begin
ambiguity <= 1'b0;
if ( shift_reg == 8'h55 | shift_reg == 8'hAA) begin
INT_SAT <= RST;
end
else if ( shift_reg == 8'hF0 | shift_reg == 8'h87 | shift_reg == 8'hC3 | shift_reg == 8'hE1 | shift_reg == 8'h78 | shift_reg == 8'h3C | shift_reg == 8'h1E | shift_reg == 8'h0F ) begin
INT_SAT <= FULL;
end
else if ( shift_reg == 8'h33 | shift_reg == 8'h66 | shift_reg == 8'hCC | shift_reg == 8'h99 ) begin
INT_SAT <= DONE;
end
else if ( shift_reg == 8'h00) begin
INT_SAT <= IDLE;
end
else begin// by default, the previous INT_SAT remains, this normally happen when the status is changing
INT_SAT <= INT_SAT;
ambiguity <= 1'b1;
end
end
always@ (negedge CLK) begin
if (MODULE_RST) begin
error_cnt <= 3'b000;
end else if(ambiguity) begin
if (error_cnt != 3'b111)
error_cnt <= error_cnt + 3'b001;
else
error_cnt <= error_cnt;
end else begin
error_cnt <= 3'b000;
end
end
always@ (negedge CLK) begin
status_error <= (error_cnt == 3'b111) ? 1'b1 : 1'b0;
end
/////////////////////////////////////////////////////////////////////////////////
/// States are exclusive of each other
always @ (posedge CLK) begin
if ( MODULE_RST == 1'b1 ) begin
RESET <= 1'b0;
TRAINING_DONE <= 1'b0;
FIFO_FULL <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == RST) begin
RESET <= 1'b1;
TRAINING_DONE <= 1'b0;
FIFO_FULL <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == DONE ) begin
TRAINING_DONE <= 1'b1;
FIFO_FULL <= 1'b0;
RESET <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == FULL ) begin
RESET <= 1'b0;
FIFO_FULL <= 1'b1;
TRAINING_DONE <= 1'b1;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == IDLE ) begin
if(IDLE_FLAG == 0) // Jiansong: edge detection
begin
IDLE_FLAG <= 1;
IDLE_RESET <= 1;
end
else
begin
IDLE_RESET <= 0;
end
RESET <= 1'b0;
FIFO_FULL <= 1'b0;
TRAINING_DONE <= 1'b0;
end
end
endmodule
|
`timescale 1ns/1ps
`default_nettype none
module SST39VF200A(A15, A14, A13, A12, A11, A10, A9, A8, NC1, NC2, WE_n, NC3, NC4, NC5, NC6, NC7, NC8, A7, A6, A5, A4, A3, A2, A1, A0, CE_n, VSS1, OE_n, DQ0, DQ8, DQ1, DQ9, DQ2, DQ10, DQ3, DQ11, VDD, DQ4, DQ12, DQ5, DQ13, DQ6, DQ14, DQ7, DQ15, VSS2, NC9, A16, SIM_RST, SIM_CLK
`ifdef TARGET_FPGA
, EPCS_DATA, EPCS_CSN, EPCS_DCLK, EPCS_ASDI
`endif
);
input wire SIM_RST;
input wire SIM_CLK;
`ifdef TARGET_FPGA
// FPGA-only EPCS IO
input wire EPCS_DATA;
output reg EPCS_CSN = 1'b1;
output reg EPCS_DCLK = 1'b1;
output reg EPCS_ASDI = 1'b0;
// EPCS controller state machine states
localparam DESELECTED=2'd0;
localparam SET=2'd1;
localparam RESET=2'd2;
localparam HOLD=2'd3;
// Current state
reg [1:0] state = DESELECTED;
// Command to be sent to EPCS
reg [39:0] cmd;
// Index into command or read
reg [5:0] ctr;
// Word read from EPCS
reg [15:0] sensed_word;
// Completion marker for end of command cycle
reg cmd_complete = 1'b0;
`endif
input wire VDD;
input wire VSS1;
input wire VSS2;
input wire CE_n;
input wire OE_n;
input wire WE_n;
input wire A0;
input wire A1;
input wire A2;
input wire A3;
input wire A4;
input wire A5;
input wire A6;
input wire A7;
input wire A8;
input wire A9;
input wire A10;
input wire A11;
input wire A12;
input wire A13;
input wire A14;
input wire A15;
input wire A16;
output wire DQ0;
output wire DQ1;
output wire DQ2;
output wire DQ3;
output wire DQ4;
output wire DQ5;
output wire DQ6;
output wire DQ7;
output wire DQ8;
output wire DQ9;
output wire DQ10;
output wire DQ11;
output wire DQ12;
output wire DQ13;
output wire DQ14;
output wire DQ15;
input wire NC1;
input wire NC2;
input wire NC3;
input wire NC4;
input wire NC5;
input wire NC6;
input wire NC7;
input wire NC8;
input wire NC9;
reg [15:0] data;
assign DQ0 = data[0];
assign DQ1 = data[1];
assign DQ2 = data[2];
assign DQ3 = data[3];
assign DQ4 = data[4];
assign DQ5 = data[5];
assign DQ6 = data[6];
assign DQ7 = data[7];
assign DQ8 = data[8];
assign DQ9 = data[9];
assign DQ10 = data[10];
assign DQ11 = data[11];
assign DQ12 = data[12];
assign DQ13 = data[13];
assign DQ14 = data[14];
assign DQ15 = data[15];
wire [16:0] addr;
`ifdef TARGET_FPGA
assign addr =
`else
assign #40 addr =
`endif
{A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0};
`ifdef TARGET_FPGA
always @(posedge SIM_CLK)
begin
case(state)
DESELECTED: begin
// When the chip is deselected, assert EPCS_DCLK high and EPCS_CSN
// high
EPCS_DCLK <= 1'b1;
EPCS_CSN <= 1'b1;
if (CE_n == 1'b0) begin
// If the flash chip enable goes low, select the EPCS and
// transition to the SET state
EPCS_CSN <= 1'b0;
state <= SET;
// Determine the command that needs to be sent. The
// 'Fast Read' opcode is 0x0b, and the AGC code is stored
// starting at address 0x7e0000 in the EPCS. The latched
// address needs to be shifted up one, since it is addressing
// 16-bit words and the EPCS data is 8 bits wide. There's also
// a trailing byte to give the device time to set up.
cmd = 40'h0b7e000000 + {14'h0, addr, 9'h0};
ctr <= 6'd39;
cmd_complete <= 1'b0;
end
end
SET: begin
// Step the clock
EPCS_DCLK = ~EPCS_DCLK;
if (EPCS_DCLK == 1'b0) begin
// If we've just taken a falling edge on the clock, transition
// ASDI to the next bit of the command
EPCS_ASDI <= cmd[ctr];
if (ctr == 6'd0) begin
// If we hit the end of the command, set the command
// completion bit. This is necessary because we need to
// remain in the SET state until the next rising edge
// (when the EPCS will latch the last command bit).
// Subsequent rising edges are when we need to read in
// data.
cmd_complete <= 1'b1;
end else begin
// Otherwise, move on to the next bit of the command
ctr <= ctr - 6'd1;
end
end
if (EPCS_DCLK == 1'b1 && cmd_complete == 1'b1) begin
// If the command is done and we've sent out the final rising
// edge, transition to RESET where we will read in the word
state <= RESET;
ctr <= 6'd15;
end
end
RESET: begin
// Step the clock
EPCS_DCLK = ~EPCS_DCLK;
if (EPCS_DCLK == 1'b1) begin
// On rising edge, incoming data is valid. Latch the current
// value into the sensed word
sensed_word[ctr] = EPCS_DATA;
if (ctr == 6'b0) begin
// If we've gotten the last bit of data, proceed to the
// HOLD state
state <= HOLD;
end
// Move on to the next bit
ctr = ctr - 6'b1;
end
end
HOLD: begin
// We're done talking to the EPCS -- assert EPCS_DCLK and EPCS_CSN
// high again
EPCS_DCLK <= 1'b1;
EPCS_CSN <= 1'b1;
if (CE_n == 1'b1) begin
// Wait for the flash chip to become deselected before
// transitioning back to the DESELECTED state
state <= DESELECTED;
end
end
endcase
if (OE_n == 1'b0) begin
// During any state, if OE_n goes low, show the currently sensed
// data word
data = sensed_word;
end else begin
// Otherwise, just assert 0
data = 15'b0;
end
end
`else
always @(CE_n, OE_n, addr)
begin
if (!CE_n && !OE_n)
begin
case (addr)
`include "roms/rom.v"
default: data = 16'hFFFF;
endcase
end
else
begin
data = 16'bZ;
end
end
`endif
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
//-----------------------------------------------------------------
// Module - Instruction Fetch
//-----------------------------------------------------------------
module altor32_fetch
(
// General
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Instruction Fetch
output fetch_o /*verilator public*/,
output reg [31:0] pc_o /*verilator public*/,
input [31:0] data_i /*verilator public*/,
input data_valid_i/*verilator public*/,
// Branch target
input branch_i /*verilator public*/,
input [31:0] branch_pc_i /*verilator public*/,
input stall_i /*verilator public*/,
// Decoded opcode
output [31:0] opcode_o /*verilator public*/,
output [31:0] opcode_pc_o /*verilator public*/,
output opcode_valid_o /*verilator public*/,
// Decoded register details
output [4:0] ra_o /*verilator public*/,
output [4:0] rb_o /*verilator public*/,
output [4:0] rd_o /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter BOOT_VECTOR = 32'h00000000;
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
parameter PIPELINED_FETCH = "DISABLED";
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg rd_q;
reg [31:0] pc_q;
reg [31:0] pc_last_q;
//-------------------------------------------------------------------
// Next PC state machine
//-------------------------------------------------------------------
wire [31:0] next_pc_w = pc_q + 32'd4;
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
pc_q <= BOOT_VECTOR + `VECTOR_RESET;
pc_last_q <= BOOT_VECTOR + `VECTOR_RESET;
rd_q <= 1'b1;
end
else if (~stall_i)
begin
// Branch - Next PC = branch target + 4
if (branch_i)
begin
rd_q <= 1'b0;
pc_last_q <= pc_o;
pc_q <= branch_pc_i + 4;
end
// Normal sequential execution (and instruction is ready)
else if (data_valid_i)
begin
// New cache line?
if (next_pc_w[CACHE_LINE_SIZE_WIDTH-1:0] == {CACHE_LINE_SIZE_WIDTH{1'b0}})
rd_q <= 1'b1;
else
rd_q <= 1'b0;
pc_last_q <= pc_o;
pc_q <= next_pc_w;
end
else
begin
rd_q <= 1'b0;
pc_last_q <= pc_o;
end
end
end
//-------------------------------------------------------------------
// Instruction Fetch
//-------------------------------------------------------------------
always @ *
begin
// Stall, revert to last requested PC
if (stall_i)
pc_o = pc_last_q;
else if (branch_i)
pc_o = branch_pc_i;
else if (~data_valid_i)
pc_o = pc_last_q;
else
pc_o = pc_q;
end
assign fetch_o = branch_i ? 1'b1 : rd_q;
//-------------------------------------------------------------------
// Opcode output (retiming)
//-------------------------------------------------------------------
generate
if (PIPELINED_FETCH == "ENABLED")
begin: FETCH_FLOPS
reg [31:0] opcode_q;
reg [31:0] opcode_pc_q;
reg opcode_valid_q;
reg branch_q;
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
opcode_q <= 32'b0;
opcode_pc_q <= 32'b0;
opcode_valid_q <= 1'b0;
branch_q <= 1'b0;
end
else
begin
branch_q <= branch_i;
if (~stall_i)
begin
opcode_pc_q <= pc_last_q;
opcode_q <= data_i;
opcode_valid_q <= (data_valid_i & !branch_i);
end
end
end
// Opcode output
assign opcode_valid_o = opcode_valid_q & ~branch_i & ~branch_q;
assign opcode_o = opcode_q;
assign opcode_pc_o = opcode_pc_q;
end
//-------------------------------------------------------------------
// Opcode output
//-------------------------------------------------------------------
else
begin : NO_FETCH_FLOPS
assign opcode_valid_o = (data_valid_i & !branch_i);
assign opcode_o = data_i;
assign opcode_pc_o = pc_last_q;
end
endgenerate
//-------------------------------------------------------------------
// Opcode output
//-------------------------------------------------------------------
// If simulation, RA = 03 if NOP instruction
`ifdef SIMULATION
wire [7:0] fetch_inst_w = {2'b00, opcode_o[31:26]};
wire nop_inst_w = (fetch_inst_w == `INST_OR32_NOP);
assign ra_o = nop_inst_w ? 5'd3 : opcode_o[20:16];
`else
assign ra_o = opcode_o[20:16];
`endif
assign rb_o = opcode_o[15:11];
assign rd_o = opcode_o[25:21];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_1_V
`define SKY130_FD_SC_HD__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
ign, ign2, ign3, ign4, ign4s,
// Inputs
clk
);
input clk;
output [31:0] ign;
output [3:0] ign2;
output [11:0] ign3;
parameter [95:0] P6 = 6;
localparam P64 = (1 << P6);
// verilator lint_off WIDTH
localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
// verilator lint_on WIDTH
reg [31:0] iright;
reg signed [31:0] irights;
reg [31:0] ileft;
reg [P64-1:0] qright;
reg signed [P64-1:0] qrights;
reg [P64-1:0] qleft;
reg [95:0] wright;
reg signed [95:0] wrights;
reg [95:0] wleft;
reg [31:0] q_iright;
reg signed [31:0] q_irights;
reg [31:0] q_ileft;
reg [P64-1:0] q_qright;
reg signed [P64-1:0] q_qrights;
reg [P64-1:0] q_qleft;
reg [95:0] q_wright;
reg signed [95:0] q_wrights;
reg [95:0] q_wleft;
reg [31:0] w_iright;
reg signed [31:0] w_irights;
reg [31:0] w_ileft;
reg [P64-1:0] w_qright;
reg signed [P64-1:0] w_qrights;
reg [P64-1:0] w_qleft;
reg [95:0] w_wright;
reg signed [95:0] w_wrights;
reg [95:0] w_wleft;
reg [31:0] iamt;
reg [63:0] qamt;
reg [95:0] wamt;
assign ign = {31'h0, clk} >>> 4'bx; // bug760
assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174
assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}},
iamt[1:0] >> {11{iamt[5:2]}},
$signed(iamt[1:0]) >>> {22{iamt[5:2]}},
$signed(iamt[1:0]) >>> {11{iamt[5:2]}},
iamt[1:0] << {22{iamt[5:2]}},
iamt[1:0] << {11{iamt[5:2]}}};
wire [95:0] wamtt = {iamt,iamt,iamt};
output wire [95:0] ign4;
assign ign4 = wamtt >> {11{iamt[5:2]}};
output wire signed [95:0] ign4s;
assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}};
always @* begin
iright = 32'h819b018a >> iamt;
irights = 32'sh819b018a >>> signed'(iamt);
ileft = 32'h819b018a << iamt;
qright = 64'hf784bf8f_12734089 >> iamt;
qrights = 64'shf784bf8f_12734089 >>> signed'(iamt);
qleft = 64'hf784bf8f_12734089 << iamt;
wright = 96'hf784bf8f_12734089_190abe48 >> iamt;
wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt);
wleft = 96'hf784bf8f_12734089_190abe48 << iamt;
q_iright = 32'h819b018a >> qamt;
q_irights = 32'sh819b018a >>> signed'(qamt);
q_ileft = 32'h819b018a << qamt;
q_qright = 64'hf784bf8f_12734089 >> qamt;
q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt);
q_qleft = 64'hf784bf8f_12734089 << qamt;
q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt;
q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt);
q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt;
w_iright = 32'h819b018a >> wamt;
w_irights = 32'sh819b018a >>> signed'(wamt);
w_ileft = 32'h819b018a << wamt;
w_qright = 64'hf784bf8f_12734089 >> wamt;
w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt);
w_qleft = 64'hf784bf8f_12734089 << wamt;
w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt;
w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt);
w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright);
`endif
if (cyc==1) begin
iamt <= 0;
qamt <= 0;
wamt <= 0;
if (P64 != 64) $stop;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
iamt <= 28;
qamt <= 28;
wamt <= 28;
if (ileft != 32'h819b018a) $stop;
if (iright != 32'h819b018a) $stop;
if (irights != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
if (qrights != 64'hf784bf8f_12734089) $stop;
if (wleft != 96'hf784bf8f12734089190abe48) $stop;
if (wright != 96'hf784bf8f12734089190abe48) $stop;
if (wrights != 96'hf784bf8f12734089190abe48) $stop;
end
if (cyc==3) begin
iamt <= 31;
qamt <= 31;
wamt <= 31;
if (ileft != 32'ha0000000) $stop;
if (iright != 32'h8) $stop;
if (irights != 32'hfffffff8) $stop;
if (qleft != 64'hf127340890000000) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
if (qrights != 64'hffffffff784bf8f1) $stop;
if (wleft != 96'hf12734089190abe480000000) $stop;
if (wright != 96'h0000000f784bf8f127340891) $stop;
if (wrights != 96'hffffffff784bf8f127340891) $stop;
end
if (cyc==4) begin
iamt <= 32;
qamt <= 32;
wamt <= 32;
if (ileft != 32'h0) $stop;
if (iright != 32'h1) $stop;
if (qleft != 64'h8939a04480000000) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
iamt <= 33;
qamt <= 33;
wamt <= 33;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h1273408900000000) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
iamt <= 64;
qamt <= 64;
wamt <= 64;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h24e6811200000000) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
iamt <= 128;
qamt <= 128;
wamt <= 128;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
iamt <= 100;
qamt <= {32'h10, 32'h0};
wamt <= {32'h10, 64'h0};
if (ileft != '0) $stop;
if (iright != '0) $stop;
if (irights != '1) $stop;
if (qleft != '0) $stop;
if (qright != '0) $stop;
if (qrights != '1) $stop;
if (wleft != '0) $stop;
if (wright != '0) $stop;
if (wrights != '1) $stop;
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
// General rule to test all q's
if (cyc != 0) begin
if (ileft != q_ileft) $stop;
if (iright != q_iright) $stop;
if (irights != q_irights) $stop;
if (qleft != q_qleft) $stop;
if (qright != q_qright) $stop;
if (qrights != q_qrights) $stop;
if (wleft != q_wleft) $stop;
if (wright != q_wright) $stop;
if (wrights != q_wrights) $stop;
if (ileft != w_ileft) $stop;
if (iright != w_iright) $stop;
if (irights != w_irights) $stop;
if (qleft != w_qleft) $stop;
if (qright != w_qright) $stop;
if (qrights != w_qrights) $stop;
if (wleft != w_wleft) $stop;
if (wright != w_wright) $stop;
if (wrights != w_wrights) $stop;
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (A_DATA_WIDTH),
.WIDTH_B (B_DATA_WIDTH))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A (data_a),
.B (data_b),
.P (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %ALTERA_MULT_ADD v16.0%
// GENERATION: XML
// mult_add_fix8bx4.v
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module mult_add_fix8bx4 (
output wire [17:0] result, // result.result
input wire [7:0] dataa_0, // dataa_0.dataa_0
input wire [7:0] dataa_1, // dataa_1.dataa_1
input wire [7:0] dataa_2, // dataa_2.dataa_2
input wire [7:0] dataa_3, // dataa_3.dataa_3
input wire [7:0] datab_0, // datab_0.datab_0
input wire [7:0] datab_1, // datab_1.datab_1
input wire [7:0] datab_2, // datab_2.datab_2
input wire [7:0] datab_3, // datab_3.datab_3
input wire clock0 // clock0.clock0
);
mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
.result (result), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.dataa_1 (dataa_1), // dataa_1.dataa_1
.dataa_2 (dataa_2), // dataa_2.dataa_2
.dataa_3 (dataa_3), // dataa_3.dataa_3
.datab_0 (datab_0), // datab_0.datab_0
.datab_1 (datab_1), // datab_1.datab_1
.datab_2 (datab_2), // datab_2.datab_2
.datab_3 (datab_3), // datab_3.datab_3
.clock0 (clock0) // clock0.clock0
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_mult_add" version="16.0" >
// Retrieval info: <generic name="number_of_multipliers" value="4" />
// Retrieval info: <generic name="width_a" value="8" />
// Retrieval info: <generic name="width_b" value="8" />
// Retrieval info: <generic name="width_result" value="18" />
// Retrieval info: <generic name="gui_4th_asynchronous_clear" value="false" />
// Retrieval info: <generic name="gui_associated_clock_enable" value="false" />
// Retrieval info: <generic name="gui_output_register" value="true" />
// Retrieval info: <generic name="gui_output_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_output_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_output_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier1_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr1" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr1" value="NONE" />
// Retrieval info: <generic name="gui_multiplier3_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr3" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr3" value="NONE" />
// Retrieval info: <generic name="gui_use_subnadd" value="false" />
// Retrieval info: <generic name="gui_representation_a" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signa" value="false" />
// Retrieval info: <generic name="gui_register_signa_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signa_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signa_sclr" value="NONE" />
// Retrieval info: <generic name="gui_representation_b" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signb" value="false" />
// Retrieval info: <generic name="gui_register_signb_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signb_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signb_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a" value="true" />
// Retrieval info: <generic name="gui_input_register_a_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_a_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b" value="true" />
// Retrieval info: <generic name="gui_input_register_b_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_b_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_a_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_scanouta_register" value="false" />
// Retrieval info: <generic name="gui_scanouta_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_scanouta_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_scanouta_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_b_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_multiplier_register" value="false" />
// Retrieval info: <generic name="gui_multiplier_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_multiplier_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_register_sclr" value="NONE" />
// Retrieval info: <generic name="preadder_mode" value="SIMPLE" />
// Retrieval info: <generic name="gui_preadder_direction" value="ADD" />
// Retrieval info: <generic name="width_c" value="16" />
// Retrieval info: <generic name="gui_datac_input_register" value="false" />
// Retrieval info: <generic name="gui_datac_input_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_datac_input_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_datac_input_register_sclr" value="NONE" />
// Retrieval info: <generic name="width_coef" value="18" />
// Retrieval info: <generic name="gui_coef_register" value="false" />
// Retrieval info: <generic name="gui_coef_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_coef_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_coef_register_sclr" value="NONE" />
// Retrieval info: <generic name="coef0_0" value="0" />
// Retrieval info: <generic name="coef0_1" value="0" />
// Retrieval info: <generic name="coef0_2" value="0" />
// Retrieval info: <generic name="coef0_3" value="0" />
// Retrieval info: <generic name="coef0_4" value="0" />
// Retrieval info: <generic name="coef0_5" value="0" />
// Retrieval info: <generic name="coef0_6" value="0" />
// Retrieval info: <generic name="coef0_7" value="0" />
// Retrieval info: <generic name="coef1_0" value="0" />
// Retrieval info: <generic name="coef1_1" value="0" />
// Retrieval info: <generic name="coef1_2" value="0" />
// Retrieval info: <generic name="coef1_3" value="0" />
// Retrieval info: <generic name="coef1_4" value="0" />
// Retrieval info: <generic name="coef1_5" value="0" />
// Retrieval info: <generic name="coef1_6" value="0" />
// Retrieval info: <generic name="coef1_7" value="0" />
// Retrieval info: <generic name="coef2_0" value="0" />
// Retrieval info: <generic name="coef2_1" value="0" />
// Retrieval info: <generic name="coef2_2" value="0" />
// Retrieval info: <generic name="coef2_3" value="0" />
// Retrieval info: <generic name="coef2_4" value="0" />
// Retrieval info: <generic name="coef2_5" value="0" />
// Retrieval info: <generic name="coef2_6" value="0" />
// Retrieval info: <generic name="coef2_7" value="0" />
// Retrieval info: <generic name="coef3_0" value="0" />
// Retrieval info: <generic name="coef3_1" value="0" />
// Retrieval info: <generic name="coef3_2" value="0" />
// Retrieval info: <generic name="coef3_3" value="0" />
// Retrieval info: <generic name="coef3_4" value="0" />
// Retrieval info: <generic name="coef3_5" value="0" />
// Retrieval info: <generic name="coef3_6" value="0" />
// Retrieval info: <generic name="coef3_7" value="0" />
// Retrieval info: <generic name="accumulator" value="NO" />
// Retrieval info: <generic name="accum_direction" value="ADD" />
// Retrieval info: <generic name="gui_ena_preload_const" value="false" />
// Retrieval info: <generic name="gui_accumulate_port_select" value="0" />
// Retrieval info: <generic name="loadconst_value" value="64" />
// Retrieval info: <generic name="gui_accum_sload_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_accum_sload_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_accum_sload_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_double_accum" value="false" />
// Retrieval info: <generic name="chainout_adder" value="NO" />
// Retrieval info: <generic name="chainout_adder_direction" value="ADD" />
// Retrieval info: <generic name="port_negate" value="PORT_UNUSED" />
// Retrieval info: <generic name="negate_register" value="UNREGISTERED" />
// Retrieval info: <generic name="negate_aclr" value="NONE" />
// Retrieval info: <generic name="negate_sclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay" value="false" />
// Retrieval info: <generic name="gui_systolic_delay_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_systolic_delay_aclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay_sclr" value="NONE" />
// Retrieval info: <generic name="gui_pipelining" value="0" />
// Retrieval info: <generic name="latency" value="0" />
// Retrieval info: <generic name="gui_input_latency_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_latency_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_latency_sclr" value="NONE" />
// Retrieval info: <generic name="selected_device_family" value="Stratix V" />
// Retrieval info: <generic name="reg_autovec_sim" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : mult_add_fix8bx4.vo
// RELATED_FILES: mult_add_fix8bx4.v, mult_add_fix8bx4_0002.v
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eg_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eg_e.v,v 1.1 2004/04/06 10:50:32 wig Exp $
// $Date: 2004/04/06 10:50:32 $
// $Log: inst_eg_e.v,v $
// Revision 1.1 2004/04/06 10:50:32 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eg_e
//
// No `defines in this module
module inst_eg_e
//
// Generated module inst_eg
//
(
acg_systime_init,
adp_scani,
adp_scano,
nreset,
nreset_s
);
// Generated Module Inputs:
input [6:0] adp_scani;
input nreset;
input nreset_s;
// Generated Module Outputs:
output [30:0] acg_systime_init;
output [6:0] adp_scano;
// Generated Wires:
wire [30:0] acg_systime_init;
wire [6:0] adp_scani;
wire [6:0] adp_scano;
wire nreset;
wire nreset_s;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eg_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
module sha1_compression(
input [159:0] hash_state_in,
input [ 31:0] w,
input [ 6:0] round,
output [159:0] hash_state_out
);
reg [31:0] k;
reg [31:0] f;
wire [31:0] temp;
wire [31:0] a = hash_state_in[159:128];
wire [31:0] b = hash_state_in[127:96 ];
wire [31:0] c = hash_state_in[ 95:64 ];
wire [31:0] d = hash_state_in[ 63:32 ];
wire [31:0] e = hash_state_in[ 31:0 ];
assign temp = {a[26:0], a[31:27]} + f + e + k + w;
assign hash_state_out = {temp, a, {b[1:0], b[31:2]}, c, d};
always @ (round or b or c or d) begin
case (1'b1)
between(7'd0, round, 7'd19): begin k = 32'h5A827999; f = (b & c) | (~b & d); end
between(7'd20, round, 7'd39): begin k = 32'h6ED9EBA1; f = b ^ c ^ d; end
between(7'd40, round, 7'd59): begin k = 32'h8F1BBCDC; f = (b & c) | (b & d) | (c & d); end
between(7'd60, round, 7'd79): begin k = 32'hCA62C1D6; f = b ^ c ^ d; end
endcase
end
function reg between(
input [6:0] low,
input [6:0] value,
input [6:0] high
);
begin
between = value >= low && value <= high;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`timescale 1ns/10ps
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_addsub ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// addition/subtraction entity for the addition/subtraction ////
//// unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, [email protected] ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_addsub(
clk,
rst,
fpu_op_i,
fracta_i,
fractb_i,
signa_i,
signb_i,
fract_o,
sign_o);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input fpu_op_i;
input [FRAC_WIDTH+4:0] fracta_i;
input [FRAC_WIDTH+4:0] fractb_i;
input signa_i;
input signb_i;
output reg [FRAC_WIDTH+4:0] fract_o;
output reg sign_o;
wire [FRAC_WIDTH+4:0] s_fracta_i;
wire [FRAC_WIDTH+4:0] s_fractb_i;
wire [FRAC_WIDTH+4:0] s_fract_o;
wire s_signa_i, s_signb_i, s_sign_o;
wire s_fpu_op_i;
wire fracta_gt_fractb;
wire s_addop;
assign s_fracta_i = fracta_i;
assign s_fractb_i = fractb_i;
assign s_signa_i = signa_i;
assign s_signb_i = signb_i;
assign s_fpu_op_i = fpu_op_i;
always @(posedge clk or posedge rst)
if (rst)
begin
fract_o <= 'd0;
sign_o <= 1'b0;
end
else
begin
fract_o <= s_fract_o;
sign_o <= s_sign_o;
end
assign fracta_gt_fractb = s_fracta_i > s_fractb_i;
// check if its a subtraction or an addition operation
assign s_addop = ((s_signa_i ^ s_signb_i) & !s_fpu_op_i) |
((s_signa_i ^~ s_signb_i) & s_fpu_op_i);
// sign of result
assign s_sign_o = ((s_fract_o == 28'd0) & !(s_signa_i & s_signb_i)) ? 1'b0 :
(!s_signa_i & (!fracta_gt_fractb & (fpu_op_i^s_signb_i)))|
(s_signa_i & (fracta_gt_fractb | (fpu_op_i^s_signb_i)));
// add/substract
assign s_fract_o = s_addop ?
(fracta_gt_fractb ? s_fracta_i - s_fractb_i :
s_fractb_i - s_fracta_i) :
s_fracta_i + s_fractb_i;
endmodule // fpu_addsub
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_2_V
`define SKY130_FD_SC_LP__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_SYMBOL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_SYMBOL_V
|
`default_nettype none
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [15:0] dout,
input wire [15:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn_from_memory,
input wire interrupt_request
);
reg interrupt_enable = 0;
wire interrupt = interrupt_request & interrupt_enable;
reg [4:0] dsp, dspN; // Data stack pointer
reg [15:0] st0, st0N; // Top of data stack
reg dstkW; // Data stack write
reg [12:0] pc, pcN; // Program Counter
wire [15:0] insn = interrupt ? 16'h4FFF : insn_from_memory; // Interrupt: Execute "Call 1FFE".
wire [12:0] pc_plus_1 = interrupt ? pc : pc + 13'd1; // Do not increment PC for interrupts to continue later at the same location.
wire fetch = pc[12] & ~interrupt; // Memory fetch data on pc[12] only valid if this is no interrupt entry.
reg rstkW; // Return stack write
wire [15:0] rstkD; // Return stack write value
reg notreboot = 0;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [15:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(16)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
always @*
begin
// Compute the new value of st0
casez ({fetch, insn[15:8]})
9'b1_???_?????: st0N = insn_from_memory; // Memory fetch
9'b0_1??_?????: st0N = { 1'b0, insn[14:0] }; // Literal
9'b0_000_?????: st0N = st0; // Jump
9'b0_010_?????: st0N = st0; // Call
9'b0_001_?????: st0N = st1; // Conditional jump
9'b0_011_?0000: st0N = st0; // TOS
9'b0_011_?0001: st0N = st1; // NOS
9'b0_011_?0010: st0N = st0 + st1; // +
9'b0_011_?0011: st0N = st0 & st1; // and
9'b0_011_?0100: st0N = st0 | st1; // or
9'b0_011_?0101: st0N = st0 ^ st1; // xor
9'b0_011_?0110: st0N = ~st0; // invert
9'b0_011_?0111: st0N = {16{(minus == 0)}}; // =
9'b0_011_?1000: st0N = {16{signedless}}; // <
9'b0_011_?1001: st0N = {st0[15], st0[15:1]}; // 1 arshift
9'b0_011_?1010: st0N = {st0[14:0], 1'b0}; // 1 lshift
9'b0_011_?1011: st0N = rst0; // r@
9'b0_011_?1100: st0N = minus[15:0]; // -
9'b0_011_?1101: st0N = io_din; // Read IO
9'b0_011_?1110: st0N = {11'b0, dsp}; // depth
9'b0_011_?1111: st0N = {16{(minus[16])}}; // u<
default: st0N = {16{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire func_dint = (insn[6:4] == 6);
wire func_eint = (insn[6:4] == 7);
wire is_alu = !fetch & (insn[15:13] == 3'b011);
assign mem_wr = notreboot & is_alu & func_write;
assign io_wr = notreboot & is_alu & func_iow;
assign io_rd = notreboot & is_alu & func_ior;
assign dout = st1;
wire eint = notreboot & is_alu & func_eint;
wire dint = notreboot & is_alu & func_dint;
wire interrupt_enableN = (interrupt_enable | eint) & ~dint;
// Value which could be written to return stack: Either return address in case of a call or TOS.
assign rstkD = (insn[13] == 1'b0) ? {2'b0, pc_plus_1, interrupt_enable} : st0;
always @*
begin
casez ({fetch, insn[15:13]}) // Calculate new data stack pointer
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01}; // Memory Fetch & Literal
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11}; // Conditional jump
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}}; // ALU
default: {dstkW, dspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({fetch, insn[15:13]}) // Calculate new return stack pointer
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11}; // Memory Fetch, triggered by high address bit set
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01}; // Call
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]}; // ALU
default: {rstkW, rspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
casez ({notreboot, fetch, insn[15:13], insn[7], |st0}) // New address for PC
7'b0_0_???_?_?: pcN = 0; // Boot: Start at address zero
7'b1_0_000_?_?,
7'b1_0_010_?_?,
7'b1_0_001_?_0: pcN = insn[12:0]; // Jumps & Calls: Destination address
7'b1_1_???_?_?,
7'b1_0_011_1_?: pcN = rst0[13:1]; // Memory Fetch & ALU+exit: Return
default: pcN = pc_plus_1; // Default: Increment PC to next opcode
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
notreboot <= 0;
{ pc, dsp, st0, interrupt_enable } <= 0;
end else begin
notreboot <= 1;
{ pc, dsp, st0, interrupt_enable} <= { pcN, dspN, st0N, interrupt_enableN };
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/29/2016 07:18:32 PM
// Design Name:
// Module Name: Priority_Encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Encoder (
input wire [31:0] d_in,
output wire [7:0] d_out
);
assign d_out = (d_in[31]==1'b1) ? 8'b00011111:
(d_in[30]==1'b1) ? 8'b00011110:
(d_in[29]==1'b1) ? 8'b00011101:
(d_in[28]==1'b1) ? 8'b00011100:
(d_in[27]==1'b1) ? 8'b00011011:
(d_in[26]==1'b1) ? 8'b00011010:
(d_in[25]==1'b1) ? 8'b00011001:
(d_in[24]==1'b1) ? 8'b00011000:
(d_in[23]==1'b1) ? 8'b00010111:
(d_in[22]==1'b1) ? 8'b00010110:
(d_in[21]==1'b1) ? 8'b00010101:
(d_in[20]==1'b1) ? 8'b00010100:
(d_in[19]==1'b1) ? 8'b00010011:
(d_in[18]==1'b1) ? 8'b00010010:
(d_in[17]==1'b1) ? 8'b00010001:
(d_in[16]==1'b1) ? 8'b00010000:
(d_in[15]==1'b1) ? 8'b00001111:
(d_in[14]==1'b1) ? 8'b00001110:
(d_in[13]==1'b1) ? 8'b00001101:
(d_in[12]==1'b1) ? 8'b00001100:
(d_in[11]==1'b1) ? 8'b00001011:
(d_in[10]==1'b1) ? 8'b00001010:
(d_in[9]==1'b1) ? 8'b00001001:
(d_in[8]==1'b1) ? 8'b00001000:
(d_in[7]==1'b1) ? 8'b00000111:
(d_in[6]==1'b1) ? 8'b00000110:
(d_in[5]==1'b1) ? 8'b00000101:
(d_in[4]==1'b1) ? 8'b00000100:
(d_in[3]==1'b1) ? 8'b00000011:
(d_in[2]==1'b1) ? 8'b00000010:
(d_in[1]==1'b1) ? 8'b00000001: 8'b00000000;
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input arb_sq_rdy,
input [3:0] sq_qid,
input [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
output sq_hcmd_ack,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
output pcie_sq_cmd_fifo_wr_en,
output [10:0] pcie_sq_cmd_fifo_wr_data,
input pcie_sq_cmd_fifo_full_n,
output pcie_sq_rx_tag_alloc,
output [7:0] pcie_sq_rx_alloc_tag,
output [6:4] pcie_sq_rx_tag_alloc_len,
input pcie_sq_rx_tag_full_n,
input pcie_sq_rx_fifo_full_n,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack
);
localparam LP_HCMD_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_HCMD_PCIE_SIZE = 10'h10;
localparam S_IDLE = 6'b000001;
localparam S_CMD_INFO = 6'b000010;
localparam S_CHECK_FIFO = 6'b000100;
localparam S_PCIE_MRD_REQ = 6'b001000;
localparam S_PCIE_MRD_ACK = 6'b010000;
localparam S_PCIE_MRD_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_sq_hcmd_ack;
reg r_hcmd_slot_alloc_en;
reg r_tx_mrd_req;
reg [2:0] r_hcmd_pcie_tag;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
reg r_hcmd_pcie_tag_update;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_sq_cmd_fifo_wr_en;
reg r_pcie_sq_rx_tag_alloc;
assign sq_hcmd_ack = r_sq_hcmd_ack;
assign hcmd_slot_alloc_en = r_hcmd_slot_alloc_en;
assign pcie_sq_cmd_fifo_wr_en = r_pcie_sq_cmd_fifo_wr_en;
assign pcie_sq_cmd_fifo_wr_data = {r_sq_qid, r_hcmd_slot_tag};
assign pcie_sq_rx_tag_alloc = r_pcie_sq_rx_tag_alloc;
assign pcie_sq_rx_alloc_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign pcie_sq_rx_tag_alloc_len = 3'b100;
assign tx_mrd_req = r_tx_mrd_req;
assign tx_mrd_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign tx_mrd_len = LP_HCMD_PCIE_SIZE;
assign tx_mrd_addr = r_hcmd_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(arb_sq_rdy == 1 && hcmd_slot_rdy == 1)
next_state <= S_CMD_INFO;
else
next_state <= S_IDLE;
end
S_CMD_INFO: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_cmd_fifo_full_n == 1 && pcie_sq_rx_tag_full_n == 1 && pcie_sq_rx_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_pcie_tag <= 0;
end
else begin
if(r_hcmd_pcie_tag_update == 1)
r_hcmd_pcie_tag <= r_hcmd_pcie_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_INFO: begin
r_sq_qid <= sq_qid;
r_hcmd_pcie_addr <= hcmd_pcie_addr;
r_hcmd_slot_tag <= hcmd_slot_tag;
end
S_CHECK_FIFO: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CMD_INFO: begin
r_sq_hcmd_ack <= 1;
r_hcmd_slot_alloc_en <= 1;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 1;
r_pcie_sq_rx_tag_alloc <= 1;
r_tx_mrd_req <= 1;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 1;
end
default: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
endcase
end
endmodule
|
module wb_intercon_tb;
localparam WB_ARB_NUM_MASTERS = 5;
reg wb_clk = 1'b1;
reg wb_mux_rst = 1'b1;
wire wb_mux_done;
reg wb_arb_rst = 1'b1;
wire wb_arb_done;
reg wb_upz_rst = 1'b1;
wire wb_upz_done;
vlog_tb_utils vlog_tb_utils0();
wb_mux_tb
wb_mux_tb0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_mux_rst),
.done (wb_mux_done));
wb_arbiter_tb
#(.NUM_MASTERS (WB_ARB_NUM_MASTERS))
wb_arbiter_tb0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_arb_rst),
.done (wb_arb_done));
wb_upsizer_tb wb_upz_tb
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_upz_rst),
.done (wb_upz_done));
always #5 wb_clk <= ~wb_clk;
task mux_test;
begin
$display("==Running wb_mux tests==");
#100 wb_mux_rst <= 0;
@(posedge wb_mux_done);
#100 $display("==wb_mux tests done==");
wb_mux_rst <= 1;
end
endtask
task arbiter_test;
begin
$display("==Running wb_arbiter tests==");
wb_arb_rst <= 0;
@(posedge wb_arb_done);
#100 $display("==wb_arbiter tests done==");
wb_arb_rst <= 1;
end
endtask
task upsizer_test;
begin
$display("==Running wb_upsizer tests==");
wb_upz_rst <= 0;
@(posedge wb_upz_done);
#100 $display("==wb_upsizer tests done==");
wb_upz_rst <= 1;
end
endtask
initial begin
mux_test;
arbiter_test;
upsizer_test;
#3 $finish;
end
endmodule // orpsoc_tb
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_BLACKBOX_V
`define SKY130_FD_SC_HS__AND2B_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_BLACKBOX_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$lut (
A,
Y
);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0])
);
end else if (WIDTH == 2) begin
LUT2 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1])
);
end else if (WIDTH == 3) begin
LUT3 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2])
);
end else if (WIDTH == 4) begin
LUT4 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2]),
.I3(A[3])
);
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`timescale 1ns/1ns
module riffa
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA",
parameter C_FPGA_NAME = "FPGA", // TODO: Give each channel a unique name
parameter C_FPGA_ID = 0,// A value from 0 to 255 uniquely identifying this RIFFA design
parameter C_DEPTH_PACKETS = 10)
(input CLK,
input RST_BUS,
output RST_OUT,
input DONE_TXC_RST,
input DONE_TXR_RST,
// Interface: RXC Engine
input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
input RXC_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
input RXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
input RXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
input [`SIG_LBE_W-1:0] RXC_META_LDWBE,
input [`SIG_FBE_W-1:0] RXC_META_FDWBE,
input [`SIG_TAG_W-1:0] RXC_META_TAG,
input [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
input [`SIG_TYPE_W-1:0] RXC_META_TYPE,
input [`SIG_LEN_W-1:0] RXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
input [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
input RXC_META_EP,
// Interface: RXR Engine
input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
input RXR_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
input RXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
input RXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
input [`SIG_TC_W-1:0] RXR_META_TC,
input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
input [`SIG_TAG_W-1:0] RXR_META_TAG,
input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
input RXR_META_EP,
// Interface: TXC Engine
output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
output TXC_DATA_VALID,
output TXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
output TXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
input TXC_DATA_READY,
output TXC_META_VALID,
output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
output [`SIG_TAG_W-1:0] TXC_META_TAG,
output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
output [`SIG_TC_W-1:0] TXC_META_TC,
output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
output TXC_META_EP,
input TXC_META_READY,
input TXC_SENT,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
input CONFIG_BUS_MASTER_ENABLE,
input [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
input [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
input [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
input [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
input [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_INTERRUPT_MSIENABLE,
input CONFIG_CPL_BOUNDARY_SEL,
// Interrupt Request
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7; // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
localparam C_NUM_VECTORS = 2;
localparam C_VECTOR_WIDTH = 32;
// Interface: Reorder Buffer Output
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
wire [C_NUM_CHNL-1:0] wRxEngMainDone;
wire [C_NUM_CHNL-1:0] wRxEngMainErr;
// Interface: Reorder Buffer to SG RX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
// Interface: Reorder Buffer to SG TX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
// Interface: Channel TX Write
wire [C_NUM_CHNL-1:0] wTxEngWrReq;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngWrAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngWrLen;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
wire [C_NUM_CHNL-1:0] wTxEngWrAck;
wire [C_NUM_CHNL-1:0] wTxEngWrSent;
// Interface: Channel TX Read
wire [C_NUM_CHNL-1:0] wTxEngRdReq;
wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngRdAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngRdLen;
wire [C_NUM_CHNL-1:0] wTxEngRdAck;
// Interface: Channel Interrupts
wire [C_NUM_CHNL-1:0] wChnlSgRxBufRecvd;
wire [C_NUM_CHNL-1:0] wChnlRxDone;
wire [C_NUM_CHNL-1:0] wChnlTxRequest;
wire [C_NUM_CHNL-1:0] wChnlTxDone;
wire [C_NUM_CHNL-1:0] wChnlSgTxBufRecvd;
wire wInternalTagValid;
wire [5:0] wInternalTag;
wire wExternalTagValid;
wire [C_TAG_WIDTH-1:0] wExternalTag;
// Interface: Channel - PIO Read
wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] wChnlTxReqLen;
wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] wChnlTxOfflast;
wire wCoreSettingsReady;
wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
wire [C_NUM_VECTORS-1:0] wIntrVectorReady;
wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] wIntrVector;
wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] wChnlTxDoneLen;
wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] wChnlRxDoneLen;
wire wChnlNameReady;
// Interface: Channel - PIO Write
wire [31:0] wChnlReqData;
wire [C_NUM_CHNL-1:0] wChnlSgRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
// Interface: TXC Engine
wire [C_PCI_DATA_WIDTH-1:0] _wTxcData, wTxcData;
wire _wTxcDataValid, wTxcDataValid;
wire _wTxcDataStartFlag, wTxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataStartOffset, wTxcDataStartOffset;
wire _wTxcDataEndFlag, wTxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataEndOffset, wTxcDataEndOffset;
wire _wTxcDataReady, wTxcDataReady;
wire _wTxcMetaValid, wTxcMetaValid;
wire [`SIG_FBE_W-1:0] _wTxcMetaFdwbe, wTxcMetaFdwbe;
wire [`SIG_LBE_W-1:0] _wTxcMetaLdwbe, wTxcMetaLdwbe;
wire [`SIG_LOWADDR_W-1:0] _wTxcMetaAddr, wTxcMetaAddr;
wire [`SIG_TYPE_W-1:0] _wTxcMetaType, wTxcMetaType;
wire [`SIG_LEN_W-1:0] _wTxcMetaLength, wTxcMetaLength;
wire [`SIG_BYTECNT_W-1:0] _wTxcMetaByteCount, wTxcMetaByteCount;
wire [`SIG_TAG_W-1:0] _wTxcMetaTag, wTxcMetaTag;
wire [`SIG_REQID_W-1:0] _wTxcMetaRequesterId, wTxcMetaRequesterId;
wire [`SIG_TC_W-1:0] _wTxcMetaTc, wTxcMetaTc;
wire [`SIG_ATTR_W-1:0] _wTxcMetaAttr, wTxcMetaAttr;
wire _wTxcMetaEp, wTxcMetaEp;
wire _wTxcMetaReady, wTxcMetaReady;
wire wRxBufSpaceAvail;
wire wTxEngRdReqSent;
wire wRxEngRdComplete;
wire [31:0] wCPciDataWidth;
reg [31:0] wCFpgaId;
reg [4:0] rWideRst;
reg rRst;
genvar i;
assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
assign wCoreSettings = {1'd0, wCFpgaId, wCPciDataWidth[8:5],
CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE,
CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE,
C_NUM_CHNL[3:0]};
// Interface: TXC Engine
assign TXC_DATA = wTxcData;
assign TXC_DATA_START_FLAG = wTxcDataStartFlag;
assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
assign TXC_DATA_VALID = wTxcDataValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcDataReady = TXC_DATA_READY & ~wPendingRst & DONE_TXC_RST;
assign TXC_META_FDWBE = wTxcMetaFdwbe;
assign TXC_META_LDWBE = wTxcMetaLdwbe;
assign TXC_META_ADDR = wTxcMetaAddr;
assign TXC_META_TYPE = wTxcMetaType;
assign TXC_META_LENGTH = wTxcMetaLength;
assign TXC_META_BYTE_COUNT = wTxcMetaByteCount;
assign TXC_META_TAG = wTxcMetaTag;
assign TXC_META_REQUESTER_ID = wTxcMetaRequesterId;
assign TXC_META_TC = wTxcMetaTc;
assign TXC_META_ATTR = wTxcMetaAttr;
assign TXC_META_EP = wTxcMetaEp;
assign TXC_META_VALID = wTxcMetaValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcMetaReady = TXC_META_READY & ~wPendingRst & DONE_TXC_RST;
/* Workaround for a bug reported by the NetFPGA group, where the parameter
C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wCPciDataWidth = 32;
end else if (C_PCI_DATA_WIDTH == 64) begin
assign wCPciDataWidth = 64;
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wCPciDataWidth = 128;
end else if (C_PCI_DATA_WIDTH == 256) begin
assign wCPciDataWidth = 256;
end
always @(*) begin
wCFpgaId = 0;
if((C_FPGA_ID & 128) != 0) begin
wCFpgaId[7] = 1;
end else if ((C_FPGA_ID & 64) != 1) begin
wCFpgaId[6] = 1;
end else if ((C_FPGA_ID & 32) != 1) begin
wCFpgaId[5] = 1;
end else if ((C_FPGA_ID & 16) != 1) begin
wCFpgaId[4] = 1;
end else if ((C_FPGA_ID & 8) != 1) begin
wCFpgaId[3] = 1;
end else if ((C_FPGA_ID & 4) != 1) begin
wCFpgaId[2] = 1;
end else if ((C_FPGA_ID & 2) != 1) begin
wCFpgaId[1] = 1;
end else if ((C_FPGA_ID & 1) != 1) begin
wCFpgaId[0] = 1;
end
end
endgenerate
/* The purpose of these two hold modules is to safely reset the TX path and
still respond to the core status request (which causes a RIFFA reset). We
could wait until after the completion has been transmitted, but we have no
guarantee that the TX path is operating correctly until after we reset */
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (2 * `SIG_FBE_W + `SIG_LOWADDR_W +
`SIG_TYPE_W + `SIG_LEN_W +
`SIG_BYTECNT_W + `SIG_TAG_W +
`SIG_REQID_W + `SIG_TC_W +
`SIG_ATTR_W + 1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_meta_hold
(// Outputs
.WR_DATA_READY (_wTxcMetaReady), // NC
.RD_DATA ({wTxcMetaFdwbe, wTxcMetaLdwbe,
wTxcMetaAddr, wTxcMetaType,
wTxcMetaLength,
wTxcMetaByteCount, wTxcMetaTag,
wTxcMetaRequesterId, wTxcMetaTc,
wTxcMetaAttr, wTxcMetaEp}),
.RD_DATA_VALID (wTxcMetaValid),
// Inputs
.WR_DATA ({_wTxcMetaFdwbe, _wTxcMetaLdwbe,
_wTxcMetaAddr, _wTxcMetaType,
_wTxcMetaLength,
_wTxcMetaByteCount, _wTxcMetaTag,
_wTxcMetaRequesterId, _wTxcMetaTc,
_wTxcMetaAttr, _wTxcMetaEp}),
.WR_DATA_VALID (_wTxcMetaValid),
.RD_DATA_READY (wTxcMetaReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (C_PCI_DATA_WIDTH +
2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_data_hold
(// Outputs
.WR_DATA_READY (_wTxcDataReady), // NC
.RD_DATA ({wTxcData, wTxcDataStartFlag,
wTxcDataStartOffset, wTxcDataEndFlag,
wTxcDataEndOffset}),
.RD_DATA_VALID (wTxcDataValid),
// Inputs
.WR_DATA ({_wTxcData, _wTxcDataStartFlag,
_wTxcDataStartOffset, _wTxcDataEndFlag,
_wTxcDataEndOffset}),
.WR_DATA_VALID (_wTxcDataValid),
.RD_DATA_READY (wTxcDataReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
reset_extender
#(.C_RST_COUNT (8)
/*AUTOINSTPARAM*/)
reset_extender_inst
(// Outputs
.PENDING_RST (wPendingRst),
// Inputs
.RST_LOGIC (wCoreSettingsReady),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS));
reorder_queue
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH))
reorderQueue
(.RST (RST_OUT),
.VALID (RXC_DATA_VALID),
.DATA_START_FLAG (RXC_DATA_START_FLAG),
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (RXC_DATA_END_FLAG),
.DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (RXC_DATA),
.DATA_EN (RXC_DATA_WORD_ENABLE),
.DONE (wRxEngRdComplete),
.ERR (RXC_META_EP),
.TAG (RXC_META_TAG[C_TAG_WIDTH-1:0]),
.INT_TAG (wInternalTag),
.INT_TAG_VALID (wInternalTagValid),
.EXT_TAG (wExternalTag),
.EXT_TAG_VALID (wExternalTagValid),
.ENG_DATA (wRxEngData),
.MAIN_DATA_EN (wRxEngMainDataEn),
.MAIN_DONE (wRxEngMainDone),
.MAIN_ERR (wRxEngMainErr),
.SG_RX_DATA_EN (wRxEngSgRxDataEn),
.SG_RX_DONE (wRxEngSgRxDone),
.SG_RX_ERR (wRxEngSgRxErr),
.SG_TX_DATA_EN (wRxEngSgTxDataEn),
.SG_TX_DONE (wRxEngSgTxDone),
.SG_TX_ERR (wRxEngSgTxErr),
/*AUTOINST*/
// Inputs
.CLK (CLK));
registers
#(// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_NUM_VECTORS (C_NUM_VECTORS),
.C_VECTOR_WIDTH (C_VECTOR_WIDTH),
.C_FPGA_NAME (C_FPGA_NAME))
reg_inst
(// Outputs
// Write Interfaces
.CHNL_REQ_DATA (wChnlReqData[31:0]),
.CHNL_SGRX_LEN_VALID (wChnlSgRxLenValid),
.CHNL_SGRX_ADDRLO_VALID (wChnlSgRxAddrLoValid),
.CHNL_SGRX_ADDRHI_VALID (wChnlSgRxAddrHiValid),
.CHNL_SGTX_LEN_VALID (wChnlSgTxLenValid),
.CHNL_SGTX_ADDRLO_VALID (wChnlSgTxAddrLoValid),
.CHNL_SGTX_ADDRHI_VALID (wChnlSgTxAddrHiValid),
.CHNL_RX_LEN_VALID (wChnlRxLenValid),
.CHNL_RX_OFFLAST_VALID (wChnlRxOfflastValid),
// Read Interfaces
.CHNL_TX_LEN_READY (wChnlTxLenReady),
.CHNL_TX_OFFLAST_READY (wChnlTxOfflastReady),
.CORE_SETTINGS_READY (wCoreSettingsReady),
.INTR_VECTOR_READY (wIntrVectorReady),
.CHNL_TX_DONE_READY (wChnlTxDoneReady),
.CHNL_RX_DONE_READY (wChnlRxDoneReady),
.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
// TXC Engine Interface
.TXC_DATA_VALID (_wTxcDataValid),
.TXC_DATA (_wTxcData[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (_wTxcDataStartFlag),
.TXC_DATA_START_OFFSET (_wTxcDataStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (_wTxcDataEndFlag),
.TXC_DATA_END_OFFSET (_wTxcDataEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (_wTxcMetaValid),
.TXC_META_FDWBE (_wTxcMetaFdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (_wTxcMetaLdwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (_wTxcMetaAddr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (_wTxcMetaType[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (_wTxcMetaLength[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (_wTxcMetaByteCount[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (_wTxcMetaTag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (_wTxcMetaRequesterId[`SIG_REQID_W-1:0]),
.TXC_META_TC (_wTxcMetaTc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (_wTxcMetaAttr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (_wTxcMetaEp),
// Inputs
// Read Data
.CORE_SETTINGS (wCoreSettings),
.CHNL_TX_REQLEN (wChnlTxReqLen),
.CHNL_TX_OFFLAST (wChnlTxOfflast),
.CHNL_TX_DONELEN (wChnlTxDoneLen),
.CHNL_RX_DONELEN (wChnlRxDoneLen),
.INTR_VECTOR (wIntrVector),
.RST_IN (RST_OUT),
.TXC_DATA_READY (_wTxcDataReady),
.TXC_META_READY (_wTxcMetaReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]));
// Track receive buffer flow control credits (header & Data)
recv_credit_flow_ctrl rc_fc
(// Outputs
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
// Inputs
.RX_ENG_RD_DONE (wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
.RST (RST_OUT),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
// Connect the interrupt vector and controller.
interrupt
#(.C_NUM_CHNL (C_NUM_CHNL))
intr
(// Inputs
.RST (RST_OUT),
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
.RX_TXN_DONE (wChnlRxDone),
.TX_TXN (wChnlTxRequest),
.TX_SG_BUF_RECVD (wChnlSgTxBufRecvd),
.TX_TXN_DONE (wChnlTxDone),
.VECT_0_RST (wIntrVectorReady[0]),
.VECT_1_RST (wIntrVectorReady[1]),
.VECT_RST (_wTxcData[31:0]),
.VECT_0 (wIntrVector[31:0]),
.VECT_1 (wIntrVector[63:32]),
.INTR_LEGACY_CLR (1'd0),
/*AUTOINST*/
// Outputs
.INTR_MSI_REQUEST (INTR_MSI_REQUEST),
// Inputs
.CLK (CLK),
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY (INTR_MSI_RDY));
tx_multiplexer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
tx_mux_inst
(
// Outputs
.WR_DATA_REN (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
.WR_ACK (wTxEngWrAck[C_NUM_CHNL-1:0]),
.RD_ACK (wTxEngRdAck[C_NUM_CHNL-1:0]),
.INT_TAG (wInternalTag[5:0]),
.INT_TAG_VALID (wInternalTagValid),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
// Inputs
.RST_IN (RST_OUT),
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.WR_SENT (wTxEngWrSent[C_NUM_CHNL-1:0]),
.RD_REQ (wTxEngRdReq[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (wExternalTag[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (wExternalTagValid),
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
/*AUTOINST*/
// Outputs
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT));
// Generate and link up the channels.
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
channel
#(
.C_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(
.RST(RST_OUT),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.PIO_DATA(wChnlReqData),
.ENG_DATA(wRxEngData),
.SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
.SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
.TXN_TX(wChnlTxRequest[i]),
.TXN_TX_DONE(wChnlTxDone[i]),
.TXN_RX_DONE(wChnlRxDone[i]),
.SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
.SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
.SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
.SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
.SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
.SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
.TXN_RX_LEN_VALID(wChnlRxLenValid[i]),
.TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]),
.TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
.TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
.TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
.TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
.TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
.TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
.TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
.RX_REQ(wTxEngRdReq[i]),
.RX_REQ_ACK(wTxEngRdAck[i]),
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
.RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
.RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
.TX_REQ(wTxEngWrReq[i]),
.TX_REQ_ACK(wTxEngWrAck[i]),
.TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]),
.TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]),
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.TX_DATA_REN(wTxEngWrDataRen[i]),
.TX_SENT(wTxEngWrSent[i]),
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.MAIN_DONE(wRxEngMainDone[i]),
.MAIN_ERR(wRxEngMainErr[i]),
.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_RX_DONE(wRxEngSgRxDone[i]),
.SG_RX_ERR(wRxEngSgRxErr[i]),
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_TX_DONE(wRxEngSgTxDone[i]),
.SG_TX_ERR(wRxEngSgTxErr[i]),
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
.CHNL_RX(CHNL_RX[i]),
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
.CHNL_TX(CHNL_TX[i]),
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "import")
// End:
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
for (i = 16; i > 0; i--)
if (mem0[i] !== i) begin
$write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i);
status = 1;
end
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Default depth for this memory model is 2048, do these when
//changing the depth.
//1)Set ARRAY_DEPTH generic/parameter from 2048 to new depth.
//2)Change mem_array depth from 2047 to (new depth - 1).
//3)VHDL only, don't forget the generic in component declaration
module ddr3_s4_amphy_mem_model_ram_module (
// inputs:
data,
rdaddress,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
parameter ARRAY_DEPTH = 2048;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 24: 0] rdaddress;
input [ 24: 0] wraddress;
input wrclock;
input wren;
wire [ 15: 0] aq;
reg [ 41: 0] mem_array [2047: 0];
wire [ 15: 0] q;
assign aq = mem_array[0][15:0];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [ 16 - 1: 0] out;
integer i;
reg found_valid_data;
reg data_written;
initial
begin
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
mem_array[i][0] <= 1'b0;
data_written <= 1'b0;
end
always @(rdaddress)
begin
found_valid_data <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (rdaddress == mem_array[i][42 - 1:42 - 25] && mem_array[i][0])
begin
out = mem_array[i][42 - 25 - 1:42 - 25 - 16];
found_valid_data = 1'b1;
end
end
if (!found_valid_data)
out = 16'dX;
end
always @(posedge wrclock)
if (wren)
begin
data_written <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (wraddress == mem_array[i][42 - 1:42 - 25] && !data_written)
begin
mem_array[i][42 - 25 - 1:42 - 25 - 16] <= data;
mem_array[i][0] <= 1'b1;
data_written = 1'b1;
end
else if (!mem_array[i][0] && !data_written)
begin
mem_array[i] <= {wraddress,data,1'b1};
data_written = 1'b1;
end
end
if (!data_written)
begin
$write($time);
$write(" --- Data could not be written, increase array depth or use full memory model --- ");
$stop;
end
end
assign q = out;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_amphy_mem_model (
// inputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_rst_n,
mem_we_n,
// outputs:
global_reset_n,
mem_dq,
mem_dqs,
mem_dqs_n
)
;
output global_reset_n;
inout [ 7: 0] mem_dq;
inout mem_dqs;
inout mem_dqs_n;
input [ 12: 0] mem_addr;
input [ 2: 0] mem_ba;
input mem_cas_n;
input mem_cke;
input mem_clk;
input mem_clk_n;
input mem_cs_n;
input mem_dm;
input mem_odt;
input mem_ras_n;
input mem_rst_n;
input mem_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
reg [ 3: 0] additive_latency;
wire [ 8: 0] addr_col;
wire [ 2: 0] ba;
reg [ 2: 0] burstlength;
reg burstmode;
wire cas_n;
wire cke;
wire clk;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 2: 0] current_row;
wire dm;
reg [ 1: 0] dm_captured;
reg [ 15: 0] dq_captured;
wire [ 7: 0] dq_temp;
wire dq_valid;
wire dqs_n_temp;
wire dqs_temp;
wire dqs_valid;
reg dqs_valid_temp;
reg [ 7: 0] first_half_dq;
wire global_reset_n;
wire [ 15: 0] mem_bytes;
wire [ 7: 0] mem_dq;
wire mem_dqs;
wire mem_dqs_n;
reg [ 12: 0] open_rows [ 7: 0];
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_10;
reg [ 24: 0] rd_addr_pipe_11;
reg [ 24: 0] rd_addr_pipe_12;
reg [ 24: 0] rd_addr_pipe_13;
reg [ 24: 0] rd_addr_pipe_14;
reg [ 24: 0] rd_addr_pipe_15;
reg [ 24: 0] rd_addr_pipe_16;
reg [ 24: 0] rd_addr_pipe_17;
reg [ 24: 0] rd_addr_pipe_18;
reg [ 24: 0] rd_addr_pipe_19;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 24: 0] rd_addr_pipe_20;
reg [ 24: 0] rd_addr_pipe_21;
reg [ 24: 0] rd_addr_pipe_3;
reg [ 24: 0] rd_addr_pipe_4;
reg [ 24: 0] rd_addr_pipe_5;
reg [ 24: 0] rd_addr_pipe_6;
reg [ 24: 0] rd_addr_pipe_7;
reg [ 24: 0] rd_addr_pipe_8;
reg [ 24: 0] rd_addr_pipe_9;
reg [ 24: 0] rd_burst_counter;
reg [ 25: 0] rd_valid_pipe;
wire [ 24: 0] read_addr_delayed;
reg read_cmd;
reg read_cmd_echo;
wire [ 15: 0] read_data;
wire [ 7: 0] read_dq;
reg [ 4: 0] read_latency;
wire read_valid;
reg read_valid_r;
reg read_valid_r2;
reg read_valid_r3;
reg read_valid_r4;
reg reset_n;
wire [ 24: 0] rmw_address;
reg [ 15: 0] rmw_temp;
reg [ 7: 0] second_half_dq;
reg [ 3: 0] tcl;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 24: 0] wr_addr_delayed;
reg [ 24: 0] wr_addr_delayed_r;
reg [ 24: 0] wr_addr_pipe_0;
reg [ 24: 0] wr_addr_pipe_1;
reg [ 24: 0] wr_addr_pipe_10;
reg [ 24: 0] wr_addr_pipe_11;
reg [ 24: 0] wr_addr_pipe_12;
reg [ 24: 0] wr_addr_pipe_13;
reg [ 24: 0] wr_addr_pipe_14;
reg [ 24: 0] wr_addr_pipe_15;
reg [ 24: 0] wr_addr_pipe_16;
reg [ 24: 0] wr_addr_pipe_17;
reg [ 24: 0] wr_addr_pipe_18;
reg [ 24: 0] wr_addr_pipe_2;
reg [ 24: 0] wr_addr_pipe_3;
reg [ 24: 0] wr_addr_pipe_4;
reg [ 24: 0] wr_addr_pipe_5;
reg [ 24: 0] wr_addr_pipe_6;
reg [ 24: 0] wr_addr_pipe_7;
reg [ 24: 0] wr_addr_pipe_8;
reg [ 24: 0] wr_addr_pipe_9;
reg [ 24: 0] wr_burst_counter;
reg [ 25: 0] wr_valid_pipe;
wire write_burst_length;
reg [ 25: 0] write_burst_length_pipe;
reg write_cmd;
reg write_cmd_echo;
reg [ 4: 0] write_latency;
wire write_to_ram;
reg write_to_ram_r;
wire write_valid;
reg write_valid_r;
reg write_valid_r2;
reg write_valid_r3;
reg [ 3: 0] wtcl;
initial
begin
$write("\n");
$write("**********************************************************************\n");
$write("This testbench includes a generated Altera memory model:\n");
$write("'ddr3_s4_amphy_mem_model.v', to simulate accesses to the DDR3 SDRAM memory.\n");
$write(" \n");
$write("**********************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
ddr3_s4_amphy_mem_model_ram_module ddr3_s4_amphy_mem_model_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress (rmw_address),
.wraddress (wr_addr_delayed_r),
.wrclock (clk),
.wren (write_to_ram_r)
);
assign clk = mem_clk;
assign dm = mem_dm;
assign cke = mem_cke;
assign cs_n = mem_cs_n;
assign ras_n = mem_ras_n;
assign cas_n = mem_cas_n;
assign we_n = mem_we_n;
assign ba = mem_ba;
assign a = mem_addr;
//generate a fake reset inside the memory model
assign global_reset_n = reset_n;
initial
begin
reset_n <= 0;
#100 reset_n <= 1;
end
assign cmd_code = (&cs_n) ? 3'b111 : {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 1];
assign current_row = {ba};
// Decode commands into their actions
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
write_cmd_echo <= 0;
read_cmd_echo <= 0;
end
else // No Activity if the clock is
if (cke)
begin
// Checks whether to echo read cmd
if (read_cmd_echo && !read_cmd)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b0;
end
else // This is a read command
if (cmd_code == 3'b101)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b1;
end
else
read_cmd <= 1'b0;
// Checks whether to echo write cmd
if (write_cmd_echo && !write_cmd)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b0;
end
else // This is a write command
if (cmd_code == 3'b100)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b1;
write_burst_length_pipe[0] <= a[12];
end
else
write_cmd <= 1'b0;
// This is an activate - store the chip/row/bank address in the same order as the DDR controller
if (cmd_code == 3'b011)
open_rows[current_row] <= a;
end
end
// Pipes are flushed here
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_1 <= 0;
wr_addr_pipe_2 <= 0;
wr_addr_pipe_3 <= 0;
wr_addr_pipe_4 <= 0;
wr_addr_pipe_5 <= 0;
wr_addr_pipe_6 <= 0;
wr_addr_pipe_7 <= 0;
wr_addr_pipe_8 <= 0;
wr_addr_pipe_9 <= 0;
wr_addr_pipe_10 <= 0;
wr_addr_pipe_11 <= 0;
wr_addr_pipe_12 <= 0;
wr_addr_pipe_13 <= 0;
wr_addr_pipe_14 <= 0;
wr_addr_pipe_15 <= 0;
wr_addr_pipe_16 <= 0;
wr_addr_pipe_17 <= 0;
wr_addr_pipe_18 <= 0;
rd_addr_pipe_1 <= 0;
rd_addr_pipe_2 <= 0;
rd_addr_pipe_3 <= 0;
rd_addr_pipe_4 <= 0;
rd_addr_pipe_5 <= 0;
rd_addr_pipe_6 <= 0;
rd_addr_pipe_7 <= 0;
rd_addr_pipe_8 <= 0;
rd_addr_pipe_9 <= 0;
rd_addr_pipe_10 <= 0;
rd_addr_pipe_11 <= 0;
rd_addr_pipe_12 <= 0;
rd_addr_pipe_13 <= 0;
rd_addr_pipe_14 <= 0;
rd_addr_pipe_15 <= 0;
rd_addr_pipe_16 <= 0;
rd_addr_pipe_17 <= 0;
rd_addr_pipe_18 <= 0;
rd_addr_pipe_19 <= 0;
rd_addr_pipe_20 <= 0;
rd_addr_pipe_21 <= 0;
end
else // No Activity if the clock is
if (cke)
begin
rd_addr_pipe_21 <= rd_addr_pipe_20;
rd_addr_pipe_20 <= rd_addr_pipe_19;
rd_addr_pipe_19 <= rd_addr_pipe_18;
rd_addr_pipe_18 <= rd_addr_pipe_17;
rd_addr_pipe_17 <= rd_addr_pipe_16;
rd_addr_pipe_16 <= rd_addr_pipe_15;
rd_addr_pipe_15 <= rd_addr_pipe_14;
rd_addr_pipe_14 <= rd_addr_pipe_13;
rd_addr_pipe_13 <= rd_addr_pipe_12;
rd_addr_pipe_12 <= rd_addr_pipe_11;
rd_addr_pipe_11 <= rd_addr_pipe_10;
rd_addr_pipe_10 <= rd_addr_pipe_9;
rd_addr_pipe_9 <= rd_addr_pipe_8;
rd_addr_pipe_8 <= rd_addr_pipe_7;
rd_addr_pipe_7 <= rd_addr_pipe_6;
rd_addr_pipe_6 <= rd_addr_pipe_5;
rd_addr_pipe_5 <= rd_addr_pipe_4;
rd_addr_pipe_4 <= rd_addr_pipe_3;
rd_addr_pipe_3 <= rd_addr_pipe_2;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_valid_pipe[25 : 1] <= rd_valid_pipe[24 : 0];
rd_valid_pipe[0] <= cmd_code == 3'b101;
wr_addr_pipe_18 <= wr_addr_pipe_17;
wr_addr_pipe_17 <= wr_addr_pipe_16;
wr_addr_pipe_16 <= wr_addr_pipe_15;
wr_addr_pipe_15 <= wr_addr_pipe_14;
wr_addr_pipe_14 <= wr_addr_pipe_13;
wr_addr_pipe_13 <= wr_addr_pipe_12;
wr_addr_pipe_12 <= wr_addr_pipe_11;
wr_addr_pipe_11 <= wr_addr_pipe_10;
wr_addr_pipe_10 <= wr_addr_pipe_9;
wr_addr_pipe_9 <= wr_addr_pipe_8;
wr_addr_pipe_8 <= wr_addr_pipe_7;
wr_addr_pipe_7 <= wr_addr_pipe_6;
wr_addr_pipe_6 <= wr_addr_pipe_5;
wr_addr_pipe_5 <= wr_addr_pipe_4;
wr_addr_pipe_4 <= wr_addr_pipe_3;
wr_addr_pipe_3 <= wr_addr_pipe_2;
wr_addr_pipe_2 <= wr_addr_pipe_1;
wr_addr_pipe_1 <= wr_addr_pipe_0;
wr_valid_pipe[25 : 1] <= wr_valid_pipe[24 : 0];
wr_valid_pipe[0] <= cmd_code == 3'b100;
wr_addr_delayed_r <= wr_addr_delayed;
write_burst_length_pipe[25 : 1] <= write_burst_length_pipe[24 : 0];
end
end
// Decode CAS Latency from bits a[6:4]
always @(posedge clk)
begin
// No Activity if the clock is disabled
if (cke)
//Load mode register - set CAS latency, burst mode and length
if (cmd_code == 3'b000 && ba == 2'b00)
begin
burstmode <= a[3];
burstlength <= a[2 : 0] << 1;
//CAS Latency = 5
if (a[6 : 4] == 3'b001)
tcl <= 4'b0100;
else //CAS Latency = 6
if (a[6 : 4] == 3'b010)
tcl <= 4'b0101;
else //CAS Latency = 7
if (a[6 : 4] == 3'b011)
tcl <= 4'b0110;
else //CAS Latency = 8
if (a[6 : 4] == 3'b100)
tcl <= 4'b0111;
else //CAS Latency = 9
if (a[6 : 4] == 3'b101)
tcl <= 4'b1000;
else
tcl <= 4'b1001;
end
else //Get additive latency
if (cmd_code == 3'b000 && ba == 2'b01)
additive_latency <= {2'b00,a[4 : 3]};
else //Get write latency
if (cmd_code == 3'b000 && ba == 2'b10)
//CWL = 5
if (a[5 : 3] == 3'b000)
wtcl <= 4'b0101;
else //CWL = 6
if (a[5 : 3] == 3'b001)
wtcl <= 4'b0110;
else //CWL = 7
if (a[5 : 3] == 3'b010)
wtcl <= 4'b0111;
else //CWL = 8
if (a[5 : 3] == 3'b011)
wtcl <= 4'b1000;
end
//Calculate actual write and read latency
always @(additive_latency or tcl or wtcl)
begin
//no additive latency
if (additive_latency == 4'd0)
begin
read_latency = tcl;
write_latency = wtcl;
end
else //CL - 1
if (additive_latency == 4'd1)
begin
read_latency = tcl + (tcl + 1) - 1;
write_latency = wtcl + (tcl + 1) - 1;
end
else
begin
read_latency = tcl + (tcl + 1) - 2;
write_latency = wtcl + (tcl + 1) - 2;
end
end
// Burst support - make the wr_addr & rd_addr keep counting
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_0 <= 0;
rd_addr_pipe_0 <= 0;
end
else
begin
// Reset write address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
begin
wr_addr_pipe_0 <= 0;
wr_burst_counter <= 0;
end
else if (cmd_code == 3'b100)
begin
wr_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
wr_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
wr_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (write_cmd || write_to_ram || write_cmd_echo)
begin
wr_addr_pipe_0 <= wr_burst_counter;
wr_burst_counter[1 : 0] <= wr_burst_counter[1 : 0] + 1;
end
else
wr_addr_pipe_0 <= 0;
// Reset read address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
rd_addr_pipe_0 <= 0;
else if (cmd_code == 3'b101)
begin
rd_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
rd_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
rd_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (read_cmd || dq_valid || read_valid || read_cmd_echo)
begin
rd_addr_pipe_0 <= rd_burst_counter;
rd_burst_counter[1 : 0] <= rd_burst_counter[1 : 0] + 1;
end
else
rd_addr_pipe_0 <= 0;
end
end
// read data transition from single to double clock rate
always @(posedge clk)
begin
first_half_dq <= read_data[15 : 8];
second_half_dq <= read_data[7 : 0];
end
assign read_dq = clk ? second_half_dq : first_half_dq;
assign dq_temp = dq_valid ? read_dq : {8{1'bz}};
assign dqs_temp = dqs_valid ? {1{clk}} : {1{1'bz}};
assign dqs_n_temp = dqs_valid ? {1{~clk}} : {1{1'bz}};
assign mem_dqs = dqs_temp;
assign mem_dq = dq_temp;
assign mem_dqs_n = dqs_n_temp;
//Pipelining registers for burst counting
always @(posedge clk)
begin
write_valid_r <= write_valid;
read_valid_r <= read_valid;
write_valid_r2 <= write_valid_r;
write_valid_r3 <= write_valid_r2;
write_to_ram_r <= write_to_ram;
read_valid_r2 <= read_valid_r;
read_valid_r3 <= read_valid_r2;
read_valid_r4 <= read_valid_r3;
end
assign write_to_ram = write_burst_length ? write_valid || write_valid_r || write_valid_r2 || write_valid_r3 : write_valid || write_valid_r;
assign dq_valid = read_valid_r || read_valid_r2 || read_valid_r3 || read_valid_r4;
assign dqs_valid = dq_valid || dqs_valid_temp;
//
always @(negedge clk)
begin
dqs_valid_temp <= read_valid;
end
//capture first half of write data with rising edge of DQS, for simulation use only 1 DQS pin
always @(posedge mem_dqs)
begin
#0.1 dq_captured[7 : 0] <= mem_dq[7 : 0];
#0.1 dm_captured[0] <= mem_dm;
end
//capture second half of write data with falling edge of DQS, for simulation use only 1 DQS pin
always @(negedge mem_dqs)
begin
#0.1 dq_captured[15 : 8] <= mem_dq[7 : 0];
#0.1 dm_captured[1] <= mem_dm;
end
//Support for incomplete writes, do a read-modify-write with mem_bytes and the write data
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[7 : 0] <= dm_captured[0] ? mem_bytes[7 : 0] : dq_captured[7 : 0];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[15 : 8] <= dm_captured[1] ? mem_bytes[15 : 8] : dq_captured[15 : 8];
end
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives valid
assign write_valid = (write_latency == 0)? wr_valid_pipe[0] :
(write_latency == 1)? wr_valid_pipe[1] :
(write_latency == 2)? wr_valid_pipe[2] :
(write_latency == 3)? wr_valid_pipe[3] :
(write_latency == 4)? wr_valid_pipe[4] :
(write_latency == 5)? wr_valid_pipe[5] :
(write_latency == 6)? wr_valid_pipe[6] :
(write_latency == 7)? wr_valid_pipe[7] :
(write_latency == 8)? wr_valid_pipe[8] :
(write_latency == 9)? wr_valid_pipe[9] :
(write_latency == 10)? wr_valid_pipe[10] :
(write_latency == 11)? wr_valid_pipe[11] :
(write_latency == 12)? wr_valid_pipe[12] :
(write_latency == 13)? wr_valid_pipe[13] :
(write_latency == 14)? wr_valid_pipe[14] :
(write_latency == 15)? wr_valid_pipe[15] :
(write_latency == 16)? wr_valid_pipe[16] :
(write_latency == 17)? wr_valid_pipe[17] :
wr_valid_pipe[18];
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives addr
assign wr_addr_delayed = (write_latency == 0)? wr_addr_pipe_0 :
(write_latency == 1)? wr_addr_pipe_1 :
(write_latency == 2)? wr_addr_pipe_2 :
(write_latency == 3)? wr_addr_pipe_3 :
(write_latency == 4)? wr_addr_pipe_4 :
(write_latency == 5)? wr_addr_pipe_5 :
(write_latency == 6)? wr_addr_pipe_6 :
(write_latency == 7)? wr_addr_pipe_7 :
(write_latency == 8)? wr_addr_pipe_8 :
(write_latency == 9)? wr_addr_pipe_9 :
(write_latency == 10)? wr_addr_pipe_10 :
(write_latency == 11)? wr_addr_pipe_11 :
(write_latency == 12)? wr_addr_pipe_12 :
(write_latency == 13)? wr_addr_pipe_13 :
(write_latency == 14)? wr_addr_pipe_14 :
(write_latency == 15)? wr_addr_pipe_15 :
(write_latency == 16)? wr_addr_pipe_16 :
(write_latency == 17)? wr_addr_pipe_17 :
wr_addr_pipe_18;
//DDR3 has on the fly mode
assign write_burst_length = (write_latency == 0)? write_burst_length_pipe[0] :
(write_latency == 1)? write_burst_length_pipe[1] :
(write_latency == 2)? write_burst_length_pipe[2] :
(write_latency == 3)? write_burst_length_pipe[3] :
(write_latency == 4)? write_burst_length_pipe[4] :
(write_latency == 5)? write_burst_length_pipe[5] :
(write_latency == 6)? write_burst_length_pipe[6] :
(write_latency == 7)? write_burst_length_pipe[7] :
(write_latency == 8)? write_burst_length_pipe[8] :
(write_latency == 9)? write_burst_length_pipe[9] :
(write_latency == 10)? write_burst_length_pipe[10] :
(write_latency == 11)? write_burst_length_pipe[11] :
(write_latency == 12)? write_burst_length_pipe[12] :
(write_latency == 13)? write_burst_length_pipe[13] :
(write_latency == 14)? write_burst_length_pipe[14] :
(write_latency == 15)? write_burst_length_pipe[15] :
(write_latency == 16)? write_burst_length_pipe[16] :
(write_latency == 17)? write_burst_length_pipe[17] :
write_burst_length_pipe[18];
assign mem_bytes = (rmw_address == wr_addr_delayed_r && write_to_ram_r) ? rmw_temp : read_data;
assign rmw_address = (write_to_ram) ? wr_addr_delayed : read_addr_delayed;
//use read_latency to select which pipeline stage drives addr
assign read_addr_delayed = (read_latency == 0)? rd_addr_pipe_0 :
(read_latency == 1)? rd_addr_pipe_1 :
(read_latency == 2)? rd_addr_pipe_2 :
(read_latency == 3)? rd_addr_pipe_3 :
(read_latency == 4)? rd_addr_pipe_4 :
(read_latency == 5)? rd_addr_pipe_5 :
(read_latency == 6)? rd_addr_pipe_6 :
(read_latency == 7)? rd_addr_pipe_7 :
(read_latency == 8)? rd_addr_pipe_8 :
(read_latency == 9)? rd_addr_pipe_9 :
(read_latency == 10)? rd_addr_pipe_10 :
(read_latency == 11)? rd_addr_pipe_11 :
(read_latency == 12)? rd_addr_pipe_12 :
(read_latency == 13)? rd_addr_pipe_13 :
(read_latency == 14)? rd_addr_pipe_14 :
(read_latency == 15)? rd_addr_pipe_15 :
(read_latency == 16)? rd_addr_pipe_16 :
(read_latency == 17)? rd_addr_pipe_17 :
(read_latency == 18)? rd_addr_pipe_18 :
(read_latency == 19)? rd_addr_pipe_19 :
(read_latency == 20)? rd_addr_pipe_20 :
rd_addr_pipe_21;
//use read_latency to select which pipeline stage drives valid
assign read_valid = (read_latency == 0)? rd_valid_pipe[0] :
(read_latency == 1)? rd_valid_pipe[1] :
(read_latency == 2)? rd_valid_pipe[2] :
(read_latency == 3)? rd_valid_pipe[3] :
(read_latency == 4)? rd_valid_pipe[4] :
(read_latency == 5)? rd_valid_pipe[5] :
(read_latency == 6)? rd_valid_pipe[6] :
(read_latency == 7)? rd_valid_pipe[7] :
(read_latency == 8)? rd_valid_pipe[8] :
(read_latency == 9)? rd_valid_pipe[9] :
(read_latency == 10)? rd_valid_pipe[10] :
(read_latency == 11)? rd_valid_pipe[11] :
(read_latency == 12)? rd_valid_pipe[12] :
(read_latency == 13)? rd_valid_pipe[13] :
(read_latency == 14)? rd_valid_pipe[14] :
(read_latency == 15)? rd_valid_pipe[15] :
(read_latency == 16)? rd_valid_pipe[16] :
(read_latency == 17)? rd_valid_pipe[17] :
(read_latency == 18)? rd_valid_pipe[18] :
(read_latency == 19)? rd_valid_pipe[19] :
(read_latency == 20)? rd_valid_pipe[20] :
rd_valid_pipe[21];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v2_3_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v2_3_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v2_3_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:39 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_flash_0/system_axi_quad_spi_flash_0_stub.v
// Design : system_axi_quad_spi_flash_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_quad_spi,Vivado 2016.4" *)
module system_axi_quad_spi_flash_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
io1_o, io1_t, io2_i, io2_o, io2_t, io3_i, io3_o, io3_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
/* synthesis syn_black_box black_box_pad_pin="ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,io2_i,io2_o,io2_t,io3_i,io3_o,io3_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [6:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input io2_i;
output io2_o;
output io2_t;
input io3_i;
output io3_o;
output io3_t;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
output ip2intc_irpt;
endmodule
|
/**
* $Id: red_pitaya_top.v 1271 2014-02-25 12:32:34Z matej.oblak $
*
* @brief Red Pitaya TOP module. It connects external pins and PS part with
* other application modules.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Top module connects PS part with rest of Red Pitaya applications.
*
*
*
* /-------\
* PS DDR <------> | PS | AXI <-> custom bus
* PS MIO <------> | / | <------------+
* PS CLK -------> | ARM | |
* \-------/ |
* |
* |
* |
* /-------\ |
* -> | SCOPE | <---+
* | \-------/ |
* | |
* | |
* /--------\ | /-----\ |
* ADC ---> | | --+-> | | |
* | ANALOG | | PID | <----+
* DAC <--- | | <---- | | |
* \--------/ ^ \-----/ |
* | |
* | |
* | /-------\ |
* -- | ASG | <---+
* \-------/ |
* |
* |
* |
* /--------\ |
* RX ----> | | |
* SATA | DAISY | <-----------------+
* TX <---- | |
* \--------/
* | |
* | |
* (FREE)
*
*
*
*
* Inside analog module, ADC data is translated from unsigned neg-slope into
* two's complement. Similar is done on DAC data.
*
* Scope module stores data from ADC into RAM, arbitrary signal generator (ASG)
* sends data from RAM to DAC. MIMO PID uses ADC ADC as input and DAC as its output.
*
* Daisy chain connects with other boards with fast serial link. Data which is
* send and received is at the moment undefined. This is left for the user.
*
*/
module red_pitaya_top
(
// PS connections
`ifdef TOOL_AHEAD
inout [54-1: 0] processing_system7_0_MIO,
input processing_system7_0_PS_SRSTB_pin,
input processing_system7_0_PS_CLK_pin,
input processing_system7_0_PS_PORB_pin,
inout processing_system7_0_DDR_Clk,
inout processing_system7_0_DDR_Clk_n,
inout processing_system7_0_DDR_CKE,
inout processing_system7_0_DDR_CS_n,
inout processing_system7_0_DDR_RAS_n,
inout processing_system7_0_DDR_CAS_n,
output processing_system7_0_DDR_WEB_pin,
inout [ 3-1: 0] processing_system7_0_DDR_BankAddr,
inout [15-1: 0] processing_system7_0_DDR_Addr,
inout processing_system7_0_DDR_ODT,
inout processing_system7_0_DDR_DRSTB,
inout [32-1: 0] processing_system7_0_DDR_DQ,
inout [ 4-1: 0] processing_system7_0_DDR_DM,
inout [ 4-1: 0] processing_system7_0_DDR_DQS,
inout [ 4-1: 0] processing_system7_0_DDR_DQS_n,
inout processing_system7_0_DDR_VRN,
inout processing_system7_0_DDR_VRP,
`endif
`ifdef TOOL_VIVADO
inout [54-1: 0] FIXED_IO_mio ,
inout FIXED_IO_ps_clk ,
inout FIXED_IO_ps_porb ,
inout FIXED_IO_ps_srstb ,
inout FIXED_IO_ddr_vrn ,
inout FIXED_IO_ddr_vrp ,
inout [15-1: 0] DDR_addr ,
inout [ 3-1: 0] DDR_ba ,
inout DDR_cas_n ,
inout DDR_ck_n ,
inout DDR_ck_p ,
inout DDR_cke ,
inout DDR_cs_n ,
inout [ 4-1: 0] DDR_dm ,
inout [32-1: 0] DDR_dq ,
inout [ 4-1: 0] DDR_dqs_n ,
inout [ 4-1: 0] DDR_dqs_p ,
inout DDR_odt ,
inout DDR_ras_n ,
inout DDR_reset_n ,
inout DDR_we_n ,
`endif
// Red Pitaya periphery
// ADC
input [14-1: 0] adc_dat_a_i , // ADC CH1
input [14-1: 0] adc_dat_b_i , // ADC CH2
input adc_clk_p_i , // ADC data clock
input adc_clk_n_i , // ADC data clock
output adc_enc_p_o , // optional ADC clock source
output adc_enc_n_o , // optional ADC clock source
output adc_csn_o , // ADC clock duty cycle stabilizer
// DAC
output [14-1: 0] dac_dat_o , // DAC combined data
output dac_wrt_o , // DAC write
output dac_sel_o , // DAC channel select
output dac_clk_o , // DAC clock
output dac_rst_o , // DAC reset
// PWM DAC
output [ 4-1: 0] dac_pwm_o , // serial PWM DAC
// XADC
input Vp_Vn_v_p ,
input Vp_Vn_v_n ,
input Vaux0_v_p ,
input Vaux0_v_n ,
input Vaux1_v_p ,
input Vaux1_v_n ,
input Vaux8_v_p ,
input Vaux8_v_n ,
input Vaux9_v_p ,
input Vaux9_v_n ,
// Expansion connector
inout [ 8-1: 0] exp_p_tri_io ,
inout [ 8-1: 0] exp_n_tri_io ,
// SATA connector
output [ 2-1: 0] daisy_p_o , // line 1 is clock capable
output [ 2-1: 0] daisy_n_o ,
input [ 2-1: 0] daisy_p_i , // line 1 is clock capable
input [ 2-1: 0] daisy_n_i ,
// LED
output [ 8-1: 0] led_o
);
wire [ 5-1: 0] vinp_i = {Vp_Vn_v_p, Vaux9_v_p, Vaux8_v_p, Vaux1_v_p, Vaux0_v_p};
wire [ 5-1: 0] vinn_i = {Vp_Vn_v_n, Vaux9_v_n, Vaux8_v_n, Vaux1_v_n, Vaux0_v_n};
//---------------------------------------------------------------------------------
//
// Connections to PS
wire [ 4-1: 0] fclk ; //[0]-125MHz, [1]-250MHz, [2]-50MHz, [3]-200MHz
wire [ 4-1: 0] frstn ;
wire ps_sys_clk ;
wire ps_sys_rstn ;
wire [ 32-1: 0] ps_sys_addr ;
wire [ 32-1: 0] ps_sys_wdata ;
wire [ 4-1: 0] ps_sys_sel ;
wire ps_sys_wen ;
wire ps_sys_ren ;
wire [ 32-1: 0] ps_sys_rdata ;
wire ps_sys_err ;
wire ps_sys_ack ;
red_pitaya_ps i_ps
(
`ifdef TOOL_AHEAD
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
`endif
`ifdef TOOL_VIVADO
.FIXED_IO_mio ( FIXED_IO_mio ),
.FIXED_IO_ps_clk ( FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb ( FIXED_IO_ps_porb ),
.FIXED_IO_ps_srstb ( FIXED_IO_ps_srstb ),
.FIXED_IO_ddr_vrn ( FIXED_IO_ddr_vrn ),
.FIXED_IO_ddr_vrp ( FIXED_IO_ddr_vrp ),
.DDR_addr ( DDR_addr ),
.DDR_ba ( DDR_ba ),
.DDR_cas_n ( DDR_cas_n ),
.DDR_ck_n ( DDR_ck_n ),
.DDR_ck_p ( DDR_ck_p ),
.DDR_cke ( DDR_cke ),
.DDR_cs_n ( DDR_cs_n ),
.DDR_dm ( DDR_dm ),
.DDR_dq ( DDR_dq ),
.DDR_dqs_n ( DDR_dqs_n ),
.DDR_dqs_p ( DDR_dqs_p ),
.DDR_odt ( DDR_odt ),
.DDR_ras_n ( DDR_ras_n ),
.DDR_reset_n ( DDR_reset_n ),
.DDR_we_n ( DDR_we_n ),
`endif
.fclk_clk_o ( fclk ),
.fclk_rstn_o ( frstn ),
// system read/write channel
.sys_clk_o ( ps_sys_clk ), // system clock
.sys_rstn_o ( ps_sys_rstn ), // system reset - active low
.sys_addr_o ( ps_sys_addr ), // system read/write address
.sys_wdata_o ( ps_sys_wdata ), // system write data
.sys_sel_o ( ps_sys_sel ), // system write byte select
.sys_wen_o ( ps_sys_wen ), // system write enable
.sys_ren_o ( ps_sys_ren ), // system read enable
.sys_rdata_i ( ps_sys_rdata ), // system read data
.sys_err_i ( ps_sys_err ), // system error indicator
.sys_ack_i ( ps_sys_ack ), // system acknowledge signal
// SPI master
.spi_ss_o ( ), // select slave 0
.spi_ss1_o ( ), // select slave 1
.spi_ss2_o ( ), // select slave 2
.spi_sclk_o ( ), // serial clock
.spi_mosi_o ( ), // master out slave in
.spi_miso_i ( 1'b0 ), // master in slave out
// SPI slave
.spi_ss_i ( 1'b1 ), // slave selected
.spi_sclk_i ( 1'b0 ), // serial clock
.spi_mosi_i ( 1'b0 ), // master out slave in
.spi_miso_o ( ) // master in slave out
);
//---------------------------------------------------------------------------------
//
// Analog peripherials
// ADC clock duty cycle stabilizer is enabled
assign adc_csn_o = 1'b1 ;
// generating ADC clock is disabled
assign adc_enc_p_o = 1'b0;
assign adc_enc_n_o = 1'b1;
//ODDR i_adc_clk_p ( .Q(adc_enc_p_o), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_enc_n_o), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
wire ser_clk ;
wire adc_clk ;
reg adc_rstn ;
wire [ 14-1: 0] adc_a ;
wire [ 14-1: 0] adc_b ;
reg [ 14-1: 0] dac_a ;
reg [ 14-1: 0] dac_b ;
wire [ 24-1: 0] dac_pwm_a ;
wire [ 24-1: 0] dac_pwm_b ;
wire [ 24-1: 0] dac_pwm_c ;
wire [ 24-1: 0] dac_pwm_d ;
red_pitaya_analog i_analog
(
// ADC IC
.adc_dat_a_i ( adc_dat_a_i ), // CH 1
.adc_dat_b_i ( adc_dat_b_i ), // CH 2
.adc_clk_p_i ( adc_clk_p_i ), // data clock
.adc_clk_n_i ( adc_clk_n_i ), // data clock
// DAC IC
.dac_dat_o ( dac_dat_o ), // combined data
.dac_wrt_o ( dac_wrt_o ), // write enable
.dac_sel_o ( dac_sel_o ), // channel select
.dac_clk_o ( dac_clk_o ), // clock
.dac_rst_o ( dac_rst_o ), // reset
// PWM DAC
.dac_pwm_o ( dac_pwm_o ), // serial PWM DAC
// user interface
.adc_dat_a_o ( adc_a ), // ADC CH1
.adc_dat_b_o ( adc_b ), // ADC CH2
.adc_clk_o ( adc_clk ), // ADC received clock
.adc_rst_i ( adc_rstn ), // reset - active low
.ser_clk_o ( ser_clk ), // fast serial clock
.dac_dat_a_i ( dac_a ), // DAC CH1
.dac_dat_b_i ( dac_b ), // DAC CH2
.dac_pwm_a_i ( dac_pwm_a ), // slow DAC CH1
.dac_pwm_b_i ( dac_pwm_b ), // slow DAC CH2
.dac_pwm_c_i ( dac_pwm_c ), // slow DAC CH3
.dac_pwm_d_i ( dac_pwm_d ), // slow DAC CH4
.dac_pwm_sync_o ( ) // slow DAC sync
);
always @(posedge adc_clk) begin
adc_rstn <= frstn[0] ;
end
//---------------------------------------------------------------------------------
//
// system bus decoder & multiplexer
// it breaks memory addresses into 8 regions
wire sys_clk = ps_sys_clk ;
wire sys_rstn = ps_sys_rstn ;
wire [ 32-1: 0] sys_addr = ps_sys_addr ;
wire [ 32-1: 0] sys_wdata = ps_sys_wdata ;
wire [ 4-1: 0] sys_sel = ps_sys_sel ;
wire [ 8-1: 0] sys_wen ;
wire [ 8-1: 0] sys_ren ;
wire [(8*32)-1: 0] sys_rdata ;
wire [ (8*1)-1: 0] sys_err ;
wire [ (8*1)-1: 0] sys_ack ;
reg [ 8-1: 0] sys_cs ;
always @(sys_addr) begin
sys_cs = 8'h0 ;
case (sys_addr[22:20])
3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6, 3'h7 :
sys_cs[sys_addr[22:20]] = 1'b1 ;
endcase
end
assign sys_wen = sys_cs & {8{ps_sys_wen}} ;
assign sys_ren = sys_cs & {8{ps_sys_ren}} ;
assign ps_sys_rdata = {32{sys_cs[ 0]}} & sys_rdata[ 0*32+31: 0*32] |
{32{sys_cs[ 1]}} & sys_rdata[ 1*32+31: 1*32] |
{32{sys_cs[ 2]}} & sys_rdata[ 2*32+31: 2*32] |
{32{sys_cs[ 3]}} & sys_rdata[ 3*32+31: 3*32] |
{32{sys_cs[ 4]}} & sys_rdata[ 4*32+31: 4*32] |
{32{sys_cs[ 5]}} & sys_rdata[ 5*32+31: 5*32] |
{32{sys_cs[ 6]}} & sys_rdata[ 6*32+31: 6*32] |
{32{sys_cs[ 7]}} & sys_rdata[ 7*32+31: 7*32] ;
assign ps_sys_err = sys_cs[ 0] & sys_err[ 0] |
sys_cs[ 1] & sys_err[ 1] |
sys_cs[ 2] & sys_err[ 2] |
sys_cs[ 3] & sys_err[ 3] |
sys_cs[ 4] & sys_err[ 4] |
sys_cs[ 5] & sys_err[ 5] |
sys_cs[ 6] & sys_err[ 6] |
sys_cs[ 7] & sys_err[ 7] ;
assign ps_sys_ack = sys_cs[ 0] & sys_ack[ 0] |
sys_cs[ 1] & sys_ack[ 1] |
sys_cs[ 2] & sys_ack[ 2] |
sys_cs[ 3] & sys_ack[ 3] |
sys_cs[ 4] & sys_ack[ 4] |
sys_cs[ 5] & sys_ack[ 5] |
sys_cs[ 6] & sys_ack[ 6] |
sys_cs[ 7] & sys_ack[ 7] ;
assign sys_rdata[ 6*32+31: 6*32] = 32'h0;
assign sys_err[6] = {1{1'b0}} ;
assign sys_ack[6] = {1{1'b1}} ;
//---------------------------------------------------------------------------------
//
// House Keeping
wire [ 8-1: 0] exp_p_in ;
wire [ 8-1: 0] exp_p_out ;
wire [ 8-1: 0] exp_p_dir ;
wire [ 8-1: 0] exp_n_in ;
wire [ 8-1: 0] exp_n_out ;
wire [ 8-1: 0] exp_n_dir ;
red_pitaya_hk i_hk
(
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
// LED
.led_o ( led_o ), // LED output
// Expansion connector
.exp_p_dat_i ( exp_p_in ), // input data
.exp_p_dat_o ( exp_p_out ), // output data
.exp_p_dir_o ( exp_p_dir ), // 1-output enable
.exp_n_dat_i ( exp_n_in ),
.exp_n_dat_o ( exp_n_out ),
.exp_n_dir_o ( exp_n_dir ),
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[0] ), // write enable
.sys_ren_i ( sys_ren[0] ), // read enable
.sys_rdata_o ( sys_rdata[ 0*32+31: 0*32] ), // read data
.sys_err_o ( sys_err[0] ), // error indicator
.sys_ack_o ( sys_ack[0] ) // acknowledge signal
);
genvar GV ;
generate
for( GV = 0 ; GV < 8 ; GV = GV + 1)
begin : exp_iobuf
IOBUF i_iobufp (.O(exp_p_in[GV]), .IO(exp_p_tri_io[GV]), .I(exp_p_out[GV]), .T(!exp_p_dir[GV]) );
IOBUF i_iobufn (.O(exp_n_in[GV]), .IO(exp_n_tri_io[GV]), .I(exp_n_out[GV]), .T(!exp_n_dir[GV]) );
end
endgenerate
//---------------------------------------------------------------------------------
//
// Oscilloscope application
wire trig_asg_out ;
red_pitaya_scope i_scope
(
// ADC
.adc_a_i ( adc_a ), // CH 1
.adc_b_i ( adc_b ), // CH 2
.adc_clk_i ( adc_clk ), // clock
.adc_rstn_i ( adc_rstn ), // reset - active low
.trig_ext_i ( exp_p_in[0] ), // external trigger
.trig_asg_i ( trig_asg_out ), // ASG trigger
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[1] ), // write enable
.sys_ren_i ( sys_ren[1] ), // read enable
.sys_rdata_o ( sys_rdata[ 1*32+31: 1*32] ), // read data
.sys_err_o ( sys_err[1] ), // error indicator
.sys_ack_o ( sys_ack[1] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
//
// DAC arbitrary signal generator
wire [ 14-1: 0] asg_a ;
wire [ 14-1: 0] asg_b ;
red_pitaya_asg i_asg
(
// DAC
.dac_a_o ( asg_a ), // CH 1
.dac_b_o ( asg_b ), // CH 2
.dac_clk_i ( adc_clk ), // clock
.dac_rstn_i ( adc_rstn ), // reset - active low
.trig_a_i ( exp_p_in[0] ),
.trig_b_i ( exp_p_in[0] ),
.trig_out_o ( trig_asg_out ),
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[2] ), // write enable
.sys_ren_i ( sys_ren[2] ), // read enable
.sys_rdata_o ( sys_rdata[ 2*32+31: 2*32] ), // read data
.sys_err_o ( sys_err[2] ), // error indicator
.sys_ack_o ( sys_ack[2] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
//
// MIMO PID controller
wire [ 14-1: 0] pid_a ;
wire [ 14-1: 0] pid_b ;
red_pitaya_pid i_pid
(
// signals
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
.dat_a_i ( adc_a ), // in 1
.dat_b_i ( adc_b ), // in 2
.dat_a_o ( pid_a ), // out 1
.dat_b_o ( pid_b ), // out 2
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[3] ), // write enable
.sys_ren_i ( sys_ren[3] ), // read enable
.sys_rdata_o ( sys_rdata[ 3*32+31: 3*32] ), // read data
.sys_err_o ( sys_err[3] ), // error indicator
.sys_ack_o ( sys_ack[3] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Sumation of ASG and PID signal
// perform saturation before sending to DAC
wire [ 15-1: 0] dac_a_sum ;
wire [ 15-1: 0] dac_b_sum ;
assign dac_a_sum = $signed(asg_a) + $signed(pid_a);
assign dac_b_sum = $signed(asg_b) + $signed(pid_b);
always @(*) begin
if (dac_a_sum[15-1:15-2] == 2'b01) // pos. overflow
dac_a <= 14'h1FFF ;
else if (dac_a_sum[15-1:15-2] == 2'b10) // neg. overflow
dac_a <= 14'h2000 ;
else
dac_a <= dac_a_sum[14-1:0] ;
if (dac_b_sum[15-1:15-2] == 2'b01) // pos. overflow
dac_b <= 14'h1FFF ;
else if (dac_b_sum[15-1:15-2] == 2'b10) // neg. overflow
dac_b <= 14'h2000 ;
else
dac_b <= dac_b_sum[14-1:0] ;
end
//---------------------------------------------------------------------------------
//
// Analog mixed signals
// XADC and slow PWM DAC control
red_pitaya_ams i_ams
(
// power test
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
.vinp_i ( vinp_i ), // voltages p
.vinn_i ( vinn_i ), // voltages n
.dac_a_o ( dac_pwm_a ), // values used for
.dac_b_o ( dac_pwm_b ), // conversion into PWM signal
.dac_c_o ( dac_pwm_c ),
.dac_d_o ( dac_pwm_d ),
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[4] ), // write enable
.sys_ren_i ( sys_ren[4] ), // read enable
.sys_rdata_o ( sys_rdata[ 4*32+31: 4*32] ), // read data
.sys_err_o ( sys_err[4] ), // error indicator
.sys_ack_o ( sys_ack[4] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Daisy chain
// simple communication module
wire daisy_rx_rdy ;
wire dly_clk = fclk[3]; // 200MHz clock from PS - used for IDELAY (optionaly)
red_pitaya_daisy i_daisy
(
// SATA connector
.daisy_p_o ( daisy_p_o ), // line 1 is clock capable
.daisy_n_o ( daisy_n_o ),
.daisy_p_i ( daisy_p_i ), // line 1 is clock capable
.daisy_n_i ( daisy_n_i ),
// Data
.ser_clk_i ( ser_clk ), // high speed serial
.dly_clk_i ( dly_clk ), // delay clock
// TX
.par_clk_i ( adc_clk ), // data paralel clock
.par_rstn_i ( adc_rstn ), // reset - active low
.par_rdy_o ( daisy_rx_rdy ),
.par_dv_i ( daisy_rx_rdy ),
.par_dat_i ( 16'h1234 ),
// RX
.par_clk_o ( ),
.par_rstn_o ( ),
.par_dv_o ( ),
.par_dat_o ( ),
.debug_o (/*led_o*/ ),
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[5] ), // write enable
.sys_ren_i ( sys_ren[5] ), // read enable
.sys_rdata_o ( sys_rdata[ 5*32+31: 5*32] ), // read data
.sys_err_o ( sys_err[5] ), // error indicator
.sys_ack_o ( sys_ack[5] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Power consumtion test
red_pitaya_test i_test
(
// power test
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
.rand_o ( ),
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( sys_addr ), // address
.sys_wdata_i ( sys_wdata ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[7] ), // write enable
.sys_ren_i ( sys_ren[7] ), // read enable
.sys_rdata_o ( sys_rdata[ 7*32+31: 7*32] ), // read data
.sys_err_o ( sys_err[7] ), // error indicator
.sys_ack_o ( sys_ack[7] ) // acknowledge signal
);
//assign sys_rdata[ 7*32+31: 7*32] = 32'h0 ;
//assign sys_err[7] = 1'b0 ;
//assign sys_ack[7] = 1'b1 ;
endmodule
|
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module ${ARBITER_NAME} (
//control signals
input clk,
input rst,
//wishbone master ports
${PORTS}
//wishbone slave signals
output o_s_we,
output o_s_stb,
output o_s_cyc,
output [3:0] o_s_sel,
output [31:0] o_s_adr,
output [31:0] o_s_dat,
input [31:0] i_s_dat,
input i_s_ack,
input i_s_int
);
localparam MASTER_COUNT = ${NUM_MASTERS};
//registers/wires
//this should be parameterized
reg [7:0] master_select;
reg [7:0] priority_select;
wire o_master_we [MASTER_COUNT - 1:0];
wire o_master_stb [MASTER_COUNT - 1:0];
wire o_master_cyc [MASTER_COUNT - 1:0];
wire [3:0] o_master_sel [MASTER_COUNT - 1:0];
wire [31:0] o_master_adr [MASTER_COUNT - 1:0];
wire [31:0] o_master_dat [MASTER_COUNT - 1:0];
${MASTER_SELECT}
//priority select
${PRIORITY_SELECT}
//slave assignments
assign o_s_we = (master_select != MASTER_NO_SEL) ? o_master_we[master_select] : 0;
assign o_s_stb = (master_select != MASTER_NO_SEL) ? o_master_stb[master_select] : 0;
assign o_s_cyc = (master_select != MASTER_NO_SEL) ? o_master_cyc[master_select] : 0;
assign o_s_sel = (master_select != MASTER_NO_SEL) ? o_master_sel[master_select] : 0;
assign o_s_adr = (master_select != MASTER_NO_SEL) ? o_master_adr[master_select] : 0;
assign o_s_dat = (master_select != MASTER_NO_SEL) ? o_master_dat[master_select] : 0;
${WRITE}
${STROBE}
${CYCLE}
${SELECT}
${ADDRESS}
${DATA}
${ASSIGN}
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:01:13 04/02/2016
// Design Name:
// Module Name: ALU_1bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_1bit
(
// Input
input a_in,
input b_in,
input carry_in,
input b_invert,
input less,
input [1:0] op,
// Output
output wire result,
output wire carry_out
);
// Internal Variables
reg b_invert_out;
reg mux_out;
wire fa_01_out;
wire and_out;
wire or_out;
//submodule
full_adder fa_01 (
.x_in ( a_in ),
.y_in ( b_invert_out ),
.c_in ( carry_in ),
.s_out ( fa_01_out ),
.c_out ( carry_out )
); // Full_Adder
// b_Inverter
always @ ( b_invert or b_in )
begin : Binvert
if ( !b_invert )
b_invert_out = b_in; // b
else
b_invert_out = ~ b_in; // b'
end
// Logical_operation
assign and_out = a_in & b_invert_out;
assign or_out = a_in | b_invert_out;
assign result = mux_out;
// op_Selection
always @ ( op or and_out or or_out or less or fa_01_out )
begin : Operation
if ( op == 0 ) // AND
mux_out = and_out;
else if ( op == 1) // OR
mux_out = or_out;
else if ( op == 2) // ADD/SUB
mux_out = fa_01_out;
else // SLT
mux_out = less;
end
endmodule
|
/*
Steve,
I have small 8bit CPU working in Iverilog, it works if I
change a line similar to the one below in the test case to
assign result = (data[0] | data[1]) ? 1:0;
using the test case below I get,
elab_net.cc:1368: failed assertion `expr_sig->pin_count() == 1'
when compiling using the standard "verilog bug.v" (verilog-20000519)
This works fine in XL.
Regards
Gerard.
PS thanks for fixing the $monitor function. It works as XL,
as long as I pipe the output through uniq (./stimexe | uniq)
*/
module stim;
wire [1:0] data;
wire result;
assign result = data ? 1:0;
initial
$display("PASSED");
endmodule // stim
/*
* Copyright (c) 2000 Gerard A. Allan ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
|
(** * More Logic *)
Require Export "Prop".
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** *** *)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** *** *)
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** *** *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** *** *)
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** Here is another example of how to work with existentials. *)
Lemma exists_example_3 :
exists (n:nat), even n /\ beautiful n.
Proof.
(* WORKED IN CLASS *)
exists 8.
split.
unfold even. simpl. reflexivity.
apply b_sum with (n:=3) (m:=5).
apply b_3. apply b_5.
Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* FILL IN HERE *)
(*
*)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
*)
(** *** *)
(**
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** *** *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
(* WORKED IN CLASS *)
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
*)
(** *** *)
(**
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
(* FILL IN HERE *)
.
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
(* FILL IN HERE *) Admitted.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
(* FILL IN HERE *) Admitted.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
(* FILL IN HERE *)
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all (except from your study group partner, if
you have one).
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
(* FILL IN HERE *)
.
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(* FILL IN HERE *) Admitted.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
(* FILL IN HERE *) Admitted.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents
the labels assigned to a list of items: if there are more items
than labels, at least two items must have the same label. This
proof is much easier if you use the [excluded_middle] hypothesis
to show that [appears_in] is decidable, i.e. [forall x
l, (appears_in x l) \/ ~ (appears_in x l)]. However, it is also
possible to make the proof go through _without_ assuming that
[appears_in] is decidable; if you can manage to do this, you will
not need the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(* FILL IN HERE *)
(* $Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: reorder_queue_input.v
// Version: 1.00
// Verilog Standard: Verilog-2005
// Description: Input stage to the reorder-queue.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue_input
#(parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8,// Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5,// Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH)
(input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload data enable
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
output [C_NUM_TAGS-1:0] TAG_FINISH, // Bitmap of tags to finish
input [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] STORED_DATA_ADDR, // Address of stored packet data for RAMs
output [C_PCI_DATA_WIDTH-1:0] STORED_DATA, // Stored packet data for RAMs
output [C_PCI_DATA_WORD-1:0] STORED_DATA_EN, // Stored packet data enable for RAMs
output PKT_VALID, // Valid flag for packet data
output [C_TAG_WIDTH-1:0] PKT_TAG, // Tag for stored packet data
output [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of stored packet payload in DWs
output PKT_WORDS_LTE1, // True if total count of stored packet payload is <= 4 DWs
output PKT_WORDS_LTE2, // True if total count of stored packet payload is <= 8 DWs
output PKT_DONE, // Stored packet done flag
output PKT_ERR); // Stored packet error flag
wire [C_PCI_DATA_COUNT_WIDTH-1:0] wDECount;
wire [C_PCI_DATA_WORD-1:0] wDE;
wire [C_PCI_DATA_WIDTH-1:0] wData;
wire [C_PCI_DATA_WORD-1:0] wStartMask;
wire [C_PCI_DATA_WORD-1:0] wEndMask;
reg [5:0] rValid=0;
reg [(C_PCI_DATA_WIDTH*5)-1:0] rData=0;
reg [(C_PCI_DATA_WORD*3)-1:0] rDE=0;
reg [(C_PCI_DATA_COUNT_WIDTH*2)-1:0] rDECount=0;
reg [5:0] rDone=0;
reg [5:0] rErr=0;
reg [(C_TAG_WIDTH*6)-1:0] rTag=0;
reg [C_PCI_DATA_WORD-1:0] rDEShift=0;
reg [(C_PCI_DATA_WORD*2)-1:0] rDEShifted=0;
reg rCountValid=0;
reg [C_NUM_TAGS-1:0] rCountRst=0;
reg [C_NUM_TAGS-1:0] rValidCount=0;
reg rUseCurrCount=0;
reg rUsePrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rPrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rCount=0;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCount;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCountClr = wCount & {C_TAG_DW_COUNT_WIDTH{rCountValid}};
reg [(C_TAG_DW_COUNT_WIDTH*3)-1:0] rWords=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShift=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShifted=0;
reg rPosValid=0;
reg [C_NUM_TAGS-1:0] rPosRst=0;
reg [C_NUM_TAGS-1:0] rValidPos=0;
reg rUseCurrPos=0;
reg rUsePrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPosNow=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPos=0;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPos;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPosClr = wPos & {C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD{rPosValid}};
reg [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] rAddr=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftUp=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftDown=0;
reg [C_DATA_ADDR_WIDTH-1:0] rBaseAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataShifted=0;
reg rLTE1Pkt=0;
reg rLTE2Pkt=0;
reg [C_NUM_TAGS-1:0] rFinish=0;
wire [31:0] wZero=32'd0;
integer i;
assign wDE = DATA_EN >> (DATA_START_FLAG ? DATA_START_OFFSET : 0);/* TODO: Could move this to the RX Engine*/
assign wData = DATA >> (DATA_START_FLAG ? {DATA_START_OFFSET,5'b0} : 0);
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wDECount = VALID ? 1 : 0;
end
if(C_PCI_DATA_WIDTH == 64) begin
assign wDECount = VALID ? DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 128) begin
assign wDECount = VALID ? DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 256) begin
assign wDECount = VALID ? DATA_EN[7] + DATA_EN[6] + DATA_EN[5] + DATA_EN[4] +
DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
endgenerate
assign TAG_FINISH = rFinish;
assign STORED_DATA_ADDR = rAddr;
assign STORED_DATA = rDataShifted;
assign STORED_DATA_EN = rDEShifted[1*C_PCI_DATA_WORD +:C_PCI_DATA_WORD];
assign PKT_VALID = rValid[5];
assign PKT_TAG = rTag[5*C_TAG_WIDTH +:C_TAG_WIDTH];
assign PKT_WORDS = rWords[2*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH];
assign PKT_WORDS_LTE1 = rLTE1Pkt;
assign PKT_WORDS_LTE2 = rLTE2Pkt;
assign PKT_DONE = rDone[5];
assign PKT_ERR = rErr[5];
// Pipeline the input and intermediate data
always @ (posedge CLK) begin
if (RST) begin
rValid <= #1 0;
rTag <= #1 0;
end
else begin
rValid <= #1 (rValid<<1) | VALID;
rTag <= #1 (rTag<<C_TAG_WIDTH) | TAG;
end
rData <= #1 (rData<<C_PCI_DATA_WIDTH) | wData;
rDE <= #1 (rDE<<C_PCI_DATA_WORD) | wDE;//DATA_EN;
rDECount <= #1 (rDECount<<C_PCI_DATA_COUNT_WIDTH) | wDECount;//DATA_EN_COUNT;
rDone <= #1 (rDone<<1) | DONE;
rErr <= #1 (rErr<<1) | ERR;
rDEShifted <= #1 (rDEShifted<<C_PCI_DATA_WORD) | rDEShift;
rWords <= #1 (rWords<<C_TAG_DW_COUNT_WIDTH) | rCount;
rShifted <= #1 (rShifted<<C_PCI_DATA_WORD_WIDTH) | rShift;
end
// Input processing pipeline
always @ (posedge CLK) begin
// STAGE 0: Register the incoming data
// STAGE 1: Request existing count from RAM
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rCount value if the tags match.
rUseCurrCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[1*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[1]);
rUsePrevCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[2]);
rPrevCount <= #1 rCount;
// See if we need to reset the count
rCountValid <= #1 (RST ? 1'd0 : rCountRst>>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidCount <= #1 (RST ? 0 : rValid[0]<<rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 2: Calculate new count (saves next cycle)
if (rUseCurrCount) begin
rShift <= #1 rCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else if (rUsePrevCount) begin
rShift <= #1 rPrevCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rPrevCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else begin
rShift <= #1 wCountClr[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 wCountClr + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
// STAGE 3: Request existing positions from RAM
// Barrel shift the DE
rDEShift <= #1 (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]<<rShift) |
(rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]>>(C_PCI_DATA_WORD-rShift));
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rPos values if the tags match.
rUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);
rUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
end
// See if we need to reset the positions
rPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidPos <= #1 (RST ? 0 : rValid[2]<<rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 4: Calculate new positions (saves next cycle)
if (rUseCurrPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else if (rUsePrevPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
// Calculate the base address offset
rBaseAddr <= #1 rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH]<<C_DATA_ADDR_STRIDE_WIDTH;
// Calculate the shift amounts for barrel shifting payload data
rShiftUp <= #1 rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH]<<5;
rShiftDown <= #1 (C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0] - rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH])<<5;
// STAGE 5: Prepare to write data, final info
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rAddr[C_DATA_ADDR_WIDTH*i +:C_DATA_ADDR_WIDTH] <= #1
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rBaseAddr;
end
rDataShifted <= #1 (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]<<rShiftUp) |
(rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]>>rShiftDown);
rLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);
rLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));
rFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<<rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH];
// STAGE 6: Write data, final info
end
// Reset the count and positions when needed
always @ (posedge CLK) begin
if (RST) begin
rCountRst <= #1 0;
rPosRst <= #1 0;
end
else begin
rCountRst <= #1 (rCountRst | rValidCount) & ~TAG_CLEAR;
rPosRst <= #1 (rPosRst | rValidPos) & ~TAG_CLEAR;
end
end
// RAM for counts
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
countRam
(
.CLK(CLK),
.ADDRA(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[2]),
.DINA(rCount),
.ADDRB(rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wCount)
);
// RAM for positions
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_PCI_DATA_WORD*C_DATA_ADDR_STRIDE_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
posRam
(
.CLK(CLK),
.ADDRA(rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[4]),
.DINA(rPos),
.ADDRB(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wPos)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
module xilinx_dist_ram_16x32
(
data_out,
we,
data_in,
read_address,
write_address,
wclk
);
output [31:0] data_out;
input we, wclk;
input [31:0] data_in;
input [3:0] write_address, read_address;
wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V
/**
* srdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V |
/*
Steve,
I have small 8bit CPU working in Iverilog, it works if I
change a line similar to the one below in the test case to
assign result = (data[0] | data[1]) ? 1:0;
using the test case below I get,
elab_net.cc:1368: failed assertion `expr_sig->pin_count() == 1'
when compiling using the standard "verilog bug.v" (verilog-20000519)
This works fine in XL.
Regards
Gerard.
PS thanks for fixing the $monitor function. It works as XL,
as long as I pipe the output through uniq (./stimexe | uniq)
*/
module stim;
wire [1:0] data;
wire result;
assign result = data ? 1:0;
initial
$display("PASSED");
endmodule // stim
/*
* Copyright (c) 2000 Gerard A. Allan ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
|
module butterfly3_16(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
output signed [27:0] o_0 ;
output signed [27:0] o_1 ;
output signed [27:0] o_2 ;
output signed [27:0] o_3 ;
output signed [27:0] o_4 ;
output signed [27:0] o_5 ;
output signed [27:0] o_6 ;
output signed [27:0] o_7 ;
output signed [27:0] o_8 ;
output signed [27:0] o_9 ;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_15;
assign b_1=i_1+i_14;
assign b_2=i_2+i_13;
assign b_3=i_3+i_12;
assign b_4=i_4+i_11;
assign b_5=i_5+i_10;
assign b_6=i_6+i_9;
assign b_7=i_7+i_8;
assign b_8=i_7-i_8;
assign b_9=i_6-i_9;
assign b_10=i_5-i_10;
assign b_11=i_4-i_11;
assign b_12=i_3-i_12;
assign b_13=i_2-i_13;
assign b_14=i_1-i_14;
assign b_15=i_0-i_15;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] right;
reg [31:0] left;
reg [63:0] qright;
reg [63:0] qleft;
reg [31:0] amt;
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
qright = 64'hf784bf8f_12734089 >> amt;
qleft = 64'hf784bf8f_12734089 >> amt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
`endif
if (cyc==1) begin
amt <= 32'd0;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
amt <= 32'd28;
if (left != 32'h819b018a) $stop;
if (right != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
end
if (cyc==3) begin
amt <= 32'd31;
if (left != 32'ha0000000) $stop;
if (right != 32'h8) $stop;
if (qleft != 64'h0000000f784bf8f1) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
end
if (cyc==4) begin
amt <= 32'd32;
if (left != 32'h0) $stop;
if (right != 32'h1) $stop;
if (qleft != 64'h00000001ef097f1e) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
amt <= 32'd33;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h00000000f784bf8f) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
amt <= 32'd64;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h000000007bc25fc7) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
amt <= 32'd128;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC top for Altera de1 board ////
/// ////
/// Franck Jullien, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
module orpsoc_top #(
parameter rom0_aw = 6,
parameter uart0_aw = 3
)
(
input sys_clk_pad_i,
input rst_n_pad_i,
output [9:0] led_r_pad_o,
inout [7:0] gpio0_io,
`ifdef SIM
output tdo_pad_o,
input tms_pad_i,
input tck_pad_i,
input tdi_pad_i,
`endif
output [1:0] sdram_ba_pad_o,
output [11:0] sdram_a_pad_o,
output sdram_cs_n_pad_o,
output sdram_ras_pad_o,
output sdram_cas_pad_o,
output sdram_we_pad_o,
inout [15:0] sdram_dq_pad_io,
output [1:0] sdram_dqm_pad_o,
output sdram_cke_pad_o,
output sdram_clk_pad_o,
input uart0_srx_pad_i,
output uart0_stx_pad_o
);
parameter IDCODE_VALUE = 32'h14951185;
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation module
//
////////////////////////////////////////////////////////////////////////
wire async_rst;
wire wb_clk, wb_rst;
wire dbg_tck;
wire sdram_clk;
wire sdram_rst;
assign sdram_clk_pad_o = sdram_clk;
clkgen clkgen0 (
.sys_clk_pad_i (sys_clk_pad_i),
.rst_n_pad_i (rst_n_pad_i),
.async_rst_o (async_rst),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
`ifdef SIM
.tck_pad_i (tck_pad_i),
.dbg_tck_o (dbg_tck),
`endif
.sdram_clk_o (sdram_clk),
.sdram_rst_o (sdram_rst)
);
////////////////////////////////////////////////////////////////////////
//
// Modules interconnections
//
////////////////////////////////////////////////////////////////////////
`include "wb_intercon.vh"
`ifdef SIM
////////////////////////////////////////////////////////////////////////
//
// GENERIC JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
tap_top #(.IDCODE_VALUE(IDCODE_VALUE))
jtag_tap0 (
.tdo_pad_o (tdo_pad_o),
.tms_pad_i (tms_pad_i),
.tck_pad_i (dbg_tck),
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_o (jtag_tap_tdo),
.shift_dr_o (jtag_tap_shift_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.capture_dr_o (jtag_tap_capture_dr),
.extest_select_o (),
.sample_preload_select_o (),
.mbist_select_o (),
.debug_select_o (dbg_if_select),
.bs_chain_tdi_i (1'b0),
.mbist_tdi_i (1'b0),
.debug_tdi_i (dbg_if_tdo)
);
`else
////////////////////////////////////////////////////////////////////////
//
// ALTERA Virtual JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
altera_virtual_jtag jtag_tap0 (
.tck_o (dbg_tck),
.debug_tdo_i (dbg_if_tdo),
.tdi_o (jtag_tap_tdo),
.test_logic_reset_o (),
.run_test_idle_o (),
.shift_dr_o (jtag_tap_shift_dr),
.capture_dr_o (jtag_tap_capture_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.debug_select_o (dbg_if_select)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// OR1K CPU
//
////////////////////////////////////////////////////////////////////////
wire [31:0] or1k_irq;
wire [31:0] or1k_dbg_dat_i;
wire [31:0] or1k_dbg_adr_i;
wire or1k_dbg_we_i;
wire or1k_dbg_stb_i;
wire or1k_dbg_ack_o;
wire [31:0] or1k_dbg_dat_o;
wire or1k_dbg_stall_i;
wire or1k_dbg_ewt_i;
wire [3:0] or1k_dbg_lss_o;
wire [1:0] or1k_dbg_is_o;
wire [10:0] or1k_dbg_wp_o;
wire or1k_dbg_bp_o;
wire or1k_dbg_rst;
wire sig_tick;
wire or1k_rst;
assign or1k_rst = wb_rst | or1k_dbg_rst;
`ifdef OR1200_CPU
or1200_top #(.boot_adr(32'hf0000100))
or1200_top0 (
// Instruction bus, clocks, reset
.iwb_clk_i (wb_clk),
.iwb_rst_i (wb_rst),
.iwb_ack_i (wb_s2m_or1k_i_ack),
.iwb_err_i (wb_s2m_or1k_i_err),
.iwb_rty_i (wb_s2m_or1k_i_rty),
.iwb_dat_i (wb_s2m_or1k_i_dat),
.iwb_cyc_o (wb_m2s_or1k_i_cyc),
.iwb_adr_o (wb_m2s_or1k_i_adr),
.iwb_stb_o (wb_m2s_or1k_i_stb),
.iwb_we_o (wb_m2s_or1k_i_we),
.iwb_sel_o (wb_m2s_or1k_i_sel),
.iwb_dat_o (wb_m2s_or1k_i_dat),
.iwb_cti_o (wb_m2s_or1k_i_cti),
.iwb_bte_o (wb_m2s_or1k_i_bte),
// Data bus, clocks, reset
.dwb_clk_i (wb_clk),
.dwb_rst_i (wb_rst),
.dwb_ack_i (wb_s2m_or1k_d_ack),
.dwb_err_i (wb_s2m_or1k_d_err),
.dwb_rty_i (wb_s2m_or1k_d_rty),
.dwb_dat_i (wb_s2m_or1k_d_dat),
.dwb_cyc_o (wb_m2s_or1k_d_cyc),
.dwb_adr_o (wb_m2s_or1k_d_adr),
.dwb_stb_o (wb_m2s_or1k_d_stb),
.dwb_we_o (wb_m2s_or1k_d_we),
.dwb_sel_o (wb_m2s_or1k_d_sel),
.dwb_dat_o (wb_m2s_or1k_d_dat),
.dwb_cti_o (wb_m2s_or1k_d_cti),
.dwb_bte_o (wb_m2s_or1k_d_bte),
// Debug interface ports
.dbg_stall_i (or1k_dbg_stall_i),
.dbg_ewt_i (1'b0),
.dbg_lss_o (or1k_dbg_lss_o),
.dbg_is_o (or1k_dbg_is_o),
.dbg_wp_o (or1k_dbg_wp_o),
.dbg_bp_o (or1k_dbg_bp_o),
.dbg_adr_i (or1k_dbg_adr_i),
.dbg_we_i (or1k_dbg_we_i),
.dbg_stb_i (or1k_dbg_stb_i),
.dbg_dat_i (or1k_dbg_dat_i),
.dbg_dat_o (or1k_dbg_dat_o),
.dbg_ack_o (or1k_dbg_ack_o),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o (),
// Core clocks, resets
.clk_i (wb_clk),
.rst_i (or1k_rst),
.clmode_i (2'b00),
// Interrupts
.pic_ints_i (or1k_irq[30:0]),
.sig_tick (sig_tick),
.pm_cpustall_i (1'b0)
);
`else
mor1kx #(
.FEATURE_DEBUGUNIT ("ENABLED"),
.FEATURE_CMOV ("ENABLED"),
.FEATURE_INSTRUCTIONCACHE ("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH (5),
.OPTION_ICACHE_SET_WIDTH (3),
.OPTION_ICACHE_WAYS (2),
.OPTION_ICACHE_LIMIT_WIDTH (32),
.FEATURE_IMMU ("ENABLED"),
.FEATURE_DATACACHE ("ENABLED"),
.OPTION_DCACHE_BLOCK_WIDTH (5),
.OPTION_DCACHE_SET_WIDTH (3),
.OPTION_DCACHE_WAYS (2),
.OPTION_DCACHE_LIMIT_WIDTH (31),
.FEATURE_DMMU ("ENABLED"),
.OPTION_PIC_TRIGGER ("LATCHED_LEVEL"),
.IBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0 ("CAPPUCCINO"),
.OPTION_RESET_PC (32'hf0000100)
) mor1kx0 (
.iwbm_adr_o (wb_m2s_or1k_i_adr),
.iwbm_stb_o (wb_m2s_or1k_i_stb),
.iwbm_cyc_o (wb_m2s_or1k_i_cyc),
.iwbm_sel_o (wb_m2s_or1k_i_sel),
.iwbm_we_o (wb_m2s_or1k_i_we),
.iwbm_cti_o (wb_m2s_or1k_i_cti),
.iwbm_bte_o (wb_m2s_or1k_i_bte),
.iwbm_dat_o (wb_m2s_or1k_i_dat),
.dwbm_adr_o (wb_m2s_or1k_d_adr),
.dwbm_stb_o (wb_m2s_or1k_d_stb),
.dwbm_cyc_o (wb_m2s_or1k_d_cyc),
.dwbm_sel_o (wb_m2s_or1k_d_sel),
.dwbm_we_o (wb_m2s_or1k_d_we ),
.dwbm_cti_o (wb_m2s_or1k_d_cti),
.dwbm_bte_o (wb_m2s_or1k_d_bte),
.dwbm_dat_o (wb_m2s_or1k_d_dat),
.clk (wb_clk),
.rst (or1k_rst),
.iwbm_err_i (wb_s2m_or1k_i_err),
.iwbm_ack_i (wb_s2m_or1k_i_ack),
.iwbm_dat_i (wb_s2m_or1k_i_dat),
.iwbm_rty_i (wb_s2m_or1k_i_rty),
.dwbm_err_i (wb_s2m_or1k_d_err),
.dwbm_ack_i (wb_s2m_or1k_d_ack),
.dwbm_dat_i (wb_s2m_or1k_d_dat),
.dwbm_rty_i (wb_s2m_or1k_d_rty),
.irq_i (or1k_irq),
.du_addr_i (or1k_dbg_adr_i[15:0]),
.du_stb_i (or1k_dbg_stb_i),
.du_dat_i (or1k_dbg_dat_i),
.du_we_i (or1k_dbg_we_i),
.du_dat_o (or1k_dbg_dat_o),
.du_ack_o (or1k_dbg_ack_o),
.du_stall_i (or1k_dbg_stall_i),
.du_stall_o (or1k_dbg_bp_o)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// Debug Interface
//
////////////////////////////////////////////////////////////////////////
adbg_top dbg_if0 (
// OR1K interface
.cpu0_clk_i (wb_clk),
.cpu0_rst_o (or1k_dbg_rst),
.cpu0_addr_o (or1k_dbg_adr_i),
.cpu0_data_o (or1k_dbg_dat_i),
.cpu0_stb_o (or1k_dbg_stb_i),
.cpu0_we_o (or1k_dbg_we_i),
.cpu0_data_i (or1k_dbg_dat_o),
.cpu0_ack_i (or1k_dbg_ack_o),
.cpu0_stall_o (or1k_dbg_stall_i),
.cpu0_bp_i (or1k_dbg_bp_o),
// TAP interface
.tck_i (dbg_tck),
.tdi_i (jtag_tap_tdo),
.tdo_o (dbg_if_tdo),
.rst_i (wb_rst),
.capture_dr_i (jtag_tap_capture_dr),
.shift_dr_i (jtag_tap_shift_dr),
.pause_dr_i (jtag_tap_pause_dr),
.update_dr_i (jtag_tap_update_dr),
.debug_select_i (dbg_if_select),
// Wishbone debug master
.wb_clk_i (wb_clk),
.wb_dat_i (wb_s2m_dbg_dat),
.wb_ack_i (wb_s2m_dbg_ack),
.wb_err_i (wb_s2m_dbg_err),
.wb_adr_o (wb_m2s_dbg_adr),
.wb_dat_o (wb_m2s_dbg_dat),
.wb_cyc_o (wb_m2s_dbg_cyc),
.wb_stb_o (wb_m2s_dbg_stb),
.wb_sel_o (wb_m2s_dbg_sel),
.wb_we_o (wb_m2s_dbg_we),
.wb_cti_o (wb_m2s_dbg_cti),
.wb_bte_o (wb_m2s_dbg_bte)
);
////////////////////////////////////////////////////////////////////////
//
// ROM
//
////////////////////////////////////////////////////////////////////////
assign wb_s2m_rom0_err = 1'b0;
assign wb_s2m_rom0_rty = 1'b0;
`ifdef BOOTROM
rom #(.ADDR_WIDTH(rom0_aw))
rom0 (
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i (wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]),
.wb_cyc_i (wb_m2s_rom0_cyc),
.wb_stb_i (wb_m2s_rom0_stb),
.wb_cti_i (wb_m2s_rom0_cti),
.wb_bte_i (wb_m2s_rom0_bte),
.wb_dat_o (wb_s2m_rom0_dat),
.wb_ack_o (wb_s2m_rom0_ack)
);
`else
assign wb_s2m_rom0_dat_o = 0;
assign wb_s2m_rom0_ack_o = 0;
`endif
////////////////////////////////////////////////////////////////////////
//
// SDRAM Memory Controller
//
////////////////////////////////////////////////////////////////////////
wire [15:0] sdram_dq_i;
wire [15:0] sdram_dq_o;
wire sdram_dq_oe;
assign sdram_dq_i = sdram_dq_pad_io;
assign sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
assign sdram_clk_pad_o = sdram_clk;
assign wb_s2m_sdram_ibus_err = 0;
assign wb_s2m_sdram_ibus_rty = 0;
assign wb_s2m_sdram_dbus_err = 0;
assign wb_s2m_sdram_dbus_rty = 0;
wb_sdram_ctrl #(
`ifdef ICARUS_SIM
.TECHNOLOGY ("GENERIC"),
`else
.TECHNOLOGY ("ALTERA"),
`endif
.CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ
`ifdef SIM
.POWERUP_DELAY (1), // power up delay in us
`endif
.WB_PORTS (2), // Number of wishbone ports
.BUF_WIDTH (3),
.BURST_LENGTH (8),
.ROW_WIDTH (12), // Row width
.COL_WIDTH (8), // Column width
.BA_WIDTH (2), // Ba width
.tCAC (3), // CAS Latency
.tRAC (5), // RAS Latency
.tRP (3), // Command Period (PRE to ACT)
.tRC (7), // Command Period (REF to REF / ACT to ACT)
.tMRD (2) // Mode Register Set To Command Delay time
)
wb_sdram_ctrl0 (
// External SDRAM interface
.ba_pad_o (sdram_ba_pad_o[1:0]),
.a_pad_o (sdram_a_pad_o[11:0]),
.cs_n_pad_o (sdram_cs_n_pad_o),
.ras_pad_o (sdram_ras_pad_o),
.cas_pad_o (sdram_cas_pad_o),
.we_pad_o (sdram_we_pad_o),
.dq_i (sdram_dq_i[15:0]),
.dq_o (sdram_dq_o[15:0]),
.dqm_pad_o (sdram_dqm_pad_o[1:0]),
.dq_oe (sdram_dq_oe),
.cke_pad_o (sdram_cke_pad_o),
.sdram_clk (sdram_clk),
.sdram_rst (sdram_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i ({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
.wb_stb_i ({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
.wb_cyc_i ({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
.wb_cti_i ({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
.wb_bte_i ({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
.wb_we_i ({wb_m2s_sdram_ibus_we, wb_m2s_sdram_dbus_we }),
.wb_sel_i ({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
.wb_dat_i ({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
.wb_dat_o ({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
.wb_ack_o ({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
);
////////////////////////////////////////////////////////////////////////
//
// UART0
//
////////////////////////////////////////////////////////////////////////
wire uart0_irq;
wire [31:0] wb8_m2s_uart0_adr;
wire [1:0] wb8_m2s_uart0_bte;
wire [2:0] wb8_m2s_uart0_cti;
wire wb8_m2s_uart0_cyc;
wire [7:0] wb8_m2s_uart0_dat;
wire wb8_m2s_uart0_stb;
wire wb8_m2s_uart0_we;
wire [7:0] wb8_s2m_uart0_dat;
wire wb8_s2m_uart0_ack;
wire wb8_s2m_uart0_err;
wire wb8_s2m_uart0_rty;
assign wb8_s2m_uart0_err = 0;
assign wb8_s2m_uart0_rty = 0;
uart_top uart16550_0 (
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb8_m2s_uart0_adr[uart0_aw-1:0]),
.wb_dat_i (wb8_m2s_uart0_dat),
.wb_we_i (wb8_m2s_uart0_we),
.wb_stb_i (wb8_m2s_uart0_stb),
.wb_cyc_i (wb8_m2s_uart0_cyc),
.wb_sel_i (4'b0), // Not used in 8-bit mode
.wb_dat_o (wb8_s2m_uart0_dat),
.wb_ack_o (wb8_s2m_uart0_ack),
// Outputs
.int_o (uart0_irq),
.stx_pad_o (uart0_stx_pad_o),
.rts_pad_o (),
.dtr_pad_o (),
// Inputs
.srx_pad_i (uart0_srx_pad_i),
.cts_pad_i (1'b0),
.dsr_pad_i (1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i (1'b0)
);
// 32-bit to 8-bit wishbone bus resize
wb_data_resize wb_data_resize_uart0 (
// Wishbone Master interface
.wbm_adr_i (wb_m2s_uart0_adr),
.wbm_dat_i (wb_m2s_uart0_dat),
.wbm_sel_i (wb_m2s_uart0_sel),
.wbm_we_i (wb_m2s_uart0_we ),
.wbm_cyc_i (wb_m2s_uart0_cyc),
.wbm_stb_i (wb_m2s_uart0_stb),
.wbm_cti_i (wb_m2s_uart0_cti),
.wbm_bte_i (wb_m2s_uart0_bte),
.wbm_dat_o (wb_s2m_uart0_dat),
.wbm_ack_o (wb_s2m_uart0_ack),
.wbm_err_o (wb_s2m_uart0_err),
.wbm_rty_o (wb_s2m_uart0_rty),
// Wishbone Slave interface
.wbs_adr_o (wb8_m2s_uart0_adr),
.wbs_dat_o (wb8_m2s_uart0_dat),
.wbs_we_o (wb8_m2s_uart0_we ),
.wbs_cyc_o (wb8_m2s_uart0_cyc),
.wbs_stb_o (wb8_m2s_uart0_stb),
.wbs_cti_o (wb8_m2s_uart0_cti),
.wbs_bte_o (wb8_m2s_uart0_bte),
.wbs_dat_i (wb8_s2m_uart0_dat),
.wbs_ack_i (wb8_s2m_uart0_ack),
.wbs_err_i (wb8_s2m_uart0_err),
.wbs_rty_i (wb8_s2m_uart0_rty)
);
////////////////////////////////////////////////////////////////////////
//
// GPIO 0
//
////////////////////////////////////////////////////////////////////////
wire [7:0] gpio0_in;
wire [7:0] gpio0_out;
wire [7:0] gpio0_dir;
wire [31:0] wb8_m2s_gpio0_adr;
wire [1:0] wb8_m2s_gpio0_bte;
wire [2:0] wb8_m2s_gpio0_cti;
wire wb8_m2s_gpio0_cyc;
wire [7:0] wb8_m2s_gpio0_dat;
wire wb8_m2s_gpio0_stb;
wire wb8_m2s_gpio0_we;
wire [7:0] wb8_s2m_gpio0_dat;
wire wb8_s2m_gpio0_ack;
wire wb8_s2m_gpio0_err;
wire wb8_s2m_gpio0_rty;
// Tristate logic for IO
// 0 = input, 1 = output
genvar i;
generate
for (i = 0; i < 8; i = i+1) begin: gpio0_tris
assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz;
assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i];
end
endgenerate
gpio gpio0 (
// GPIO bus
.gpio_i (gpio0_in),
.gpio_o (gpio0_out),
.gpio_dir_o (gpio0_dir),
// Wishbone slave interface
.wb_adr_i (wb8_m2s_gpio0_adr[0]),
.wb_dat_i (wb8_m2s_gpio0_dat),
.wb_we_i (wb8_m2s_gpio0_we),
.wb_cyc_i (wb8_m2s_gpio0_cyc),
.wb_stb_i (wb8_m2s_gpio0_stb),
.wb_cti_i (wb8_m2s_gpio0_cti),
.wb_bte_i (wb8_m2s_gpio0_bte),
.wb_dat_o (wb8_s2m_gpio0_dat),
.wb_ack_o (wb8_s2m_gpio0_ack),
.wb_err_o (wb8_s2m_gpio0_err),
.wb_rty_o (wb8_s2m_gpio0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
// 32-bit to 8-bit wishbone bus resize
wb_data_resize wb_data_resize_gpio0 (
// Wishbone Master interface
.wbm_adr_i (wb_m2s_gpio0_adr),
.wbm_dat_i (wb_m2s_gpio0_dat),
.wbm_sel_i (wb_m2s_gpio0_sel),
.wbm_we_i (wb_m2s_gpio0_we ),
.wbm_cyc_i (wb_m2s_gpio0_cyc),
.wbm_stb_i (wb_m2s_gpio0_stb),
.wbm_cti_i (wb_m2s_gpio0_cti),
.wbm_bte_i (wb_m2s_gpio0_bte),
.wbm_dat_o (wb_s2m_gpio0_dat),
.wbm_ack_o (wb_s2m_gpio0_ack),
.wbm_err_o (wb_s2m_gpio0_err),
.wbm_rty_o (wb_s2m_gpio0_rty),
// Wishbone Slave interface
.wbs_adr_o (wb8_m2s_gpio0_adr),
.wbs_dat_o (wb8_m2s_gpio0_dat),
.wbs_we_o (wb8_m2s_gpio0_we ),
.wbs_cyc_o (wb8_m2s_gpio0_cyc),
.wbs_stb_o (wb8_m2s_gpio0_stb),
.wbs_cti_o (wb8_m2s_gpio0_cti),
.wbs_bte_o (wb8_m2s_gpio0_bte),
.wbs_dat_i (wb8_s2m_gpio0_dat),
.wbs_ack_i (wb8_s2m_gpio0_ack),
.wbs_err_i (wb8_s2m_gpio0_err),
.wbs_rty_i (wb8_s2m_gpio0_rty)
);
////////////////////////////////////////////////////////////////////////
//
// Interrupt assignment
//
////////////////////////////////////////////////////////////////////////
assign or1k_irq[0] = 0; // Non-maskable inside OR1K
assign or1k_irq[1] = 0; // Non-maskable inside OR1K
assign or1k_irq[2] = uart0_irq;
assign or1k_irq[3] = 0;
assign or1k_irq[4] = 0;
assign or1k_irq[5] = 0;
assign or1k_irq[6] = 0;
assign or1k_irq[7] = 0;
assign or1k_irq[8] = 0;
assign or1k_irq[9] = 0;
assign or1k_irq[10] = 0;
assign or1k_irq[11] = 0;
assign or1k_irq[12] = 0;
assign or1k_irq[13] = 0;
assign or1k_irq[14] = 0;
assign or1k_irq[15] = 0;
assign or1k_irq[16] = 0;
assign or1k_irq[17] = 0;
assign or1k_irq[18] = 0;
assign or1k_irq[19] = 0;
assign or1k_irq[20] = 0;
assign or1k_irq[21] = 0;
assign or1k_irq[22] = 0;
assign or1k_irq[23] = 0;
assign or1k_irq[24] = 0;
assign or1k_irq[25] = 0;
assign or1k_irq[26] = 0;
assign or1k_irq[27] = 0;
assign or1k_irq[28] = 0;
assign or1k_irq[29] = 0;
assign or1k_irq[30] = 0;
assign or1k_irq[31] = 0;
endmodule // orpsoc_top
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Storage Buffer ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : BUFRAM64C1.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse
// output order
// FILES: BUFRAM64C1.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x64C_1.v - dual ported synchronous RAM, contains:
// RAM64.v -single ported synchronous RAM
// PROPERTIES: 1)Has the volume of 2x64 complex data
// 2)Contains 2- port RAM and address counter
// 3)Has 64-clock cycle period starting with the START
// impulse and continuing forever
// 4)Signal RDY precedes the 1-st correct datum output
// from the buffer
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// Parameter file ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : fft64_config.inc
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
//input data bit width
//2-nd stage data bit width
//twiddle factor bit width
//when is absent then FFT, when is present then IFFT
//`define USFFT64paramifft
//buffer number 2 or 3
`define USFFT64parambuffers3
// buffer type: 1 ports in RAMS else -2 ports RAMS
// NOTE: will need to uncomment RAM64 module definition
//`define USFFT64bufferports1
//Coeficient 0.707 bit width is increased
`define USFFT64bitwidth_0707_high
module BUFRAM64C1_NB16 (CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI);
localparam local_nb = 16;
output RDY ;
reg RDY;
output [local_nb-1:0] DOR ;
wire [local_nb-1:0] DOR;
output [local_nb-1:0] DOI ;
wire [local_nb-1:0] DOI;
input CLK ;
wire CLK;
input RST ;
wire RST;
input ED ;
wire ED;
input START ;
wire START;
input [local_nb-1:0] DR ;
wire [local_nb-1:0] DR;
input [local_nb-1:0] DI ;
wire [local_nb-1:0] DI;
wire odd, we;
wire [5:0] addrw,addrr;
reg [6:0] addr;
reg [7:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=6'b000000;
ct2<= 7'b1000001;
RDY<=1'b0; end
else if (START) begin
addr<=6'b000000;
ct2<= 6'b000000;
RDY<=1'b0;end
else if (ED) begin
addr<=addr+1;
if (ct2!=65) begin
ct2<=ct2+1;
end
if (ct2==64) begin
RDY<=1'b1;
end else begin
RDY<=1'b0;
end
end
end
assign addrw= addr[5:0];
assign odd=addr[6]; // signal which switches the 2 parts of the buffer
assign addrr={addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address
assign we = ED;
RAM2x64C_1 URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
defparam URAM.nb = 16;
endmodule
module BUFRAM64C1_NB18 (CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI);
localparam local_nb = 18;
output RDY ;
reg RDY;
output [local_nb-1:0] DOR ;
wire [local_nb-1:0] DOR;
output [local_nb-1:0] DOI ;
wire [local_nb-1:0] DOI;
input CLK ;
wire CLK;
input RST ;
wire RST;
input ED ;
wire ED;
input START ;
wire START;
input [local_nb-1:0] DR ;
wire [local_nb-1:0] DR;
input [local_nb-1:0] DI ;
wire [local_nb-1:0] DI;
wire odd, we;
wire [5:0] addrw,addrr;
reg [6:0] addr;
reg [7:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=6'b000000;
ct2<= 7'b1000001;
RDY<=1'b0; end
else if (START) begin
addr<=6'b000000;
ct2<= 6'b000000;
RDY<=1'b0;end
else if (ED) begin
addr<=addr+1;
if (ct2!=65) begin
ct2<=ct2+1;
end
if (ct2==64) begin
RDY<=1'b1;
end else begin
RDY<=1'b0;
end
end
end
assign addrw= addr[5:0];
assign odd=addr[6]; // signal which switches the 2 parts of the buffer
assign addrr={addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address
assign we = ED;
RAM2x64C_1 URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
defparam URAM.nb = 18;
endmodule
module BUFRAM64C1_NB19 (CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI);
localparam local_nb = 19;
output RDY ;
reg RDY;
output [local_nb-1:0] DOR ;
wire [local_nb-1:0] DOR;
output [local_nb-1:0] DOI ;
wire [local_nb-1:0] DOI;
input CLK ;
wire CLK;
input RST ;
wire RST;
input ED ;
wire ED;
input START ;
wire START;
input [local_nb-1:0] DR ;
wire [local_nb-1:0] DR;
input [local_nb-1:0] DI ;
wire [local_nb-1:0] DI;
wire odd, we;
wire [5:0] addrw,addrr;
reg [6:0] addr;
reg [7:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=6'b000000;
ct2<= 7'b1000001;
RDY<=1'b0; end
else if (START) begin
addr<=6'b000000;
ct2<= 6'b000000;
RDY<=1'b0;end
else if (ED) begin
addr<=addr+1;
if (ct2!=65) begin
ct2<=ct2+1;
end
if (ct2==64) begin
RDY<=1'b1;
end else begin
RDY<=1'b0;
end
end
end
assign addrw= addr[5:0];
assign odd=addr[6]; // signal which switches the 2 parts of the buffer
assign addrr={addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address
assign we = ED;
RAM2x64C_1 URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
defparam URAM.nb = 19;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Normalization unit ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : CNORM.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: shifting left up to 3 bits
// PROPERTIES: 1)shifting left up to 3 bits controlled by
// the 2-bit code SHIFT
// 2)Is registered
// 3)Overflow detector detects the overflow event
// by the given shift condition. The detector is
// zeroed by the START signal
// 4)RDY is the START signal delayed to a single
// clock cycle
/////////////////////////////////////////////////////////////////////
module CNORM (CLK,
ED,
START,
DR,
DI,
SHIFT,
OVF,
RDY,
DOR,
DOI);
parameter nb=16;
output OVF ;
reg OVF;
output RDY ;
reg RDY;
output [nb+1:0] DOR ;
wire [nb+1:0] DOR;
output [nb+1:0] DOI ;
wire [nb+1:0] DOI;
input CLK ;
wire CLK;
input ED ;
wire ED;
input START ;
wire START;
input [nb+2:0] DR ;
wire [nb+2:0] DR;
input [nb+2:0] DI ;
wire [nb+2:0] DI;
input [1:0] SHIFT ;
wire [1:0] SHIFT;
reg [nb+2:0] diri,diii;
always @ (DR or SHIFT) begin
case (SHIFT)
2'h0: begin
diri = DR;
end
2'h1: begin
diri[(nb+2):1] = DR[(nb+2)-1:0];
diri[0:0] = 1'b0;
end
2'h2: begin
diri[(nb+2):2] = DR[(nb+2)-2:0];
diri[1:0] = 2'b00;
end
2'h3: begin
diri[(nb+2):3] = DR[(nb+2)-3:0];
diri[2:0] = 3'b000;
end
endcase
end
always @ (DI or SHIFT) begin
case (SHIFT)
2'h0: begin
diii = DI;
end
2'h1: begin
diii[(nb+2):1] = DI[(nb+2)-1:0];
diii[0:0] = 1'b0;
end
2'h2: begin
diii[(nb+2):2] = DI[(nb+2)-2:0];
diii[1:0] = 2'b00;
end
2'h3: begin
diii[(nb+2):3] = DI[(nb+2)-3:0];
diii[2:0] = 3'b000;
end
endcase
end
reg [nb+2:0] dir,dii;
always @( posedge CLK ) begin
if (ED) begin
dir<=diri[nb+2:1];
dii<=diii[nb+2:1];
end
end
always @( posedge CLK ) begin
if (ED) begin
RDY<=START;
if (START)
OVF<=0;
else
case (SHIFT)
2'b01 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]);
2'b10 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]) ||
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]);
2'b11 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1])||
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]) ||
(DR[nb+2] != DR[nb+1]) || (DI[nb-1] != DI[nb-1]);
endcase
end
end
assign DOR= dir;
assign DOI= dii;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// 8-point FFT, First stage of FFT 64 processor ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : FFT8.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: 8-point FFT
// FILES: FFT8.v - 1-st stage, contains
// MPU707.v - multiplier to the factor 0.707.
// PROPERTIES:1) Fully pipelined
// 2) Each clock cycle complex datum is entered
// and complex result is outputted
// 3) Has 8-clock cycle period starting with the START
// impulse and continuing forever
// 4) rounding is not used
// 5)Algorithm is from the book "H.J.Nussbaumer FFT and
// convolution algorithms".
// 6)IFFT is performed by substituting the output result
// order to the reversed one
// (by exchanging - to + and + to -)
/////////////////////////////////////////////////////////////////////
//Algorithm:
// procedure FFT8(
// D: in MEMOC8; -- input array
// DO:out MEMOC8) -- output ARRAY
// is
// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;
// variable s1,s2,s3,s4: complex;
// begin
// t1:=D(0) + D(4);
// m3:=D(0) - D(4);
// t2:=D(6) + D(2);
// m6:=CBASE_j*(D(6)-D(2));
// t3:=D(1) + D(5);
// t4:=D(1) - D(5);
// t5:=D(3) + D(7);
// t6:=D(3) - D(7);
// t8:=t5 + t3;
// m5:=CBASE_j*(t5-t3);
// t7:=t1 + t2;
// m2:=t1 - t2;
// m0:=t7 + t8;
// m1:=t7 - t8;
// m4:=SQRT(0.5)*(t4 - t6);
// m7:=-CBASE_j*SQRT(0.5)*(t4 + t6);
// s1:=m3 + m4;
// s2:=m3 - m4;
// s3:=m6 + m7;
// s4:=m6 - m7;
// DO(0):=m0;
// DO(4):=m1;
// DO(1):=s1 + s3;
// DO(7):=s1 - s3;
// DO(2):=m2 + m5;
// DO(6):=m2 - m5;
// DO(5):=s2 + s4;
// DO(3):=s2 - s4;
// end procedure;
/////////////////////////////////////////////////////////////////////
module FFT8 (CLK,
RST,
ED,
START,
DIR,
DII,
RDY,
DOR,
DOI);
parameter nb=16;
input ED ;
wire ED;
input RST ;
wire RST;
input CLK ;
wire CLK;
input [nb-1:0] DII ;
wire [nb-1:0] DII;
input START ;
wire START;
input [nb-1:0] DIR ;
wire [nb-1:0] DIR;
output [nb+2:0] DOI ;
wire [nb+2:0] DOI;
output [nb+2:0] DOR ;
wire [nb+2:0] DOR;
output RDY ;
reg RDY;
reg [2:0] ct; //main phase counter
reg [3:0] ctd; //delay counter
always @( posedge CLK) begin //Control counter
//
if (RST) begin
ct<=0;
ctd<=15;
RDY<=0; end
else if (START) begin
ct<=0;
ctd<=0;
RDY<=0; end
else if (ED) begin
ct<=ct+1;
if (ctd !=4'b1111)
ctd<=ctd+1;
if (ctd==12 ) begin
RDY<=1;
end else begin
RDY<=0;
end
end
end
reg [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;
always @(posedge CLK) // input register file
begin
if (ED) begin
dr<=DIR;
d1r<=dr;
d2r<=d1r;
d3r<=d2r;
d4r<=d3r;
di<=DII;
d1i<=di;
d2i<=d1i;
d3i<=d2i;
d4i<=d3i;
end
end
reg [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r;
reg [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i;
always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed
if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin
s1r<=d4r + dr ;
s1i<=d4i + di ;
s2r<=d4r - dr ;
s2i<= d4i - di;
end
if (ED) begin
s1d1r<=s1r;
s1d2r<=s1d1r;
s1d1i<=s1i;
s1d2i<=s1d1i;
if (ct==0 || ct==1) begin //## note for vhdl
s1d3r<=s1d2r;
s1d3i<=s1d2i;
end
if (ct==6 || ct==7 || ct==0) begin
s2d1r<=s2r;
s2d2r<=s2d1r;
s2d1i<=s2i;
s2d2i<=s2d1i;
end
if (ct==0) begin
s2d3r<=s2d2r;
s2d3i<=s2d2i;
end
end
end
reg [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r;
reg [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i;
always @(posedge CLK) begin //ALU S3:
if (ED)
case (ct)
0: begin s3r<= s1d2r+s1r; //t7
s3i<= s1d2i+ s1i ;end
1: begin s3r<= s1d3r - s1d1r; //m2
s3i<= s1d3i - s1d1i; end
2: begin s3r<= s1d3r +s1r; //t8
s3i<= s1d3i+ s1i ; end
3: begin s3r<= s1d3r - s1r; //
s3i<= s1d3i - s1i ; end
endcase
if (ED) begin
if (ct==1 || ct==2 || ct==3) begin
s3d1r<=s3r; //t8
s3d1i<=s3i;
end
if ( ct==2 || ct==3) begin
s3d2r<=s3d1r; //m2
s3d3r<=s3d2r; //t7
s3d2i<=s3d1i;
s3d3i<=s3d2i;
end
end
end
always @ (posedge CLK) begin // S4
if (ED) begin
if (ct==1) begin
s4r<= s2d2r + s2r;
s4i<= s2d2i + s2i; end
else if (ct==2) begin
s4r<=s2d2r - s2r;
s4i<= s2d2i - s2i;
end
end
end
wire em;
assign em = ((ct==2 || ct==3 || ct==4)&& ED);
wire [nb+1:0] m4m7r,m4m7i;
MPU707 UMR( .CLK(CLK),.DO(m4m7r),.DI(s4r),.EI(em)); // UMR
MPU707 UMI( .CLK(CLK),.DO(m4m7i),.DI(s4i),.EI(em)); // UMR
defparam UMR.nb = 16;
defparam UMI.nb = 16;
reg [nb+1:0] sjr,sji, m6r,m6i;
// wire [nb+1:0] a_zero_reg;
// assign a_zero_reg = 0;
always @ (posedge CLK) begin //multiply by J
if (ED) begin
case (ct)
3: begin sjr<= s2d1i; //m6
sji<= 0 - s2d1r; end
4: begin sjr<= m4m7i; //m7
sji<= 0 - m4m7r;end
6: begin sjr<= s3i; //m5
sji<= 0 - s3r; end
endcase
if (ct==4) begin
m6r<=sjr; //m6
m6i<=sji;
end
end
end
reg [nb+2:0] s5r,s5d1r,s5d2r,q1r;
reg [nb+2:0] s5i,s5d1i,s5d2i,q1i;
always @ (posedge CLK) // S5:
if (ED)
case (ct)
5: begin q1r<=s2d3r +m4m7r ; // S1
q1i<=s2d3i +m4m7i ;
s5r<=m6r + sjr;
s5i<=m6i + sji; end
6: begin s5r<=m6r - sjr;
s5i<=m6i - sji;
s5d1r<=s5r;
s5d1i<=s5i; end
7: begin s5r<=s2d3r - m4m7r;
s5i<=s2d3i - m4m7i;
s5d1r<=s5r;
s5d1i<=s5i;
s5d2r<=s5d1r;
s5d2i<=s5d1i;
end
endcase
reg [nb+3:0] s6r,s6i;
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
5: begin s6r<=s3d3r +s3d1r ; // -- D0
s6i<=s3d3i +s3d1i ;end //-- D0
6: begin
s6r<=q1r + s5r ; //-- D1
s6i<=q1i + s5i ; end
7: begin
s6r<=s3d2r +sjr ; //-- D2
s6i<=s3d2i +sji ; end
0: begin
s6r<=s5r - s5d1r ; // -- D3
s6i<= s5i - s5d1i ;end
1:begin s6r<=s3d3r - s3d1r ; //-- D4
s6i<=s3d3i - s3d1i ; end
2: begin
s6r<=s5r + s5d1r ; //-- D5
s6i<=s5i + s5d1i ; end
3: begin
s6r<= s3d3r - sjr ; // D6
s6i<=s3d3i - sji ; end
4: begin
s6r<= q1r - s5d2r ; // D0
s6i<= q1i - s5d2i ; end
endcase
end
// assign #1 DOR=s6r[nb+2:0];
// assign #1 DOI= s6i[nb+2:0];
assign DOR=s6r[nb+2:0];
assign DOI= s6i[nb+2:0];
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Multiplier by 0.7071 ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : MPU707.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: Constant multiplier
// PROPERTIES:1)Is based on shifts right and add
// 2)for short input bit width 0.7071 is approximated as
// 10110101 then rounding is not used
// 3)for long input bit width 0.7071 is approximated as
// 10110101000000101
// 4)hardware is 3 or 4 adders
/////////////////////////////////////////////////////////////////////
module MPU707 (CLK,
DO,
DI,
EI);
parameter nb=16;
input CLK ;
wire CLK;
input [nb+1:0] DI ;
wire [nb+1:0] DI;
input EI ;
wire EI;
output [nb+1:0] DO ;
reg [nb+1:0] DO;
reg [nb+5 :0] dx5;
reg [nb+2 : 0] dt;
wire [nb+6 : 0] dx5p;
wire [nb+6 : 0] dot;
always @(posedge CLK)
begin
if (EI) begin
dx5<=DI+(DI <<2); //multiply by 5
dt<=DI;
DO<=dot >>4;
end
end
assign dot= (dx5p+(dt>>4)+(dx5>>12)); // multiply by 10110101000000101
assign dx5p=(dx5<<1)+(dx5>>2); // multiply by 101101
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// 2-port RAM ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : RAM2x64C_1.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: 2-port RAM with 1 port to write and 1 port to read
// FILES: RAM2x64C_1.v - dual ported synchronous RAM, contains:
// RAM64.v -single ported synchronous RAM
// PROPERTIES: 1)Has the volume of 2x64 complex data
// 2)Contains 4 single port RAMs for real and
// imaginary parts of data in the 2-fold volume
// Two halves of RAM are switched on and off in the
// write mode by the signal ODD
// 3)RAM is synchronous one, the read datum is
// outputted in 2 cycles after the address setting
// 4)Can be substituted to any 2-port synchronous
// RAM for example, to one RAMB16_S36_S36 in XilinxFPGAs
/////////////////////////////////////////////////////////////////////
module RAM2x64C_1 (CLK,
ED,
WE,
ODD,
ADDRW,
ADDRR,
DR,
DI,
DOR,
DOI);
parameter nb=16;
output [nb-1:0] DOR ;
wire [nb-1:0] DOR;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI;
input CLK ;
wire CLK;
input ED ;
wire ED;
input WE ; //write enable
wire WE;
input ODD ; // RAM part switshing
wire ODD;
input [5:0] ADDRW ;
wire [5:0] ADDRW;
input [5:0] ADDRR ;
wire [5:0] ADDRR;
input [nb-1:0] DR ;
wire [nb-1:0] DR;
input [nb-1:0] DI ;
wire [nb-1:0] DI;
reg oddd,odd2;
always @( posedge CLK) begin //switch which reswiches the RAM parts
if (ED) begin
oddd<=ODD;
odd2<=oddd;
end
end
//Two-port RAM is used
wire [6:0] addrr2 = {ODD,ADDRR};
wire [6:0] addrw2 = {~ODD,ADDRW};
wire [2*nb-1:0] di= {DR,DI};
wire [2*nb-1:0] doi;
reg [2*nb-1:0] ram [127:0];
reg [6:0] read_addra;
always @(posedge CLK) begin
if (ED)
begin
if (WE)
ram[addrw2] <= di;
read_addra <= addrr2;
end
end
assign doi = ram[read_addra];
assign DOR=doi[2*nb-1:nb]; // Real read data
assign DOI=doi[nb-1:0]; // Imaginary read data
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// 1-port synchronous RAM ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : RAM64.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: 1-port synchronous RAM
// FILES: RAM64.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 64 data
// 2) RAM is synchronous one, the read datum is outputted
// in 2 cycles after the address setting
// 3) Can be substituted to any 2-port synchronous RAM
/////////////////////////////////////////////////////////////////////
// commented out because it is not used in the default config,
// and ODIN II then thinks that there are 2 top level modules.
// module RAM64 ( CLK, ED,WE ,ADDR ,DI ,DO );
// `USFFT64paramnb
// output [nb-1:0] DO ;
// reg [nb-1:0] DO ;
// input CLK ;
// wire CLK ;
// input ED;
// input WE ;
// wire WE ;
// input [5:0] ADDR ;
// wire [5:0] ADDR ;
// input [nb-1:0] DI ;
// wire [nb-1:0] DI ;
// reg [nb-1:0] mem [63:0];
// reg [5:0] addrrd;
// always @(posedge CLK) begin
// if (ED) begin
// if (WE) mem[ADDR] <= DI;
// addrrd <= ADDR; //storing the address
// DO <= mem[addrrd]; // registering the read datum
// end
// end
// endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// rotating unit, stays between 2 stages of FFT pipeline ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name :
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT
// PROPERTIES: 1) Has 64-clock cycle period starting with the START impulse and continuing forever
// 2) rounding is not used
/////////////////////////////////////////////////////////////////////
module ROTATOR64 (CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI);
parameter nb=16;
parameter nw=15;
input RST ;
wire RST;
input CLK ;
wire CLK;
input ED ; //operation enable
input [nb+1:0] DI; //Imaginary part of data
wire [nb+1:0] DI;
input [nb+1:0] DR ; //Real part of data
input START ; //1-st Data is entered after this impulse
wire START;
output [nb+1:0] DOI ; //Imaginary part of data
wire [nb+1:0] DOI;
output [nb+1:0] DOR ; //Real part of data
wire [nb+1:0] DOR;
output RDY ; //repeats START impulse following the output data
reg RDY;
reg [5:0] addrw;
reg sd1,sd2;
always @( posedge CLK) //address counter for twiddle factors
begin
if (RST) begin
addrw<=0;
sd1<=0;
sd2<=0;
end
else if (START && ED) begin
addrw[5:0]<=0;
sd1<=START;
sd2<=0;
end
else if (ED) begin
addrw<=addrw+1;
sd1<=START;
sd2<=sd1;
RDY<=sd2;
end
end
wire [nw-1:0] wr,wi; //twiddle factor coefficients
//twiddle factor ROM
WROM64 UROM(
.WI(wi),
.WR(wr),
.ADDR(addrw)
);
reg [nb+1 : 0] drd,did;
reg [nw-1 : 0] wrd,wid;
wire [nw+nb+1 : 0] drri,drii,diri,diii;
reg [nb+2:0] drr,dri,dir,dii,dwr,dwi;
assign drri=drd*wrd;
assign diri=did*wrd;
assign drii=drd*wid;
assign diii=did*wid;
always @(posedge CLK) //complex multiplier
begin
if (ED) begin
drd<=DR;
did<=DI;
wrd<=wr;
wid<=wi;
drr<=drri[nw+nb+1 :nw-1]; //msbs of multiplications are stored
dri<=drii[nw+nb+1 : nw-1];
dir<=diri[nw+nb+1 : nw-1];
dii<=diii[nw+nb+1 : nw-1];
dwr<=drr - dii;
dwi<=dri + dir;
end
end
assign DOR=dwr[nb+2:1];
assign DOI=dwi[nb+2 :1];
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Top level of the high speed FFT core ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name :
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: Structural model of the high speed 64-complex point FFT
// PROPERTIES:
//1.Fully pipelined, 1 complex data in, 1 complex result out each
//clock cycle
//2. Input data, output data, coefficient widths are adjustable
//in range 8..16
//3. Normalization stages trigger the data overflow and shift
//data right to prevent the overflow
//4. Core can contain 2 or 3 data buffers. In the configuration of
//2 buffers the results are in the shuffled order but provided with
//the proper address.
//5. The core operation can be slowed down by the control
//of the ED input
//6. The reset RST is synchronous
/////////////////////////////////////////////////////////////////////
module USFFT64_2B (CLK,
RST,
ED,
START,
SHIFT,
DR,
DI,
RDY,
OVF1,
OVF2,
ADDR,
DOR,
DOI);
parameter nb=16; //nb is the data bit width
output RDY ; // in the next cycle after RDY=1 the 0-th result is present
wire RDY;
output OVF1 ; // 1 signals that an overflow occured in the 1-st stage
wire OVF1;
output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage
wire OVF2;
output [5:0] ADDR ; //result data address/number
wire [5:0] ADDR;
output [nb+2:0] DOR ;//Real part of the output data,
wire [nb+2:0] DOR; // the bit width is nb+3, can be decreased when instantiating the core
output [nb+2:0] DOI ;//Imaginary part of the output data
wire [nb+2:0] DOI;
input CLK ; //Clock signal is less than 320 MHz for the Xilinx Virtex5 FPGA
wire CLK;
input RST ; //Reset signal, is the synchronous one with respect to CLK
wire RST;
input ED ; //=1 enables the operation (eneabling CLK)
wire ED;
input START ; // its falling edge starts the transform or the serie of transforms
wire START; // and resets the overflow detectors
input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage
wire [3:0] SHIFT; // bits 3,2 -shift left code in the 2-nd stage
input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after
wire [nb-1:0] DR; // the START signal or after 63-th data of the previous transform
input [nb-1:0] DI ; //Imaginary part of the input data
wire [nb-1:0] DI;
wire [nb-1:0] dr1,di1;
wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5;
wire [nb+2:0] dr2,di2;
wire [nb+4:0] dr6,di6;
wire [nb+2:0] dr7,di7,dr8,di8;
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8;
reg [5:0] addri;
// input buffer =8-bit inversion ordering
BUFRAM64C1_NB16 U_BUF1(
.CLK(CLK),
.RST(RST),
.ED(ED),
.START(START),
.DR(DR),
.DI(DI),
.RDY(rdy1),
.DOR(dr1),
.DOI(di1)
);
//1-st stage of FFT
FFT8 U_FFT1(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy1),.DIR(dr1),.DII(di1),
.RDY(rdy2), .DOR(dr2),. DOI(di2));
defparam U_FFT1.nb = 16;
wire [1:0] shiftl;
assign shiftl = SHIFT[1:0];
CNORM U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit
.START(rdy2), // overflow detector reset
.DR(dr2), .DI(di2),
.SHIFT(shiftl), //shift left bit number
.OVF(OVF1),
.RDY(rdy3),
.DOR(dr3),.DOI(di3));
defparam U_NORM1.nb = 16;
// rotator to the angles proportional to PI/32
ROTATOR64 U_MPU (.CLK(CLK),.RST(RST),.ED(ED),
.START(rdy3),. DR(dr3),.DI(di3),
.RDY(rdy4), .DOR(dr4), .DOI(di4));
BUFRAM64C1_NB18 U_BUF2(.CLK(CLK), .RST(RST), .ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy4), .DR(dr4), .DI(di4),
.RDY(rdy5), .DOR(dr5), .DOI(di5));
//2-nd stage of FFT
FFT8 U_FFT2(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy5),. DIR(dr5),.DII(di5),
.RDY(rdy6), .DOR(dr6), .DOI(di6));
defparam U_FFT2.nb = 18;
wire [1:0] shifth;
assign shifth = SHIFT[3:2];
//2-nd normalization unit
CNORM U_NORM2 ( .CLK(CLK), .ED(ED),
.START(rdy6), // overflow detector reset
.DR(dr6), .DI(di6),
.SHIFT(shifth), //shift left bit number
.OVF(OVF2),
.RDY(rdy7),
.DOR(dr7), .DOI(di7));
defparam U_NORM2.nb = 18;
BUFRAM64C1_NB19 Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy7),. DR(dr7),.DI(di7),
.RDY(rdy8), .DOR(dr8), .DOI(di8));
// 3-data buffer configuratiion
always @(posedge CLK) begin //POINTER to the result samples
if (RST)
addri<=6'b000000;
else if (rdy8==1 )
addri<=6'b000000;
else if (ED)
addri<=addri+1;
end
assign ADDR= addri ;
assign DOR=dr8;
assign DOI=di8;
assign RDY=rdy8;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Twiddle factor ROM for 64-point FFT ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// Design_Version : 1.0
// File name : WROM64.v
// File Revision :
// Last modification : Sun Sep 30 20:11:56 2007
/////////////////////////////////////////////////////////////////////
// FUNCTION: 1-port synchronous RAM
// FILES: RAM64.v -single ported synchronous RAM
// PROPERTIES:
//1) Has 64 complex coefficients which form a table 8x8,
//and stay in the needed order, as they are addressed
//by the simple counter
//2) 16-bit values are stored. When shorter bit width is set
//then rounding is not used
//3) for FFT and IFFT depending on paramifft
/////////////////////////////////////////////////////////////////////
//%%GENDEFINE%% (choose_from, blocking, 0, 63)
//%%GENDEFINE%% (always_list, 0, 63)
module WROM64 (WI,
WR,
ADDR);
parameter nw=15;
input [5:0] ADDR ;
wire [5:0] ADDR;
output [nw-1:0] WI ;
wire [nw-1:0] WI;
output [nw-1:0] WR ;
wire [nw-1:0] WR;
parameter [15:0] c0 = 16'h7fff;
parameter [15:0] s0 = 16'h0000;
parameter [15:0] c1 = 16'h7f62;
parameter [15:0] s1 = 16'h0c8c;
parameter [15:0] c2 = 16'h7d8a;
parameter [15:0] s2 = 16'h18f9 ;
parameter [15:0] c3 = 16'h7a7d;
parameter [15:0] s3 = 16'h2528;
parameter [15:0] c4 = 16'h7642;
parameter [15:0] s4 = 16'h30fc;
parameter [15:0] c5 = 16'h70e3;
parameter [15:0] s5 = 16'h3c57;
parameter [15:0] c6 = 16'h6a6e;
parameter [15:0] s6 = 16'h471d ;
parameter [15:0] c7 = 16'h62f2;
parameter [15:0] s7 = 16'h5134;
parameter [15:0] c8 = 16'h5a82;
wire [31:0] wf_0;
wire [31:0] wf_1;
wire [31:0] wf_2;
wire [31:0] wf_3;
wire [31:0] wf_4;
wire [31:0] wf_5;
wire [31:0] wf_6;
wire [31:0] wf_7;
wire [31:0] wf_8;
wire [31:0] wf_9;
wire [31:0] wf_10;
wire [31:0] wf_11;
wire [31:0] wf_12;
wire [31:0] wf_13;
wire [31:0] wf_14;
wire [31:0] wf_15;
wire [31:0] wf_16;
wire [31:0] wf_17;
wire [31:0] wf_18;
wire [31:0] wf_19;
wire [31:0] wf_20;
wire [31:0] wf_21;
wire [31:0] wf_22;
wire [31:0] wf_23;
wire [31:0] wf_24;
wire [31:0] wf_25;
wire [31:0] wf_26;
wire [31:0] wf_27;
wire [31:0] wf_28;
wire [31:0] wf_29;
wire [31:0] wf_30;
wire [31:0] wf_31;
wire [31:0] wf_32;
wire [31:0] wf_33;
wire [31:0] wf_34;
wire [31:0] wf_35;
wire [31:0] wf_36;
wire [31:0] wf_37;
wire [31:0] wf_38;
wire [31:0] wf_39;
wire [31:0] wf_40;
wire [31:0] wf_41;
wire [31:0] wf_42;
wire [31:0] wf_43;
wire [31:0] wf_44;
wire [31:0] wf_45;
wire [31:0] wf_46;
wire [31:0] wf_47;
wire [31:0] wf_48;
wire [31:0] wf_49;
wire [31:0] wf_50;
wire [31:0] wf_51;
wire [31:0] wf_52;
wire [31:0] wf_53;
wire [31:0] wf_54;
wire [31:0] wf_55;
wire [31:0] wf_56;
wire [31:0] wf_57;
wire [31:0] wf_58;
wire [31:0] wf_59;
wire [31:0] wf_60;
wire [31:0] wf_61;
wire [31:0] wf_62;
wire [31:0] wf_63;
// integer i;
// always@(ADDR) begin
//(w0, w0, w0, w0, w0, w0, w0, w0, 0..7 // twiddle factors for FFT
// w0, w1, w2, w3, w4, w5, w6, w7, 8..15
// w0, w2, w4, w6, w8, w10,w12,w14, 16..23
// w0, w3, w6, w9, w12,w15,w18,w21, 24..31
// w0, w4, w8, w12,w16,w20,w24,w28, 32..47
// w0, w5, w10,w15,w20,w25,w30,w35,
// w0, w6, w12,w18,w24,w30,w36,w42,
// w0, w7, w14,w21,w28,w35,w42,w49);
// for( i =0; i<8; i=i+1) wf[i] =w0;
assign wf_0 = {c0,s0} ;
assign wf_1 = {c0,s0} ;
assign wf_2 = {c0,s0} ;
assign wf_3 = {c0,s0} ;
assign wf_4 = {c0,s0} ;
assign wf_5 = {c0,s0} ;
assign wf_6 = {c0,s0} ;
assign wf_7 = {c0,s0} ;
// for( i =8; i<63; i=i+8) wf[i] =w0;
assign wf_8 = {c0,s0} ;
assign wf_16 = {c0,s0} ;
assign wf_24 = {c0,s0} ;
assign wf_32 = {c0,s0} ;
assign wf_40 = {c0,s0} ;
assign wf_48 = {c0,s0} ;
assign wf_56 = {c0,s0} ;
assign wf_9 = {c1,-s1} ;
assign wf_10 = {c2,-s2} ;
assign wf_11 = {c3,-s3} ;
assign wf_12 = {c4,-s4} ;
assign wf_13 = {c5,-s5} ;
assign wf_14 = {c6,-s6} ;
assign wf_15 = {c7,-s7} ;
assign wf_17 = {c2,-s2} ;
assign wf_18 = {c4,-s4} ;
assign wf_19 = {c6,-s6} ;
assign wf_20 = {c8,-c8} ;
assign wf_21 = {s6,-c6} ;
assign wf_22 = {s4,-c4} ;
assign wf_23 = {s2,-c2} ;
assign wf_25 = {c3,-s3} ;
assign wf_26 = {c6,-s6} ;
assign wf_27 = {s7,-c7} ;
assign wf_28 = {s4,-c4} ;
assign wf_29 = {s1,-c1} ;
assign wf_30 = {-s2, -c2} ;
assign wf_31 = {-s5, -c5} ;
assign wf_33 = {c4,-s4} ;
assign wf_34 = {c8,-c8} ;
assign wf_35 = {s4,-c4} ;
assign wf_36 = {s0,-c0} ;
assign wf_37 = {-s4, -c4} ;
assign wf_38 = {-c8, -c8} ;
assign wf_39 = {-c4, -s4} ;
assign wf_41 = {c5,-s5} ;
assign wf_42 = {s6,-c6} ;
assign wf_43 = {s1,-c1} ;
assign wf_44 = {-s4, -c4} ;
assign wf_45 = {-c7, -s7} ;
assign wf_46 = {-c2, -s2} ;
assign wf_47 = {-c3, s3} ;
assign wf_49 = {c6,-s6} ;
assign wf_50 = {s4,-c4} ;
assign wf_51 = {-s2, -c2} ;
assign wf_52 = {-c8, -c8} ;
assign wf_53 = {-c2, -s2} ;
assign wf_54 = {-c4, s4} ;
assign wf_55 = {-s6, c6} ;
assign wf_57 = {c7,-s7} ;
assign wf_58 = {s2,-c2} ;
assign wf_59 = {-s5, -c5} ;
assign wf_60 = {-c4, -s4} ;
assign wf_61 = {-c3, s3} ;
assign wf_62 = {-s6, c6} ;
assign wf_63 = {s1, c1} ;
// end
wire [31:0] wb_0;
wire [31:0] wb_1;
wire [31:0] wb_2;
wire [31:0] wb_3;
wire [31:0] wb_4;
wire [31:0] wb_5;
wire [31:0] wb_6;
wire [31:0] wb_7;
wire [31:0] wb_8;
wire [31:0] wb_9;
wire [31:0] wb_10;
wire [31:0] wb_11;
wire [31:0] wb_12;
wire [31:0] wb_13;
wire [31:0] wb_14;
wire [31:0] wb_15;
wire [31:0] wb_16;
wire [31:0] wb_17;
wire [31:0] wb_18;
wire [31:0] wb_19;
wire [31:0] wb_20;
wire [31:0] wb_21;
wire [31:0] wb_22;
wire [31:0] wb_23;
wire [31:0] wb_24;
wire [31:0] wb_25;
wire [31:0] wb_26;
wire [31:0] wb_27;
wire [31:0] wb_28;
wire [31:0] wb_29;
wire [31:0] wb_30;
wire [31:0] wb_31;
wire [31:0] wb_32;
wire [31:0] wb_33;
wire [31:0] wb_34;
wire [31:0] wb_35;
wire [31:0] wb_36;
wire [31:0] wb_37;
wire [31:0] wb_38;
wire [31:0] wb_39;
wire [31:0] wb_40;
wire [31:0] wb_41;
wire [31:0] wb_42;
wire [31:0] wb_43;
wire [31:0] wb_44;
wire [31:0] wb_45;
wire [31:0] wb_46;
wire [31:0] wb_47;
wire [31:0] wb_48;
wire [31:0] wb_49;
wire [31:0] wb_50;
wire [31:0] wb_51;
wire [31:0] wb_52;
wire [31:0] wb_53;
wire [31:0] wb_54;
wire [31:0] wb_55;
wire [31:0] wb_56;
wire [31:0] wb_57;
wire [31:0] wb_58;
wire [31:0] wb_59;
wire [31:0] wb_60;
wire [31:0] wb_61;
wire [31:0] wb_62;
wire [31:0] wb_63;
// always@(ADDR) begin
//initial begin #10;
//(w0, w0, w0, w0, w0, w0, w0, w0, // twiddle factors for IFFT
// for( i =0; i<8; i=i+1) wb[i] =wi0;
assign wb_0 = {c0,s0} ;
assign wb_1 = {c0,s0} ;
assign wb_2 = {c0,s0} ;
assign wb_3 = {c0,s0} ;
assign wb_4 = {c0,s0} ;
assign wb_5 = {c0,s0} ;
assign wb_6 = {c0,s0} ;
assign wb_7 = {c0,s0} ;
// for( i =8; i<63; i=i+8) wb[i] =wi0;
assign wb_8 = {c0,s0} ;
assign wb_16 = {c0,s0} ;
assign wb_24 = {c0,s0} ;
assign wb_32 = {c0,s0} ;
assign wb_40 = {c0,s0} ;
assign wb_48 = {c0,s0} ;
assign wb_56 = {c0,s0} ;
assign wb_9 = {c1,s1} ;
assign wb_10 = {c2,s2} ;
assign wb_11 = {c3,s3} ;
assign wb_12 = {c4,s4} ;
assign wb_13 = {c5,s5} ;
assign wb_14 = {c6,s6} ;
assign wb_15 = {c7,s7} ;
assign wb_17 = {c2,s2} ;
assign wb_18 = {c4,s4} ;
assign wb_19 = {c6,s6} ;
assign wb_20 = {c8,c8} ;
assign wb_21 = {s6,c6} ;
assign wb_22 = {s4,c4} ;
assign wb_23 = {s2,c2} ;
assign wb_25 = {c3,s3} ;
assign wb_26 = {c6,s6} ;
assign wb_27 = {s7,c7} ;
assign wb_28 = {s4,c4} ;
assign wb_29 = {s1,c1} ;
assign wb_30 = {-s2, c2} ;
assign wb_31 = {-s5, c5} ;
assign wb_33 = {c4,s4} ;
assign wb_34 = {c8,c8} ;
assign wb_35 = {s4,c4} ;
assign wb_36 = {s0,c0} ;
assign wb_37 = {-s4, c4} ;
assign wb_38 = {-c8, c8} ;
assign wb_39 = {-c4, s4} ;
assign wb_41 = {c5,s5} ;
assign wb_42 = {s6,c6} ;
assign wb_43 = {s1,c1} ;
assign wb_44 = {-s4, c4} ;
assign wb_45 = {-c7, s7} ;
assign wb_46 = {-c2, s2} ;
assign wb_47 = {-c3, -s3} ;
assign wb_49 = {c6,s6} ;
assign wb_50 = {s4,c4} ;
assign wb_51 = {-s2, c2} ;
assign wb_52 = {-c8, c8} ;
assign wb_53 = {-c2, s2} ;
assign wb_54 = {-c4, -s4} ;
assign wb_55 = {-s6, -c6} ;
assign wb_57 = {c7,s7} ;
assign wb_58 = {s2,c2} ;
assign wb_59 = {-s5, c5} ;
assign wb_60 = {-c4, s4} ;
assign wb_61 = {-c3, -s3} ;
assign wb_62 = {-s6, -c6} ;
assign wb_63 = {s1, -c1} ;
// end
reg [31:0] reim;
// in place of:
// assign reim = wf[ADDR];
always @ (ADDR or wf_0 or wf_1 or wf_2 or wf_3 or wf_4 or wf_5 or wf_6 or wf_7 or wf_8 or wf_9 or wf_10 or wf_11 or wf_12 or wf_13 or wf_14 or wf_15 or wf_16 or wf_17 or wf_18 or wf_19 or wf_20 or wf_21 or wf_22 or wf_23 or wf_24 or wf_25 or wf_26 or wf_27 or wf_28 or wf_29 or wf_30 or wf_31 or wf_32 or wf_33 or wf_34 or wf_35 or wf_36 or wf_37 or wf_38 or wf_39 or wf_40 or wf_41 or wf_42 or wf_43 or wf_44 or wf_45 or wf_46 or wf_47 or wf_48 or wf_49 or wf_50 or wf_51 or wf_52 or wf_53 or wf_54 or wf_55 or wf_56 or wf_57 or wf_58 or wf_59 or wf_60 or wf_61 or wf_62 or wf_63) begin
case (ADDR)
'd0:reim = wf_0;
'd1:reim = wf_1;
'd2:reim = wf_2;
'd3:reim = wf_3;
'd4:reim = wf_4;
'd5:reim = wf_5;
'd6:reim = wf_6;
'd7:reim = wf_7;
'd8:reim = wf_8;
'd9:reim = wf_9;
'd10:reim = wf_10;
'd11:reim = wf_11;
'd12:reim = wf_12;
'd13:reim = wf_13;
'd14:reim = wf_14;
'd15:reim = wf_15;
'd16:reim = wf_16;
'd17:reim = wf_17;
'd18:reim = wf_18;
'd19:reim = wf_19;
'd20:reim = wf_20;
'd21:reim = wf_21;
'd22:reim = wf_22;
'd23:reim = wf_23;
'd24:reim = wf_24;
'd25:reim = wf_25;
'd26:reim = wf_26;
'd27:reim = wf_27;
'd28:reim = wf_28;
'd29:reim = wf_29;
'd30:reim = wf_30;
'd31:reim = wf_31;
'd32:reim = wf_32;
'd33:reim = wf_33;
'd34:reim = wf_34;
'd35:reim = wf_35;
'd36:reim = wf_36;
'd37:reim = wf_37;
'd38:reim = wf_38;
'd39:reim = wf_39;
'd40:reim = wf_40;
'd41:reim = wf_41;
'd42:reim = wf_42;
'd43:reim = wf_43;
'd44:reim = wf_44;
'd45:reim = wf_45;
'd46:reim = wf_46;
'd47:reim = wf_47;
'd48:reim = wf_48;
'd49:reim = wf_49;
'd50:reim = wf_50;
'd51:reim = wf_51;
'd52:reim = wf_52;
'd53:reim = wf_53;
'd54:reim = wf_54;
'd55:reim = wf_55;
'd56:reim = wf_56;
'd57:reim = wf_57;
'd58:reim = wf_58;
'd59:reim = wf_59;
'd60:reim = wf_60;
'd61:reim = wf_61;
'd62:reim = wf_62;
default:reim = wf_63;
endcase
end
assign WR =reim[31:32-nw];
assign WI=reim[15 :16-nw];
endmodule
|
//
// Title : Software Wishbone master unit for testbenches
//
// File : wishbone_master_tb.v
// Author : Tomasz Wlostowski <[email protected]>
// Created : Tue Mar 23 12:19:36 2010
// Standard : Verilog 2001
//
// Modified by Lucas Russo <[email protected]>
// date: 04/10/2012
`include "defines.v"
// Default values of certain WB parameters.
// Bus clock period
`ifndef WB_CLOCK_PERIOD
`define WB_CLOCK_PERIOD 100
`define WB_RESET_DELAY (4*`WB_CLOCK_PERIOD)
`endif
// Widths of wishbone address/data/byte select
`ifndef WB_DATA_BUS_WIDTH
`define WB_DATA_BUS_WIDTH 32
`endif
`ifndef WB_ADDRESS_BUS_WIDTH
`define WB_ADDRESS_BUS_WIDTH 32
`endif
`define WB_BWSEL_WIDTH ((`WB_DATA_BUS_WIDTH + 7) / 8)
module WB_TEST_MASTER(
wb_clk
);
// these signals make the WB bus, which can be accessed from outside the module
reg [`WB_ADDRESS_BUS_WIDTH - 1 : 0] wb_addr = 0;
reg [`WB_DATA_BUS_WIDTH - 1 : 0] wb_data_o = 0;
reg [`WB_BWSEL_WIDTH - 1 : 0] wb_bwsel = 0;
wire [`WB_DATA_BUS_WIDTH -1 : 0] wb_data_i;
wire wb_ack_i;
reg wb_cyc = 0;
reg wb_stb = 0;
reg wb_we = 0;
//reg wb_rst = 0;
//reg wb_clk = 1;
input wb_clk;
reg wb_tb_verbose = 1;
reg wb_monitor_bus = 1;
time last_access_t = 0;
reg [`WB_DATA_BUS_WIDTH -1 : 0] dummy;
// ready signal. 1 indicates that WB_TEST unit is initialized and ready for commands
reg ready = 0;
// Generated outside this module
// generate the WB bus clock
//always #(`WB_CLOCK_PERIOD/2) wb_clk <= ~wb_clk;
// generate the reset and ready signals
initial begin
//#(`WB_RESET_DELAY) wb_rst <= 1;
#(`WB_CLOCK_PERIOD*2) ready <= 1;
end
// enables/disables displaying information about each read/write operation.
task verbose;
input onoff;
begin
wb_tb_verbose = onoff;
end
endtask // wb_verbose
task monitor_bus;
input onoff;
begin
wb_monitor_bus = onoff;
end
endtask // monitor_bus
task rw_generic;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [`WB_DATA_BUS_WIDTH - 1 : 0] data_i;
output [`WB_DATA_BUS_WIDTH - 1 : 0] data_o;
input rw;
input [3:0] size;
begin : rw_generic_main
// Debug information
if(wb_tb_verbose) begin
if(rw)
$display("@%0d: WB write %s: addr %x, data %x",
$time, (size==1?"byte":((size==2)?"short":"int")),
addr, data_i);
else // !rw
$display("@%0d: WB read %s: addr %x",
$time, (size==1?"byte":((size==2)?"short":"int")),
addr);
end // wb_tb_verbose
if($time != last_access_t) begin
@(posedge wb_clk);
end
wb_stb<=1;
wb_cyc<=1;
//wb_addr <= {2'b00, addr[31:2]};
wb_addr <= addr;
wb_we <= rw;
if(rw) begin
case(size)
4: begin wb_data_o<=data_i; wb_bwsel <= 4'b1111; end
2: begin
if(addr[1]) begin
wb_data_o[31:16] = data_i[15:0];
wb_bwsel = 4'b1100;
end else begin
wb_data_o[15:0] = data_i[15:0];
wb_bwsel = 4'b0011;
end
end
1: begin
case(addr[1:0])
0: begin wb_data_o[31:24] = data_i[7:0]; wb_bwsel <= 4'b1000; end
1: begin wb_data_o[23:16] = data_i[7:0]; wb_bwsel <= 4'b0100; end
2: begin wb_data_o[15:8] = data_i[7:0]; wb_bwsel <= 4'b0010; end
3: begin wb_data_o[7:0] = data_i[7:0]; wb_bwsel <= 4'b0001; end
endcase // case(addr[1:0])
end
endcase // case(size)
end // if (rw)
#(`WB_CLOCK_PERIOD-1);
// Wait for ack.
// FIXME: insert a maximum wait time
while(wb_ack_i == 0) begin @(posedge wb_clk); end
data_o = wb_data_i;
wb_cyc <= 0;
wb_we <= 0;
wb_stb <= 0;
//if(wb_tb_verbose && !rw)
// $display("@%0d: WB read %s: addr %x, data %x",
// $time, (size==1?"byte":((size==2)?"short":"int")),
// addr, wb_data_i);
last_access_t = $time;
end
endtask // rw_generic
task write8;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [7 : 0] data_i;
begin
rw_generic(addr, data_i, dummy, 1, 1);
end
endtask // write8
task read8;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
output [7 : 0] data_o;
begin : read8_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval;
rw_generic(addr, 0, rval, 0, 1);
data_o = rval[7:0];
end
endtask // read8
task write32;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [31 : 0] data_i;
begin
rw_generic(addr, data_i, dummy, 1, 4);
end
endtask // write32
task read32;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
output [31 : 0] data_o;
begin : read32_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval;
rw_generic(addr, 0, rval, 0, 4);
data_o = rval[31:0];
end
endtask // read32
// bus monitor
always@(posedge wb_clk) begin
if(wb_monitor_bus && wb_cyc && wb_stb && wb_ack_i)begin
if(wb_we)
$display("@%0d: ACK-Write: addr %x wdata %x bwsel %b", $time, wb_addr, wb_data_o, wb_bwsel);
else
$display("@%0d: ACK-Read: addr %x rdata %x", $time, wb_addr, wb_data_i);
end
end
endmodule
|
/************************
* Willard Wider
* 08-04-17
* ELEC3725
* cpu5.v
* building a 32 bit CPU
************************/
//cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
module cpu5(ibus,clk,daddrbus,databus,reset,iaddrbus);
//just a clock
input clk;
//reset to clear the counter
input reset;
//instruction bus
output [31:0] iaddrbus;//from PC, to SIM_OUT
wire [31:0] iaddrbusWire1;//from mux, to PC
wire [31:0] iaddrbusWire2;//from PC, to mux4/iaddrbusWire4
wire [31:0] iaddrbusWire4;//from PC, to IF_ID
//SLT SLE control bits
//00 = nothing, 01 = SLT, 10 = SLE
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
//for SLT/SLE operations
wire ZBit;//high when rs(a) - rt(b) = 0, 1 otherwise
wire [31:0] potentialSLEBit;//the value to set to dbus if it is a SLE operation
wire [31:0] potentialSLTBit;
wire [31:0] actualSLBit;
//the cout for the alu
wire ALUCoutWire;
//BEQ and BNE congtrol bits
//00 = noting, 01 = BEQ, 10 = BNE
reg [1:0] branchControlBit;
wire [1:0] branchControlBitWire1;
wire [1:0] branchControlBitWire2;
wire [1:0] branchControlBitWire3;
//program counter wires to be piped into the IF_ID stage
wire [31:0] PCWire1;//form IF_ID, to branchCalcWire1
//the wire for the branch calculation, part 1 (immediate sign extended, bit shifted by 2 for *4)
wire [31:0] branchCalcWire1;//from immediate, to branchCalcwire2
//the wire for the branch calculation, part 2 (+4)
wire [31:0] branchCalcWire2;//from branchCalcWire1, to mux4
//the new bus things
output [31:0] daddrbus;//from EX_MEM, to SIM_OUT
inout [31:0] databus;//from SIM_IN/EX_MEM, to SIM_OUT/MEM_WB
//decoder tings
wire [5:0] opCode;//from IF_ID
wire [5:0] funktion;//from IF_ID
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [5:0] rs;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to regfile
wire [5:0] rt;//from ibsuWire, to BselectWire and mxu1
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//abus
//output [31:0] abus;//from ID_EX, to SIM_OUT
wire [31:0] abusWire1;//from regOut, to ID_EX
wire [31:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [31:0] bbus;//from mux2Out, to SIM_OUT
wire [31:0] bbusWire1;//from regOut, to ID_EX
wire [31:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [31:0] bbusWire3;//from EX_MEM, to memory logic
wire [31:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [31:0] bbusWire4;//from MEM_WB, to mux3
//dbus
wire [31:0] dbusWire1;//from ALU, to dbusWire1_5(SLE_MUX_TEST)
wire [31:0] dbusWire1_5;//from SLE_MUX_TEST to EX_MEM
wire [31:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [31:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [31:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [31:0] mux2Out;//from bbusWire2/immWire2, to ALU
//mux4 deciding wire
wire mux4Controller;//controls the pc address bus
//immediate
wire [31:0] immWire1;//from IF_ID, to ID_EX
wire [31:0] immWire2;//from ID_EX, to mux2
wire [31:0] branchWire;
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
branchControlBit = 2'b0;
setControlBits = 2'b00;
end
//latch for pipeline 0(PC)
//module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut);
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
//assign the output
assign iaddrbus = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//iaddrbusWire4 gets feed into the IF_ID stage
assign iaddrbusWire4 = iaddrbusWire2;
//feed the pc back into itself. may update iaddrbusWire2 from the IF_ID stage
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
//PIPELINE_0_END
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
//PIPELINE_1_START
//decode the input command
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
assign branchWire = ibusWire[15]? {14'b11111111111111, ibusWire[15:0], 2'b00} : {14'b00000000000000, ibusWire[15:0], 2'b00};
//for the change in the opcode which is like always
always @(ibusWire) begin
//first mux value is to assume 0
immBit1 = 1;
CinWire1 = 0;
branchControlBit = 0;
setControlBits = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2'b00;
//write the cases for the opcode (immediate)
case (opCode)
6'b000011: begin
//addi
SWire1 = 3'b010;
end
6'b000010: begin
//subi
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xori
SWire1 = 3'b000;
end
6'b001111: begin
//andi
SWire1 = 3'b110;
end
6'b001100: begin
//ori
SWire1 = 3'b100;
end
6'b011110: begin
//load word, but still addi
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
6'b011111: begin
//store word, but still addi
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
6'b110000: begin
//BEQ
SWire1 = 3'b010;
//set control bit
branchControlBit = 2'b01;
end
6'b110001: begin
//BNE
SWire1 = 3'b010;
//set control bit
branchControlBit = 2'b10;
end
//if 00000
6'b000000: begin
//write the mux value here
immBit1= 0;
//then write the cases for the funct
case (funktion)
6'b000011: begin
//add
SWire1 = 3'b010;
end
6'b000010: begin
//sub
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xor
SWire1 = 3'b000;
end
6'b000111: begin
//and
SWire1 = 3'b110;
end
6'b000100: begin
//or
SWire1 = 3'b100;
end
6'b110110: begin
//SLT
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2'b01;
//set to subtraction
SWire1 = 3'b011;
end
6'b110111: begin
//SLE
//00 = nothing, 01 = SLT, 10 = SLE
setControlBits = 2'b10;
//set to subtraction
SWire1 = 3'b011;
end
endcase
end
endcase
end
//write the select lines
assign AselectWire = 1 << rs;
//only write to Bselect for real if it's actually goign to use Bselect
//i don't think this line matters but i feel like it's good pratice
//assign BselectWire = immBit1? 32'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rt;
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//update the muxWire4 controll if the instruction is BEQ or BNE, and if it is actually equal
//mux4Controller = 1 if ((BEQ and abus == bbus) or (BNE and bbus != abus)), 0 otherwise
//00 = noting, 01 = BEQ, 10 = BNE
assign mux4Controller = ((!clk) && ((branchControlBit==2'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2'b10) && (abusWire1!=bbusWire1)))? 1: 0;
//the branch calculation
assign branchCalcWire1 = immWire1 << 2;
assign branchCalcWire2 = branchWire + PCWire1;
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1));
//PIPELINE_2_START
//mux2
//immWire for true, Bselet for false
assign mux2Out = immBit2? immWire2: bbusWire2;
//make the ALU
//module alu32 (d, Cout, V, a, b, Cin, S);
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));
//wipe the dbus if it's an SLT or an SLE
//zero result flag
assign ZBit = (dbusWire1==0)? 1:0;
//potential values for if the instruction is for SLT or SLE
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 32'h00000001:32'h00000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 32'h00000001:32'h00000000;
//a determinate wire that uses SLT or SLE, assuming if not one, than the other
//(a wire later decides if that always "lateer" choosen one is actually used
//00 = nothing, 01 = SLT, 10 = SLE
assign actualSLBit = (setControlBitsWire1 == 2'b01)? potentialSLTBit: potentialSLEBit;
//the wire that is used for the new dbusWire, adds a check for if the result needs to be the SLT or not
//SLE_MUX_TEST
assign dbusWire1_5 = (setControlBitsWire1 > 2'b00)? actualSLBit:dbusWire1;
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_5),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2));
//PIPELINE_3_SRART
//assign output values
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 32'hzzzzzzzz;
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),
.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),.branchControlBitWire3(branchControlBitWire3));
//PIPELINE_4_START
//the mux for the data writeBack
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
//disable the writeback if it's a store word OR if it's a beq branch
assign DselectWire4 = ((lwSwFlag4 == 2'b10) ||(branchControlBitWire3 > 2'b00))? 32'h00000001: DselectWire3_5;
//PIPELINE_4_END
endmodule
//phase 0 pipeline latch (PC)
module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [31:0] iaddrbusWire1;
output [31:0] iaddrbusOut;
reg [31:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
//if reset is high, reset the counter
//else incriment
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus, PCIn;
input clk;
output [31:0] ibusWire, PCOut;
reg [31:0] ibusWire, PCOut;
always @(posedge clk) begin
//EDIT: this is delayed branching, other instructions can be put in place
ibusWire = ibus;
PCOut = PCIn;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [1:0] branchControlBit;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [1:0] branchControlBitWire1;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [1:0] branchControlBitWire1;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,branchControlBitWire2);
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
input [1:0] branchControlBitWire1;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
output [1:0] branchControlBitWire2;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
reg [1:0] branchControlBitWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,branchControlBitWire3);
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
input [1:0] branchControlBitWire2;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
output [1:0] branchControlBitWire3;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
reg [1:0] branchControlBitWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over ?/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a ?
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;//generate carry
p = a ^ bint;//proragate carry
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, [email protected]
//// Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module aes_ip
(
//OUTPUTS
output int_ccf,
output int_err,
output dma_req_wr,
output dma_req_rd,
output PREADY,
output PSLVERR,
output [31:0] PRDATA,
//INPUTS
input [ 3:0] PADDR,
input [31:0] PWDATA,
input PWRITE,
input PENABLE,
input PSEL,
input PCLK,
input PRESETn
);
wire [31:0] col_out;
wire [31:0] key_out;
wire [31:0] iv_out;
wire end_aes;
wire [ 3:0] iv_en;
wire [ 3:0] iv_sel_rd;
wire [ 3:0] key_en;
wire [ 1:0] key_sel_rd;
wire [ 1:0] data_type;
wire [ 1:0] addr;
wire [ 1:0] op_mode;
wire [ 1:0] aes_mode;
wire start;
wire disable_core;
wire write_en;
wire read_en;
wire first_block;
//wire pwdata_host_interface;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
//assign pwdata_host_interface = PWDATA[12:0];
host_interface HOST_INTERFACE
(
.key_en ( key_en ),
.col_addr ( addr ),
.col_wr_en ( write_en ),
.col_rd_en ( read_en ),
.key_sel ( key_sel_rd ),
.iv_en ( iv_en ),
.iv_sel ( iv_sel_rd ),
.int_ccf ( int_ccf ),
.int_err ( int_err ),
.chmod ( aes_mode ),
.mode ( op_mode ),
.data_type ( data_type ),
.disable_core ( disable_core ),
.first_block ( first_block ),
.dma_req_wr ( dma_req_wr ),
.dma_req_rd ( dma_req_rd ),
.start_core ( start ),
.PRDATA ( PRDATA ),
.PADDR ( PADDR ),
.PWDATA ( PWDATA[12:0] ),
.PWRITE ( PWRITE ),
.PENABLE ( PENABLE ),
.PSEL ( PSEL ),
.PCLK ( PCLK ),
.PRESETn ( PRESETn ),
.key_bus ( key_out ),
.col_bus ( col_out ),
.iv_bus ( iv_out ),
.ccf_set ( end_aes )
);
aes_core AES_CORE
(
.col_out ( col_out ),
.key_out ( key_out ),
.iv_out ( iv_out ),
.end_aes ( end_aes ),
.bus_in ( PWDATA ),
.iv_en ( iv_en ),
.iv_sel_rd ( iv_sel_rd ),
.key_en ( key_en ),
.key_sel_rd ( key_sel_rd ),
.data_type ( data_type ),
.addr ( addr ),
.op_mode ( op_mode ),
.aes_mode ( aes_mode ),
.start ( start ),
.disable_core ( disable_core ),
.write_en ( write_en ),
.read_en ( read_en ),
.first_block ( first_block ),
.rst_n ( PRESETn ),
.clk ( PCLK )
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:41:40 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_color_test_0_0 -prefix
// system_vga_color_test_0_0_ system_vga_color_test_0_0_sim_netlist.v
// Design : system_vga_color_test_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_color_test_0_0,vga_color_test,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_color_test,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_color_test_0_0
(clk_25,
xaddr,
yaddr,
rgb);
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
wire clk_25;
wire [23:3]\^rgb ;
wire [9:0]xaddr;
wire [9:0]yaddr;
assign rgb[23:22] = \^rgb [23:22];
assign rgb[21] = \^rgb [20];
assign rgb[20] = \^rgb [20];
assign rgb[19] = \^rgb [20];
assign rgb[18] = \^rgb [20];
assign rgb[17] = \^rgb [20];
assign rgb[16] = \^rgb [20];
assign rgb[15:14] = \^rgb [15:14];
assign rgb[13] = \^rgb [12];
assign rgb[12] = \^rgb [12];
assign rgb[11] = \^rgb [12];
assign rgb[10] = \^rgb [12];
assign rgb[9] = \^rgb [12];
assign rgb[8] = \^rgb [12];
assign rgb[7:5] = \^rgb [7:5];
assign rgb[4] = \^rgb [3];
assign rgb[3] = \^rgb [3];
assign rgb[2] = \^rgb [3];
assign rgb[1] = \^rgb [3];
assign rgb[0] = \^rgb [3];
system_vga_color_test_0_0_vga_color_test U0
(.clk_25(clk_25),
.rgb({\^rgb [23:22],\^rgb [20],\^rgb [15:14],\^rgb [12],\^rgb [7:5],\^rgb [3]}),
.xaddr(xaddr),
.yaddr(yaddr[9:3]));
endmodule
module system_vga_color_test_0_0_vga_color_test
(rgb,
yaddr,
xaddr,
clk_25);
output [9:0]rgb;
input [6:0]yaddr;
input [9:0]xaddr;
input clk_25;
wire clk_25;
wire [9:0]rgb;
wire \rgb[13]_i_1_n_0 ;
wire \rgb[14]_i_1_n_0 ;
wire \rgb[14]_i_2_n_0 ;
wire \rgb[14]_i_3_n_0 ;
wire \rgb[14]_i_4_n_0 ;
wire \rgb[14]_i_5_n_0 ;
wire \rgb[14]_i_6_n_0 ;
wire \rgb[15]_i_1_n_0 ;
wire \rgb[15]_i_2_n_0 ;
wire \rgb[15]_i_3_n_0 ;
wire \rgb[15]_i_4_n_0 ;
wire \rgb[15]_i_5_n_0 ;
wire \rgb[15]_i_6_n_0 ;
wire \rgb[15]_i_7_n_0 ;
wire \rgb[21]_i_1_n_0 ;
wire \rgb[22]_i_10_n_0 ;
wire \rgb[22]_i_11_n_0 ;
wire \rgb[22]_i_1_n_0 ;
wire \rgb[22]_i_2_n_0 ;
wire \rgb[22]_i_3_n_0 ;
wire \rgb[22]_i_4_n_0 ;
wire \rgb[22]_i_5_n_0 ;
wire \rgb[22]_i_6_n_0 ;
wire \rgb[22]_i_7_n_0 ;
wire \rgb[22]_i_8_n_0 ;
wire \rgb[22]_i_9_n_0 ;
wire \rgb[23]_i_10_n_0 ;
wire \rgb[23]_i_11_n_0 ;
wire \rgb[23]_i_12_n_0 ;
wire \rgb[23]_i_13_n_0 ;
wire \rgb[23]_i_14_n_0 ;
wire \rgb[23]_i_15_n_0 ;
wire \rgb[23]_i_16_n_0 ;
wire \rgb[23]_i_17_n_0 ;
wire \rgb[23]_i_18_n_0 ;
wire \rgb[23]_i_1_n_0 ;
wire \rgb[23]_i_2_n_0 ;
wire \rgb[23]_i_3_n_0 ;
wire \rgb[23]_i_4_n_0 ;
wire \rgb[23]_i_5_n_0 ;
wire \rgb[23]_i_6_n_0 ;
wire \rgb[23]_i_7_n_0 ;
wire \rgb[23]_i_8_n_0 ;
wire \rgb[23]_i_9_n_0 ;
wire \rgb[4]_i_1_n_0 ;
wire \rgb[4]_i_2_n_0 ;
wire \rgb[5]_i_1_n_0 ;
wire \rgb[5]_i_2_n_0 ;
wire \rgb[6]_i_1_n_0 ;
wire \rgb[6]_i_2_n_0 ;
wire \rgb[6]_i_3_n_0 ;
wire \rgb[6]_i_4_n_0 ;
wire \rgb[6]_i_5_n_0 ;
wire \rgb[7]_i_1_n_0 ;
wire \rgb[7]_i_2_n_0 ;
wire \rgb[7]_i_3_n_0 ;
wire \rgb[7]_i_4_n_0 ;
wire \rgb[7]_i_5_n_0 ;
wire \rgb[7]_i_6_n_0 ;
wire [9:0]xaddr;
wire [6:0]yaddr;
LUT5 #(
.INIT(32'h5555FF02))
\rgb[13]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.O(\rgb[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55555555FFFFFF02))
\rgb[14]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_3_n_0 ),
.I4(\rgb[22]_i_2_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h02F20202))
\rgb[14]_i_2
(.I0(\rgb[14]_i_4_n_0 ),
.I1(\rgb[23]_i_11_n_0 ),
.I2(xaddr[9]),
.I3(\rgb[14]_i_5_n_0 ),
.I4(\rgb[23]_i_10_n_0 ),
.O(\rgb[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'hE))
\rgb[14]_i_3
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.O(\rgb[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEFEFEFEFEEE))
\rgb[14]_i_4
(.I0(xaddr[4]),
.I1(xaddr[5]),
.I2(xaddr[3]),
.I3(xaddr[0]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[14]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFF8))
\rgb[14]_i_5
(.I0(xaddr[2]),
.I1(xaddr[5]),
.I2(xaddr[7]),
.I3(xaddr[6]),
.I4(xaddr[8]),
.O(\rgb[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hA888A888A8888888))
\rgb[14]_i_6
(.I0(yaddr[5]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[3]),
.I4(yaddr[1]),
.I5(yaddr[0]),
.O(\rgb[14]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF55455545))
\rgb[15]_i_1
(.I0(\rgb[23]_i_4_n_0 ),
.I1(\rgb[22]_i_2_n_0 ),
.I2(\rgb[15]_i_2_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[15]_i_4_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[23]_i_12_n_0 ),
.O(\rgb[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hAAA88888))
\rgb[15]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.I4(xaddr[8]),
.O(\rgb[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hECEEEEEEECECECEC))
\rgb[15]_i_4
(.I0(xaddr[8]),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(\rgb[15]_i_6_n_0 ),
.I5(\rgb[15]_i_7_n_0 ),
.O(\rgb[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h1F))
\rgb[15]_i_5
(.I0(xaddr[0]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[15]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_6
(.I0(xaddr[5]),
.I1(xaddr[4]),
.O(\rgb[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h8880))
\rgb[15]_i_7
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[4]),
.I3(xaddr[3]),
.O(\rgb[15]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFBF0FB))
\rgb[21]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_4_n_0 ),
.I2(\rgb[23]_i_2_n_0 ),
.I3(\rgb[23]_i_6_n_0 ),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFFF00FFEF))
\rgb[22]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_3_n_0 ),
.I2(\rgb[22]_i_4_n_0 ),
.I3(\rgb[23]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h01))
\rgb[22]_i_10
(.I0(xaddr[9]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[22]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0070))
\rgb[22]_i_11
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.O(\rgb[22]_i_11_n_0 ));
LUT6 #(
.INIT(64'h00000000AAABABAB))
\rgb[22]_i_2
(.I0(\rgb[22]_i_5_n_0 ),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000FD0000))
\rgb[22]_i_3
(.I0(\rgb[23]_i_15_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[22]_i_7_n_0 ),
.I4(xaddr[9]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\rgb[22]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_8_n_0 ),
.I3(\rgb[14]_i_3_n_0 ),
.O(\rgb[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000200030003))
\rgb[22]_i_5
(.I0(\rgb[15]_i_5_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.I4(xaddr[3]),
.I5(xaddr[4]),
.O(\rgb[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h111111111111111F))
\rgb[22]_i_6
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(\rgb[22]_i_9_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[22]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFEFEFEFFFFFFFF))
\rgb[22]_i_7
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.I3(xaddr[5]),
.I4(xaddr[2]),
.I5(\rgb[23]_i_10_n_0 ),
.O(\rgb[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5515551555151515))
\rgb[22]_i_8
(.I0(\rgb[23]_i_14_n_0 ),
.I1(\rgb[22]_i_10_n_0 ),
.I2(\rgb[22]_i_11_n_0 ),
.I3(xaddr[4]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[22]_i_8_n_0 ));
LUT6 #(
.INIT(64'hCCCC000088800000))
\rgb[22]_i_9
(.I0(xaddr[3]),
.I1(xaddr[6]),
.I2(xaddr[2]),
.I3(xaddr[1]),
.I4(xaddr[5]),
.I5(xaddr[4]),
.O(\rgb[22]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAAEAAAEAAAE))
\rgb[23]_i_1
(.I0(\rgb[23]_i_2_n_0 ),
.I1(\rgb[23]_i_3_n_0 ),
.I2(\rgb[23]_i_4_n_0 ),
.I3(\rgb[23]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h1F))
\rgb[23]_i_10
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[5]),
.O(\rgb[23]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h7F))
\rgb[23]_i_11
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[23]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_12
(.I0(yaddr[6]),
.I1(\rgb[14]_i_6_n_0 ),
.O(\rgb[23]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0515555515155555))
\rgb[23]_i_13
(.I0(\rgb[23]_i_18_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_17_n_0 ),
.I4(xaddr[6]),
.I5(xaddr[3]),
.O(\rgb[23]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_14
(.I0(xaddr[9]),
.I1(xaddr[8]),
.O(\rgb[23]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h15))
\rgb[23]_i_15
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[23]_i_15_n_0 ));
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_16
(.I0(xaddr[7]),
.I1(xaddr[6]),
.O(\rgb[23]_i_16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_17
(.I0(xaddr[2]),
.I1(xaddr[1]),
.O(\rgb[23]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hFE))
\rgb[23]_i_18
(.I0(xaddr[7]),
.I1(xaddr[8]),
.I2(xaddr[9]),
.O(\rgb[23]_i_18_n_0 ));
LUT6 #(
.INIT(64'h0000000000022222))
\rgb[23]_i_2
(.I0(\rgb[15]_i_4_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[4]),
.I3(yaddr[3]),
.I4(yaddr[5]),
.I5(\rgb[23]_i_8_n_0 ),
.O(\rgb[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAAFFFB))
\rgb[23]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_9_n_0 ),
.I3(xaddr[9]),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00004440))
\rgb[23]_i_4
(.I0(xaddr[9]),
.I1(\rgb[23]_i_9_n_0 ),
.I2(\rgb[23]_i_10_n_0 ),
.I3(\rgb[23]_i_11_n_0 ),
.I4(\rgb[23]_i_12_n_0 ),
.O(\rgb[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0057FFFF00570057))
\rgb[23]_i_5
(.I0(yaddr[5]),
.I1(yaddr[3]),
.I2(yaddr[4]),
.I3(yaddr[6]),
.I4(\rgb[23]_i_12_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[23]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0155))
\rgb[23]_i_6
(.I0(yaddr[6]),
.I1(yaddr[4]),
.I2(yaddr[3]),
.I3(yaddr[5]),
.O(\rgb[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h40CC44CC44CC44CC))
\rgb[23]_i_7
(.I0(xaddr[6]),
.I1(\rgb[23]_i_14_n_0 ),
.I2(\rgb[23]_i_15_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[4]),
.I5(xaddr[5]),
.O(\rgb[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFD500000000))
\rgb[23]_i_8
(.I0(\rgb[23]_i_10_n_0 ),
.I1(xaddr[2]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_16_n_0 ),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[23]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFFFE0))
\rgb[23]_i_9
(.I0(\rgb[23]_i_17_n_0 ),
.I1(xaddr[0]),
.I2(xaddr[3]),
.I3(xaddr[5]),
.I4(xaddr[4]),
.I5(\rgb[23]_i_11_n_0 ),
.O(\rgb[23]_i_9_n_0 ));
LUT5 #(
.INIT(32'h04770404))
\rgb[4]_i_1
(.I0(\rgb[6]_i_2_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[4]_i_2_n_0 ),
.I4(\rgb[5]_i_2_n_0 ),
.O(\rgb[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF2F2FFFFF202F))
\rgb[4]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[6]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAFEAAAAAAAA))
\rgb[5]_i_1
(.I0(\rgb[7]_i_4_n_0 ),
.I1(\rgb[15]_i_2_n_0 ),
.I2(\rgb[15]_i_4_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[5]_i_2_n_0 ),
.O(\rgb[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7F7F0F7F))
\rgb[5]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[23]_i_7_n_0 ),
.I4(\rgb[7]_i_3_n_0 ),
.O(\rgb[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000F000FFFFF0045))
\rgb[6]_i_1
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[7]_i_3_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[6]_i_2_n_0 ),
.I4(\rgb[6]_i_3_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hEA))
\rgb[6]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.O(\rgb[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00FF0002))
\rgb[6]_i_3
(.I0(xaddr[9]),
.I1(\rgb[22]_i_7_n_0 ),
.I2(\rgb[6]_i_4_n_0 ),
.I3(\rgb[22]_i_6_n_0 ),
.I4(\rgb[6]_i_5_n_0 ),
.O(\rgb[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000007))
\rgb[6]_i_4
(.I0(xaddr[2]),
.I1(xaddr[1]),
.I2(xaddr[3]),
.I3(xaddr[4]),
.I4(xaddr[5]),
.O(\rgb[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0057))
\rgb[6]_i_5
(.I0(xaddr[8]),
.I1(xaddr[7]),
.I2(xaddr[6]),
.I3(xaddr[9]),
.O(\rgb[6]_i_5_n_0 ));
LUT5 #(
.INIT(32'h0000222A))
\rgb[7]_i_1
(.I0(\rgb[7]_i_3_n_0 ),
.I1(yaddr[5]),
.I2(yaddr[3]),
.I3(yaddr[4]),
.I4(yaddr[6]),
.O(\rgb[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF000000FB))
\rgb[7]_i_2
(.I0(\rgb[7]_i_3_n_0 ),
.I1(\rgb[23]_i_7_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[23]_i_4_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[7]_i_4_n_0 ),
.O(\rgb[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0000000D))
\rgb[7]_i_3
(.I0(xaddr[6]),
.I1(\rgb[7]_i_5_n_0 ),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.O(\rgb[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000444))
\rgb[7]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.I3(\rgb[22]_i_8_n_0 ),
.I4(\rgb[14]_i_2_n_0 ),
.O(\rgb[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1515155515155555))
\rgb[7]_i_5
(.I0(xaddr[5]),
.I1(xaddr[3]),
.I2(xaddr[4]),
.I3(xaddr[0]),
.I4(xaddr[2]),
.I5(xaddr[1]),
.O(\rgb[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000007F55))
\rgb[7]_i_6
(.I0(\rgb[15]_i_7_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(\rgb[7]_i_6_n_0 ));
FDRE \rgb_reg[13]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[13]_i_1_n_0 ),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[14]_i_1_n_0 ),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[15]_i_1_n_0 ),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[21]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[21]_i_1_n_0 ),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[22]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[22]_i_1_n_0 ),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[23]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[23]_i_1_n_0 ),
.Q(rgb[9]),
.R(1'b0));
FDSE \rgb_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[4]_i_1_n_0 ),
.Q(rgb[0]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[5]_i_1_n_0 ),
.Q(rgb[1]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[6]_i_1_n_0 ),
.Q(rgb[2]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[7]_i_2_n_0 ),
.Q(rgb[3]),
.S(\rgb[7]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %ALTGXB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altgxb
// ============================================================
// File Name: altpcie_serdes_1sgx_x1_15625.v
// Megafunction Name(s):
// altgxb
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_1sgx_x1_15625 (
inclk,
pll_areset,
pllenable,
rx_cruclk,
rx_enacdet,
rx_in,
rxanalogreset,
rxdigitalreset,
tx_coreclk,
tx_in,
txdigitalreset,
coreclk_out,
pll_locked,
rx_clkout,
rx_freqlocked,
rx_locked,
rx_out,
rx_patterndetect,
rx_syncstatus,
tx_out);
input [0:0] inclk;
input [0:0] pll_areset;
input [0:0] pllenable;
input [0:0] rx_cruclk;
input [0:0] rx_enacdet;
input [0:0] rx_in;
input [0:0] rxanalogreset;
input [0:0] rxdigitalreset;
input [0:0] tx_coreclk;
input [19:0] tx_in;
input [0:0] txdigitalreset;
output [0:0] coreclk_out;
output [0:0] pll_locked;
output [0:0] rx_clkout;
output [0:0] rx_freqlocked;
output [0:0] rx_locked;
output [19:0] rx_out;
output [1:0] rx_patterndetect;
output [1:0] rx_syncstatus;
output [0:0] tx_out;
wire [1:0] sub_wire0;
wire [0:0] sub_wire1;
wire [19:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [1:0] sub_wire7;
wire [0:0] sub_wire8;
wire [1:0] rx_patterndetect = sub_wire0[1:0];
wire [0:0] tx_out = sub_wire1[0:0];
wire [19:0] rx_out = sub_wire2[19:0];
wire [0:0] coreclk_out = sub_wire3[0:0];
wire [0:0] rx_locked = sub_wire4[0:0];
wire [0:0] rx_freqlocked = sub_wire5[0:0];
wire [0:0] rx_clkout = sub_wire6[0:0];
wire [1:0] rx_syncstatus = sub_wire7[1:0];
wire [0:0] pll_locked = sub_wire8[0:0];
altgxb altgxb_component (
.pll_areset (pll_areset),
.rx_enacdet (rx_enacdet),
.rx_cruclk (rx_cruclk),
.pllenable (pllenable),
.inclk (inclk),
.rx_in (rx_in),
.tx_in (tx_in),
.rxanalogreset (rxanalogreset),
.tx_coreclk (tx_coreclk),
.rxdigitalreset (rxdigitalreset),
.txdigitalreset (txdigitalreset),
.rx_patterndetect (sub_wire0),
.tx_out (sub_wire1),
.rx_out (sub_wire2),
.coreclk_out (sub_wire3),
.rx_locked (sub_wire4),
.rx_freqlocked (sub_wire5),
.rx_clkout (sub_wire6),
.rx_syncstatus (sub_wire7),
.pll_locked (sub_wire8)
// synopsys translate_off
,
.rx_we (),
.rx_coreclk (),
.rx_channelaligned (),
.rx_bisterr (),
.rx_slpbk (),
.rx_aclr (),
.rx_fifoalmostempty (),
.tx_aclr (),
.rx_bistdone (),
.rx_signaldetect (),
.tx_forcedisparity (),
.tx_vodctrl (),
.rx_equalizerctrl (),
.rx_a1a2size (),
.tx_srlpbk (),
.rx_errdetect (),
.rx_re (),
.rx_disperr (),
.rx_locktodata (),
.tx_preemphasisctrl (),
.rx_rlv (),
.rx_fifoalmostfull (),
.rx_bitslip (),
.rx_a1a2sizeout (),
.rx_locktorefclk (),
.rx_ctrldetect (),
.tx_ctrlenable ()
// synopsys translate_on
);
defparam
altgxb_component.align_pattern = "P0101111100",
altgxb_component.align_pattern_length = 10,
altgxb_component.allow_gxb_merging = "OFF",
altgxb_component.channel_width = 20,
altgxb_component.clk_out_mode_reference = "ON",
altgxb_component.consider_enable_tx_8b_10b_i1i2_generation = "ON",
altgxb_component.consider_instantiate_transmitter_pll_param = "ON",
altgxb_component.cru_inclock_period = 6400,
altgxb_component.data_rate = 2500,
altgxb_component.data_rate_remainder = 0,
altgxb_component.disparity_mode = "ON",
altgxb_component.dwidth_factor = 2,
altgxb_component.enable_tx_8b_10b_i1i2_generation = "OFF",
altgxb_component.equalizer_ctrl_setting = 20,
altgxb_component.flip_rx_out = "OFF",
altgxb_component.flip_tx_in = "OFF",
altgxb_component.force_disparity_mode = "OFF",
altgxb_component.for_engineering_sample_device = "OFF",
altgxb_component.instantiate_transmitter_pll = "ON",
altgxb_component.intended_device_family = "Stratix GX",
altgxb_component.loopback_mode = "NONE",
altgxb_component.lpm_type = "altgxb",
altgxb_component.number_of_channels = 1,
altgxb_component.number_of_quads = 1,
altgxb_component.operation_mode = "DUPLEX",
altgxb_component.pll_bandwidth_type = "LOW",
altgxb_component.pll_inclock_period = 6400,
altgxb_component.preemphasis_ctrl_setting = 10,
altgxb_component.protocol = "CUSTOM",
altgxb_component.reverse_loopback_mode = "NONE",
altgxb_component.run_length_enable = "OFF",
altgxb_component.rx_bandwidth_type = "NEW_LOW",
altgxb_component.rx_data_rate = 2500,
altgxb_component.rx_data_rate_remainder = 0,
altgxb_component.rx_enable_dc_coupling = "OFF",
altgxb_component.rx_force_signal_detect = "ON",
altgxb_component.rx_ppm_setting = 1000,
altgxb_component.signal_threshold_select = 530,
altgxb_component.tx_termination = 2,
altgxb_component.use_8b_10b_mode = "OFF",
altgxb_component.use_auto_bit_slip = "ON",
altgxb_component.use_channel_align = "OFF",
altgxb_component.use_double_data_mode = "ON",
altgxb_component.use_equalizer_ctrl_signal = "OFF",
altgxb_component.use_generic_fifo = "OFF",
altgxb_component.use_preemphasis_ctrl_signal = "OFF",
altgxb_component.use_rate_match_fifo = "OFF",
altgxb_component.use_rx_clkout = "ON",
altgxb_component.use_rx_coreclk = "OFF",
altgxb_component.use_rx_cruclk = "ON",
altgxb_component.use_self_test_mode = "OFF",
altgxb_component.use_symbol_align = "ON",
altgxb_component.use_tx_coreclk = "ON",
altgxb_component.use_vod_ctrl_signal = "OFF",
altgxb_component.vod_ctrl_setting = 800;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADD_GENERIC_FIFO_WE_SYNCH_REGISTER STRING "0"
// Retrieval info: PRIVATE: ALIGN_PATTERN STRING "0101111100"
// Retrieval info: PRIVATE: ALIGN_PATTERN_LENGTH STRING "10"
// Retrieval info: PRIVATE: CHANNEL_WIDTH STRING "20"
// Retrieval info: PRIVATE: CLK_OUT_MODE_REFERENCE STRING "1"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "0"
// Retrieval info: PRIVATE: EQU_SETTING STRING "2"
// Retrieval info: PRIVATE: FLIP_ALIGN_PATTERN STRING "0"
// Retrieval info: PRIVATE: FLIP_RX_OUT STRING "0"
// Retrieval info: PRIVATE: FLIP_TX_IN STRING "0"
// Retrieval info: PRIVATE: FOR_ENGINEERING_SAMPLE_DEVICE STRING "0"
// Retrieval info: PRIVATE: GXB_QUAD_MERGE STRING "0"
// Retrieval info: PRIVATE: INFINIBAND_INVALID_CODE STRING "0"
// Retrieval info: PRIVATE: INSTANTIATE_TRANSMITTER_PLL STRING "1"
// Retrieval info: PRIVATE: LOOPBACK_MODE NUMERIC "0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;pll_areset;rx_in;rx_coreclk;rx_cruclk"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "rx_aclr;rx_bitslip;rx_enacdet;rx_we;rx_re"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "rx_slpbk;rx_a1a2size;rx_equalizerctrl;rx_locktorefclk;rx_locktodata"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "tx_in;tx_coreclk;tx_aclr;tx_ctrlenable;tx_forcedisparity"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "tx_srlpbk;tx_vodctrl;tx_preemphasisctrl;txdigitalreset;rxdigitalreset"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "rxanalogreset;pllenable;pll_locked;coreclk_out;rx_out"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "rx_clkout;rx_locked;rx_freqlocked;rx_rlv;rx_syncstatus"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_7 STRING "rx_patterndetect;rx_ctrldetect;rx_errdetect;rx_disperr;rx_signaldetect"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_8 STRING "rx_fifoalmostempty;rx_fifoalmostfull;rx_channelaligned;rx_bisterr;rx_bistdone"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_9 STRING "rx_a1a2sizeout;tx_out"
// Retrieval info: PRIVATE: NUMBER_OF_CHANNELS STRING "1"
// Retrieval info: PRIVATE: OP_MODE STRING "Duplex"
// Retrieval info: PRIVATE: PLL_ACLR STRING "1"
// Retrieval info: PRIVATE: PLL_BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: PRIVATE: PLL_DC_COUPLING STRING "1"
// Retrieval info: PRIVATE: PLL_ENABLE STRING "1"
// Retrieval info: PRIVATE: PLL_LOCKED STRING "1"
// Retrieval info: PRIVATE: PREEMPHASIS_SETTING STRING "2"
// Retrieval info: PRIVATE: PREEMPHASIS_SIGNAL STRING "0"
// Retrieval info: PRIVATE: PROTOCOL STRING "CUSTOM"
// Retrieval info: PRIVATE: REVERSE_LOOPBACK_MODE NUMERIC "0"
// Retrieval info: PRIVATE: RLV STRING "5"
// Retrieval info: PRIVATE: RX_A1A2 STRING "0"
// Retrieval info: PRIVATE: RX_A1A2SIZEOUT STRING "0"
// Retrieval info: PRIVATE: RX_BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: PRIVATE: RX_BASE_INPUT_TYPE STRING ""
// Retrieval info: PRIVATE: RX_BISTDONE STRING "0"
// Retrieval info: PRIVATE: RX_BISTERR STRING "0"
// Retrieval info: PRIVATE: RX_BITSLIP STRING "0"
// Retrieval info: PRIVATE: RX_CLKOUT STRING "1"
// Retrieval info: PRIVATE: RX_CLR STRING "1"
// Retrieval info: PRIVATE: RX_CTRLDETECT STRING "0"
// Retrieval info: PRIVATE: RX_DATA_RATE STRING "2500.00"
// Retrieval info: PRIVATE: RX_DISPERR STRING "0"
// Retrieval info: PRIVATE: RX_ENACDET STRING "1"
// Retrieval info: PRIVATE: RX_ERRDETECT STRING "0"
// Retrieval info: PRIVATE: RX_FIFOALMOSTEMPTY STRING "0"
// Retrieval info: PRIVATE: RX_FIFOALMOSTFULL STRING "0"
// Retrieval info: PRIVATE: RX_FIFOEMPTY STRING "0"
// Retrieval info: PRIVATE: RX_FIFOFULL STRING "0"
// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "1"
// Retrieval info: PRIVATE: RX_FREQLOCKED STRING "1"
// Retrieval info: PRIVATE: RX_FREQUENCY STRING "156.25"
// Retrieval info: PRIVATE: RX_LOCKED STRING "1"
// Retrieval info: PRIVATE: RX_LOCKTODATA STRING "0"
// Retrieval info: PRIVATE: RX_LOCKTOREFCLK STRING "0"
// Retrieval info: PRIVATE: RX_PATTERNDETECT STRING "1"
// Retrieval info: PRIVATE: RX_PPM_SETTING STRING "1000"
// Retrieval info: PRIVATE: RX_SIGDET STRING "0"
// Retrieval info: PRIVATE: RX_SYNCSTATUS STRING "1"
// Retrieval info: PRIVATE: SELF_TEST_MODE NUMERIC "-1"
// Retrieval info: PRIVATE: SIGNAL_THRESHOLD_SELECT STRING "530"
// Retrieval info: PRIVATE: TX_BASE_INPUT_TYPE STRING ""
// Retrieval info: PRIVATE: TX_CLR STRING "1"
// Retrieval info: PRIVATE: TX_DATA_RATE STRING "2500.00"
// Retrieval info: PRIVATE: TX_FORCE_DISPARITY STRING "0"
// Retrieval info: PRIVATE: TX_FREQUENCY STRING "156.25"
// Retrieval info: PRIVATE: TX_PLL_LOCKED STRING "1"
// Retrieval info: PRIVATE: TX_TERMINATION STRING "100"
// Retrieval info: PRIVATE: USE_8B10B_DECODER STRING "0"
// Retrieval info: PRIVATE: USE_8B10B_ENCODER STRING "0"
// Retrieval info: PRIVATE: USE_8B_10B_MODE STRING "OFF"
// Retrieval info: PRIVATE: USE_AUTO_BIT_SLIP NUMERIC "1"
// Retrieval info: PRIVATE: USE_CRUCLK_FROM_PLL STRING "1"
// Retrieval info: PRIVATE: USE_DC_COUPLING STRING "0"
// Retrieval info: PRIVATE: USE_EQUALIZER STRING "0"
// Retrieval info: PRIVATE: USE_EXTERNAL_TX_TERMINATION STRING "0"
// Retrieval info: PRIVATE: USE_GENERIC_FIFO STRING "0"
// Retrieval info: PRIVATE: USE_RATE_MATCH_FIFO STRING "0"
// Retrieval info: PRIVATE: USE_RLV STRING "0"
// Retrieval info: PRIVATE: USE_RX_CORECLK STRING "0"
// Retrieval info: PRIVATE: USE_RX_CRUCLK STRING "1"
// Retrieval info: PRIVATE: USE_TX_CORECLK STRING "1"
// Retrieval info: PRIVATE: VERSION STRING "4.0"
// Retrieval info: PRIVATE: VOD_SETTING STRING "800"
// Retrieval info: PRIVATE: VOD_SIGNAL STRING "0"
// Retrieval info: PRIVATE: XGM_RXANALOGRESET STRING "1"
// Retrieval info: LIBRARY: altgxb altgxb.all
// Retrieval info: CONSTANT: ALIGN_PATTERN STRING "P0101111100"
// Retrieval info: CONSTANT: ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: ALLOW_GXB_MERGING STRING "OFF"
// Retrieval info: CONSTANT: CHANNEL_WIDTH NUMERIC "20"
// Retrieval info: CONSTANT: CLK_OUT_MODE_REFERENCE STRING "ON"
// Retrieval info: CONSTANT: CONSIDER_ENABLE_TX_8B_10B_I1I2_GENERATION STRING "ON"
// Retrieval info: CONSTANT: CONSIDER_INSTANTIATE_TRANSMITTER_PLL_PARAM STRING "ON"
// Retrieval info: CONSTANT: CRU_INCLOCK_PERIOD NUMERIC "6400"
// Retrieval info: CONSTANT: DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: DISPARITY_MODE STRING "ON"
// Retrieval info: CONSTANT: DWIDTH_FACTOR NUMERIC "2"
// Retrieval info: CONSTANT: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "OFF"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_SETTING NUMERIC "20"
// Retrieval info: CONSTANT: FLIP_RX_OUT STRING "OFF"
// Retrieval info: CONSTANT: FLIP_TX_IN STRING "OFF"
// Retrieval info: CONSTANT: FORCE_DISPARITY_MODE STRING "OFF"
// Retrieval info: CONSTANT: FOR_ENGINEERING_SAMPLE_DEVICE STRING "OFF"
// Retrieval info: CONSTANT: INSTANTIATE_TRANSMITTER_PLL STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "NONE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altgxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: NUMBER_OF_QUADS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUPLEX"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: PLL_INCLOCK_PERIOD NUMERIC "6400"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_SETTING NUMERIC "10"
// Retrieval info: CONSTANT: PROTOCOL STRING "CUSTOM"
// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "NONE"
// Retrieval info: CONSTANT: RUN_LENGTH_ENABLE STRING "OFF"
// Retrieval info: CONSTANT: RX_BANDWIDTH_TYPE STRING "NEW_LOW"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_ENABLE_DC_COUPLING STRING "OFF"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "ON"
// Retrieval info: CONSTANT: RX_PPM_SETTING NUMERIC "1000"
// Retrieval info: CONSTANT: SIGNAL_THRESHOLD_SELECT NUMERIC "530"
// Retrieval info: CONSTANT: TX_TERMINATION NUMERIC "2"
// Retrieval info: CONSTANT: USE_8B_10B_MODE STRING "OFF"
// Retrieval info: CONSTANT: USE_AUTO_BIT_SLIP STRING "ON"
// Retrieval info: CONSTANT: USE_CHANNEL_ALIGN STRING "OFF"
// Retrieval info: CONSTANT: USE_DOUBLE_DATA_MODE STRING "ON"
// Retrieval info: CONSTANT: USE_EQUALIZER_CTRL_SIGNAL STRING "OFF"
// Retrieval info: CONSTANT: USE_GENERIC_FIFO STRING "OFF"
// Retrieval info: CONSTANT: USE_PREEMPHASIS_CTRL_SIGNAL STRING "OFF"
// Retrieval info: CONSTANT: USE_RATE_MATCH_FIFO STRING "OFF"
// Retrieval info: CONSTANT: USE_RX_CLKOUT STRING "ON"
// Retrieval info: CONSTANT: USE_RX_CORECLK STRING "OFF"
// Retrieval info: CONSTANT: USE_RX_CRUCLK STRING "ON"
// Retrieval info: CONSTANT: USE_SELF_TEST_MODE STRING "OFF"
// Retrieval info: CONSTANT: USE_SYMBOL_ALIGN STRING "ON"
// Retrieval info: CONSTANT: USE_TX_CORECLK STRING "ON"
// Retrieval info: CONSTANT: USE_VOD_CTRL_SIGNAL STRING "OFF"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "800"
// Retrieval info: USED_PORT: coreclk_out 0 0 1 0 OUTPUT NODEFVAL "coreclk_out[0..0]"
// Retrieval info: USED_PORT: inclk 0 0 1 0 INPUT GND "inclk[0..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT GND "pll_areset[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pllenable 0 0 1 0 INPUT VCC "pllenable[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_enacdet 0 0 1 0 INPUT GND "rx_enacdet[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT GND "rx_in[0..0]"
// Retrieval info: USED_PORT: rx_locked 0 0 1 0 OUTPUT NODEFVAL "rx_locked[0..0]"
// Retrieval info: USED_PORT: rx_out 0 0 20 0 OUTPUT NODEFVAL "rx_out[19..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
// Retrieval info: USED_PORT: rxanalogreset 0 0 1 0 INPUT GND "rxanalogreset[0..0]"
// Retrieval info: USED_PORT: rxdigitalreset 0 0 1 0 INPUT GND "rxdigitalreset[0..0]"
// Retrieval info: USED_PORT: tx_coreclk 0 0 1 0 INPUT GND "tx_coreclk[0..0]"
// Retrieval info: USED_PORT: tx_in 0 0 20 0 INPUT GND "tx_in[19..0]"
// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL "tx_out[0..0]"
// Retrieval info: USED_PORT: txdigitalreset 0 0 1 0 INPUT GND "txdigitalreset[0..0]"
// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
// Retrieval info: CONNECT: @pllenable 0 0 1 0 pllenable 0 0 1 0
// Retrieval info: CONNECT: rx_locked 0 0 1 0 @rx_locked 0 0 1 0
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
// Retrieval info: CONNECT: @txdigitalreset 0 0 1 0 txdigitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: CONNECT: coreclk_out 0 0 1 0 @coreclk_out 0 0 1 0
// Retrieval info: CONNECT: @tx_coreclk 0 0 1 0 tx_coreclk 0 0 1 0
// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
// Retrieval info: CONNECT: rx_out 0 0 20 0 @rx_out 0 0 20 0
// Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
// Retrieval info: CONNECT: @rxdigitalreset 0 0 1 0 rxdigitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: @rxanalogreset 0 0 1 0 rxanalogreset 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: @rx_enacdet 0 0 1 0 rx_enacdet 0 0 1 0
// Retrieval info: CONNECT: @tx_in 0 0 20 0 tx_in 0 0 20 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625_bb.v FALSE FALSE
|
module resource_table
(/*AUTOARG*/
// Outputs
res_table_done, cam_biggest_space_size, cam_biggest_space_addr,
// Inputs
clk, rst, alloc_res_en, dealloc_res_en, alloc_cu_id, dealloc_cu_id,
alloc_wg_slot_id, dealloc_wg_slot_id, alloc_res_size,
alloc_res_start
);
parameter CU_ID_WIDTH = 1;
parameter NUMBER_CU = 2;
parameter WG_SLOT_ID_WIDTH = 6;
parameter NUMBER_WF_SLOTS_PER_CU = 40;
parameter RES_ID_WIDTH = 10;
parameter NUMBER_RES_SLOTS = 1024;
localparam TABLE_ADDR_WIDTH = WG_SLOT_ID_WIDTH + CU_ID_WIDTH;
localparam TABLE_ENTRY_WIDTH = 2*WG_SLOT_ID_WIDTH + 2*RES_ID_WIDTH+1;
input clk, rst;
input alloc_res_en, dealloc_res_en;
input [CU_ID_WIDTH-1:0] alloc_cu_id, dealloc_cu_id;
input [WG_SLOT_ID_WIDTH-1:0] alloc_wg_slot_id, dealloc_wg_slot_id;
input [RES_ID_WIDTH :0] alloc_res_size;
input [RES_ID_WIDTH-1 :0] alloc_res_start;
output reg res_table_done;
output [RES_ID_WIDTH :0] cam_biggest_space_size;
output [RES_ID_WIDTH-1 :0] cam_biggest_space_addr;
reg alloc_res_en_i, dealloc_res_en_i;
reg [CU_ID_WIDTH-1:0] alloc_cu_id_i, dealloc_cu_id_i;
reg [WG_SLOT_ID_WIDTH-1:0] alloc_wg_slot_id_i, dealloc_wg_slot_id_i;
reg [RES_ID_WIDTH :0] alloc_res_start_i;
reg [RES_ID_WIDTH-1 :0] alloc_res_size_i;
function[TABLE_ENTRY_WIDTH-1 : 0] get_new_entry;
input [RES_ID_WIDTH-1 :0] res_start;
input [RES_ID_WIDTH :0] res_size;
input [WG_SLOT_ID_WIDTH-1:0] prev_entry, next_entry;
get_new_entry = {next_entry, prev_entry, res_size, res_start};
endfunction // if
// Put here localparams for items location
localparam RES_STRT_L = 0;
localparam RES_STRT_H = RES_ID_WIDTH-1;
localparam RES_SIZE_L = RES_STRT_H+1;
localparam RES_SIZE_H = RES_SIZE_L+RES_ID_WIDTH;
localparam PREV_ENTRY_L = RES_SIZE_H+1;
localparam PREV_ENTRY_H = PREV_ENTRY_L + WG_SLOT_ID_WIDTH-1;
localparam NEXT_ENTRY_L = PREV_ENTRY_H + 1;
localparam NEXT_ENTRY_H = NEXT_ENTRY_L + WG_SLOT_ID_WIDTH-1;
function[TABLE_ADDR_WIDTH-1 : 0] calc_table_addr;
input [CU_ID_WIDTH-1:0] cu_id;
input [WG_SLOT_ID_WIDTH-1:0] wg_slot_id;
calc_table_addr = NUMBER_WF_SLOTS_PER_CU*cu_id + wg_slot_id;
endfunction // calc_table_addr
function[WG_SLOT_ID_WIDTH-1 : 0] get_prev_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_prev_item_wg_slot = table_entry[PREV_ENTRY_H:PREV_ENTRY_L];
endfunction // if
function[WG_SLOT_ID_WIDTH-1 : 0] get_next_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_next_item_wg_slot = table_entry[NEXT_ENTRY_H:NEXT_ENTRY_L];
endfunction // if
function[RES_ID_WIDTH-1 : 0] get_res_start;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_res_start = table_entry[RES_STRT_H:RES_STRT_L];
endfunction // if
function[RES_ID_WIDTH : 0] get_res_size;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_res_size = table_entry[RES_SIZE_H:RES_SIZE_L];
endfunction // if
function[TABLE_ENTRY_WIDTH-1 : 0] set_prev_item_wg_slot;
input [WG_SLOT_ID_WIDTH-1:0] prev_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
set_prev_item_wg_slot
= {table_entry[NEXT_ENTRY_H:NEXT_ENTRY_L],
prev_item_wg_slot,
table_entry[RES_SIZE_H:RES_SIZE_L],
table_entry[RES_STRT_H:RES_STRT_L]};
endfunction // if
function[TABLE_ENTRY_WIDTH-1 : 0] set_next_item_wg_slot;
input [WG_SLOT_ID_WIDTH-1:0] next_item_wg_slot;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
set_next_item_wg_slot
= {next_item_wg_slot,
table_entry[PREV_ENTRY_H:PREV_ENTRY_L],
table_entry[RES_SIZE_H:RES_SIZE_L],
table_entry[RES_STRT_H:RES_STRT_L]};
endfunction // if
function[RES_ID_WIDTH-1 : 0] get_free_res_start;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_free_res_start = get_res_start(table_entry) + get_res_size(table_entry);
endfunction // if
function[RES_ID_WIDTH:0] get_free_res_size;
input [TABLE_ENTRY_WIDTH-1 : 0] last_table_entry, table_entry;
get_free_res_size
= (table_entry[RES_STRT_H:RES_STRT_L]) -
(last_table_entry[RES_STRT_H:RES_STRT_L]+
last_table_entry[RES_SIZE_H:RES_SIZE_L]);
endfunction // if
function[RES_ID_WIDTH:0] get_free_res_size_last;
input [TABLE_ENTRY_WIDTH-1 : 0] table_entry;
get_free_res_size_last
= NUMBER_RES_SLOTS -
(table_entry[RES_STRT_H:RES_STRT_L]+table_entry[RES_SIZE_H:RES_SIZE_L]);
endfunction // if
// Ram to implement the table
localparam NUM_ENTRIES = NUMBER_CU*(NUMBER_WF_SLOTS_PER_CU+1);
localparam[WG_SLOT_ID_WIDTH-1:0] RES_TABLE_END_TABLE = 2**WG_SLOT_ID_WIDTH-1;
localparam[WG_SLOT_ID_WIDTH-1:0] RES_TABLE_HEAD_POINTER = 2**WG_SLOT_ID_WIDTH-2;
reg [TABLE_ENTRY_WIDTH-1 : 0] resource_table_ram[NUM_ENTRIES-1:0];
reg [WG_SLOT_ID_WIDTH-1 : 0] table_head_pointer[NUMBER_CU-1:0];
reg [WG_SLOT_ID_WIDTH-1 : 0] table_head_pointer_i;
wire [RES_ID_WIDTH-1 : 0] rtwr_res_strt, rtrr_res_strt,
rtne_res_strt, rtlrr_res_strt;
wire [RES_ID_WIDTH : 0] rtwr_res_size, rtrr_res_size,
rtne_res_size, rtlrr_res_size;
wire [TABLE_ENTRY_WIDTH-1 : 0] rtwr_prev_item, rtrr_prev_item,
rtne_prev_item, rtlrr_prev_item;
wire [RES_ID_WIDTH-1 : 0] rtwr_next_item, rtrr_next_item,
rtne_next_item, rtlrr_next_item;
// State machines
// Main state machine
localparam ST_M_IDLE = 1;
localparam ST_M_ALLOC = 2;
localparam ST_M_DEALLOC = 4;
localparam ST_M_FIND_MAX = 8;
reg [3:0] m_state;
// Alloc state machine
localparam ST_A_IDLE = 1;
localparam ST_A_FIND_POSITION = 2;
localparam ST_A_UPDATE_PREV_ENTRY = 4;
localparam ST_A_WRITE_NEW_ENTRY = 8;
reg [3:0] a_state;
// Dealloc state machine
localparam ST_D_IDLE = 1;
localparam ST_D_READ_PREV_ENTRY = 2;
localparam ST_D_READ_NEXT_ENTRY = 4;
localparam ST_D_UPDATE_PREV_ENTRY = 8;
localparam ST_D_UPDATE_NEXT_ENTRY = 16;
reg [4:0] d_state;
// Find max state machine
localparam ST_F_IDLE = 1;
localparam ST_F_FIRST_ITEM = 2;
localparam ST_F_SEARCHING = 4;
localparam ST_F_LAST_ITEM = 8;
reg [3:0] f_state;
// Datapath regs
reg [TABLE_ENTRY_WIDTH-1 : 0] res_table_wr_reg, res_table_rd_reg;
reg [TABLE_ENTRY_WIDTH-1 : 0] res_table_last_rd_reg;
reg [CU_ID_WIDTH-1:0] res_addr_cu_id;
reg [WG_SLOT_ID_WIDTH-1 : 0] res_addr_wg_slot;
reg res_table_rd_en, res_table_wr_en;
reg res_table_rd_valid;
reg [RES_ID_WIDTH : 0] res_table_max_size;
reg [RES_ID_WIDTH-1 : 0] res_table_max_start;
// Control signals
reg alloc_start, dealloc_start, find_max_start;
reg alloc_done, dealloc_done, find_max_done;
reg new_entry_is_last, new_entry_is_first;
reg rem_entry_is_last, rem_entry_is_first;
reg [NUMBER_CU-1:0] cu_initialized;
reg cu_initialized_i;
assign rtwr_res_strt = get_res_start(res_table_wr_reg);
assign rtrr_res_strt = get_res_start(res_table_rd_reg);
assign rtlrr_res_strt = get_res_start(res_table_last_rd_reg);
assign rtwr_res_size = get_res_size(res_table_wr_reg);
assign rtrr_res_size = get_res_size(res_table_rd_reg);
assign rtlrr_res_size = get_res_size(res_table_last_rd_reg);
assign rtwr_prev_item = get_prev_item_wg_slot(res_table_wr_reg);
assign rtrr_prev_item = get_prev_item_wg_slot(res_table_rd_reg);
assign rtlrr_prev_item = get_prev_item_wg_slot(res_table_last_rd_reg);
assign rtwr_next_item = get_next_item_wg_slot(res_table_wr_reg);
assign rtrr_next_item = get_next_item_wg_slot(res_table_rd_reg);
assign rtlrr_next_item = get_next_item_wg_slot(res_table_last_rd_reg);
// Implements the resouce table
always @(posedge clk or rst) begin
if(rst) begin
m_state = ST_M_IDLE;
a_state = ST_A_IDLE;
d_state = ST_D_IDLE;
f_state = ST_F_IDLE;
alloc_res_en_i <= 0;
alloc_cu_id_i <= 0;
alloc_res_start_i <= 0;
alloc_res_size_i <= 0;
alloc_start <= 0;
alloc_done <= 0;
new_entry_is_first <= 0;
new_entry_is_last <= 0;
dealloc_res_en_i <= 0;
dealloc_cu_id_i <= 0;
dealloc_wg_slot_id_i <= 0;
dealloc_start <= 0;
dealloc_done <= 0;
find_max_start <= 0;
find_max_done <=0;
rem_entry_is_first <= 0;
rem_entry_is_last <= 0;
find_max_done <= 0;
find_max_start <= 0;
res_table_max_size <= 0;
res_table_max_start <= 0;
res_addr_cu_id <= 0;
res_addr_wg_slot <= 0;
table_head_pointer_i <= 0;
res_table_rd_reg <= 0;
res_table_last_rd_reg <= 0;
res_table_rd_en <= 0;
res_table_rd_valid <=0;
res_table_wr_en <= 0;
res_table_wr_reg <= 0;
cu_initialized <= 0;
cu_initialized_i <= 0;
end else begin
// Flop input signals
alloc_res_en_i <= alloc_res_en;
if(alloc_res_en) begin
alloc_cu_id_i <= alloc_cu_id;
alloc_wg_slot_id_i <= alloc_wg_slot_id;
alloc_res_start_i <= alloc_res_start;
alloc_res_size_i <= alloc_res_size;
res_addr_cu_id <= alloc_cu_id;
end
dealloc_res_en_i <= dealloc_res_en;
if(dealloc_res_en) begin
dealloc_cu_id_i <= dealloc_cu_id;
dealloc_wg_slot_id_i <= dealloc_wg_slot_id;
res_addr_cu_id <= dealloc_cu_id;
end
// Main state machine of the resource table
alloc_start <= 1'b0;
dealloc_start <= 1'b0;
find_max_start <= 1'b0;
res_table_done <= 1'b0;
case(m_state)
ST_M_IDLE : begin
if(1'b1 == alloc_res_en_i) begin
alloc_start <= 1'b1;
m_state <= ST_M_ALLOC;
end else if(1'b1 == dealloc_res_en_i) begin
dealloc_start <= 1'b1;
m_state <= ST_M_DEALLOC;
end
end
/////////////////////////////////////////////////
ST_M_ALLOC : begin
if(1'b1 == alloc_done) begin
find_max_start <= 1'b1;
m_state <= ST_M_FIND_MAX;
end
end
/////////////////////////////////////////////////
ST_M_DEALLOC : begin
if(1'b1 == dealloc_done) begin
find_max_start <= 1'b1;
m_state <= ST_M_FIND_MAX;
end
end
/////////////////////////////////////////////////
ST_M_FIND_MAX : begin
if(1'b1 == find_max_done) begin
res_table_done <= 1'b1;
m_state <= ST_M_IDLE;
end
end
/////////////////////////////////////////////////
endcase // case (m_state)
// All state machines share the same resource (the table) so,
// there can be onle one machine out of IDLE state at a given time.
res_table_rd_en <= 1'b0;
res_table_wr_en <= 1'b0;
alloc_done <= 1'b0;
// Alloc state machine
case(a_state)
ST_A_IDLE : begin
// Start looking for the new entry positon on
// head_position
if( alloc_start ) begin
// Table is clear or cu was not initialized
if( (table_head_pointer_i == RES_TABLE_END_TABLE) ||
!cu_initialized_i) begin
new_entry_is_first <= 1'b1;
new_entry_is_last <= 1'b1;
a_state <= ST_A_WRITE_NEW_ENTRY;
// Otherwise we have to find a position
end else begin
new_entry_is_last <= 1'b0;
new_entry_is_first <= 1'b0;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= table_head_pointer_i;
a_state <= ST_A_FIND_POSITION;
end
end // if ( alloc_start )
end // case: ST_A_IDLE
ST_A_FIND_POSITION : begin
// Look for the entry postion
if( res_table_rd_valid ) begin
// Found the entry that will be after the new one
if( get_res_start(res_table_rd_reg) > alloc_res_start_i ) begin
// if new entry will be the first entry
if( get_prev_item_wg_slot(res_table_rd_reg) ==
RES_TABLE_HEAD_POINTER) begin
new_entry_is_first <= 1'b1;
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_prev_item_wg_slot(alloc_wg_slot_id_i,
res_table_rd_reg);
a_state <= ST_A_WRITE_NEW_ENTRY;
end
// Normal case
else begin
// Update this entry
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_prev_item_wg_slot(alloc_wg_slot_id_i,
res_table_rd_reg);
a_state <= ST_A_UPDATE_PREV_ENTRY;
end // else: !if( get_prev_item_wg_slot(res_table_rd_reg) ==...
end // if ( get_res_start(res_table_rd_reg) > alloc_res_start_i )
// The new entry will be the last entry
else if( get_next_item_wg_slot(res_table_rd_reg) ==
RES_TABLE_END_TABLE ) begin
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_next_item_wg_slot(alloc_wg_slot_id_i,res_table_rd_reg);
new_entry_is_last <= 1'b1;
a_state <= ST_A_WRITE_NEW_ENTRY;
end
// Keep looking for the entry postion
else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
end // else: !if( get_next_item_wg_slot(res_table_rd_reg) ==...
end // if ( res_table_rd_valid )
end // case: ST_A_FIND_POSITION
ST_A_UPDATE_PREV_ENTRY : begin
// Update the entry that will be before the new one
res_table_wr_en <= 1'b1;
res_table_wr_reg
<= set_next_item_wg_slot(alloc_wg_slot_id_i,
res_table_last_rd_reg);
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
a_state <= ST_A_WRITE_NEW_ENTRY;
end
ST_A_WRITE_NEW_ENTRY : begin
if( new_entry_is_first ) begin
table_head_pointer_i <= alloc_wg_slot_id_i;
end
// Write the new entry
res_table_wr_en <= 1'b1;
res_addr_wg_slot <= alloc_wg_slot_id_i;
if( new_entry_is_first && new_entry_is_last ) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
RES_TABLE_HEAD_POINTER,
RES_TABLE_END_TABLE);
end
else if( new_entry_is_last ) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
res_addr_wg_slot,
RES_TABLE_END_TABLE);
end
else if(new_entry_is_first) begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
RES_TABLE_HEAD_POINTER,
res_addr_wg_slot);
end
else begin
res_table_wr_reg
<= get_new_entry(alloc_res_start_i, alloc_res_size_i,
res_addr_wg_slot,
get_next_item_wg_slot(res_table_last_rd_reg));
end // else: !if( new_entry_is_last )
alloc_done <= 1'b1;
a_state <= ST_A_IDLE;
end
endcase // case (a_state)
// Dealloc state machine
dealloc_done <= 1'b0;
case(d_state)
ST_D_IDLE: begin
if( dealloc_start ) begin
rem_entry_is_last <= 1'b0;
rem_entry_is_first <= 1'b0;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= dealloc_wg_slot_id_i;
d_state <= ST_D_READ_PREV_ENTRY;
end
end
ST_D_READ_PREV_ENTRY : begin
if (res_table_rd_valid ) begin
// We are removing the last remaining entry on the table
if( (get_prev_item_wg_slot(res_table_rd_reg)
== RES_TABLE_HEAD_POINTER) &&
(get_next_item_wg_slot(res_table_rd_reg)
== RES_TABLE_END_TABLE)) begin
table_head_pointer_i <= RES_TABLE_END_TABLE;
dealloc_done <= 1'b1;
d_state <= ST_D_IDLE;
// We are removing the first entry on the table
end else if(get_prev_item_wg_slot(res_table_rd_reg)
== RES_TABLE_HEAD_POINTER) begin
rem_entry_is_first <= 1'b1;
d_state <= ST_D_READ_NEXT_ENTRY;
// We are removing the last entry on the table
end else if (get_next_item_wg_slot(res_table_rd_reg)
== RES_TABLE_END_TABLE) begin
rem_entry_is_last <= 1'b1;
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_UPDATE_PREV_ENTRY;
// We are a normal entry
end else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_READ_NEXT_ENTRY;
end
end // if (res_table_rd_valid )
end // case: ST_D_READ_PREV_ENTRY
ST_D_READ_NEXT_ENTRY : begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
d_state <= ST_D_UPDATE_PREV_ENTRY;
end
ST_D_UPDATE_PREV_ENTRY : begin
// In this cycle it is reading the next entry, so we can use the
// the addr_reg to get our the next entry addr
// Single cycle delay to complete reading if the entry if the entry
// is the first or the last
if(rem_entry_is_first) begin
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end else if(rem_entry_is_last) begin
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end else begin
res_table_wr_en <= 1'b1;
res_addr_wg_slot <= get_prev_item_wg_slot(res_table_last_rd_reg);
res_table_wr_reg
<= set_next_item_wg_slot(res_addr_wg_slot,
res_table_rd_reg);
d_state <= ST_D_UPDATE_NEXT_ENTRY;
end // else: !if(rem_entry_is_last)
end // case: ST_D_UPDATE_PREV_ENTRY
ST_D_UPDATE_NEXT_ENTRY : begin
// In this cycle it is writing the previous entry, so we can use the
// the addr_reg to get our the next entry addr
res_table_wr_en <= 1'b1;
if( rem_entry_is_first ) begin
table_head_pointer_i <= res_addr_wg_slot;
res_table_wr_reg
<= set_prev_item_wg_slot(RES_TABLE_HEAD_POINTER,
res_table_rd_reg);
end else if ( rem_entry_is_last ) begin
res_table_wr_en <= 1'b1;
// No need to update addr, we are writing the
// entry we just read
res_table_wr_reg
<= set_next_item_wg_slot(RES_TABLE_END_TABLE,
res_table_rd_reg);
end else begin
res_addr_wg_slot <= get_next_item_wg_slot(res_table_wr_reg);
res_table_wr_reg
<= set_prev_item_wg_slot(res_addr_wg_slot,
res_table_rd_reg);
end
dealloc_done <= 1'b1;
d_state <= ST_D_IDLE;
end // case: ST_D_UPDATE_NEXT_ENTRY
endcase
// Find max state machine
find_max_done <= 1'b0;
case(f_state)
ST_F_IDLE : begin
if( find_max_start ) begin
// Zero the max res size reg
res_table_max_size <= 0;
// In case table is clear, return 0 and finish
if(table_head_pointer_i == RES_TABLE_END_TABLE) begin
res_table_max_size
<= NUMBER_RES_SLOTS;
res_table_max_start
<= 0;
find_max_done <= 1'b1;
// otherwise start searching
end else begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= table_head_pointer_i;
f_state <= ST_F_FIRST_ITEM;
end
end // if ( find_max_start )
end // case: ST_F_IDLE
ST_F_FIRST_ITEM: begin
// only read first item. If it is alst the last, skip
// the searching state
if( res_table_rd_valid ) begin
res_table_max_size
<= get_res_start(res_table_rd_reg);
res_table_max_start
<= 0;
// check if it is in the end o of the table
if( get_next_item_wg_slot(res_table_rd_reg) !=
RES_TABLE_END_TABLE) begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
f_state <= ST_F_SEARCHING;
end else begin
f_state <= ST_F_LAST_ITEM;
end
end // if ( res_table_rd_valid )
end // case: ST_F_FIRST_ITEM
ST_F_SEARCHING : begin
if( res_table_rd_valid ) begin
// check if it is in the end o of the table
if( get_next_item_wg_slot(res_table_rd_reg) !=
RES_TABLE_END_TABLE) begin
res_table_rd_en <= 1'b1;
res_addr_wg_slot <= get_next_item_wg_slot(res_table_rd_reg);
end else begin
f_state <= ST_F_LAST_ITEM;
end
// check if this is the max res size
if( get_free_res_size(res_table_last_rd_reg, res_table_rd_reg) >
res_table_max_size) begin
res_table_max_size
<= get_free_res_size(res_table_last_rd_reg, res_table_rd_reg);
res_table_max_start
<= get_free_res_start(res_table_last_rd_reg);
end
end // if ( res_table_rd_valid )
end // case: ST_F_SEARCHING
ST_F_LAST_ITEM : begin
// calculate the free space for the last item
if( get_free_res_size_last(res_table_rd_reg) >
res_table_max_size) begin
res_table_max_size
<= get_free_res_size_last(res_table_rd_reg);
res_table_max_start
<= get_free_res_start(res_table_rd_reg);
end
find_max_done <= 1'b1;
f_state <= ST_F_IDLE;
end // case: ST_F_LAST_ITEM
endcase
// Data path of the resource table
if( alloc_res_en_i || dealloc_res_en_i ) begin
// Read the head pointer at the start
cu_initialized_i <= cu_initialized[res_addr_cu_id];
table_head_pointer_i <= table_head_pointer[res_addr_cu_id];
end else if (alloc_done || dealloc_done) begin
// Write at the end
table_head_pointer[res_addr_cu_id] <= table_head_pointer_i;
cu_initialized[res_addr_cu_id] <= 1'b1;
end
res_table_rd_valid <= res_table_rd_en;
if( res_table_rd_en ) begin
res_table_rd_reg
<= resource_table_ram[calc_table_addr(res_addr_cu_id,
res_addr_wg_slot)];
res_table_last_rd_reg <= res_table_rd_reg;
end else if (res_table_wr_en) begin
resource_table_ram[calc_table_addr(res_addr_cu_id, res_addr_wg_slot)]
<= res_table_wr_reg;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
assign cam_biggest_space_size = res_table_max_size;
assign cam_biggest_space_addr = res_table_max_start;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
|
Require Import
FormTopC.FormTop
Algebra.SetsC
Algebra.OrderC.
Module JoinTop.
Section JoinTop.
(** We assume we have some type [S] equipped
with a partial order. *)
(** NO! This context gives us two (different) preorders on S.
Will need to fix this. *)
Context {S : PreSpace.t} {ops : JoinLat.Ops S} {JL : JoinLat.t S ops}.
Variable bot : S.
Local Open Scope FT.
Class t : Type :=
{ FT :> FormTop.t S
; bot_ok : @PreO.bottom _ JoinLat.le bot
; bot_Cov : forall U, bot <| U
; join_left : forall a b U, a <| U -> b <| U -> JoinLat.max a b <| U
}.
Hypothesis FTS : t.
(** Check properties we expect to hold *)
Definition singleton (s s' : S) : Prop := s = s'.
Lemma join_right : forall a b c, a <| (singleton b)
-> a <| singleton (JoinLat.max b c).
Proof.
intros. eapply FormTop.trans. apply X. clear X. clear a.
intros a sba. unfold singleton in sba. subst.
apply FormTop.le_left with (JoinLat.max a c).
apply JoinLat.max_ok.
apply FormTop.refl. unfold In in *. subst. reflexivity.
Qed.
End JoinTop.
(** Given a formal topology, we can always produce a join-closed formal
topology by taking "free join" elements (i.e., the free monoid, a list)
and interpreting the cover relation accordingly.
*)
Require Import Coq.Lists.List Types.List.
Section Joinify.
Context {S} {le : S -> Subset S} {PO : PreO.t le}.
Definition leL (xs ys : list S) := forall x,
member x xs -> { y : S & (le x y * member y ys)%type }.
Definition eqL (xs ys : list S) : Type := leL xs ys * leL ys xs.
Definition joinL (xs ys : list S) : list S := xs ++ ys.
Definition ops' : JoinLat.Ops (list S) :=
{| JoinLat.le := leL
; JoinLat.eq := eqL
; JoinLat.max := joinL
|}.
Instance ops : JoinLat.Ops (list S) := ops'.
Require Import CMorphisms.
Instance joinPreO : @PreO.t (list S) leL.
Proof.
constructor; intros.
- simpl. unfold leL. intros. exists x0.
split. apply PreO.le_refl. assumption.
- simpl in *. unfold leL in *. intros.
destruct (X x0 X1). destruct p.
destruct (X0 x1 m). destruct p.
exists x2. split. eapply PreO.le_trans; eassumption.
assumption.
Qed.
Instance joinPO : @PO.t (list S) leL JoinLat.eq.
Proof.
constructor.
- apply joinPreO.
- repeat intro.
destruct X, X0. split; intros.
transitivity x. assumption. transitivity x0; eassumption.
transitivity y; try assumption. transitivity y0; eassumption.
- intros. split; assumption.
Qed.
Lemma joinLE (xs ys xs' ys' : list S) : leL xs xs' -> leL ys ys'
-> leL (xs ++ ys) (xs' ++ ys').
Proof.
unfold leL in *.
intros H H0 x H1.
apply member_app in H1.
destruct H1 as [In1 | In2].
- destruct (H x In1). exists x0. destruct p.
split. assumption. apply member_app. left. assumption.
- destruct (H0 x In2). exists x0. destruct p.
split. assumption. apply member_app. right. assumption.
Qed.
Theorem JL : JoinLat.t (list S) ops.
Proof.
constructor.
- apply joinPO.
- repeat intro. simpl in *. unfold joinL.
unfold eqL in *. destruct X, X0.
auto using joinLE.
- intros. simpl. unfold joinL. constructor; unfold leL; intros.
+ exists x. split. apply PreO.le_refl. apply member_app. auto.
+ exists x. split. apply PreO.le_refl. apply member_app. auto.
+ apply member_app in X1. destruct X1; [apply X | apply X0]; assumption.
Qed.
Variable Cov : S -> (Subset S) -> Prop.
Definition LCov (a : list S) (U : Subset (list S)) :=
forall s : S, member s a -> Cov s (fun s' => { xs : list S & (member s' xs * U xs)%type }).
Instance joinify : FormTop.t le Cov -> t nil LCov.
Proof.
intros FTS.
constructor.
- constructor.
+ unfold LCov. intros. apply FormTop.refl.
exists a. split; assumption.
+ unfold LCov. intros. eapply FormTop.trans.
eapply H. assumption. simpl.
clear s X. intros.
destruct X as (xs & Inxs & Uxs).
eapply H0. eassumption. assumption.
+ simpl. unfold LCov. intros. unfold leL in *.
specialize (X s X0). destruct X as (y & sy & Inyb).
apply FormTop.le_left with y. assumption.
apply H. assumption.
+ unfold LCov. intros.
pose proof (fun (s' : S) (insa : member s' a) =>
@FormTop.le_right _ _ _ _ s' _ _ (H s' insa) (H0 s' insa)).
eapply FormTop.monotone. 2: apply (H1 s X). simpl.
unfold Included, pointwise_rel, arrow; intros.
destruct X0. destruct d, d0. unfold flip, SetsC.In in *.
destruct i as (xs & Inxs & Uxs).
destruct i0 as (ys & Inys & Vys).
exists (cons a0 nil). split. left.
constructor; (econstructor; [eassumption|]);
unfold flip, leL; intros x' inx; simpl in inx; inv inx; subst;
match goal with
| [ H: member ?z ?xs |- { y : _ & (_ * member y ?xs)%type } ] => exists z; split; auto
end.
inv X0. inv X0.
- unfold PreO.bottom. simpl. unfold leL. intros.
inv X.
- unfold LCov. intros. inv X.
- unfold LCov. simpl. unfold joinL. intros.
apply member_app in X. destruct X.
+ apply H; assumption.
+ apply H0; assumption.
Qed.
End Joinify.
End JoinTop.
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
/* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/*
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1)
(* keep *) cycloneiv_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(CO), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
//assign CO = COx[Y_WIDTH];
else
cycloneiv_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
/*assign X = AA ^ BB;
endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneiv_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tb_cmd_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: 7 Series
//Design Name: PRBS_Generator
//Purpose:
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_tg_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 10, // LFSR shift register length
parameter nCK_PER_CLK = 4 // output:internal clock freq ratio
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
output [2*nCK_PER_CLK-1:0] prbs_o, // generated address
// ReSeedcounter used to indicate when pseudo-PRBS sequence has reached
// the end of it's cycle. May not be needed, but for now included to
// maintain compatibility with current TG code
output [31:0] ReSeedcounter_o
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK);
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg [PRBS_WIDTH-1:0] lfsr_reg_r;
wire [PRBS_WIDTH-1:0] next_lfsr_reg;
reg [PRBS_WIDTH-1:0] reseed_cnt_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
genvar i;
//***************************************************************************
assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r};
always @ (posedge clk_i)
if (rst_i)
reseed_cnt_r <= 'b0;
else if (clk_en_i)
if (reseed_cnt_r == {PRBS_WIDTH {1'b1}})
reseed_cnt_r <= 'b0;
else
reseed_cnt_r <= reseed_cnt_r + 1;
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
if (rst_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
// Load initial seed or update LFSR contents
always @(posedge clk_i)
if (rst_i)
lfsr_reg_r <= #TCQ prbs_seed_i;
else if (clk_en_i)
if (reseed_prbs_r)
lfsr_reg_r <= #TCQ prbs_seed_i;
else begin
lfsr_reg_r <= #TCQ next_lfsr_reg;
end
// Calculate next set of nCK_PER_CLK samplse for LFSR
// Basically we calculate all PRBS_WIDTH samples in parallel, rather
// than serially shifting the LFSR to determine future sample values.
// Shifting is possible, but requires multiple shift registers to be
// instantiated because the fabric clock frequency is running at a
// fraction of the output clock frequency
generate
if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]) ;
assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^
lfsr_reg_r[0] ^ next_lfsr_reg[7]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^
next_lfsr_reg[7] ^ next_lfsr_reg[6]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^
next_lfsr_reg[6] ^ next_lfsr_reg[5]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^
next_lfsr_reg[5] ^ next_lfsr_reg[4]);
end
end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[9] = lfsr_reg_r[5];
assign next_lfsr_reg[8] = lfsr_reg_r[4];
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[9] = lfsr_reg_r[1];
assign next_lfsr_reg[8] = lfsr_reg_r[0];
assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]);
end
end
endgenerate
// Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest"
// tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first
// data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be
// routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the
// output, etc.
generate
for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose
assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i];
end
endgenerate
endmodule
|
/**************************************************************************
Sync FIFO
-parameter N
Queue data vector width
Example : DATA[3:0] is N=4
-parameter DEPTH
Queue entry depth
Example DEPTH 16 is DEPTH=16
-parameter D_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032isa_sync_fifo
#(
parameter N = 16,
parameter DEPTH = 4,
parameter D_N = 2
)(
//System
input wire iCLOCK,
input wire inRESET,
input wire iREMOVE,
//Counter
output wire [D_N-1:0] oCOUNT,
//WR
input wire iWR_EN,
input wire [N-1:0] iWR_DATA,
output wire oWR_FULL,
//RD
input wire iRD_EN,
output wire [N-1:0] oRD_DATA,
output wire oRD_EMPTY
);
//Count - Wire
wire [D_N:0] count;
//Reg
reg [D_N:0] b_write_pointer;
reg [D_N:0] b_read_pointer;
reg [N-1:0] b_memory [0 : DEPTH-1];
assign count = b_write_pointer - b_read_pointer;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_write_pointer <= {D_N+1{1'b0}};
b_read_pointer <= {D_N+1{1'b0}};
end
else if(iREMOVE)begin
b_write_pointer <= {D_N+1{1'b0}};
b_read_pointer <= {D_N+1{1'b0}};
end
else begin
if(iWR_EN)begin
b_write_pointer <= b_write_pointer + {{D_N-1{1'b0}}, 1'b1};
b_memory [b_write_pointer[D_N-1:0]] <= iWR_DATA;
end
if(iRD_EN)begin
b_read_pointer <= b_read_pointer + {{D_N-1{1'b0}}, 1'b1};
end
end
end //always
//Assign
assign oRD_DATA = b_memory [b_read_pointer[D_N-1:0]];
assign oRD_EMPTY = ((b_write_pointer - b_read_pointer) == {D_N+1{1'b0}})? 1'b1 : 1'b0;
assign oWR_FULL = count[D_N];//|| (count [D_N-1:0] == {D_N{1'b1}})? 1'b1 : 1'b0;
assign oCOUNT = count [D_N-1:0];
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blockram.v when simulating
// the core, blockram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blockram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [5 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input [0 : 0] web;
input [5 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(6),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(64),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(64),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
// Module handles updating the loopy scroll register
module LoopyGen(input clk, input ce,
input is_rendering,
input [2:0] ain, // input address from CPU
input [7:0] din, // data input
input read, // read
input write, // write
input is_pre_render, // Is this the pre-render scanline
input [8:0] cycle,
output [14:0] loopy,
output [2:0] fine_x_scroll); // Current loopy value
// Controls how much to increment on each write
reg ppu_incr; // 0 = 1, 1 = 32
// Current VRAM address
reg [14:0] loopy_v;
// Temporary VRAM address
reg [14:0] loopy_t;
// Fine X scroll (3 bits)
reg [2:0] loopy_x;
// Latch
reg ppu_address_latch;
initial begin
ppu_incr = 0;
loopy_v = 0;
loopy_t = 0;
loopy_x = 0;
ppu_address_latch = 0;
end
// Handle updating loopy_t and loopy_v
always @(posedge clk) if (ce) begin
if (is_rendering) begin
// Increment course X scroll right after attribute table byte was fetched.
if (cycle[2:0] == 3 && (cycle < 256 || cycle >= 320 && cycle < 336)) begin
loopy_v[4:0] <= loopy_v[4:0] + 1;
loopy_v[10] <= loopy_v[10] ^ (loopy_v[4:0] == 31);
end
// Vertical Increment
if (cycle == 251) begin
loopy_v[14:12] <= loopy_v[14:12] + 1;
if (loopy_v[14:12] == 7) begin
if (loopy_v[9:5] == 29) begin
loopy_v[9:5] <= 0;
loopy_v[11] <= !loopy_v[11];
end else begin
loopy_v[9:5] <= loopy_v[9:5] + 1;
end
end
end
// Horizontal Reset at cycle 257
if (cycle == 256)
{loopy_v[10], loopy_v[4:0]} <= {loopy_t[10], loopy_t[4:0]};
// On cycle 256 of each scanline, copy horizontal bits from loopy_t into loopy_v
// On cycle 304 of the pre-render scanline, copy loopy_t into loopy_v
if (cycle == 304 && is_pre_render) begin
loopy_v <= loopy_t;
end
end
if (write && ain == 0) begin
loopy_t[10] <= din[0];
loopy_t[11] <= din[1];
ppu_incr <= din[2];
end else if (write && ain == 5) begin
if (!ppu_address_latch) begin
loopy_t[4:0] <= din[7:3];
loopy_x <= din[2:0];
end else begin
loopy_t[9:5] <= din[7:3];
loopy_t[14:12] <= din[2:0];
end
ppu_address_latch <= !ppu_address_latch;
end else if (write && ain == 6) begin
if (!ppu_address_latch) begin
loopy_t[13:8] <= din[5:0];
loopy_t[14] <= 0;
end else begin
loopy_t[7:0] <= din;
loopy_v <= {loopy_t[14:8], din};
end
ppu_address_latch <= !ppu_address_latch;
end else if (read && ain == 2) begin
ppu_address_latch <= 0; //Reset PPU address latch
end else if ((read || write) && ain == 7 && !is_rendering) begin
// Increment address every time we accessed a reg
loopy_v <= loopy_v + (ppu_incr ? 32 : 1);
end
end
assign loopy = loopy_v;
assign fine_x_scroll = loopy_x;
endmodule
// Generates the current scanline / cycle counters
module ClockGen(input clk, input ce, input reset,
input is_rendering,
output reg [8:0] scanline,
output reg [8:0] cycle,
output reg is_in_vblank,
output end_of_line,
output at_last_cycle_group,
output exiting_vblank,
output entering_vblank,
output reg is_pre_render);
reg second_frame;
// Scanline 0..239 = picture scan lines
// Scanline 240 = dummy scan line
// Scanline 241..260 = VBLANK
// Scanline -1 = Pre render scanline (Fetches objects for next line)
assign at_last_cycle_group = (cycle[8:3] == 42);
// Every second pre-render frame is only 340 cycles instead of 341.
assign end_of_line = at_last_cycle_group && cycle[3:0] == (is_pre_render && second_frame && is_rendering ? 3 : 4);
// Set the clock right before vblank begins
assign entering_vblank = end_of_line && scanline == 240;
// Set the clock right before vblank ends
assign exiting_vblank = end_of_line && scanline == 260;
// New value for is_in_vblank flag
wire new_is_in_vblank = entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank;
// Set if the current line is line 0..239
always @(posedge clk) if (reset) begin
cycle <= 0;
is_in_vblank <= 1;
end else if (ce) begin
cycle <= end_of_line ? 0 : cycle + 1;
is_in_vblank <= new_is_in_vblank;
end
// always @(posedge clk) if (ce) begin
// $write("%x %x %x %x %x\n", new_is_in_vblank, entering_vblank, exiting_vblank, is_in_vblank, entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank);
// end
always @(posedge clk) if (reset) begin
scanline <= 0;
is_pre_render <= 0;
second_frame <= 0;
end else if (ce && end_of_line) begin
// Once the scanline counter reaches end of 260, it gets reset to -1.
scanline <= exiting_vblank ? 9'b111111111 : scanline + 1;
// The pre render flag is set while we're on scanline -1.
is_pre_render <= exiting_vblank;
if (exiting_vblank)
second_frame <= !second_frame;
end
endmodule // ClockGen
// 8 of these exist, they are used to output sprites.
module Sprite(input clk, input ce,
input enable,
input [3:0] load,
input [26:0] load_in,
output [26:0] load_out,
output [4:0] bits); // Low 4 bits = pixel, high bit = prio
reg [1:0] upper_color; // Upper 2 bits of color
reg [7:0] x_coord; // X coordinate where we want things
reg [7:0] pix1, pix2; // Shift registers, output when x_coord == 0
reg aprio; // Current prio
wire active = (x_coord == 0);
always @(posedge clk) if (ce) begin
if (enable) begin
if (!active) begin
// Decrease until x_coord is zero.
x_coord <= x_coord - 8'h01;
end else begin
pix1 <= pix1 >> 1;
pix2 <= pix2 >> 1;
end
end
if (load[3]) pix1 <= load_in[26:19];
if (load[2]) pix2 <= load_in[18:11];
if (load[1]) x_coord <= load_in[10:3];
if (load[0]) {upper_color, aprio} <= load_in[2:0];
end
assign bits = {aprio, upper_color, active && pix2[0], active && pix1[0]};
assign load_out = {pix1, pix2, x_coord, upper_color, aprio};
endmodule // SpriteGen
// This contains all 8 sprites. Will return the pixel value of the highest prioritized sprite.
// When load is set, and clocked, load_in is loaded into sprite 7 and all others are shifted down.
// Sprite 0 has highest prio.
// 226 LUTs, 68 Slices
module SpriteSet(input clk, input ce, // Input clock
input enable, // Enable pixel generation
input [3:0] load, // Which parts of the state to load/shift.
input [26:0] load_in, // State to load with
output [4:0] bits, // Output bits
output is_sprite0); // Set to true if sprite #0 was output
wire [26:0] load_out7, load_out6, load_out5, load_out4, load_out3, load_out2, load_out1, load_out0;
wire [4:0] bits7, bits6, bits5, bits4, bits3, bits2, bits1, bits0;
Sprite sprite7(clk, ce, enable, load, load_in, load_out7, bits7);
Sprite sprite6(clk, ce, enable, load, load_out7, load_out6, bits6);
Sprite sprite5(clk, ce, enable, load, load_out6, load_out5, bits5);
Sprite sprite4(clk, ce, enable, load, load_out5, load_out4, bits4);
Sprite sprite3(clk, ce, enable, load, load_out4, load_out3, bits3);
Sprite sprite2(clk, ce, enable, load, load_out3, load_out2, bits2);
Sprite sprite1(clk, ce, enable, load, load_out2, load_out1, bits1);
Sprite sprite0(clk, ce, enable, load, load_out1, load_out0, bits0);
// Determine which sprite is visible on this pixel.
assign bits = bits0[1:0] != 0 ? bits0 :
bits1[1:0] != 0 ? bits1 :
bits2[1:0] != 0 ? bits2 :
bits3[1:0] != 0 ? bits3 :
bits4[1:0] != 0 ? bits4 :
bits5[1:0] != 0 ? bits5 :
bits6[1:0] != 0 ? bits6 :
bits7;
assign is_sprite0 = bits0[1:0] != 0;
endmodule // SpriteSet
module SpriteRAM(input clk, input ce,
input reset_line, // OAM evaluator needs to be reset before processing is started.
input sprites_enabled, // Set to 1 if evaluations are enabled
input exiting_vblank, // Set to 1 when exiting vblank so spr_overflow can be reset
input obj_size, // Set to 1 if objects are 16 pixels.
input [8:0] scanline, // Current scan line (compared against Y)
input [8:0] cycle, // Current cycle.
output reg [7:0] oam_bus, // Current value on the OAM bus, returned to NES through $2004.
input oam_ptr_load, // Load oam with specified value, when writing to NES $2003.
input oam_load, // Load oam_ptr with specified value, when writing to NES $2004.
input [7:0] data_in, // New value for oam or oam_ptr
output reg spr_overflow, // Set to true if we had more than 8 objects on a scan line. Reset when exiting vblank.
output reg sprite0); // True if sprite#0 is included on the scan line currently being painted.
reg [7:0] sprtemp[0:31]; // Sprite Temporary Memory. 32 bytes.
reg [7:0] oam[0:255]; // Sprite OAM. 256 bytes.
reg [7:0] oam_ptr; // Pointer into oam_ptr.
reg [2:0] p; // Upper 3 bits of pointer into temp, the lower bits are oam_ptr[1:0].
reg [1:0] state; // Current state machine state
wire [7:0] oam_data = oam[oam_ptr];
// Compute the current address we read/write in sprtemp.
reg [4:0] sprtemp_ptr;
// Check if the current Y coordinate is inside.
wire [8:0] spr_y_coord = scanline - {1'b0, oam_data};
wire spr_is_inside = (spr_y_coord[8:4] == 0) && (obj_size || spr_y_coord[3] == 0);
reg [7:0] new_oam_ptr; // [wire] New value for oam ptr
reg [1:0] oam_inc; // [wire] How much to increment oam ptr
reg sprite0_curr; // If sprite0 is included on the line being processed.
reg oam_wrapped; // [wire] if new_oam or new_p wrapped.
wire [7:0] sprtemp_data = sprtemp[sprtemp_ptr];
always @* begin
// Compute address to read/write in temp sprite ram
casez({cycle[8], cycle[2]})
2'b0_?: sprtemp_ptr = {p, oam_ptr[1:0]};
2'b1_0: sprtemp_ptr = {cycle[5:3], cycle[1:0]}; // 1-4. Read Y, Tile, Attribs
2'b1_1: sprtemp_ptr = {cycle[5:3], 2'b11}; // 5-8. Keep reading X.
endcase
end
always @* begin
/* verilator lint_off CASEOVERLAP */
// Compute value to return to cpu through $2004. And also the value that gets written to temp sprite ram.
casez({sprites_enabled, cycle[8], cycle[6], state, oam_ptr[1:0]})
7'b1_10_??_??: oam_bus = sprtemp_data; // At cycle 256-319 we output what's in sprite temp ram
7'b1_??_00_??: oam_bus = 8'b11111111; // On the first 64 cycles (while inside state 0), we output 0xFF.
7'b1_??_01_00: oam_bus = {4'b0000, spr_y_coord[3:0]}; // Y coord that will get written to temp ram.
7'b?_??_??_10: oam_bus = {oam_data[7:5], 3'b000, oam_data[1:0]}; // Bits 2-4 of attrib are always zero when reading oam.
default: oam_bus = oam_data; // Default to outputting from oam.
endcase
end
always @* begin
// Compute incremented oam counters
casez ({oam_load, state, oam_ptr[1:0]})
5'b1_??_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // Always increment by 1 when writing to oam.
5'b0_00_??: oam_inc = 2'b01; // State 0: On the the first 64 cycles we fill temp ram with 0xFF, increment low bits.
5'b0_01_00: oam_inc = {!spr_is_inside, spr_is_inside}; // State 1: Copy Y coordinate and increment oam by 1 if it's inside, otherwise 4.
5'b0_01_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // State 1: Copy remaining 3 bytes of the oam.
// State 3: We've had more than 8 sprites. Set overflow flag if we found a sprite that overflowed.
// NES BUG: It increments both low and high counters.
5'b0_11_??: oam_inc = 2'b11;
// While in the final state, keep incrementing the low bits only until they're zero.
5'b0_10_??: oam_inc = {1'b0, oam_ptr[1:0] != 0};
endcase
/* verilator lint_on CASEOVERLAP */
new_oam_ptr[1:0] = oam_ptr[1:0] + {1'b0, oam_inc[0]};
{oam_wrapped, new_oam_ptr[7:2]} = {1'b0, oam_ptr[7:2]} + {6'b0, oam_inc[1]};
end
always @(posedge clk) if (ce) begin
// Some bits of the OAM are hardwired to zero.
if (oam_load)
oam[oam_ptr] <= (oam_ptr & 3) == 2 ? data_in & 8'hE3: data_in;
if (cycle[0] && sprites_enabled || oam_load || oam_ptr_load) begin
oam_ptr <= oam_ptr_load ? data_in : new_oam_ptr;
end
// Set overflow flag?
if (sprites_enabled && state == 2'b11 && spr_is_inside)
spr_overflow <= 1;
// Remember if sprite0 is included on the scanline, needed for hit test later.
sprite0_curr <= (state == 2'b01 && oam_ptr[7:2] == 0 && spr_is_inside || sprite0_curr);
// if (scanline == 0 && cycle[0] && (state == 2'b01 || state == 2'b00))
// $write("Drawing sprite %d/%d. bus=%d oam_ptr=%X->%X oam_data=%X p=%d (%d %d %d)\n", scanline, cycle, oam_bus, oam_ptr, new_oam_ptr, oam_data, p,
// cycle[0] && sprites_enabled, oam_load, oam_ptr_load);
// Always writing to temp ram while we're in state 0 or 1.
if (!state[1]) sprtemp[sprtemp_ptr] <= oam_bus;
// Update state machine on every second cycle.
if (cycle[0]) begin
// Increment p whenever oam_ptr carries in state 0 or 1.
if (!state[1] && oam_ptr[1:0] == 2'b11) p <= p + 1;
// Set sprite0 if sprite1 was included on the scan line
casez({state, (p == 7) && (oam_ptr[1:0] == 2'b11), oam_wrapped})
4'b00_0_?: state <= 2'b00; // State #0: Keep filling
4'b00_1_?: state <= 2'b01; // State #0: Until we filled 64 items.
4'b01_?_1: state <= 2'b10; // State #1: Goto State 2 if processed all OAM
4'b01_1_0: state <= 2'b11; // State #1: Goto State 3 if we found 8 sprites
4'b01_0_0: state <= 2'b01; // State #1: Keep comparing Y coordinates.
4'b11_?_1: state <= 2'b10; // State #3: Goto State 2 if processed all OAM
4'b11_?_0: state <= 2'b11; // State #3: Keep comparing Y coordinates
4'b10_?_?: state <= 2'b10; // Stuck in state 2.
endcase
end
if (reset_line) begin
state <= 0;
p <= 0;
oam_ptr <= 0;
sprite0_curr <= 0;
sprite0 <= sprite0_curr;
end
if (exiting_vblank)
spr_overflow <= 0;
end
endmodule // SpriteRAM
// Generates addresses in VRAM where we'll fetch sprite graphics from,
// and populates load, load_in so the SpriteGen can be loaded.
// 10 LUT, 4 Slices
module SpriteAddressGen(input clk, input ce,
input enabled, // If unset, |load| will be all zeros.
input obj_size, // 0: Sprite Height 8, 1: Sprite Height 16.
input obj_patt, // Object pattern table selection
input [2:0] cycle, // Current load cycle. At #4, first bitmap byte is loaded. At #6, second bitmap byte is.
input [7:0] temp, // Input temp data from SpriteTemp. #0 = Y Coord, #1 = Tile, #2 = Attribs, #3 = X Coord
output [12:0] vram_addr,// Low bits of address in VRAM that we'd like to read.
input [7:0] vram_data, // Byte of VRAM in the specified address
output [3:0] load, // Which subset of load_in that is now valid, will be loaded into SpritesGen.
output [26:0] load_in); // Bits to load into SpritesGen.
reg [7:0] temp_tile; // Holds the tile that we will get
reg [3:0] temp_y; // Holds the Y coord (will be swapped based on FlipY).
reg flip_x, flip_y; // If incoming bitmap data needs to be flipped in the X or Y direction.
wire load_y = (cycle == 0);
wire load_tile = (cycle == 1);
wire load_attr = (cycle == 2) && enabled;
wire load_x = (cycle == 3) && enabled;
wire load_pix1 = (cycle == 5) && enabled;
wire load_pix2 = (cycle == 7) && enabled;
reg dummy_sprite; // Set if attrib indicates the sprite is invalid.
// Flip incoming vram data based on flipx. Zero out the sprite if it's invalid. The bits are already flipped once.
wire [7:0] vram_f = dummy_sprite ? 0 :
!flip_x ? {vram_data[0], vram_data[1], vram_data[2], vram_data[3], vram_data[4], vram_data[5], vram_data[6], vram_data[7]} :
vram_data;
wire [3:0] y_f = temp_y ^ {flip_y, flip_y, flip_y, flip_y};
assign load = {load_pix1, load_pix2, load_x, load_attr};
assign load_in = {vram_f, vram_f, temp, temp[1:0], temp[5]};
// If $2000.5 = 0, the tile index data is used as usual, and $2000.3
// selects the pattern table to use. If $2000.5 = 1, the MSB of the range
// result value become the LSB of the indexed tile, and the LSB of the tile
// index value determines pattern table selection. The lower 3 bits of the
// range result value are always used as the fine vertical offset into the
// selected pattern.
assign vram_addr = {obj_size ? temp_tile[0] : obj_patt,
temp_tile[7:1], obj_size ? y_f[3] : temp_tile[0], cycle[1], y_f[2:0] };
always @(posedge clk) if (ce) begin
if (load_y) temp_y <= temp[3:0];
if (load_tile) temp_tile <= temp;
if (load_attr) {flip_y, flip_x, dummy_sprite} <= {temp[7:6], temp[4]};
end
// always @(posedge clk) begin
// if (load[3]) $write("Loading pix1: %x\n", load_in[26:19]);
// if (load[2]) $write("Loading pix2: %x\n", load_in[18:11]);
// if (load[1]) $write("Loading x: %x\n", load_in[10:3]);
//
// if (valid_sprite && enabled)
// $write("%d. Found %d. Flip:%d%d, Addr: %x, Vram: %x!\n", cycle, temp, flip_x, flip_y, vram_addr, vram_data);
// end
endmodule // SpriteAddressGen
module BgPainter(input clk, input ce,
input enable, // Shift registers activated
input [2:0] cycle,
input [2:0] fine_x_scroll,
input [14:0] loopy,
output [7:0] name_table, // VRAM name table to read next.
input [7:0] vram_data,
output [3:0] pixel);
reg [15:0] playfield_pipe_1; // Name table pixel pipeline #1
reg [15:0] playfield_pipe_2; // Name table pixel pipeline #2
reg [8:0] playfield_pipe_3; // Attribute table pixel pipe #1
reg [8:0] playfield_pipe_4; // Attribute table pixel pipe #2
reg [7:0] current_name_table; // Holds the current name table byte
reg [1:0] current_attribute_table; // Holds the 2 current attribute table bits
reg [7:0] bg0; // Pixel data for last loaded background
wire [7:0] bg1 = vram_data;
initial begin
playfield_pipe_1 = 0;
playfield_pipe_2 = 0;
playfield_pipe_3 = 0;
playfield_pipe_4 = 0;
current_name_table = 0;
current_attribute_table = 0;
bg0 = 0;
end
always @(posedge clk) if (ce) begin
case (cycle[2:0])
1: current_name_table <= vram_data;
3: current_attribute_table <= (!loopy[1] && !loopy[6]) ? vram_data[1:0] :
( loopy[1] && !loopy[6]) ? vram_data[3:2] :
(!loopy[1] && loopy[6]) ? vram_data[5:4] :
vram_data[7:6];
5: bg0 <= vram_data; // Pattern table bitmap #0
// 7: bg1 <= vram_data; // Pattern table bitmap #1
endcase
if (enable) begin
playfield_pipe_1[14:0] <= playfield_pipe_1[15:1];
playfield_pipe_2[14:0] <= playfield_pipe_2[15:1];
playfield_pipe_3[7:0] <= playfield_pipe_3[8:1];
playfield_pipe_4[7:0] <= playfield_pipe_4[8:1];
// Load the new values into the shift registers at the last pixel.
if (cycle[2:0] == 7) begin
playfield_pipe_1[15:8] <= {bg0[0], bg0[1], bg0[2], bg0[3], bg0[4], bg0[5], bg0[6], bg0[7]};
playfield_pipe_2[15:8] <= {bg1[0], bg1[1], bg1[2], bg1[3], bg1[4], bg1[5], bg1[6], bg1[7]};
playfield_pipe_3[8] <= current_attribute_table[0];
playfield_pipe_4[8] <= current_attribute_table[1];
end
end
end
assign name_table = current_name_table;
wire [3:0] i = {1'b0, fine_x_scroll};
assign pixel = {playfield_pipe_4[i], playfield_pipe_3[i],
playfield_pipe_2[i], playfield_pipe_1[i]};
endmodule // BgPainter
module PixelMuxer(input [3:0] bg, input [3:0] obj, input obj_prio, output [3:0] out, output is_obj);
wire bg_flag = bg[0] | bg[1];
wire obj_flag = obj[0] | obj[1];
assign is_obj = !(obj_prio && bg_flag) && obj_flag;
assign out = is_obj ? obj : bg;
endmodule
module PaletteRam(input clk, input ce, input [4:0] addr, input [5:0] din, output [5:0] dout, input write);
reg [5:0] palette [0:31];
initial begin
$readmemh("oam_palette.txt", palette);
end
// Force read from backdrop channel if reading from any addr 0.
wire [4:0] addr2 = (addr[1:0] == 0) ? 0 : addr;
assign dout = palette[addr2];
always @(posedge clk) if (ce && write) begin
// Allow writing only to x0
if (!(addr[3:2] != 0 && addr[1:0] == 0))
palette[addr2] <= din;
end
endmodule // PaletteRam
module PPU(input clk, input ce, input reset, // input clock 21.48 MHz / 4. 1 clock cycle = 1 pixel
output [5:0] color, // output color value, one pixel outputted every clock
input [7:0] din, // input data from bus
output [7:0] dout, // output data to CPU
input [2:0] ain, // input address from CPU
input read, // read
input write, // write
output nmi, // one while inside vblank
output vram_r, // read from vram active
output vram_w, // write to vram active
output [13:0] vram_a, // vram address
input [7:0] vram_din, // vram input
output [7:0] vram_dout,
output [8:0] scanline,
output [8:0] cycle,
output [19:0] mapper_ppu_flags);
// These are stored in control register 0
reg obj_patt; // Object pattern table
reg bg_patt; // Background pattern table
reg obj_size; // 1 if sprites are 16 pixels high, else 0.
reg vbl_enable; // Enable VBL flag
// These are stored in control register 1
reg grayscale; // Disable color burst
reg playfield_clip; // 0: Left side 8 pixels playfield clipping
reg object_clip; // 0: Left side 8 pixels object clipping
reg enable_playfield; // Enable playfield display
reg enable_objects; // Enable objects display
reg [2:0] color_intensity; // Color intensity
initial begin
obj_patt = 0;
bg_patt = 0;
obj_size = 0;
vbl_enable = 0;
grayscale = 0;
playfield_clip = 0;
object_clip = 0;
enable_playfield = 0;
enable_objects = 0;
color_intensity = 0;
end
reg nmi_occured; // True if NMI has occured but not cleared.
reg [7:0] vram_latch;
// Clock generator
wire is_in_vblank; // True if we're in VBLANK
//wire [8:0] scanline; // Current scanline
//wire [8:0] cycle; // Current cycle inside of the line
wire end_of_line; // At the last pixel of a line
wire at_last_cycle_group; // At the very last cycle group of the scan line.
wire exiting_vblank; // At the very last cycle of the vblank
wire entering_vblank; //
wire is_pre_render_line; // True while we're on the pre render scanline
wire is_rendering = (enable_playfield || enable_objects) && !is_in_vblank && scanline != 240;
ClockGen clock(clk, ce, reset, is_rendering, scanline, cycle, is_in_vblank, end_of_line, at_last_cycle_group,
exiting_vblank, entering_vblank, is_pre_render_line);
// The loopy module handles updating of the loopy address
wire [14:0] loopy;
wire [2:0] fine_x_scroll;
LoopyGen loopy0(clk, ce, is_rendering, ain, din, read, write, is_pre_render_line, cycle, loopy, fine_x_scroll);
// Set to true if the current ppu_addr pointer points into
// palette ram.
wire is_pal_address = (loopy[13:8] == 6'b111111);
// Paints background
wire [7:0] bg_name_table;
wire [3:0] bg_pixel_noblank;
BgPainter bg_painter(clk, ce, !at_last_cycle_group, cycle[2:0], fine_x_scroll, loopy, bg_name_table, vram_din, bg_pixel_noblank);
// Blank out BG in the leftmost 8 pixels?
wire show_bg_on_pixel = (playfield_clip || (cycle[7:3] != 0)) && enable_playfield;
wire [3:0] bg_pixel = {bg_pixel_noblank[3:2], show_bg_on_pixel ? bg_pixel_noblank[1:0] : 2'b00};
// This will set oam_ptr to 0 right before the scanline 240 and keep it there throughout vblank.
wire before_line = (enable_playfield || enable_objects) && (exiting_vblank || end_of_line && !is_in_vblank);
wire [7:0] oam_bus;
wire sprite_overflow;
wire obj0_on_line; // True if sprite#0 is included on the current line
SpriteRAM sprite_ram(clk, ce,
before_line, // Condition for resetting the sprite line state.
is_rendering, // Condition for enabling sprite ram logic. Check so we're not on
exiting_vblank,
obj_size,
scanline, cycle,
oam_bus,
write && (ain == 3), // Write to oam_ptr
write && (ain == 4), // Write to oam[oam_ptr]
din,
sprite_overflow,
obj0_on_line);
wire [4:0] obj_pixel_noblank;
wire [12:0] sprite_vram_addr;
wire is_obj0_pixel; // True if obj_pixel originates from sprite0.
wire [3:0] spriteset_load; // Which subset of the |load_in| to load into SpriteSet
wire [26:0] spriteset_load_in; // Bits to load into SpriteSet
// Between 256..319 (64 cycles), fetches bitmap data for the 8 sprites and fills in the SpriteSet
// so that it can start drawing on the next frame.
SpriteAddressGen address_gen(clk, ce,
cycle[8] && !cycle[6], // Load sprites between 256..319
obj_size, obj_patt, // Object size and pattern table
cycle[2:0], // Cycle counter
oam_bus, // Info from temp buffer.
sprite_vram_addr, // [out] VRAM Address that we want data from
vram_din, // [in] Data at the specified address
spriteset_load,
spriteset_load_in); // Which parts of SpriteGen to load
// Between 0..255 (256 cycles), draws pixels.
// Between 256..319 (64 cycles), will be populated for next line
SpriteSet sprite_gen(clk, ce, !cycle[8], spriteset_load, spriteset_load_in, obj_pixel_noblank, is_obj0_pixel);
// Blank out obj in the leftmost 8 pixels?
wire show_obj_on_pixel = (object_clip || (cycle[7:3] != 0)) && enable_objects;
wire [4:0] obj_pixel = {obj_pixel_noblank[4:2], show_obj_on_pixel ? obj_pixel_noblank[1:0] : 2'b00};
reg sprite0_hit_bg; // True if sprite#0 has collided with the BG in the last frame.
always @(posedge clk) if (ce) begin
if (exiting_vblank)
sprite0_hit_bg <= 0;
else if (is_rendering && // Object rendering is enabled
!cycle[8] && // X Pixel 0..255
cycle[7:0] != 255 && // X pixel != 255
!is_pre_render_line && // Y Pixel 0..239
obj0_on_line && // True if sprite#0 is included on the scan line.
is_obj0_pixel && // True if the pixel came from tempram #0.
show_obj_on_pixel &&
bg_pixel[1:0] != 0) begin // Background pixel nonzero.
sprite0_hit_bg <= 1;
end
// if (!cycle[8] && is_visible_line && obj0_on_line && is_obj0_pixel)
// $write("Sprite0 hit bg scan %d!!\n", scanline);
// if (is_obj0_pixel)
// $write("drawing obj0 pixel %d/%d\n", scanline, cycle);
end
wire [3:0] pixel;
wire pixel_is_obj;
PixelMuxer pixel_muxer(bg_pixel, obj_pixel[3:0], obj_pixel[4], pixel, pixel_is_obj);
// Compute the value to put on the VRAM address bus
assign vram_a = !is_rendering ? loopy[13:0] : // VRAM
(cycle[2:1] == 0) ? {2'b10, loopy[11:0]} : // Name table
(cycle[2:1] == 1) ? {2'b10, loopy[11:10], 4'b1111, loopy[9:7], loopy[4:2]} : // Attribute table
cycle[8] && !cycle[6] ? {1'b0, sprite_vram_addr} :
{1'b0, bg_patt, bg_name_table, cycle[1], loopy[14:12]}; // Pattern table bitmap #0, #1
// Read from VRAM, either when user requested a manual read, or when we're generating pixels.
assign vram_r = read && (ain == 7) ||
is_rendering && cycle[0] == 0 && !end_of_line;
// Write to VRAM?
assign vram_w = write && (ain == 7) && !is_pal_address && !is_rendering;
wire [5:0] color2;
PaletteRam palette_ram(clk, ce,
is_rendering ? {pixel_is_obj, pixel[3:0]} : (is_pal_address ? loopy[4:0] : 5'b0000), // Read addr
din[5:0], // Value to write
color2, // Output color
write && (ain == 7) && is_pal_address); // Condition for writing
assign color = grayscale ? {color2[5:4], 4'b0} : color2;
// always @(posedge clk)
// if (scanline == 194 && cycle < 8 && color == 15) begin
// $write("Pixel black %x %x %x %x %x\n", bg_pixel,obj_pixel,pixel,pixel_is_obj,color);
// end
always @(posedge clk) if (ce) begin
// if (!is_in_vblank && write)
// $write("%d/%d: $200%d <= %x\n", scanline, cycle, ain, din);
if (write) begin
case (ain)
0: begin // PPU Control Register 1
// t:....BA.. ........ = d:......BA
obj_patt <= din[3];
bg_patt <= din[4];
obj_size <= din[5];
vbl_enable <= din[7];
//$write("PPU Control #0 <= %X\n", din);
end
1: begin // PPU Control Register 2
grayscale <= din[0];
playfield_clip <= din[1];
object_clip <= din[2];
enable_playfield <= din[3];
enable_objects <= din[4];
color_intensity <= din[7:5];
if (!din[3] && scanline == 59)
$write("Disabling playfield at cycle %d\n", cycle);
end
endcase
end
// Reset frame specific counters upon exiting vblank
if (exiting_vblank)
nmi_occured <= 0;
// Set the
if (entering_vblank)
nmi_occured <= 1;
// Reset NMI register when reading from Status
if (read && ain == 2)
nmi_occured <= 0;
end
// If we're triggering a VBLANK NMI
assign nmi = nmi_occured && vbl_enable;
// One cycle after vram_r was asserted, the value
// is available on the bus.
reg vram_read_delayed;
always @(posedge clk) if (ce) begin
if (vram_read_delayed)
vram_latch <= vram_din;
vram_read_delayed = vram_r;
end
// Value currently being written to video ram
assign vram_dout = din;
reg [7:0] latched_dout;
always @* begin
case (ain)
2: latched_dout = {nmi_occured,
sprite0_hit_bg,
sprite_overflow,
5'b00000};
4: latched_dout = oam_bus;
default: if (is_pal_address) begin
latched_dout = {2'b00, color};
end else begin
latched_dout = vram_latch;
end
endcase
end
assign dout = latched_dout;
assign mapper_ppu_flags = {scanline, cycle, obj_size, is_rendering};
endmodule // PPU
|
//
// clkgen: Clock generation for I2S serializer
//
// mclk = clk/4.
// @ 48MHz => 12MHz master rate
// rate = mclk/256.
// @ 48MHz => 46.875 kHz sample rate
//
module clkgen(clk, reset, mclk, mclk_ena, rate);
parameter div = 8; // 2, 4, 8 clk / mclk ratio
input clk; // 48MHz system clock
input reset; // POR
output mclk; // 256x master clock output (50% duty cycle)
output mclk_ena;// 256x master clock enable output (25% duty cycle)
output rate; // Sample rate clock output
// master clock divider (4x)
wire [2:0] cnt_mask = div-1;
reg [2:0] mclk_cnt;
reg mclk_ena;
always @(posedge clk)
if(reset)
begin
mclk_cnt <= 3'b111;
mclk_ena <= 1'b1;
end
else
begin
mclk_cnt <= mclk_cnt - 1;
if((mclk_cnt & cnt_mask) == 3'b000)
mclk_ena <= 1'b1;
else
mclk_ena <= 1'b0;
end
assign mclk = mclk_cnt[1];
// rate counter
reg rate;
reg [7:0] rate_cnt;
always @(posedge clk)
if(reset | rate)
rate_cnt <= 8'd255;
else if(mclk_ena)
rate_cnt <= rate_cnt - 1;
// detect end condition for one cycle pulse in sync with mclk_ena
always @(posedge clk)
rate <= ((rate_cnt == 8'd0) && ((mclk_cnt & cnt_mask) == 3'b000));
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:3.92
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:00 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module clk_ibuf #
(
parameter INPUT_CLK_TYPE = "DIFFERENTIAL" // input clock type
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/gcd_block_design_gcd_0_1_sim_netlist.v
// Design : gcd_block_design_gcd_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "gcd_block_design_gcd_0_1,gcd,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "HLS" *)
(* X_CORE_INFO = "gcd,Vivado 2018.2" *) (* hls_module = "yes" *)
(* NotValidForBitStream *)
module gcd_block_design_gcd_0_1
(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *) input [5:0]s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *) input s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *) output s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *) input [31:0]s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *) input [3:0]s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *) input s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *) output s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *) output [1:0]s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *) output s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *) input s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *) input [5:0]s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *) input s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *) output s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *) output [31:0]s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *) output [1:0]s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *) output s_axi_gcd_bus_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_gcd_bus_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0" *) input ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_rst_n;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *) output interrupt;
wire ap_clk;
wire ap_rst_n;
wire interrupt;
wire [5:0]s_axi_gcd_bus_ARADDR;
wire s_axi_gcd_bus_ARREADY;
wire s_axi_gcd_bus_ARVALID;
wire [5:0]s_axi_gcd_bus_AWADDR;
wire s_axi_gcd_bus_AWREADY;
wire s_axi_gcd_bus_AWVALID;
wire s_axi_gcd_bus_BREADY;
wire [1:0]s_axi_gcd_bus_BRESP;
wire s_axi_gcd_bus_BVALID;
wire [31:0]s_axi_gcd_bus_RDATA;
wire s_axi_gcd_bus_RREADY;
wire [1:0]s_axi_gcd_bus_RRESP;
wire s_axi_gcd_bus_RVALID;
wire [31:0]s_axi_gcd_bus_WDATA;
wire s_axi_gcd_bus_WREADY;
wire [3:0]s_axi_gcd_bus_WSTRB;
wire s_axi_gcd_bus_WVALID;
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_GCD_BUS_ADDR_WIDTH = "6" *)
(* C_S_AXI_GCD_BUS_DATA_WIDTH = "32" *)
(* C_S_AXI_GCD_BUS_WSTRB_WIDTH = "4" *)
(* C_S_AXI_WSTRB_WIDTH = "4" *)
(* ap_ST_fsm_state1 = "4'b0001" *)
(* ap_ST_fsm_state2 = "4'b0010" *)
(* ap_ST_fsm_state3 = "4'b0100" *)
(* ap_ST_fsm_state4 = "4'b1000" *)
gcd_block_design_gcd_0_1_gcd inst
(.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID));
endmodule
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_GCD_BUS_ADDR_WIDTH = "6" *) (* C_S_AXI_GCD_BUS_DATA_WIDTH = "32" *)
(* C_S_AXI_GCD_BUS_WSTRB_WIDTH = "4" *) (* C_S_AXI_WSTRB_WIDTH = "4" *) (* ORIG_REF_NAME = "gcd" *)
(* ap_ST_fsm_state1 = "4'b0001" *) (* ap_ST_fsm_state2 = "4'b0010" *) (* ap_ST_fsm_state3 = "4'b0100" *)
(* ap_ST_fsm_state4 = "4'b1000" *) (* hls_module = "yes" *)
module gcd_block_design_gcd_0_1_gcd
(ap_clk,
ap_rst_n,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_BRESP,
interrupt);
input ap_clk;
input ap_rst_n;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output interrupt;
wire \<const0> ;
wire [15:0]a;
wire [15:0]a_assign_fu_78_p21_out;
wire [15:0]a_assign_reg_121;
wire a_assign_reg_1210;
wire \a_assign_reg_121[11]_i_2_n_0 ;
wire \a_assign_reg_121[11]_i_3_n_0 ;
wire \a_assign_reg_121[11]_i_4_n_0 ;
wire \a_assign_reg_121[11]_i_5_n_0 ;
wire \a_assign_reg_121[15]_i_2_n_0 ;
wire \a_assign_reg_121[15]_i_3_n_0 ;
wire \a_assign_reg_121[15]_i_4_n_0 ;
wire \a_assign_reg_121[15]_i_5_n_0 ;
wire \a_assign_reg_121[3]_i_2_n_0 ;
wire \a_assign_reg_121[3]_i_3_n_0 ;
wire \a_assign_reg_121[3]_i_4_n_0 ;
wire \a_assign_reg_121[3]_i_5_n_0 ;
wire \a_assign_reg_121[7]_i_2_n_0 ;
wire \a_assign_reg_121[7]_i_3_n_0 ;
wire \a_assign_reg_121[7]_i_4_n_0 ;
wire \a_assign_reg_121[7]_i_5_n_0 ;
wire \a_assign_reg_121_reg[11]_i_1_n_0 ;
wire \a_assign_reg_121_reg[11]_i_1_n_1 ;
wire \a_assign_reg_121_reg[11]_i_1_n_2 ;
wire \a_assign_reg_121_reg[11]_i_1_n_3 ;
wire \a_assign_reg_121_reg[15]_i_1_n_1 ;
wire \a_assign_reg_121_reg[15]_i_1_n_2 ;
wire \a_assign_reg_121_reg[15]_i_1_n_3 ;
wire \a_assign_reg_121_reg[3]_i_1_n_0 ;
wire \a_assign_reg_121_reg[3]_i_1_n_1 ;
wire \a_assign_reg_121_reg[3]_i_1_n_2 ;
wire \a_assign_reg_121_reg[3]_i_1_n_3 ;
wire \a_assign_reg_121_reg[7]_i_1_n_0 ;
wire \a_assign_reg_121_reg[7]_i_1_n_1 ;
wire \a_assign_reg_121_reg[7]_i_1_n_2 ;
wire \a_assign_reg_121_reg[7]_i_1_n_3 ;
wire [15:0]a_read_reg_107;
wire \ap_CS_fsm_reg_n_0_[0] ;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_state3;
wire ap_CS_fsm_state4;
wire [2:0]ap_NS_fsm;
wire ap_NS_fsm1;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_inv;
wire [15:0]b;
wire [15:0]b_assign_fu_84_p20_out;
wire [15:0]b_assign_reg_126;
wire \b_assign_reg_126[11]_i_2_n_0 ;
wire \b_assign_reg_126[11]_i_3_n_0 ;
wire \b_assign_reg_126[11]_i_4_n_0 ;
wire \b_assign_reg_126[11]_i_5_n_0 ;
wire \b_assign_reg_126[15]_i_2_n_0 ;
wire \b_assign_reg_126[15]_i_3_n_0 ;
wire \b_assign_reg_126[15]_i_4_n_0 ;
wire \b_assign_reg_126[15]_i_5_n_0 ;
wire \b_assign_reg_126[3]_i_2_n_0 ;
wire \b_assign_reg_126[3]_i_3_n_0 ;
wire \b_assign_reg_126[3]_i_4_n_0 ;
wire \b_assign_reg_126[3]_i_5_n_0 ;
wire \b_assign_reg_126[7]_i_2_n_0 ;
wire \b_assign_reg_126[7]_i_3_n_0 ;
wire \b_assign_reg_126[7]_i_4_n_0 ;
wire \b_assign_reg_126[7]_i_5_n_0 ;
wire \b_assign_reg_126_reg[11]_i_1_n_0 ;
wire \b_assign_reg_126_reg[11]_i_1_n_1 ;
wire \b_assign_reg_126_reg[11]_i_1_n_2 ;
wire \b_assign_reg_126_reg[11]_i_1_n_3 ;
wire \b_assign_reg_126_reg[15]_i_1_n_1 ;
wire \b_assign_reg_126_reg[15]_i_1_n_2 ;
wire \b_assign_reg_126_reg[15]_i_1_n_3 ;
wire \b_assign_reg_126_reg[3]_i_1_n_0 ;
wire \b_assign_reg_126_reg[3]_i_1_n_1 ;
wire \b_assign_reg_126_reg[3]_i_1_n_2 ;
wire \b_assign_reg_126_reg[3]_i_1_n_3 ;
wire \b_assign_reg_126_reg[7]_i_1_n_0 ;
wire \b_assign_reg_126_reg[7]_i_1_n_1 ;
wire \b_assign_reg_126_reg[7]_i_1_n_2 ;
wire \b_assign_reg_126_reg[7]_i_1_n_3 ;
wire [15:0]b_read_reg_102;
wire interrupt;
wire [15:0]p_1_in;
wire [15:0]p_s_reg_45;
wire \p_s_reg_45[0]_i_1_n_0 ;
wire \p_s_reg_45[10]_i_1_n_0 ;
wire \p_s_reg_45[11]_i_1_n_0 ;
wire \p_s_reg_45[12]_i_1_n_0 ;
wire \p_s_reg_45[13]_i_1_n_0 ;
wire \p_s_reg_45[14]_i_1_n_0 ;
wire \p_s_reg_45[15]_i_1_n_0 ;
wire \p_s_reg_45[15]_i_2_n_0 ;
wire \p_s_reg_45[1]_i_1_n_0 ;
wire \p_s_reg_45[2]_i_1_n_0 ;
wire \p_s_reg_45[3]_i_1_n_0 ;
wire \p_s_reg_45[4]_i_1_n_0 ;
wire \p_s_reg_45[5]_i_1_n_0 ;
wire \p_s_reg_45[6]_i_1_n_0 ;
wire \p_s_reg_45[7]_i_1_n_0 ;
wire \p_s_reg_45[8]_i_1_n_0 ;
wire \p_s_reg_45[9]_i_1_n_0 ;
wire [15:0]result_reg_56;
wire \result_reg_56[15]_i_1_n_0 ;
wire [5:0]s_axi_gcd_bus_ARADDR;
wire s_axi_gcd_bus_ARREADY;
wire s_axi_gcd_bus_ARVALID;
wire [5:0]s_axi_gcd_bus_AWADDR;
wire s_axi_gcd_bus_AWREADY;
wire s_axi_gcd_bus_AWVALID;
wire s_axi_gcd_bus_BREADY;
wire s_axi_gcd_bus_BVALID;
wire [15:0]\^s_axi_gcd_bus_RDATA ;
wire s_axi_gcd_bus_RREADY;
wire s_axi_gcd_bus_RVALID;
wire [31:0]s_axi_gcd_bus_WDATA;
wire s_axi_gcd_bus_WREADY;
wire [3:0]s_axi_gcd_bus_WSTRB;
wire s_axi_gcd_bus_WVALID;
wire tmp_2_fu_66_p2;
wire tmp_3_fu_72_p2;
wire tmp_3_reg_115;
wire \tmp_3_reg_115[0]_i_10_n_0 ;
wire \tmp_3_reg_115[0]_i_11_n_0 ;
wire \tmp_3_reg_115[0]_i_12_n_0 ;
wire \tmp_3_reg_115[0]_i_13_n_0 ;
wire \tmp_3_reg_115[0]_i_14_n_0 ;
wire \tmp_3_reg_115[0]_i_15_n_0 ;
wire \tmp_3_reg_115[0]_i_16_n_0 ;
wire \tmp_3_reg_115[0]_i_17_n_0 ;
wire \tmp_3_reg_115[0]_i_18_n_0 ;
wire \tmp_3_reg_115[0]_i_3_n_0 ;
wire \tmp_3_reg_115[0]_i_4_n_0 ;
wire \tmp_3_reg_115[0]_i_5_n_0 ;
wire \tmp_3_reg_115[0]_i_6_n_0 ;
wire \tmp_3_reg_115[0]_i_7_n_0 ;
wire \tmp_3_reg_115[0]_i_8_n_0 ;
wire \tmp_3_reg_115[0]_i_9_n_0 ;
wire \tmp_3_reg_115_reg[0]_i_1_n_1 ;
wire \tmp_3_reg_115_reg[0]_i_1_n_2 ;
wire \tmp_3_reg_115_reg[0]_i_1_n_3 ;
wire \tmp_3_reg_115_reg[0]_i_2_n_0 ;
wire \tmp_3_reg_115_reg[0]_i_2_n_1 ;
wire \tmp_3_reg_115_reg[0]_i_2_n_2 ;
wire \tmp_3_reg_115_reg[0]_i_2_n_3 ;
wire [3:3]\NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED ;
wire [3:0]\NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED ;
assign s_axi_gcd_bus_BRESP[1] = \<const0> ;
assign s_axi_gcd_bus_BRESP[0] = \<const0> ;
assign s_axi_gcd_bus_RDATA[31] = \<const0> ;
assign s_axi_gcd_bus_RDATA[30] = \<const0> ;
assign s_axi_gcd_bus_RDATA[29] = \<const0> ;
assign s_axi_gcd_bus_RDATA[28] = \<const0> ;
assign s_axi_gcd_bus_RDATA[27] = \<const0> ;
assign s_axi_gcd_bus_RDATA[26] = \<const0> ;
assign s_axi_gcd_bus_RDATA[25] = \<const0> ;
assign s_axi_gcd_bus_RDATA[24] = \<const0> ;
assign s_axi_gcd_bus_RDATA[23] = \<const0> ;
assign s_axi_gcd_bus_RDATA[22] = \<const0> ;
assign s_axi_gcd_bus_RDATA[21] = \<const0> ;
assign s_axi_gcd_bus_RDATA[20] = \<const0> ;
assign s_axi_gcd_bus_RDATA[19] = \<const0> ;
assign s_axi_gcd_bus_RDATA[18] = \<const0> ;
assign s_axi_gcd_bus_RDATA[17] = \<const0> ;
assign s_axi_gcd_bus_RDATA[16] = \<const0> ;
assign s_axi_gcd_bus_RDATA[15:0] = \^s_axi_gcd_bus_RDATA [15:0];
assign s_axi_gcd_bus_RRESP[1] = \<const0> ;
assign s_axi_gcd_bus_RRESP[0] = \<const0> ;
GND GND
(.G(\<const0> ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[11]_i_2
(.I0(result_reg_56[11]),
.I1(p_s_reg_45[11]),
.O(\a_assign_reg_121[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[11]_i_3
(.I0(result_reg_56[10]),
.I1(p_s_reg_45[10]),
.O(\a_assign_reg_121[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[11]_i_4
(.I0(result_reg_56[9]),
.I1(p_s_reg_45[9]),
.O(\a_assign_reg_121[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[11]_i_5
(.I0(result_reg_56[8]),
.I1(p_s_reg_45[8]),
.O(\a_assign_reg_121[11]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[15]_i_2
(.I0(result_reg_56[15]),
.I1(p_s_reg_45[15]),
.O(\a_assign_reg_121[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[15]_i_3
(.I0(result_reg_56[14]),
.I1(p_s_reg_45[14]),
.O(\a_assign_reg_121[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[15]_i_4
(.I0(result_reg_56[13]),
.I1(p_s_reg_45[13]),
.O(\a_assign_reg_121[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[15]_i_5
(.I0(result_reg_56[12]),
.I1(p_s_reg_45[12]),
.O(\a_assign_reg_121[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[3]_i_2
(.I0(result_reg_56[3]),
.I1(p_s_reg_45[3]),
.O(\a_assign_reg_121[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[3]_i_3
(.I0(result_reg_56[2]),
.I1(p_s_reg_45[2]),
.O(\a_assign_reg_121[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[3]_i_4
(.I0(result_reg_56[1]),
.I1(p_s_reg_45[1]),
.O(\a_assign_reg_121[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[3]_i_5
(.I0(result_reg_56[0]),
.I1(p_s_reg_45[0]),
.O(\a_assign_reg_121[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[7]_i_2
(.I0(result_reg_56[7]),
.I1(p_s_reg_45[7]),
.O(\a_assign_reg_121[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[7]_i_3
(.I0(result_reg_56[6]),
.I1(p_s_reg_45[6]),
.O(\a_assign_reg_121[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[7]_i_4
(.I0(result_reg_56[5]),
.I1(p_s_reg_45[5]),
.O(\a_assign_reg_121[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\a_assign_reg_121[7]_i_5
(.I0(result_reg_56[4]),
.I1(p_s_reg_45[4]),
.O(\a_assign_reg_121[7]_i_5_n_0 ));
FDRE \a_assign_reg_121_reg[0]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[0]),
.Q(a_assign_reg_121[0]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[10]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[10]),
.Q(a_assign_reg_121[10]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[11]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[11]),
.Q(a_assign_reg_121[11]),
.R(1'b0));
CARRY4 \a_assign_reg_121_reg[11]_i_1
(.CI(\a_assign_reg_121_reg[7]_i_1_n_0 ),
.CO({\a_assign_reg_121_reg[11]_i_1_n_0 ,\a_assign_reg_121_reg[11]_i_1_n_1 ,\a_assign_reg_121_reg[11]_i_1_n_2 ,\a_assign_reg_121_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(result_reg_56[11:8]),
.O(a_assign_fu_78_p21_out[11:8]),
.S({\a_assign_reg_121[11]_i_2_n_0 ,\a_assign_reg_121[11]_i_3_n_0 ,\a_assign_reg_121[11]_i_4_n_0 ,\a_assign_reg_121[11]_i_5_n_0 }));
FDRE \a_assign_reg_121_reg[12]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[12]),
.Q(a_assign_reg_121[12]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[13]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[13]),
.Q(a_assign_reg_121[13]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[14]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[14]),
.Q(a_assign_reg_121[14]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[15]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[15]),
.Q(a_assign_reg_121[15]),
.R(1'b0));
CARRY4 \a_assign_reg_121_reg[15]_i_1
(.CI(\a_assign_reg_121_reg[11]_i_1_n_0 ),
.CO({\NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED [3],\a_assign_reg_121_reg[15]_i_1_n_1 ,\a_assign_reg_121_reg[15]_i_1_n_2 ,\a_assign_reg_121_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,result_reg_56[14:12]}),
.O(a_assign_fu_78_p21_out[15:12]),
.S({\a_assign_reg_121[15]_i_2_n_0 ,\a_assign_reg_121[15]_i_3_n_0 ,\a_assign_reg_121[15]_i_4_n_0 ,\a_assign_reg_121[15]_i_5_n_0 }));
FDRE \a_assign_reg_121_reg[1]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[1]),
.Q(a_assign_reg_121[1]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[2]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[2]),
.Q(a_assign_reg_121[2]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[3]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[3]),
.Q(a_assign_reg_121[3]),
.R(1'b0));
CARRY4 \a_assign_reg_121_reg[3]_i_1
(.CI(1'b0),
.CO({\a_assign_reg_121_reg[3]_i_1_n_0 ,\a_assign_reg_121_reg[3]_i_1_n_1 ,\a_assign_reg_121_reg[3]_i_1_n_2 ,\a_assign_reg_121_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(result_reg_56[3:0]),
.O(a_assign_fu_78_p21_out[3:0]),
.S({\a_assign_reg_121[3]_i_2_n_0 ,\a_assign_reg_121[3]_i_3_n_0 ,\a_assign_reg_121[3]_i_4_n_0 ,\a_assign_reg_121[3]_i_5_n_0 }));
FDRE \a_assign_reg_121_reg[4]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[4]),
.Q(a_assign_reg_121[4]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[5]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[5]),
.Q(a_assign_reg_121[5]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[6]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[6]),
.Q(a_assign_reg_121[6]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[7]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[7]),
.Q(a_assign_reg_121[7]),
.R(1'b0));
CARRY4 \a_assign_reg_121_reg[7]_i_1
(.CI(\a_assign_reg_121_reg[3]_i_1_n_0 ),
.CO({\a_assign_reg_121_reg[7]_i_1_n_0 ,\a_assign_reg_121_reg[7]_i_1_n_1 ,\a_assign_reg_121_reg[7]_i_1_n_2 ,\a_assign_reg_121_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(result_reg_56[7:4]),
.O(a_assign_fu_78_p21_out[7:4]),
.S({\a_assign_reg_121[7]_i_2_n_0 ,\a_assign_reg_121[7]_i_3_n_0 ,\a_assign_reg_121[7]_i_4_n_0 ,\a_assign_reg_121[7]_i_5_n_0 }));
FDRE \a_assign_reg_121_reg[8]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[8]),
.Q(a_assign_reg_121[8]),
.R(1'b0));
FDRE \a_assign_reg_121_reg[9]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(a_assign_fu_78_p21_out[9]),
.Q(a_assign_reg_121[9]),
.R(1'b0));
FDRE \a_read_reg_107_reg[0]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[0]),
.Q(a_read_reg_107[0]),
.R(1'b0));
FDRE \a_read_reg_107_reg[10]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[10]),
.Q(a_read_reg_107[10]),
.R(1'b0));
FDRE \a_read_reg_107_reg[11]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[11]),
.Q(a_read_reg_107[11]),
.R(1'b0));
FDRE \a_read_reg_107_reg[12]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[12]),
.Q(a_read_reg_107[12]),
.R(1'b0));
FDRE \a_read_reg_107_reg[13]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[13]),
.Q(a_read_reg_107[13]),
.R(1'b0));
FDRE \a_read_reg_107_reg[14]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[14]),
.Q(a_read_reg_107[14]),
.R(1'b0));
FDRE \a_read_reg_107_reg[15]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[15]),
.Q(a_read_reg_107[15]),
.R(1'b0));
FDRE \a_read_reg_107_reg[1]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[1]),
.Q(a_read_reg_107[1]),
.R(1'b0));
FDRE \a_read_reg_107_reg[2]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[2]),
.Q(a_read_reg_107[2]),
.R(1'b0));
FDRE \a_read_reg_107_reg[3]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[3]),
.Q(a_read_reg_107[3]),
.R(1'b0));
FDRE \a_read_reg_107_reg[4]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[4]),
.Q(a_read_reg_107[4]),
.R(1'b0));
FDRE \a_read_reg_107_reg[5]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[5]),
.Q(a_read_reg_107[5]),
.R(1'b0));
FDRE \a_read_reg_107_reg[6]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[6]),
.Q(a_read_reg_107[6]),
.R(1'b0));
FDRE \a_read_reg_107_reg[7]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[7]),
.Q(a_read_reg_107[7]),
.R(1'b0));
FDRE \a_read_reg_107_reg[8]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[8]),
.Q(a_read_reg_107[8]),
.R(1'b0));
FDRE \a_read_reg_107_reg[9]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(a[9]),
.Q(a_read_reg_107[9]),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
\ap_CS_fsm[2]_i_1
(.I0(ap_CS_fsm_state2),
.I1(ap_CS_fsm_state4),
.O(ap_NS_fsm[2]));
LUT2 #(
.INIT(4'h2))
\ap_CS_fsm[3]_i_1
(.I0(ap_CS_fsm_state3),
.I1(tmp_2_fu_66_p2),
.O(a_assign_reg_1210));
(* FSM_ENCODING = "none" *)
FDSE #(
.INIT(1'b1))
\ap_CS_fsm_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm[0]),
.Q(\ap_CS_fsm_reg_n_0_[0] ),
.S(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm[1]),
.Q(ap_CS_fsm_state2),
.R(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(ap_NS_fsm[2]),
.Q(ap_CS_fsm_state3),
.R(ap_rst_n_inv));
(* FSM_ENCODING = "none" *)
FDRE #(
.INIT(1'b0))
\ap_CS_fsm_reg[3]
(.C(ap_clk),
.CE(1'b1),
.D(a_assign_reg_1210),
.Q(ap_CS_fsm_state4),
.R(ap_rst_n_inv));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[11]_i_2
(.I0(p_s_reg_45[11]),
.I1(result_reg_56[11]),
.O(\b_assign_reg_126[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[11]_i_3
(.I0(p_s_reg_45[10]),
.I1(result_reg_56[10]),
.O(\b_assign_reg_126[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[11]_i_4
(.I0(p_s_reg_45[9]),
.I1(result_reg_56[9]),
.O(\b_assign_reg_126[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[11]_i_5
(.I0(p_s_reg_45[8]),
.I1(result_reg_56[8]),
.O(\b_assign_reg_126[11]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[15]_i_2
(.I0(p_s_reg_45[15]),
.I1(result_reg_56[15]),
.O(\b_assign_reg_126[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[15]_i_3
(.I0(p_s_reg_45[14]),
.I1(result_reg_56[14]),
.O(\b_assign_reg_126[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[15]_i_4
(.I0(p_s_reg_45[13]),
.I1(result_reg_56[13]),
.O(\b_assign_reg_126[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[15]_i_5
(.I0(p_s_reg_45[12]),
.I1(result_reg_56[12]),
.O(\b_assign_reg_126[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[3]_i_2
(.I0(p_s_reg_45[3]),
.I1(result_reg_56[3]),
.O(\b_assign_reg_126[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[3]_i_3
(.I0(p_s_reg_45[2]),
.I1(result_reg_56[2]),
.O(\b_assign_reg_126[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[3]_i_4
(.I0(p_s_reg_45[1]),
.I1(result_reg_56[1]),
.O(\b_assign_reg_126[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[3]_i_5
(.I0(p_s_reg_45[0]),
.I1(result_reg_56[0]),
.O(\b_assign_reg_126[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[7]_i_2
(.I0(p_s_reg_45[7]),
.I1(result_reg_56[7]),
.O(\b_assign_reg_126[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[7]_i_3
(.I0(p_s_reg_45[6]),
.I1(result_reg_56[6]),
.O(\b_assign_reg_126[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[7]_i_4
(.I0(p_s_reg_45[5]),
.I1(result_reg_56[5]),
.O(\b_assign_reg_126[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\b_assign_reg_126[7]_i_5
(.I0(p_s_reg_45[4]),
.I1(result_reg_56[4]),
.O(\b_assign_reg_126[7]_i_5_n_0 ));
FDRE \b_assign_reg_126_reg[0]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[0]),
.Q(b_assign_reg_126[0]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[10]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[10]),
.Q(b_assign_reg_126[10]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[11]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[11]),
.Q(b_assign_reg_126[11]),
.R(1'b0));
CARRY4 \b_assign_reg_126_reg[11]_i_1
(.CI(\b_assign_reg_126_reg[7]_i_1_n_0 ),
.CO({\b_assign_reg_126_reg[11]_i_1_n_0 ,\b_assign_reg_126_reg[11]_i_1_n_1 ,\b_assign_reg_126_reg[11]_i_1_n_2 ,\b_assign_reg_126_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_s_reg_45[11:8]),
.O(b_assign_fu_84_p20_out[11:8]),
.S({\b_assign_reg_126[11]_i_2_n_0 ,\b_assign_reg_126[11]_i_3_n_0 ,\b_assign_reg_126[11]_i_4_n_0 ,\b_assign_reg_126[11]_i_5_n_0 }));
FDRE \b_assign_reg_126_reg[12]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[12]),
.Q(b_assign_reg_126[12]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[13]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[13]),
.Q(b_assign_reg_126[13]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[14]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[14]),
.Q(b_assign_reg_126[14]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[15]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[15]),
.Q(b_assign_reg_126[15]),
.R(1'b0));
CARRY4 \b_assign_reg_126_reg[15]_i_1
(.CI(\b_assign_reg_126_reg[11]_i_1_n_0 ),
.CO({\NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED [3],\b_assign_reg_126_reg[15]_i_1_n_1 ,\b_assign_reg_126_reg[15]_i_1_n_2 ,\b_assign_reg_126_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,p_s_reg_45[14:12]}),
.O(b_assign_fu_84_p20_out[15:12]),
.S({\b_assign_reg_126[15]_i_2_n_0 ,\b_assign_reg_126[15]_i_3_n_0 ,\b_assign_reg_126[15]_i_4_n_0 ,\b_assign_reg_126[15]_i_5_n_0 }));
FDRE \b_assign_reg_126_reg[1]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[1]),
.Q(b_assign_reg_126[1]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[2]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[2]),
.Q(b_assign_reg_126[2]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[3]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[3]),
.Q(b_assign_reg_126[3]),
.R(1'b0));
CARRY4 \b_assign_reg_126_reg[3]_i_1
(.CI(1'b0),
.CO({\b_assign_reg_126_reg[3]_i_1_n_0 ,\b_assign_reg_126_reg[3]_i_1_n_1 ,\b_assign_reg_126_reg[3]_i_1_n_2 ,\b_assign_reg_126_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(p_s_reg_45[3:0]),
.O(b_assign_fu_84_p20_out[3:0]),
.S({\b_assign_reg_126[3]_i_2_n_0 ,\b_assign_reg_126[3]_i_3_n_0 ,\b_assign_reg_126[3]_i_4_n_0 ,\b_assign_reg_126[3]_i_5_n_0 }));
FDRE \b_assign_reg_126_reg[4]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[4]),
.Q(b_assign_reg_126[4]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[5]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[5]),
.Q(b_assign_reg_126[5]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[6]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[6]),
.Q(b_assign_reg_126[6]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[7]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[7]),
.Q(b_assign_reg_126[7]),
.R(1'b0));
CARRY4 \b_assign_reg_126_reg[7]_i_1
(.CI(\b_assign_reg_126_reg[3]_i_1_n_0 ),
.CO({\b_assign_reg_126_reg[7]_i_1_n_0 ,\b_assign_reg_126_reg[7]_i_1_n_1 ,\b_assign_reg_126_reg[7]_i_1_n_2 ,\b_assign_reg_126_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_s_reg_45[7:4]),
.O(b_assign_fu_84_p20_out[7:4]),
.S({\b_assign_reg_126[7]_i_2_n_0 ,\b_assign_reg_126[7]_i_3_n_0 ,\b_assign_reg_126[7]_i_4_n_0 ,\b_assign_reg_126[7]_i_5_n_0 }));
FDRE \b_assign_reg_126_reg[8]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[8]),
.Q(b_assign_reg_126[8]),
.R(1'b0));
FDRE \b_assign_reg_126_reg[9]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(b_assign_fu_84_p20_out[9]),
.Q(b_assign_reg_126[9]),
.R(1'b0));
FDRE \b_read_reg_102_reg[0]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[0]),
.Q(b_read_reg_102[0]),
.R(1'b0));
FDRE \b_read_reg_102_reg[10]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[10]),
.Q(b_read_reg_102[10]),
.R(1'b0));
FDRE \b_read_reg_102_reg[11]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[11]),
.Q(b_read_reg_102[11]),
.R(1'b0));
FDRE \b_read_reg_102_reg[12]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[12]),
.Q(b_read_reg_102[12]),
.R(1'b0));
FDRE \b_read_reg_102_reg[13]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[13]),
.Q(b_read_reg_102[13]),
.R(1'b0));
FDRE \b_read_reg_102_reg[14]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[14]),
.Q(b_read_reg_102[14]),
.R(1'b0));
FDRE \b_read_reg_102_reg[15]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[15]),
.Q(b_read_reg_102[15]),
.R(1'b0));
FDRE \b_read_reg_102_reg[1]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[1]),
.Q(b_read_reg_102[1]),
.R(1'b0));
FDRE \b_read_reg_102_reg[2]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[2]),
.Q(b_read_reg_102[2]),
.R(1'b0));
FDRE \b_read_reg_102_reg[3]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[3]),
.Q(b_read_reg_102[3]),
.R(1'b0));
FDRE \b_read_reg_102_reg[4]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[4]),
.Q(b_read_reg_102[4]),
.R(1'b0));
FDRE \b_read_reg_102_reg[5]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[5]),
.Q(b_read_reg_102[5]),
.R(1'b0));
FDRE \b_read_reg_102_reg[6]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[6]),
.Q(b_read_reg_102[6]),
.R(1'b0));
FDRE \b_read_reg_102_reg[7]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[7]),
.Q(b_read_reg_102[7]),
.R(1'b0));
FDRE \b_read_reg_102_reg[8]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[8]),
.Q(b_read_reg_102[8]),
.R(1'b0));
FDRE \b_read_reg_102_reg[9]
(.C(ap_clk),
.CE(ap_NS_fsm1),
.D(b[9]),
.Q(b_read_reg_102[9]),
.R(1'b0));
gcd_block_design_gcd_0_1_gcd_gcd_bus_s_axi gcd_gcd_bus_s_axi_U
(.CO(tmp_2_fu_66_p2),
.D(ap_NS_fsm[1:0]),
.E(ap_NS_fsm1),
.Q({ap_CS_fsm_state4,ap_CS_fsm_state3,ap_CS_fsm_state2,\ap_CS_fsm_reg_n_0_[0] }),
.SR(ap_rst_n_inv),
.\a_read_reg_107_reg[15] (a),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.\b_read_reg_102_reg[15] (b),
.interrupt(interrupt),
.out({s_axi_gcd_bus_BVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_AWREADY}),
.\p_s_reg_45_reg[15] (p_s_reg_45),
.\result_reg_56_reg[15] (result_reg_56),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_RDATA(\^s_axi_gcd_bus_RDATA ),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.s_axi_gcd_bus_RVALID({s_axi_gcd_bus_RVALID,s_axi_gcd_bus_ARREADY}),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA[15:0]),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB[1:0]),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[0]_i_1
(.I0(b_assign_reg_126[0]),
.I1(b_read_reg_102[0]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[10]_i_1
(.I0(b_assign_reg_126[10]),
.I1(b_read_reg_102[10]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[10]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[11]_i_1
(.I0(b_assign_reg_126[11]),
.I1(b_read_reg_102[11]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[12]_i_1
(.I0(b_assign_reg_126[12]),
.I1(b_read_reg_102[12]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[12]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[13]_i_1
(.I0(b_assign_reg_126[13]),
.I1(b_read_reg_102[13]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[13]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[14]_i_1
(.I0(b_assign_reg_126[14]),
.I1(b_read_reg_102[14]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[14]_i_1_n_0 ));
LUT3 #(
.INIT(8'h74))
\p_s_reg_45[15]_i_1
(.I0(tmp_3_reg_115),
.I1(ap_CS_fsm_state4),
.I2(ap_CS_fsm_state2),
.O(\p_s_reg_45[15]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[15]_i_2
(.I0(b_assign_reg_126[15]),
.I1(b_read_reg_102[15]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[15]_i_2_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[1]_i_1
(.I0(b_assign_reg_126[1]),
.I1(b_read_reg_102[1]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[2]_i_1
(.I0(b_assign_reg_126[2]),
.I1(b_read_reg_102[2]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[3]_i_1
(.I0(b_assign_reg_126[3]),
.I1(b_read_reg_102[3]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[4]_i_1
(.I0(b_assign_reg_126[4]),
.I1(b_read_reg_102[4]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[5]_i_1
(.I0(b_assign_reg_126[5]),
.I1(b_read_reg_102[5]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[5]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[6]_i_1
(.I0(b_assign_reg_126[6]),
.I1(b_read_reg_102[6]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[7]_i_1
(.I0(b_assign_reg_126[7]),
.I1(b_read_reg_102[7]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[8]_i_1
(.I0(b_assign_reg_126[8]),
.I1(b_read_reg_102[8]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\p_s_reg_45[9]_i_1
(.I0(b_assign_reg_126[9]),
.I1(b_read_reg_102[9]),
.I2(ap_CS_fsm_state4),
.O(\p_s_reg_45[9]_i_1_n_0 ));
FDRE \p_s_reg_45_reg[0]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[0]_i_1_n_0 ),
.Q(p_s_reg_45[0]),
.R(1'b0));
FDRE \p_s_reg_45_reg[10]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[10]_i_1_n_0 ),
.Q(p_s_reg_45[10]),
.R(1'b0));
FDRE \p_s_reg_45_reg[11]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[11]_i_1_n_0 ),
.Q(p_s_reg_45[11]),
.R(1'b0));
FDRE \p_s_reg_45_reg[12]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[12]_i_1_n_0 ),
.Q(p_s_reg_45[12]),
.R(1'b0));
FDRE \p_s_reg_45_reg[13]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[13]_i_1_n_0 ),
.Q(p_s_reg_45[13]),
.R(1'b0));
FDRE \p_s_reg_45_reg[14]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[14]_i_1_n_0 ),
.Q(p_s_reg_45[14]),
.R(1'b0));
FDRE \p_s_reg_45_reg[15]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[15]_i_2_n_0 ),
.Q(p_s_reg_45[15]),
.R(1'b0));
FDRE \p_s_reg_45_reg[1]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[1]_i_1_n_0 ),
.Q(p_s_reg_45[1]),
.R(1'b0));
FDRE \p_s_reg_45_reg[2]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[2]_i_1_n_0 ),
.Q(p_s_reg_45[2]),
.R(1'b0));
FDRE \p_s_reg_45_reg[3]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[3]_i_1_n_0 ),
.Q(p_s_reg_45[3]),
.R(1'b0));
FDRE \p_s_reg_45_reg[4]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[4]_i_1_n_0 ),
.Q(p_s_reg_45[4]),
.R(1'b0));
FDRE \p_s_reg_45_reg[5]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[5]_i_1_n_0 ),
.Q(p_s_reg_45[5]),
.R(1'b0));
FDRE \p_s_reg_45_reg[6]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[6]_i_1_n_0 ),
.Q(p_s_reg_45[6]),
.R(1'b0));
FDRE \p_s_reg_45_reg[7]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[7]_i_1_n_0 ),
.Q(p_s_reg_45[7]),
.R(1'b0));
FDRE \p_s_reg_45_reg[8]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[8]_i_1_n_0 ),
.Q(p_s_reg_45[8]),
.R(1'b0));
FDRE \p_s_reg_45_reg[9]
(.C(ap_clk),
.CE(\p_s_reg_45[15]_i_1_n_0 ),
.D(\p_s_reg_45[9]_i_1_n_0 ),
.Q(p_s_reg_45[9]),
.R(1'b0));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[0]_i_1
(.I0(a_assign_reg_121[0]),
.I1(a_read_reg_107[0]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[0]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[10]_i_1
(.I0(a_assign_reg_121[10]),
.I1(a_read_reg_107[10]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[10]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[11]_i_1
(.I0(a_assign_reg_121[11]),
.I1(a_read_reg_107[11]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[11]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[12]_i_1
(.I0(a_assign_reg_121[12]),
.I1(a_read_reg_107[12]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[12]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[13]_i_1
(.I0(a_assign_reg_121[13]),
.I1(a_read_reg_107[13]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[13]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[14]_i_1
(.I0(a_assign_reg_121[14]),
.I1(a_read_reg_107[14]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[14]));
LUT3 #(
.INIT(8'hB8))
\result_reg_56[15]_i_1
(.I0(tmp_3_reg_115),
.I1(ap_CS_fsm_state4),
.I2(ap_CS_fsm_state2),
.O(\result_reg_56[15]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[15]_i_2
(.I0(a_assign_reg_121[15]),
.I1(a_read_reg_107[15]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[15]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[1]_i_1
(.I0(a_assign_reg_121[1]),
.I1(a_read_reg_107[1]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[1]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[2]_i_1
(.I0(a_assign_reg_121[2]),
.I1(a_read_reg_107[2]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[2]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[3]_i_1
(.I0(a_assign_reg_121[3]),
.I1(a_read_reg_107[3]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[3]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[4]_i_1
(.I0(a_assign_reg_121[4]),
.I1(a_read_reg_107[4]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[4]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[5]_i_1
(.I0(a_assign_reg_121[5]),
.I1(a_read_reg_107[5]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[5]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[6]_i_1
(.I0(a_assign_reg_121[6]),
.I1(a_read_reg_107[6]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[6]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[7]_i_1
(.I0(a_assign_reg_121[7]),
.I1(a_read_reg_107[7]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[7]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[8]_i_1
(.I0(a_assign_reg_121[8]),
.I1(a_read_reg_107[8]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[8]));
LUT3 #(
.INIT(8'hAC))
\result_reg_56[9]_i_1
(.I0(a_assign_reg_121[9]),
.I1(a_read_reg_107[9]),
.I2(ap_CS_fsm_state4),
.O(p_1_in[9]));
FDRE \result_reg_56_reg[0]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[0]),
.Q(result_reg_56[0]),
.R(1'b0));
FDRE \result_reg_56_reg[10]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[10]),
.Q(result_reg_56[10]),
.R(1'b0));
FDRE \result_reg_56_reg[11]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[11]),
.Q(result_reg_56[11]),
.R(1'b0));
FDRE \result_reg_56_reg[12]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[12]),
.Q(result_reg_56[12]),
.R(1'b0));
FDRE \result_reg_56_reg[13]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[13]),
.Q(result_reg_56[13]),
.R(1'b0));
FDRE \result_reg_56_reg[14]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[14]),
.Q(result_reg_56[14]),
.R(1'b0));
FDRE \result_reg_56_reg[15]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[15]),
.Q(result_reg_56[15]),
.R(1'b0));
FDRE \result_reg_56_reg[1]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[1]),
.Q(result_reg_56[1]),
.R(1'b0));
FDRE \result_reg_56_reg[2]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(result_reg_56[2]),
.R(1'b0));
FDRE \result_reg_56_reg[3]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(result_reg_56[3]),
.R(1'b0));
FDRE \result_reg_56_reg[4]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[4]),
.Q(result_reg_56[4]),
.R(1'b0));
FDRE \result_reg_56_reg[5]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[5]),
.Q(result_reg_56[5]),
.R(1'b0));
FDRE \result_reg_56_reg[6]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[6]),
.Q(result_reg_56[6]),
.R(1'b0));
FDRE \result_reg_56_reg[7]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[7]),
.Q(result_reg_56[7]),
.R(1'b0));
FDRE \result_reg_56_reg[8]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(result_reg_56[8]),
.R(1'b0));
FDRE \result_reg_56_reg[9]
(.C(ap_clk),
.CE(\result_reg_56[15]_i_1_n_0 ),
.D(p_1_in[9]),
.Q(result_reg_56[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_10
(.I0(result_reg_56[8]),
.I1(p_s_reg_45[8]),
.I2(result_reg_56[9]),
.I3(p_s_reg_45[9]),
.O(\tmp_3_reg_115[0]_i_10_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_11
(.I0(result_reg_56[6]),
.I1(p_s_reg_45[6]),
.I2(p_s_reg_45[7]),
.I3(result_reg_56[7]),
.O(\tmp_3_reg_115[0]_i_11_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_12
(.I0(result_reg_56[4]),
.I1(p_s_reg_45[4]),
.I2(p_s_reg_45[5]),
.I3(result_reg_56[5]),
.O(\tmp_3_reg_115[0]_i_12_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_13
(.I0(result_reg_56[2]),
.I1(p_s_reg_45[2]),
.I2(p_s_reg_45[3]),
.I3(result_reg_56[3]),
.O(\tmp_3_reg_115[0]_i_13_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_14
(.I0(result_reg_56[0]),
.I1(p_s_reg_45[0]),
.I2(p_s_reg_45[1]),
.I3(result_reg_56[1]),
.O(\tmp_3_reg_115[0]_i_14_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_15
(.I0(result_reg_56[6]),
.I1(p_s_reg_45[6]),
.I2(result_reg_56[7]),
.I3(p_s_reg_45[7]),
.O(\tmp_3_reg_115[0]_i_15_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_16
(.I0(result_reg_56[4]),
.I1(p_s_reg_45[4]),
.I2(result_reg_56[5]),
.I3(p_s_reg_45[5]),
.O(\tmp_3_reg_115[0]_i_16_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_17
(.I0(result_reg_56[2]),
.I1(p_s_reg_45[2]),
.I2(result_reg_56[3]),
.I3(p_s_reg_45[3]),
.O(\tmp_3_reg_115[0]_i_17_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_18
(.I0(result_reg_56[0]),
.I1(p_s_reg_45[0]),
.I2(result_reg_56[1]),
.I3(p_s_reg_45[1]),
.O(\tmp_3_reg_115[0]_i_18_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_3
(.I0(result_reg_56[14]),
.I1(p_s_reg_45[14]),
.I2(result_reg_56[15]),
.I3(p_s_reg_45[15]),
.O(\tmp_3_reg_115[0]_i_3_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_4
(.I0(result_reg_56[12]),
.I1(p_s_reg_45[12]),
.I2(p_s_reg_45[13]),
.I3(result_reg_56[13]),
.O(\tmp_3_reg_115[0]_i_4_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_5
(.I0(result_reg_56[10]),
.I1(p_s_reg_45[10]),
.I2(p_s_reg_45[11]),
.I3(result_reg_56[11]),
.O(\tmp_3_reg_115[0]_i_5_n_0 ));
LUT4 #(
.INIT(16'h2F02))
\tmp_3_reg_115[0]_i_6
(.I0(result_reg_56[8]),
.I1(p_s_reg_45[8]),
.I2(p_s_reg_45[9]),
.I3(result_reg_56[9]),
.O(\tmp_3_reg_115[0]_i_6_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_7
(.I0(result_reg_56[14]),
.I1(p_s_reg_45[14]),
.I2(p_s_reg_45[15]),
.I3(result_reg_56[15]),
.O(\tmp_3_reg_115[0]_i_7_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_8
(.I0(result_reg_56[12]),
.I1(p_s_reg_45[12]),
.I2(result_reg_56[13]),
.I3(p_s_reg_45[13]),
.O(\tmp_3_reg_115[0]_i_8_n_0 ));
LUT4 #(
.INIT(16'h9009))
\tmp_3_reg_115[0]_i_9
(.I0(result_reg_56[10]),
.I1(p_s_reg_45[10]),
.I2(result_reg_56[11]),
.I3(p_s_reg_45[11]),
.O(\tmp_3_reg_115[0]_i_9_n_0 ));
FDRE \tmp_3_reg_115_reg[0]
(.C(ap_clk),
.CE(a_assign_reg_1210),
.D(tmp_3_fu_72_p2),
.Q(tmp_3_reg_115),
.R(1'b0));
CARRY4 \tmp_3_reg_115_reg[0]_i_1
(.CI(\tmp_3_reg_115_reg[0]_i_2_n_0 ),
.CO({tmp_3_fu_72_p2,\tmp_3_reg_115_reg[0]_i_1_n_1 ,\tmp_3_reg_115_reg[0]_i_1_n_2 ,\tmp_3_reg_115_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\tmp_3_reg_115[0]_i_3_n_0 ,\tmp_3_reg_115[0]_i_4_n_0 ,\tmp_3_reg_115[0]_i_5_n_0 ,\tmp_3_reg_115[0]_i_6_n_0 }),
.O(\NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED [3:0]),
.S({\tmp_3_reg_115[0]_i_7_n_0 ,\tmp_3_reg_115[0]_i_8_n_0 ,\tmp_3_reg_115[0]_i_9_n_0 ,\tmp_3_reg_115[0]_i_10_n_0 }));
CARRY4 \tmp_3_reg_115_reg[0]_i_2
(.CI(1'b0),
.CO({\tmp_3_reg_115_reg[0]_i_2_n_0 ,\tmp_3_reg_115_reg[0]_i_2_n_1 ,\tmp_3_reg_115_reg[0]_i_2_n_2 ,\tmp_3_reg_115_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\tmp_3_reg_115[0]_i_11_n_0 ,\tmp_3_reg_115[0]_i_12_n_0 ,\tmp_3_reg_115[0]_i_13_n_0 ,\tmp_3_reg_115[0]_i_14_n_0 }),
.O(\NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED [3:0]),
.S({\tmp_3_reg_115[0]_i_15_n_0 ,\tmp_3_reg_115[0]_i_16_n_0 ,\tmp_3_reg_115[0]_i_17_n_0 ,\tmp_3_reg_115[0]_i_18_n_0 }));
endmodule
(* ORIG_REF_NAME = "gcd_gcd_bus_s_axi" *)
module gcd_block_design_gcd_0_1_gcd_gcd_bus_s_axi
(out,
s_axi_gcd_bus_RVALID,
SR,
interrupt,
D,
CO,
E,
\b_read_reg_102_reg[15] ,
\a_read_reg_107_reg[15] ,
s_axi_gcd_bus_RDATA,
ap_clk,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_BREADY,
Q,
\result_reg_56_reg[15] ,
\p_s_reg_45_reg[15] ,
s_axi_gcd_bus_ARADDR,
ap_rst_n,
s_axi_gcd_bus_AWADDR);
output [2:0]out;
output [1:0]s_axi_gcd_bus_RVALID;
output [0:0]SR;
output interrupt;
output [1:0]D;
output [0:0]CO;
output [0:0]E;
output [15:0]\b_read_reg_102_reg[15] ;
output [15:0]\a_read_reg_107_reg[15] ;
output [15:0]s_axi_gcd_bus_RDATA;
input ap_clk;
input s_axi_gcd_bus_ARVALID;
input s_axi_gcd_bus_RREADY;
input s_axi_gcd_bus_AWVALID;
input s_axi_gcd_bus_WVALID;
input [15:0]s_axi_gcd_bus_WDATA;
input [1:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_BREADY;
input [3:0]Q;
input [15:0]\result_reg_56_reg[15] ;
input [15:0]\p_s_reg_45_reg[15] ;
input [5:0]s_axi_gcd_bus_ARADDR;
input ap_rst_n;
input [5:0]s_axi_gcd_bus_AWADDR;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire \FSM_onehot_rstate[1]_i_1_n_0 ;
wire \FSM_onehot_rstate[2]_i_1_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_rstate_reg_n_0_[0] ;
wire \FSM_onehot_wstate[1]_i_1_n_0 ;
wire \FSM_onehot_wstate[2]_i_1_n_0 ;
wire \FSM_onehot_wstate[3]_i_2_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_wstate_reg_n_0_[0] ;
wire [3:0]Q;
wire [0:0]SR;
wire [15:0]\a_read_reg_107_reg[15] ;
wire ap_clk;
wire ap_done;
wire ap_idle;
wire ap_rst_n;
wire ap_start;
wire ar_hs;
wire [15:0]\b_read_reg_102_reg[15] ;
wire [15:0]int_a0;
wire \int_a[15]_i_1_n_0 ;
wire \int_a[15]_i_3_n_0 ;
wire int_ap_done;
wire int_ap_done1;
wire int_ap_done_i_1_n_0;
wire int_ap_idle;
wire int_ap_ready;
wire int_ap_start3_out;
wire int_ap_start_i_10_n_0;
wire int_ap_start_i_1_n_0;
wire int_ap_start_i_5_n_0;
wire int_ap_start_i_6_n_0;
wire int_ap_start_i_7_n_0;
wire int_ap_start_i_8_n_0;
wire int_ap_start_i_9_n_0;
wire int_ap_start_reg_i_2_n_3;
wire int_ap_start_reg_i_4_n_0;
wire int_ap_start_reg_i_4_n_1;
wire int_ap_start_reg_i_4_n_2;
wire int_ap_start_reg_i_4_n_3;
wire int_auto_restart;
wire int_auto_restart_i_1_n_0;
wire [15:0]int_b0;
wire \int_b[15]_i_1_n_0 ;
wire int_gie_i_1_n_0;
wire int_gie_reg_n_0;
wire \int_ier[0]_i_1_n_0 ;
wire \int_ier[1]_i_1_n_0 ;
wire \int_ier[1]_i_2_n_0 ;
wire \int_ier_reg_n_0_[0] ;
wire \int_ier_reg_n_0_[1] ;
wire int_isr6_out;
wire \int_isr[0]_i_1_n_0 ;
wire \int_isr[1]_i_1_n_0 ;
wire \int_isr_reg_n_0_[0] ;
wire [15:0]int_pResult;
wire int_pResult_ap_vld;
wire int_pResult_ap_vld1;
wire int_pResult_ap_vld_i_1_n_0;
wire interrupt;
(* RTL_KEEP = "yes" *) wire [2:0]out;
wire p_1_in;
wire [15:0]\p_s_reg_45_reg[15] ;
wire \rdata[0]_i_1_n_0 ;
wire \rdata[0]_i_2_n_0 ;
wire \rdata[0]_i_3_n_0 ;
wire \rdata[0]_i_4_n_0 ;
wire \rdata[10]_i_1_n_0 ;
wire \rdata[11]_i_1_n_0 ;
wire \rdata[12]_i_1_n_0 ;
wire \rdata[13]_i_1_n_0 ;
wire \rdata[14]_i_1_n_0 ;
wire \rdata[15]_i_1_n_0 ;
wire \rdata[15]_i_3_n_0 ;
wire \rdata[1]_i_1_n_0 ;
wire \rdata[1]_i_2_n_0 ;
wire \rdata[1]_i_3_n_0 ;
wire \rdata[1]_i_4_n_0 ;
wire \rdata[1]_i_5_n_0 ;
wire \rdata[2]_i_1_n_0 ;
wire \rdata[2]_i_2_n_0 ;
wire \rdata[3]_i_1_n_0 ;
wire \rdata[3]_i_2_n_0 ;
wire \rdata[4]_i_1_n_0 ;
wire \rdata[5]_i_1_n_0 ;
wire \rdata[6]_i_1_n_0 ;
wire \rdata[7]_i_1_n_0 ;
wire \rdata[7]_i_2_n_0 ;
wire \rdata[8]_i_1_n_0 ;
wire \rdata[9]_i_1_n_0 ;
wire [15:0]\result_reg_56_reg[15] ;
wire [5:0]s_axi_gcd_bus_ARADDR;
wire s_axi_gcd_bus_ARVALID;
wire [5:0]s_axi_gcd_bus_AWADDR;
wire s_axi_gcd_bus_AWVALID;
wire s_axi_gcd_bus_BREADY;
wire [15:0]s_axi_gcd_bus_RDATA;
wire s_axi_gcd_bus_RREADY;
(* RTL_KEEP = "yes" *) wire [1:0]s_axi_gcd_bus_RVALID;
wire [15:0]s_axi_gcd_bus_WDATA;
wire [1:0]s_axi_gcd_bus_WSTRB;
wire s_axi_gcd_bus_WVALID;
wire waddr;
wire \waddr_reg_n_0_[0] ;
wire \waddr_reg_n_0_[1] ;
wire \waddr_reg_n_0_[2] ;
wire \waddr_reg_n_0_[3] ;
wire \waddr_reg_n_0_[4] ;
wire \waddr_reg_n_0_[5] ;
wire [3:2]NLW_int_ap_start_reg_i_2_CO_UNCONNECTED;
wire [3:0]NLW_int_ap_start_reg_i_2_O_UNCONNECTED;
wire [3:0]NLW_int_ap_start_reg_i_4_O_UNCONNECTED;
LUT4 #(
.INIT(16'hF747))
\FSM_onehot_rstate[1]_i_1
(.I0(s_axi_gcd_bus_ARVALID),
.I1(s_axi_gcd_bus_RVALID[0]),
.I2(s_axi_gcd_bus_RVALID[1]),
.I3(s_axi_gcd_bus_RREADY),
.O(\FSM_onehot_rstate[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88F8))
\FSM_onehot_rstate[2]_i_1
(.I0(s_axi_gcd_bus_ARVALID),
.I1(s_axi_gcd_bus_RVALID[0]),
.I2(s_axi_gcd_bus_RVALID[1]),
.I3(s_axi_gcd_bus_RREADY),
.O(\FSM_onehot_rstate[2]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_rstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(1'b0),
.Q(\FSM_onehot_rstate_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_rstate_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_rstate[1]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RVALID[0]),
.R(SR));
(* FSM_ENCODED_STATES = "RDIDLE:010,RDDATA:100,iSTATE:001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_rstate_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_rstate[2]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RVALID[1]),
.R(SR));
LUT5 #(
.INIT(32'h888BFF8B))
\FSM_onehot_wstate[1]_i_1
(.I0(s_axi_gcd_bus_BREADY),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.I4(s_axi_gcd_bus_AWVALID),
.O(\FSM_onehot_wstate[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_wstate[2]_i_1
(.I0(s_axi_gcd_bus_AWVALID),
.I1(out[0]),
.I2(s_axi_gcd_bus_WVALID),
.I3(out[1]),
.O(\FSM_onehot_wstate[2]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\FSM_onehot_wstate[3]_i_1
(.I0(ap_rst_n),
.O(SR));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_wstate[3]_i_2
(.I0(s_axi_gcd_bus_WVALID),
.I1(out[1]),
.I2(s_axi_gcd_bus_BREADY),
.I3(out[2]),
.O(\FSM_onehot_wstate[3]_i_2_n_0 ));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_wstate_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(1'b0),
.Q(\FSM_onehot_wstate_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[1]_i_1_n_0 ),
.Q(out[0]),
.R(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[2]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[2]_i_1_n_0 ),
.Q(out[1]),
.R(SR));
(* FSM_ENCODED_STATES = "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_wstate_reg[3]
(.C(ap_clk),
.CE(1'b1),
.D(\FSM_onehot_wstate[3]_i_2_n_0 ),
.Q(out[2]),
.R(SR));
LUT4 #(
.INIT(16'hFA30))
\ap_CS_fsm[0]_i_1
(.I0(CO),
.I1(ap_start),
.I2(Q[0]),
.I3(Q[2]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00001000))
\ap_CS_fsm[1]_i_1
(.I0(Q[1]),
.I1(Q[3]),
.I2(Q[0]),
.I3(ap_start),
.I4(Q[2]),
.O(D[1]));
LUT2 #(
.INIT(4'h8))
\b_read_reg_102[15]_i_1
(.I0(Q[0]),
.I1(ap_start),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\int_a[0]_i_1
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [0]),
.O(int_a0[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\int_a[10]_i_1
(.I0(s_axi_gcd_bus_WDATA[10]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [10]),
.O(int_a0[10]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\int_a[11]_i_1
(.I0(s_axi_gcd_bus_WDATA[11]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [11]),
.O(int_a0[11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_a[12]_i_1
(.I0(s_axi_gcd_bus_WDATA[12]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [12]),
.O(int_a0[12]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\int_a[13]_i_1
(.I0(s_axi_gcd_bus_WDATA[13]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [13]),
.O(int_a0[13]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_a[14]_i_1
(.I0(s_axi_gcd_bus_WDATA[14]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [14]),
.O(int_a0[14]));
LUT4 #(
.INIT(16'h0008))
\int_a[15]_i_1
(.I0(\waddr_reg_n_0_[4] ),
.I1(\int_a[15]_i_3_n_0 ),
.I2(\waddr_reg_n_0_[2] ),
.I3(\waddr_reg_n_0_[3] ),
.O(\int_a[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\int_a[15]_i_2
(.I0(s_axi_gcd_bus_WDATA[15]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [15]),
.O(int_a0[15]));
LUT5 #(
.INIT(32'h00001000))
\int_a[15]_i_3
(.I0(\waddr_reg_n_0_[0] ),
.I1(\waddr_reg_n_0_[5] ),
.I2(out[1]),
.I3(s_axi_gcd_bus_WVALID),
.I4(\waddr_reg_n_0_[1] ),
.O(\int_a[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\int_a[1]_i_1
(.I0(s_axi_gcd_bus_WDATA[1]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [1]),
.O(int_a0[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\int_a[2]_i_1
(.I0(s_axi_gcd_bus_WDATA[2]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [2]),
.O(int_a0[2]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_a[3]_i_1
(.I0(s_axi_gcd_bus_WDATA[3]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [3]),
.O(int_a0[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\int_a[4]_i_1
(.I0(s_axi_gcd_bus_WDATA[4]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [4]),
.O(int_a0[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\int_a[5]_i_1
(.I0(s_axi_gcd_bus_WDATA[5]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [5]),
.O(int_a0[5]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\int_a[6]_i_1
(.I0(s_axi_gcd_bus_WDATA[6]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [6]),
.O(int_a0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\int_a[7]_i_1
(.I0(s_axi_gcd_bus_WDATA[7]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\a_read_reg_107_reg[15] [7]),
.O(int_a0[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\int_a[8]_i_1
(.I0(s_axi_gcd_bus_WDATA[8]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [8]),
.O(int_a0[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\int_a[9]_i_1
(.I0(s_axi_gcd_bus_WDATA[9]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\a_read_reg_107_reg[15] [9]),
.O(int_a0[9]));
FDRE #(
.INIT(1'b0))
\int_a_reg[0]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[0]),
.Q(\a_read_reg_107_reg[15] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[10]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[10]),
.Q(\a_read_reg_107_reg[15] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[11]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[11]),
.Q(\a_read_reg_107_reg[15] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[12]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[12]),
.Q(\a_read_reg_107_reg[15] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[13]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[13]),
.Q(\a_read_reg_107_reg[15] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[14]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[14]),
.Q(\a_read_reg_107_reg[15] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[15]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[15]),
.Q(\a_read_reg_107_reg[15] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[1]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[1]),
.Q(\a_read_reg_107_reg[15] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[2]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[2]),
.Q(\a_read_reg_107_reg[15] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[3]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[3]),
.Q(\a_read_reg_107_reg[15] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[4]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[4]),
.Q(\a_read_reg_107_reg[15] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[5]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[5]),
.Q(\a_read_reg_107_reg[15] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[6]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[6]),
.Q(\a_read_reg_107_reg[15] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[7]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[7]),
.Q(\a_read_reg_107_reg[15] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[8]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[8]),
.Q(\a_read_reg_107_reg[15] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_a_reg[9]
(.C(ap_clk),
.CE(\int_a[15]_i_1_n_0 ),
.D(int_a0[9]),
.Q(\a_read_reg_107_reg[15] [9]),
.R(SR));
LUT6 #(
.INIT(64'h8FFFFFFF88888888))
int_ap_done_i_1
(.I0(Q[2]),
.I1(CO),
.I2(s_axi_gcd_bus_RVALID[0]),
.I3(s_axi_gcd_bus_ARVALID),
.I4(int_ap_done1),
.I5(int_ap_done),
.O(int_ap_done_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
int_ap_done_i_2
(.I0(s_axi_gcd_bus_ARADDR[5]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(s_axi_gcd_bus_ARADDR[1]),
.I3(s_axi_gcd_bus_ARADDR[0]),
.I4(s_axi_gcd_bus_ARADDR[3]),
.I5(s_axi_gcd_bus_ARADDR[2]),
.O(int_ap_done1));
FDRE #(
.INIT(1'b0))
int_ap_done_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_ap_done_i_1_n_0),
.Q(int_ap_done),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
int_ap_idle_i_1
(.I0(Q[0]),
.I1(ap_start),
.O(ap_idle));
FDRE int_ap_idle_reg
(.C(ap_clk),
.CE(1'b1),
.D(ap_idle),
.Q(int_ap_idle),
.R(SR));
LUT2 #(
.INIT(4'h8))
int_ap_ready_i_1
(.I0(CO),
.I1(Q[2]),
.O(ap_done));
FDRE int_ap_ready_reg
(.C(ap_clk),
.CE(1'b1),
.D(ap_done),
.Q(int_ap_ready),
.R(SR));
LUT5 #(
.INIT(32'hFFBFFF80))
int_ap_start_i_1
(.I0(int_auto_restart),
.I1(Q[2]),
.I2(CO),
.I3(int_ap_start3_out),
.I4(ap_start),
.O(int_ap_start_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
int_ap_start_i_10
(.I0(\result_reg_56_reg[15] [0]),
.I1(\p_s_reg_45_reg[15] [0]),
.I2(\p_s_reg_45_reg[15] [2]),
.I3(\result_reg_56_reg[15] [2]),
.I4(\p_s_reg_45_reg[15] [1]),
.I5(\result_reg_56_reg[15] [1]),
.O(int_ap_start_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000800))
int_ap_start_i_3
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\waddr_reg_n_0_[2] ),
.I3(\int_ier[1]_i_2_n_0 ),
.I4(\waddr_reg_n_0_[3] ),
.O(int_ap_start3_out));
LUT2 #(
.INIT(4'h9))
int_ap_start_i_5
(.I0(\p_s_reg_45_reg[15] [15]),
.I1(\result_reg_56_reg[15] [15]),
.O(int_ap_start_i_5_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
int_ap_start_i_6
(.I0(\result_reg_56_reg[15] [12]),
.I1(\p_s_reg_45_reg[15] [12]),
.I2(\p_s_reg_45_reg[15] [14]),
.I3(\result_reg_56_reg[15] [14]),
.I4(\p_s_reg_45_reg[15] [13]),
.I5(\result_reg_56_reg[15] [13]),
.O(int_ap_start_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
int_ap_start_i_7
(.I0(\result_reg_56_reg[15] [9]),
.I1(\p_s_reg_45_reg[15] [9]),
.I2(\p_s_reg_45_reg[15] [11]),
.I3(\result_reg_56_reg[15] [11]),
.I4(\p_s_reg_45_reg[15] [10]),
.I5(\result_reg_56_reg[15] [10]),
.O(int_ap_start_i_7_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
int_ap_start_i_8
(.I0(\result_reg_56_reg[15] [6]),
.I1(\p_s_reg_45_reg[15] [6]),
.I2(\p_s_reg_45_reg[15] [8]),
.I3(\result_reg_56_reg[15] [8]),
.I4(\p_s_reg_45_reg[15] [7]),
.I5(\result_reg_56_reg[15] [7]),
.O(int_ap_start_i_8_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
int_ap_start_i_9
(.I0(\result_reg_56_reg[15] [3]),
.I1(\p_s_reg_45_reg[15] [3]),
.I2(\p_s_reg_45_reg[15] [5]),
.I3(\result_reg_56_reg[15] [5]),
.I4(\p_s_reg_45_reg[15] [4]),
.I5(\result_reg_56_reg[15] [4]),
.O(int_ap_start_i_9_n_0));
FDRE #(
.INIT(1'b0))
int_ap_start_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_ap_start_i_1_n_0),
.Q(ap_start),
.R(SR));
CARRY4 int_ap_start_reg_i_2
(.CI(int_ap_start_reg_i_4_n_0),
.CO({NLW_int_ap_start_reg_i_2_CO_UNCONNECTED[3:2],CO,int_ap_start_reg_i_2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_int_ap_start_reg_i_2_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,int_ap_start_i_5_n_0,int_ap_start_i_6_n_0}));
CARRY4 int_ap_start_reg_i_4
(.CI(1'b0),
.CO({int_ap_start_reg_i_4_n_0,int_ap_start_reg_i_4_n_1,int_ap_start_reg_i_4_n_2,int_ap_start_reg_i_4_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_int_ap_start_reg_i_4_O_UNCONNECTED[3:0]),
.S({int_ap_start_i_7_n_0,int_ap_start_i_8_n_0,int_ap_start_i_9_n_0,int_ap_start_i_10_n_0}));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
int_auto_restart_i_1
(.I0(s_axi_gcd_bus_WDATA[7]),
.I1(\waddr_reg_n_0_[3] ),
.I2(\int_ier[1]_i_2_n_0 ),
.I3(\waddr_reg_n_0_[2] ),
.I4(s_axi_gcd_bus_WSTRB[0]),
.I5(int_auto_restart),
.O(int_auto_restart_i_1_n_0));
FDRE #(
.INIT(1'b0))
int_auto_restart_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_auto_restart_i_1_n_0),
.Q(int_auto_restart),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\int_b[0]_i_1
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [0]),
.O(int_b0[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_b[10]_i_1
(.I0(s_axi_gcd_bus_WDATA[10]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [10]),
.O(int_b0[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\int_b[11]_i_1
(.I0(s_axi_gcd_bus_WDATA[11]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [11]),
.O(int_b0[11]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_b[12]_i_1
(.I0(s_axi_gcd_bus_WDATA[12]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [12]),
.O(int_b0[12]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\int_b[13]_i_1
(.I0(s_axi_gcd_bus_WDATA[13]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [13]),
.O(int_b0[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_b[14]_i_1
(.I0(s_axi_gcd_bus_WDATA[14]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [14]),
.O(int_b0[14]));
LUT4 #(
.INIT(16'h0080))
\int_b[15]_i_1
(.I0(\waddr_reg_n_0_[3] ),
.I1(\waddr_reg_n_0_[4] ),
.I2(\int_a[15]_i_3_n_0 ),
.I3(\waddr_reg_n_0_[2] ),
.O(\int_b[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\int_b[15]_i_2
(.I0(s_axi_gcd_bus_WDATA[15]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [15]),
.O(int_b0[15]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\int_b[1]_i_1
(.I0(s_axi_gcd_bus_WDATA[1]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [1]),
.O(int_b0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_b[2]_i_1
(.I0(s_axi_gcd_bus_WDATA[2]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [2]),
.O(int_b0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_b[3]_i_1
(.I0(s_axi_gcd_bus_WDATA[3]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [3]),
.O(int_b0[3]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\int_b[4]_i_1
(.I0(s_axi_gcd_bus_WDATA[4]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [4]),
.O(int_b0[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\int_b[5]_i_1
(.I0(s_axi_gcd_bus_WDATA[5]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [5]),
.O(int_b0[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\int_b[6]_i_1
(.I0(s_axi_gcd_bus_WDATA[6]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [6]),
.O(int_b0[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\int_b[7]_i_1
(.I0(s_axi_gcd_bus_WDATA[7]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\b_read_reg_102_reg[15] [7]),
.O(int_b0[7]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\int_b[8]_i_1
(.I0(s_axi_gcd_bus_WDATA[8]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [8]),
.O(int_b0[8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\int_b[9]_i_1
(.I0(s_axi_gcd_bus_WDATA[9]),
.I1(s_axi_gcd_bus_WSTRB[1]),
.I2(\b_read_reg_102_reg[15] [9]),
.O(int_b0[9]));
FDRE #(
.INIT(1'b0))
\int_b_reg[0]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[0]),
.Q(\b_read_reg_102_reg[15] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[10]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[10]),
.Q(\b_read_reg_102_reg[15] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[11]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[11]),
.Q(\b_read_reg_102_reg[15] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[12]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[12]),
.Q(\b_read_reg_102_reg[15] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[13]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[13]),
.Q(\b_read_reg_102_reg[15] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[14]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[14]),
.Q(\b_read_reg_102_reg[15] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[15]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[15]),
.Q(\b_read_reg_102_reg[15] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[1]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[1]),
.Q(\b_read_reg_102_reg[15] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[2]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[2]),
.Q(\b_read_reg_102_reg[15] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[3]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[3]),
.Q(\b_read_reg_102_reg[15] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[4]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[4]),
.Q(\b_read_reg_102_reg[15] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[5]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[5]),
.Q(\b_read_reg_102_reg[15] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[6]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[6]),
.Q(\b_read_reg_102_reg[15] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[7]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[7]),
.Q(\b_read_reg_102_reg[15] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[8]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[8]),
.Q(\b_read_reg_102_reg[15] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_b_reg[9]
(.C(ap_clk),
.CE(\int_b[15]_i_1_n_0 ),
.D(int_b0[9]),
.Q(\b_read_reg_102_reg[15] [9]),
.R(SR));
LUT6 #(
.INIT(64'hFBFFFFFF08000000))
int_gie_i_1
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\waddr_reg_n_0_[3] ),
.I3(\waddr_reg_n_0_[2] ),
.I4(\int_ier[1]_i_2_n_0 ),
.I5(int_gie_reg_n_0),
.O(int_gie_i_1_n_0));
FDRE #(
.INIT(1'b0))
int_gie_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_gie_i_1_n_0),
.Q(int_gie_reg_n_0),
.R(SR));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\int_ier[0]_i_1
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\int_ier[1]_i_2_n_0 ),
.I3(\waddr_reg_n_0_[2] ),
.I4(\waddr_reg_n_0_[3] ),
.I5(\int_ier_reg_n_0_[0] ),
.O(\int_ier[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\int_ier[1]_i_1
(.I0(s_axi_gcd_bus_WDATA[1]),
.I1(s_axi_gcd_bus_WSTRB[0]),
.I2(\int_ier[1]_i_2_n_0 ),
.I3(\waddr_reg_n_0_[2] ),
.I4(\waddr_reg_n_0_[3] ),
.I5(\int_ier_reg_n_0_[1] ),
.O(\int_ier[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\int_ier[1]_i_2
(.I0(\waddr_reg_n_0_[1] ),
.I1(s_axi_gcd_bus_WVALID),
.I2(out[1]),
.I3(\waddr_reg_n_0_[5] ),
.I4(\waddr_reg_n_0_[0] ),
.I5(\waddr_reg_n_0_[4] ),
.O(\int_ier[1]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\int_ier_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\int_ier[0]_i_1_n_0 ),
.Q(\int_ier_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_ier_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\int_ier[1]_i_1_n_0 ),
.Q(\int_ier_reg_n_0_[1] ),
.R(SR));
LUT6 #(
.INIT(64'hF7777777F8888888))
\int_isr[0]_i_1
(.I0(s_axi_gcd_bus_WDATA[0]),
.I1(int_isr6_out),
.I2(\int_ier_reg_n_0_[0] ),
.I3(CO),
.I4(Q[2]),
.I5(\int_isr_reg_n_0_[0] ),
.O(\int_isr[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\int_isr[0]_i_2
(.I0(s_axi_gcd_bus_WSTRB[0]),
.I1(\waddr_reg_n_0_[2] ),
.I2(\int_ier[1]_i_2_n_0 ),
.I3(\waddr_reg_n_0_[3] ),
.O(int_isr6_out));
LUT6 #(
.INIT(64'hF7777777F8888888))
\int_isr[1]_i_1
(.I0(s_axi_gcd_bus_WDATA[1]),
.I1(int_isr6_out),
.I2(\int_ier_reg_n_0_[1] ),
.I3(CO),
.I4(Q[2]),
.I5(p_1_in),
.O(\int_isr[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\int_isr_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\int_isr[0]_i_1_n_0 ),
.Q(\int_isr_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_isr_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\int_isr[1]_i_1_n_0 ),
.Q(p_1_in),
.R(SR));
LUT6 #(
.INIT(64'h8FFFFFFF88888888))
int_pResult_ap_vld_i_1
(.I0(Q[2]),
.I1(CO),
.I2(s_axi_gcd_bus_RVALID[0]),
.I3(s_axi_gcd_bus_ARVALID),
.I4(int_pResult_ap_vld1),
.I5(int_pResult_ap_vld),
.O(int_pResult_ap_vld_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000001000))
int_pResult_ap_vld_i_2
(.I0(s_axi_gcd_bus_ARADDR[1]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(s_axi_gcd_bus_ARADDR[5]),
.I3(s_axi_gcd_bus_ARADDR[2]),
.I4(s_axi_gcd_bus_ARADDR[3]),
.I5(s_axi_gcd_bus_ARADDR[0]),
.O(int_pResult_ap_vld1));
FDRE int_pResult_ap_vld_reg
(.C(ap_clk),
.CE(1'b1),
.D(int_pResult_ap_vld_i_1_n_0),
.Q(int_pResult_ap_vld),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[0]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [0]),
.Q(int_pResult[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[10]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [10]),
.Q(int_pResult[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[11]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [11]),
.Q(int_pResult[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[12]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [12]),
.Q(int_pResult[12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[13]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [13]),
.Q(int_pResult[13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[14]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [14]),
.Q(int_pResult[14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[15]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [15]),
.Q(int_pResult[15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[1]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [1]),
.Q(int_pResult[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[2]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [2]),
.Q(int_pResult[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[3]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [3]),
.Q(int_pResult[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[4]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [4]),
.Q(int_pResult[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[5]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [5]),
.Q(int_pResult[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[6]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [6]),
.Q(int_pResult[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[7]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [7]),
.Q(int_pResult[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[8]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [8]),
.Q(int_pResult[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\int_pResult_reg[9]
(.C(ap_clk),
.CE(ap_done),
.D(\p_s_reg_45_reg[15] [9]),
.Q(int_pResult[9]),
.R(SR));
LUT3 #(
.INIT(8'hE0))
interrupt_INST_0
(.I0(p_1_in),
.I1(\int_isr_reg_n_0_[0] ),
.I2(int_gie_reg_n_0),
.O(interrupt));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\rdata[0]_i_1
(.I0(\rdata[0]_i_2_n_0 ),
.I1(s_axi_gcd_bus_ARADDR[2]),
.I2(\rdata[0]_i_3_n_0 ),
.I3(\rdata[1]_i_4_n_0 ),
.I4(ar_hs),
.I5(s_axi_gcd_bus_RDATA[0]),
.O(\rdata[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\rdata[0]_i_2
(.I0(\int_ier_reg_n_0_[0] ),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(\b_read_reg_102_reg[15] [0]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(s_axi_gcd_bus_ARADDR[3]),
.I5(\rdata[0]_i_4_n_0 ),
.O(\rdata[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0033223000002230))
\rdata[0]_i_3
(.I0(int_pResult_ap_vld),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_gie_reg_n_0),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(s_axi_gcd_bus_ARADDR[3]),
.I5(\int_isr_reg_n_0_[0] ),
.O(\rdata[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[0]_i_4
(.I0(\a_read_reg_107_reg[15] [0]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_pResult[0]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(ap_start),
.O(\rdata[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[10]_i_1
(.I0(\b_read_reg_102_reg[15] [10]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [10]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[10]),
.O(\rdata[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[11]_i_1
(.I0(\b_read_reg_102_reg[15] [11]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [11]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[11]),
.O(\rdata[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[12]_i_1
(.I0(\b_read_reg_102_reg[15] [12]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [12]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[12]),
.O(\rdata[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[13]_i_1
(.I0(\b_read_reg_102_reg[15] [13]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [13]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[13]),
.O(\rdata[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[14]_i_1
(.I0(\b_read_reg_102_reg[15] [14]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [14]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[14]),
.O(\rdata[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h88888880))
\rdata[15]_i_1
(.I0(s_axi_gcd_bus_ARVALID),
.I1(s_axi_gcd_bus_RVALID[0]),
.I2(s_axi_gcd_bus_ARADDR[1]),
.I3(s_axi_gcd_bus_ARADDR[0]),
.I4(s_axi_gcd_bus_ARADDR[2]),
.O(\rdata[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\rdata[15]_i_2
(.I0(s_axi_gcd_bus_RVALID[0]),
.I1(s_axi_gcd_bus_ARVALID),
.O(ar_hs));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[15]_i_3
(.I0(\b_read_reg_102_reg[15] [15]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [15]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[15]),
.O(\rdata[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\rdata[1]_i_1
(.I0(\rdata[1]_i_2_n_0 ),
.I1(s_axi_gcd_bus_ARADDR[2]),
.I2(\rdata[1]_i_3_n_0 ),
.I3(\rdata[1]_i_4_n_0 ),
.I4(ar_hs),
.I5(s_axi_gcd_bus_RDATA[1]),
.O(\rdata[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\rdata[1]_i_2
(.I0(\int_ier_reg_n_0_[1] ),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(\b_read_reg_102_reg[15] [1]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(s_axi_gcd_bus_ARADDR[3]),
.I5(\rdata[1]_i_5_n_0 ),
.O(\rdata[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1000))
\rdata[1]_i_3
(.I0(s_axi_gcd_bus_ARADDR[4]),
.I1(s_axi_gcd_bus_ARADDR[5]),
.I2(s_axi_gcd_bus_ARADDR[3]),
.I3(p_1_in),
.O(\rdata[1]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\rdata[1]_i_4
(.I0(s_axi_gcd_bus_ARADDR[1]),
.I1(s_axi_gcd_bus_ARADDR[0]),
.O(\rdata[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[1]_i_5
(.I0(\a_read_reg_107_reg[15] [1]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_pResult[1]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(int_ap_done),
.O(\rdata[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'h40FF4000))
\rdata[2]_i_1
(.I0(s_axi_gcd_bus_ARADDR[5]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(\b_read_reg_102_reg[15] [2]),
.I3(s_axi_gcd_bus_ARADDR[3]),
.I4(\rdata[2]_i_2_n_0 ),
.O(\rdata[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[2]_i_2
(.I0(\a_read_reg_107_reg[15] [2]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_pResult[2]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(int_ap_idle),
.O(\rdata[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h40FF4000))
\rdata[3]_i_1
(.I0(s_axi_gcd_bus_ARADDR[5]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(\b_read_reg_102_reg[15] [3]),
.I3(s_axi_gcd_bus_ARADDR[3]),
.I4(\rdata[3]_i_2_n_0 ),
.O(\rdata[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[3]_i_2
(.I0(\a_read_reg_107_reg[15] [3]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_pResult[3]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(int_ap_ready),
.O(\rdata[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[4]_i_1
(.I0(\b_read_reg_102_reg[15] [4]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [4]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[4]),
.O(\rdata[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[5]_i_1
(.I0(\b_read_reg_102_reg[15] [5]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [5]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[5]),
.O(\rdata[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[6]_i_1
(.I0(\b_read_reg_102_reg[15] [6]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [6]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[6]),
.O(\rdata[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h40FF4000))
\rdata[7]_i_1
(.I0(s_axi_gcd_bus_ARADDR[5]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(\b_read_reg_102_reg[15] [7]),
.I3(s_axi_gcd_bus_ARADDR[3]),
.I4(\rdata[7]_i_2_n_0 ),
.O(\rdata[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\rdata[7]_i_2
(.I0(\a_read_reg_107_reg[15] [7]),
.I1(s_axi_gcd_bus_ARADDR[4]),
.I2(int_pResult[7]),
.I3(s_axi_gcd_bus_ARADDR[5]),
.I4(int_auto_restart),
.O(\rdata[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[8]_i_1
(.I0(\b_read_reg_102_reg[15] [8]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [8]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[8]),
.O(\rdata[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0033B8000000B800))
\rdata[9]_i_1
(.I0(\b_read_reg_102_reg[15] [9]),
.I1(s_axi_gcd_bus_ARADDR[3]),
.I2(\a_read_reg_107_reg[15] [9]),
.I3(s_axi_gcd_bus_ARADDR[4]),
.I4(s_axi_gcd_bus_ARADDR[5]),
.I5(int_pResult[9]),
.O(\rdata[9]_i_1_n_0 ));
FDRE \rdata_reg[0]
(.C(ap_clk),
.CE(1'b1),
.D(\rdata[0]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[0]),
.R(1'b0));
FDRE \rdata_reg[10]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[10]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[10]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[11]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[11]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[11]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[12]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[12]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[12]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[13]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[13]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[13]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[14]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[14]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[14]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[15]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[15]_i_3_n_0 ),
.Q(s_axi_gcd_bus_RDATA[15]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[1]
(.C(ap_clk),
.CE(1'b1),
.D(\rdata[1]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[1]),
.R(1'b0));
FDRE \rdata_reg[2]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[2]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[2]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[3]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[3]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[3]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[4]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[4]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[4]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[5]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[5]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[5]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[6]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[6]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[6]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[7]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[7]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[7]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[8]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[8]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[8]),
.R(\rdata[15]_i_1_n_0 ));
FDRE \rdata_reg[9]
(.C(ap_clk),
.CE(ar_hs),
.D(\rdata[9]_i_1_n_0 ),
.Q(s_axi_gcd_bus_RDATA[9]),
.R(\rdata[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\waddr[5]_i_1
(.I0(out[0]),
.I1(s_axi_gcd_bus_AWVALID),
.O(waddr));
FDRE \waddr_reg[0]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[0]),
.Q(\waddr_reg_n_0_[0] ),
.R(1'b0));
FDRE \waddr_reg[1]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[1]),
.Q(\waddr_reg_n_0_[1] ),
.R(1'b0));
FDRE \waddr_reg[2]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[2]),
.Q(\waddr_reg_n_0_[2] ),
.R(1'b0));
FDRE \waddr_reg[3]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[3]),
.Q(\waddr_reg_n_0_[3] ),
.R(1'b0));
FDRE \waddr_reg[4]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[4]),
.Q(\waddr_reg_n_0_[4] ),
.R(1'b0));
FDRE \waddr_reg[5]
(.C(ap_clk),
.CE(waddr),
.D(s_axi_gcd_bus_AWADDR[5]),
.Q(\waddr_reg_n_0_[5] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
#[global]
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
#[global]
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module hilbert(CLK,RST,ED,START,DReal,DImag,RDY,DOReal,DOImag);
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output reg RDY;
output reg signed [total_bits-1:0] DOReal;
output reg signed [total_bits-1:0] DOImag;
wire rdy1;
wire signed [total_bits-1:0] dr1,di1;
wire start1;
reg startReg;
wire [total_bits-1:0] inr1,ini1;
reg signed [total_bits-1:0] RE,IM;
assign inr1 = (state==0)?DReal:RE;
assign ini1 = (state==0)?DImag:IM;
assign start1 = (state==0)?START:startReg;
reg signed [total_bits-1:0] dataREstage1[0:31];
reg signed [total_bits-1:0] dataIMstage1[0:31];
fft32 #(total_bits) FF(.CLK(CLK),.RST(RST),.ED(ED),.START(start1),.DReal(inr1),.DImag(ini1),.RDY(rdy1),.DOReal(dr1),.DOImag(di1),.ifft(1'b0));
reg [5:0] count;
reg [2:0] state;
reg flag;
initial begin
state<=0;
count<=0;
flag<=0;
startReg<=0;
dataREstage1[0]<=0;
dataIMstage1[0]<=0;
dataREstage1[16]<=0;
dataIMstage1[16]<=0;
end
always@(posedge CLK) begin
if(RST) begin
count<=32;
state<=0;
end
else if(START) begin
count<=0;
state<=0;
end
else if(ED)begin
RDY<=0;startReg<=0;
if(rdy1)begin
if(state==0)begin
state<=1;
count<=1;
end
if(state==2)begin
state<=3;
count<=1;
end
end
if(state==1)begin
if(count>=1&&count<=15)begin
dataREstage1[count]<=di1;
dataIMstage1[count]<=-1*dr1;
end
else if(count>=17&&count<=31)begin
dataREstage1[count]<=-1*di1;
dataIMstage1[count]<=dr1;
end
if(count<32)
count<=count+1;
//if(count<32)
//$display("count:%d %d+i%d",count-1,dataREstage1[count-1],dataIMstage1[count-1]);
if(count==31)
flag<=1;
if(count==32&&flag==1)begin
startReg<=1;state=2;flag<=0;count<=0;end
end
if(state==2)begin
RE<=dataREstage1[count];
IM<=dataIMstage1[count];
if(count<32)
count<=count+1;
end
if(state==3)begin
dataREstage1[32-count]<=(dr1>>>5);
dataIMstage1[32-count]<=(di1>>>5);
if(count<32)
count<=count+1;
if(count==31) begin
state<=4; count<=0;RDY<=1;end
//if(count<32)
//$display("count:%d %d+i%d",count-1,dataREstage1[count-1],dataIMstage1[count-1]);
end
else if(state==2&&rdy1) begin
dataREstage1[0]<=(dr1>>>5);
dataIMstage1[0]<=(di1>>>5);
end
if(state==4) begin
//$display("count:%d ")
DOReal<=dataREstage1[count];
DOImag<=dataIMstage1[count];
if(count<32)
count<=count+1;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Wed May 03 18:20:15 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/kernel-on-chip/hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_stub.v
// Design : bd_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module bd_clk_wiz_0_0(clk_ref_i, aclk, sys_clk_i, resetn, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_ref_i,aclk,sys_clk_i,resetn,clk_in1" */;
output clk_ref_i;
output aclk;
output sys_clk_i;
input resetn;
input clk_in1;
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_addr_map O 1 const
// slave_awready O 1 reg
// slave_wready O 1 reg
// slave_bvalid O 1 reg
// slave_bid O 4 reg
// slave_bresp O 2 reg
// slave_arready O 1 reg
// slave_rvalid O 1 reg
// slave_rid O 4 reg
// slave_rdata O 64 reg
// slave_rresp O 2 reg
// slave_rlast O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// slave_awvalid I 1
// slave_awid I 4 reg
// slave_awaddr I 64 reg
// slave_awlen I 8 reg
// slave_awsize I 3 reg
// slave_awburst I 2 reg
// slave_awlock I 1 reg
// slave_awcache I 4 reg
// slave_awprot I 3 reg
// slave_awqos I 4 reg
// slave_awregion I 4 reg
// slave_wvalid I 1
// slave_wdata I 64 reg
// slave_wstrb I 8 reg
// slave_wlast I 1 reg
// slave_bready I 1
// slave_arvalid I 1
// slave_arid I 4 reg
// slave_araddr I 64 reg
// slave_arlen I 8 reg
// slave_arsize I 3 reg
// slave_arburst I 2 reg
// slave_arlock I 1 reg
// slave_arcache I 4 reg
// slave_arprot I 3 reg
// slave_arqos I 4 reg
// slave_arregion I 4 reg
// slave_rready I 1
// EN_set_addr_map I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBoot_ROM(CLK,
RST_N,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
slave_awvalid,
slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion,
slave_awready,
slave_wvalid,
slave_wdata,
slave_wstrb,
slave_wlast,
slave_wready,
slave_bvalid,
slave_bid,
slave_bresp,
slave_bready,
slave_arvalid,
slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion,
slave_arready,
slave_rvalid,
slave_rid,
slave_rdata,
slave_rresp,
slave_rlast,
slave_rready);
input CLK;
input RST_N;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method slave_m_awvalid
input slave_awvalid;
input [3 : 0] slave_awid;
input [63 : 0] slave_awaddr;
input [7 : 0] slave_awlen;
input [2 : 0] slave_awsize;
input [1 : 0] slave_awburst;
input slave_awlock;
input [3 : 0] slave_awcache;
input [2 : 0] slave_awprot;
input [3 : 0] slave_awqos;
input [3 : 0] slave_awregion;
// value method slave_m_awready
output slave_awready;
// action method slave_m_wvalid
input slave_wvalid;
input [63 : 0] slave_wdata;
input [7 : 0] slave_wstrb;
input slave_wlast;
// value method slave_m_wready
output slave_wready;
// value method slave_m_bvalid
output slave_bvalid;
// value method slave_m_bid
output [3 : 0] slave_bid;
// value method slave_m_bresp
output [1 : 0] slave_bresp;
// value method slave_m_buser
// action method slave_m_bready
input slave_bready;
// action method slave_m_arvalid
input slave_arvalid;
input [3 : 0] slave_arid;
input [63 : 0] slave_araddr;
input [7 : 0] slave_arlen;
input [2 : 0] slave_arsize;
input [1 : 0] slave_arburst;
input slave_arlock;
input [3 : 0] slave_arcache;
input [2 : 0] slave_arprot;
input [3 : 0] slave_arqos;
input [3 : 0] slave_arregion;
// value method slave_m_arready
output slave_arready;
// value method slave_m_rvalid
output slave_rvalid;
// value method slave_m_rid
output [3 : 0] slave_rid;
// value method slave_m_rdata
output [63 : 0] slave_rdata;
// value method slave_m_rresp
output [1 : 0] slave_rresp;
// value method slave_m_rlast
output slave_rlast;
// value method slave_m_ruser
// action method slave_m_rready
input slave_rready;
// signals for module outputs
wire [63 : 0] slave_rdata;
wire [3 : 0] slave_bid, slave_rid;
wire [1 : 0] slave_bresp, slave_rresp;
wire RDY_set_addr_map,
slave_arready,
slave_awready,
slave_bvalid,
slave_rlast,
slave_rvalid,
slave_wready;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_module_ready
reg rg_module_ready;
wire rg_module_ready$D_IN, rg_module_ready$EN;
// ports of submodule slave_xactor_f_rd_addr
wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_set_addr_map,
CAN_FIRE_slave_m_arvalid,
CAN_FIRE_slave_m_awvalid,
CAN_FIRE_slave_m_bready,
CAN_FIRE_slave_m_rready,
CAN_FIRE_slave_m_wvalid,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_set_addr_map,
WILL_FIRE_slave_m_arvalid,
WILL_FIRE_slave_m_awvalid,
WILL_FIRE_slave_m_bready,
WILL_FIRE_slave_m_rready,
WILL_FIRE_slave_m_wvalid;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h899;
reg [31 : 0] v__h6528;
reg [31 : 0] v__h6817;
reg [31 : 0] v__h6927;
reg [31 : 0] v__h893;
reg [31 : 0] v__h6522;
reg [31 : 0] v__h6811;
reg [31 : 0] v__h6921;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] data64__h1055;
reg [31 : 0] CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3;
reg CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4,
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5;
wire [63 : 0] rdata__h1011,
slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1;
wire [1 : 0] rdr_rresp__h1044;
wire NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33,
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method slave_m_awvalid
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
// value method slave_m_awready
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method slave_m_wvalid
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
// value method slave_m_wready
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method slave_m_bvalid
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method slave_m_bid
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method slave_m_bresp
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method slave_m_bready
assign CAN_FIRE_slave_m_bready = 1'd1 ;
assign WILL_FIRE_slave_m_bready = 1'd1 ;
// action method slave_m_arvalid
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
// value method slave_m_arready
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method slave_m_rvalid
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method slave_m_rid
assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method slave_m_rdata
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method slave_m_rresp
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method slave_m_rlast
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method slave_m_rready
assign CAN_FIRE_slave_m_rready = 1'd1 ;
assign WILL_FIRE_slave_m_rready = 1'd1 ;
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
slave_xactor_f_rd_addr$EMPTY_N &&
slave_xactor_f_rd_data$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N &&
slave_xactor_f_wr_resp$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_module_ready
assign rg_module_ready$D_IN = 1'd1 ;
assign rg_module_ready$EN = EN_set_addr_map ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
{ slave_xactor_f_rd_addr$D_OUT[96:93],
rdata__h1011,
rdr_rresp__h1044,
1'd1 } ;
assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_data$DEQ =
slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ slave_wdata, slave_wstrb, slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
{ slave_xactor_f_wr_addr$D_OUT[96:93],
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 ?
2'b10 :
2'b0 } ;
assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_resp$DEQ =
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 ||
rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] ||
slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ;
assign NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 ||
rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] ||
slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ;
assign rdata__h1011 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
64'd0 :
data64__h1055 ;
assign rdr_rresp__h1044 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
2'b10 :
2'b0 ;
assign slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 =
slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ;
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2,
61'd3,
61'd7,
61'd9,
61'd10,
61'd11,
61'd25,
61'd29,
61'd39,
61'd53,
61'd56,
61'd75,
61'd91,
61'd142,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 = 32'h0;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h54040000;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h88030000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h11000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h50030000;
61'd12,
61'd14,
61'd26,
61'd28,
61'd30,
61'd54,
61'd61,
61'd109,
61'd111:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h04000000;
61'd13, 61'd15, 61'd63, 61'd99, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h02000000;
61'd16:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h16000000;
61'd17:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h62626375;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656B6970;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65642D65;
61'd20,
61'd33,
61'd35,
61'd37,
61'd42,
61'd45,
61'd48,
61'd57,
61'd69,
61'd74,
61'd76,
61'd78,
61'd84,
61'd88,
61'd95,
61'd102,
61'd105,
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h03000000;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h26000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h732C7261;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7261622D;
61'd24,
61'd27,
61'd50,
61'd55,
61'd62,
61'd64,
61'd73,
61'd93,
61'd94,
61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h01000000;
61'd31, 61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h80969800;
61'd32:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40757063;
61'd34:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h3F000000;
61'd36, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4B000000;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4F000000;
61'd40:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h06000000;
61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h63736972;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h56000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h75616D69;
61'd46:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h60000000;
61'd47:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h76732C76;
61'd49:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69000000;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70757272;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F72746E;
61'd58, 61'd79, 61'd89, 61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h1B000000;
61'd59:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70632C76;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00006374;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h38407972;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00303030;
61'd67:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h07000000;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D656D;
61'd71:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000080;
61'd72:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000010;
61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h0F000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69730063;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7375622D;
61'd85:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hA7000000;
61'd86:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E696C63;
61'd87, 61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h30303030;
61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C632C76;
61'd92:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h10000000;
61'd97:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000002;
61'd98:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000C00;
61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h74726175;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61303535;
61'd107:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h000000C0;
61'd108:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40000000;
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h08000000;
61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h09000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73736572;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h2300736C;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C65632D;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61706D6F;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D0065;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656D6974;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6572662D;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h64007963;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79745F65;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73006765;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69720073;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00617369;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65707974;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h662D6B63;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79636E65;
61'd132, 61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h72726574;
61'd133:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C6C6563;
61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h746E6F63;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70007265;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7200656C;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E690073;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73747075;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65646E65;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h68732D67;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00028067;
61'd3:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80000000;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hEDFE0DD0;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h38000000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h28000000;
61'd7, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h10000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hCC000000;
61'd9,
61'd10,
61'd13,
61'd27,
61'd37,
61'd71,
61'd72,
61'd84,
61'd85,
61'd97,
61'd98,
61'd105,
61'd107,
61'd108,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 = 32'h0;
61'd11, 61'd32, 61'd86, 61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h01000000;
61'd12,
61'd14,
61'd16,
61'd26,
61'd28,
61'd30,
61'd40,
61'd54,
61'd56,
61'd61,
61'd67,
61'd92,
61'd94,
61'd109,
61'd111,
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h03000000;
61'd15, 61'd29, 61'd58:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0F000000;
61'd17, 61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h1B000000;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h732C7261;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7261622D;
61'd20, 61'd42:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000076;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h12000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h62626375;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656B6970;
61'd24:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000065;
61'd25:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h73757063;
61'd31:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C000000;
61'd33, 61'd88, 61'd102:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000030;
61'd34, 61'd36, 61'd49, 61'd75, 61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h04000000;
61'd35:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00757063;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h05000000;
61'd39:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79616B6F;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0A000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h32337672;
61'd45:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000073;
61'd46, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0B000000;
61'd47, 61'd59, 61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63736972;
61'd48:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00003233;
61'd50:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80969800;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65746E69;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F632D74;
61'd53:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72656C6C;
61'd55:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79000000;
61'd57:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h8A000000;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692D75;
61'd62:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h9F000000;
61'd63, 61'd64, 61'd73, 61'd76, 61'd78, 61'd99, 61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h02000000;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6D656D;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30303030;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3F000000;
61'd69:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00007972;
61'd74:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00636F73;
61'd79:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h21000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F732D65;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656C706D;
61'd87:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30324074;
61'd89:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0D000000;
61'd91:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30746E69;
61'd93, 61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAE000000;
61'd95:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h07000000;
61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30306340;
61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h09000000;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3631736E;
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hC2000000;
61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h69000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h64646123;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C65632D;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h657A6973;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6300736C;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C626974;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h006C6564;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65736162;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E657571;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63697665;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72006570;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75746174;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C766373;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D756D6D;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6C6300;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75716572;
61'd132:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692300;
61'd133, 61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D747075;
61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E690073;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C6C6F72;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h646E6168;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65676E61;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72726574;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7478652D;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65720064;
61'd142:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00746669;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd0: data64__h1055 = 64'h0202859300000297;
61'd1: data64__h1055 = 64'h0182A283F1402573;
default: data64__h1055 =
{ CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 };
endcase
end
always@(slave_xactor_f_rd_addr$D_OUT)
begin
case (slave_xactor_f_rd_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0;
endcase
end
always@(slave_xactor_f_wr_addr$D_OUT)
begin
case (slave_xactor_f_wr_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_module_ready$EN)
rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_module_ready = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
begin
v__h899 = $stime;
#0;
end
v__h893 = v__h899 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
v__h893);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
begin
v__h6528 = $stime;
#0;
end
v__h6522 = v__h6528 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized or misaligned addr",
v__h6522);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
begin
v__h6817 = $stime;
#0;
end
v__h6811 = v__h6817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h6811,
set_addr_map_addr_base);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
begin
v__h6927 = $stime;
#0;
end
v__h6921 = v__h6927 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h6921,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkBoot_ROM
|
/********************************************************************
* TEST BENCH FOR PROTECTION CELLS *
********************************************************************
* Laboratory : Robotics and Embedded System Technology
* Engineer : Hanjara Cahya Adhyatma
* Create Date : 19/04/2017
* Project Name : FINAL PROJECT
* Target Devices: TEST BENCH SIM PROTECTION AND FPGA
* Tool versions : VERILOG 2001 RUN ON ICARUS 10
* Description : 日本へかえりますために。。。
* Dependencies : いない
* Revision : 今から
* Additional Comments: いない
********************************************************************
* INCLUDE MODULES *
*******************************************************************/
`include "../module/protection.v"
/********************************************************************
* IO DEFINITIONS *
*******************************************************************/
module protection_sim;
reg RST, CLK, ENA;
reg [7:0]RGA;
reg [7:0]RGB;
wire [7:0]RGZ;
reg [1:0]KEY;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, prot);
$monitor($time, " REG A = %b REG Z = %b", RGA, RGZ);
end
/********************************************************************
* CLOCKING *
*******************************************************************/
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
/********************************************************************
* RESET *
*******************************************************************/
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
/********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b101;
#10 RGA = 3'b110;
#10 RGA = 3'b010;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b001;
#10 RGA = 3'b010;
#10 RGA = 3'b101;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b111;
#10 RGA = 3'b011;
#10 RGA = 3'b000;
$finish;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
protection prot( RST, CLK, ENA, RGA, RGB, RGZ, KEY);
endmodule
|
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_wdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 16,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 5,
CFG_DATA_ID_WIDTH = 4,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_TBP_NUM = 8,
CFG_BUFFER_ADDR_WIDTH = 10,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_WDATA_REG = 0,
CFG_PARTIAL_BE_PER_WORD_ENABLE = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_ECC_BE_ALLLOW_RMW = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_enable_ecc_code_overwrites,
cfg_interface_width,
// command generator & TBP command load interface / cmd update interface
wdatap_free_id_valid,
wdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
tbp_load_index,
proc_size,
// input interface data channel / buffer write interface
wr_data_mem_full,
write_data_en,
write_data,
byte_en,
// notify TBP interface
data_complete,
data_rmw_complete,
data_rmw_fetch,
data_partial_be,
// AFI interface / buffer read interface
doing_write,
dataid,
dataid_vector,
rdwr_data_valid,
rmw_correct,
rmw_partial,
doing_write_first,
dataid_first,
dataid_vector_first,
rdwr_data_valid_first,
rmw_correct_first,
rmw_partial_first,
doing_write_first_vector,
rdwr_data_valid_first_vector,
doing_write_last,
dataid_last,
dataid_vector_last,
rdwr_data_valid_last,
rmw_correct_last,
rmw_partial_last,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_dm,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
// RMW fifo interface, from rdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_BURSTCOUNT_TRACKING_WIDTH = CFG_BUFFER_ADDR_WIDTH+1;
localparam CFG_RMWFIFO_ECC_DBE_WIDTH = CFG_ECC_MULTIPLES;
localparam CFG_RMWFIFO_ECC_CODE_WIDTH = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_ADDR_WIDTH = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
localparam CFG_LOCAL_BE_WIDTH = CFG_LOCAL_DATA_WIDTH / 8;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DM_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
// -----------------------------
// port declaration
// -----------------------------
// clock and reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
output wdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
// command generator & TBP command load interface / cmd update interface
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_write;
input [CFG_TBP_NUM-1:0] tbp_load_index;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
output wr_data_mem_full;
input write_data_en;
input [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
input [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
output [CFG_TBP_NUM-1:0] data_complete;
output data_rmw_complete; // broadcast to TBP's
input data_rmw_fetch;
output data_partial_be;
// AFI interface / buffer read interface
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
input doing_write_first;
input [CFG_DATA_ID_WIDTH-1:0] dataid_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_first;
input rdwr_data_valid_first;
input rmw_correct_first;
input rmw_partial_first;
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write_first_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid_first_vector;
input doing_write_last;
input [CFG_DATA_ID_WIDTH-1:0] dataid_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_last;
input rdwr_data_valid_last;
input rmw_correct_last;
input rmw_partial_last;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
output wdatap_rmw_partial;
output wdatap_rmw_correct;
output [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
output [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
input rmwfifo_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
input [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
wire [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
wire wdatap_free_id_valid;
wire wdatap_int_free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_free_id_dataid_vector;
// command generator & TBP command load interface / cmd update interface
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire [CFG_TBP_NUM-1:0] tbp_load_index;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
wire wr_data_mem_full;
wire write_data_en;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
// AFI interface / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
reg [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// signal declaration
// -----------------------------
// configuration
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
// command generator & TBP command load interface / cmd update interface
wire wdatap_cmdload_ready;
wire wdatap_cmdload_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_cmdload_dataid;
wire [CFG_TBP_NUM-1:0] wdatap_cmdload_tbp_index;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_cmdload_burstcount;
// input interface data channel / buffer write interface
wire wdatap_datawrite_ready;
wire wdatap_datawrite_valid;
wire wdatap_datawrite_accepted;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_datawrite_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] wdatap_datawrite_be;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_datawrite_dm;
reg [CFG_LOCAL_DM_WIDTH-1:0] int_datawrite_dm;
wire wdatap_datawrite_partial_be;
wire wdatap_datawrite_allzeros_be;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_datawrite_address;
reg [CFG_ECC_MULTIPLES-1:0] int_datawrite_partial_be;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] wdatap_tbp_data_ready;
wire wdatap_tbp_data_partial_be;
// AFI interface data channel / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_r;
wire wdatap_dataread_valid_first;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_first;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid_first_vector;
wire wdatap_dataread_valid_last;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_last;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_datavalid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_correct_data;
reg wdatap_dataread_rmw_partial;
reg wdatap_dataread_rmw_correct;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_dm;
wire [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_dataread_address;
wire wdatap_dataread_done;
wire wdatap_dataread_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_buffer_data;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_buffer_dm;
wire wdatap_free_id_get_ready;
wire wdatap_allocated_put_ready;
wire wdatap_allocated_put_valid;
wire wdatap_update_data_dataid_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_update_data_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_update_data_dataid_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_next_burstcount;
wire wdatap_notify_data_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_notify_data_burstcount_consumed;
// buffer read/write signals
wire wdatap_buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffwrite_address;
wire wdatap_buffread_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffread_address;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_input;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_output;
wire rmwfifo_output_read;
wire rmwfifo_output_valid;
reg rmwfifo_output_valid_r;
wire rmwfifo_output_valid_pulse;
reg rmwfifo_output_valid_handshake;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data_r;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_output_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmw_merged_data;
reg rmw_correct_r1;
reg rmw_partial_r1;
reg rmw_correct_r2;
reg rmw_partial_r2;
wire rmwfifo_ready;
// debug signals, for assertions
wire err_rmwfifo_overflow;
// -----------------------------
// module definition
// -----------------------------
// renaming port names to more meaningfull internal names
assign wdatap_cmdload_valid = ~proc_busy & proc_load & proc_write & proc_load_dataid;
assign wdatap_cmdload_tbp_index = tbp_load_index;
assign wdatap_cmdload_burstcount = proc_size;
assign wdatap_cmdload_dataid = wdatap_free_id_dataid;
assign wr_data_mem_full = ~wdatap_datawrite_ready;
assign wdatap_datawrite_valid = write_data_en;
assign wdatap_datawrite_data = write_data;
assign wdatap_datawrite_be = byte_en; // we need to replicate
assign data_complete = wdatap_tbp_data_ready;
assign data_rmw_complete = rmwfifo_output_valid_pulse | rmwfifo_output_valid_handshake; // broadcast to all TBP's
assign data_partial_be = wdatap_tbp_data_partial_be;
assign wdatap_dataread_valid = doing_write & rdwr_data_valid & ~rmw_correct;
assign wdatap_dataread_dataid = dataid;
assign wdatap_dataread_dataid_vector = dataid_vector;
assign wdatap_dataread_valid_first = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
assign wdatap_dataread_dataid_first = dataid_first;
assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
assign wdatap_dataread_valid_first_vector = rdwr_data_valid_first_vector;
assign wdatap_dataread_valid_last = doing_write_last & rdwr_data_valid_last & ~rmw_correct_last ;
assign wdatap_dataread_dataid_last = dataid_last;
assign wdatap_dataread_dataid_vector_last = dataid_vector_last;
assign wdatap_data = wdatap_dataread_data;
assign wdatap_rmw_partial_data = wdatap_dataread_rmw_partial_data;
assign wdatap_rmw_correct_data = wdatap_dataread_rmw_correct_data;
assign wdatap_rmw_partial = wdatap_dataread_rmw_partial;
assign wdatap_rmw_correct = wdatap_dataread_rmw_correct;
assign wdatap_dm = wdatap_dataread_dm;
// internal signals
// flow control between free list & allocated list
assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH; // SPR:362973
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
//reset state ...
wdatap_dataread_dataid_r <= 0;
end
else
begin
//active state ...
wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
end
end
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
wdatap_list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_free_id_get_ready),
.list_get_entry_valid (wdatap_int_free_id_valid),
.list_get_entry_id (wdatap_free_id_dataid),
.list_get_entry_id_vector (wdatap_free_id_dataid_vector),
// wdatap_dataread_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_dataread_ready),
.list_put_entry_valid (wdatap_dataread_done),
.list_put_entry_id (wdatap_dataread_dataid_r)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
wdatap_list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_notify_data_valid),
.list_get_entry_valid (wdatap_update_data_dataid_valid),
.list_get_entry_id (wdatap_update_data_dataid),
.list_get_entry_id_vector (wdatap_update_data_dataid_vector),
// wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_allocated_put_ready),
.list_put_entry_valid (wdatap_allocated_put_valid),
.list_put_entry_id (wdatap_free_id_dataid)
);
alt_mem_ddrx_burst_tracking
# (
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH)
)
wdatap_burst_tracking_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// data burst interface
.burst_ready (wdatap_datawrite_ready),
.burst_valid (wdatap_datawrite_valid),
// burstcount counter sent to data_id_manager
.burst_pending_burstcount (wdatap_update_data_burstcount),
.burst_next_pending_burstcount (wdatap_update_data_next_burstcount),
// burstcount consumed by data_id_manager
.burst_consumed_valid (wdatap_notify_data_valid),
.burst_counsumed_burstcount (wdatap_notify_data_burstcount_consumed)
);
alt_mem_ddrx_dataid_manager
# (
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH),
.CFG_TBP_NUM (CFG_TBP_NUM),
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_ECC_BE_ALLLOW_RMW (CFG_ECC_BE_ALLLOW_RMW)
)
wdatap_dataid_manager_inst
(
// clock & reset
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// configuration signals
.cfg_burst_length (cfg_burst_length),
.cfg_enable_ecc (cfg_enable_ecc),
.cfg_enable_auto_corr (cfg_enable_auto_corr),
.cfg_enable_no_dm (cfg_enable_no_dm),
// update cmd interface
.update_cmd_if_ready (wdatap_cmdload_ready),
.update_cmd_if_valid (wdatap_cmdload_valid),
.update_cmd_if_data_id (wdatap_cmdload_dataid),
.update_cmd_if_burstcount (wdatap_cmdload_burstcount),
.update_cmd_if_tbp_id (wdatap_cmdload_tbp_index),
// update data interface
.update_data_if_valid (wdatap_update_data_dataid_valid),
.update_data_if_data_id (wdatap_update_data_dataid),
.update_data_if_data_id_vector (wdatap_update_data_dataid_vector),
.update_data_if_burstcount (wdatap_update_data_burstcount),
.update_data_if_next_burstcount (wdatap_update_data_next_burstcount),
// notify data interface
.notify_data_if_valid (wdatap_notify_data_valid),
.notify_data_if_burstcount (wdatap_notify_data_burstcount_consumed),
// notify tbp interface
.notify_tbp_data_ready (wdatap_tbp_data_ready),
.notify_tbp_data_partial_be (wdatap_tbp_data_partial_be),
// buffer write address generate interface
.write_data_if_ready (wdatap_datawrite_ready),
.write_data_if_valid (wdatap_datawrite_valid),
.write_data_if_accepted (wdatap_datawrite_accepted),
.write_data_if_address (wdatap_datawrite_address),
.write_data_if_partial_be (wdatap_datawrite_partial_be),
.write_data_if_allzeros_be (wdatap_datawrite_allzeros_be),
// read data interface
.read_data_if_valid (wdatap_dataread_valid),
.read_data_if_data_id (wdatap_dataread_dataid),
.read_data_if_data_id_vector (wdatap_dataread_dataid_vector),
.read_data_if_valid_first (wdatap_dataread_valid_first),
.read_data_if_data_id_first (wdatap_dataread_dataid_first),
.read_data_if_data_id_vector_first (wdatap_dataread_dataid_vector_first),
.read_data_if_valid_first_vector (wdatap_dataread_valid_first_vector),
.read_data_if_valid_last (wdatap_dataread_valid_last),
.read_data_if_data_id_last (wdatap_dataread_dataid_last),
.read_data_if_data_id_vector_last (wdatap_dataread_dataid_vector_last),
.read_data_if_address (wdatap_dataread_address),
.read_data_if_datavalid (wdatap_dataread_datavalid),
.read_data_if_done (wdatap_dataread_done) // use with wdatap_dataread_dataid_r
);
genvar wdatap_m;
genvar wdatap_n;
generate
for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
begin : wdata_buffer_per_dwidth_ratio
for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
begin : wdata_buffer_per_dqs_group
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DATA_WIDTH_PER_DQS_GROUP),
.REGISTER_OUTPUT (CFG_WDATA_REG)
)
wdatap_buffer_data_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (wdatap_datawrite_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
);
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DM_WIDTH_PER_DQS_GROUP),
.REGISTER_OUTPUT (CFG_WDATA_REG)
)
wdatap_buffer_be_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (int_datawrite_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
);
end
end
endgenerate
//
// byteenables analysis & generation
//
// - generate partial byteenable signal, per DQ word or per local word
// - set unused interface width byteenables to either 0 or 1
//
genvar wdatap_j, wdatap_k;
generate
if (CFG_ECC_BE_ALLLOW_RMW) begin
reg [CFG_ECC_MULTIPLES-1:0] be_all_ones;
reg [CFG_ECC_MULTIPLES-1:0] be_all_zeros;
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
assign wdatap_datawrite_allzeros_be = (!cfg_enable_no_dm & &be_all_zeros) ? 1'b1 : 1'b0;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
always @ (*)
begin
be_all_ones[wdatap_j] = &int_datawrite_dm_unused1[wdatap_j];
be_all_zeros[wdatap_j] = ~(|int_datawrite_dm_unused0[wdatap_j]);
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_be[wdatap_j] = ~be_all_ones[wdatap_j];
end
else
begin
int_datawrite_partial_be[wdatap_j] = ~(be_all_ones[wdatap_j] | be_all_zeros[wdatap_j]);
end
if (cfg_enable_ecc)
begin
if (be_all_zeros[wdatap_j])
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
end
else begin
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
assign wdatap_datawrite_allzeros_be = 0;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
wire be_all_ones = &int_datawrite_dm_unused1[wdatap_j];
wire be_all_zeros = ~(|int_datawrite_dm_unused0[wdatap_j]);
always @ (*)
begin
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_be[wdatap_j] = ~be_all_ones;
end
else
begin
int_datawrite_partial_be[wdatap_j] = ~( be_all_ones | be_all_zeros );
end
if (cfg_enable_ecc)
begin
if (be_all_zeros)
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
end
endgenerate
//
// rmw data fifo
//
// assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
// New data_rmw_complete logic, TBP/cmd_gen will have to assert data_rmw_fetch before data_rmw_complete de-asserts
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmwfifo_output_valid_handshake <= 1'b0;
end
else
begin
if (data_rmw_fetch)
begin
rmwfifo_output_valid_handshake <= 1'b0;
end
else if (rmwfifo_output_valid_pulse)
begin
rmwfifo_output_valid_handshake <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rmwfifo_output_valid_r <= 1'b0;
rmw_correct_r1 <= 1'b0;
rmw_partial_r1 <= 1'b0;
rmw_correct_r2 <= 1'b0;
rmw_partial_r2 <= 1'b0;
end
else
begin
rmwfifo_output_valid_r <= rmwfifo_output_valid;
rmw_correct_r1 <= rmw_correct;
rmw_partial_r1 <= rmw_partial;
rmw_correct_r2 <= rmw_correct_r1;
rmw_partial_r2 <= rmw_partial_r1;
end
end
// RMW FIFO output register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmwfifo_output_data_r <= 0;
end
else
begin
rmwfifo_output_data_r <= rmwfifo_output_data;
end
end
assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
assign rmwfifo_output_read = rmw_correct_r1 | (&wdatap_dataread_datavalid & rmw_partial_r1); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
)
rmw_data_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rmwfifo_output_read),
.get_valid (rmwfifo_output_valid),
.get_data (rmwfifo_output),
.put_ready (rmwfifo_ready),
.put_valid (rmwfifo_data_valid),
.put_data (rmwfifo_input)
);
//
// rmw data merge block
//
genvar wdatap_i;
generate
for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1)
begin : gen_rmw_data_merge
always @ (*)
begin
if (wdatap_dataread_buffer_dm[wdatap_i])
begin
// data from wdatap buffer
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
// data from rmwfifo
if (CFG_WDATA_REG)
begin
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data_r [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
end
end
end
endgenerate
//
// wdata output mux
//
// drives wdatap_data & wdatap_be from either of
// if cfg_enabled etc ?
// - wdatap buffer (~rmw_correct & ~rmw_partial)
// - rmwfifo (rmw_correct)
// - merged wdatap buffer & rmwfifo (rmw_partial)
//
generate
if (CFG_WDATA_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data_r;
wdatap_dataread_rmw_partial = rmw_partial_r2;
wdatap_dataread_rmw_correct = rmw_correct_r2;
if (rmw_correct_r2 | rmw_partial_r2)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_ecc_code <= 0;
wdatap_ecc_code_overwrite <= 0;
end
else
begin
wdatap_ecc_code <= rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r1)
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r1)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
wdatap_dataread_rmw_partial = rmw_partial_r1;
wdatap_dataread_rmw_correct = rmw_correct_r1;
if (rmw_correct_r1 | rmw_partial_r1)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (*)
begin
wdatap_ecc_code = rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r1)
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r1)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
`timescale 1ns / 1ps
module Gato_FSM(
clk,
reset,
state,
p1_mm,
p2_mm,
//entradas que son salidas de la otra maquina de estados
p1_tie,
p1_loss,
p1_win,
p2_tie,
p2_loss,
p2_win,
//salidas que van hacia a otra maquina de estados
verifica_status,
turno_p1,
turno_p2,
win_game,
loss_game,
tie_game
);
input clk, reset;
input p1_mm, p2_mm;
input p1_tie, p1_loss, p1_win, p2_tie, p2_loss, p2_win;
output reg turno_p1, turno_p2;
output reg verifica_status;
output reg win_game, loss_game, tie_game;
output [3:0] state;
reg [3:0] state, nextState;
//Estados de las FSM
parameter P1_Move = 0;
parameter P1_Status = 1;
parameter P2_Move = 2;
parameter P2_Status = 3;
parameter Win = 4;
parameter Tie = 5;
parameter Loss = 6;
initial turno_p1 <= 1'b1;
initial turno_p2 <= 1'b0;
//Asignación sincrona del singuiente estado
always @(posedge clk or posedge reset)
begin
if (reset)
state <= P1_Move;
else
state <= nextState;
end
//Asignacion asincrona de los estados
always @(state or p1_mm or p2_mm or p1_win or p1_loss or p1_tie or p2_win or p2_loss or p2_tie)
begin
nextState = 3'bxxx;
case(state)
P1_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p1_mm == 1'b0)
nextState = P1_Move;
else if (p1_mm == 1'b1)
nextState = P1_Status;
end
P1_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p1_tie == 1'b1 & p1_loss == 1'b0 & p1_win == 1'b0)
nextState = Tie;
else if (p1_win == 1'b1 & p1_tie == 1'b0 & p1_loss == 1'b0)
nextState = Loss;
else if (p2_mm == 1'b0)
nextState = P2_Move;
end
P2_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p2_mm == 1'b0)
nextState = P2_Move;
else if (p2_mm == 1'b1)
nextState = P2_Status;
end
P2_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p2_tie == 1'b1 & p2_loss == 1'b0 & p2_win == 1'b0)
nextState = Tie;
else if (p2_win == 1'b1 & p2_tie == 1'b0 & p2_loss == 1'b0)
nextState = Win;
else if (p1_mm == 1'b0)
nextState = P1_Move;
end
Win:
begin
win_game <= 1'b1;
nextState = Win;
end
Tie:
begin
tie_game <= 1'b1;
nextState = Tie;
end
Loss:
begin
loss_game <= 1'b1;
nextState = Loss;
end
default: nextState = P1_Move;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_ram4x26.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This is the 4x50 dual port RAM for the header information of the
outstanding Completion packets in the error manager.
The RAM output is registered.
***********************************************************************/
`define FFD 1
module cmm_errman_ram4x26 (
rddata, // Output
wrdata, // Inputs
wr_ptr,
rd_ptr,
we,
rst,
clk
);
output [49:0] rddata;
input [49:0] wrdata;
input [1:0] wr_ptr;
input [1:0] rd_ptr;
input we;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
//******************************************************************//
// Construct the RAM. //
//******************************************************************//
reg [49:0] lutram_data [0:3];
always @(posedge clk) begin
if (we)
lutram_data[wr_ptr] <= #`FFD wrdata;
end
//******************************************************************//
// Register the outputs. //
//******************************************************************//
reg [49:0] reg_rdata;
always @(posedge clk or posedge rst)
begin
if (rst) reg_rdata <= #`FFD 50'h0000_0000_0000;
else reg_rdata <= #`FFD lutram_data[rd_ptr];
end
assign rddata = reg_rdata;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
module Mac(input clk, input use_accum, input [17:0] A, input [17:0] B, input [17:0] D, output [47:0] P);
wire [7:0] OPMODE = use_accum ? 8'b00011001 : 8'b00010001;
DSP48A1 #(
.A0REG(0), // First stage A input pipeline register (0/1)
.A1REG(0), // Second stage A input pipeline register (0/1)
.B0REG(0), // First stage B input pipeline register (0/1)
.B1REG(0), // Second stage B input pipeline register (0/1)
.CARRYINREG(0), // CARRYIN input pipeline register (0/1)
.CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5"
.CARRYOUTREG(0), // CARRYOUT output pipeline register (0/1)
.CREG(0), // C input pipeline register (0/1)
.DREG(0), // D pre-adder input pipeline register (0/1)
.MREG(0), // M pipeline register (0/1)
.OPMODEREG(0), // Enable=1/disable=0 OPMODE input pipeline registers
.PREG(1), // P output pipeline register (0/1)
.RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC"
)
DSP48A1_inst (
// Cascade Ports: 18-bit (each) output: Ports to cascade from one DSP48 to another
// .BCOUT(BCOUT), // 18-bit output: B port cascade output
// .PCOUT(PCOUT), // 48-bit output: P cascade output (if used, connect to PCIN of another DSP48A1)
// Data Ports: 1-bit (each) output: Data input and output ports
// .CARRYOUT(CARRYOUT), // 1-bit output: carry output (if used, connect to CARRYIN pin of another
// // DSP48A1)
// .CARRYOUTF(CARRYOUTF), // 1-bit output: fabric carry output
// .M(M), // 36-bit output: fabric multiplier data output
.P(P), // 48-bit output: data output
// Cascade Ports: 48-bit (each) input: Ports to cascade from one DSP48 to another
// .PCIN(0), // 48-bit input: P cascade input (if used, connect to PCOUT of another DSP48A1)
// Control Input Ports: 1-bit (each) input: Clocking and operation mode
.CLK(clk), // 1-bit input: clock input
.OPMODE(OPMODE), // 8-bit input: operation mode input
// Data Ports: 18-bit (each) input: Data input and output ports
.A(A), // 18-bit input: A data input
.B(B), // 18-bit input: B data input (connected to fabric or BCOUT of adjacent DSP48A1)
// .C(C), // 48-bit input: C data input
// .CARRYIN(CARRYIN), // 1-bit input: carry input signal (if used, connect to CARRYOUT pin of another
// // DSP48A1)
.D(D), // 18-bit input: B pre-adder data input
// Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports
.CEA(1'b0), // 1-bit input: active high clock enable input for A registers
.CEB(1'b0), // 1-bit input: active high clock enable input for B registers
.CEC(1'b0), // 1-bit input: active high clock enable input for C registers
.CECARRYIN(1'b0), // 1-bit input: active high clock enable input for CARRYIN registers
.CED(1'b0), // 1-bit input: active high clock enable input for D registers
.CEM(1'b0), // 1-bit input: active high clock enable input for multiplier registers
.CEOPMODE(1'b0), // 1-bit input: active high clock enable input for OPMODE registers
.CEP(1'b1), // 1-bit input: active high clock enable input for P registers
.RSTA(1'b0), // 1-bit input: reset input for A pipeline registers
.RSTB(1'b0), // 1-bit input: reset input for B pipeline registers
.RSTC(1'b0), // 1-bit input: reset input for C pipeline registers
.RSTCARRYIN(1'b0), // 1-bit input: reset input for CARRYIN pipeline registers
.RSTD(1'b0), // 1-bit input: reset input for D pipeline registers
.RSTM(1'b0), // 1-bit input: reset input for M pipeline registers
.RSTOPMODE(1'b0), // 1-bit input: reset input for OPMODE pipeline registers
.RSTP(1'b0) // 1-bit input: reset input for P pipeline registers
);
endmodule
module Add24(input [4:0] a, input [4:0] b, output [4:0] r);
wire [5:0] t = a + b;
wire [1:0] u = t[5:3] == 0 ? 0 :
t[5:3] == 1 ? 1 :
t[5:3] == 2 ? 2 :
t[5:3] == 3 ? 0 :
t[5:3] == 4 ? 1 :
t[5:3] == 5 ? 2 :
t[5:3] == 6 ? 0 : 1;
assign r = {u, t[2:0]};
endmodule
module FirFilter(input clk, input [15:0] sample_in, output [15:0] sample_out, output sample_now);
reg [15:0] X[0:1023]; // Samples are only 16 bits.
reg [17:0] B[0:511]; // Coefficients are 18 bits.
integer i;
// IIR Coefficients
initial begin
for(i = 0;i < 1024; i = i + 1) X[i] = 0;
B[0]=0; B[1]=-13; B[2]=-25; B[3]=-38;
B[4]=-50; B[5]=-63; B[6]=-75; B[7]=-87;
B[8]=-100; B[9]=-112; B[10]=-124; B[11]=-136;
B[12]=-148; B[13]=-160; B[14]=-172; B[15]=-184;
B[16]=-195; B[17]=-206; B[18]=-217; B[19]=-227;
B[20]=-238; B[21]=-248; B[22]=-257; B[23]=-266;
B[24]=-275; B[25]=-284; B[26]=-292; B[27]=-299;
B[28]=-306; B[29]=-312; B[30]=-318; B[31]=-323;
B[32]=-328; B[33]=-332; B[34]=-335; B[35]=-337;
B[36]=-339; B[37]=-340; B[38]=-340; B[39]=-340;
B[40]=-338; B[41]=-335; B[42]=-332; B[43]=-328;
B[44]=-322; B[45]=-316; B[46]=-309; B[47]=-300;
B[48]=-291; B[49]=-281; B[50]=-269; B[51]=-256;
B[52]=-243; B[53]=-228; B[54]=-212; B[55]=-195;
B[56]=-178; B[57]=-159; B[58]=-138; B[59]=-117;
B[60]=-95; B[61]=-72; B[62]=-48; B[63]=-23;
B[64]=3; B[65]=29; B[66]=57; B[67]=85;
B[68]=114; B[69]=144; B[70]=174; B[71]=205;
B[72]=236; B[73]=268; B[74]=300; B[75]=333;
B[76]=365; B[77]=398; B[78]=430; B[79]=463;
B[80]=495; B[81]=527; B[82]=558; B[83]=589;
B[84]=620; B[85]=650; B[86]=679; B[87]=707;
B[88]=734; B[89]=760; B[90]=785; B[91]=808;
B[92]=830; B[93]=850; B[94]=869; B[95]=886;
B[96]=901; B[97]=914; B[98]=925; B[99]=933;
B[100]=940; B[101]=944; B[102]=945; B[103]=944;
B[104]=941; B[105]=935; B[106]=925; B[107]=914;
B[108]=899; B[109]=881; B[110]=861; B[111]=837;
B[112]=810; B[113]=781; B[114]=748; B[115]=712;
B[116]=673; B[117]=631; B[118]=587; B[119]=539;
B[120]=488; B[121]=435; B[122]=378; B[123]=319;
B[124]=258; B[125]=193; B[126]=127; B[127]=58;
B[128]=-13; B[129]=-86; B[130]=-161; B[131]=-238;
B[132]=-316; B[133]=-396; B[134]=-477; B[135]=-559;
B[136]=-642; B[137]=-726; B[138]=-810; B[139]=-894;
B[140]=-978; B[141]=-1062; B[142]=-1145; B[143]=-1228;
B[144]=-1309; B[145]=-1390; B[146]=-1469; B[147]=-1546;
B[148]=-1621; B[149]=-1694; B[150]=-1764; B[151]=-1832;
B[152]=-1896; B[153]=-1957; B[154]=-2015; B[155]=-2069;
B[156]=-2119; B[157]=-2164; B[158]=-2205; B[159]=-2241;
B[160]=-2272; B[161]=-2298; B[162]=-2319; B[163]=-2333;
B[164]=-2343; B[165]=-2346; B[166]=-2343; B[167]=-2333;
B[168]=-2318; B[169]=-2295; B[170]=-2267; B[171]=-2231;
B[172]=-2189; B[173]=-2139; B[174]=-2083; B[175]=-2020;
B[176]=-1950; B[177]=-1873; B[178]=-1789; B[179]=-1698;
B[180]=-1600; B[181]=-1496; B[182]=-1385; B[183]=-1268;
B[184]=-1145; B[185]=-1015; B[186]=-880; B[187]=-739;
B[188]=-592; B[189]=-440; B[190]=-283; B[191]=-122;
B[192]=44; B[193]=213; B[194]=387; B[195]=563;
B[196]=743; B[197]=924; B[198]=1108; B[199]=1294;
B[200]=1480; B[201]=1668; B[202]=1855; B[203]=2042;
B[204]=2229; B[205]=2414; B[206]=2597; B[207]=2778;
B[208]=2956; B[209]=3131; B[210]=3302; B[211]=3468;
B[212]=3630; B[213]=3786; B[214]=3935; B[215]=4078;
B[216]=4214; B[217]=4343; B[218]=4463; B[219]=4574;
B[220]=4676; B[221]=4769; B[222]=4851; B[223]=4923;
B[224]=4984; B[225]=5033; B[226]=5070; B[227]=5096;
B[228]=5108; B[229]=5108; B[230]=5095; B[231]=5068;
B[232]=5027; B[233]=4972; B[234]=4904; B[235]=4821;
B[236]=4723; B[237]=4611; B[238]=4485; B[239]=4344;
B[240]=4188; B[241]=4018; B[242]=3833; B[243]=3634;
B[244]=3421; B[245]=3194; B[246]=2954; B[247]=2700;
B[248]=2433; B[249]=2153; B[250]=1861; B[251]=1557;
B[252]=1242; B[253]=915; B[254]=579; B[255]=233;
B[256]=-122; B[257]=-485; B[258]=-857; B[259]=-1235;
B[260]=-1619; B[261]=-2008; B[262]=-2402; B[263]=-2800;
B[264]=-3200; B[265]=-3602; B[266]=-4004; B[267]=-4407;
B[268]=-4808; B[269]=-5208; B[270]=-5603; B[271]=-5995;
B[272]=-6381; B[273]=-6761; B[274]=-7133; B[275]=-7496;
B[276]=-7850; B[277]=-8193; B[278]=-8523; B[279]=-8840;
B[280]=-9144; B[281]=-9431; B[282]=-9702; B[283]=-9956;
B[284]=-10191; B[285]=-10406; B[286]=-10600; B[287]=-10773;
B[288]=-10922; B[289]=-11048; B[290]=-11149; B[291]=-11224;
B[292]=-11273; B[293]=-11294; B[294]=-11287; B[295]=-11251;
B[296]=-11185; B[297]=-11088; B[298]=-10960; B[299]=-10801;
B[300]=-10609; B[301]=-10385; B[302]=-10127; B[303]=-9836;
B[304]=-9510; B[305]=-9150; B[306]=-8756; B[307]=-8327;
B[308]=-7863; B[309]=-7365; B[310]=-6831; B[311]=-6263;
B[312]=-5660; B[313]=-5023; B[314]=-4352; B[315]=-3647;
B[316]=-2909; B[317]=-2137; B[318]=-1334; B[319]=-498;
B[320]=368; B[321]=1265; B[322]=2191; B[323]=3146;
B[324]=4129; B[325]=5139; B[326]=6174; B[327]=7235;
B[328]=8318; B[329]=9424; B[330]=10552; B[331]=11699;
B[332]=12864; B[333]=14047; B[334]=15245; B[335]=16457;
B[336]=17682; B[337]=18918; B[338]=20163; B[339]=21416;
B[340]=22676; B[341]=23939; B[342]=25206; B[343]=26474;
B[344]=27741; B[345]=29005; B[346]=30265; B[347]=31520;
B[348]=32766; B[349]=34004; B[350]=35229; B[351]=36442;
B[352]=37640; B[353]=38821; B[354]=39984; B[355]=41127;
B[356]=42248; B[357]=43345; B[358]=44418; B[359]=45464;
B[360]=46482; B[361]=47470; B[362]=48426; B[363]=49350;
B[364]=50239; B[365]=51094; B[366]=51911; B[367]=52690;
B[368]=53430; B[369]=54129; B[370]=54787; B[371]=55402;
B[372]=55974; B[373]=56501; B[374]=56983; B[375]=57419;
B[376]=57808; B[377]=58150; B[378]=58444; B[379]=58690;
B[380]=58887; B[381]=59035; B[382]=59134; B[383]=59183;
end
reg [4:0] s = 0;
reg [4:0] xo = 0;
reg [3:0] t = 0;
wire [47:0] P; // Output from MAC unit
// wire [4:0] outp = (xo + t) % 24, outn = (xo + 23 - t) % 24;
wire [4:0] outp, outn;
Add24 add24(xo, {1'b0, t}, outp);
Add24 sub24(xo, 5'd23 - {1'b0, t}, outn);
// Various addresses
wire [8:0] a1 = {t, s};
wire [9:0] a2 = {outp, s}, a3 = {outn, ~s};
// Temp storage from blockram.
reg [17:0] next_B = 0;
reg [15:0] next_X0 = 0, next_X1 = 0;
// Output sample is delayed two clocks. One is for fetching
// from blockram, and one is in multiplier.
reg delay1 = 0, delay2 = 0;
assign sample_now = !delay2;
assign sample_out = P[37:22];
// Clock 0 => Read from RAM into temp registers
// Clock 1 => Multiply and accumulate into P reg.
// Clock 2 => Output is available
Mac mac(.clk(clk), .use_accum(delay2),
.A(next_B),
.B({next_X0[15], next_X0[15], next_X0}),
.D({next_X1[15], next_X1[15], next_X1}),
.P(P));
wire [5:0] new_s = s + (t == 4'd11);
wire [4:0] new_xo = xo - 5'd1;
always @(posedge clk) begin
//$write("xo:%d s:%d t:%d a1:%d a2:%d a3:%d (%d %d) P:%d(%d)\n", xo, s, t, a1, a2, a3, outp, outn, $signed(P), delay2);
t <= (t == 4'd11) ? 0 : t + 4'd1;
s <= new_s[4:0];
{next_B, next_X0, next_X1} <= {B[a1], X[a2], X[a3]};
if (t == 0)
X[a3] <= sample_in;
if (new_s[5])
xo <= {new_xo[4:3] == 2'b11 ? 2'b10 : new_xo[4:3], new_xo[2:0]};
delay2 <= delay1;
delay1 <= !new_s[5];
end
endmodule // FirFilter
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp_block
(
preIntegrator,
preSat,
saturated,
Clamp
);
input signed [35:0] preIntegrator; // sfix36_En29
input signed [35:0] preSat; // sfix36_En23
input saturated;
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S17>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S17>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S17>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp_block
|
Subsets and Splits