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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_1_V
`define SKY130_FD_SC_HS__NOR4BB_1_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_1 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_1 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_jsp_module.v ////
//// ////
//// ////
//// This file is part of the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn ([email protected]) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "adbg_defines.v"
// Module interface
module adbg_jsp_module (
// JTAG signals
tck_i,
module_tdo_o,
tdi_i,
// TAP states
capture_dr_i,
shift_dr_i,
update_dr_i,
data_register_i, // the data register is at top level, shared between all modules
module_select_i,
top_inhibit_o,
rst_i,
// WISHBONE common signals
wb_clk_i, wb_rst_i,
// WISHBONE slave interface
wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o
);
// JTAG signals
input tck_i;
output module_tdo_o;
input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
// TAP states
input capture_dr_i;
input shift_dr_i;
input update_dr_i;
input [52:0] data_register_i;
input module_select_i;
output top_inhibit_o;
input rst_i;
// WISHBONE slave interface
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
input wb_cyc_i;
input wb_stb_i;
input [3:0] wb_sel_i;
input wb_we_i;
output wb_ack_o;
input wb_cab_i;
output wb_err_o;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output int_o;
// Declare inputs / outputs as wires / registers
wire module_tdo_o;
wire top_inhibit_o;
// NOTE: For the rest of this file, "input" and the "in" direction refer to bytes being transferred
// from the PC, through the JTAG, and into the BIU FIFO. The "output" direction refers to data being
// transferred from the BIU FIFO, through the JTAG to the PC.
// The read and write bit counts are separated to allow for JTAG chains with multiple devices.
// The read bit count starts right away (after a single throwaway bit), but the write count
// waits to receive a '1' start bit.
// Registers to hold state etc.
reg [3:0] read_bit_count; // How many bits have been shifted out
reg [3:0] write_bit_count; // How many bits have been shifted in
reg [3:0] input_word_count; // space (bytes) remaining in input FIFO (from JTAG)
reg [3:0] output_word_count; // bytes remaining in output FIFO (to JTAG)
reg [3:0] user_word_count; // bytes user intends to send from PC
reg [7:0] data_out_shift_reg; // parallel-load output shift register
// Control signals for the various counters / registers / state machines
reg rd_bit_ct_en; // enable bit counter
reg rd_bit_ct_rst; // reset (zero) bit count register
reg wr_bit_ct_en; // enable bit counter
reg wr_bit_ct_rst; // reset (zero) bit count register
reg in_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
reg out_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
reg in_word_ct_en; // Enable input byte counter register
reg out_word_ct_en; // Enable output byte count register
reg user_word_ct_en; // Enable user byte count registere
reg user_word_ct_sel; // selects data for user byte counter. 0 = user data, 1 = decremented byte count
reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg
reg out_reg_shift_en; // Enable shift of data_out_shift_reg
reg out_reg_data_sel; // 0 = BIU data, 1 = byte count data (also from BIU)
reg biu_rd_strobe; // Indicates that the bus unit should ACK the last read operation + start another
reg biu_wr_strobe; // Indicates BIU should latch input + begin a write operation
// Status signals
wire in_word_count_zero; // true when input byte counter is zero
wire out_word_count_zero; // true when output byte counter is zero
wire user_word_count_zero; // true when user byte counter is zero
wire rd_bit_count_max; // true when bit counter is equal to current word size
wire wr_bit_count_max; // true when bit counter is equal to current word size
// Intermediate signals
wire [3:0] data_to_in_word_counter; // output of the mux in front of the input byte counter reg
wire [3:0] data_to_out_word_counter; // output of the mux in front of the output byte counter reg
wire [3:0] data_to_user_word_counter; // output of mux in front of user word counter
wire [3:0] decremented_in_word_count;
wire [3:0] decremented_out_word_count;
wire [3:0] decremented_user_word_count;
wire [3:0] count_data_in; // from data_register_i
wire [7:0] data_to_biu; // from data_register_i
wire [7:0] data_from_biu; // to data_out_shift_register
wire [3:0] biu_space_available;
wire [3:0] biu_bytes_available;
wire [7:0] count_data_from_biu; // combined space avail / bytes avail
wire [7:0] out_reg_data; // parallel input to the output shift register
/////////////////////////////////////////////////
// Combinatorial assignments
assign count_data_from_biu = {biu_bytes_available, biu_space_available};
assign count_data_in = {tdi_i, data_register_i[52:50]}; // Second nibble of user data
assign data_to_biu = {tdi_i,data_register_i[52:46]};
assign top_inhibit_o = 1'b0;
//////////////////////////////////////
// Input bit counter
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) write_bit_count <= 4'h0;
else if(wr_bit_ct_rst) write_bit_count <= 4'h0;
else if(wr_bit_ct_en) write_bit_count <= write_bit_count + 4'h1;
end
assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;
//////////////////////////////////////
// Output bit counter
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) read_bit_count <= 4'h0;
else if(rd_bit_ct_rst) read_bit_count <= 4'h0;
else if(rd_bit_ct_en) read_bit_count <= read_bit_count + 4'h1;
end
assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;
////////////////////////////////////////
// Input word counter
assign data_to_in_word_counter = (in_word_ct_sel) ? decremented_in_word_count : biu_space_available;
assign decremented_in_word_count = input_word_count - 4'h1;
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
input_word_count <= 4'h0;
else if(in_word_ct_en)
input_word_count <= data_to_in_word_counter;
end
assign in_word_count_zero = (input_word_count == 4'h0);
////////////////////////////////////////
// Output word counter
assign data_to_out_word_counter = (out_word_ct_sel) ? decremented_out_word_count : biu_bytes_available;
assign decremented_out_word_count = output_word_count - 4'h1;
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
output_word_count <= 4'h0;
else if(out_word_ct_en)
output_word_count <= data_to_out_word_counter;
end
assign out_word_count_zero = (output_word_count == 4'h0);
////////////////////////////////////////
// User word counter
assign data_to_user_word_counter = (user_word_ct_sel) ? decremented_user_word_count : count_data_in;
assign decremented_user_word_count = user_word_count - 4'h1;
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) user_word_count <= 4'h0;
else if(user_word_ct_en) user_word_count <= data_to_user_word_counter;
end
assign user_word_count_zero = (user_word_count == 4'h0);
/////////////////////////////////////////////////////
// Output register and TDO output MUX
assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) data_out_shift_reg <= 8'h0;
else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
end
assign module_tdo_o = data_out_shift_reg[0];
////////////////////////////////////////
// Bus Interface Unit (to JTAG / WB UART)
// It is assumed that the BIU has internal registers, and will
// latch write data (and ack read data) on rising clock edge
// when strobe is asserted
adbg_jsp_biu jsp_biu_i (
// Debug interface signals
.tck_i (tck_i),
.rst_i (rst_i),
.data_i (data_to_biu),
.data_o (data_from_biu),
.bytes_available_o (biu_bytes_available),
.bytes_free_o (biu_space_available),
.rd_strobe_i (biu_rd_strobe),
.wr_strobe_i (biu_wr_strobe),
// Wishbone slave signals
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i),
.wb_dat_o (wb_dat_o),
.wb_dat_i (wb_dat_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_ack_o (wb_ack_o),
.wb_cab_i (wb_cab_i),
.wb_err_o (wb_err_o),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.int_o (int_o)
);
////////////////////////////////////////
// Input Control FSM
// Definition of machine state values.
// Don't worry too much about the state encoding, the synthesis tool
// will probably re-encode it anyway.
`define STATE_wr_idle 3'h0
`define STATE_wr_wait 3'h1
`define STATE_wr_counts 3'h2
`define STATE_wr_xfer 3'h3
reg [2:0] wr_module_state; // FSM state
reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register
// sequential part of the FSM
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
wr_module_state <= `STATE_wr_idle;
else
wr_module_state <= wr_module_next_state;
end
// Determination of next state; purely combinatorial
always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i
or shift_dr_i or wr_bit_count_max or tdi_i)
begin
case(wr_module_state)
`STATE_wr_idle:
begin
`ifdef ADBG_JSP_SUPPORT_MULTI
if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
`else
if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
`endif
else wr_module_next_state <= `STATE_wr_idle;
end
`STATE_wr_wait:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts; // got start bit
else wr_module_next_state <= `STATE_wr_wait;
end
`STATE_wr_counts:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
else wr_module_next_state <= `STATE_wr_counts;
end
`STATE_wr_xfer:
begin
if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
else wr_module_next_state <= `STATE_wr_xfer;
end
default: wr_module_next_state <= `STATE_wr_idle; // shouldn't actually happen...
endcase
end
// Outputs of state machine, pure combinatorial
always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
or decremented_out_word_count or user_word_count_zero)
begin
// Default everything to 0, keeps the case statement simple
wr_bit_ct_en <= 1'b0; // enable bit counter
wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register
in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
user_word_ct_sel <= 1'b0; // selects data for user byte counter, 0 = user data, 1 = decremented count
in_word_ct_en <= 1'b0; // Enable input byte counter register
user_word_ct_en <= 1'b0; // enable user byte count register
biu_wr_strobe <= 1'b0; // Indicates BIU should latch input + begin a write operation
case(wr_module_state)
`STATE_wr_idle:
begin
in_word_ct_sel <= 1'b0;
// Going to transfer; enable count registers and output register
if(wr_module_next_state != `STATE_wr_idle) begin
wr_bit_ct_rst <= 1'b1;
in_word_ct_en <= 1'b1;
end
end
// This state is only used when support for multi-device JTAG chains is enabled.
`STATE_wr_wait:
begin
wr_bit_ct_en <= 1'b0; // Don't do anything, just wait for the start bit.
end
`STATE_wr_counts:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
wr_bit_ct_en <= 1'b1;
user_word_ct_sel <= 1'b0;
if(wr_bit_count_max) begin
wr_bit_ct_rst <= 1'b1;
user_word_ct_en <= 1'b1;
end
end
end
`STATE_wr_xfer:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
wr_bit_ct_en <= 1'b1;
in_word_ct_sel <= 1'b1;
user_word_ct_sel <= 1'b1;
if(wr_bit_count_max) begin // Start biu transactions, if word counts allow
wr_bit_ct_rst <= 1'b1;
if(!(in_word_count_zero || user_word_count_zero)) begin
biu_wr_strobe <= 1'b1;
in_word_ct_en <= 1'b1;
user_word_ct_en <= 1'b1;
end
end
end
end
default: ;
endcase
end
////////////////////////////////////////
// Output Control FSM
// Definition of machine state values.
// Don't worry too much about the state encoding, the synthesis tool
// will probably re-encode it anyway.
`define STATE_rd_idle 4'h0
`define STATE_rd_counts 4'h1
`define STATE_rd_rdack 4'h2
`define STATE_rd_xfer 4'h3
// We do not send the equivalent of a 'start bit' (like the one the input FSM
// waits for when support for multi-device JTAG chains is enabled). Since the
// input and output are going to be offset anyway, why bother...
reg [2:0] rd_module_state; // FSM state
reg [2:0] rd_module_next_state; // combinatorial signal, not actually a register
// sequential part of the FSM
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i)
rd_module_state <= `STATE_rd_idle;
else
rd_module_state <= rd_module_next_state;
end
// Determination of next state; purely combinatorial
always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
begin
case(rd_module_state)
`STATE_rd_idle:
begin
if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
else rd_module_next_state <= `STATE_rd_idle;
end
`STATE_rd_counts:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
else rd_module_next_state <= `STATE_rd_counts;
end
`STATE_rd_rdack:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else rd_module_next_state <= `STATE_rd_xfer;
end
`STATE_rd_xfer:
begin
if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
else rd_module_next_state <= `STATE_rd_xfer;
end
default: rd_module_next_state <= `STATE_rd_idle; // shouldn't actually happen...
endcase
end
// Outputs of state machine, pure combinatorial
always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
or decremented_out_word_count)
begin
// Default everything to 0, keeps the case statement simple
rd_bit_ct_en <= 1'b0; // enable bit counter
rd_bit_ct_rst <= 1'b0; // reset (zero) bit count register
out_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
out_word_ct_en <= 1'b0; // Enable output byte count register
out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg
out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg
out_reg_data_sel <= 1'b0; // 0 = BIU data, 1 = byte count data (also from BIU)
biu_rd_strobe <= 1'b0; // Indicates that the bus unit should ACK the last read operation + start another
case(rd_module_state)
`STATE_rd_idle:
begin
out_reg_data_sel <= 1'b1;
out_word_ct_sel <= 1'b0;
// Going to transfer; enable count registers and output register
if(rd_module_next_state != `STATE_rd_idle) begin
out_reg_ld_en <= 1'b1;
rd_bit_ct_rst <= 1'b1;
out_word_ct_en <= 1'b1;
end
end
`STATE_rd_counts:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
rd_bit_ct_en <= 1'b1;
out_reg_shift_en <= 1'b1;
if(rd_bit_count_max) begin
rd_bit_ct_rst <= 1'b1;
// Latch the next output word, but don't ack until STATE_rd_rdack
if(!out_word_count_zero) begin
out_reg_ld_en <= 1'b1;
out_reg_shift_en <= 1'b0;
end
end
end
end
`STATE_rd_rdack:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
rd_bit_ct_en <= 1'b1;
out_reg_shift_en <= 1'b1;
out_reg_data_sel <= 1'b0;
// Never have to worry about bit_count_max here.
if(!out_word_count_zero) begin
biu_rd_strobe <= 1'b1;
end
end
end
`STATE_rd_xfer:
begin
if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states
rd_bit_ct_en <= 1'b1;
out_word_ct_sel <= 1'b1;
out_reg_shift_en <= 1'b1;
out_reg_data_sel <= 1'b0;
if(rd_bit_count_max) begin // Start biu transaction, if word count allows
rd_bit_ct_rst <= 1'b1;
// Don't ack the read byte here, we do it in STATE_rdack
if(!out_word_count_zero) begin
out_reg_ld_en <= 1'b1;
out_reg_shift_en <= 1'b0;
out_word_ct_en <= 1'b1;
end
end
end
end
default: ;
endcase
end
endmodule
|
// file: hashing_clock_multiplier.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___400.000______0.000______50.0_______85.815_____89.971
// CLK_OUT2___100.000______0.000______50.0______112.316_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "hashing_clock_multiplier,clk_wiz_v5_0,{component_name=hashing_clock_multiplier,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,PRIMITIVE=MMCME2,num_out_clk=2,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module hashing_clock_multiplier
(// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output tx_hash_clk,
output tx_comm_clk
);
hashing_clock_multiplier_clk_wiz inst
(// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n),
// Clock out ports
.tx_hash_clk(tx_hash_clk),
.tx_comm_clk(tx_comm_clk)
);
endmodule
|
`timescale 1 ns / 1 ps
module sync_2_fifo (
input clk,
input rst,
output [1:0] afull_out,
input [1:0] write_en_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_1_out,
output [63:0] data_0_out
);
wire [1:0] fifo_empty_s;
fifo_64x512 FIFO_0 (
.clk (clk),
.rst (rst),
.din (data_0_in),
.wr_en (write_en_in[0]),
.rd_en (read_en_in),
.dout (data_0_out),
.full (),
.empty (fifo_empty_s[0]),
.prog_full (afull_out[0])
);
fifo_64x512 FIFO_1 (
.clk (clk),
.rst (rst),
.din (data_1_in),
.wr_en (write_en_in[1]),
.rd_en (read_en_in),
.dout (data_1_out),
.full (),
.empty (fifo_empty_s[1]),
.prog_full (afull_out[1])
);
assign empty_out = (fifo_empty_s != 2'd0);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11,
o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/EFUSE_USR.v,v 1.1.72.1 2009/04/10 19:56:17 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description :
// / /
// /__/ /\ Filename : EFUSE_USR.v
// \ \ / \ Timestamp : Wed Mar 19 12:34:06 2008
// \__\/\__ \
//
// Revision:
// 03/19/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module EFUSE_USR (
EFUSEUSR
);
parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [31:0] EFUSEUSR;
assign EFUSEUSR = SIM_EFUSE_VALUE;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 2.5
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((done == 1) & (src_response_valid == 0)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:0, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) & (write_complete == 1) & (length_counter < bytes_to_transfer); // packet transfer and the length counter is about to roll over so stop transfering
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_3_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
// megafunction wizard: %ALTFP_SQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_sqrt
// ============================================================
// File Name: acl_fp_sqrt_double.v
// Megafunction Name(s):
// altfp_sqrt
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_sqrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=30 ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altfp_sqrt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//alt_sqrt_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=30 WIDTH_SQRT=54 aclr clken clock rad root_result
//VERSION_BEGIN 10.0SP1 cbx_altfp_sqrt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 54 reg 2383
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_double_alt_sqrt_block_1hb
(
aclr,
clken,
clock,
rad,
root_result) ;
input aclr;
input clken;
input clock;
input [54:0] rad;
output [53:0] root_result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] q_ff0c;
reg [51:0] q_ff10c;
reg [51:0] q_ff12c;
reg [51:0] q_ff14c;
reg [51:0] q_ff16c;
reg [51:0] q_ff18c;
reg [51:0] q_ff20c;
reg [51:0] q_ff22c;
reg [51:0] q_ff24c;
reg [51:0] q_ff26c;
reg [51:0] q_ff28c;
reg [51:0] q_ff2c;
reg [51:0] q_ff30c;
reg [51:0] q_ff32c;
reg [51:0] q_ff34c;
reg [51:0] q_ff36c;
reg [51:0] q_ff38c;
reg [51:0] q_ff40c;
reg [51:0] q_ff42c;
reg [51:0] q_ff44c;
reg [51:0] q_ff46c;
reg [51:0] q_ff48c;
reg [51:0] q_ff4c;
reg [51:0] q_ff50c;
reg [26:0] q_ff52c;
reg [51:0] q_ff6c;
reg [51:0] q_ff8c;
reg [43:0] rad_ff11c;
reg [41:0] rad_ff13c;
reg [39:0] rad_ff15c;
reg [37:0] rad_ff17c;
reg [35:0] rad_ff19c;
reg [53:0] rad_ff1c;
reg [33:0] rad_ff21c;
reg [31:0] rad_ff23c;
reg [29:0] rad_ff25c;
reg [27:0] rad_ff27c;
reg [28:0] rad_ff29c;
reg [30:0] rad_ff31c;
reg [32:0] rad_ff33c;
reg [34:0] rad_ff35c;
reg [36:0] rad_ff37c;
reg [38:0] rad_ff39c;
reg [51:0] rad_ff3c;
reg [40:0] rad_ff41c;
reg [42:0] rad_ff43c;
reg [44:0] rad_ff45c;
reg [46:0] rad_ff47c;
reg [48:0] rad_ff49c;
reg [50:0] rad_ff51c;
reg [49:0] rad_ff5c;
reg [47:0] rad_ff7c;
reg [45:0] rad_ff9c;
wire [8:0] wire_add_sub10_result;
wire [9:0] wire_add_sub11_result;
wire [10:0] wire_add_sub12_result;
wire [11:0] wire_add_sub13_result;
wire [12:0] wire_add_sub14_result;
wire [13:0] wire_add_sub15_result;
wire [14:0] wire_add_sub16_result;
wire [15:0] wire_add_sub17_result;
wire [16:0] wire_add_sub18_result;
wire [17:0] wire_add_sub19_result;
wire [18:0] wire_add_sub20_result;
wire [19:0] wire_add_sub21_result;
wire [20:0] wire_add_sub22_result;
wire [21:0] wire_add_sub23_result;
wire [22:0] wire_add_sub24_result;
wire [23:0] wire_add_sub25_result;
wire [24:0] wire_add_sub26_result;
wire [25:0] wire_add_sub27_result;
wire [26:0] wire_add_sub28_result;
wire [27:0] wire_add_sub29_result;
wire [28:0] wire_add_sub30_result;
wire [27:0] wire_add_sub31_result;
wire [27:0] wire_add_sub32_result;
wire [28:0] wire_add_sub33_result;
wire [29:0] wire_add_sub34_result;
wire [30:0] wire_add_sub35_result;
wire [31:0] wire_add_sub36_result;
wire [32:0] wire_add_sub37_result;
wire [33:0] wire_add_sub38_result;
wire [34:0] wire_add_sub39_result;
wire [2:0] wire_add_sub4_result;
wire [35:0] wire_add_sub40_result;
wire [36:0] wire_add_sub41_result;
wire [37:0] wire_add_sub42_result;
wire [38:0] wire_add_sub43_result;
wire [39:0] wire_add_sub44_result;
wire [40:0] wire_add_sub45_result;
wire [41:0] wire_add_sub46_result;
wire [42:0] wire_add_sub47_result;
wire [43:0] wire_add_sub48_result;
wire [44:0] wire_add_sub49_result;
wire [3:0] wire_add_sub5_result;
wire [45:0] wire_add_sub50_result;
wire [46:0] wire_add_sub51_result;
wire [47:0] wire_add_sub52_result;
wire [48:0] wire_add_sub53_result;
wire [49:0] wire_add_sub54_result;
wire [50:0] wire_add_sub55_result;
wire [51:0] wire_add_sub56_result;
wire [52:0] wire_add_sub57_result;
wire [4:0] wire_add_sub6_result;
wire [5:0] wire_add_sub7_result;
wire [6:0] wire_add_sub8_result;
wire [7:0] wire_add_sub9_result;
wire [55:0] addnode_w0c;
wire [55:0] addnode_w10c;
wire [55:0] addnode_w11c;
wire [55:0] addnode_w12c;
wire [55:0] addnode_w13c;
wire [55:0] addnode_w14c;
wire [55:0] addnode_w15c;
wire [55:0] addnode_w16c;
wire [55:0] addnode_w17c;
wire [55:0] addnode_w18c;
wire [55:0] addnode_w19c;
wire [55:0] addnode_w1c;
wire [55:0] addnode_w20c;
wire [55:0] addnode_w21c;
wire [55:0] addnode_w22c;
wire [55:0] addnode_w23c;
wire [55:0] addnode_w24c;
wire [55:0] addnode_w25c;
wire [55:0] addnode_w26c;
wire [55:0] addnode_w27c;
wire [55:0] addnode_w28c;
wire [55:0] addnode_w29c;
wire [55:0] addnode_w2c;
wire [55:0] addnode_w30c;
wire [55:0] addnode_w31c;
wire [55:0] addnode_w32c;
wire [55:0] addnode_w33c;
wire [55:0] addnode_w34c;
wire [55:0] addnode_w35c;
wire [55:0] addnode_w36c;
wire [55:0] addnode_w37c;
wire [55:0] addnode_w38c;
wire [55:0] addnode_w39c;
wire [55:0] addnode_w3c;
wire [55:0] addnode_w40c;
wire [55:0] addnode_w41c;
wire [55:0] addnode_w42c;
wire [55:0] addnode_w43c;
wire [55:0] addnode_w44c;
wire [55:0] addnode_w45c;
wire [55:0] addnode_w46c;
wire [55:0] addnode_w47c;
wire [55:0] addnode_w48c;
wire [55:0] addnode_w49c;
wire [55:0] addnode_w4c;
wire [55:0] addnode_w50c;
wire [55:0] addnode_w51c;
wire [55:0] addnode_w52c;
wire [55:0] addnode_w53c;
wire [55:0] addnode_w5c;
wire [55:0] addnode_w6c;
wire [55:0] addnode_w7c;
wire [55:0] addnode_w8c;
wire [55:0] addnode_w9c;
wire [2:0] qlevel_w0c;
wire [12:0] qlevel_w10c;
wire [13:0] qlevel_w11c;
wire [14:0] qlevel_w12c;
wire [15:0] qlevel_w13c;
wire [16:0] qlevel_w14c;
wire [17:0] qlevel_w15c;
wire [18:0] qlevel_w16c;
wire [19:0] qlevel_w17c;
wire [20:0] qlevel_w18c;
wire [21:0] qlevel_w19c;
wire [3:0] qlevel_w1c;
wire [22:0] qlevel_w20c;
wire [23:0] qlevel_w21c;
wire [24:0] qlevel_w22c;
wire [25:0] qlevel_w23c;
wire [26:0] qlevel_w24c;
wire [27:0] qlevel_w25c;
wire [28:0] qlevel_w26c;
wire [29:0] qlevel_w27c;
wire [30:0] qlevel_w28c;
wire [31:0] qlevel_w29c;
wire [4:0] qlevel_w2c;
wire [32:0] qlevel_w30c;
wire [33:0] qlevel_w31c;
wire [34:0] qlevel_w32c;
wire [35:0] qlevel_w33c;
wire [36:0] qlevel_w34c;
wire [37:0] qlevel_w35c;
wire [38:0] qlevel_w36c;
wire [39:0] qlevel_w37c;
wire [40:0] qlevel_w38c;
wire [41:0] qlevel_w39c;
wire [5:0] qlevel_w3c;
wire [42:0] qlevel_w40c;
wire [43:0] qlevel_w41c;
wire [44:0] qlevel_w42c;
wire [45:0] qlevel_w43c;
wire [46:0] qlevel_w44c;
wire [47:0] qlevel_w45c;
wire [48:0] qlevel_w46c;
wire [49:0] qlevel_w47c;
wire [50:0] qlevel_w48c;
wire [51:0] qlevel_w49c;
wire [6:0] qlevel_w4c;
wire [52:0] qlevel_w50c;
wire [53:0] qlevel_w51c;
wire [54:0] qlevel_w52c;
wire [55:0] qlevel_w53c;
wire [7:0] qlevel_w5c;
wire [8:0] qlevel_w6c;
wire [9:0] qlevel_w7c;
wire [10:0] qlevel_w8c;
wire [11:0] qlevel_w9c;
wire [55:0] slevel_w0c;
wire [55:0] slevel_w10c;
wire [55:0] slevel_w11c;
wire [55:0] slevel_w12c;
wire [55:0] slevel_w13c;
wire [55:0] slevel_w14c;
wire [55:0] slevel_w15c;
wire [55:0] slevel_w16c;
wire [55:0] slevel_w17c;
wire [55:0] slevel_w18c;
wire [55:0] slevel_w19c;
wire [55:0] slevel_w1c;
wire [55:0] slevel_w20c;
wire [55:0] slevel_w21c;
wire [55:0] slevel_w22c;
wire [55:0] slevel_w23c;
wire [55:0] slevel_w24c;
wire [55:0] slevel_w25c;
wire [55:0] slevel_w26c;
wire [55:0] slevel_w27c;
wire [55:0] slevel_w28c;
wire [55:0] slevel_w29c;
wire [55:0] slevel_w2c;
wire [55:0] slevel_w30c;
wire [55:0] slevel_w31c;
wire [55:0] slevel_w32c;
wire [55:0] slevel_w33c;
wire [55:0] slevel_w34c;
wire [55:0] slevel_w35c;
wire [55:0] slevel_w36c;
wire [55:0] slevel_w37c;
wire [55:0] slevel_w38c;
wire [55:0] slevel_w39c;
wire [55:0] slevel_w3c;
wire [55:0] slevel_w40c;
wire [55:0] slevel_w41c;
wire [55:0] slevel_w42c;
wire [55:0] slevel_w43c;
wire [55:0] slevel_w44c;
wire [55:0] slevel_w45c;
wire [55:0] slevel_w46c;
wire [55:0] slevel_w47c;
wire [55:0] slevel_w48c;
wire [55:0] slevel_w49c;
wire [55:0] slevel_w4c;
wire [55:0] slevel_w50c;
wire [55:0] slevel_w51c;
wire [55:0] slevel_w52c;
wire [55:0] slevel_w53c;
wire [55:0] slevel_w5c;
wire [55:0] slevel_w6c;
wire [55:0] slevel_w7c;
wire [55:0] slevel_w8c;
wire [55:0] slevel_w9c;
// synopsys translate_off
initial
q_ff0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff0c <= 2'b0;
else if (clken == 1'b1) q_ff0c <= {(~ addnode_w52c[55]), (~ addnode_w53c[55])};
// synopsys translate_off
initial
q_ff10c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff10c <= 52'b0;
else if (clken == 1'b1) q_ff10c <= {q_ff10c[49:0], (~ addnode_w42c[55]), (~ addnode_w43c[55])};
// synopsys translate_off
initial
q_ff12c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff12c <= 52'b0;
else if (clken == 1'b1) q_ff12c <= {q_ff12c[49:0], (~ addnode_w40c[55]), (~ addnode_w41c[55])};
// synopsys translate_off
initial
q_ff14c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff14c <= 52'b0;
else if (clken == 1'b1) q_ff14c <= {q_ff14c[49:0], (~ addnode_w38c[55]), (~ addnode_w39c[55])};
// synopsys translate_off
initial
q_ff16c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff16c <= 52'b0;
else if (clken == 1'b1) q_ff16c <= {q_ff16c[49:0], (~ addnode_w36c[55]), (~ addnode_w37c[55])};
// synopsys translate_off
initial
q_ff18c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff18c <= 52'b0;
else if (clken == 1'b1) q_ff18c <= {q_ff18c[49:0], (~ addnode_w34c[55]), (~ addnode_w35c[55])};
// synopsys translate_off
initial
q_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff20c <= 52'b0;
else if (clken == 1'b1) q_ff20c <= {q_ff20c[49:0], (~ addnode_w32c[55]), (~ addnode_w33c[55])};
// synopsys translate_off
initial
q_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff22c <= 52'b0;
else if (clken == 1'b1) q_ff22c <= {q_ff22c[49:0], (~ addnode_w30c[55]), (~ addnode_w31c[55])};
// synopsys translate_off
initial
q_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff24c <= 52'b0;
else if (clken == 1'b1) q_ff24c <= {q_ff24c[49:0], (~ addnode_w28c[55]), (~ addnode_w29c[55])};
// synopsys translate_off
initial
q_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff26c <= 52'b0;
else if (clken == 1'b1) q_ff26c <= {q_ff26c[49:0], (~ addnode_w26c[55]), (~ addnode_w27c[55])};
// synopsys translate_off
initial
q_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff28c <= 52'b0;
else if (clken == 1'b1) q_ff28c <= {q_ff28c[49:0], (~ addnode_w24c[55]), (~ addnode_w25c[55])};
// synopsys translate_off
initial
q_ff2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff2c <= 52'b0;
else if (clken == 1'b1) q_ff2c <= {q_ff2c[49:0], (~ addnode_w50c[55]), (~ addnode_w51c[55])};
// synopsys translate_off
initial
q_ff30c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff30c <= 52'b0;
else if (clken == 1'b1) q_ff30c <= {q_ff30c[49:0], (~ addnode_w22c[55]), (~ addnode_w23c[55])};
// synopsys translate_off
initial
q_ff32c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff32c <= 52'b0;
else if (clken == 1'b1) q_ff32c <= {q_ff32c[49:0], (~ addnode_w20c[55]), (~ addnode_w21c[55])};
// synopsys translate_off
initial
q_ff34c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff34c <= 52'b0;
else if (clken == 1'b1) q_ff34c <= {q_ff34c[49:0], (~ addnode_w18c[55]), (~ addnode_w19c[55])};
// synopsys translate_off
initial
q_ff36c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff36c <= 52'b0;
else if (clken == 1'b1) q_ff36c <= {q_ff36c[49:0], (~ addnode_w16c[55]), (~ addnode_w17c[55])};
// synopsys translate_off
initial
q_ff38c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff38c <= 52'b0;
else if (clken == 1'b1) q_ff38c <= {q_ff38c[49:0], (~ addnode_w14c[55]), (~ addnode_w15c[55])};
// synopsys translate_off
initial
q_ff40c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff40c <= 52'b0;
else if (clken == 1'b1) q_ff40c <= {q_ff40c[49:0], (~ addnode_w12c[55]), (~ addnode_w13c[55])};
// synopsys translate_off
initial
q_ff42c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff42c <= 52'b0;
else if (clken == 1'b1) q_ff42c <= {q_ff42c[49:0], (~ addnode_w10c[55]), (~ addnode_w11c[55])};
// synopsys translate_off
initial
q_ff44c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff44c <= 52'b0;
else if (clken == 1'b1) q_ff44c <= {q_ff44c[49:0], (~ addnode_w8c[55]), (~ addnode_w9c[55])};
// synopsys translate_off
initial
q_ff46c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff46c <= 52'b0;
else if (clken == 1'b1) q_ff46c <= {q_ff46c[49:0], (~ addnode_w6c[55]), (~ addnode_w7c[55])};
// synopsys translate_off
initial
q_ff48c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff48c <= 52'b0;
else if (clken == 1'b1) q_ff48c <= {q_ff48c[49:0], (~ addnode_w4c[55]), (~ addnode_w5c[55])};
// synopsys translate_off
initial
q_ff4c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff4c <= 52'b0;
else if (clken == 1'b1) q_ff4c <= {q_ff4c[49:0], (~ addnode_w48c[55]), (~ addnode_w49c[55])};
// synopsys translate_off
initial
q_ff50c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff50c <= 52'b0;
else if (clken == 1'b1) q_ff50c <= {q_ff50c[49:0], (~ addnode_w2c[55]), (~ addnode_w3c[55])};
// synopsys translate_off
initial
q_ff52c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff52c <= 27'b0;
else if (clken == 1'b1) q_ff52c <= {q_ff52c[25:0], (~ addnode_w1c[55])};
// synopsys translate_off
initial
q_ff6c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff6c <= 52'b0;
else if (clken == 1'b1) q_ff6c <= {q_ff6c[49:0], (~ addnode_w46c[55]), (~ addnode_w47c[55])};
// synopsys translate_off
initial
q_ff8c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff8c <= 52'b0;
else if (clken == 1'b1) q_ff8c <= {q_ff8c[49:0], (~ addnode_w44c[55]), (~ addnode_w45c[55])};
// synopsys translate_off
initial
rad_ff11c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff11c <= 44'b0;
else if (clken == 1'b1) rad_ff11c <= addnode_w11c[55:12];
// synopsys translate_off
initial
rad_ff13c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff13c <= 42'b0;
else if (clken == 1'b1) rad_ff13c <= addnode_w13c[55:14];
// synopsys translate_off
initial
rad_ff15c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff15c <= 40'b0;
else if (clken == 1'b1) rad_ff15c <= addnode_w15c[55:16];
// synopsys translate_off
initial
rad_ff17c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff17c <= 38'b0;
else if (clken == 1'b1) rad_ff17c <= addnode_w17c[55:18];
// synopsys translate_off
initial
rad_ff19c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff19c <= 36'b0;
else if (clken == 1'b1) rad_ff19c <= addnode_w19c[55:20];
// synopsys translate_off
initial
rad_ff1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff1c <= 54'b0;
else if (clken == 1'b1) rad_ff1c <= addnode_w1c[55:2];
// synopsys translate_off
initial
rad_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff21c <= 34'b0;
else if (clken == 1'b1) rad_ff21c <= addnode_w21c[55:22];
// synopsys translate_off
initial
rad_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff23c <= 32'b0;
else if (clken == 1'b1) rad_ff23c <= addnode_w23c[55:24];
// synopsys translate_off
initial
rad_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff25c <= 30'b0;
else if (clken == 1'b1) rad_ff25c <= addnode_w25c[55:26];
// synopsys translate_off
initial
rad_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff27c <= 28'b0;
else if (clken == 1'b1) rad_ff27c <= addnode_w27c[55:28];
// synopsys translate_off
initial
rad_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff29c <= 29'b0;
else if (clken == 1'b1) rad_ff29c <= addnode_w29c[55:27];
// synopsys translate_off
initial
rad_ff31c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff31c <= 31'b0;
else if (clken == 1'b1) rad_ff31c <= addnode_w31c[55:25];
// synopsys translate_off
initial
rad_ff33c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff33c <= 33'b0;
else if (clken == 1'b1) rad_ff33c <= addnode_w33c[55:23];
// synopsys translate_off
initial
rad_ff35c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff35c <= 35'b0;
else if (clken == 1'b1) rad_ff35c <= addnode_w35c[55:21];
// synopsys translate_off
initial
rad_ff37c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff37c <= 37'b0;
else if (clken == 1'b1) rad_ff37c <= addnode_w37c[55:19];
// synopsys translate_off
initial
rad_ff39c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff39c <= 39'b0;
else if (clken == 1'b1) rad_ff39c <= addnode_w39c[55:17];
// synopsys translate_off
initial
rad_ff3c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff3c <= 52'b0;
else if (clken == 1'b1) rad_ff3c <= addnode_w3c[55:4];
// synopsys translate_off
initial
rad_ff41c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff41c <= 41'b0;
else if (clken == 1'b1) rad_ff41c <= addnode_w41c[55:15];
// synopsys translate_off
initial
rad_ff43c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff43c <= 43'b0;
else if (clken == 1'b1) rad_ff43c <= addnode_w43c[55:13];
// synopsys translate_off
initial
rad_ff45c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff45c <= 45'b0;
else if (clken == 1'b1) rad_ff45c <= addnode_w45c[55:11];
// synopsys translate_off
initial
rad_ff47c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff47c <= 47'b0;
else if (clken == 1'b1) rad_ff47c <= addnode_w47c[55:9];
// synopsys translate_off
initial
rad_ff49c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff49c <= 49'b0;
else if (clken == 1'b1) rad_ff49c <= addnode_w49c[55:7];
// synopsys translate_off
initial
rad_ff51c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff51c <= 51'b0;
else if (clken == 1'b1) rad_ff51c <= addnode_w51c[55:5];
// synopsys translate_off
initial
rad_ff5c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff5c <= 50'b0;
else if (clken == 1'b1) rad_ff5c <= addnode_w5c[55:6];
// synopsys translate_off
initial
rad_ff7c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff7c <= 48'b0;
else if (clken == 1'b1) rad_ff7c <= addnode_w7c[55:8];
// synopsys translate_off
initial
rad_ff9c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff9c <= 46'b0;
else if (clken == 1'b1) rad_ff9c <= addnode_w9c[55:10];
lpm_add_sub add_sub10
(
.cout(),
.dataa({slevel_w6c[55:47]}),
.datab({(({7{(~ rad_ff5c[49])}} & (~ qlevel_w6c[8:2])) | ({7{rad_ff5c[49]}} & qlevel_w6c[8:2])), qlevel_w6c[1:0]}),
.overflow(),
.result(wire_add_sub10_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub10.lpm_direction = "ADD",
add_sub10.lpm_pipeline = 0,
add_sub10.lpm_width = 9,
add_sub10.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub11
(
.cout(),
.dataa({slevel_w7c[55:46]}),
.datab({(({8{(~ addnode_w6c[55])}} & (~ qlevel_w7c[9:2])) | ({8{addnode_w6c[55]}} & qlevel_w7c[9:2])), qlevel_w7c[1:0]}),
.overflow(),
.result(wire_add_sub11_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub11.lpm_direction = "ADD",
add_sub11.lpm_pipeline = 0,
add_sub11.lpm_width = 10,
add_sub11.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub12
(
.cout(),
.dataa({slevel_w8c[55:45]}),
.datab({(({9{(~ rad_ff7c[47])}} & (~ qlevel_w8c[10:2])) | ({9{rad_ff7c[47]}} & qlevel_w8c[10:2])), qlevel_w8c[1:0]}),
.overflow(),
.result(wire_add_sub12_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub12.lpm_direction = "ADD",
add_sub12.lpm_pipeline = 0,
add_sub12.lpm_width = 11,
add_sub12.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub13
(
.cout(),
.dataa({slevel_w9c[55:44]}),
.datab({(({10{(~ addnode_w8c[55])}} & (~ qlevel_w9c[11:2])) | ({10{addnode_w8c[55]}} & qlevel_w9c[11:2])), qlevel_w9c[1:0]}),
.overflow(),
.result(wire_add_sub13_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub13.lpm_direction = "ADD",
add_sub13.lpm_pipeline = 0,
add_sub13.lpm_width = 12,
add_sub13.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub14
(
.cout(),
.dataa({slevel_w10c[55:43]}),
.datab({(({11{(~ rad_ff9c[45])}} & (~ qlevel_w10c[12:2])) | ({11{rad_ff9c[45]}} & qlevel_w10c[12:2])), qlevel_w10c[1:0]}),
.overflow(),
.result(wire_add_sub14_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub14.lpm_direction = "ADD",
add_sub14.lpm_pipeline = 0,
add_sub14.lpm_width = 13,
add_sub14.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub15
(
.cout(),
.dataa({slevel_w11c[55:42]}),
.datab({(({12{(~ addnode_w10c[55])}} & (~ qlevel_w11c[13:2])) | ({12{addnode_w10c[55]}} & qlevel_w11c[13:2])), qlevel_w11c[1:0]}),
.overflow(),
.result(wire_add_sub15_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub15.lpm_direction = "ADD",
add_sub15.lpm_pipeline = 0,
add_sub15.lpm_width = 14,
add_sub15.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub16
(
.cout(),
.dataa({slevel_w12c[55:41]}),
.datab({(({13{(~ rad_ff11c[43])}} & (~ qlevel_w12c[14:2])) | ({13{rad_ff11c[43]}} & qlevel_w12c[14:2])), qlevel_w12c[1:0]}),
.overflow(),
.result(wire_add_sub16_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub16.lpm_direction = "ADD",
add_sub16.lpm_pipeline = 0,
add_sub16.lpm_width = 15,
add_sub16.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub17
(
.cout(),
.dataa({slevel_w13c[55:40]}),
.datab({(({14{(~ addnode_w12c[55])}} & (~ qlevel_w13c[15:2])) | ({14{addnode_w12c[55]}} & qlevel_w13c[15:2])), qlevel_w13c[1:0]}),
.overflow(),
.result(wire_add_sub17_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub17.lpm_direction = "ADD",
add_sub17.lpm_pipeline = 0,
add_sub17.lpm_width = 16,
add_sub17.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub18
(
.cout(),
.dataa({slevel_w14c[55:39]}),
.datab({(({15{(~ rad_ff13c[41])}} & (~ qlevel_w14c[16:2])) | ({15{rad_ff13c[41]}} & qlevel_w14c[16:2])), qlevel_w14c[1:0]}),
.overflow(),
.result(wire_add_sub18_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub18.lpm_direction = "ADD",
add_sub18.lpm_pipeline = 0,
add_sub18.lpm_width = 17,
add_sub18.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub19
(
.cout(),
.dataa({slevel_w15c[55:38]}),
.datab({(({16{(~ addnode_w14c[55])}} & (~ qlevel_w15c[17:2])) | ({16{addnode_w14c[55]}} & qlevel_w15c[17:2])), qlevel_w15c[1:0]}),
.overflow(),
.result(wire_add_sub19_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub19.lpm_direction = "ADD",
add_sub19.lpm_pipeline = 0,
add_sub19.lpm_width = 18,
add_sub19.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub20
(
.cout(),
.dataa({slevel_w16c[55:37]}),
.datab({(({17{(~ rad_ff15c[39])}} & (~ qlevel_w16c[18:2])) | ({17{rad_ff15c[39]}} & qlevel_w16c[18:2])), qlevel_w16c[1:0]}),
.overflow(),
.result(wire_add_sub20_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub20.lpm_direction = "ADD",
add_sub20.lpm_pipeline = 0,
add_sub20.lpm_width = 19,
add_sub20.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub21
(
.cout(),
.dataa({slevel_w17c[55:36]}),
.datab({(({18{(~ addnode_w16c[55])}} & (~ qlevel_w17c[19:2])) | ({18{addnode_w16c[55]}} & qlevel_w17c[19:2])), qlevel_w17c[1:0]}),
.overflow(),
.result(wire_add_sub21_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub21.lpm_direction = "ADD",
add_sub21.lpm_pipeline = 0,
add_sub21.lpm_width = 20,
add_sub21.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub22
(
.cout(),
.dataa({slevel_w18c[55:35]}),
.datab({(({19{(~ rad_ff17c[37])}} & (~ qlevel_w18c[20:2])) | ({19{rad_ff17c[37]}} & qlevel_w18c[20:2])), qlevel_w18c[1:0]}),
.overflow(),
.result(wire_add_sub22_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub22.lpm_direction = "ADD",
add_sub22.lpm_pipeline = 0,
add_sub22.lpm_width = 21,
add_sub22.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub23
(
.cout(),
.dataa({slevel_w19c[55:34]}),
.datab({(({20{(~ addnode_w18c[55])}} & (~ qlevel_w19c[21:2])) | ({20{addnode_w18c[55]}} & qlevel_w19c[21:2])), qlevel_w19c[1:0]}),
.overflow(),
.result(wire_add_sub23_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub23.lpm_direction = "ADD",
add_sub23.lpm_pipeline = 0,
add_sub23.lpm_width = 22,
add_sub23.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub24
(
.cout(),
.dataa({slevel_w20c[55:33]}),
.datab({(({21{(~ rad_ff19c[35])}} & (~ qlevel_w20c[22:2])) | ({21{rad_ff19c[35]}} & qlevel_w20c[22:2])), qlevel_w20c[1:0]}),
.overflow(),
.result(wire_add_sub24_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub24.lpm_direction = "ADD",
add_sub24.lpm_pipeline = 0,
add_sub24.lpm_width = 23,
add_sub24.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub25
(
.cout(),
.dataa({slevel_w21c[55:32]}),
.datab({(({22{(~ addnode_w20c[55])}} & (~ qlevel_w21c[23:2])) | ({22{addnode_w20c[55]}} & qlevel_w21c[23:2])), qlevel_w21c[1:0]}),
.overflow(),
.result(wire_add_sub25_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub25.lpm_direction = "ADD",
add_sub25.lpm_pipeline = 0,
add_sub25.lpm_width = 24,
add_sub25.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub26
(
.cout(),
.dataa({slevel_w22c[55:31]}),
.datab({(({23{(~ rad_ff21c[33])}} & (~ qlevel_w22c[24:2])) | ({23{rad_ff21c[33]}} & qlevel_w22c[24:2])), qlevel_w22c[1:0]}),
.overflow(),
.result(wire_add_sub26_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub26.lpm_direction = "ADD",
add_sub26.lpm_pipeline = 0,
add_sub26.lpm_width = 25,
add_sub26.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub27
(
.cout(),
.dataa({slevel_w23c[55:30]}),
.datab({(({24{(~ addnode_w22c[55])}} & (~ qlevel_w23c[25:2])) | ({24{addnode_w22c[55]}} & qlevel_w23c[25:2])), qlevel_w23c[1:0]}),
.overflow(),
.result(wire_add_sub27_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub27.lpm_direction = "ADD",
add_sub27.lpm_pipeline = 0,
add_sub27.lpm_width = 26,
add_sub27.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub28
(
.cout(),
.dataa({slevel_w24c[55:29]}),
.datab({(({25{(~ rad_ff23c[31])}} & (~ qlevel_w24c[26:2])) | ({25{rad_ff23c[31]}} & qlevel_w24c[26:2])), qlevel_w24c[1:0]}),
.overflow(),
.result(wire_add_sub28_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub28.lpm_direction = "ADD",
add_sub28.lpm_pipeline = 0,
add_sub28.lpm_width = 27,
add_sub28.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub29
(
.cout(),
.dataa({slevel_w25c[55:28]}),
.datab({(({26{(~ addnode_w24c[55])}} & (~ qlevel_w25c[27:2])) | ({26{addnode_w24c[55]}} & qlevel_w25c[27:2])), qlevel_w25c[1:0]}),
.overflow(),
.result(wire_add_sub29_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub29.lpm_direction = "ADD",
add_sub29.lpm_pipeline = 0,
add_sub29.lpm_width = 28,
add_sub29.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub30
(
.cout(),
.dataa({slevel_w26c[55:27]}),
.datab({(({27{(~ rad_ff25c[29])}} & (~ qlevel_w26c[28:2])) | ({27{rad_ff25c[29]}} & qlevel_w26c[28:2])), qlevel_w26c[1:0]}),
.overflow(),
.result(wire_add_sub30_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub30.lpm_direction = "ADD",
add_sub30.lpm_pipeline = 0,
add_sub30.lpm_width = 29,
add_sub30.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub31
(
.cout(),
.dataa({slevel_w27c[55:28]}),
.datab({(({28{(~ addnode_w26c[55])}} & (~ qlevel_w27c[29:2])) | ({28{addnode_w26c[55]}} & qlevel_w27c[29:2]))}),
.overflow(),
.result(wire_add_sub31_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub31.lpm_direction = "ADD",
add_sub31.lpm_pipeline = 0,
add_sub31.lpm_width = 28,
add_sub31.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub32
(
.cout(),
.dataa({slevel_w28c[55:28]}),
.datab({(({28{(~ rad_ff27c[27])}} & (~ qlevel_w28c[30:3])) | ({28{rad_ff27c[27]}} & qlevel_w28c[30:3]))}),
.overflow(),
.result(wire_add_sub32_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub32.lpm_direction = "ADD",
add_sub32.lpm_pipeline = 0,
add_sub32.lpm_width = 28,
add_sub32.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub33
(
.cout(),
.dataa({slevel_w29c[55:27]}),
.datab({(({29{(~ addnode_w28c[55])}} & (~ qlevel_w29c[31:3])) | ({29{addnode_w28c[55]}} & qlevel_w29c[31:3]))}),
.overflow(),
.result(wire_add_sub33_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub33.lpm_direction = "ADD",
add_sub33.lpm_pipeline = 0,
add_sub33.lpm_width = 29,
add_sub33.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub34
(
.cout(),
.dataa({slevel_w30c[55:26]}),
.datab({(({30{(~ rad_ff29c[28])}} & (~ qlevel_w30c[32:3])) | ({30{rad_ff29c[28]}} & qlevel_w30c[32:3]))}),
.overflow(),
.result(wire_add_sub34_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub34.lpm_direction = "ADD",
add_sub34.lpm_pipeline = 0,
add_sub34.lpm_width = 30,
add_sub34.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub35
(
.cout(),
.dataa({slevel_w31c[55:25]}),
.datab({(({31{(~ addnode_w30c[55])}} & (~ qlevel_w31c[33:3])) | ({31{addnode_w30c[55]}} & qlevel_w31c[33:3]))}),
.overflow(),
.result(wire_add_sub35_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub35.lpm_direction = "ADD",
add_sub35.lpm_pipeline = 0,
add_sub35.lpm_width = 31,
add_sub35.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub36
(
.cout(),
.dataa({slevel_w32c[55:24]}),
.datab({(({32{(~ rad_ff31c[30])}} & (~ qlevel_w32c[34:3])) | ({32{rad_ff31c[30]}} & qlevel_w32c[34:3]))}),
.overflow(),
.result(wire_add_sub36_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub36.lpm_direction = "ADD",
add_sub36.lpm_pipeline = 0,
add_sub36.lpm_width = 32,
add_sub36.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub37
(
.cout(),
.dataa({slevel_w33c[55:23]}),
.datab({(({33{(~ addnode_w32c[55])}} & (~ qlevel_w33c[35:3])) | ({33{addnode_w32c[55]}} & qlevel_w33c[35:3]))}),
.overflow(),
.result(wire_add_sub37_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub37.lpm_direction = "ADD",
add_sub37.lpm_pipeline = 0,
add_sub37.lpm_width = 33,
add_sub37.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub38
(
.cout(),
.dataa({slevel_w34c[55:22]}),
.datab({(({34{(~ rad_ff33c[32])}} & (~ qlevel_w34c[36:3])) | ({34{rad_ff33c[32]}} & qlevel_w34c[36:3]))}),
.overflow(),
.result(wire_add_sub38_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub38.lpm_direction = "ADD",
add_sub38.lpm_pipeline = 0,
add_sub38.lpm_width = 34,
add_sub38.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub39
(
.cout(),
.dataa({slevel_w35c[55:21]}),
.datab({(({35{(~ addnode_w34c[55])}} & (~ qlevel_w35c[37:3])) | ({35{addnode_w34c[55]}} & qlevel_w35c[37:3]))}),
.overflow(),
.result(wire_add_sub39_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub39.lpm_direction = "ADD",
add_sub39.lpm_pipeline = 0,
add_sub39.lpm_width = 35,
add_sub39.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa({slevel_w0c[55:53]}),
.datab({qlevel_w0c[2:0]}),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_pipeline = 0,
add_sub4.lpm_width = 3,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub40
(
.cout(),
.dataa({slevel_w36c[55:20]}),
.datab({(({36{(~ rad_ff35c[34])}} & (~ qlevel_w36c[38:3])) | ({36{rad_ff35c[34]}} & qlevel_w36c[38:3]))}),
.overflow(),
.result(wire_add_sub40_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub40.lpm_direction = "ADD",
add_sub40.lpm_pipeline = 0,
add_sub40.lpm_width = 36,
add_sub40.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub41
(
.cout(),
.dataa({slevel_w37c[55:19]}),
.datab({(({37{(~ addnode_w36c[55])}} & (~ qlevel_w37c[39:3])) | ({37{addnode_w36c[55]}} & qlevel_w37c[39:3]))}),
.overflow(),
.result(wire_add_sub41_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub41.lpm_direction = "ADD",
add_sub41.lpm_pipeline = 0,
add_sub41.lpm_width = 37,
add_sub41.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub42
(
.cout(),
.dataa({slevel_w38c[55:18]}),
.datab({(({38{(~ rad_ff37c[36])}} & (~ qlevel_w38c[40:3])) | ({38{rad_ff37c[36]}} & qlevel_w38c[40:3]))}),
.overflow(),
.result(wire_add_sub42_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub42.lpm_direction = "ADD",
add_sub42.lpm_pipeline = 0,
add_sub42.lpm_width = 38,
add_sub42.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub43
(
.cout(),
.dataa({slevel_w39c[55:17]}),
.datab({(({39{(~ addnode_w38c[55])}} & (~ qlevel_w39c[41:3])) | ({39{addnode_w38c[55]}} & qlevel_w39c[41:3]))}),
.overflow(),
.result(wire_add_sub43_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub43.lpm_direction = "ADD",
add_sub43.lpm_pipeline = 0,
add_sub43.lpm_width = 39,
add_sub43.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub44
(
.cout(),
.dataa({slevel_w40c[55:16]}),
.datab({(({40{(~ rad_ff39c[38])}} & (~ qlevel_w40c[42:3])) | ({40{rad_ff39c[38]}} & qlevel_w40c[42:3]))}),
.overflow(),
.result(wire_add_sub44_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub44.lpm_direction = "ADD",
add_sub44.lpm_pipeline = 0,
add_sub44.lpm_width = 40,
add_sub44.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub45
(
.cout(),
.dataa({slevel_w41c[55:15]}),
.datab({(({41{(~ addnode_w40c[55])}} & (~ qlevel_w41c[43:3])) | ({41{addnode_w40c[55]}} & qlevel_w41c[43:3]))}),
.overflow(),
.result(wire_add_sub45_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub45.lpm_direction = "ADD",
add_sub45.lpm_pipeline = 0,
add_sub45.lpm_width = 41,
add_sub45.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub46
(
.cout(),
.dataa({slevel_w42c[55:14]}),
.datab({(({42{(~ rad_ff41c[40])}} & (~ qlevel_w42c[44:3])) | ({42{rad_ff41c[40]}} & qlevel_w42c[44:3]))}),
.overflow(),
.result(wire_add_sub46_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub46.lpm_direction = "ADD",
add_sub46.lpm_pipeline = 0,
add_sub46.lpm_width = 42,
add_sub46.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub47
(
.cout(),
.dataa({slevel_w43c[55:13]}),
.datab({(({43{(~ addnode_w42c[55])}} & (~ qlevel_w43c[45:3])) | ({43{addnode_w42c[55]}} & qlevel_w43c[45:3]))}),
.overflow(),
.result(wire_add_sub47_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub47.lpm_direction = "ADD",
add_sub47.lpm_pipeline = 0,
add_sub47.lpm_width = 43,
add_sub47.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub48
(
.cout(),
.dataa({slevel_w44c[55:12]}),
.datab({(({44{(~ rad_ff43c[42])}} & (~ qlevel_w44c[46:3])) | ({44{rad_ff43c[42]}} & qlevel_w44c[46:3]))}),
.overflow(),
.result(wire_add_sub48_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub48.lpm_direction = "ADD",
add_sub48.lpm_pipeline = 0,
add_sub48.lpm_width = 44,
add_sub48.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub49
(
.cout(),
.dataa({slevel_w45c[55:11]}),
.datab({(({45{(~ addnode_w44c[55])}} & (~ qlevel_w45c[47:3])) | ({45{addnode_w44c[55]}} & qlevel_w45c[47:3]))}),
.overflow(),
.result(wire_add_sub49_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub49.lpm_direction = "ADD",
add_sub49.lpm_pipeline = 0,
add_sub49.lpm_width = 45,
add_sub49.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.cout(),
.dataa({slevel_w1c[55:52]}),
.datab({qlevel_w1c[3:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 0,
add_sub5.lpm_width = 4,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub50
(
.cout(),
.dataa({slevel_w46c[55:10]}),
.datab({(({46{(~ rad_ff45c[44])}} & (~ qlevel_w46c[48:3])) | ({46{rad_ff45c[44]}} & qlevel_w46c[48:3]))}),
.overflow(),
.result(wire_add_sub50_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub50.lpm_direction = "ADD",
add_sub50.lpm_pipeline = 0,
add_sub50.lpm_width = 46,
add_sub50.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub51
(
.cout(),
.dataa({slevel_w47c[55:9]}),
.datab({(({47{(~ addnode_w46c[55])}} & (~ qlevel_w47c[49:3])) | ({47{addnode_w46c[55]}} & qlevel_w47c[49:3]))}),
.overflow(),
.result(wire_add_sub51_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub51.lpm_direction = "ADD",
add_sub51.lpm_pipeline = 0,
add_sub51.lpm_width = 47,
add_sub51.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub52
(
.cout(),
.dataa({slevel_w48c[55:8]}),
.datab({(({48{(~ rad_ff47c[46])}} & (~ qlevel_w48c[50:3])) | ({48{rad_ff47c[46]}} & qlevel_w48c[50:3]))}),
.overflow(),
.result(wire_add_sub52_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub52.lpm_direction = "ADD",
add_sub52.lpm_pipeline = 0,
add_sub52.lpm_width = 48,
add_sub52.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub53
(
.cout(),
.dataa({slevel_w49c[55:7]}),
.datab({(({49{(~ addnode_w48c[55])}} & (~ qlevel_w49c[51:3])) | ({49{addnode_w48c[55]}} & qlevel_w49c[51:3]))}),
.overflow(),
.result(wire_add_sub53_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub53.lpm_direction = "ADD",
add_sub53.lpm_pipeline = 0,
add_sub53.lpm_width = 49,
add_sub53.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub54
(
.cout(),
.dataa({slevel_w50c[55:6]}),
.datab({(({50{(~ rad_ff49c[48])}} & (~ qlevel_w50c[52:3])) | ({50{rad_ff49c[48]}} & qlevel_w50c[52:3]))}),
.overflow(),
.result(wire_add_sub54_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub54.lpm_direction = "ADD",
add_sub54.lpm_pipeline = 0,
add_sub54.lpm_width = 50,
add_sub54.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub55
(
.cout(),
.dataa({slevel_w51c[55:5]}),
.datab({(({51{(~ addnode_w50c[55])}} & (~ qlevel_w51c[53:3])) | ({51{addnode_w50c[55]}} & qlevel_w51c[53:3]))}),
.overflow(),
.result(wire_add_sub55_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub55.lpm_direction = "ADD",
add_sub55.lpm_pipeline = 0,
add_sub55.lpm_width = 51,
add_sub55.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub56
(
.cout(),
.dataa({slevel_w52c[55:4]}),
.datab({(({52{(~ rad_ff51c[50])}} & (~ qlevel_w52c[54:3])) | ({52{rad_ff51c[50]}} & qlevel_w52c[54:3]))}),
.overflow(),
.result(wire_add_sub56_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub56.lpm_direction = "ADD",
add_sub56.lpm_pipeline = 0,
add_sub56.lpm_width = 52,
add_sub56.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub57
(
.cout(),
.dataa({slevel_w53c[55:3]}),
.datab({qlevel_w53c[55:54], (({51{(~ addnode_w52c[55])}} & (~ qlevel_w53c[53:3])) | ({51{addnode_w52c[55]}} & qlevel_w53c[53:3]))}),
.overflow(),
.result(wire_add_sub57_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub57.lpm_direction = "ADD",
add_sub57.lpm_pipeline = 0,
add_sub57.lpm_width = 53,
add_sub57.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa({slevel_w2c[55:51]}),
.datab({(({3{(~ rad_ff1c[53])}} & (~ qlevel_w2c[4:2])) | ({3{rad_ff1c[53]}} & qlevel_w2c[4:2])), qlevel_w2c[1:0]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_pipeline = 0,
add_sub6.lpm_width = 5,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub7
(
.cout(),
.dataa({slevel_w3c[55:50]}),
.datab({(({4{(~ addnode_w2c[55])}} & (~ qlevel_w3c[5:2])) | ({4{addnode_w2c[55]}} & qlevel_w3c[5:2])), qlevel_w3c[1:0]}),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_pipeline = 0,
add_sub7.lpm_width = 6,
add_sub7.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub8
(
.cout(),
.dataa({slevel_w4c[55:49]}),
.datab({(({5{(~ rad_ff3c[51])}} & (~ qlevel_w4c[6:2])) | ({5{rad_ff3c[51]}} & qlevel_w4c[6:2])), qlevel_w4c[1:0]}),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_pipeline = 0,
add_sub8.lpm_width = 7,
add_sub8.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub9
(
.cout(),
.dataa({slevel_w5c[55:48]}),
.datab({(({6{(~ addnode_w4c[55])}} & (~ qlevel_w5c[7:2])) | ({6{addnode_w4c[55]}} & qlevel_w5c[7:2])), qlevel_w5c[1:0]}),
.overflow(),
.result(wire_add_sub9_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub9.lpm_direction = "ADD",
add_sub9.lpm_pipeline = 0,
add_sub9.lpm_width = 8,
add_sub9.lpm_type = "lpm_add_sub";
assign
addnode_w0c = {wire_add_sub4_result[2:0], slevel_w0c[52:0]},
addnode_w10c = {wire_add_sub14_result[12:0], slevel_w10c[42:0]},
addnode_w11c = {wire_add_sub15_result[13:0], slevel_w11c[41:0]},
addnode_w12c = {wire_add_sub16_result[14:0], slevel_w12c[40:0]},
addnode_w13c = {wire_add_sub17_result[15:0], slevel_w13c[39:0]},
addnode_w14c = {wire_add_sub18_result[16:0], slevel_w14c[38:0]},
addnode_w15c = {wire_add_sub19_result[17:0], slevel_w15c[37:0]},
addnode_w16c = {wire_add_sub20_result[18:0], slevel_w16c[36:0]},
addnode_w17c = {wire_add_sub21_result[19:0], slevel_w17c[35:0]},
addnode_w18c = {wire_add_sub22_result[20:0], slevel_w18c[34:0]},
addnode_w19c = {wire_add_sub23_result[21:0], slevel_w19c[33:0]},
addnode_w1c = {wire_add_sub5_result[3:0], slevel_w1c[51:0]},
addnode_w20c = {wire_add_sub24_result[22:0], slevel_w20c[32:0]},
addnode_w21c = {wire_add_sub25_result[23:0], slevel_w21c[31:0]},
addnode_w22c = {wire_add_sub26_result[24:0], slevel_w22c[30:0]},
addnode_w23c = {wire_add_sub27_result[25:0], slevel_w23c[29:0]},
addnode_w24c = {wire_add_sub28_result[26:0], slevel_w24c[28:0]},
addnode_w25c = {wire_add_sub29_result[27:0], slevel_w25c[27:0]},
addnode_w26c = {wire_add_sub30_result[28:0], slevel_w26c[26:0]},
addnode_w27c = {wire_add_sub31_result[27:0], qlevel_w27c[1:0], slevel_w27c[25:0]},
addnode_w28c = {wire_add_sub32_result[27:0], 1'b1, qlevel_w28c[1:0], slevel_w28c[24:0]},
addnode_w29c = {wire_add_sub33_result[28:0], 1'b1, qlevel_w29c[1:0], slevel_w29c[23:0]},
addnode_w2c = {wire_add_sub6_result[4:0], slevel_w2c[50:0]},
addnode_w30c = {wire_add_sub34_result[29:0], 1'b1, qlevel_w30c[1:0], slevel_w30c[22:0]},
addnode_w31c = {wire_add_sub35_result[30:0], 1'b1, qlevel_w31c[1:0], slevel_w31c[21:0]},
addnode_w32c = {wire_add_sub36_result[31:0], 1'b1, qlevel_w32c[1:0], slevel_w32c[20:0]},
addnode_w33c = {wire_add_sub37_result[32:0], 1'b1, qlevel_w33c[1:0], slevel_w33c[19:0]},
addnode_w34c = {wire_add_sub38_result[33:0], 1'b1, qlevel_w34c[1:0], slevel_w34c[18:0]},
addnode_w35c = {wire_add_sub39_result[34:0], 1'b1, qlevel_w35c[1:0], slevel_w35c[17:0]},
addnode_w36c = {wire_add_sub40_result[35:0], 1'b1, qlevel_w36c[1:0], slevel_w36c[16:0]},
addnode_w37c = {wire_add_sub41_result[36:0], 1'b1, qlevel_w37c[1:0], slevel_w37c[15:0]},
addnode_w38c = {wire_add_sub42_result[37:0], 1'b1, qlevel_w38c[1:0], slevel_w38c[14:0]},
addnode_w39c = {wire_add_sub43_result[38:0], 1'b1, qlevel_w39c[1:0], slevel_w39c[13:0]},
addnode_w3c = {wire_add_sub7_result[5:0], slevel_w3c[49:0]},
addnode_w40c = {wire_add_sub44_result[39:0], 1'b1, qlevel_w40c[1:0], slevel_w40c[12:0]},
addnode_w41c = {wire_add_sub45_result[40:0], 1'b1, qlevel_w41c[1:0], slevel_w41c[11:0]},
addnode_w42c = {wire_add_sub46_result[41:0], 1'b1, qlevel_w42c[1:0], slevel_w42c[10:0]},
addnode_w43c = {wire_add_sub47_result[42:0], 1'b1, qlevel_w43c[1:0], slevel_w43c[9:0]},
addnode_w44c = {wire_add_sub48_result[43:0], 1'b1, qlevel_w44c[1:0], slevel_w44c[8:0]},
addnode_w45c = {wire_add_sub49_result[44:0], 1'b1, qlevel_w45c[1:0], slevel_w45c[7:0]},
addnode_w46c = {wire_add_sub50_result[45:0], 1'b1, qlevel_w46c[1:0], slevel_w46c[6:0]},
addnode_w47c = {wire_add_sub51_result[46:0], 1'b1, qlevel_w47c[1:0], slevel_w47c[5:0]},
addnode_w48c = {wire_add_sub52_result[47:0], 1'b1, qlevel_w48c[1:0], slevel_w48c[4:0]},
addnode_w49c = {wire_add_sub53_result[48:0], 1'b1, qlevel_w49c[1:0], slevel_w49c[3:0]},
addnode_w4c = {wire_add_sub8_result[6:0], slevel_w4c[48:0]},
addnode_w50c = {wire_add_sub54_result[49:0], 1'b1, qlevel_w50c[1:0], slevel_w50c[2:0]},
addnode_w51c = {wire_add_sub55_result[50:0], 1'b1, qlevel_w51c[1:0], slevel_w51c[1:0]},
addnode_w52c = {wire_add_sub56_result[51:0], 1'b1, qlevel_w52c[1:0], slevel_w52c[0]},
addnode_w53c = {wire_add_sub57_result[52:0], 1'b1, qlevel_w53c[1:0]},
addnode_w5c = {wire_add_sub9_result[7:0], slevel_w5c[47:0]},
addnode_w6c = {wire_add_sub10_result[8:0], slevel_w6c[46:0]},
addnode_w7c = {wire_add_sub11_result[9:0], slevel_w7c[45:0]},
addnode_w8c = {wire_add_sub12_result[10:0], slevel_w8c[44:0]},
addnode_w9c = {wire_add_sub13_result[11:0], slevel_w9c[43:0]},
qlevel_w0c = {3{1'b1}},
qlevel_w10c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], {2{1'b1}}},
qlevel_w11c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], (~ addnode_w10c[55]), {2{1'b1}}},
qlevel_w12c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], {2{1'b1}}},
qlevel_w13c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], (~ addnode_w12c[55]), {2{1'b1}}},
qlevel_w14c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], {2{1'b1}}},
qlevel_w15c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], (~ addnode_w14c[55]), {2{1'b1}}},
qlevel_w16c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], {2{1'b1}}},
qlevel_w17c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], (~ addnode_w16c[55]), {2{1'b1}}},
qlevel_w18c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], {2{1'b1}}},
qlevel_w19c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], (~ addnode_w18c[55]), {2{1'b1}}},
qlevel_w1c = {1'b1, 1'b0, {2{1'b1}}},
qlevel_w20c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], {2{1'b1}}},
qlevel_w21c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], (~ addnode_w20c[55]), {2{1'b1}}},
qlevel_w22c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], {2{1'b1}}},
qlevel_w23c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], (~ addnode_w22c[55]), {2{1'b1}}},
qlevel_w24c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], {2{1'b1}}},
qlevel_w25c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], (~ addnode_w24c[55]), {2{1'b1}}},
qlevel_w26c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], {2{1'b1}}},
qlevel_w27c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], (~ addnode_w26c[55]), {2{1'b1}}},
qlevel_w28c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], {2{1'b1}}},
qlevel_w29c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], (~ addnode_w28c[55]), {2{1'b1}}},
qlevel_w2c = {1'b0, 1'b1, q_ff52c[0], {2{1'b1}}},
qlevel_w30c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], {2{1'b1}}},
qlevel_w31c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], (~ addnode_w30c[55]), {2{1'b1}}},
qlevel_w32c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], {2{1'b1}}},
qlevel_w33c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], (~ addnode_w32c[55]), {2{1'b1}}},
qlevel_w34c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], {2{1'b1}}},
qlevel_w35c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], (~ addnode_w34c[55]), {2{1'b1}}},
qlevel_w36c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], {2{1'b1}}},
qlevel_w37c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], (~ addnode_w36c[55]), {2{1'b1}}},
qlevel_w38c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], {2{1'b1}}},
qlevel_w39c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], (~ addnode_w38c[55]), {2{1'b1}}},
qlevel_w3c = {1'b0, 1'b1, q_ff52c[0], (~ addnode_w2c[55]), {2{1'b1}}},
qlevel_w40c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], {2{1'b1}}},
qlevel_w41c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], (~ addnode_w40c[55]), {2{1'b1}}},
qlevel_w42c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], {2{1'b1}}},
qlevel_w43c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], (~ addnode_w42c[55]), {2{1'b1}}},
qlevel_w44c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], {2{1'b1}}},
qlevel_w45c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], (~ addnode_w44c[55]), {2{1'b1}}},
qlevel_w46c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], {2{1'b1}}},
qlevel_w47c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], (~ addnode_w46c[55]), {2{1'b1}}},
qlevel_w48c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], {2{1'b1}}},
qlevel_w49c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], (~ addnode_w48c[55]), {2{1'b1}}},
qlevel_w4c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], {2{1'b1}}},
qlevel_w50c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], {2{1'b1}}},
qlevel_w51c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], (~ addnode_w50c[55]), {2{1'b1}}},
qlevel_w52c = {1'b0, 1'b1, q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], {2{1'b1}}},
qlevel_w53c = {(~ addnode_w52c[55]), addnode_w52c[55], q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], (~ addnode_w52c[55]), {2{1'b1}}},
qlevel_w5c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], (~ addnode_w4c[55]), {2{1'b1}}},
qlevel_w6c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], {2{1'b1}}},
qlevel_w7c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], (~ addnode_w6c[55]), {2{1'b1}}},
qlevel_w8c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], {2{1'b1}}},
qlevel_w9c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], (~ addnode_w8c[55]), {2{1'b1}}},
root_result = {1'b1, q_ff52c[26], q_ff50c[51:50], q_ff48c[49:48], q_ff46c[47:46], q_ff44c[45:44], q_ff42c[43:42], q_ff40c[41:40], q_ff38c[39:38], q_ff36c[37:36], q_ff34c[35:34], q_ff32c[33:32], q_ff30c[31:30], q_ff28c[29:28], q_ff26c[27:26], q_ff24c[25:24], q_ff22c[23:22], q_ff20c[21:20], q_ff18c[19:18], q_ff16c[17:16], q_ff14c[15:14], q_ff12c[13:12], q_ff10c[11:10], q_ff8c[9:8], q_ff6c[7:6], q_ff4c[5:4], q_ff2c[3:2], q_ff0c[1:0]},
slevel_w0c = {1'b0, rad},
slevel_w10c = {rad_ff9c[44:0], {11{1'b0}}},
slevel_w11c = {addnode_w10c[54:11], {12{1'b0}}},
slevel_w12c = {rad_ff11c[42:0], {13{1'b0}}},
slevel_w13c = {addnode_w12c[54:13], {14{1'b0}}},
slevel_w14c = {rad_ff13c[40:0], {15{1'b0}}},
slevel_w15c = {addnode_w14c[54:15], {16{1'b0}}},
slevel_w16c = {rad_ff15c[38:0], {17{1'b0}}},
slevel_w17c = {addnode_w16c[54:17], {18{1'b0}}},
slevel_w18c = {rad_ff17c[36:0], {19{1'b0}}},
slevel_w19c = {addnode_w18c[54:19], {20{1'b0}}},
slevel_w1c = {addnode_w0c[54:1], {2{1'b0}}},
slevel_w20c = {rad_ff19c[34:0], {21{1'b0}}},
slevel_w21c = {addnode_w20c[54:21], {22{1'b0}}},
slevel_w22c = {rad_ff21c[32:0], {23{1'b0}}},
slevel_w23c = {addnode_w22c[54:23], {24{1'b0}}},
slevel_w24c = {rad_ff23c[30:0], {25{1'b0}}},
slevel_w25c = {addnode_w24c[54:25], {26{1'b0}}},
slevel_w26c = {rad_ff25c[28:0], {27{1'b0}}},
slevel_w27c = {addnode_w26c[54:27], {28{1'b0}}},
slevel_w28c = {rad_ff27c[26:0], {2{1'b1}}, {27{1'b0}}},
slevel_w29c = {addnode_w28c[54:28], {3{1'b1}}, {26{1'b0}}},
slevel_w2c = {rad_ff1c[52:0], {3{1'b0}}},
slevel_w30c = {rad_ff29c[27:0], {3{1'b1}}, {25{1'b0}}},
slevel_w31c = {addnode_w30c[54:26], {3{1'b1}}, {24{1'b0}}},
slevel_w32c = {rad_ff31c[29:0], {3{1'b1}}, {23{1'b0}}},
slevel_w33c = {addnode_w32c[54:24], {3{1'b1}}, {22{1'b0}}},
slevel_w34c = {rad_ff33c[31:0], {3{1'b1}}, {21{1'b0}}},
slevel_w35c = {addnode_w34c[54:22], {3{1'b1}}, {20{1'b0}}},
slevel_w36c = {rad_ff35c[33:0], {3{1'b1}}, {19{1'b0}}},
slevel_w37c = {addnode_w36c[54:20], {3{1'b1}}, {18{1'b0}}},
slevel_w38c = {rad_ff37c[35:0], {3{1'b1}}, {17{1'b0}}},
slevel_w39c = {addnode_w38c[54:18], {3{1'b1}}, {16{1'b0}}},
slevel_w3c = {addnode_w2c[54:3], {4{1'b0}}},
slevel_w40c = {rad_ff39c[37:0], {3{1'b1}}, {15{1'b0}}},
slevel_w41c = {addnode_w40c[54:16], {3{1'b1}}, {14{1'b0}}},
slevel_w42c = {rad_ff41c[39:0], {3{1'b1}}, {13{1'b0}}},
slevel_w43c = {addnode_w42c[54:14], {3{1'b1}}, {12{1'b0}}},
slevel_w44c = {rad_ff43c[41:0], {3{1'b1}}, {11{1'b0}}},
slevel_w45c = {addnode_w44c[54:12], {3{1'b1}}, {10{1'b0}}},
slevel_w46c = {rad_ff45c[43:0], {3{1'b1}}, {9{1'b0}}},
slevel_w47c = {addnode_w46c[54:10], {3{1'b1}}, {8{1'b0}}},
slevel_w48c = {rad_ff47c[45:0], {3{1'b1}}, {7{1'b0}}},
slevel_w49c = {addnode_w48c[54:8], {3{1'b1}}, {6{1'b0}}},
slevel_w4c = {rad_ff3c[50:0], {5{1'b0}}},
slevel_w50c = {rad_ff49c[47:0], {3{1'b1}}, {5{1'b0}}},
slevel_w51c = {addnode_w50c[54:6], {3{1'b1}}, {4{1'b0}}},
slevel_w52c = {rad_ff51c[49:0], {3{1'b1}}, {3{1'b0}}},
slevel_w53c = {addnode_w52c[54:4], {3{1'b1}}, {2{1'b0}}},
slevel_w5c = {addnode_w4c[54:5], {6{1'b0}}},
slevel_w6c = {rad_ff5c[48:0], {7{1'b0}}},
slevel_w7c = {addnode_w6c[54:7], {8{1'b0}}},
slevel_w8c = {rad_ff7c[46:0], {9{1'b0}}},
slevel_w9c = {addnode_w8c[54:9], {10{1'b0}}};
endmodule //acl_fp_sqrt_double_alt_sqrt_block_1hb
//synthesis_resources = lpm_add_sub 56 reg 2983
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_double_altfp_sqrt_0dd
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] wire_alt_sqrt_block2_root_result;
reg exp_all_one_ff;
reg [10:0] exp_ff1;
reg [10:0] exp_ff20c;
reg [10:0] exp_ff210c;
reg [10:0] exp_ff211c;
reg [10:0] exp_ff212c;
reg [10:0] exp_ff213c;
reg [10:0] exp_ff214c;
reg [10:0] exp_ff215c;
reg [10:0] exp_ff216c;
reg [10:0] exp_ff217c;
reg [10:0] exp_ff218c;
reg [10:0] exp_ff219c;
reg [10:0] exp_ff21c;
reg [10:0] exp_ff220c;
reg [10:0] exp_ff221c;
reg [10:0] exp_ff222c;
reg [10:0] exp_ff223c;
reg [10:0] exp_ff224c;
reg [10:0] exp_ff225c;
reg [10:0] exp_ff226c;
reg [10:0] exp_ff22c;
reg [10:0] exp_ff23c;
reg [10:0] exp_ff24c;
reg [10:0] exp_ff25c;
reg [10:0] exp_ff26c;
reg [10:0] exp_ff27c;
reg [10:0] exp_ff28c;
reg [10:0] exp_ff29c;
reg [10:0] exp_in_ff;
reg exp_not_zero_ff;
reg [10:0] exp_result_ff;
reg [0:0] infinity_ff0;
reg [0:0] infinity_ff1;
reg [0:0] infinity_ff2;
reg [0:0] infinity_ff3;
reg [0:0] infinity_ff4;
reg [0:0] infinity_ff5;
reg [0:0] infinity_ff6;
reg [0:0] infinity_ff7;
reg [0:0] infinity_ff8;
reg [0:0] infinity_ff9;
reg [0:0] infinity_ff10;
reg [0:0] infinity_ff11;
reg [0:0] infinity_ff12;
reg [0:0] infinity_ff13;
reg [0:0] infinity_ff14;
reg [0:0] infinity_ff15;
reg [0:0] infinity_ff16;
reg [0:0] infinity_ff17;
reg [0:0] infinity_ff18;
reg [0:0] infinity_ff19;
reg [0:0] infinity_ff20;
reg [0:0] infinity_ff21;
reg [0:0] infinity_ff22;
reg [0:0] infinity_ff23;
reg [0:0] infinity_ff24;
reg [0:0] infinity_ff25;
reg [0:0] infinity_ff26;
reg [51:0] man_in_ff;
reg man_not_zero_ff;
reg [51:0] man_result_ff;
reg [51:0] man_rounding_ff;
reg [0:0] nan_man_ff0;
reg [0:0] nan_man_ff1;
reg [0:0] nan_man_ff2;
reg [0:0] nan_man_ff3;
reg [0:0] nan_man_ff4;
reg [0:0] nan_man_ff5;
reg [0:0] nan_man_ff6;
reg [0:0] nan_man_ff7;
reg [0:0] nan_man_ff8;
reg [0:0] nan_man_ff9;
reg [0:0] nan_man_ff10;
reg [0:0] nan_man_ff11;
reg [0:0] nan_man_ff12;
reg [0:0] nan_man_ff13;
reg [0:0] nan_man_ff14;
reg [0:0] nan_man_ff15;
reg [0:0] nan_man_ff16;
reg [0:0] nan_man_ff17;
reg [0:0] nan_man_ff18;
reg [0:0] nan_man_ff19;
reg [0:0] nan_man_ff20;
reg [0:0] nan_man_ff21;
reg [0:0] nan_man_ff22;
reg [0:0] nan_man_ff23;
reg [0:0] nan_man_ff24;
reg [0:0] nan_man_ff25;
reg [0:0] nan_man_ff26;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg [0:0] sign_node_ff10;
reg [0:0] sign_node_ff11;
reg [0:0] sign_node_ff12;
reg [0:0] sign_node_ff13;
reg [0:0] sign_node_ff14;
reg [0:0] sign_node_ff15;
reg [0:0] sign_node_ff16;
reg [0:0] sign_node_ff17;
reg [0:0] sign_node_ff18;
reg [0:0] sign_node_ff19;
reg [0:0] sign_node_ff20;
reg [0:0] sign_node_ff21;
reg [0:0] sign_node_ff22;
reg [0:0] sign_node_ff23;
reg [0:0] sign_node_ff24;
reg [0:0] sign_node_ff25;
reg [0:0] sign_node_ff26;
reg [0:0] sign_node_ff27;
reg [0:0] sign_node_ff28;
reg [0:0] sign_node_ff29;
reg [0:0] zero_exp_ff0;
reg [0:0] zero_exp_ff1;
reg [0:0] zero_exp_ff2;
reg [0:0] zero_exp_ff3;
reg [0:0] zero_exp_ff4;
reg [0:0] zero_exp_ff5;
reg [0:0] zero_exp_ff6;
reg [0:0] zero_exp_ff7;
reg [0:0] zero_exp_ff8;
reg [0:0] zero_exp_ff9;
reg [0:0] zero_exp_ff10;
reg [0:0] zero_exp_ff11;
reg [0:0] zero_exp_ff12;
reg [0:0] zero_exp_ff13;
reg [0:0] zero_exp_ff14;
reg [0:0] zero_exp_ff15;
reg [0:0] zero_exp_ff16;
reg [0:0] zero_exp_ff17;
reg [0:0] zero_exp_ff18;
reg [0:0] zero_exp_ff19;
reg [0:0] zero_exp_ff20;
reg [0:0] zero_exp_ff21;
reg [0:0] zero_exp_ff22;
reg [0:0] zero_exp_ff23;
reg [0:0] zero_exp_ff24;
reg [0:0] zero_exp_ff25;
reg [0:0] zero_exp_ff26;
wire [11:0] wire_add_sub1_result;
wire [51:0] wire_add_sub3_result;
wire aclr;
wire [10:0] bias;
wire [10:0] exp_all_one_w;
wire [10:0] exp_div_w;
wire [10:0] exp_ff2_w;
wire [10:0] exp_not_zero_w;
wire infinitycondition_w;
wire [51:0] man_not_zero_w;
wire [53:0] man_root_result_w;
wire nancondition_w;
wire preadjust_w;
wire [54:0] radicand_w;
wire roundbit_w;
acl_fp_sqrt_double_alt_sqrt_block_1hb alt_sqrt_block2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.rad(radicand_w),
.root_result(wire_alt_sqrt_block2_root_result));
// synopsys translate_off
initial
exp_all_one_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_all_one_ff <= 1'b0;
else if (clk_en == 1'b1) exp_all_one_ff <= exp_all_one_w[10];
// synopsys translate_off
initial
exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff1 <= 11'b0;
else if (clk_en == 1'b1) exp_ff1 <= exp_div_w;
// synopsys translate_off
initial
exp_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff20c <= 11'b0;
else if (clk_en == 1'b1) exp_ff20c <= exp_ff1;
// synopsys translate_off
initial
exp_ff210c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff210c <= 11'b0;
else if (clk_en == 1'b1) exp_ff210c <= exp_ff29c;
// synopsys translate_off
initial
exp_ff211c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff211c <= 11'b0;
else if (clk_en == 1'b1) exp_ff211c <= exp_ff210c;
// synopsys translate_off
initial
exp_ff212c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff212c <= 11'b0;
else if (clk_en == 1'b1) exp_ff212c <= exp_ff211c;
// synopsys translate_off
initial
exp_ff213c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff213c <= 11'b0;
else if (clk_en == 1'b1) exp_ff213c <= exp_ff212c;
// synopsys translate_off
initial
exp_ff214c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff214c <= 11'b0;
else if (clk_en == 1'b1) exp_ff214c <= exp_ff213c;
// synopsys translate_off
initial
exp_ff215c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff215c <= 11'b0;
else if (clk_en == 1'b1) exp_ff215c <= exp_ff214c;
// synopsys translate_off
initial
exp_ff216c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff216c <= 11'b0;
else if (clk_en == 1'b1) exp_ff216c <= exp_ff215c;
// synopsys translate_off
initial
exp_ff217c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff217c <= 11'b0;
else if (clk_en == 1'b1) exp_ff217c <= exp_ff216c;
// synopsys translate_off
initial
exp_ff218c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff218c <= 11'b0;
else if (clk_en == 1'b1) exp_ff218c <= exp_ff217c;
// synopsys translate_off
initial
exp_ff219c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff219c <= 11'b0;
else if (clk_en == 1'b1) exp_ff219c <= exp_ff218c;
// synopsys translate_off
initial
exp_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff21c <= 11'b0;
else if (clk_en == 1'b1) exp_ff21c <= exp_ff20c;
// synopsys translate_off
initial
exp_ff220c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff220c <= 11'b0;
else if (clk_en == 1'b1) exp_ff220c <= exp_ff219c;
// synopsys translate_off
initial
exp_ff221c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff221c <= 11'b0;
else if (clk_en == 1'b1) exp_ff221c <= exp_ff220c;
// synopsys translate_off
initial
exp_ff222c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff222c <= 11'b0;
else if (clk_en == 1'b1) exp_ff222c <= exp_ff221c;
// synopsys translate_off
initial
exp_ff223c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff223c <= 11'b0;
else if (clk_en == 1'b1) exp_ff223c <= exp_ff222c;
// synopsys translate_off
initial
exp_ff224c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff224c <= 11'b0;
else if (clk_en == 1'b1) exp_ff224c <= exp_ff223c;
// synopsys translate_off
initial
exp_ff225c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff225c <= 11'b0;
else if (clk_en == 1'b1) exp_ff225c <= exp_ff224c;
// synopsys translate_off
initial
exp_ff226c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff226c <= 11'b0;
else if (clk_en == 1'b1) exp_ff226c <= exp_ff225c;
// synopsys translate_off
initial
exp_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff22c <= 11'b0;
else if (clk_en == 1'b1) exp_ff22c <= exp_ff21c;
// synopsys translate_off
initial
exp_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff23c <= 11'b0;
else if (clk_en == 1'b1) exp_ff23c <= exp_ff22c;
// synopsys translate_off
initial
exp_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff24c <= 11'b0;
else if (clk_en == 1'b1) exp_ff24c <= exp_ff23c;
// synopsys translate_off
initial
exp_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff25c <= 11'b0;
else if (clk_en == 1'b1) exp_ff25c <= exp_ff24c;
// synopsys translate_off
initial
exp_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff26c <= 11'b0;
else if (clk_en == 1'b1) exp_ff26c <= exp_ff25c;
// synopsys translate_off
initial
exp_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff27c <= 11'b0;
else if (clk_en == 1'b1) exp_ff27c <= exp_ff26c;
// synopsys translate_off
initial
exp_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff28c <= 11'b0;
else if (clk_en == 1'b1) exp_ff28c <= exp_ff27c;
// synopsys translate_off
initial
exp_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff29c <= 11'b0;
else if (clk_en == 1'b1) exp_ff29c <= exp_ff28c;
// synopsys translate_off
initial
exp_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_in_ff <= 11'b0;
else if (clk_en == 1'b1) exp_in_ff <= data[62:52];
// synopsys translate_off
initial
exp_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) exp_not_zero_ff <= exp_not_zero_w[10];
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= (((exp_ff2_w & {11{zero_exp_ff26[0:0]}}) | {11{nan_man_ff26[0:0]}}) | {11{infinity_ff26[0:0]}});
// synopsys translate_off
initial
infinity_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff0 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff0 <= (infinitycondition_w & (~ sign_node_ff1[0:0]));
// synopsys translate_off
initial
infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff1 <= infinity_ff0[0:0];
// synopsys translate_off
initial
infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff2 <= infinity_ff1[0:0];
// synopsys translate_off
initial
infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff3 <= infinity_ff2[0:0];
// synopsys translate_off
initial
infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff4 <= infinity_ff3[0:0];
// synopsys translate_off
initial
infinity_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff5 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff5 <= infinity_ff4[0:0];
// synopsys translate_off
initial
infinity_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff6 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff6 <= infinity_ff5[0:0];
// synopsys translate_off
initial
infinity_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff7 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff7 <= infinity_ff6[0:0];
// synopsys translate_off
initial
infinity_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff8 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff8 <= infinity_ff7[0:0];
// synopsys translate_off
initial
infinity_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff9 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff9 <= infinity_ff8[0:0];
// synopsys translate_off
initial
infinity_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff10 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff10 <= infinity_ff9[0:0];
// synopsys translate_off
initial
infinity_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff11 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff11 <= infinity_ff10[0:0];
// synopsys translate_off
initial
infinity_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff12 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff12 <= infinity_ff11[0:0];
// synopsys translate_off
initial
infinity_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff13 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff13 <= infinity_ff12[0:0];
// synopsys translate_off
initial
infinity_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff14 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff14 <= infinity_ff13[0:0];
// synopsys translate_off
initial
infinity_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff15 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff15 <= infinity_ff14[0:0];
// synopsys translate_off
initial
infinity_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff16 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff16 <= infinity_ff15[0:0];
// synopsys translate_off
initial
infinity_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff17 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff17 <= infinity_ff16[0:0];
// synopsys translate_off
initial
infinity_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff18 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff18 <= infinity_ff17[0:0];
// synopsys translate_off
initial
infinity_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff19 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff19 <= infinity_ff18[0:0];
// synopsys translate_off
initial
infinity_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff20 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff20 <= infinity_ff19[0:0];
// synopsys translate_off
initial
infinity_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff21 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff21 <= infinity_ff20[0:0];
// synopsys translate_off
initial
infinity_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff22 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff22 <= infinity_ff21[0:0];
// synopsys translate_off
initial
infinity_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff23 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff23 <= infinity_ff22[0:0];
// synopsys translate_off
initial
infinity_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff24 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff24 <= infinity_ff23[0:0];
// synopsys translate_off
initial
infinity_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff25 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff25 <= infinity_ff24[0:0];
// synopsys translate_off
initial
infinity_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff26 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff26 <= infinity_ff25[0:0];
// synopsys translate_off
initial
man_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_in_ff <= 52'b0;
else if (clk_en == 1'b1) man_in_ff <= data[51:0];
// synopsys translate_off
initial
man_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) man_not_zero_ff <= man_not_zero_w[51];
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= ((man_rounding_ff & {52{zero_exp_ff26[0:0]}}) | {52{nan_man_ff26[0:0]}});
// synopsys translate_off
initial
man_rounding_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_rounding_ff <= 52'b0;
else if (clk_en == 1'b1) man_rounding_ff <= wire_add_sub3_result;
// synopsys translate_off
initial
nan_man_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff0 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff0 <= nancondition_w;
// synopsys translate_off
initial
nan_man_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff1 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff1 <= nan_man_ff0[0:0];
// synopsys translate_off
initial
nan_man_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff2 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff2 <= nan_man_ff1[0:0];
// synopsys translate_off
initial
nan_man_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff3 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff3 <= nan_man_ff2[0:0];
// synopsys translate_off
initial
nan_man_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff4 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff4 <= nan_man_ff3[0:0];
// synopsys translate_off
initial
nan_man_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff5 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff5 <= nan_man_ff4[0:0];
// synopsys translate_off
initial
nan_man_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff6 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff6 <= nan_man_ff5[0:0];
// synopsys translate_off
initial
nan_man_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff7 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff7 <= nan_man_ff6[0:0];
// synopsys translate_off
initial
nan_man_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff8 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff8 <= nan_man_ff7[0:0];
// synopsys translate_off
initial
nan_man_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff9 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff9 <= nan_man_ff8[0:0];
// synopsys translate_off
initial
nan_man_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff10 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff10 <= nan_man_ff9[0:0];
// synopsys translate_off
initial
nan_man_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff11 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff11 <= nan_man_ff10[0:0];
// synopsys translate_off
initial
nan_man_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff12 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff12 <= nan_man_ff11[0:0];
// synopsys translate_off
initial
nan_man_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff13 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff13 <= nan_man_ff12[0:0];
// synopsys translate_off
initial
nan_man_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff14 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff14 <= nan_man_ff13[0:0];
// synopsys translate_off
initial
nan_man_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff15 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff15 <= nan_man_ff14[0:0];
// synopsys translate_off
initial
nan_man_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff16 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff16 <= nan_man_ff15[0:0];
// synopsys translate_off
initial
nan_man_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff17 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff17 <= nan_man_ff16[0:0];
// synopsys translate_off
initial
nan_man_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff18 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff18 <= nan_man_ff17[0:0];
// synopsys translate_off
initial
nan_man_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff19 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff19 <= nan_man_ff18[0:0];
// synopsys translate_off
initial
nan_man_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff20 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff20 <= nan_man_ff19[0:0];
// synopsys translate_off
initial
nan_man_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff21 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff21 <= nan_man_ff20[0:0];
// synopsys translate_off
initial
nan_man_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff22 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff22 <= nan_man_ff21[0:0];
// synopsys translate_off
initial
nan_man_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff23 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff23 <= nan_man_ff22[0:0];
// synopsys translate_off
initial
nan_man_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff24 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff24 <= nan_man_ff23[0:0];
// synopsys translate_off
initial
nan_man_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff25 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff25 <= nan_man_ff24[0:0];
// synopsys translate_off
initial
nan_man_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff26 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff26 <= nan_man_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= data[63];
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sign_node_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff10 <= sign_node_ff9[0:0];
// synopsys translate_off
initial
sign_node_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff11 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff11 <= sign_node_ff10[0:0];
// synopsys translate_off
initial
sign_node_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff12 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff12 <= sign_node_ff11[0:0];
// synopsys translate_off
initial
sign_node_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff13 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff13 <= sign_node_ff12[0:0];
// synopsys translate_off
initial
sign_node_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff14 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff14 <= sign_node_ff13[0:0];
// synopsys translate_off
initial
sign_node_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff15 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff15 <= sign_node_ff14[0:0];
// synopsys translate_off
initial
sign_node_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff16 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff16 <= sign_node_ff15[0:0];
// synopsys translate_off
initial
sign_node_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff17 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff17 <= sign_node_ff16[0:0];
// synopsys translate_off
initial
sign_node_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff18 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff18 <= sign_node_ff17[0:0];
// synopsys translate_off
initial
sign_node_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff19 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff19 <= sign_node_ff18[0:0];
// synopsys translate_off
initial
sign_node_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff20 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff20 <= sign_node_ff19[0:0];
// synopsys translate_off
initial
sign_node_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff21 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff21 <= sign_node_ff20[0:0];
// synopsys translate_off
initial
sign_node_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff22 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff22 <= sign_node_ff21[0:0];
// synopsys translate_off
initial
sign_node_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff23 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff23 <= sign_node_ff22[0:0];
// synopsys translate_off
initial
sign_node_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff24 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff24 <= sign_node_ff23[0:0];
// synopsys translate_off
initial
sign_node_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff25 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff25 <= sign_node_ff24[0:0];
// synopsys translate_off
initial
sign_node_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff26 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff26 <= sign_node_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff27 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff27 <= sign_node_ff26[0:0];
// synopsys translate_off
initial
sign_node_ff28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff28 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff28 <= sign_node_ff27[0:0];
// synopsys translate_off
initial
sign_node_ff29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff29 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff29 <= sign_node_ff28[0:0];
// synopsys translate_off
initial
zero_exp_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff0 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff0 <= exp_not_zero_ff;
// synopsys translate_off
initial
zero_exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff1 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff1 <= zero_exp_ff0[0:0];
// synopsys translate_off
initial
zero_exp_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff2 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff2 <= zero_exp_ff1[0:0];
// synopsys translate_off
initial
zero_exp_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff3 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff3 <= zero_exp_ff2[0:0];
// synopsys translate_off
initial
zero_exp_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff4 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff4 <= zero_exp_ff3[0:0];
// synopsys translate_off
initial
zero_exp_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff5 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff5 <= zero_exp_ff4[0:0];
// synopsys translate_off
initial
zero_exp_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff6 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff6 <= zero_exp_ff5[0:0];
// synopsys translate_off
initial
zero_exp_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff7 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff7 <= zero_exp_ff6[0:0];
// synopsys translate_off
initial
zero_exp_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff8 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff8 <= zero_exp_ff7[0:0];
// synopsys translate_off
initial
zero_exp_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff9 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff9 <= zero_exp_ff8[0:0];
// synopsys translate_off
initial
zero_exp_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff10 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff10 <= zero_exp_ff9[0:0];
// synopsys translate_off
initial
zero_exp_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff11 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff11 <= zero_exp_ff10[0:0];
// synopsys translate_off
initial
zero_exp_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff12 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff12 <= zero_exp_ff11[0:0];
// synopsys translate_off
initial
zero_exp_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff13 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff13 <= zero_exp_ff12[0:0];
// synopsys translate_off
initial
zero_exp_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff14 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff14 <= zero_exp_ff13[0:0];
// synopsys translate_off
initial
zero_exp_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff15 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff15 <= zero_exp_ff14[0:0];
// synopsys translate_off
initial
zero_exp_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff16 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff16 <= zero_exp_ff15[0:0];
// synopsys translate_off
initial
zero_exp_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff17 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff17 <= zero_exp_ff16[0:0];
// synopsys translate_off
initial
zero_exp_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff18 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff18 <= zero_exp_ff17[0:0];
// synopsys translate_off
initial
zero_exp_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff19 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff19 <= zero_exp_ff18[0:0];
// synopsys translate_off
initial
zero_exp_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff20 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff20 <= zero_exp_ff19[0:0];
// synopsys translate_off
initial
zero_exp_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff21 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff21 <= zero_exp_ff20[0:0];
// synopsys translate_off
initial
zero_exp_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff22 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff22 <= zero_exp_ff21[0:0];
// synopsys translate_off
initial
zero_exp_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff23 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff23 <= zero_exp_ff22[0:0];
// synopsys translate_off
initial
zero_exp_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff24 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff24 <= zero_exp_ff23[0:0];
// synopsys translate_off
initial
zero_exp_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff25 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff25 <= zero_exp_ff24[0:0];
// synopsys translate_off
initial
zero_exp_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff26 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff26 <= zero_exp_ff25[0:0];
lpm_add_sub add_sub1
(
.cout(),
.dataa({1'b0, exp_in_ff}),
.datab({1'b0, bias}),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_pipeline = 0,
add_sub1.lpm_width = 12,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(man_root_result_w[52:1]),
.datab({{51{1'b0}}, roundbit_w}),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "ADD",
add_sub3.lpm_pipeline = 0,
add_sub3.lpm_width = 52,
add_sub3.lpm_type = "lpm_add_sub";
assign
aclr = 1'b0,
bias = {1'b0, {10{1'b1}}},
exp_all_one_w = {(exp_in_ff[10] & exp_all_one_w[9]), (exp_in_ff[9] & exp_all_one_w[8]), (exp_in_ff[8] & exp_all_one_w[7]), (exp_in_ff[7] & exp_all_one_w[6]), (exp_in_ff[6] & exp_all_one_w[5]), (exp_in_ff[5] & exp_all_one_w[4]), (exp_in_ff[4] & exp_all_one_w[3]), (exp_in_ff[3] & exp_all_one_w[2]), (exp_in_ff[2] & exp_all_one_w[1]), (exp_in_ff[1] & exp_all_one_w[0]), exp_in_ff[0]},
exp_div_w = {wire_add_sub1_result[11:1]},
exp_ff2_w = exp_ff226c,
exp_not_zero_w = {(exp_in_ff[10] | exp_not_zero_w[9]), (exp_in_ff[9] | exp_not_zero_w[8]), (exp_in_ff[8] | exp_not_zero_w[7]), (exp_in_ff[7] | exp_not_zero_w[6]), (exp_in_ff[6] | exp_not_zero_w[5]), (exp_in_ff[5] | exp_not_zero_w[4]), (exp_in_ff[4] | exp_not_zero_w[3]), (exp_in_ff[3] | exp_not_zero_w[2]), (exp_in_ff[2] | exp_not_zero_w[1]), (exp_in_ff[1] | exp_not_zero_w[0]), exp_in_ff[0]},
infinitycondition_w = ((~ man_not_zero_ff) & exp_all_one_ff),
man_not_zero_w = {(man_in_ff[51] | man_not_zero_w[50]), (man_in_ff[50] | man_not_zero_w[49]), (man_in_ff[49] | man_not_zero_w[48]), (man_in_ff[48] | man_not_zero_w[47]), (man_in_ff[47] | man_not_zero_w[46]), (man_in_ff[46] | man_not_zero_w[45]), (man_in_ff[45] | man_not_zero_w[44]), (man_in_ff[44] | man_not_zero_w[43]), (man_in_ff[43] | man_not_zero_w[42]), (man_in_ff[42] | man_not_zero_w[41]), (man_in_ff[41] | man_not_zero_w[40]), (man_in_ff[40] | man_not_zero_w[39]), (man_in_ff[39] | man_not_zero_w[38]), (man_in_ff[38] | man_not_zero_w[37]), (man_in_ff[37] | man_not_zero_w[36]), (man_in_ff[36] | man_not_zero_w[35]), (man_in_ff[35] | man_not_zero_w[34]), (man_in_ff[34] | man_not_zero_w[33]), (man_in_ff[33] | man_not_zero_w[32]), (man_in_ff[32] | man_not_zero_w[31]), (man_in_ff[31] | man_not_zero_w[30]), (man_in_ff[30] | man_not_zero_w[29]), (man_in_ff[29] | man_not_zero_w[28]), (man_in_ff[28] | man_not_zero_w[27]), (man_in_ff[27] | man_not_zero_w[26]), (man_in_ff[26] | man_not_zero_w[25]), (man_in_ff[25] | man_not_zero_w[24]), (man_in_ff[24] | man_not_zero_w[23]), (man_in_ff[23] | man_not_zero_w[22]), (man_in_ff[22] | man_not_zero_w[21]), (man_in_ff[21] | man_not_zero_w[20]), (man_in_ff[20] | man_not_zero_w[19]), (man_in_ff[19] | man_not_zero_w[18]), (man_in_ff[18] | man_not_zero_w[17]), (man_in_ff[17] | man_not_zero_w[16]), (man_in_ff[16] | man_not_zero_w[15]), (man_in_ff[15] | man_not_zero_w[14]), (man_in_ff[14] | man_not_zero_w[13]), (man_in_ff[13] | man_not_zero_w[12]), (man_in_ff[12] | man_not_zero_w[11]), (man_in_ff[11] | man_not_zero_w[10]), (man_in_ff[10] | man_not_zero_w[9]), (man_in_ff[9] | man_not_zero_w[8]), (man_in_ff[8] | man_not_zero_w[7]), (man_in_ff[7] | man_not_zero_w[6]), (man_in_ff[6] | man_not_zero_w[5]), (man_in_ff[5] | man_not_zero_w[4]), (man_in_ff[4] | man_not_zero_w[3]), (man_in_ff[3] | man_not_zero_w[2]), (man_in_ff[2] | man_not_zero_w[1]), (man_in_ff[1] | man_not_zero_w[0]), man_in_ff[0]},
man_root_result_w = wire_alt_sqrt_block2_root_result,
nancondition_w = ((sign_node_ff1[0:0] & exp_not_zero_ff) | (exp_all_one_ff & man_not_zero_ff)),
preadjust_w = exp_in_ff[0],
radicand_w = {(~ preadjust_w), (preadjust_w | (man_in_ff[51] & (~ preadjust_w))), ((man_in_ff[51:1] & {51{preadjust_w}}) | (man_in_ff[50:0] & {51{(~ preadjust_w)}})), (man_in_ff[0] & preadjust_w), 1'b0},
result = {sign_node_ff29[0:0], exp_result_ff, man_result_ff},
roundbit_w = wire_alt_sqrt_block2_root_result[0];
endmodule //acl_fp_sqrt_double_altfp_sqrt_0dd
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sqrt_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_sqrt_double_altfp_sqrt_0dd acl_fp_sqrt_double_altfp_sqrt_0dd_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "30"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_double_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_BNC_P_read_AW30h for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_BNC_P_read_AW30h
// Module Name: NPCG_Toggle_BNC_P_read_AW30h
// File Name: NPCG_Toggle_BNC_P_read_AW30h.v
//
// Version: v1.0.0
//
// Description: Page read trigger FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_BNC_P_read_AW30h
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
iColAddress ,
iRowAddress ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
input [15:0] iColAddress ;
input [23:0] iRowAddress ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
reg [NumberOfWays - 1:0] rTargetWay ;
reg [15:0] rColAddress ;
reg [23:0] rRowAddress ;
wire wModuleTriggered;
wire wTMStart ;
reg [7:0] rPMTrigger ;
reg [2:0] rPCommandOption ;
reg [15:0] rNumOfData ;
reg [7:0] rCAData ;
reg rPMCommandOrAddress ;
localparam State_Idle = 4'b0000 ;
localparam State_NCALIssue = 4'b0001 ;
localparam State_NCmdWrite0 = 4'b0011 ;
localparam State_NAddrWrite0 = 4'b0010 ;
localparam State_NAddrWrite1 = 4'b0110 ;
localparam State_NAddrWrite2 = 4'b0111 ;
localparam State_NAddrWrite3 = 4'b0101 ;
localparam State_NAddrWrite4 = 4'b0100 ;
localparam State_NCmdWrite1 = 4'b1100 ;
localparam State_NTMIssue = 4'b1101 ;
localparam State_WaitDone = 4'b1111 ;
reg [3:0] rCurState ;
reg [3:0] rNextState ;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_NCALIssue:State_Idle;
State_NCALIssue:
rNextState <= (iPM_Ready)?State_NCmdWrite0:State_NCALIssue;
State_NCmdWrite0:
rNextState <= State_NAddrWrite0;
State_NAddrWrite0:
rNextState <= State_NAddrWrite1;
State_NAddrWrite1:
rNextState <= State_NAddrWrite2;
State_NAddrWrite2:
rNextState <= State_NAddrWrite3;
State_NAddrWrite3:
rNextState <= State_NAddrWrite4;
State_NAddrWrite4:
rNextState <= State_NCmdWrite1;
State_NCmdWrite1:
rNextState <= State_NTMIssue;
State_NTMIssue:
rNextState <= (wTMStart)?State_WaitDone:State_NTMIssue;
State_WaitDone:
rNextState <= (oLastStep)?State_Idle:State_WaitDone;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b000000);
assign wTMStart = (rCurState == State_NTMIssue) & iPM_LastStep[3];
assign oCMDReady = (rCurState == State_Idle);
always @ (posedge iSystemClock)
if (iReset)
begin
rTargetWay <= {(NumberOfWays){1'b0}};
rColAddress <= 16'b0;
rRowAddress <= 24'b0;
end
else
if (wModuleTriggered && (rCurState == State_Idle))
begin
rTargetWay <= iWaySelect ;
rColAddress <= iColAddress ;
rRowAddress <= iRowAddress ;
end
always @ (*)
case (rCurState)
State_NCALIssue:
rPMTrigger <= 8'b00001000;
State_NTMIssue:
rPMTrigger <= 8'b00000001;
default:
rPMTrigger <= 0;
endcase
always @ (*)
case (rCurState)
State_NTMIssue:
rPCommandOption[2:0] <= 3'b110;
default:
rPCommandOption[2:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCALIssue:
rNumOfData[15:0] <= 16'd6; // 1 cmd + 5 addr + 1 cmd = 7 (=> 6)
State_NTMIssue:
rNumOfData[15:0] <= 16'd3; // 40 ns
default:
rNumOfData[15:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCmdWrite0:
rPMCommandOrAddress <= 1'b0;
State_NCmdWrite1:
rPMCommandOrAddress <= 1'b0;
State_NAddrWrite0:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite1:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite2:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite3:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite4:
rPMCommandOrAddress <= 1'b1;
default:
rPMCommandOrAddress <= 1'b0;
endcase
always @ (posedge iSystemClock)
if (iReset)
rCAData <= 0;
else
case (rNextState)
State_NCmdWrite0:
rCAData <= 8'h00;
State_NAddrWrite0:
rCAData <= rColAddress[7:0];
State_NAddrWrite1:
rCAData <= rColAddress[15:8];
State_NAddrWrite2:
rCAData <= rRowAddress[7:0];
State_NAddrWrite3:
rCAData <= rRowAddress[15:8];
State_NAddrWrite4:
rCAData <= rRowAddress[23:16];
State_NCmdWrite1:
rCAData <= 8'h30;
default:
rCAData <= 0;
endcase
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_WaitDone) & iPM_LastStep[0];
assign oPM_PCommand = rPMTrigger;
assign oPM_PCommandOption = rPCommandOption;//1'b0;
assign oPM_TargetWay = rTargetWay;
assign oPM_NumOfData = rNumOfData; //16'd6;
assign oPM_CASelect = rPMCommandOrAddress;
assign oPM_CAData = rCAData;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "simulation_includes.vh"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
//`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h00000035); //115200bps from 100 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, {24'h000000, char});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!`testbench.uart0_int)
@(posedge `testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h0, `testbench.read_word);
$display("TASK: UART Read = %c @ %d", `testbench.read_word, $time);
if (`testbench.read_word != expected)
begin
$display("FAIL: UART Read = 0x%h NOT 0x%h @ %d", `testbench.read_word[7:0], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge `testbench.clk);
end
endtask // uart_read_char
endmodule // uart_tasks
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}" *)
module sin_taylor_series (
x,
ap_clk,
ap_rst,
ap_return,
ap_done,
ap_start,
ap_ready,
ap_idle
);
input [63:0] x;
input ap_clk;
input ap_rst;
output [63:0] ap_return;
output ap_done;
input ap_start;
output ap_ready;
output ap_idle;
wire Loop_sum_loop_proc_U0_ap_start;
wire Loop_sum_loop_proc_U0_ap_done;
wire Loop_sum_loop_proc_U0_ap_continue;
wire Loop_sum_loop_proc_U0_ap_idle;
wire Loop_sum_loop_proc_U0_ap_ready;
wire [63:0] Loop_sum_loop_proc_U0_ap_return_0;
wire [63:0] Loop_sum_loop_proc_U0_ap_return_1;
wire ap_channel_done_sum_negative_0_loc_l;
wire sum_negative_0_loc_l_full_n;
reg ap_sync_reg_channel_write_sum_negative_0_loc_l;
wire ap_sync_channel_write_sum_negative_0_loc_l;
wire ap_channel_done_sum_positive_0_loc_l;
wire sum_positive_0_loc_l_full_n;
reg ap_sync_reg_channel_write_sum_positive_0_loc_l;
wire ap_sync_channel_write_sum_positive_0_loc_l;
wire Block_sin_taylor_ser_U0_ap_start;
wire Block_sin_taylor_ser_U0_ap_done;
wire Block_sin_taylor_ser_U0_ap_continue;
wire Block_sin_taylor_ser_U0_ap_idle;
wire Block_sin_taylor_ser_U0_ap_ready;
wire [63:0] Block_sin_taylor_ser_U0_ap_return;
wire ap_channel_done_tmp_loc_channel;
wire tmp_loc_channel_full_n;
wire p_source_files_sr_U0_ap_start;
wire p_source_files_sr_U0_ap_done;
wire p_source_files_sr_U0_ap_continue;
wire p_source_files_sr_U0_ap_idle;
wire p_source_files_sr_U0_ap_ready;
wire [63:0] p_source_files_sr_U0_ap_return;
wire [63:0] tmp_p_source_files_sr_fu_42_ap_return;
wire ap_sync_continue;
wire [63:0] sum_positive_0_loc_l_dout;
wire sum_positive_0_loc_l_empty_n;
wire [63:0] sum_negative_0_loc_l_dout;
wire sum_negative_0_loc_l_empty_n;
wire [63:0] tmp_loc_channel_dout;
wire tmp_loc_channel_empty_n;
wire ap_sync_done;
wire ap_sync_ready;
wire Loop_sum_loop_proc_U0_start_full_n;
wire Loop_sum_loop_proc_U0_start_write;
wire Block_sin_taylor_ser_U0_start_full_n;
wire Block_sin_taylor_ser_U0_start_write;
wire p_source_files_sr_U0_start_full_n;
wire p_source_files_sr_U0_start_write;
// power-on initialization
initial begin
#0 ap_sync_reg_channel_write_sum_negative_0_loc_l = 1'b0;
#0 ap_sync_reg_channel_write_sum_positive_0_loc_l = 1'b0;
end
Loop_sum_loop_proc Loop_sum_loop_proc_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(Loop_sum_loop_proc_U0_ap_start),
.ap_done(Loop_sum_loop_proc_U0_ap_done),
.ap_continue(Loop_sum_loop_proc_U0_ap_continue),
.ap_idle(Loop_sum_loop_proc_U0_ap_idle),
.ap_ready(Loop_sum_loop_proc_U0_ap_ready),
.x(x),
.ap_return_0(Loop_sum_loop_proc_U0_ap_return_0),
.ap_return_1(Loop_sum_loop_proc_U0_ap_return_1)
);
Block_sin_taylor_ser Block_sin_taylor_ser_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(Block_sin_taylor_ser_U0_ap_start),
.ap_done(Block_sin_taylor_ser_U0_ap_done),
.ap_continue(Block_sin_taylor_ser_U0_ap_continue),
.ap_idle(Block_sin_taylor_ser_U0_ap_idle),
.ap_ready(Block_sin_taylor_ser_U0_ap_ready),
.p_read(sum_positive_0_loc_l_dout),
.p_read1(sum_negative_0_loc_l_dout),
.ap_return(Block_sin_taylor_ser_U0_ap_return)
);
p_source_files_sr p_source_files_sr_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(p_source_files_sr_U0_ap_start),
.ap_done(p_source_files_sr_U0_ap_done),
.ap_continue(p_source_files_sr_U0_ap_continue),
.ap_idle(p_source_files_sr_U0_ap_idle),
.ap_ready(p_source_files_sr_U0_ap_ready),
.p_read(tmp_loc_channel_dout),
.ap_return(p_source_files_sr_U0_ap_return)
);
fifo_w64_d2_A sum_positive_0_loc_l_U(
.clk(ap_clk),
.reset(ap_rst),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_sum_loop_proc_U0_ap_return_0),
.if_full_n(sum_positive_0_loc_l_full_n),
.if_write(ap_channel_done_sum_positive_0_loc_l),
.if_dout(sum_positive_0_loc_l_dout),
.if_empty_n(sum_positive_0_loc_l_empty_n),
.if_read(Block_sin_taylor_ser_U0_ap_ready)
);
fifo_w64_d2_A sum_negative_0_loc_l_U(
.clk(ap_clk),
.reset(ap_rst),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_sum_loop_proc_U0_ap_return_1),
.if_full_n(sum_negative_0_loc_l_full_n),
.if_write(ap_channel_done_sum_negative_0_loc_l),
.if_dout(sum_negative_0_loc_l_dout),
.if_empty_n(sum_negative_0_loc_l_empty_n),
.if_read(Block_sin_taylor_ser_U0_ap_ready)
);
fifo_w64_d2_A tmp_loc_channel_U(
.clk(ap_clk),
.reset(ap_rst),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_sin_taylor_ser_U0_ap_return),
.if_full_n(tmp_loc_channel_full_n),
.if_write(Block_sin_taylor_ser_U0_ap_done),
.if_dout(tmp_loc_channel_dout),
.if_empty_n(tmp_loc_channel_empty_n),
.if_read(p_source_files_sr_U0_ap_ready)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_sync_reg_channel_write_sum_negative_0_loc_l <= 1'b0;
end else begin
if ((1'b1 == (Loop_sum_loop_proc_U0_ap_done & Loop_sum_loop_proc_U0_ap_continue))) begin
ap_sync_reg_channel_write_sum_negative_0_loc_l <= 1'b0;
end else begin
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_sync_reg_channel_write_sum_positive_0_loc_l <= 1'b0;
end else begin
if ((1'b1 == (Loop_sum_loop_proc_U0_ap_done & Loop_sum_loop_proc_U0_ap_continue))) begin
ap_sync_reg_channel_write_sum_positive_0_loc_l <= 1'b0;
end else begin
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end
end
end
assign Block_sin_taylor_ser_U0_ap_continue = tmp_loc_channel_full_n;
assign Block_sin_taylor_ser_U0_ap_start = (sum_positive_0_loc_l_empty_n & sum_negative_0_loc_l_empty_n);
assign Block_sin_taylor_ser_U0_start_full_n = 1'b0;
assign Block_sin_taylor_ser_U0_start_write = 1'b0;
assign Loop_sum_loop_proc_U0_ap_continue = (ap_sync_channel_write_sum_negative_0_loc_l & ap_sync_channel_write_sum_positive_0_loc_l);
assign Loop_sum_loop_proc_U0_ap_start = ap_start;
assign Loop_sum_loop_proc_U0_start_full_n = 1'b0;
assign Loop_sum_loop_proc_U0_start_write = 1'b0;
assign ap_channel_done_sum_negative_0_loc_l = (Loop_sum_loop_proc_U0_ap_done & (ap_sync_reg_channel_write_sum_negative_0_loc_l ^ 1'b1));
assign ap_channel_done_sum_positive_0_loc_l = (Loop_sum_loop_proc_U0_ap_done & (ap_sync_reg_channel_write_sum_positive_0_loc_l ^ 1'b1));
assign ap_channel_done_tmp_loc_channel = Block_sin_taylor_ser_U0_ap_done;
assign ap_done = p_source_files_sr_U0_ap_done;
assign ap_idle = (Loop_sum_loop_proc_U0_ap_idle & Block_sin_taylor_ser_U0_ap_idle & p_source_files_sr_U0_ap_idle & (sum_positive_0_loc_l_empty_n ^ 1'b1) & (sum_negative_0_loc_l_empty_n ^ 1'b1) & (tmp_loc_channel_empty_n ^ 1'b1));
assign ap_ready = Loop_sum_loop_proc_U0_ap_ready;
assign ap_return = p_source_files_sr_U0_ap_return;
assign ap_sync_channel_write_sum_negative_0_loc_l = ((ap_channel_done_sum_negative_0_loc_l & sum_negative_0_loc_l_full_n) | ap_sync_reg_channel_write_sum_negative_0_loc_l);
assign ap_sync_channel_write_sum_positive_0_loc_l = ((ap_channel_done_sum_positive_0_loc_l & sum_positive_0_loc_l_full_n) | ap_sync_reg_channel_write_sum_positive_0_loc_l);
assign ap_sync_continue = 1'b1;
assign ap_sync_done = p_source_files_sr_U0_ap_done;
assign ap_sync_ready = Loop_sum_loop_proc_U0_ap_ready;
assign p_source_files_sr_U0_ap_continue = 1'b1;
assign p_source_files_sr_U0_ap_start = tmp_loc_channel_empty_n;
assign p_source_files_sr_U0_start_full_n = 1'b0;
assign p_source_files_sr_U0_start_write = 1'b0;
assign tmp_p_source_files_sr_fu_42_ap_return = 64'd0;
endmodule //sin_taylor_series
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sd_spi
(input clk,
input rst,
// SD Card interface
output reg sd_clk,
output sd_mosi,
input sd_miso,
// Controls
input [7:0] clk_div,
input [7:0] send_dat,
output [7:0] rcv_dat,
input go,
output ready);
reg [7:0] clk_ctr;
reg [3:0] bit_ctr;
wire bit_ready = (clk_ctr == 8'd0);
wire bit_busy = (clk_ctr != 8'd0);
wire bit_done = (clk_ctr == clk_div);
wire send_clk_hi = (clk_ctr == (clk_div>>1));
wire latch_dat = (clk_ctr == (clk_div - 8'd2));
wire send_clk_lo = (clk_ctr == (clk_div - 8'd1));
wire send_bit = (bit_ready && (bit_ctr != 0));
assign ready = (bit_ctr == 0);
always @(posedge clk)
if(rst)
clk_ctr <= 0;
else if(bit_done)
clk_ctr <= 0;
else if(bit_busy)
clk_ctr <= clk_ctr + 1;
else if(send_bit)
clk_ctr <= 1;
always @(posedge clk)
if(rst)
sd_clk <= 0;
else if(send_clk_hi)
sd_clk <= 1;
else if(send_clk_lo)
sd_clk <= 0;
always @(posedge clk)
if(rst)
bit_ctr <= 0;
else if(bit_done)
if(bit_ctr == 4'd8)
bit_ctr <= 0;
else
bit_ctr <= bit_ctr + 1;
else if(bit_ready & go)
bit_ctr <= 1;
reg [7:0] shift_reg;
always @(posedge clk)
if(go)
shift_reg <= send_dat;
else if(latch_dat)
shift_reg <= {shift_reg[6:0],sd_miso};
assign sd_mosi = shift_reg[7];
assign rcv_dat = shift_reg;
endmodule // sd_spi
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pm(/*AUTOARG*/
// Outputs
pcx_spc_grant_bufpm_pa, pcx_stall_bufpm_pq,
// Inputs
pcx_spc_grant_pa, pcx_stall_pq
);
output [4:0] pcx_spc_grant_bufpm_pa;
output pcx_stall_bufpm_pq;
input [4:0] pcx_spc_grant_pa;
input pcx_stall_pq;
assign pcx_spc_grant_bufpm_pa = pcx_spc_grant_pa;
assign pcx_stall_bufpm_pq = pcx_stall_pq;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux using MUXF7/8.
// Any generic_baseblocks_v2_1_mux ratio.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// mux_enc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [16 - 1 : 0] a;
input [16 - 1 : 0] b;
output [16 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [16 - 1 : 0] a_reg;
wire [16 - 1 : 0] b_reg;
// wires for each small adder
wire [4 - 1 : 0] a0_cb;
wire [4 - 1 : 0] b0_cb;
wire [8 - 1 : 4] a1_cb;
wire [8 - 1 : 4] b1_cb;
wire [12 - 1 : 8] a2_cb;
wire [12 - 1 : 8] b2_cb;
wire [16 - 1 : 12] a3_cb;
wire [16 - 1 : 12] b3_cb;
// registers for input register array
reg [4 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
// wires for each full adder sum
wire [16 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
// registers for output register array
reg [4 - 1 : 0] s0_ca_rego0[2 - 0 : 0];
reg [4 - 1 : 0] s1_ca_rego1[2 - 1 : 0];
reg [4 - 1 : 0] s2_ca_rego2[2 - 2 : 0];
// wire for the temporary output
wire [16 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[4 - 1 : 0];
assign b0_cb = b_reg[4 - 1 : 0];
assign a1_cb = a_reg[8 - 1 : 4];
assign b1_cb = b_reg[8 - 1 : 4];
assign a2_cb = a_reg[12 - 1 : 8];
assign b2_cb = b_reg[12 - 1 : 8];
assign a3_cb = a_reg[16 - 1 : 12];
assign b3_cb = b_reg[16 - 1 : 12];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[3:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[7:4] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[11:8] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg ),
.fas ( fas[15 :12] ),
.facout ( faccout3_co3 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[4-1 : 0];
s1_ca_rego1 [0] <= fas[8-1 : 4];
s2_ca_rego2 [0] <= fas[12-1 : 8];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[4-1 : 0] = s0_ca_rego0[2];
assign s_tmp[8-1 : 4] = s1_ca_rego1[1];
assign s_tmp[12-1 : 8] = s2_ca_rego2[0];
assign s_tmp[16 - 1 : 12] = fas[15 :12];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_fadder_f
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3 nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_3_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module dispatches group ids to possibly multiple work item iterators.
// Each work-item iterator should be separated by a fifo from the dispatcher.
module acl_work_group_dispatcher
#(
parameter WIDTH = 32, // width of all the counters
parameter NUM_COPIES = 1, // number of kernel copies to manage
parameter RUN_FOREVER = 0 // flag for infinitely running kernel
)
(
input clock,
input resetn,
input start, // Assert to restart the iterators
// Populated during kernel startup
input [WIDTH-1:0] num_groups[2:0],
input [WIDTH-1:0] local_size[2:0],
// Handshaking with iterators for each kernel copy
input [NUM_COPIES-1:0] stall_in,
output [NUM_COPIES-1:0] valid_out,
// Export group_id to iterators.
output reg [WIDTH-1:0] group_id_out[2:0],
output reg [WIDTH-1:0] global_id_base_out[2:0],
output start_out,
// High when all groups have been dispatched to id iterators
output reg dispatched_all_groups
);
//////////////////////////////////
// Group id register updates.
reg started; // one cycle delayed after start goes high. stays high
reg delayed_start; // two cycles delayed after start goes high. stays high
reg [WIDTH-1:0] max_group_id[2:0];
reg [WIDTH-1:0] group_id[2:0];
wire last_group_id[2:0];
assign last_group_id[0] = (group_id[0] == max_group_id[0] );
assign last_group_id[1] = (group_id[1] == max_group_id[1] );
assign last_group_id[2] = (group_id[2] == max_group_id[2] );
wire last_group = last_group_id[0] & last_group_id[1] & last_group_id[2];
wire group_id_ready;
wire bump_group_id[2:0];
assign bump_group_id[0] = 1'b1;
assign bump_group_id[1] = last_group_id[0];
assign bump_group_id[2] = last_group_id[0] && last_group_id[1];
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
global_id_base_out[0] <= {WIDTH{1'b0}};
global_id_base_out[1] <= {WIDTH{1'b0}};
global_id_base_out[2] <= {WIDTH{1'b0}};
max_group_id[0] <= {WIDTH{1'b0}};
max_group_id[1] <= {WIDTH{1'b0}};
max_group_id[2] <= {WIDTH{1'b0}};
started <= 1'b0;
delayed_start <= 1'b0;
dispatched_all_groups <= 1'b0;
end else if ( start ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
global_id_base_out[0] <= {WIDTH{1'b0}};
global_id_base_out[1] <= {WIDTH{1'b0}};
global_id_base_out[2] <= {WIDTH{1'b0}};
max_group_id[0] <= num_groups[0] - 2'b01;
max_group_id[1] <= num_groups[1] - 2'b01;
max_group_id[2] <= num_groups[2] - 2'b01;
started <= 1'b1;
delayed_start <= started;
dispatched_all_groups <= 1'b0;
end else // We presume that start and issue are mutually exclusive.
begin
if ( started & stall_in != {NUM_COPIES{1'b1}} & ~dispatched_all_groups ) begin
if ( bump_group_id[0] ) group_id[0] <= last_group_id[0] ? {WIDTH{1'b0}} : (group_id[0] + 2'b01);
if ( bump_group_id[1] ) group_id[1] <= last_group_id[1] ? {WIDTH{1'b0}} : (group_id[1] + 2'b01);
if ( bump_group_id[2] ) group_id[2] <= last_group_id[2] ? {WIDTH{1'b0}} : (group_id[2] + 2'b01);
// increment global_id_base here so it's always equal to
// group_id x local_size.
// without using any multipliers.
if ( bump_group_id[0] ) global_id_base_out[0] <= last_group_id[0] ? {WIDTH{1'b0}} : (global_id_base_out[0] + local_size[0]);
if ( bump_group_id[1] ) global_id_base_out[1] <= last_group_id[1] ? {WIDTH{1'b0}} : (global_id_base_out[1] + local_size[1]);
if ( bump_group_id[2] ) global_id_base_out[2] <= last_group_id[2] ? {WIDTH{1'b0}} : (global_id_base_out[2] + local_size[2]);
if ( last_group && RUN_FOREVER == 0 )
dispatched_all_groups <= 1'b1;
end
// reset these registers so that next kernel invocation will work.
if ( dispatched_all_groups ) begin
started <= 1'b0;
delayed_start <= 1'b0;
end
end
end
// will have 1 at the lowest position where stall_in has 0.
wire [NUM_COPIES-1:0] single_one_from_stall_in = ~stall_in & (stall_in + 1'b1);
assign group_id_ready = delayed_start & ~dispatched_all_groups;
assign start_out = start;
assign group_id_out = group_id;
assign valid_out = single_one_from_stall_in & {NUM_COPIES{group_id_ready}};
endmodule
// vim:set filetype=verilog:
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: reg_grp.v 1930 2007-07-14 02:16:20Z grg $
//
// Module: reg_grp.v
// Project: NetFPGA
// Description: Generic register group
//
// Muxes the registers for a group
//
// Note: The downstream modules should respect the rules for the number of
// cycles to hold ack high.
//
///////////////////////////////////////////////////////////////////////////////
module reg_grp #(
parameter REG_ADDR_BITS = 10,
parameter NUM_OUTPUTS = 4
)
(
// Upstream register interface
input reg_req,
input reg_rd_wr_L,
input [REG_ADDR_BITS -1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg reg_ack,
output reg [`CPCI_NF2_DATA_WIDTH -1:0] reg_rd_data,
// Downstream register interface
output [NUM_OUTPUTS - 1 : 0] local_reg_req,
output [NUM_OUTPUTS - 1 : 0] local_reg_rd_wr_L,
output [NUM_OUTPUTS * (REG_ADDR_BITS - log2(NUM_OUTPUTS)) -1:0] local_reg_addr,
output [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_wr_data,
input [NUM_OUTPUTS - 1 : 0] local_reg_ack,
input [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_rd_data,
//-- misc
input clk,
input reset
);
// Log base 2 function
//
// Returns ceil(log2(X))
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Register addresses
localparam SWITCH_ADDR_BITS = log2(NUM_OUTPUTS);
// ===========================================
// Local variables
wire [SWITCH_ADDR_BITS - 1 : 0] sel;
integer i;
// Internal register interface signals
reg int_reg_req[NUM_OUTPUTS - 1 : 0];
reg int_reg_rd_wr_L[NUM_OUTPUTS - 1 : 0];
reg [REG_ADDR_BITS -1:0] int_reg_addr[NUM_OUTPUTS - 1 : 0];
reg [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_wr_data[NUM_OUTPUTS - 1 : 0];
wire int_reg_ack[NUM_OUTPUTS - 1 : 0];
wire [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_rd_data[NUM_OUTPUTS - 1 : 0];
assign sel = reg_addr[REG_ADDR_BITS - 1 : REG_ADDR_BITS - SWITCH_ADDR_BITS];
// =====================================================
// Process register requests
always @(posedge clk)
begin
for (i = 0; i < NUM_OUTPUTS ; i = i + 1) begin
if (reset || sel != i) begin
int_reg_req[i] <= 1'b0;
int_reg_rd_wr_L[i] <= 1'b0;
int_reg_addr[i] <= 'h0;
int_reg_wr_data[i] <= 'h0;
end
else begin
int_reg_req[i] <= reg_req;
int_reg_rd_wr_L[i] <= reg_rd_wr_L;
int_reg_addr[i] <= reg_addr;
int_reg_wr_data[i] <= reg_wr_data;
end
end // for
end
always @(posedge clk)
begin
if (reset || sel >= NUM_OUTPUTS) begin
// Reset the outputs
reg_ack <= 1'b0;
reg_rd_data <= reset ? 'h0 : 'h dead_beef;
end
else begin
reg_ack <= int_reg_ack[sel];
reg_rd_data <= int_reg_rd_data[sel];
end
end
// =====================================================
// Logic to split/join inputs/outputs
genvar j;
generate
for (j = 0; j < NUM_OUTPUTS ; j = j + 1) begin : flatten
assign local_reg_req[j] = int_reg_req[j];
assign local_reg_rd_wr_L[j] = int_reg_rd_wr_L[j];
assign local_reg_addr[j * (REG_ADDR_BITS - SWITCH_ADDR_BITS) +: (REG_ADDR_BITS - SWITCH_ADDR_BITS)] = int_reg_addr[j];
assign local_reg_wr_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH] = int_reg_wr_data[j];
assign int_reg_ack[j] = local_reg_ack[j];
assign int_reg_rd_data[j] = local_reg_rd_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH];
end
endgenerate
// =====================================================
// Verify that ack is never high when the request signal is low
// synthesis translate_off
integer k;
always @(posedge clk) begin
if (reg_req === 1'b0)
for (k = 0; k < NUM_OUTPUTS ; k = k + 1)
if (int_reg_ack[k] === 1'b1)
$display($time, " %m: ERROR: int_reg_ack[%1d] is high when reg_req is low", k);
end
// synthesis translate_on
endmodule // reg_grp
|
// megafunction wizard: %Altera PLL v15.1%
// GENERATION: XML
// pll.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="15.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="25.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="25.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
module ch_pcma(
input CLK,
input CLK_SAMP,
input nRESET,
input FLAGMASK,
output reg END_FLAG,
input KEYON, KEYOFF,
input [11:0] JEDI_DOUT,
input [15:0] ADDR_START,
input [15:0] ADDR_STOP,
input [7:0] VOLPAN, // TODO: This :) Also see ADPCM-A total level
output [21:0] ROM_ADDR,
output reg [3:0] DATA,
output reg [9:0] ADPCM_STEP, // 0~768
input [7:0] ROM_DATA,
output reg [15:0] SAMPLE_OUT
);
reg RUN;
reg [1:0] ROM_BANK;
reg [19:0] ADDR_CNT;
reg NIBBLE;
reg [11:0] ADPCM_ACC;
reg SET_FLAG;
reg PREV_FLAGMASK;
assign ROM_ADDR = { ROM_BANK, ADDR_CNT };
always @(posedge CLK)
begin
if (!nRESET)
begin
SET_FLAG <= 0; // ?
PREV_FLAGMASK <= 0; // ?
RUN <= 0;
end
else
begin
if (KEYON)
begin
ADDR_CNT <= { ADDR_START[11:0], 8'h0 };
ROM_BANK <= ADDR_START[13:12]; // Should be 4 bits in real YM2610 (16M ROMs max., not 4M)
END_FLAG <= 0;
NIBBLE <= 0; // ?
ADPCM_ACC <= 0;
ADPCM_STEP <= 0;
RUN <= 1;
end
if (KEYOFF)
RUN <= 0;
// Get one sample:
if (RUN && CLK_SAMP)
begin
// Edge detect, clear flag
if ((FLAGMASK == 1) && (PREV_FLAGMASK == 0))
END_FLAG <= 0;
PREV_FLAGMASK <= FLAGMASK;
if (ADDR_CNT[19:8] == ADDR_STOP[11:0])
begin
// Edge detect, set flag if not masked
if (SET_FLAG == 0)
begin
SET_FLAG <= 1;
END_FLAG <= ~FLAGMASK;
end
end
else
begin
SET_FLAG <= 0;
if (NIBBLE)
begin
DATA <= ROM_DATA[3:0];
ADDR_CNT <= ADDR_CNT + 1'b1;
end
else
DATA <= ROM_DATA[7:4];
ADPCM_ACC <= ADPCM_ACC + JEDI_DOUT;
case (DATA[2:0])
0, 1, 2, 3 :
begin
if (ADPCM_STEP >= 16)
ADPCM_STEP <= ADPCM_STEP - 10'd16;
else
ADPCM_STEP <= 0;
end
4 :
begin
if (ADPCM_STEP <= (768 - 32))
ADPCM_STEP <= ADPCM_STEP + 10'd32;
else
ADPCM_STEP <= 768;
end
5 :
begin
if (ADPCM_STEP <= (768 - 80))
ADPCM_STEP <= ADPCM_STEP + 10'd80;
else
ADPCM_STEP <= 768;
end
6 :
begin
if (ADPCM_STEP <= (768 - 112))
ADPCM_STEP <= ADPCM_STEP + 10'd112;
else
ADPCM_STEP <= 768;
end
7 :
begin
if (ADPCM_STEP <= (768 - 144))
ADPCM_STEP <= ADPCM_STEP + 10'd144;
else
ADPCM_STEP <= 768;
end
endcase
// Sign-extend 12 to 16
SAMPLE_OUT <= ADPCM_ACC[11] ? { 4'b1111, ADPCM_ACC } : { 4'b0000, ADPCM_ACC };
NIBBLE <= ~NIBBLE;
end
end
end
end
endmodule
|
`define ADDER_WIDTH 011
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
// $Id: c_lfsr.v 1836 2010-03-23 02:35:46Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic multi-input linear feedback shift register register
module c_lfsr
(clk, reset, load, run, feedback, complete, d, q);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
// initial state
parameter [offset:(offset+width)-1] reset_value = {width{1'b1}};
// how many iterations to perform at once
parameter iterations = 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// load data input into signature register
input load;
// activate signature updates
input run;
// feedback polynomial(s)
input [0:width-1] feedback;
// include all-zeros state in state sequence
input complete;
// data input
input [offset:(offset+width)-1] d;
// data output
output [offset:(offset+width)-1] q;
wire [offset:(offset+width)-1] q;
wire [offset:(offset+width)-1] state_q;
wire [0:width-1] feedback_sum;
c_fbmult
#(.width(width),
.iterations(iterations))
fbmult
(.feedback(feedback),
.complete(complete),
.data_in(state_q),
.data_out(feedback_sum));
wire [offset:(offset+width)-1] feedback_value;
assign feedback_value = {width{~load}} & feedback_sum;
wire [offset:(offset+width)-1] toggle_value;
assign toggle_value = feedback_value ^ d;
wire [offset:(offset+width)-1] base_value;
generate
if(width == 1)
begin
assign base_value = 1'b0;
end
else
begin
assign base_value
= {1'b0, {(width-1){~load}} & state_q[offset:(offset+width-1)-1]};
end
endgenerate
wire [offset:(offset+width)-1] state_s;
assign state_s = (load | run) ? (base_value ^ toggle_value) : state_q;
c_dff
#(.width(width),
.offset(offset),
.reset_type(reset_type),
.reset_value(reset_value))
stateq
(.clk(clk),
.reset(reset),
.d(state_s),
.q(state_q));
assign q = state_q;
endmodule
|
`timescale 1ns / 1ps
module top_movil_TB;
reg clk;
// reg start;
reg reset;
reg rxd;
// wire [0:76] String;
wire [15:0] ledsOut;
top_movil uut ( .clk(clk), .rxd(rxd), .reset(reset), .ledsOut(ledsOut));
initial begin // Process for clk
forever
begin
#5
clk = 1'b0;
#5
clk = 1'b1;
end
end
/* initial begin
reset=1;
#100
reset=0;
start=0;
#200
reset=1;
#1000
start=1;
#20
reset=0;
#13998680
reset=1;
#200
reset=0;
end*/
initial begin
reset=1;
#200
reset=0;
rxd =1;
#2000
rxd=0; // simulacion de ruido
#40
rxd=1;
#208280
rxd=0; // Bit de Start 1
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1; // Se termina char 0110011
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 2
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1; // Se termina char 0010101
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 3
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1110010
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 4
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0101100
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 5
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 1110000
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 6
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1; // Se termina char 0011111
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 7
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0010100
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 8
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1; // Se termina char 0011001
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 9
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1100110
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 10
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1111110
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 11
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0110000
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop y queda en 1 como IDLE
end // initial begin
initial begin: TEST_CASE
$dumpfile("top_movil_TB.vcd");
$dumpvars(-1, uut);
#32000000 $finish;
end
endmodule
|
// This is the Avalon slave for the motor controller
// Registers 0-5 store the direction and on/off switch for each motor
// Registers 8-13 store the respective duty cycle
// The output should be fed to GPIO pins in the SOPC configuration
`include "defines.v"
module slave_controller(input clk, input reset, input chipselect, input write, input [3:0]addr, input [31:0] writedata, output [23:0] GPIO_out);
reg [11:0] in = 12'd0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (chipselect & write)
casex (addr)
4'b0000:
in[1:0] <= writedata[1:0];
4'b0001:
in[3:2] <= writedata[1:0];
4'b0010:
in[5:4] <= writedata[1:0];
4'b0011:
in[7:6] <= writedata[1:0];
4'b0100:
in[9:8] <= writedata[1:0];
4'b0101:
in[11:10] <= writedata[1:0];
4'b1000:
duty_cycle[`PERIOD_LENGTH-1:0] <= writedata[`PERIOD_LENGTH-1:0];
4'b1001:
duty_cycle[2*`PERIOD_LENGTH-1:`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1010:
duty_cycle[3*`PERIOD_LENGTH-1:2*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1011:
duty_cycle[4*`PERIOD_LENGTH-1:3*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1100:
duty_cycle[5*`PERIOD_LENGTH-1:4*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1101:
duty_cycle[6*`PERIOD_LENGTH-1:5*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1110:
period <= writedata[15:0];
default:
; // do nothing
endcase
generate
genvar i;
for (i=0; i<6; i=i+1)
begin : motor_control_loop
motor_controller mc(clk, in[i*2 + 1], in[i*2], period, duty_cycle[(i+1)*`PERIOD_LENGTH-1:i*`PERIOD_LENGTH], GPIO_out[i*4+3:i*4]);
end
endgenerate
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 1
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "triangle_intersect_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "triangle_intersect_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module triangle_intersect_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [63 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [63 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [7 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [1 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(2),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg484")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
(** * RecordSub_J: レコードのサブタイプ *)
(* * RecordSub: Subtyping with Records *)
(* $Date: 2011-04-04 09:00:42 -0400 (Mon, 04 Apr 2011) $ *)
Require Export MoreStlc_J.
(* ###################################################### *)
(* * Core Definitions *)
(** * 中核部の定義 *)
(* ################################### *)
(* *** Syntax *)
(** *** 構文 *)
Inductive ty : Type :=
(* proper types *)
| ty_Top : ty
| ty_base : id -> ty
| ty_arrow : ty -> ty -> ty
(* record types *)
| ty_rnil : ty
| ty_rcons : id -> ty -> ty -> ty.
Tactic Notation "ty_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ty_Top" | Case_aux c "ty_base" | Case_aux c "ty_arrow"
| Case_aux c "ty_rnil" | Case_aux c "ty_rcons" ].
Inductive tm : Type :=
(* proper terms *)
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_proj : tm -> id -> tm
(* record terms *)
| tm_rnil : tm
| tm_rcons : id -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app" | Case_aux c "tm_abs"
| Case_aux c "tm_proj" | Case_aux c "tm_rnil" | Case_aux c "tm_rcons" ].
(* ################################### *)
(* *** Well-Formedness *)
(** *** Well-Formedness *)
Inductive record_ty : ty -> Prop :=
| rty_nil :
record_ty ty_rnil
| rty_cons : forall i T1 T2,
record_ty (ty_rcons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtm_nil :
record_tm tm_rnil
| rtm_cons : forall i t1 t2,
record_tm (tm_rcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfty_Top :
well_formed_ty ty_Top
| wfty_base : forall i,
well_formed_ty (ty_base i)
| wfty_arrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (ty_arrow T1 T2)
| wfty_rnil :
well_formed_ty ty_rnil
| wfty_rcons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (ty_rcons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ################################### *)
(* *** Substitution *)
(** *** 置換 *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tm_var y => if beq_id x y then s else t
| tm_abs y T t1 => tm_abs y T (if beq_id x y then t1 else (subst x s t1))
| tm_app t1 t2 => tm_app (subst x s t1) (subst x s t2)
| tm_proj t1 i => tm_proj (subst x s t1) i
| tm_rnil => tm_rnil
| tm_rcons i t1 tr2 => tm_rcons i (subst x s t1) (subst x s tr2)
end.
(* ################################### *)
(* *** Reduction *)
(** *** 簡約 *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tm_abs x T t)
| v_rnil : value tm_rnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (tm_rcons i v vr).
Hint Constructors value.
Fixpoint ty_lookup (i:id) (Tr:ty) : option ty :=
match Tr with
| ty_rcons i' T Tr' => if beq_id i i' then Some T else ty_lookup i Tr'
| _ => None
end.
Fixpoint tm_lookup (i:id) (tr:tm) : option tm :=
match tr with
| tm_rcons i' t tr' => if beq_id i i' then Some t else tm_lookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tm_app (tm_abs x T t12) v2) ==> (subst x v2 t12)
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tm_app t1 t2) ==> (tm_app t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tm_app v1 t2) ==> (tm_app v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tm_proj tr i) ==> (tm_proj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tm_lookup i tr = Some vi ->
(tm_proj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(tm_rcons i t1 tr2) ==> (tm_rcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(tm_rcons i v1 tr2) ==> (tm_rcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Proj1" | Case_aux c "ST_ProjRcd" | Case_aux c "ST_Rcd"
| Case_aux c "ST_Rcd_Head" | Case_aux c "ST_Rcd_Tail" ].
Hint Constructors step.
(* ###################################################################### *)
(* * Subtyping *)
(** * サブタイプ *)
(* Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(** おもしろい部分に来ました。サブタイプ関係を定義し、
その重要な技術的性質のいくつかを調べることから始めます。 *)
(* ################################### *)
(* ** Definition *)
(** ** 定義 *)
(* The definition of subtyping is essentially just what we
sketched in the motivating discussion, but we need to add
well-formedness side conditions to some of the rules. *)
(** サブタイプの定義は、本質的には、動機付けの議論で概観した通りです。
ただ、いくつかの規則に付加条件として well-formedness を追加する必要があります。 *)
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
well_formed_ty S ->
subtype S ty_Top
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (ty_arrow S1 S2) (ty_arrow T1 T2)
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (ty_rcons i T1 T2) ->
subtype (ty_rcons i T1 T2) ty_rnil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
subtype S1 T1 ->
subtype Sr2 Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
subtype (ty_rcons i S1 Sr2) (ty_rcons i T1 Tr2)
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (ty_rcons i1 T1 (ty_rcons i2 T2 Tr3)) ->
i1 <> i2 ->
subtype (ty_rcons i1 T1 (ty_rcons i2 T2 Tr3))
(ty_rcons i2 T2 (ty_rcons i1 T1 Tr3)).
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans" | Case_aux c "S_Top"
| Case_aux c "S_Arrow" | Case_aux c "S_RcdWidth"
| Case_aux c "S_RcdDepth" | Case_aux c "S_RcdPerm" ].
(* ############################################### *)
(* ** Subtyping Examples and Exercises *)
(** ** サブタイプの例と練習問題 *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (ty_base (Id 6)).
Notation B := (ty_base (Id 7)).
Notation C := (ty_base (Id 8)).
Definition ty_rcd_j :=
(ty_rcons j (ty_arrow B B) ty_rnil). (* {j:B->B} *)
Definition ty_rcd_kj :=
ty_rcons k (ty_arrow A A) ty_rcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (ty_arrow C ty_rcd_kj)
(ty_arrow C ty_rnil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold ty_rcd_kj, ty_rcd_j. apply S_RcdWidth; auto.
Qed.
(* The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** 以下の事実のほとんどはCoqで証明することは簡単です。
練習問題の効果を最大にするため、どのように証明するかを理解していることを紙の上でも確認しなさい!
*)
(* **** Exercise: 2 stars *)
(** **** 練習問題: ★★ *)
Example subtyping_example_1 :
subtype ty_rcd_kj ty_rcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star *)
(** **** 練習問題: ★ *)
Example subtyping_example_2 :
subtype (ty_arrow ty_Top ty_rcd_kj)
(ty_arrow (ty_arrow C C) ty_rcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star *)
(** **** 練習問題: ★ *)
Example subtyping_example_3 :
subtype (ty_arrow ty_rnil (ty_rcons j A ty_rnil))
(ty_arrow (ty_rcons k B ty_rnil) ty_rnil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars *)
(** **** 練習問題: ★★ *)
Example subtyping_example_4 :
subtype (ty_rcons x A (ty_rcons y B (ty_rcons z C ty_rnil)))
(ty_rcons z C (ty_rcons y B (ty_rcons x A ty_rnil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Definition tm_rcd_kj :=
(tm_rcons k (tm_abs z A (tm_var z))
(tm_rcons j (tm_abs z B (tm_var z))
tm_rnil)).
End Examples.
(* ###################################################################### *)
(* ** Properties of Subtyping *)
(** ** サブタイプの性質 *)
(* *** Well-Formedness *)
(** *** Well-Formedness *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
subtype_cases (induction Hsub) Case;
intros; try (destruct IHHsub1; destruct IHHsub2)...
Case "S_RcdPerm".
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
ty_lookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
ty_cases (induction T) Case; intros; try solve by inversion.
Case "ty_rcons".
inversion H. subst. unfold ty_lookup in H0.
remember (beq_id i i0) as b. destruct b; subst...
inversion H0. subst... Qed.
(* *** Field Lookup *)
(** *** フィールド参照 *)
(* Our record matching lemmas get a little more complicated in
the presence of subtyping for two reasons: First, record
types no longer necessarily describe the exact structure of
corresponding terms. Second, reasoning by induction on
[has_type] derivations becomes harder in general, because
[has_type] is no longer syntax directed. *)
(** サブタイプがあることで、レコードマッチング補題はいくらか複雑になります。
それには2つの理由があります。
1つはレコード型が対応する項の正確な構造を記述する必要がなくなることです。
2つ目は、[has_type]の導出に関する帰納法を使う推論が一般には難しくなることです。
なぜなら、[has_type]が構文指向ではなくなるからです。 *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
ty_lookup i T = Some Ti ->
exists Si, ty_lookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
subtype_cases (induction Hsub) Case; intros Ti Hget;
try solve by inversion.
Case "S_Refl".
exists Ti...
Case "S_Trans".
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
Case "S_RcdDepth".
rename i0 into k.
unfold ty_lookup. unfold ty_lookup in Hget.
remember (beq_id i k) as b. destruct b...
SCase "i = k -- we're looking up the first field".
inversion Hget. subst. exists S1...
Case "S_RcdPerm".
exists Ti. split.
SCase "lookup".
unfold ty_lookup. unfold ty_lookup in Hget.
remember (beq_id i i1) as b. destruct b...
SSCase "i = i1 -- we're looking up the first field".
remember (beq_id i i2) as b. destruct b...
SSSCase "i = i2 - -contradictory".
destruct H0.
apply beq_id_eq in Heqb. apply beq_id_eq in Heqb0.
subst...
SCase "subtype".
inversion H. subst. inversion H5. subst... Qed.
(* **** Exercise: 3 stars (rcd_types_match_informal) *)
(** **** 練習問題: ★★★ (rcd_types_match_informal) *)
(* Write a careful informal proof of the [rcd_types_match]
lemma. *)
(** [rcd_types_match]補題の非形式的証明を注意深く記述しなさい。 *)
(* FILL IN HERE *)
(** [] *)
(* *** Inversion Lemmas *)
(** *** 反転補題 *)
(* **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
(** **** 練習問題: ★★★, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (ty_arrow V1 V2) ->
exists U1, exists U2,
(U=(ty_arrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (ty_arrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(* * Typing *)
(** * 型付け *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if beq_id x x' then Some T else Gamma x'.
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
has_type Gamma (tm_var x) T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tm_abs x T11 t12) (ty_arrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (ty_arrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tm_app t1 t2) T2
| T_Proj : forall Gamma i t T Ti,
has_type Gamma t T ->
ty_lookup i T = Some Ti ->
has_type Gamma (tm_proj t i) Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T
(* Rules for record terms *)
| T_RNil : forall Gamma,
has_type Gamma tm_rnil ty_rnil
| T_RCons : forall Gamma i t T tr Tr,
has_type Gamma t T ->
has_type Gamma tr Tr ->
record_ty Tr ->
record_tm tr ->
has_type Gamma (tm_rcons i t tr) (ty_rcons i T Tr).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Proj" | Case_aux c "T_Sub"
| Case_aux c "T_RNil" | Case_aux c "T_RCons" ].
(* ############################################### *)
(* ** Typing Examples *)
(** ** 型付けの例 *)
Module Examples2.
Import Examples.
(* **** Exercise: 1 star *)
(** **** 練習問題: ★ *)
Example typing_example_0 :
has_type empty
(tm_rcons k (tm_abs z A (tm_var z))
(tm_rcons j (tm_abs z B (tm_var z))
tm_rnil))
ty_rcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars *)
(** **** 練習問題: ★★ *)
Example typing_example_1 :
has_type empty
(tm_app (tm_abs x ty_rcd_j (tm_proj (tm_var x) j))
(tm_rcd_kj))
(ty_arrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j) {k=(\z:A.z), j=(\z:B.z)} : B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional *)
(** **** 練習問題: ★★, optional *)
Example typing_example_2 :
has_type empty
(tm_app (tm_abs z (ty_arrow (ty_arrow C C) ty_rcd_j)
(tm_proj (tm_app (tm_var z)
(tm_abs x C (tm_var x)))
j))
(tm_abs z (ty_arrow C C) tm_rcd_kj))
(ty_arrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ###################################################################### *)
(* ** Properties of Typing *)
(** ** 型付けの性質 *)
(* *** Well-Formedness *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
has_type_cases (induction Htyp) Case...
Case "T_App".
inversion IHHtyp1...
Case "T_Proj".
eapply wf_rcd_lookup...
Case "T_Sub".
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(* *** Field Lookup *)
(** *** フィールド参照 *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
ty_lookup i T = Some Ti ->
exists vi, tm_lookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
has_type_cases (induction Htyp) Case; intros; subst; try solve by inversion.
Case "T_Sub".
apply (rcd_types_match S) in H0... destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
Case "T_RCons".
simpl in H0. simpl. simpl in H1.
remember (beq_id i i0) as b. destruct b.
SCase "i is first".
inversion H1. subst. exists t...
SCase "i in tail".
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ########################################## *)
(* *** Progress *)
(** *** 進行 *)
(* **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
(** **** 練習問題: ★★★ (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (ty_arrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tm_abs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists (subst x t2 t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tm_app t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tm_app t1' t2)...
Case "T_Proj".
right. destruct IHHt...
SCase "rcd is value".
destruct (lookup_field_in_value t T i Ti) as [t' [Hget Ht']]...
SCase "rcd_steps".
destruct H0 as [t' Hstp]. exists (tm_proj t' i)...
Case "T_RCons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. destruct H2 as [tr' Hstp].
exists (tm_rcons i t tr')...
SCase "head steps".
right. destruct H1 as [t' Hstp].
exists (tm_rcons i t' tr)... Qed.
(* Informal proof of progress:
Theorem : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
Proof : Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the typing derivation. Cases [T_Abs] and
[T_RNil] are immediate because abstractions and [{}] are always
values. Case [T_Var] is vacuous because variables cannot be
typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and
[empty |- t2 : T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[t1 t2 ==> t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then
[t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for some
[x], [S1], and [s2]. And [(\x:S1.s2) t2 ==> [t2/x]s2] by
[ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [ty_lookup i Tr = Some T].
The IH for the typing subderivation gives us that either [tr]
is a value or it steps. If [tr ==> tr'] for some term [tr'],
then [tr.i ==> tr'.i] by rule [ST_Proj1].
Otherwise, [tr] is a value. In this case, lemma
[lookup_field_in_value] yields that there is a term [ti] such
that [tm_lookup i tr = Some ti]. It follows that [tr.i ==> ti]
by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[{i=t1, tr} ==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then
[{i=t1, tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail],
since [t1] is a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(** 進行の非形式的証明:
定理： 任意の項[t]と型[T]について、[empty |- t : T]ならば、
[t]は値であるか、ある項[t']について [t ==> t'] である。
証明 : [t]と[T]が [empty |- t : T] を満たすとする。
型付け導出についての帰納法を使う。
[T_Abs]と[T_RNil]の場合は自明である。それは、関数抽象と[{}]は常に値だからである。
[T_Var]の場合は考えなくて良い。なぜなら変数は空コンテキストで型付けできないからである。
- 型付け導出の最後のステップが[T_App]の適用だった場合、
項 [t1] [t2] と型 [T1] [T2] があって [t = t1 t2]、[T = T2]、
[empty |- t1 : T1 -> T2]、[empty |- t2 : T1] となる。
これらの型付け導出の帰納法の仮定より、[t1]は値であるかステップを進めることができ、
また[t2]は値であるかステップを進めることができる。
それぞれの場合を考える:
- ある項[t1']について [t1 ==> t1'] とする。
すると[ST_App1]より [t1 t2 ==> t1' t2] である。
- そうでないならば[t1]は値である。
- ある項[t2']について [t2 ==> t2'] とする。
すると[t1]が値であることから規則[ST_App2]により [t1 t2 ==> t1 t2'] となる。
- そうでなければ[t2]は値である。補題[canonical_forms_for_arrow_types]により、
ある[x]、[S1]、[s2]について [t1 = \x:S1.s2] である。
すると[t2]が値であることから、[ST_AppAbs]により
[(\x:S1.s2) t2 ==> [t2/x]s2] となる。
- 導出の最後のステップが[T_Proj]の適用だった場合、
項[tr]、型[Tr]、ラベル[i]が存在して [t = tr.i]、[empty |- tr : Tr]、
[ty_lookup i Tr = Some T] となる。
導出の一部である型付け導出の帰納仮定より、[tr]は値であるかステップを進むことができる。
もしある項[tr']について [tr ==> tr'] ならば、規則[ST_Proj1]より
[tr.i ==> tr'.i] となる。
そうでなければ、[tr]は値である。この場合、補題[lookup_field_in_value]
により項[ti]が存在して [tm_lookup i tr = Some ti] となる。
これから、規則[ST_ProjRcd]より [tr.i ==> ti] となる。
- 導出の最後のステップが[T_Sub]の適用だった場合、
型[S]が存在して [S <: T] かつ [empty |- t : S] となる。
導出の一部である型付け導出の帰納法の仮定から求める結果がすぐに得られる。
- 導出の最後のステップが[T_RCons]の適用だった場合、
項[t1] [tr]、型 [T1 Tr]、ラベル[i]が存在して
[t = {i=t1, tr}]、[T = {i:T1, Tr}]、[record_tm tr]、
[record_tm Tr]、[empty |- t1 : T1]、[empty |- tr : Tr] となる。
これらの型付け導出についての帰納法の仮定より、[t1]は値であるか、ステップを進めることができ、
[tr]は値であるかステップを進めることができることが言える。
それそれの場合を考える:
- ある項[t1']について [t1 ==> t1'] とする。
すると規則[ST_Rcd_Head]から [{i=t1, tr} ==> {i=t1', tr}] となる。
- そうではないとき、[t1]は値である。
- ある項[tr']について [tr ==> tr'] とする。
すると[t1]が値であることから、規則[ST_Rcd_Tail]より
[{i=t1, tr} ==> {i=t1, tr'}] となる。
- そうではないとき、[tr]も値である。すると、[v_rcons]から [{i=t1, tr}] は値である。
*)
(* ########################################## *)
(* *** Inversion Lemmas *)
(** *** 反転補題 *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tm_var x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tm_var x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tm_app t1 t2) T2 ->
exists T1,
has_type Gamma t1 (ty_arrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tm_app t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tm_abs x S1 t2) T ->
(exists S2, subtype (ty_arrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tm_abs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tm_proj t1 i) Ti ->
exists T, exists Si,
ty_lookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tm_proj t1 i) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Proj".
assert (well_formed_ty Ti) as Hwf.
SCase "pf of assertion".
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H...
exists T. exists Ti...
Case "T_Sub".
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (tm_rcons i ti tr) T ->
exists Si, exists Sr,
subtype (ty_rcons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (tm_rcons i ti tr) as t.
has_type_cases (induction Hty) Case;
inversion Heqt; subst...
Case "T_Sub".
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
Case "T_RCons".
assert (well_formed_ty (ty_rcons i T Tr)) as Hwf.
SCase "pf of assertion".
apply has_type__wf in Hty1.
apply has_type__wf in Hty2...
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tm_abs x S1 s2) (ty_arrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(* *** Context Invariance *)
(** *** コンテキスト不変性 *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tm_var x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_app t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_app t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tm_abs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tm_proj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (tm_rcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (tm_rcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. remember (beq_id x x0) as e.
destruct e...
Case "T_App".
apply T_App with T1...
Case "T_RCons".
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold extend in Hctx. apply not_eq_beq_id_false in H3.
rewrite H3 in Hctx... Qed.
(* ########################################## *)
(* *** Preservation *)
(** *** 保存 *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma (subst x v t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
tm_cases (induction t) Case; intros; simpl.
Case "tm_var".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold extend in Hctx.
remember (beq_id x y) as e. destruct e...
SCase "x=y".
apply beq_id_eq in Heqe. subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
destruct (subtype__wf _ _ Hsub)...
Case "tm_app".
destruct (typing_inversion_app _ _ _ _ Htypt) as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tm_abs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (ty_arrow T1 T2)... apply T_Abs...
remember (beq_id x y) as e. destruct e.
SCase "x=y".
eapply context_invariance...
apply beq_id_eq in Heqe. subst.
intros x Hafi. unfold extend.
destruct (beq_id y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
remember (beq_id y z) as e0. destruct e0...
apply beq_id_eq in Heqe0. subst.
rewrite <- Heqe...
Case "tm_proj".
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
Case "tm_rnil".
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
Case "tm_rcons".
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (ty_rcons i Ti Tr)...
apply T_RCons...
SCase "record_ty Tr".
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
SCase "record_tm (subst x v t2)".
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Case "T_Proj".
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
Case "T_RCons".
eauto using step_preserves_record_tm. Qed.
(* Informal proof of [preservation]:
Theorem: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
Proof: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and {} don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [t2/x]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [t2/x] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [ty_lookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tm_lookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(** [preservation]の非形式的証明:
定理: [t]、[t']が項で[T]が型であり [empty |- t : T] かつ [t ==> t'] ならば、
[empty |- t' : T] である。
証明: [t]と[T]が [empty |- t : T] であるとする。
[t']を特化しないまま、型付け導出の構造についての帰納法で証明を進める。
[T_Var]の場合は前と同様考える必要はない。コンテキストが空だからである。
- もし導出の最後ステップで使った規則が[T_App]ならば、
項[t1] [t2]と型[T1] [T2]があり、[t = t1 t2]、
[T = T2]、[empty |- t1 : T1 -> T2]、[empty |- t2 : T1] である。
ステップ関係の定義を見ることにより、 [t1 t2] がステップを進める方法は3通りであることがわかる。
[ST_App1]と[ST_App2]の場合は型付け導出の帰納法の仮定と[T_App]を使うことで、
すぐに証明が完了する。
そうではなく[ST_AppAbs]により [t1 t2] がステップを進めるとする。
すると、ある型[S]と項[t12]について [t1 = \x:S.t12] かつ [t' = [t2/x]t12]
となる。
補題[abs_arrow]より、[T1 <: S] かつ [x:S1 |- s2 : T2] であるから、
補題[substitution_preserves_typing]より [empty |- [t2/x] t12 : T2]
となり、これが求める結果である。
- もし導出の最後ステップで使った規則が[T_Proj]ならば、
項[tr]、型[Tr]、ラベル[i]が存在して [t = tr.i] かつ [empty |- tr : Tr]
かつ [ty_lookup i Tr = Some T] となる。
型付け導出の帰納仮定より、任意の項[tr']について、[tr ==> tr'] ならば
[empty |- tr' Tr] である。ステップ関係の定義より、射影がステップを進める方法は2つである。
[ST_Proj1]の場合は帰納仮定からすぐに証明される。
そうではなく[tr.i]のステップが[ST_ProjRcd]による場合、
[tr]は値であり、ある項[vi]があって [tm_lookup i tr = Some vi] かつ
[t' = vi] となる。しかし補題[lookup_field_in_value]より
[empty |- vi : Ti] となるが、これが求める結果である。
- もし導出の最後ステップで使った規則が[T_Sub]ならば、型[S]が存在して
[S <: T] かつ [empty |- t : S] となる。
型付け導出の帰納法の仮定と[T_Sub]の適用により結果がすぐに得られる。
- もし導出の最後ステップで使った規則が[T_RCons]ならば、
項 [t1] [tr]、型 [T1 Tr]、ラベル[i]が存在して
[t = {i=t1, tr}]、[T = {i:T1, Tr}]、[record_tm tr]、
[record_tm Tr]、[empty |- t1 : T1]、[empty |- tr : Tr] となる。
ステップ関係の定義より、[t]は[ST_Rcd_Head]または[ST_Rcd_Tail]
によってステップを進めたはずである。[ST_Rcd_Head]の場合、
[t1]の型付け導出についての帰納仮定と[T_RCons]より求める結果が得られる。
[ST_Rcd_Tail]の場合、[tr]の型付け導出についての帰納仮定、[T_RCons]、
および[step_preserves_record_tm]補題の使用から求める結果が得られる。 *)
(* ###################################################### *)
(* ** Exercises on Typing *)
(** ** 型付けの練習問題 *)
(* **** Exercise: 2 stars, optional (variations) *)
(** **** 練習問題: ★★, optional (variations) *)
(* Each part of this problem suggests a different way of
changing the definition of the STLC with records and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
[[[
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
]]]
- Suppose we add the following reduction rule:
[[[
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny3)
{} <: Top->Top
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny4)
Top->Top <: {}
]]]
- Suppose we add the following evaluation rule:
[[[
----------------- (ST_Funny5)
({} t) ==> (t {})
]]]
- Suppose we add the same evaluation rule *and* a new typing rule:
[[[
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
]]]
- Suppose we *change* the arrow subtyping rule to:
[[[
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
]]]
[]
*)
(** この問題のそれぞれの部分は、レコードとサブタイプを持つSTLCの定義を変更する別々の方法を表しています。
(これらの変更は累積的ではありません。それぞれの部分はもともとの言語から始めます。)
それぞれの部分について、(進行、保存の)性質のうち成立するものをリストアップしなさい。
また、成立しない性質について、反例を挙げなさい。
- 次の型付け規則を追加する:
[[
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
]]
- 次の簡約規則を追加する:
[[
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
]]
- 次のサブタイプ規則を追加する:
[[
-------------- (S_Funny3)
{} <: Top->Top
]]
- 次のサブタイプ規則を追加する:
[[
-------------- (S_Funny4)
Top->Top <: {}
]]
- 次の評価規則を追加する:
[[
----------------- (ST_Funny5)
({} t) ==> (t {})
]]
- 上と同じ評価規則と新しい型付け規則を追加する:
[[
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
]]
- 関数型についてのサブタイプ規則を次のものに変更する:
[[
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
]]
[]
*)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_2_V
`define SKY130_FD_SC_MS__DFBBN_2_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_2_V
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// This a power trigger module implemented on top of the custom dsp template.
// Power triggering is implemented after the existing DDC chain.
// Triggering is controlled via user settings registers.
// Register 0:
// threshold for power trigger
// 32 bit unsigned fixed-point number of some arbitrary scaling
module power_trig
#(
//frontend bus width
parameter WIDTH = 24,
parameter BASE = 0
)
(
//control signals
input clock, //dsp clock
input reset, //active high synchronous reset
input clear, //active high on packet control init
input enable, //active high when streaming enabled
//user settings bus, controlled through user setting regs API
input set_stb, input [7:0] set_addr, input [31:0] set_data,
//full rate inputs directly from the RX frontend
input [WIDTH-1:0] frontend_i,
input [WIDTH-1:0] frontend_q,
//full rate outputs directly to the DDC chain
output [WIDTH-1:0] ddc_in_i,
output [WIDTH-1:0] ddc_in_q,
//strobed samples {I16,Q16} from the RX DDC chain
input [31:0] ddc_out_sample,
input ddc_out_strobe, //high on valid sample
output ddc_out_enable, //enables DDC module
//strobbed baseband samples {I16,Q16} from this module
output [31:0] bb_sample,
output bb_strobe //high on valid sample
);
//leave frontend tied to existing ddc chain
assign ddc_in_i = frontend_i;
assign ddc_in_q = frontend_q;
//ddc enable remains tied to global enable
assign ddc_out_enable = enable;
//below we implement a power trigger between baseband samples and ddc output...
reg [8:0] wr_addr;
wire [8:0] rd_addr;
reg triggered, triggerable;
wire trigger;
wire [31:0] delayed_sample;
wire [31:0] thresh;
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(thresh),.changed());
assign rd_addr = wr_addr + 1; // FIXME adjustable delay
ram_2port #(.DWIDTH(32),.AWIDTH(9)) delay_line
(.clka(clk),.ena(1),.wea(ddc_out_strobe),.addra(wr_addr),.dia(ddc_out_sample),.doa(),
.clkb(clk),.enb(ddc_out_strobe),.web(1'b0),.addrb(rd_addr),.dib(32'hFFFF),.dob(delayed_sample));
always @(posedge clock)
if(reset | ~enable)
wr_addr <= 0;
else
if(ddc_out_strobe)
wr_addr <= wr_addr + 1;
always @(posedge clock)
if(reset | ~enable)
triggerable <= 0;
else if(wr_addr == 9'h1FF) // Wait till we're nearly full
triggerable <= 1;
reg stb_d1, stb_d2;
always @(posedge clock) stb_d1 <= ddc_out_strobe;
always @(posedge clock) stb_d2 <= stb_d1;
assign bb_sample = delayed_sample;
assign bb_strobe = stb_d1 & triggered;
// Compute Mag
wire [17:0] mult_in = stb_d1 ? { ddc_out_sample[15],ddc_out_sample[15:0], 1'b0 } :
{ ddc_out_sample[31], ddc_out_sample[31:16], 1'b0 };
wire [35:0] prod;
reg [31:0] sum;
MULT18X18S mult (.P(prod), .A(mult_in), .B(mult_in), .C(clock), .CE(ddc_out_strobe | stb_d1), .R(reset) );
always @(posedge clock)
if(stb_d1)
sum <= prod[35:4];
else if(stb_d2)
sum <= sum + prod[35:4];
always @(posedge clock)
if(reset | ~enable | ~triggerable)
triggered <= 0;
else if(trigger)
triggered <= 1;
assign trigger = (sum > thresh);
endmodule // power_trig
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* SINGLE-OPERAND ARITHMETIC: RETI INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the RETI instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer i;
reg [15:0] temp_val;
integer inst_cnt;
always @(inst_number)
inst_cnt <= inst_cnt+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef NMI
// Test NMI disabled
//--------------------------
@(r15==16'h1000);
$display(" Test NMI disabled");
@(r15==16'h1001);
#(2000);
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
nmi = 1'b1;
#(6000);
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
wkup[0] = 1'b1;
@(negedge mclk)
irq[`IRQ_NR-16] = 1'b1;
@(negedge irq_acc[`IRQ_NR-16])
wkup[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b0;
@(r15==16'h1002);
nmi = 1'b0;
if (r6 !==16'h0000) tb_error("====== NMI disabled: NMI irq was taken =====");
if (r14 !==16'h0000) tb_error("====== NMI disabled: flag is set after reset =====");
if (r13 !==16'h0010) tb_error("====== NMI disabled: flag is not set =====");
if (r12 !==16'h0000) tb_error("====== NMI disabled: flag was not cleared =====");
if (r11 !==16'h0000) tb_error("====== NMI disabled: flag is set =====");
// Test NMI rising edge
//--------------------------
@(r15==16'h2000);
$display(" Test NMI rising edge");
@(r15==16'h2001);
#(2000);
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
#(2000);
nmi = 1'b1;
#(2000);
if (r6 !==16'h0001) tb_error("====== NMI rising edge: NMI irq was not taken first time =====");
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU did not woke up because of NMI =====");
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
#(2000);
nmi = 1'b0;
#(4000);
if (r6 !==16'h0001) tb_error("====== NMI rising edge: NMI irq was taken with falling edge =====");
if (inst_cnt !==16'h0000) tb_error("====== NMI rising edge: CPU is not sleeping =====");
#(2000);
nmi = 1'b1;
#(2000);
if (r6 !==16'h0002) tb_error("====== NMI rising edge: NMI irq was not taken second time =====");
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU did not woke up because of NMI =====");
inst_cnt = 0;
#(2000);
if (inst_cnt ===16'h0000) tb_error("====== NMI rising edge: CPU is not running =====");
#(2000);
nmi = 1'b0;
#(4000);
if (r6 !==16'h0002) tb_error("====== NMI rising edge: NMI irq was taken with falling edge =====");
// Test NMI falling edge
//--------------------------
@(r15==16'h3000);
`ifdef WATCHDOG
$display(" Test NMI falling edge");
`else
$display(" Skip NMI falling edge (Watchdog is not included)");
`endif
@(r15==16'h3001);
#(2000);
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
#(2000);
nmi = 1'b1;
#(2000);
`ifdef WATCHDOG
if (r6 !==16'h0000) tb_error("====== NMI falling edge: NMI irq was taken with rising edge =====");
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
`else
#(2000);
`endif
#(2000);
nmi = 1'b0;
#(2000);
if (r6 !==16'h0001) tb_error("====== NMI falling edge: NMI irq was not taken first time =====");
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU did not woke up because of NMI =====");
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
#(2000);
nmi = 1'b1;
#(2000);
`ifdef WATCHDOG
if (r6 !==16'h0001) tb_error("====== NMI falling edge: NMI irq was taken with rising edge =====");
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI falling edge: CPU is not sleeping =====");
`else
#(2000);
`endif
#(2000);
nmi = 1'b0;
#(2000);
if (r6 !==16'h0002) tb_error("====== NMI falling edge: NMI irq was not taken second time =====");
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU did not woke up because of NMI =====");
inst_cnt = 0;
#(2000);
if (inst_cnt ===16'h0000) tb_error("====== NMI falling edge: CPU is not out of LPM4 =====");
#(2000);
// Test NMI nested from Maskable-IRQ
//-----------------------------------
@(r15==16'h4000);
$display(" Test NMI nested from Maskable-IRQ");
@(r15==16'h4001);
#(2000);
inst_cnt = 0;
#(2000);
if (inst_cnt !==16'h0000) tb_error("====== NMI nested: CPU is not sleeping =====");
#(2000);
wkup[0] = 1'b1;
irq[`IRQ_NR-16] = 1'b1;
@(negedge irq_acc[`IRQ_NR-16])
wkup[0] = 1'b0;
irq[`IRQ_NR-16] = 1'b0;
nmi = 1'b1;
@(r15==16'h4002);
if (r6 !==16'h0001) tb_error("====== NMI nested: NMI irq was not taken =====");
if (inst_cnt ===16'h0000) tb_error("====== NMI nested: CPU did not woke up =====");
if (r10 !==16'h5679) tb_error("====== NMI nested: NMI was not nested from IRQ =====");
`else
tb_skip_finish("| (the NMI support is not included) |");
`endif
stimulus_done = 1;
end
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 10:33:48 03/17/2013
// Design Name:
// Module Name: Transmisor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module Transmisor
#(
parameter DBIT = 8 , // #databits
SB_TICK = 16 // #ticks fors top bits
)
(
input wire clk, reset,
input wire tx_start, s_tick,
input wire [7:0] din,
output reg TX_Done=0,
output wire tx
);
// synlbolic s t a t e d e c l a r a t i o n
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaratio n
reg [1:0] state_reg=0, state_next=0;
reg [3:0] s_reg=0, s_next=0;
reg [2:0] n_reg=0, n_next=0;
reg [7:0] b_reg=0, b_next=0;
reg tx_reg=1, tx_next=1;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0 ;
tx_reg <= 1'b1;
end
else
begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
// FSMD next_state logic&functional units
always @*
begin
state_next = state_reg;
TX_Done = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
tx_next = tx_reg;
case (state_reg)
idle:
begin
tx_next = 1'b1;
if (tx_start)
begin
state_next = start;
s_next =0;
b_next = din;
end
end
start:
begin
tx_next =1'b0;
if (s_tick)
if (s_reg ==15)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg + 1;
end
data:
begin
tx_next =b_reg[0];
if (s_tick)
if (s_reg == 15)
begin
s_next =0;
b_next = b_reg>>1;
if (n_reg==(DBIT-1))
state_next = stop;
else
n_next = n_reg + 1;
end
else
s_next = s_reg + 1;
end
stop:
begin
tx_next =1'b1;
if (s_tick)
if (s_reg==(SB_TICK-1 ))
begin
state_next = idle;
TX_Done = 1'b1;
end
else
s_next = s_reg+ 1;
end
endcase
end
// output
assign tx = tx_reg;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] right;
reg [31:0] left;
reg [63:0] qright;
reg [63:0] qleft;
reg [31:0] amt;
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
qright = 64'hf784bf8f_12734089 >> amt;
qleft = 64'hf784bf8f_12734089 >> amt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
`endif
if (cyc==1) begin
amt <= 32'd0;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
end
if (cyc==2) begin
amt <= 32'd28;
if (left != 32'h819b018a) $stop;
if (right != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
end
if (cyc==3) begin
amt <= 32'd31;
if (left != 32'ha0000000) $stop;
if (right != 32'h8) $stop;
if (qleft != 64'h0000000f784bf8f1) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
end
if (cyc==4) begin
amt <= 32'd32;
if (left != 32'h0) $stop;
if (right != 32'h1) $stop;
if (qleft != 64'h00000001ef097f1e) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
amt <= 32'd33;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h00000000f784bf8f) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
amt <= 32'd64;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h000000007bc25fc7) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
amt <= 32'd128;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module main;
wire [2:0] value1, value2, value3, value4;
dut #( .select(1) ) dut1(value1);
dut #( .select(2) ) dut2(value2);
dut #( .select(3) ) dut3(value3);
dut #( .select(4) ) dut4(value4);
initial begin
#1 $display("value1=%d, value2=%d, value3=%d, value4=%d",
value1, value2, value3, value4);
if (value1 !== 1) begin
$display("FAILED -- value1=%b", value1);
$finish;
end
if (value2 !== 2) begin
$display("FAILED -- value2=%b", value2);
$finish;
end
if (value3 !== 3) begin
$display("FAILED -- value3=%b", value3);
$finish;
end
if (value4 !== 7) begin
$display("FAILED -- value4=%b", value4);
$finish;
end
$display("PASSED");
end
endmodule // main
module dut(output wire [2:0] value);
parameter select = 0;
case (select)
0: assign value = 0;
1: assign value = 1;
2: assign value = 2;
3: assign value = 3;
default:
assign value = 7;
endcase // case endcase
endmodule // dut
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Top level module for a full setup with DUCs and DDCs
// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
// for debugging info. NB, This can kill the m'board and/or d'board if you
// have anything except basic d'boards installed.
// Uncomment the following to include optional circuitry
module usrp_sounder
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
output wire [13:0] tx_b,
output wire TXSYNC_A,
output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [2:0] usbctl,
output wire [1:0] usbrdy,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
inout wire [15:0] io_rx_b
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
// wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_pkt_rdy;
assign usbrdy[0] = 1'b0; // have_space;
assign usbrdy[1] = have_pkt_rdy;
wire tx_underrun, rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = 1'b0; // tx_underrun;
wire [15:0] usbdata_out;
wire [3:0] rx_numchan;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
assign clk64 = master_clk;
// TX
wire tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
wire [13:0] tx_i, tx_q;
wire [13:0] tx_dac;
dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
.strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
.tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
assign tx_a = tx_dac;
// Wedge DAC #2 at zero
assign TXSYNC_B = 1'b0;
assign tx_b = 14'b0;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
wire rx_sample_strobe, rx_strobe;
wire [15:0] rx_adc0_i, rx_adc0_q;
wire [15:0] rx_buf_i, rx_buf_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
.rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
.ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
.ddc1_in_i(),.ddc1_in_q(),
.ddc2_in_i(),.ddc2_in_q(),
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(rx_buf_i),.ch_1(rx_buf_q),
.ch_2(),.ch_3(),
.ch_4(),.ch_5(),
.ch_6(),.ch_7(),
.rxclk(clk64),.rxstrobe(rx_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.debugbus() );
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Top level application
sounder sounder
( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
.rx_strobe_o(rx_strobe),.rx_imp_i_o(rx_buf_i),.rx_imp_q_o(rx_buf_q)
);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = 0; // `TX_CAP_HB;
assign capabilities[6:4] = 2; // `TX_CAP_NCHAN;
assign capabilities[3] = 0; // `RX_CAP_HB;
assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(),.readback_5(),.readback_6(),.readback_7()
);
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(),.decim_rate(),
.tx_sample_strobe(),.strobe_interp(),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
.tx_empty(tx_empty),
.debug_0(),.debug_1(),
.debug_2(),.debug_3(),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
endmodule // usrp_sounder
|
module wrapper
(
input USER_RESET,
output SPI_SCK,
output [0:0] SPI_CS_n,
inout SPI_IO1,
inout SPI_IO2,
inout SPI_IO3,
inout SPI_IO4,
input USER_CLOCK,
input GPIO_DIP1,
input GPIO_DIP2,
input GPIO_DIP3,
input GPIO_DIP4,
output [3:0] GPIO_LED,
input USB_RS232_RXD,
output USB_RS232_TXD,
inout SCL,
input SDA,
output [12:0] LPDDR_A,
output [1:0] LPDDR_BA,
inout [15:0] LPDDR_DQ,
output LPDDR_LDM,
output LPDDR_UDM,
inout LPDDR_LDQS,
inout LPDDR_UDQS,
output LPDDR_CK_N,
output LPDDR_CK_P,
output LPDDR_CKE,
output LPDDR_CAS_n,
output LPDDR_RAS_n,
output LPDDR_WE_n,
output LPDDR_RZQ,
input ETH_COL,
input ETH_CRS,
input ETH_MDC,
input ETH_MDIO,
output ETH_RESET_n,
input ETH_RX_CLK,
input [3:0] ETH_RX_D,
input ETH_RX_DV,
input ETH_RX_ER,
input ETH_TX_CLK,
output [3:0] ETH_TX_D,
output ETH_TX_EN
);
wire [7:0] led;
assign GPIO_LED = led[3:0];
system #(
.CLKSPEED(40000000),
.BAUD(115200),
.SEVEN_SEG_DUTY_CYCLE(7)
) system (
.clk(USER_CLOCK),
.sw({4'b0, GPIO_DIP4, GPIO_DIP3, GPIO_DIP2, GPIO_DIP1}),
.led(led),
.rxd(USB_RS232_RXD),
.txd(USB_RS232_TXD),
.seg(),
.an(),
.select(!USER_RESET)
);
// Sensible defaults for AVNet On-board peripherals
assign SPI_SCK = 1'b1;
assign SPI_CS_n = 1'b1;
assign SPI_IO1 = 1'bz;
assign SPI_IO2 = 1'bz;
assign SPI_IO3 = 1'bz;
assign SPI_IO4 = 1'bz;
assign SCL = 1'bz;
assign LPDDR_A = 13'b0;
assign LPDDR_BA = 1'b0;
assign LPDDR_DQ = 16'bz;
assign LPDDR_LDM = 1'b0;
assign LPDDR_UDM = 1'b0;
assign LPDDR_LDQS = 1'bz;
assign LPDDR_UDQS = 1'bz;
assign LPDDR_CKE = 1'b0;
assign LPDDR_CAS_n = 1'b1;
assign LPDDR_RAS_n = 1'b1;
assign LPDDR_WE_n = 1'b1;
assign LPDDR_RZQ = 1'bz;
assign ETH_RESET_n = 1'b1;
assign ETH_TX_D = 4'bz;
assign ETH_TX_EN = 1'b0;
OBUFDS LPDDR_CK_inst (
.O(LPDDR_CK_P), // Diff_p output (connect directly to top-level port)
.OB(LPDDR_CK_N), // Diff_n output (connect directly to top-level port)
.I(1'b0)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind relational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : relation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : relation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : relation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : relation A) :=
asymmetry : forall {x y}, R x y -> R y x -> False.
Class Transitive (R : relation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : relation A) : Prop := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence relations. *)
Class Equivalence (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(E:Equivalence R) : PER R | 10 :=
{ }.
(** An Equivalence is a PreOrder plus symmetry. *)
Global Instance Equivalence_PreOrder {R} `(E:Equivalence R) : PreOrder R | 10 :=
{ }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : relation A) : Prop :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros. red in H0. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : relation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Global Instance equivalence_rewrite_relation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite relations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Arguments irreflexivity {A R Irreflexive} [x] _.
Arguments symmetry {A} {R} {_} [x] [y] _.
Arguments asymmetry {A} {R} {_} [x] [y] _ _.
Arguments transitivity {A} {R} {_} [x] [y] [z] _ _.
Arguments Antisymmetric A eqA {_} _.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(* Note, we do not use [list Type] because it imposes unnecessary universe constraints *)
#[universes(template)]
Inductive Tlist : Type := Tnil : Tlist | Tcons : Type -> Tlist -> Tlist.
Local Infix "::" := Tcons.
Fixpoint arrows (l : Tlist) (r : Type) : Type :=
match l with
| Tnil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::Tnil) A.
Definition binary_operation A := arrows (A::A::Tnil) A.
Definition ternary_operation A := arrows (A::A::A::Tnil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::Tnil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::Tnil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : Tlist) : binary_operation (arrows l T) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : Tlist) : binary_relation (predicate l) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : Tlist} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : Tlist} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Declare Scope predicate_scope.
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Local Open Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l.
- firstorder.
- intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l.
- firstorder.
- unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : relation (relation A) :=
@predicate_equivalence (_::_::Tnil).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::Tnil) R R'.
Definition relation_disjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::Tnil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. exact (@predicate_equivalence_equivalence (A::A::Tnil)). Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::Tnil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. firstorder. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_7_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_7_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_7_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:10 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_stub.v
// Design : ip_design_nco_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "nco,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule
|
(** * Sub: Subtyping *)
Require Export Types.
(* ###################################################### *)
(** * Concepts *)
(** We now turn to the study of _subtyping_, perhaps the most
characteristic feature of the static type systems of recently
designed programming languages and a key feature needed to support
the object-oriented programming style. *)
(* ###################################################### *)
(** ** A Motivating Example *)
(** Suppose we are writing a program involving two record types
defined as follows:
<<
Person = {name:String, age:Nat}
Student = {name:String, age:Nat, gpa:Nat}
>>
*)
(** In the simply typed lamdba-calculus with records, the term
<<
(\r:Person. (r.age)+1) {name="Pat",age=21,gpa=1}
>>
is not typable: it involves an application of a function that wants
a one-field record to an argument that actually provides two
fields, while the [T_App] rule demands that the domain type of the
function being applied must match the type of the argument
precisely.
But this is silly: we're passing the function a _better_ argument
than it needs! The only thing the body of the function can
possibly do with its record argument [r] is project the field [age]
from it: nothing else is allowed by the type, and the presence or
absence of an extra [gpa] field makes no difference at all. So,
intuitively, it seems that this function should be applicable to
any record value that has at least an [age] field.
Looking at the same thing from another point of view, a record with
more fields is "at least as good in any context" as one with just a
subset of these fields, in the sense that any value belonging to
the longer record type can be used _safely_ in any context
expecting the shorter record type. If the context expects
something with the shorter type but we actually give it something
with the longer type, nothing bad will happen (formally, the
program will not get stuck).
The general principle at work here is called _subtyping_. We say
that "[S] is a subtype of [T]", informally written [S <: T], if a
value of type [S] can safely be used in any context where a value
of type [T] is expected. The idea of subtyping applies not only to
records, but to all of the type constructors in the language --
functions, pairs, etc. *)
(** ** Subtyping and Object-Oriented Languages *)
(** Subtyping plays a fundamental role in many programming
languages -- in particular, it is closely related to the notion of
_subclassing_ in object-oriented languages.
An _object_ in Java, C[#], etc. can be thought of as a record,
some of whose fields are functions ("methods") and some of whose
fields are data values ("fields" or "instance variables").
Invoking a method [m] of an object [o] on some arguments [a1..an]
consists of projecting out the [m] field of [o] and applying it to
[a1..an].
The type of an object can be given as either a _class_ or an
_interface_. Both of these provide a description of which methods
and which data fields the object offers.
Classes and interfaces are related by the _subclass_ and
_subinterface_ relations. An object belonging to a subclass (or
subinterface) is required to provide all the methods and fields of
one belonging to a superclass (or superinterface), plus possibly
some more.
The fact that an object from a subclass (or sub-interface) can be
used in place of one from a superclass (or super-interface)
provides a degree of flexibility that is is extremely handy for
organizing complex libraries. For example, a GUI toolkit like
Java's Swing framework might define an abstract interface
[Component] that collects together the common fields and methods
of all objects having a graphical representation that can be
displayed on the screen and that can interact with the user.
Examples of such object would include the buttons, checkboxes, and
scrollbars of a typical GUI. A method that relies only on this
common interface can now be applied to any of these objects.
Of course, real object-oriented languages include many other
features besides these. For example, fields can be updated.
Fields and methods can be declared [private]. Classes also give
_code_ that is used when constructing objects and implementing
their methods, and the code in subclasses cooperate with code in
superclasses via _inheritance_. Classes can have static methods
and fields, initializers, etc., etc.
To keep things simple here, we won't deal with any of these
issues -- in fact, we won't even talk any more about objects or
classes. (There is a lot of discussion in _Types and Programming
Languages_, if you are interested.) Instead, we'll study the core
concepts behind the subclass / subinterface relation in the
simplified setting of the STLC. *)
(** *** *)
(** Of course, real OO languages have lots of other features...
- mutable fields
- [private] and other visibility modifiers
- method inheritance
- static components
- etc., etc.
We'll ignore all these and focus on core mechanisms. *)
(** ** The Subsumption Rule *)
(** Our goal for this chapter is to add subtyping to the simply typed
lambda-calculus (with some of the basic extensions from [MoreStlc]).
This involves two steps:
- Defining a binary _subtype relation_ between types.
- Enriching the typing relation to take subtyping into account.
The second step is actually very simple. We add just a single rule
to the typing relation: the so-called _rule of subsumption_:
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
This rule says, intuitively, that it is OK to "forget" some of
what we know about a term. *)
(** For example, we may know that [t] is a record with two
fields (e.g., [S = {x:A->A, y:B->B}]), but choose to forget about
one of the fields ([T = {y:B->B}]) so that we can pass [t] to a
function that requires just a single-field record. *)
(** ** The Subtype Relation *)
(** The first step -- the definition of the relation [S <: T] -- is
where all the action is. Let's look at each of the clauses of its
definition. *)
(** *** Structural Rules *)
(** To start off, we impose two "structural rules" that are
independent of any particular type constructor: a rule of
_transitivity_, which says intuitively that, if [S] is better than
[U] and [U] is better than [T], then [S] is better than [T]...
S <: U U <: T
---------------- (S_Trans)
S <: T
... and a rule of _reflexivity_, since certainly any type [T] is
as good as itself:
------ (S_Refl)
T <: T
*)
(** *** Products *)
(** Now we consider the individual type constructors, one by one,
beginning with product types. We consider one pair to be "better
than" another if each of its components is.
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
*)
(** *** Arrows *)
(** Suppose we have two functions [f] and [g] with these types:
f : C -> Student
g : (C->Person) -> D
That is, [f] is a function that yields a record of type [Student],
and [g] is a (higher-order) function that expects its (function)
argument to yield a record of type [Person]. Also suppose, even
though we haven't yet discussed subtyping for records, that
[Student] is a subtype of [Person]. Then the application [g f] is
safe even though their types do not match up precisely, because
the only thing [g] can do with [f] is to apply it to some
argument (of type [C]); the result will actually be a [Student],
while [g] will be expecting a [Person], but this is safe because
the only thing [g] can then do is to project out the two fields
that it knows about ([name] and [age]), and these will certainly
be among the fields that are present.
This example suggests that the subtyping rule for arrow types
should say that two arrow types are in the subtype relation if
their results are:
S2 <: T2
---------------- (S_Arrow_Co)
S1 -> S2 <: S1 -> T2
We can generalize this to allow the arguments of the two arrow
types to be in the subtype relation as well:
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
Notice that the argument types are subtypes "the other way round":
in order to conclude that [S1->S2] to be a subtype of [T1->T2], it
must be the case that [T1] is a subtype of [S1]. The arrow
constructor is said to be _contravariant_ in its first argument
and _covariant_ in its second.
Here is an example that illustrates this:
f : Person -> C
g : (Student -> C) -> D
The application [g f] is safe, because the only thing the body of
[g] can do with [f] is to apply it to some argument of type
[Student]. Since [f] requires records having (at least) the
fields of a [Person], this will always work. So [Person -> C] is a
subtype of [Student -> C] since [Student] is a subtype of
[Person].
The intuition is that, if we have a function [f] of type [S1->S2],
then we know that [f] accepts elements of type [S1]; clearly, [f]
will also accept elements of any subtype [T1] of [S1]. The type of
[f] also tells us that it returns elements of type [S2]; we can
also view these results belonging to any supertype [T2] of
[S2]. That is, any function [f] of type [S1->S2] can also be
viewed as having type [T1->T2].
*)
(** *** Records *)
(** What about subtyping for record types? *)
(** The basic intuition about subtyping for record types is that it is
always safe to use a "bigger" record in place of a "smaller" one.
That is, given a record type, adding extra fields will always
result in a subtype. If some code is expecting a record with
fields [x] and [y], it is perfectly safe for it to receive a record
with fields [x], [y], and [z]; the [z] field will simply be ignored.
For example,
{name:String, age:Nat, gpa:Nat} <: {name:String, age:Nat}
{name:String, age:Nat} <: {name:String}
{name:String} <: {}
This is known as "width subtyping" for records. *)
(** We can also create a subtype of a record type by replacing the type
of one of its fields with a subtype. If some code is expecting a
record with a field [x] of type [T], it will be happy with a record
having a field [x] of type [S] as long as [S] is a subtype of
[T]. For example,
{x:Student} <: {x:Person}
This is known as "depth subtyping". *)
(** Finally, although the fields of a record type are written in a
particular order, the order does not really matter. For example,
{name:String,age:Nat} <: {age:Nat,name:String}
This is known as "permutation subtyping". *)
(** We could formalize these requirements in a single subtyping rule
for records as follows:
for each jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
That is, the record on the left should have all the field labels of
the one on the right (and possibly more), while the types of the
common fields should be in the subtype relation. However, this rule
is rather heavy and hard to read. If we like, we can decompose it
into three simpler rules, which can be combined using [S_Trans] to
achieve all the same effects. *)
(** First, adding fields to the end of a record type gives a subtype:
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
We can use [S_RcdWidth] to drop later fields of a multi-field
record while keeping earlier fields, showing for example that
[{age:Nat,name:String} <: {name:String}]. *)
(** Second, we can apply subtyping inside the components of a compound
record type:
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
For example, we can use [S_RcdDepth] and [S_RcdWidth] together to
show that [{y:Student, x:Nat} <: {y:Person}]. *)
(** Third, we need to be able to reorder fields. For example, we
might expect that [{name:String, gpa:Nat, age:Nat} <: Person]. We
haven't quite achieved this yet: using just [S_RcdDepth] and
[S_RcdWidth] we can only drop fields from the _end_ of a record
type. So we need:
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(** It is worth noting that full-blown language designs may choose not
to adopt all of these subtyping rules. For example, in Java:
- A subclass may not change the argument or result types of a
method of its superclass (i.e., no depth subtyping or no arrow
subtyping, depending how you look at it).
- Each class has just one superclass ("single inheritance" of
classes).
- Each class member (field or method) can be assigned a single
index, adding new indices "on the right" as more members are
added in subclasses (i.e., no permutation for classes).
- A class may implement multiple interfaces -- so-called "multiple
inheritance" of interfaces (i.e., permutation is allowed for
interfaces). *)
(** **** Exercise: 2 stars (arrow_sub_wrong) *)
(** Suppose we had incorrectly defined subtyping as covariant on both
the right and the left of arrow types:
S1 <: T1 S2 <: T2
-------------------- (S_Arrow_wrong)
S1 -> S2 <: T1 -> T2
Give a concrete example of functions [f] and [g] with the following types...
f : Student -> Nat
g : (Person -> Nat) -> Nat
... such that the application [g f] will get stuck during
execution.
[] *)
(** *** Top *)
(** Finally, it is natural to give the subtype relation a maximal
element -- a type that lies above every other type and is
inhabited by all (well-typed) values. We do this by adding to the
language one new type constant, called [Top], together with a
subtyping rule that places it above every other type in the
subtype relation:
-------- (S_Top)
S <: Top
The [Top] type is an analog of the [Object] type in Java and C[#]. *)
(* ############################################### *)
(** *** Summary *)
(** In summary, we form the STLC with subtyping by starting with the
pure STLC (over some set of base types) and...
- adding a base type [Top],
- adding the rule of subsumption
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
to the typing relation, and
- defining a subtype relation as follows:
S <: U U <: T
---------------- (S_Trans)
S <: T
------ (S_Refl)
T <: T
-------- (S_Top)
S <: Top
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1 * S2 <: T1 * T2
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1 -> S2 <: T1 -> T2
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
*)
(* ############################################### *)
(** ** Exercises *)
(** **** Exercise: 1 star, optional (subtype_instances_tf_1) *)
(** Suppose we have types [S], [T], [U], and [V] with [S <: T]
and [U <: V]. Which of the following subtyping assertions
are then true? Write _true_ or _false_ after each one.
([A], [B], and [C] here are base types.)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[] *)
(** **** Exercise: 2 stars (subtype_order) *)
(** The following types happen to form a linear order with respect to subtyping:
- [Top]
- [Top -> Student]
- [Student -> Person]
- [Student -> Top]
- [Person -> Student]
Write these types in order from the most specific to the most general.
Where does the type [Top->Top->Student] fit into this order?
*)
(** **** Exercise: 1 star (subtype_instances_tf_2) *)
(** Which of the following statements are true? Write _true_ or
_false_ after each one.
forall S T,
S <: T ->
S->S <: T->T
forall S,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T2,
(S <: T1 -> T2) ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T1 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
[] *)
(** **** Exercise: 1 star (subtype_concepts_tf) *)
(** Which of the following statements are true, and which are false?
- There exists a type that is a supertype of every other type.
- There exists a type that is a subtype of every other type.
- There exists a pair type that is a supertype of every other
pair type.
- There exists a pair type that is a subtype of every other
pair type.
- There exists an arrow type that is a supertype of every other
arrow type.
- There exists an arrow type that is a subtype of every other
arrow type.
- There is an infinite descending chain of distinct types in the
subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a subtype of [Si].
- There is an infinite _ascending_ chain of distinct types in
the subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a supertype of [Si].
[] *)
(** **** Exercise: 2 stars (proper_subtypes) *)
(** Is the following statement true or false? Briefly explain your
answer.
forall T,
~(exists n, T = TBase n) ->
exists S,
S <: T /\ S <> T
]]
[] *)
(** **** Exercise: 2 stars (small_large_1) *)
(**
- What is the _smallest_ type [T] ("smallest" in the subtype
relation) that makes the following assertion true? (Assume we
have [Unit] among the base types and [unit] as a constant of this
type.)
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_2) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars, optional (small_large_3) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
- What is the _largest_ type [T] that makes the same assertion true?
[] *)
(** **** Exercise: 2 stars (small_large_4) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
- What is the _largest_ type [T] that makes the same
assertion true?
[] *)
(** **** Exercise: 2 stars (smallest_1) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[] *)
(** **** Exercise: 2 stars (smallest_2) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[] *)
(** **** Exercise: 3 stars, optional (count_supertypes) *)
(** How many supertypes does the record type [{x:A, y:C->C}] have? That is,
how many different types [T] are there such that [{x:A, y:C->C} <:
T]? (We consider two types to be different if they are written
differently, even if each is a subtype of the other. For example,
[{x:A,y:B}] and [{y:B,x:A}] are different.)
[] *)
(** **** Exercise: 2 stars (pair_permutation) *)
(** The subtyping rule for product types
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1*S2 <: T1*T2
intuitively corresponds to the "depth" subtyping rule for records. Extending the analogy, we might consider adding a "permutation" rule
--------------
T1*T2 <: T2*T1
for products.
Is this a good idea? Briefly explain why or why not.
[] *)
(* ###################################################### *)
(** * Formal Definitions *)
(** Most of the definitions -- in particular, the syntax and
operational semantics of the language -- are identical to what we
saw in the last chapter. We just need to extend the typing
relation with the subsumption rule and add a new [Inductive]
definition for the subtyping relation. Let's first do the
identical bits. *)
(* ###################################################### *)
(** ** Core Definitions *)
(* ################################### *)
(** *** Syntax *)
(** For the sake of more interesting examples below, we'll allow an
arbitrary set of additional base types like [String], [Float],
etc. We won't bother adding any constants belonging to these
types or any operators on them, but we could easily do so. *)
(** In the rest of the chapter, we formalize just base types,
booleans, arrow types, [Unit], and [Top], omitting record types
and leaving product types as an exercise. *)
Inductive ty : Type :=
| TTop : ty
| TBool : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
| TUnit : ty
.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TTop" | Case_aux c "TBool"
| Case_aux c "TBase" | Case_aux c "TArrow"
| Case_aux c "TUnit" |
].
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tunit : tm
.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif"
| Case_aux c "tunit"
].
(* ################################### *)
(** *** Substitution *)
(** The definition of substitution remains exactly the same as for the
pure STLC. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
tunit
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
(** Likewise the definitions of the [value] property and the [step]
relation. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse
| v_unit :
value tunit
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
].
Hint Constructors step.
(* ###################################################################### *)
(** ** Subtyping *)
(** Now we come to the most interesting part. We begin by
defining the subtyping relation and developing some of its
important technical properties. *)
(** The definition of subtyping is just what we sketched in the
motivating discussion. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
| S_Refl : forall T,
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
(TArrow S1 S2) <: (TArrow T1 T2)
where "T '<:' U" := (subtype T U).
(** Note that we don't need any special rules for base types: they are
automatically subtypes of themselves (by [S_Refl]) and [Top] (by
[S_Top]), and that's all we want. *)
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans"
| Case_aux c "S_Top" | Case_aux c "S_Arrow"
].
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Notation String := (TBase (Id 9)).
Notation Float := (TBase (Id 10)).
Notation Integer := (TBase (Id 11)).
(** **** Exercise: 2 stars, optional (subtyping_judgements) *)
(** (Do this exercise after you have added product types to the
language, at least up to this point in the file).
Using the encoding of records into pairs, define pair types
representing the record types
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
Recall that in chapter MoreStlc, the optional subsection "Encoding
Records" describes how records can be encoded as pairs.
*)
Definition Person : ty :=
(* FILL IN HERE *) admit.
Definition Student : ty :=
(* FILL IN HERE *) admit.
Definition Employee : ty :=
(* FILL IN HERE *) admit.
Example sub_student_person :
Student <: Person.
Proof.
(* FILL IN HERE *) Admitted.
Example sub_employee_person :
Employee <: Person.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Example subtyping_example_0 :
(TArrow C Person) <: (TArrow C TTop).
(* C->Person <: C->Top *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 1 star, optional (subtyping_example_1) *)
Example subtyping_example_1 :
(TArrow TTop Student) <: (TArrow (TArrow C C) Person).
(* Top->Student <: (C->C)->Person *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (subtyping_example_2) *)
Example subtyping_example_2 :
(TArrow TTop Person) <: (TArrow Person TTop).
(* Top->Person <: Person->Top *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ###################################################################### *)
(** ** Typing *)
(** The only change to the typing relation is the addition of the rule
of subsumption, [T_Sub]. *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Same as before *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- (tif t1 t2 t3) \in T
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* New rule of subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
S <: T ->
Gamma |- t \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Unit"
| Case_aux c "T_Sub" ].
(* To make your job simpler, the following hints help construct typing
derivations. *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ############################################### *)
(** ** Typing examples *)
Module Examples2.
Import Examples.
(** Do the following exercises after you have added product types to
the language. For each informal typing judgement, write it as a
formal statement in Coq and prove it. *)
(** **** Exercise: 1 star, optional (typing_example_0) *)
(* empty |- ((\z:A.z), (\z:B.z))
: (A->A * B->B) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_1) *)
(* empty |- (\x:(Top * B->B). x.snd) ((\z:A.z), (\z:B.z))
: B->B *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
(* empty |- (\z:(C->C)->(Top * B->B). (z (\x:C.x)).snd)
(\z:C->C. ((\z:A.z), (\z:B.z)))
: B->B *)
(* FILL IN HERE *)
(** [] *)
End Examples2.
(* ###################################################################### *)
(** * Properties *)
(** The fundamental properties of the system that we want to check are
the same as always: progress and preservation. Unlike the
extension of the STLC with references, we don't need to change the
_statements_ of these properties to take subtyping into account.
However, their proofs do become a little bit more involved. *)
(* ###################################################################### *)
(** ** Inversion Lemmas for Subtyping *)
(** Before we look at the properties of the typing relation, we need
to record a couple of critical structural properties of the subtype
relation:
- [Bool] is the only subtype of [Bool]
- every subtype of an arrow type is itself an arrow type. *)
(** These are called _inversion lemmas_ because they play the same
role in later proofs as the built-in [inversion] tactic: given a
hypothesis that there exists a derivation of some subtyping
statement [S <: T] and some constraints on the shape of [S] and/or
[T], each one reasons about what this derivation must look like to
tell us something further about the shapes of [S] and [T] and the
existence of subtype relations between their parts. *)
(** **** Exercise: 2 stars, optional (sub_inversion_Bool) *)
Lemma sub_inversion_Bool : forall U,
U <: TBool ->
U = TBool.
Proof with auto.
intros U Hs.
remember TBool as V.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
U <: (TArrow V1 V2) ->
exists U1, exists U2,
U = (TArrow U1 U2) /\ (V1 <: U1) /\ (U2 <: V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################## *)
(** ** Canonical Forms *)
(** We'll see first that the proof of the progress theorem doesn't
change too much -- we just need one small refinement. When we're
considering the case where the term in question is an application
[t1 t2] where both [t1] and [t2] are values, we need to know that
[t1] has the _form_ of a lambda-abstraction, so that we can apply
the [ST_AppAbs] reduction rule. In the ordinary STLC, this is
obvious: we know that [t1] has a function type [T11->T12], and
there is only one rule that can be used to give a function type to
a value -- rule [T_Abs] -- and the form of the conclusion of this
rule forces [t1] to be an abstraction.
In the STLC with subtyping, this reasoning doesn't quite work
because there's another rule that can be used to show that a value
has a function type: subsumption. Fortunately, this possibility
doesn't change things much: if the last rule used to show [Gamma
|- t1 : T11->T12] is subsumption, then there is some
_sub_-derivation whose subject is also [t1], and we can reason by
induction until we finally bottom out at a use of [T_Abs].
This bit of reasoning is packaged up in the following lemma, which
tells us the possible "canonical forms" (i.e. values) of function
type. *)
(** **** Exercise: 3 stars, optional (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
Gamma |- s \in (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, the canonical forms of type [Bool] are the constants
[true] and [false]. *)
Lemma canonical_forms_of_Bool : forall Gamma s,
Gamma |- s \in TBool ->
value s ->
(s = ttrue \/ s = tfalse).
Proof with eauto.
intros Gamma s Hty Hv.
remember TBool as T.
has_type_cases (induction Hty) Case; try solve by inversion...
Case "T_Sub".
subst. apply sub_inversion_Bool in H. subst...
Qed.
(* ########################################## *)
(** ** Progress *)
(** The proof of progress proceeds like the one for the pure
STLC, except that in several places we invoke canonical forms
lemmas... *)
(** _Theorem_ (Progress): For any term [t] and type [T], if [empty |-
t : T] then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given, with [empty |- t : T]. Proceed
by induction on the typing derivation.
The cases for [T_Abs], [T_Unit], [T_True] and [T_False] are
immediate because abstractions, [unit], [true], and [false] are
already values. The [T_Var] case is vacuous because variables
cannot be typed in the empty context. The remaining cases are
more interesting:
- If the last step in the typing derivation uses rule [T_App],
then there are terms [t1] [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and [empty |-
t2 : T1]. Moreover, by the induction hypothesis, either [t1] is
a value or it steps, and either [t2] is a value or it steps.
There are three possibilities to consider:
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==> t1' t2]
by [ST_App1].
- Suppose [t1] is a value and [t2 ==> t2'] for some term [t2'].
Then [t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a
value.
- Finally, suppose [t1] and [t2] are both values. By Lemma
[canonical_forms_for_arrow_types], we know that [t1] has the
form [\x:S1.s2] for some [x], [S1], and [s2]. But then
[(\x:S1.s2) t2 ==> [x:=t2]s2] by [ST_AppAbs], since [t2] is a
value.
- If the final step of the derivation uses rule [T_If], then there
are terms [t1], [t2], and [t3] such that [t = if t1 then t2 else
t3], with [empty |- t1 : Bool] and with [empty |- t2 : T] and
[empty |- t3 : T]. Moreover, by the induction hypothesis,
either [t1] is a value or it steps.
- If [t1] is a value, then by the canonical forms lemma for
booleans, either [t1 = true] or [t1 = false]. In either
case, [t] can step, using rule [ST_IfTrue] or [ST_IfFalse].
- If [t1] can step, then so can [t], by rule [ST_If].
- If the final step of the derivation is by [T_Sub], then there is
a type [S] such that [S <: T] and [empty |- t : S]. The desired
result is exactly the induction hypothesis for the typing
subderivation.
*)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
SSCase "t2 steps".
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right.
destruct IHHt1.
SCase "t1 is a value"...
assert (t1 = ttrue \/ t1 = tfalse)
by (eapply canonical_forms_of_Bool; eauto).
inversion H0; subst...
inversion H. rename x into t1'. eauto.
Qed.
(* ########################################## *)
(** ** Inversion Lemmas for Typing *)
(** The proof of the preservation theorem also becomes a little more
complex with the addition of subtyping. The reason is that, as
with the "inversion lemmas for subtyping" above, there are a
number of facts about the typing relation that are "obvious from
the definition" in the pure STLC (and hence can be obtained
directly from the [inversion] tactic) but that require real proofs
in the presence of subtyping because there are multiple ways to
derive the same [has_type] statement.
The following "inversion lemma" tells us that, if we have a
derivation of some typing statement [Gamma |- \x:S1.t2 : T] whose
subject is an abstraction, then there must be some subderivation
giving a type to the body [t2]. *)
(** _Lemma_: If [Gamma |- \x:S1.t2 : T], then there is a type [S2]
such that [Gamma, x:S1 |- t2 : S2] and [S1 -> S2 <: T].
(Notice that the lemma does _not_ say, "then [T] itself is an arrow
type" -- this is tempting, but false!)
_Proof_: Let [Gamma], [x], [S1], [t2] and [T] be given as
described. Proceed by induction on the derivation of [Gamma |-
\x:S1.t2 : T]. Cases [T_Var], [T_App], are vacuous as those
rules cannot be used to give a type to a syntactic abstraction.
- If the last step of the derivation is a use of [T_Abs] then
there is a type [T12] such that [T = S1 -> T12] and [Gamma,
x:S1 |- t2 : T12]. Picking [T12] for [S2] gives us what we
need: [S1 -> T12 <: S1 -> T12] follows from [S_Refl].
- If the last step of the derivation is a use of [T_Sub] then
there is a type [S] such that [S <: T] and [Gamma |- \x:S1.t2 :
S]. The IH for the typing subderivation tell us that there is
some type [S2] with [S1 -> S2 <: S] and [Gamma, x:S1 |- t2 :
S2]. Picking type [S2] gives us what we need, since [S1 -> S2
<: T] then follows by [S_Trans]. *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
Gamma |- (tabs x S1 t2) \in T ->
(exists S2, (TArrow S1 S2) <: T
/\ (extend Gamma x S1) |- t2 \in S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
(** Similarly... *)
Lemma typing_inversion_var : forall Gamma x T,
Gamma |- (tvar x) \in T ->
exists S,
Gamma x = Some S /\ S <: T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
Gamma |- (tapp t1 t2) \in T2 ->
exists T1,
Gamma |- t1 \in (TArrow T1 T2) /\
Gamma |- t2 \in T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
Qed.
Lemma typing_inversion_true : forall Gamma T,
Gamma |- ttrue \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember ttrue as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_false : forall Gamma T,
Gamma |- tfalse \in T ->
TBool <: T.
Proof with eauto.
intros Gamma T Htyp. remember tfalse as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_if : forall Gamma t1 t2 t3 T,
Gamma |- (tif t1 t2 t3) \in T ->
Gamma |- t1 \in TBool
/\ Gamma |- t2 \in T
/\ Gamma |- t3 \in T.
Proof with eauto.
intros Gamma t1 t2 t3 T Hty.
remember (tif t1 t2 t3) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_If".
auto.
Case "T_Sub".
destruct (IHHty H0) as [H1 [H2 H3]]...
Qed.
Lemma typing_inversion_unit : forall Gamma T,
Gamma |- tunit \in T ->
TUnit <: T.
Proof with eauto.
intros Gamma T Htyp. remember tunit as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
(** The inversion lemmas for typing and for subtyping between arrow
types can be packaged up as a useful "combination lemma" telling
us exactly what we'll actually require below. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
empty |- (tabs x S1 s2) \in (TArrow T1 T2) ->
T1 <: S1
/\ (extend empty x S1) |- s2 \in T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
inversion Hty as [S2 [Hsub Hty1]].
apply sub_inversion_arrow in Hsub.
inversion Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** ** Context Invariance *)
(** The context invariance lemma follows the same pattern as in the
pure STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. destruct (eq_id_dec x x0)...
Case "T_If".
apply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case;
subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H4) as [T Hctx]. exists T.
unfold extend in Hctx. rewrite neq_id in Hctx... Qed.
(* ########################################## *)
(** ** Substitution *)
(** The _substitution lemma_ is proved along the same lines as
for the pure STLC. The only significant change is that there are
several places where, instead of the built-in [inversion] tactic,
we need to use the inversion lemmas that we proved above to
extract structural information from assumptions about the
well-typedness of subterms. *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt)
as [T [Hctx Hsub]].
unfold extend in Hctx.
destruct (eq_id_dec x y)...
SCase "x=y".
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra)
as [T' HT']...
inversion HT'.
Case "tapp".
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tabs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Case "ttrue".
assert (TBool <: S)
by apply (typing_inversion_true _ _ Htypt)...
Case "tfalse".
assert (TBool <: S)
by apply (typing_inversion_false _ _ Htypt)...
Case "tif".
assert ((extend Gamma x U) |- t1 \in TBool
/\ (extend Gamma x U) |- t2 \in S
/\ (extend Gamma x U) |- t3 \in S)
by apply (typing_inversion_if _ _ _ _ _ Htypt).
inversion H as [H1 [H2 H3]].
apply IHt1 in H1. apply IHt2 in H2. apply IHt3 in H3.
auto.
Case "tunit".
assert (TUnit <: S)
by apply (typing_inversion_unit _ _ Htypt)...
Qed.
(* ########################################## *)
(** ** Preservation *)
(** The proof of preservation now proceeds pretty much as in earlier
chapters, using the substitution lemma at the appropriate point
and again using inversion lemmas from above to extract structural
information from typing assumptions. *)
(** _Theorem_ (Preservation): If [t], [t'] are terms and [T] is a type
such that [empty |- t : T] and [t ==> t'], then [empty |- t' :
T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the structure of this typing derivation,
leaving [t'] general. The cases [T_Abs], [T_Unit], [T_True], and
[T_False] cases are vacuous because abstractions and constants
don't step. Case [T_Var] is vacuous as well, since the context is
empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] and [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and
[empty |- t2 : T1].
By the definition of the step relation, there are three ways
[t1 t2] can step. Cases [ST_App1] and [ST_App2] follow
immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then [t1 =
\x:S.t12] for some type [S] and term [t12], and [t' =
[x:=t2]t12].
By lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by the substitution lemma
([substitution_preserves_typing]) that [empty |- [x:=t2]
t12 : T2] as desired.
- If the final step of the derivation uses rule [T_If], then
there are terms [t1], [t2], and [t3] such that [t = if t1 then
t2 else t3], with [empty |- t1 : Bool] and with [empty |- t2 :
T] and [empty |- t3 : T]. Moreover, by the induction
hypothesis, if [t1] steps to [t1'] then [empty |- t1' : Bool].
There are three cases to consider, depending on which rule was
used to show [t ==> t'].
- If [t ==> t'] by rule [ST_If], then [t' = if t1' then t2
else t3] with [t1 ==> t1']. By the induction hypothesis,
[empty |- t1' : Bool], and so [empty |- t' : T] by [T_If].
- If [t ==> t'] by rule [ST_IfTrue] or [ST_IfFalse], then
either [t' = t2] or [t' = t3], and [empty |- t' : T]
follows by assumption.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub]. [] *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Qed.
(** ** Records, via Products and Top *)
(** This formalization of the STLC with subtyping has omitted record
types, for brevity. If we want to deal with them more seriously,
we have two choices.
First, we can treat them as part of the core language, writing
down proper syntax, typing, and subtyping rules for them. Chapter
[RecordSub] shows how this extension works.
On the other hand, if we are treating them as a derived form that
is desugared in the parser, then we shouldn't need any new rules:
we should just check that the existing rules for subtyping product
and [Unit] types give rise to reasonable rules for record
subtyping via this encoding. To do this, we just need to make one
small change to the encoding described earlier: instead of using
[Unit] as the base case in the encoding of tuples and the "don't
care" placeholder in the encoding of records, we use [Top]. So:
<<
{a:Nat, b:Nat} ----> {Nat,Nat} i.e. (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} i.e. (Nat,(Top,(Nat,Top)))
>>
The encoding of record values doesn't change at all. It is
easy (and instructive) to check that the subtyping rules above are
validated by the encoding. For the rest of this chapter, we'll
follow this encoding-based approach. *)
(* ###################################################### *)
(** ** Exercises *)
(** **** Exercise: 2 stars (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with Unit and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
------------------ (ST_Funny21)
unit ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
-------------- (S_Funny3)
Unit <: Top->Top
- Suppose we add the following subtyping rule:
-------------- (S_Funny4)
Top->Top <: Unit
- Suppose we add the following evaluation rule:
----------------- (ST_Funny5)
(unit t) ==> (t unit)
- Suppose we add the same evaluation rule _and_ a new typing rule:
----------------- (ST_Funny5)
(unit t) ==> (t unit)
---------------------- (T_Funny6)
empty |- Unit : Top->Top
- Suppose we _change_ the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
[] *)
(* ###################################################################### *)
(** * Exercise: Adding Products *)
(** **** Exercise: 4 stars (products) *)
(** Adding pairs, projections, and product types to the system we have
defined is a relatively straightforward matter. Carry out this
extension:
- Add constructors for pairs, first and second projections, and
product types to the definitions of [ty] and [tm]. (Don't
forget to add corresponding cases to [T_cases] and [t_cases].)
- Extend the substitution function and value relation as in
MoreSTLC.
- Extend the operational semantics with the same reduction rules
as in MoreSTLC.
- Extend the subtyping relation with this rule:
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
- Extend the typing relation with the same rules for pairs and
projections as in MoreSTLC.
- Extend the proofs of progress, preservation, and all their
supporting lemmas to deal with the new constructs. (You'll also
need to add some completely new lemmas.)
[] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
// Inputs
clk, index
);
input clk;
input [9:0] index;
output [3:0] outr;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] outr;
// End of automatics
// =============================
// Created from perl
//for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i,
//rand(256); };
// Reset cheating
initial outr = 4'b0;
always @(posedge clk) begin
case (index[7:0])
8'h00: begin outr <= 4'h0; end
8'h01: begin /*No Change*/ end
8'h02: begin outr <= outr^index[8:5]^4'ha; end
8'h03: begin outr <= outr^index[8:5]^4'h4; end
8'h04: begin outr <= outr^index[8:5]^4'hd; end
8'h05: begin outr <= outr^index[8:5]^4'h1; end
8'h06: begin outr <= outr^index[8:5]^4'hf; end
8'h07: begin outr <= outr^index[8:5]^4'he; end
8'h08: begin outr <= outr^index[8:5]^4'h0; end
8'h09: begin outr <= outr^index[8:5]^4'h4; end
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
8'h10: begin outr <= outr^index[8:5]^4'h3; end
8'h11: begin outr <= outr^index[8:5]^4'hb; end
8'h12: begin outr <= outr^index[8:5]^4'h0; end
8'h13: begin outr <= outr^index[8:5]^4'hf; end
8'h14: begin outr <= outr^index[8:5]^4'h3; end
8'h15: begin outr <= outr^index[8:5]^4'h5; end
8'h16: begin outr <= outr^index[8:5]^4'h7; end
8'h17: begin outr <= outr^index[8:5]^4'h2; end
8'h18: begin outr <= outr^index[8:5]^4'h3; end
8'h19: begin outr <= outr^index[8:5]^4'hb; end
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
8'h20: begin outr <= outr^index[8:5]^4'h6; end
8'h21: begin outr <= outr^index[8:5]^4'ha; end
8'h22: begin outr <= outr^index[8:5]^4'h6; end
8'h23: begin outr <= outr^index[8:5]^4'hb; end
8'h24: begin outr <= outr^index[8:5]^4'ha; end
8'h25: begin outr <= outr^index[8:5]^4'he; end
8'h26: begin outr <= outr^index[8:5]^4'h7; end
8'h27: begin outr <= outr^index[8:5]^4'ha; end
8'h28: begin outr <= outr^index[8:5]^4'h3; end
8'h29: begin outr <= outr^index[8:5]^4'h8; end
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
8'h2e: begin outr <= outr^index[8:5]^4'he; end
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
8'h30: begin outr <= outr^index[8:5]^4'ha; end
8'h31: begin outr <= outr^index[8:5]^4'h7; end
8'h32: begin outr <= outr^index[8:5]^4'h0; end
8'h33: begin outr <= outr^index[8:5]^4'h3; end
8'h34: begin outr <= outr^index[8:5]^4'h1; end
8'h35: begin outr <= outr^index[8:5]^4'h3; end
8'h36: begin outr <= outr^index[8:5]^4'h4; end
8'h37: begin outr <= outr^index[8:5]^4'h6; end
8'h38: begin outr <= outr^index[8:5]^4'h4; end
8'h39: begin outr <= outr^index[8:5]^4'hb; end
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
8'h40: begin outr <= outr^index[8:5]^4'h7; end
8'h41: begin outr <= outr^index[8:5]^4'h5; end
8'h42: begin outr <= outr^index[8:5]^4'h5; end
8'h43: begin outr <= outr^index[8:5]^4'h4; end
8'h44: begin outr <= outr^index[8:5]^4'h8; end
8'h45: begin outr <= outr^index[8:5]^4'h5; end
8'h46: begin outr <= outr^index[8:5]^4'hf; end
8'h47: begin outr <= outr^index[8:5]^4'h6; end
8'h48: begin outr <= outr^index[8:5]^4'h7; end
8'h49: begin outr <= outr^index[8:5]^4'h4; end
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
8'h50: begin outr <= outr^index[8:5]^4'h9; end
8'h51: begin outr <= outr^index[8:5]^4'ha; end
8'h52: begin outr <= outr^index[8:5]^4'hf; end
8'h53: begin outr <= outr^index[8:5]^4'h3; end
8'h54: begin outr <= outr^index[8:5]^4'h1; end
8'h55: begin outr <= outr^index[8:5]^4'h0; end
8'h56: begin outr <= outr^index[8:5]^4'h2; end
8'h57: begin outr <= outr^index[8:5]^4'h9; end
8'h58: begin outr <= outr^index[8:5]^4'h2; end
8'h59: begin outr <= outr^index[8:5]^4'h4; end
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
8'h60: begin outr <= outr^index[8:5]^4'h7; end
8'h61: begin outr <= outr^index[8:5]^4'h3; end
8'h62: begin outr <= outr^index[8:5]^4'h3; end
8'h63: begin outr <= outr^index[8:5]^4'hb; end
8'h64: begin outr <= outr^index[8:5]^4'h9; end
8'h65: begin outr <= outr^index[8:5]^4'h4; end
8'h66: begin outr <= outr^index[8:5]^4'h3; end
8'h67: begin outr <= outr^index[8:5]^4'h6; end
8'h68: begin outr <= outr^index[8:5]^4'h7; end
8'h69: begin outr <= outr^index[8:5]^4'h7; end
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
8'h6d: begin outr <= outr^index[8:5]^4'he; end
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
8'h70: begin outr <= outr^index[8:5]^4'hc; end
8'h71: begin outr <= outr^index[8:5]^4'h9; end
8'h72: begin outr <= outr^index[8:5]^4'h5; end
8'h73: begin outr <= outr^index[8:5]^4'ha; end
8'h74: begin outr <= outr^index[8:5]^4'h7; end
8'h75: begin outr <= outr^index[8:5]^4'h0; end
8'h76: begin outr <= outr^index[8:5]^4'h1; end
8'h77: begin outr <= outr^index[8:5]^4'he; end
8'h78: begin outr <= outr^index[8:5]^4'ha; end
8'h79: begin outr <= outr^index[8:5]^4'h7; end
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
8'h7b: begin outr <= outr^index[8:5]^4'he; end
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
8'h80: begin outr <= outr^index[8:5]^4'h0; end
8'h81: begin outr <= outr^index[8:5]^4'hd; end
8'h82: begin outr <= outr^index[8:5]^4'hb; end
8'h83: begin outr <= outr^index[8:5]^4'hc; end
8'h84: begin outr <= outr^index[8:5]^4'h2; end
8'h85: begin outr <= outr^index[8:5]^4'h8; end
8'h86: begin outr <= outr^index[8:5]^4'h3; end
8'h87: begin outr <= outr^index[8:5]^4'ha; end
8'h88: begin outr <= outr^index[8:5]^4'he; end
8'h89: begin outr <= outr^index[8:5]^4'h9; end
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
8'h90: begin outr <= outr^index[8:5]^4'h0; end
8'h91: begin outr <= outr^index[8:5]^4'h6; end
8'h92: begin outr <= outr^index[8:5]^4'h7; end
8'h93: begin outr <= outr^index[8:5]^4'hc; end
8'h94: begin outr <= outr^index[8:5]^4'hb; end
8'h95: begin outr <= outr^index[8:5]^4'h3; end
8'h96: begin outr <= outr^index[8:5]^4'h0; end
8'h97: begin outr <= outr^index[8:5]^4'hc; end
8'h98: begin outr <= outr^index[8:5]^4'hc; end
8'h99: begin outr <= outr^index[8:5]^4'hb; end
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
8'h9f: begin outr <= outr^index[8:5]^4'he; end
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
8'haa: begin outr <= outr^index[8:5]^4'h5; end
8'hab: begin outr <= outr^index[8:5]^4'hb; end
8'hac: begin outr <= outr^index[8:5]^4'he; end
8'had: begin outr <= outr^index[8:5]^4'h0; end
8'hae: begin outr <= outr^index[8:5]^4'hf; end
8'haf: begin outr <= outr^index[8:5]^4'h9; end
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
8'hb4: begin outr <= outr^index[8:5]^4'he; end
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
8'hb6: begin outr <= outr^index[8:5]^4'he; end
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
8'hba: begin outr <= outr^index[8:5]^4'h3; end
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
8'hbf: begin outr <= outr^index[8:5]^4'he; end
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
8'hc1: begin outr <= outr^index[8:5]^4'he; end
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
8'hca: begin outr <= outr^index[8:5]^4'h3; end
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
8'hcc: begin outr <= outr^index[8:5]^4'he; end
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
8'hce: begin outr <= outr^index[8:5]^4'h5; end
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
8'hda: begin outr <= outr^index[8:5]^4'h8; end
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
8'hdc: begin outr <= outr^index[8:5]^4'he; end
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
8'hde: begin outr <= outr^index[8:5]^4'h9; end
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
8'he0: begin outr <= outr^index[8:5]^4'h7; end
8'he1: begin outr <= outr^index[8:5]^4'h0; end
8'he2: begin outr <= outr^index[8:5]^4'h9; end
8'he3: begin outr <= outr^index[8:5]^4'h3; end
8'he4: begin outr <= outr^index[8:5]^4'h2; end
8'he5: begin outr <= outr^index[8:5]^4'h4; end
8'he6: begin outr <= outr^index[8:5]^4'h5; end
8'he7: begin outr <= outr^index[8:5]^4'h5; end
8'he8: begin outr <= outr^index[8:5]^4'hf; end
8'he9: begin outr <= outr^index[8:5]^4'ha; end
8'hea: begin outr <= outr^index[8:5]^4'hc; end
8'heb: begin outr <= outr^index[8:5]^4'hd; end
8'hec: begin outr <= outr^index[8:5]^4'h1; end
8'hed: begin outr <= outr^index[8:5]^4'h5; end
8'hee: begin outr <= outr^index[8:5]^4'h9; end
8'hef: begin outr <= outr^index[8:5]^4'h0; end
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
8'hf5: begin outr <= outr^index[8:5]^4'he; end
8'hf6: begin outr <= outr^index[8:5]^4'he; end
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
default: begin outr <= outr^index[8:5]^4'h6; end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:55:04 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P6 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_29_CI, intadd_29_n5, intadd_29_n4, intadd_29_n3, intadd_29_n2,
intadd_29_n1, n2, n3, n4, n5, n6, n7, n8, n9, n10;
CMPR32X2TS intadd_29_U6 ( .A(in2[1]), .B(in1[1]), .C(intadd_29_CI), .CO(
intadd_29_n5), .S(res[1]) );
CMPR32X2TS intadd_29_U5 ( .A(in2[2]), .B(in1[2]), .C(intadd_29_n5), .CO(
intadd_29_n4), .S(res[2]) );
CMPR32X2TS intadd_29_U4 ( .A(in2[3]), .B(in1[3]), .C(intadd_29_n4), .CO(
intadd_29_n3), .S(res[3]) );
CMPR32X2TS intadd_29_U3 ( .A(in2[4]), .B(in1[4]), .C(intadd_29_n3), .CO(
intadd_29_n2), .S(res[4]) );
CMPR32X2TS intadd_29_U2 ( .A(in2[5]), .B(in1[5]), .C(intadd_29_n2), .CO(
intadd_29_n1), .S(res[5]) );
OAI211XLTS U2 ( .A0(in1[2]), .A1(in2[2]), .B0(in2[1]), .C0(in1[1]), .Y(n2)
);
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_29_CI) );
XOR2XLTS U4 ( .A(n10), .B(in1[6]), .Y(res[6]) );
XOR2XLTS U5 ( .A(intadd_29_n1), .B(in2[6]), .Y(n10) );
OAI2BB2XLTS U6 ( .B0(n8), .B1(n7), .A0N(in1[6]), .A1N(in2[6]), .Y(n9) );
AOI222X1TS U7 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n6), .C0(in1[5]),
.C1(n6), .Y(n8) );
OAI2BB2X1TS U8 ( .B0(n5), .B1(n4), .A0N(in1[4]), .A1N(in2[4]), .Y(n6) );
OAI2BB1X1TS U9 ( .A0N(in2[2]), .A1N(in1[2]), .B0(n2), .Y(n3) );
AOI222X1TS U10 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[3]), .B1(n3), .C0(in1[3]),
.C1(n3), .Y(n5) );
NOR2XLTS U11 ( .A(in1[4]), .B(in2[4]), .Y(n4) );
NOR2XLTS U12 ( .A(in1[6]), .B(in2[6]), .Y(n7) );
CMPR32X2TS U13 ( .A(in1[7]), .B(in2[7]), .C(n9), .CO(res[8]), .S(res[7]) );
AOI2BB1XLTS U14 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_29_CI), .Y(res[0])
);
initial $sdf_annotate("GeAr_N8_R1_P6_syn.sdf");
endmodule
|
/*
* Copyright (c) 2000 Mark Schellhorn <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/****************************************************************************
The following code illustrates an apparent bug in the VCS v5.2 simulator.
The check for whether or not the memory[0] array element was set correctly
fails; yet the $display statement immediately after the check shows the
memory[0] element actually has been set correctly.
I've noted that if the $display and the check are reversed, the $display
is incorrect but the check passes.
This appears to be a problem with the simulator's internal scheduler.
***************************************************************************/
module bug_test;
reg [1:0] temp;
initial begin
/********** First test. */
$display("Running first test.\n");
// Try setting memory array in other module using hierarchical
// references & concatenation.
temp = 2'h3;
top.memory.memory[0] = {2'h0,temp};
top.memory.memory[0] = {top.memory.memory[0],temp};
// Check that setting was made correctly
if (top.memory.memory[0] != {2{temp}}) begin
$display("ERROR! top.memory.memory[0] failed to get");
$display("set correctly!");
end else begin
$display("PASS! top.memory.memory[0] set correctly.");
end
// Display the value that was checked
$display("top.memory.memory[0] = %h",top.memory.memory[0]);
/********** Second test. */
$display("\nRunning second test.\n");
// Try setting memory array in other module using hierarchical
// references & concatenation.
temp = 2'h3;
top.memory.memory[1] = {2'h0,temp};
top.memory.memory[1] = {top.memory.memory[1],temp};
// Display the value that will be checked
$display("top.memory.memory[1] = %h",top.memory.memory[1]);
// Check that setting was made correctly
if (top.memory.memory[1] != {2{temp}}) begin
$display("ERROR! top.memory.memory[1] failed to get");
$display("set correctly!");
end else begin
$display("PASS! top.memory.memory[1] set correctly.");
end
// Display the value that was checked
$display("top.memory.memory[1] = %h",top.memory.memory[1]);
$finish;
end
endmodule
// Module containing a memory array
module memory;
reg [3:0] memory [0:1];
endmodule
// Module to instantiate test and memory modules
module top;
bug_test bug_test();
memory memory();
endmodule
|
module IDEX_Reg (
input clk,
input flush,
input stall,
input [5-1:0] EX_ctrl_i,
output [5-1:0] EX_ctrl_o,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] Rs_data_i,
output [32-1:0] Rs_data_o,
input [32-1:0] Rt_data_i,
output [32-1:0] Rt_data_o,
input [32-1:0] imm_data_i,
output [32-1:0] imm_data_o,
input [5-1:0] Rs_i,
output [5-1:0] Rs_o,
input [5-1:0] Rt_i,
output [5-1:0] Rt_o,
input [5-1:0] Rd_i,
output [5-1:0] Rd_o
);
Latch #(.width(5)) IDEX_EX_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (EX_ctrl_i),
.data_o (EX_ctrl_o)
);
Latch #(.width(2)) IDEX_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) IDEX_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch IDEX_Rs_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_data_i),
.data_o (Rs_data_o)
);
Latch IDEX_Rt_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_data_i),
.data_o (Rt_data_o)
);
Latch IDEX_imm_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (imm_data_i),
.data_o (imm_data_o)
);
Latch #(.width(5)) IDEX_Rs (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_i),
.data_o (Rs_o)
);
Latch #(.width(5)) IDEX_Rt (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_i),
.data_o (Rt_o)
);
Latch #(.width(5)) IDEX_Rd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rd_i),
.data_o (Rd_o)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Manipulates phaser out stg2f and stg3 on behalf of
// scan and DQS centering.
//
// Maintains a shadow of the phaser out stg2f and stg3 tap settings.
// The stg3 shadow is 6 bits, just like the phaser out. stg2f is
// 8 bits. This allows the po_cntlr to track how far past the stg2f
// saturation points we have gone when stepping to the limits of stg3.
// This way we're can stay in sync when we step back from the saturation
// limits.
//
// Looks at the edge values and determines which case has been
// detected by the scan. Uses the results to drive the centering.
//
// Main state machine waits until it sees reset_scan go to zero. While
// waiting it is writing the initialzation values to the stg2 and stg3
// shadows. When reset_scan goes low, taps_set is pulsed. This
// tells the sampling block to begin sampling. When the sampling
// block has finished sampling this setting of the phaser out taps,
// is signals by setting samp_done. When the main state machine
// sees samp_done it sets the next value in the phaser out and
// waits for the phaser out to be ready before beginning the next
// sample.
//
// Turns out phy_init is sensitive to the length of the ocal_num_samples_done
// pulse. Something like a precharge and activate time. Added feature
// to resume_wait to wait at least 32 cycles between assertion and
// subsequent deassertion of ocal_num_samples_done.
//
// Also turns out phy_init needs help to get into consistent
// starting state for complex cal. This can be done by preseting
// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,
// turn off _done and then assert _resume.
//
// Scanning algorithm.
//
// Phaser manipulation algoritm.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_po_cntlr #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter nCK_PER_CLK = 4,
parameter SAMPLES = 128,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,
oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,
ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,
cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,
scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,
taps_set, use_noise_window, ocal_scan_win_not_found,
// Inputs
clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,
lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,
po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,
mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,
fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,
scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
input reset_scan;
reg scan_done_r;
output scan_done;
assign scan_done = scan_done_r;
output [5:0] simp_stg3_final_sel;
reg cmplx_samples_done_ns, cmplx_samples_done_r;
always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;
output ocal_num_samples_done_r;
assign ocal_num_samples_done_r = cmplx_samples_done_r;
// Write Level signals during OCLKDELAY calibration
input [5:0] oclkdelay_init_val;
input [5:0] lim2ocal_stg3_right_lim;
input [5:0] lim2ocal_stg3_left_lim;
input complex_oclkdelay_calib_start;
reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;
always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;
output oclkdelay_center_calib_start;
assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;
reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;
always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;
output oclkdelay_center_calib_done;
assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;
reg oclk_center_write_resume_ns, oclk_center_write_resume_r;
always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;
output oclk_center_write_resume;
assign oclk_center_write_resume = oclk_center_write_resume_r;
reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;
output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;
assign ocd2stg2_inc = ocd2stg2_inc_r;
assign ocd2stg2_dec = ocd2stg2_dec_r;
assign ocd2stg3_inc = ocd2stg3_inc_r;
assign ocd2stg3_dec = ocd2stg3_dec_r;
// Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.
reg [8:0] stg2_ns, stg2_r;
always @(posedge clk) stg2_r <= #TCQ stg2_ns;
reg [5:0] stg3_ns, stg3_r;
always @(posedge clk) stg3_r <= #TCQ stg3_ns;
output [5:0] stg3;
assign stg3 = stg3_r;
input [5:0] wl_po_fine_cnt_sel;
input [8:0] po_counter_read_val;
reg [5:0] po_counter_read_val_r;
always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];
reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;
always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;
always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;
output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
assign simp_stg3_final = simp_stg3_final_r;
assign cmplx_stg3_final = cmplx_stg3_final_r;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;
assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];
wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;
wire signed [8:0] stg2_steps = stg3_r > stg3_init
? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})
: 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});
wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;
reg signed [8:0] stg2_target_r;
always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;
reg [5:0] stg2_final_ns, stg2_final_r;
always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;
always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1
? 6'd0
: stg2_target_r > 9'd63
? 6'd63
: stg2_target_r[5:0];
wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;
wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;
wire left_lim = stg3_r == lim2ocal_stg3_left_lim;
wire right_lim = stg3_r == lim2ocal_stg3_right_lim;
reg [1:0] ninety_offsets_ns, ninety_offsets_r;
always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;
output [1:0] ninety_offsets;
assign ninety_offsets = ninety_offsets_r;
reg scanning_right_ns, scanning_right_r;
always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;
output scanning_right;
assign scanning_right = scanning_right_r;
reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;
always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;
always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;
output ocd_ktap_left, ocd_ktap_right;
assign ocd_ktap_left = ocd_ktap_left_r;
assign ocd_ktap_right = ocd_ktap_right_r;
reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;
always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;
output ocd_edge_detect_rdy;
assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;
input mmcm_edge_detect_done;
input mmcm_lbclk_edge_aligned;
input poc_backup;
reg poc_backup_ns, poc_backup_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
reg taps_set_r;
output taps_set;
assign taps_set = taps_set_r;
input phy_rddata_en_3;
input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
input z2f, f2z, o2f, f2o;
wire zero = f2z && z2f;
wire noise = z2f && f2o;
wire oneeighty = f2o && o2f;
reg win_not_found;
reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r;
always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns;
reg [5:0] left, right, current_edge;
always @(*) begin
left = lim2ocal_stg3_left_lim;
right = lim2ocal_stg3_right_lim;
ninety_offsets_final_ns = 2'd0;
win_not_found = 1'b0;
if (zero) begin
left = fuzz2zero;
right = zero2fuzz;
end
else if (noise) begin
left = zero2fuzz;
right = fuzz2oneeighty;
ninety_offsets_final_ns = 2'd1;
end
else if (oneeighty) begin
left = fuzz2oneeighty;
right = oneeighty2fuzz;
ninety_offsets_final_ns = 2'd2;
end
else if (z2f) begin
right = zero2fuzz;
end
else if (f2o) begin
left = fuzz2oneeighty;
ninety_offsets_final_ns = 2'd2;
end
else if (f2z) begin
left = fuzz2zero;
end
else win_not_found = 1'b1;
current_edge = ocd_ktap_left_r ? left : right;
end // always @ begin
output use_noise_window;
assign use_noise_window = ninety_offsets == 2'd1;
reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;
always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;
output ocal_scan_win_not_found;
assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;
wire inc_po_ns = current_edge > stg3_r;
wire dec_po_ns = current_edge < stg3_r;
reg inc_po_r, dec_po_r;
always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;
always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;
input scan_right;
wire left_stop = left_lim || scan_right;
wire right_stop = right_lim || o2f;
// POC samples every other fabric clock.
localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15;
localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31;
localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1);
reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r;
always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;
wire resume_wait = |resume_wait_r;
reg po_done_ns, po_done_r;
always @(posedge clk) po_done_r <= #TCQ po_done_ns;
input samp_done;
input po_rdy;
reg up_ns, up_r;
always @(posedge clk) up_r <= #TCQ up_ns;
reg [1:0] two_ns, two_r;
always @(posedge clk) two_r <= #TCQ two_ns;
/* wire stg2_zero = ~|stg2_r;
wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0
: stg2_r > 9'd63
? 9'd63
: stg2_r; */
reg [3:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;
always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;
always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3
? ~phy_rddata_en_3_second_r
: phy_rddata_en_3_second_r);
wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;
reg po_center_wait;
reg po_slew;
reg po_finish_scan;
always @(*) begin
// Default next state assignments.
cmplx_samples_done_ns = cmplx_samples_done_r;
cmplx_stg3_final_ns = cmplx_stg3_final_r;
scanning_right_ns = scanning_right_r;
ninety_offsets_ns = ninety_offsets_r;
ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;
ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;
ocd_ktap_left_ns = ocd_ktap_left_r;
ocd_ktap_right_ns = ocd_ktap_right_r;
ocd2stg2_inc_r = 1'b0;
ocd2stg2_dec_r = 1'b0;
ocd2stg3_inc_r = 1'b0;
ocd2stg3_dec_r = 1'b0;
oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;
oclkdelay_center_calib_done_ns = 1'b0;
oclk_center_write_resume_ns = oclk_center_write_resume_r;
po_center_wait = 1'b0;
po_done_ns = po_done_r;
po_finish_scan = 1'b0;
po_slew = 1'b0;
poc_backup_ns = poc_backup_r;
scan_done_r = 1'b0;
simp_stg3_final_ns = simp_stg3_final_r;
sm_ns = sm_r;
taps_set_r = 1'b0;
up_ns = up_r;
stg2_ns = stg2_r;
stg3_ns = stg3_r;
two_ns = two_r;
resume_wait_ns = resume_wait_r;
if (rst == 1'b1) begin
// RESET next states
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b0;
ocd_edge_detect_rdy_ns = 1'b0;
oclk_center_write_resume_ns = 1'b0;
oclkdelay_center_calib_start_ns = 1'b0;
po_done_ns = 1'b1;
resume_wait_ns = 5'd0;
sm_ns = /*AK("READY")*/4'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/4'd0:begin
poc_backup_ns = 1'b0;
stg2_ns = {3'b0, wl_po_fine_cnt_sel};
stg3_ns = stg3_init;
scanning_right_ns = 1'b0;
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
if (!reset_scan && ~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
end
end
/*AL("SAMPLING")*/4'd1:begin
if (samp_done && use_samp_done) begin
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
scanning_right_ns = scanning_right_r || left_stop;
if (right_stop && scanning_right_r) begin
oclkdelay_center_calib_start_ns = 1'b1;
ocd_ktap_left_ns = 1'b1;
ocal_scan_win_not_found_ns = win_not_found;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else begin
if (scanning_right_ns) ocd2stg3_inc_r = 1'b1;
else ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("PO_WAIT")*/4'd2;
end
end
end
/*AL("PO_WAIT")*/4'd2:begin
if (po_done_r && ~resume_wait) begin
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
cmplx_samples_done_ns = 1'b0;
end
end
/*AL("SLEW_PO")*/4'd3:begin
po_slew = 1'b1;
ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00;
if (~resume_wait) begin
if (po_done_r) begin
if (inc_po_r) ocd2stg3_inc_r = 1'b1;
else if (dec_po_r) ocd2stg3_dec_r = 1'b1;
else if (~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end // if (po_done)
end
end // case: 3'd3
/*AL("ALIGN_EDGES")*/4'd4:
if (~resume_wait) begin
if (mmcm_edge_detect_done) begin
ocd_edge_detect_rdy_ns = 1'b0;
if (ocd_ktap_left_r) begin
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b1;
oclk_center_write_resume_ns = 1'b0;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else if (ocd_ktap_right_r) begin
ocd_ktap_right_ns = 1'b0;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else if (~mmcm_lbclk_edge_aligned) begin
sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6;
oclk_center_write_resume_ns = 1'b0;
end else begin
if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin
ninety_offsets_ns = ninety_offsets_r + 2'b01;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else begin
oclk_center_write_resume_ns = 1'b0;
poc_backup_ns = poc_backup;
// stg2_ns = stg2_2_zero;
sm_ns = /*AK("FINISH_SCAN")*/4'd8;
end
end // else: !if(~mmcm_lbclk_edge_aligned)
end else ocd_edge_detect_rdy_ns = 1'b1;
end // if (~resume_wait)
/*AL("WAIT_ONE")*/4'd5:
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
/*AL("DQS_STOP_WAIT")*/4'd6:
if (~resume_wait) begin
ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7;
end
/*AL("CENTER_PO_WAIT")*/4'd7: begin
po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.
if (po_done_r) begin
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end
/*AL("FINISH_SCAN")*/4'd8: begin
po_finish_scan = 1'b1;
if (resume_wait_r == 5'd1) begin
if (~poc_backup_r) begin
oclkdelay_center_calib_done_ns = 1'b1;
oclkdelay_center_calib_start_ns = 1'b0;
end
end
if (~resume_wait) begin
if (po_rdy)
if (poc_backup_r) begin
ocd2stg3_inc_r = 1'b1;
poc_backup_ns = 1'b0;
end
else if (~final_stg2_inc && ~final_stg2_dec) begin
if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
sm_ns = /*AK("READY")*/4'd0;
scan_done_r = 1'b1;
end else begin
ocd2stg2_inc_r = final_stg2_inc;
ocd2stg2_dec_r = final_stg2_dec;
end
end // if (~resume_wait)
end // case: 4'd8
endcase // case (sm_r)
if (ocd2stg3_inc_r) begin
stg3_ns = stg3_r + 6'h1;
up_ns = 1'b0;
end
if (ocd2stg3_dec_r) begin
stg3_ns = stg3_r - 6'h1;
up_ns = 1'b1;
end
if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin
po_done_ns = 1'b0;
two_ns = 2'b00;
end
if (~po_done_r)
if (po_rdy)
if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;
else begin
two_ns = two_r + 2'b1;
if (up_r) begin
stg2_ns = stg2_r + 9'b1;
if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;
end else begin
stg2_ns = stg2_r - 9'b1;
if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;
end
end // else: !if(two_r == 2'b10)
if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1;
else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r)
resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0];
else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15;
else if (cmplx_samples_done_ns & ~cmplx_samples_done_r ||
complex_oclkdelay_calib_start & reset_scan ||
poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31;
else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1;
end // always @ begin
endmodule // mig_7series_v4_0_ddr_phy_ocd_po_cntlr
// Local Variables:
// verilog-autolabel-prefix: "4'd"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_TB_V
`define SKY130_FD_SC_LP__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_TB_V
|
//==================================================================================================
// Filename : musb_exmem_register.v
// Created On : 2014-09-27 20:25:03
// Last Modified : 2015-05-31 13:04:37
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: EX -> MEM
//==================================================================================================
module musb_exmem_register(
input clk, // main clock
input rst, // main reset
input [31:0] ex_alu_result, // ALU result
input [31:0] ex_mem_store_data, // data to memory
input [4:0] ex_gpr_wa, // GPR write address
input ex_gpr_we, // GPR write enable
input ex_mem_to_gpr_select, // Select MEM/ALU to GPR
input ex_mem_write, // Mem write operation
input ex_mem_byte, // byte access
input ex_mem_halfword, // halfword access
input ex_mem_data_sign_ext, // Sign/Zero extend data from memory
input [31:0] ex_exception_pc,
input ex_movn,
input ex_movz,
input ex_b_is_zero,
input ex_llsc,
input ex_kernel_mode,
input ex_is_bds,
input ex_trap,
input ex_trap_condition,
input ex_mem_exception_source,
input ex_flush, // clean
input ex_stall, // stall EX stage
input mem_stall, // stall MEM stage
output reg [31:0] mem_alu_result, // Same signals, but on mem stage
output reg [31:0] mem_mem_store_data, //
output reg [4:0] mem_gpr_wa, //
output reg mem_gpr_we, //
output reg mem_mem_to_gpr_select, //
output reg mem_mem_write, //
output reg mem_mem_byte, //
output reg mem_mem_halfword, //
output reg mem_mem_data_sign_ext, //
output reg [31:0] mem_exception_pc,
output reg mem_llsc,
output reg mem_kernel_mode,
output reg mem_is_bds,
output reg mem_trap,
output reg mem_trap_condition,
output reg mem_mem_exception_source
);
// Check for MOVN or MOVZ instruction
wire mov_reg_write = (ex_movn & ~ex_b_is_zero) | (ex_movz & ex_b_is_zero);
//--------------------------------------------------------------------------
// Propagate signals
// Clear WE and Write signals only, on EX stall.
//--------------------------------------------------------------------------
always @(posedge clk) begin
mem_alu_result <= (rst) ? 32'b0 : ((mem_stall) ? mem_alu_result : ex_alu_result);
mem_mem_store_data <= (rst) ? 32'b0 : ((mem_stall) ? mem_mem_store_data : ex_mem_store_data);
mem_gpr_wa <= (rst) ? 5'b0 : ((mem_stall) ? mem_gpr_wa : ex_gpr_wa);
mem_gpr_we <= (rst) ? 1'b0 : ((mem_stall) ? mem_gpr_we : ((ex_stall | ex_flush) ? 1'b0 : ((ex_movz | ex_movn) ? mov_reg_write : ex_gpr_we)));
mem_mem_to_gpr_select <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_to_gpr_select : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_to_gpr_select)); // test
mem_mem_write <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_write : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_write));
mem_mem_byte <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_byte : ex_mem_byte);
mem_mem_halfword <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_halfword : ex_mem_halfword);
mem_mem_data_sign_ext <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_data_sign_ext : ex_mem_data_sign_ext);
mem_exception_pc <= (rst) ? 32'b0 : ((mem_stall) ? mem_exception_pc : ex_exception_pc);
mem_llsc <= (rst) ? 1'b0 : ((mem_stall) ? mem_llsc : ex_llsc);
mem_kernel_mode <= (rst) ? 1'b0 : ((mem_stall) ? mem_kernel_mode : ex_kernel_mode);
mem_is_bds <= (rst) ? 1'b0 : ((mem_stall) ? mem_is_bds : ex_is_bds);
mem_trap <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap : ((ex_stall | ex_flush) ? 1'b0 : ex_trap));
mem_trap_condition <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap_condition : ex_trap_condition);
mem_mem_exception_source <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_exception_source : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_exception_source));
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:46:27 02/23/2009
// Design Name:
// Module Name: MSG_utils
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//module inst_TX_MSG ( CLK,
// CLKDIV,
// DATA_IN,
// OSER_OQ,
// RST,
// CLKWR,
// WREN,
// CON_P, //input feedback from decode module
// CON_N,
// BACK_WRONG, //feedback output to internal module
// BACK_RIGHT,
// ALMOSTFULL,
// EMPTY);
module RCB_FRL_TX_MSG (
CLK,
CLKDIV,
DATA_IN,
OSER_OQ,
RST,
CLKWR,
WREN,
CON_P,
CON_N,
BACK_WRONG,
BACK_RIGHT,
ALMOSTFULL,
EMPTY,
probe,
EN_SIG,
RE_SIG,
TRAINING_DONE
);
input CLK, CLKDIV, RST, CLKWR, WREN, CON_P, CON_N, TRAINING_DONE;
input [39:0] DATA_IN;
output probe;
input RE_SIG, EN_SIG;
output OSER_OQ;
output BACK_WRONG, BACK_RIGHT, ALMOSTFULL;
output EMPTY;
reg [7:0] input_reg;
wire [39:0] fifo_DO;
wire ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL;
wire EMPTY_fifo; // Added by Jiansong, 2010-5-27
wire RDEN;
reg [8:0] count;
parameter NUM = 8'h06;
reg RDEN_REG;
RCB_FRL_fifo_MSG RCB_FRL_fifo_MSG_inst (
.ALMOSTEMPTY(ALMOSTEMPTY),
.ALMOSTFULL(ALMOSTFULL),
.DO(fifo_DO),
// .EMPTY(EMPTY),
.EMPTY(EMPTY_fifo), // modified by Jiansong, 2010-5-27
.FULL(FULL),
.DI(DATA_IN),
.RDCLK(CLKDIV),
.RDEN(RDEN_REG),
.WRCLK(CLKWR),
.WREN(WREN),
.RST(RST)
);
//assign EMPTY = 0; //xt
wire [7:0] CRC;
RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst ( .D({{NUM},{fifo_DO}}), .NewCRC(CRC));
// Added by Jiansong, 2010-5-27, do not send out control message in training stage
assign EMPTY = EMPTY_fifo | (~TRAINING_DONE);
reg [3:0] times;
reg BACK_WRONG, BACK_RIGHT;
assign probe = RDEN_REG;
always @ (posedge CLKDIV) begin
if (RST == 1'b1) begin
count <= 9'h000;
RDEN_REG <= 1'b0;
times <= 4'h0;
end
else begin
if (count == 9'h1FF | count == 9'h1FE)
begin
count <= 9'h000;
end
else if (count == 9'h000) begin
if ( EN_SIG == 1'b1) // Jiansong: ACK first
begin
count <= 9'h1FF;
end
else if (RE_SIG == 1'b1)
begin
count <= 9'h1FE;
end
else
begin
if (EMPTY == 1'b1 & times == 4'h0) begin
count <= 9'h000;
end
else if (EMPTY == 1'b0) begin
count <= 9'h001;
RDEN_REG <= 1'b0;
end
else if (times == 4'h1 | times ==4'h2) begin
count <= 9'h001;
RDEN_REG <= 1'b0;
end
else if (times == 4'h3) begin
times <= 1'b0;
RDEN_REG <= 1'b0;
end
end
BACK_WRONG <= 1'b0;
BACK_RIGHT <= 1'b0;
end
else if (count == 9'h001) begin
if (times == 4'h0) begin
RDEN_REG <= 1'b1;
end
times <= times + 4'h1;
count <= 9'h002;
BACK_WRONG <= 1'b0;
BACK_RIGHT <= 1'b0;
end
else if (count == 9'h002) begin
RDEN_REG <= 1'b0;
count <= 9'h003;
end
//else if (count == (NUM+8'h03) ) begin
else if ( CON_P == 1'b1) begin
// if (EMPTY == 1'b0) begin
// count <= 9'h001;
// end
// else begin
count <= 9'h000;
// end
times <= 4'h0;
BACK_RIGHT <= 1'b1;
end
else if (times == 4'h3 & count == 9'h150) begin
// if (EMPTY == 1'b0) begin
// count <= 9'h001;
// end
// else begin
count <= 9'h000;
// end
times <= 4'h0;
BACK_WRONG <= 1'b1;
end
else if ( CON_N == 1'b1 | count == 9'h150) begin
count <= 9'h000;
end
else begin
count <= count + 9'h001;
end
end
end
reg [8:0] data_counter;
always @ (negedge CLKDIV) begin
if ( RST == 1'b1 ) begin
input_reg[7:0] <= 8'h00;
data_counter <= 8'h00;
end
else if (count == 9'h001) begin
input_reg[7:0] <= 8'hF5;
end
else if (count == 9'h002) begin
input_reg[7:0] <= NUM;
end
else if (count == 9'h000) begin
input_reg[7:0] <= 8'h44; // modified by zjs, 2009-3-8, send 8'h44 on idle state to train LVDS receiver
end
else if (count == 9'h003) begin
input_reg[7:0] <= fifo_DO[39:32];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h004) begin
input_reg[7:0] <= fifo_DO[31:24];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h005) begin
input_reg[7:0] <= fifo_DO[23:16];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h006) begin
input_reg[7:0] <= fifo_DO[15:8];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h007) begin
input_reg[7:0] <= fifo_DO[7:0];
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
end
else if (count == 9'h008) begin
//data_counter <= data_counter + 1;
//input_reg[7:0] <= data_counter;
input_reg[7:0] <= CRC[7:0];
//input_reg[7:0] = 8'h02;
end
else if (count == 9'h1FF) begin
input_reg[7:0] <= 8'h5f;
end
else if (count == 9'h1FE) begin
input_reg[7:0] <= 8'haf;
end
else begin
input_reg[7:0] <= 8'h00;
end
end
/*
wire CE;
assign CE = 1'b1;
wire [9:0] OUTPUT_REG;
encode_8b10b_lut_base inst_encode_8b10b_lut_base_CMD(
.DIN(input_reg[7:0]),
.KIN(),
.CLK(CLKDIV), // : IN STD_LOGIC :='0' ;
.DOUT(OUTPUT_REG[9:0]), // : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) :=
// str_to_slv(C_FORCE_CODE_VAL, 10) ;
.CE(CE), // : IN STD_LOGIC :='0' ;
.FORCE_CODE(), // : IN STD_LOGIC :='0' ;
.FORCE_DISP(), // : IN STD_LOGIC :='0' ;
.DISP_IN(), // : IN STD_LOGIC :='0' ;
.DISP_OUT(), // : OUT STD_LOGIC :=
// bint_2_sl(C_FORCE_CODE_DISP);
.KERR(), // : OUT STD_LOGIC :='0' ;
.ND() // : OUT STD_LOGIC :='0'
);
*/
wire [7:0] PATTERN;
RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
.CLK(CLKDIV),
.RST(RST),
.DATA_OUT(PATTERN));
wire [7:0] input_reg_inv;
assign input_reg_inv = TRAINING_DONE ? input_reg : PATTERN;
//assign input_reg_inv = PATTERN;
//inst_OSERDES_MSG inst_OSERDES1 (.OQ(OSER_OQ), .CLK(CLK), .CLKDIV(CLKDIV), .DI(input_reg_inv), .OCE(1'b1), .SR(RST));
RCB_FRL_OSERDES_MSG RCB_FRL_OSERDES_MSG_inst (
.OQ(OSER_OQ), .CLK(CLK), .CLKDIV(CLKDIV), .DI(input_reg_inv), .OCE(1'b1), .SR(RST));
endmodule
|
//Jun.30.2004 Mux sentibity list bug fix
//Jul.2.2004 Cleanup
//Jul.7.2004 int bug fix
//Jan.20.2005 apply @*
`include "define.h"
module Pipelined_RegFile(clock,sync_reset,
dest_addrD2,source_addr,target_addr, wren,memory_wdata,
A_Right_SELD1,A_Left_SELD1,PCD1,IMMD1,ALU_FuncD2,Shift_FuncD2,
Shift_amountD2,RRegSelD1,MOUT,RF_inputD2,alu_source,alu_target,
MWriteD2,MWriteD1,mul_alu_selD2,mul_div_funcD2,pause_out,
Shift_Amount_selD2,int_stateD1,PCCDD
);
parameter adder_type="GENERIC";
`ifdef RAM4K
input [11:0] PCD1;
`else
input [25:0] PCD1;
`endif
input [15:0] IMMD1;//Jul.6.2004
input [4:0] dest_addrD2;
input [4:0] source_addr;
input [4:0] target_addr;
input wren;
input clock;
input A_Left_SELD1;
input [3:0] ALU_FuncD2;
input [4:0] Shift_amountD2;
input [1:0] Shift_FuncD2;
input [1:0] A_Right_SELD1;
input sync_reset;
input [1:0] RRegSelD1;
output [31:0] alu_target,alu_source;
output [31:0] memory_wdata;
input [31:0] MOUT;
input [1:0] RF_inputD2;
input MWriteD2,MWriteD1;
input [1:0] mul_alu_selD2;
input [3:0] mul_div_funcD2;
output pause_out;
input Shift_Amount_selD2;
input int_stateD1;
reg [31:0] AReg,NReg,RReg,DReg;
reg [31:0] alu_left_latch,alu_right_latch;
reg [31:0] memory_wdata;
`ifdef RAM4K
input [11:0] PCCDD;
reg [11:0] PCD2;
`else
input [25:0] PCCDD;
reg [25:0] PCD2;
`endif
reg [15:0] IMMD2;//Jul.6.2004
reg [4:0] dadrD3,dadrD4,dadrD5,dadrD6;
reg [4:0] sadrD1,sadrD2;
reg [4:0] tadrD1,tadrD2;
reg WD3,WD4,WD5,WD6;
reg [1:0] A_Right_SELD2;
reg [1:0] RRegSelD2, RRegSelD3, RRegSelD4;
reg [31:0] RRegin;
reg test1D,test2D;
wire [31:0] alu_right;
reg [31:0] alu_left;
wire [31:0] source_out,target_out;
wire [31:0] alu_out,shift_out;
wire [31:0] alu_source=alu_left;
wire [31:0] alu_target=alu_right;
wire [31:0] regfile_in;
wire [31:0] test,test2;
wire test1;
reg stest1D,stest2D;
reg stest1D_dup1,stest1D_dup2,stest1D_dup3,stest1D_dup4;
reg [31:0] mul_alu_out;
reg div_mode_ff;
reg sign_ff;
reg RRegSelD4_dup1,RRegSelD4_dup2,RRegSelD4_dup3;
wire mul_div_enable,mul_div_sign,mul_div_mode;
wire [31:0] mul_div_out;
wire [31:0] c_mult;
wire [4:0] Shift_Amount;
localparam [4:0] zero_=0,
at_=1,
v0_=2,
v1_=3,
a0_=4,
a1_=5,
a2_=6,
a3_=7,
t0_=8, t1_=9,t2_=10,t3_=11,t4_=12,t5_=13,t6_=14,t7_=15,
s0_=16,s1_=17,s2_=18,s3_=19,s4_=20,s5_=21,s6_=22,s7_=23,t8_=24,t9_=25,
k0_=26,k1_=27,gp_=28,sp_=29,s8_=30,ra_=31;
always @(posedge clock) begin
dadrD3<=dest_addrD2;
dadrD4<=dadrD3;
dadrD5<=dadrD4;
dadrD6<=dadrD5;
tadrD1<=target_addr;
tadrD2<=tadrD1;
sadrD1<=source_addr;
sadrD2<=sadrD1;
if ( (mul_div_funcD2 ==4'b0000 ) ||
(mul_div_funcD2 ==4'b0001 ) ||
(mul_div_funcD2 ==4'b0010 ) ) WD3<=wren;//NOTHING,READLO/HI ÈOÅÍCgð~ßé
else WD3<=1'b0;
WD4<=WD3;
WD5<=WD4;
WD6<=WD5;
A_Right_SELD2<=A_Right_SELD1;
IMMD2<=IMMD1;
if (int_stateD1) PCD2<=PCCDD;//Jul.7.2004
else PCD2<=PCD1;
RRegSelD2<=RRegSelD1;
RRegSelD3<=RRegSelD2;
RRegSelD4<=RRegSelD3;
RRegSelD4_dup1<=RRegSelD3[0];
RRegSelD4_dup2<=RRegSelD3[0];
RRegSelD4_dup3<=RRegSelD3[0];
end
//AReg
always @(posedge clock) begin
case (RF_inputD2)
`RF_ALU_sel : AReg<=alu_out;
`RF_Shifter_sel: AReg<=shift_out;
`SHIFT16_SEL: AReg<= {IMMD2[15:0],16'h00};
`RF_PC_SEL : AReg<=mul_alu_out;
endcase
end
//ARegSel
always @(*) begin//Mar.5.2005
if (! mul_alu_selD2[1] ) mul_alu_out={6'b00_0000,PCD2};
else mul_alu_out=c_mult;
end
//NReg
always @(posedge clock) NReg<=AReg;
//RReg
always @(posedge clock) begin
case (RRegSelD4_dup1)
`MOUT_SEL : RReg<=MOUT;
`NREG_SEL: RReg<=NReg;
default : RReg<=MOUT;
endcase
end
//DReg
always @(posedge clock) begin
DReg<=RReg;
end
always @(*) begin
case (RRegSelD4_dup2)
`MOUT_SEL : RRegin=MOUT;
`NREG_SEL: RRegin=NReg;
default : RRegin=MOUT;
endcase
end
//target_reg
always @(*) memory_wdata=alu_right;
mul_div MulDiv(.clock(clock),.sync_reset(sync_reset),.a(alu_left),.b(alu_right),
.mul_div_out(c_mult),.mul_div_sign(mul_div_funcD2[1]),
.mul_div_word(1'b1),.mul_div_mode(mul_div_funcD2[2]),
.stop_state(pause_out),.mul_div_enable(mul_div_funcD2[3]),.lohi(mul_div_funcD2[0]));
assign mul_div_enable= mul_div_funcD2;
always @(posedge clock) begin
if (sync_reset) div_mode_ff<=1'b0;
else if (mul_div_enable) div_mode_ff<=mul_div_mode;
end
always @(posedge clock) begin
if (sync_reset) sign_ff<=1'b0;
else if (mul_div_enable) sign_ff<=mul_div_sign;
end
assign mul_div_mode=!(IMMD2[1] ==`MUL_DIV_MUL_SEL);//div high / mul low
assign mul_div_sign=!IMMD2[0];
alu alu1(.a(alu_left),.b(alu_right),.alu_func(ALU_FuncD2),.alu_out(alu_out));
shifter sh1(.a(alu_right),.shift_out(shift_out),.shift_func(Shift_FuncD2),
.shift_amount(Shift_Amount));
assign Shift_Amount=Shift_Amount_selD2==`SHIFT_AMOUNT_REG_SEL ?
alu_left[4:0] : Shift_amountD2;
//alu left latch
always @(posedge clock) begin
begin
if (sadrD1==dadrD4 && WD4) alu_left_latch<=RRegin;
//OK
else if (sadrD1==dadrD5 && WD5) alu_left_latch<=RReg;//This must be priority encoder
else if (sadrD1==dadrD6 && WD6) alu_left_latch<=DReg;
else alu_left_latch<=source_out;
end
end
//alu right latch
always @(posedge clock) begin
begin
case (A_Right_SELD1)
`Imm_signed : alu_right_latch<={ {16{IMMD1[15]}},IMMD1[15:0]};
`Imm_unsigned : alu_right_latch<={ 16'h000,IMMD1[15:0]};
`A_RIGHT_ERT : begin
if (tadrD1==dadrD4 && WD4 ) alu_right_latch<=RRegin;
else //OK
if (tadrD1==dadrD5 && WD5 ) alu_right_latch<=RReg;
else if (tadrD1==dadrD6 && WD6) alu_right_latch<=DReg;
else alu_right_latch<=target_out;
end
`IMM_26_SEL : begin
alu_right_latch<={6'b00_0000,IMMD1};
end
default : alu_right_latch<={ {16{IMMD1[15]}},IMMD1[15:0]};
endcase
end
end
`ifdef ALTERA
ram_regfile32xx32 RFile(
.data(regfile_in),
.wraddress(dadrD5),
.rdaddress_a(target_addr),
.rdaddress_b(source_addr),
.wren(WD5),
.clock(clock),
.qa(target_out),
.qb(source_out));
`else
ram32x32_xilinx RFile (
.data(regfile_in),
.wraddress(dadrD5),
.rdaddress_a(target_addr),
.rdaddress_b(source_addr),
.wren(WD5),
.clock(clock),
.qa(target_out),
.qb(source_out));
`endif
assign regfile_in=dadrD5==5'b0_0000 ? 32'h0000_0000 :RReg;
always @* begin //
case (stest1D_dup1)
1'b1: alu_left[7:0]=AReg[7:0];
1'b0:
case(stest2D)
1'b1:
case (RRegSelD4_dup3)
`MOUT_SEL : alu_left[7:0]=MOUT[7:0];
`NREG_SEL: alu_left[7:0]=NReg[7:0];
endcase
1'b0: alu_left[7:0]=alu_left_latch[7:0];
endcase
endcase
end
always @* begin //
case (stest1D_dup2)
1'b1: alu_left[15:8]=AReg[15:8];
1'b0:
case(stest2D)
1'b1:
case (RRegSelD4_dup3)
`MOUT_SEL : alu_left[15:8]=MOUT[15:8];
`NREG_SEL: alu_left[15:8]=NReg[15:8];
endcase
1'b0: alu_left[15:8]=alu_left_latch[15:8];
endcase
endcase
end
always @* begin//
case (stest1D_dup3)
1'b1: alu_left[23:16]=AReg[23:16];
1'b0:
case(stest2D)
1'b1:
case (RRegSelD4_dup3)
`MOUT_SEL : alu_left[23:16]=MOUT[23:16];
`NREG_SEL: alu_left[23:16]=NReg[23:16];
endcase
1'b0: alu_left[23:16]=alu_left_latch[23:16];
endcase
endcase
end
always @* begin //
case (stest1D_dup4)
1'b1: alu_left[31:24]=AReg[31:24];
1'b0:
case(stest2D)
1'b1:
case (RRegSelD4_dup3)
`MOUT_SEL : alu_left[31:24]=MOUT[31:24];
`NREG_SEL: alu_left[31:24]=NReg[31:24];
endcase
1'b0: alu_left[31:24]=alu_left_latch[31:24];
endcase
endcase
end
assign alu_right=test1D ? AReg :
test2D ? RRegin : alu_right_latch;
always @(posedge clock) begin
stest1D<=(sadrD1==dest_addrD2) && wren;
stest1D_dup1<=(sadrD1==dest_addrD2) && wren;
stest1D_dup2<=(sadrD1==dest_addrD2) && wren;
stest1D_dup3<=(sadrD1==dest_addrD2) && wren;
stest1D_dup4<=(sadrD1==dest_addrD2) && wren;
end
always @(posedge clock) begin
stest2D<=(sadrD1==dadrD3) && WD3 ;
end
always @(posedge clock) begin
test1D<=tadrD1==dest_addrD2 && (wren ) && A_Right_SELD1==`A_RIGHT_ERT;
end
always @(posedge clock) begin
test2D<=tadrD1==dadrD3 && (WD3 ) && A_Right_SELD1==`A_RIGHT_ERT;
end
`ifdef Veritak
reg [30*8:1] alu_function;
reg [30*8:1] shift_function;
reg [30*8:1] AReg_Input_Sel;
always @*//Jan.20.2005 @(ALU_FuncD2,alu_left,alu_right)
case (ALU_FuncD2)
`ALU_NOTHING : $sprintf(alu_function,"non_operation");
`ALU_ADD : $sprintf(alu_function,"ADD %h,%h",alu_left,alu_right);
`ALU_SUBTRACT :$sprintf(alu_function,"SUB %h,%h,alu_left,alu_right");
`ALU_LESS_THAN_UNSIGNED :$sprintf(alu_function ,"LT_Unsigned %h,%h",alu_left,alu_right);
`ALU_LESS_THAN_SIGNED : $sprintf(alu_function,"LT_Signed %h,%h",alu_left,alu_right);
`ALU_OR : $sprintf(alu_function,"OR %h,%h",alu_left,alu_right);
`ALU_AND : $sprintf(alu_function,"XOR %h,%h,alu_left,alu_right");
`ALU_XOR : $sprintf(alu_function,"AND %h,%h",alu_left,alu_right);
`ALU_NOR : $sprintf(alu_function,"NOR %h,%h",alu_left,alu_right);
default: $sprintf(alu_function,"non_operation");
endcase
always @* begin //
case (Shift_FuncD2)
`SHIFT_LEFT : $sprintf(shift_function,"SLL %d",Shift_Amount);
`SHIFT_RIGHT_UNSIGNED : $sprintf(shift_function,"SLR %d",Shift_Amount);
`SHIFT_RIGHT_SIGNED : $sprintf(shift_function,"SAR %d",Shift_Amount);
default: $sprintf(shift_function,"non_operation");
endcase
end
always @* begin //
case (RF_inputD2)
`RF_ALU_sel : $sprintf(AReg_Input_Sel,"ALU");
`RF_Shifter_sel: $sprintf(AReg_Input_Sel,"Shifter");
`SHIFT16_SEL: $sprintf(AReg_Input_Sel,"IMM16<<16");
`RF_PC_SEL : $sprintf(AReg_Input_Sel,"PC/MulOutSEL");
endcase
end
`endif
endmodule |
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : dlx_processor.v
// KEYWORDS : dlx, pipeline, core, toplevel
// -----------------------------------------------------------------------------
// PURPOSE: Top level entity of uDLX core processor
// -----------------------------------------------------------------------------
module dlx_processor
#(
parameter DATA_WIDTH = 32,
parameter INST_ADDR_WIDTH = 20,
parameter DATA_ADDR_WIDTH = 32
)
(
input clk,
input rst_n,
input enable,
output instr_rd_en,
output [INST_ADDR_WIDTH-1:0] instr_addr,
input [DATA_WIDTH-1:0] instruction,
output data_rd_en,
output data_wr_en,
output [DATA_ADDR_WIDTH-1:0] data_addr,
input [DATA_WIDTH-1:0] data_read,
output [DATA_WIDTH-1:0] data_write,
input boot_mode
);
localparam INSTRUCTION_WIDTH = DATA_WIDTH;
localparam PC_WIDTH = INST_ADDR_WIDTH;
localparam REG_ADDR_WIDTH = 5;
localparam OPCODE_WIDTH = 6;
localparam FUNCTION_WIDTH = 6;
localparam IMEDIATE_WIDTH = 16;
localparam PC_OFFSET_WIDTH = 26;
localparam PC_INITIAL_ADDRESS = 20'h00000;
// -----------------------------------------------------------------------------
// Internal signals
// -----------------------------------------------------------------------------
// Wires
// -----------------------------------------------------------------------------
// IF/ID Wires
// -----------------------------------------------------------------------------
wire [PC_WIDTH-1:0] if_id_new_pc;
wire [PC_WIDTH-1:0] new_pc;
wire [INSTRUCTION_WIDTH-1:0] if_id_instruction;
// wire [PC_WIDTH-1:0] instr_addr;
wire stall;
wire flush;
// -----------------------------------------------------------------------------
// ID/EX Wires
// -----------------------------------------------------------------------------
wire [DATA_WIDTH-1:0] data_alu_a;
wire [DATA_WIDTH-1:0] data_alu_b;
wire [OPCODE_WIDTH-1:0] opcode;
wire [FUNCTION_WIDTH-1:0] inst_function;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr1;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr2;
// wire [REG_ADDR_WIDTH-1:0] reg_wr_addr;
// wire reg_wr_en;
wire [REG_ADDR_WIDTH-1:0] reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] reg_b_wr_addr;
wire reg_a_wr_en;
wire reg_b_wr_en;
wire imm_inst;
wire [DATA_WIDTH-1:0] constant;
wire [PC_OFFSET_WIDTH-1:0] pc_offset;
wire mem_data_wr_en;
wire mem_data_rd_en;
wire write_back_mux_sel;
wire branch_inst;
wire branch_use_r;
wire jump_inst;
wire jump_use_r;
wire decode_flush;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_a_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_b_addr;
wire [INSTRUCTION_WIDTH-1:0] id_ex_instruction;
wire [OPCODE_WIDTH-1:0] id_ex_opcode;
wire [FUNCTION_WIDTH-1:0] id_ex_function;
wire id_ex_mem_data_rd_en;
wire id_ex_mem_data_wr_en;
wire id_ex_write_back_mux_sel;
// wire id_ex_reg_rd_en; TODO see
// wire id_ex_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] id_ex_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_b_wr_addr;
wire id_ex_reg_a_wr_en;
wire id_ex_reg_b_wr_en;
wire [DATA_WIDTH-1:0] id_ex_constant;
//wire id_ex_imm_inst;
wire [DATA_WIDTH-1:0] id_ex_data_alu_a;
wire [DATA_WIDTH-1:0] id_ex_data_alu_b;
wire [PC_WIDTH-1:0] id_ex_new_pc;
wire [PC_OFFSET_WIDTH-1:0] id_ex_pc_offset;
wire id_ex_branch_inst;
wire id_ex_branch_use_r;
wire id_ex_jump_inst;
wire id_ex_jump_use_r;
// -----------------------------------------------------------------------------
// EX/MEM Wires
// -----------------------------------------------------------------------------
wire ex_mem_data_rd_en;
wire ex_mem_data_wr_en;
wire [DATA_WIDTH-1:0] ex_mem_data_write;
wire [DATA_WIDTH-1:0] ex_mem_alu_data;
wire [DATA_WIDTH-1:0] ex_mem_hi_data;
wire [DATA_WIDTH-1:0] ex_mem_reg_data;
// wire ex_mem_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_b_wr_addr;
// wire [DATA_WIDTH-1:0] ex_mem_reg_a_wr_data;
// wire [DATA_WIDTH-1:0] ex_mem_reg_b_wr_data;
wire ex_mem_reg_a_wr_en;
wire ex_mem_reg_b_wr_en;
wire ex_mem_write_back_mux_sel;
wire ex_mem_select_new_pc;
wire [PC_WIDTH-1:0] ex_mem_new_pc;
wire [INSTRUCTION_WIDTH-1:0] ex_mem_instruction;
wire [DATA_WIDTH-1:0] mem_data;
wire [DATA_WIDTH-1:0] alu_data;
wire [DATA_WIDTH-1:0] hi_data;
wire fetch_select_new_pc;
wire [PC_WIDTH-1:0] fetch_new_pc;
// -----------------------------------------------------------------------------
// MEM/WB wires
// -----------------------------------------------------------------------------
wire mem_wb_write_back_mux_sel;
// wire [DATA_WIDTH-1:0] mem_wb_mem_data;
wire [DATA_WIDTH-1:0] mem_wb_alu_data;
wire [DATA_WIDTH-1:0] mem_wb_hi_data;
// wire mem_wb_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_b_wr_addr;
// wire [DATA_WIDTH-1:0] mem_wb_reg_a_wr_data;
// wire [DATA_WIDTH-1:0] mem_wb_reg_b_wr_data;
wire mem_wb_reg_a_wr_en;
wire mem_wb_reg_b_wr_en;
wire [INSTRUCTION_WIDTH-1:0] mem_wb_instruction;
// -----------------------------------------------------------------------------
// WB wires
// -----------------------------------------------------------------------------
// wire wb_write_enable;
// wire [DATA_WIDTH-1:0] wb_write_data;
// wire [REG_ADDR_WIDTH-1:0] wb_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] wb_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] wb_reg_b_wr_addr;
wire [DATA_WIDTH-1:0] wb_reg_a_wr_data;
wire [DATA_WIDTH-1:0] wb_reg_b_wr_data;
wire wb_reg_a_wr_en;
wire wb_reg_b_wr_en;
// -----------------------------------------------------------------------------
// Instruction Fetch modules
// -----------------------------------------------------------------------------
// Program Counter top level (including PC mux)
top_fetch
#(
.PC_DATA_WIDTH(PC_WIDTH),
.INSTRUCTION_WIDTH(DATA_WIDTH),
.PC_INITIAL_ADDRESS(PC_INITIAL_ADDRESS)
)
instruction_fetch_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.stall(stall),
.select_new_pc_in(fetch_select_new_pc),
.new_pc_in(fetch_new_pc),
.pc_out(new_pc),
.inst_mem_addr_out(instr_addr),
.boot_mode(boot_mode)
);
// -----------------------------------------------------------------------------
// Pipeline registers IF/ID
// -----------------------------------------------------------------------------
if_id_reg
#(
.INSTRUCTION_WIDTH(DATA_WIDTH),
.PC_DATA_WIDTH(PC_WIDTH)
)
if_id_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.stall(stall),
.flush(flush),
.inst_mem_data_in(instruction),
.pc_in(new_pc),
.new_pc_out(if_id_new_pc),
.instruction_reg_out(if_id_instruction)
);
// -----------------------------------------------------------------------------
// Instruction Decode modules
// -----------------------------------------------------------------------------
instruction_decode
#(
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.IMEDIATE_WIDTH(IMEDIATE_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
instruction_decode_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.instruction_in(if_id_instruction),
// write back
.reg_a_wr_addr_in(wb_reg_a_wr_addr),
.reg_b_wr_addr_in(wb_reg_b_wr_addr),
.reg_a_wr_data_in(wb_reg_a_wr_data),
.reg_b_wr_data_in(wb_reg_b_wr_data),
.reg_a_wr_en_in(wb_reg_a_wr_en),
.reg_b_wr_en_in(wb_reg_b_wr_en),
// .wb_write_enable_in(wb_write_enable),
// .wb_write_data_in(wb_write_data),
// .wb_reg_wr_addr_in(wb_reg_wr_addr),
.select_new_pc_in(ex_mem_select_new_pc),
// ----- Hazzard control -----
.id_ex_mem_data_rd_en_in(id_ex_mem_data_rd_en),
.id_ex_reg_wr_addr_in(id_ex_reg_a_wr_addr),
// -----
.reg_rd_addr1_out(reg_rd_addr1), //(id_ex_reg_a_addr),
.reg_rd_addr2_out(reg_rd_addr2), //(id_ex_reg_b_addr),
.opcode_out(opcode),
.inst_function_out(inst_function),
.mem_data_rd_en_out(mem_data_rd_en),//(id_ex_mem_data_rd_en),
.mem_data_wr_en_out(mem_data_wr_en),//(id_ex_mem_data_wr_en),
.write_back_mux_sel_out(write_back_mux_sel),//(id_ex_write_back_mux_sel),
// .reg_wr_en_out(reg_wr_en),(id_ex_reg_wr_en),
// .reg_wr_addr_out(reg_wr_addr),(id_ex_reg_wr_addr),
.reg_a_wr_addr_out(reg_a_wr_addr),
.reg_b_wr_addr_out(reg_b_wr_addr),
.reg_a_wr_en_out(reg_a_wr_en),
.reg_b_wr_en_out(reg_b_wr_en),
.constant_out(constant), //(id_ex_constant),
.imm_inst_out(imm_inst), //(id_ex_imm_inst),
.data_alu_a_out(data_alu_a),//(id_ex_data_alu_a),
.data_alu_b_out(data_alu_b),//(id_ex_data_alu_b),
.pc_offset_out(pc_offset),//(id_ex_pc_offset),
.branch_inst_out(branch_inst),//(id_ex_branch_inst),
.branch_use_r_out(branch_use_r),
.jump_inst_out(jump_inst),//(id_ex_jump_inst),
.jump_use_r_out(jump_use_r),//(id_ex_jump_use_r),
.rd_inst_ena_out(instr_rd_en),
.stall_out(stall),
.general_flush_out(flush),
.decode_flush_out(decode_flush)
);
// -----------------------------------------------------------------------------
// Pipeline registers ID/EX
// -----------------------------------------------------------------------------
id_ex_reg
#(
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.IMEDIATE_WIDTH(IMEDIATE_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
id_ex_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.flush_in(decode_flush),
.data_alu_a_in(data_alu_a),
.data_alu_b_in(data_alu_b),
.new_pc_in(if_id_new_pc),
.instruction_in(if_id_instruction),
.opcode_in(opcode),
.inst_function_in(inst_function),
.reg_rd_addr1_in(reg_rd_addr1),
.reg_rd_addr2_in(reg_rd_addr2),
// .reg_wr_addr_in(reg_wr_addr),
// .reg_wr_en_in(reg_wr_en),
.reg_a_wr_addr_in(reg_a_wr_addr),
.reg_b_wr_addr_in(reg_b_wr_addr),
.reg_a_wr_en_in(reg_a_wr_en),
.reg_b_wr_en_in(reg_b_wr_en),
.constant_in(constant),
.imm_inst_in(imm_inst),
.pc_offset_in(pc_offset),
.mem_data_wr_en_in(mem_data_wr_en),
.mem_data_rd_en_in(mem_data_rd_en),
.write_back_mux_sel_in(write_back_mux_sel),
.branch_inst_in(branch_inst),
.branch_use_r_in(branch_use_r),
.jump_inst_in(jump_inst),
.jump_use_r_in(jump_use_r),
// Outputs
.data_alu_a_out(id_ex_data_alu_a),
.data_alu_b_out(id_ex_data_alu_b),
.new_pc_out(id_ex_new_pc),
.instruction_out(id_ex_instruction),
.opcode_out(id_ex_opcode),
.inst_function_out(id_ex_function),
.reg_rd_addr1_out(id_ex_reg_a_addr),
.reg_rd_addr2_out(id_ex_reg_b_addr),
// .reg_wr_addr_out(id_ex_reg_wr_addr),
// .reg_wr_en_out(id_ex_reg_wr_en),
.reg_a_wr_addr_out(id_ex_reg_a_wr_addr),
.reg_b_wr_addr_out(id_ex_reg_b_wr_addr),
.reg_a_wr_en_out(id_ex_reg_a_wr_en),
.reg_b_wr_en_out(id_ex_reg_b_wr_en),
.constant_out(id_ex_constant),
.imm_inst_out(id_ex_imm_inst),
.pc_offset_out(id_ex_pc_offset),
.mem_data_wr_en_out(id_ex_mem_data_wr_en),
.mem_data_rd_en_out(id_ex_mem_data_rd_en),
.write_back_mux_sel_out(id_ex_write_back_mux_sel),
.branch_inst_out(id_ex_branch_inst),
.branch_use_r_out(id_ex_branch_use_r),
.jump_inst_out(id_ex_jump_inst),
.jump_use_r_out(id_ex_jump_use_r)
);
// -----------------------------------------------------------------------------
// Execute modules
// -----------------------------------------------------------------------------
execute_address_calculate
#(
.DATA_WIDTH(DATA_WIDTH),
.PC_WIDTH(PC_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
execute_address_calculate_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.alu_opcode_in(id_ex_opcode),
.alu_function_in(id_ex_function),
.data_alu_a_in(id_ex_data_alu_a),
.data_alu_b_in(id_ex_data_alu_b),
.reg_a_addr_in(id_ex_reg_a_addr),
.reg_b_addr_in(id_ex_reg_b_addr),
.constant_in(id_ex_constant),
.imm_inst_in(id_ex_imm_inst),
.new_pc_in(id_ex_new_pc),
.pc_offset_in(id_ex_pc_offset),
.branch_inst_in(id_ex_branch_inst),
.branch_use_r_in(id_ex_branch_use_r),
.jmp_inst_in(id_ex_jump_inst),
.jmp_use_r_in(id_ex_jump_use_r),
.instruction_in(id_ex_instruction),
//fowarding input
.ex_mem_reg_a_data_in(ex_mem_alu_data),//ex_mem_reg_a_wr_data),//input
.ex_mem_reg_b_data_in(ex_mem_hi_data),//ex_mem_reg_b_wr_data),//input
.ex_mem_reg_a_addr_in(ex_mem_reg_a_wr_addr),//input
.ex_mem_reg_b_addr_in(ex_mem_reg_b_wr_addr),//input
.ex_mem_reg_a_wr_ena_in(ex_mem_reg_a_wr_en),//input
.ex_mem_reg_b_wr_ena_in(ex_mem_reg_b_wr_en),//input
.wb_reg_a_data_in(wb_reg_a_wr_data),
.wb_reg_b_data_in(wb_reg_b_wr_data),
.wb_reg_a_addr_in(wb_reg_a_wr_addr),
.wb_reg_b_addr_in(wb_reg_b_wr_addr),
.wb_reg_a_wr_ena_in(wb_reg_a_wr_en),
.wb_reg_b_wr_ena_in(wb_reg_b_wr_en),
.mem_data_out(mem_data),
.alu_data_out(alu_data),
.hi_data_out(hi_data),
.fetch_new_pc_out(fetch_new_pc),
.fetch_select_new_pc_out(fetch_select_new_pc)
);
assign data_addr = ex_mem_alu_data;
assign data_rd_en = ex_mem_data_rd_en;
assign data_wr_en = ex_mem_data_wr_en;
assign data_write = ex_mem_data_write;
assign ex_mem_reg_data = ex_mem_alu_data;
// -----------------------------------------------------------------------------
// Pipeline registers EX/MEM
// -----------------------------------------------------------------------------
ex_mem_reg
#(
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
ex_mem_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.flush_in(flush),
.mem_data_rd_en_in(id_ex_mem_data_rd_en),
.mem_data_wr_en_in(id_ex_mem_data_wr_en),
.mem_data_in(mem_data),
.alu_data_in(alu_data),
.hi_data_in(hi_data),
// .reg_wr_en_in(id_ex_reg_wr_en),
// .reg_wr_addr_in(id_ex_reg_wr_addr),
.reg_a_wr_addr_in(id_ex_reg_a_wr_addr),
.reg_b_wr_addr_in(id_ex_reg_b_wr_addr),
.reg_a_wr_en_in(id_ex_reg_a_wr_en),
.reg_b_wr_en_in(id_ex_reg_b_wr_en),
.write_back_mux_sel_in(id_ex_write_back_mux_sel),
.select_new_pc_in(fetch_select_new_pc),
.new_pc_in(fetch_new_pc),
.instruction_in(id_ex_instruction),
.mem_data_rd_en_out(ex_mem_data_rd_en),
.mem_data_wr_en_out(ex_mem_data_wr_en),
.mem_data_out(ex_mem_data_write),
.alu_data_out(ex_mem_alu_data),
.hi_data_out(ex_mem_hi_data),
// .reg_wr_en_out(ex_mem_reg_wr_en),
// .reg_wr_addr_out(ex_mem_reg_wr_addr),
.reg_a_wr_addr_out(ex_mem_reg_a_wr_addr),
.reg_b_wr_addr_out(ex_mem_reg_b_wr_addr),
.reg_a_wr_en_out(ex_mem_reg_a_wr_en),
.reg_b_wr_en_out(ex_mem_reg_b_wr_en),
.write_back_mux_sel_out(ex_mem_write_back_mux_sel),
.select_new_pc_out(ex_mem_select_new_pc),
.new_pc_out(ex_mem_new_pc),
.instruction_out(ex_mem_instruction)
);
// -----------------------------------------------------------------------------
// Memory Access modules
// Due to data memory to be outside Core processor, this RTL contains only
// the pipeline registers. The memory access is due by the Memory Interface.
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// Pipeline registers MEM/WB
// -----------------------------------------------------------------------------
mem_wb_reg
#(
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
mem_wb_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.write_back_mux_sel_in(ex_mem_write_back_mux_sel),
.alu_data_in(ex_mem_alu_data),
.hi_data_in(ex_mem_hi_data),
// .reg_wr_en_in(ex_mem_reg_wr_en),
// .reg_wr_addr_in(ex_mem_reg_wr_addr),
.reg_a_wr_addr_in(ex_mem_reg_a_wr_addr),
.reg_b_wr_addr_in(ex_mem_reg_b_wr_addr),
.reg_a_wr_en_in(ex_mem_reg_a_wr_en),
.reg_b_wr_en_in(ex_mem_reg_b_wr_en),
.instruction_in(ex_mem_instruction),
.write_back_mux_sel_out(mem_wb_write_back_mux_sel),
.alu_data_out(mem_wb_alu_data),
.hi_data_out(mem_wb_hi_data),
// .reg_wr_en_out(mem_wb_reg_wr_en),
// .reg_wr_addr_out(mem_wb_reg_wr_addr),
.reg_a_wr_addr_out(mem_wb_reg_a_wr_addr),
.reg_b_wr_addr_out(mem_wb_reg_b_wr_addr),
.reg_a_wr_en_out(mem_wb_reg_a_wr_en),
.reg_b_wr_en_out(mem_wb_reg_b_wr_en),
.instruction_out(mem_wb_instruction)
);
// -----------------------------------------------------------------------------
// Write-back multiplexer
// -----------------------------------------------------------------------------
write_back
#(
.DATA_WIDTH(DATA_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
write_back_u0
(
.mem_data_in(data_read),
.alu_data_in(mem_wb_alu_data),
.hi_data_in(mem_wb_hi_data),
// .reg_wr_en_in(mem_wb_reg_wr_en),
// .reg_wr_addr_in(mem_wb_reg_wr_addr),
.reg_a_wr_addr_in(mem_wb_reg_a_wr_addr),
.reg_b_wr_addr_in(mem_wb_reg_b_wr_addr),
.reg_a_wr_en_in(mem_wb_reg_a_wr_en),
.reg_b_wr_en_in(mem_wb_reg_b_wr_en),
.write_back_mux_sel(mem_wb_write_back_mux_sel),
.reg_a_wr_addr_out(wb_reg_a_wr_addr),
.reg_b_wr_addr_out(wb_reg_b_wr_addr),
.reg_a_wr_data_out(wb_reg_a_wr_data),
.reg_b_wr_data_out(wb_reg_b_wr_data),
.reg_a_wr_en_out(wb_reg_a_wr_en),
.reg_b_wr_en_out(wb_reg_b_wr_en)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Top level multiplier and MAC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Multiplier is 32x32 however multiply instructions only ////
//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
//// ////
//// To Do: ////
//// - make signed division better, w/o negating the operands ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
`ifdef OR1200_IMPL_DIV
wire [31:0] div_result;
`endif
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
`ifdef OR1200_MULT_IMPLEMENTED
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b
`ifdef OR1200_IMPL_DIV
or div_result
`endif
)
casex(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV:
result = a[31] ^ b[31] ? ~div_result + 1'b1 : div_result;
`OR1200_ALUOP_DIVU:
result = div_result;
`endif
`OR1200_ALUOP_MUL:
result = mul_prod_r[31:0];
default:
result = mac_r[59:28];
endcase
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier
//
always @(posedge rst or posedge clk)
if (rst) begin
mul_prod_r <= #1 64'h0000_0000_0000_0000;
end
else begin
mul_prod_r <= #1 mul_prod[63:0];
end
//
// Registered output from the divider
//
`ifdef OR1200_IMPL_DIV
reg [2:0] div_cntr;
reg [width-1:0] div_x_r;
reg [width-1:0] div_t;
reg [2*width-1:0] div_y_r;
wire [3:0] cmp0;
wire [31:0] cmp3_x0 = cmp0[3] ? x - {y, 31'h0} : x;
wire [31:0] cmp2_x0 = cmp0[2] ? cmp3_x0 - {y, 30'h0} : cmp3_x0;
wire [31:0] cmp1_x0 = cmp0[1] ? cmp2_x0 - {y, 29'h0} : cmp2_x0;
wire [31:0] cmp0_x0 = cmp0[0] ? cmp1_x0 - {y, 28'h0} : cmp1_x0;
assign cmp0[3] = ({y, 31'h0} <= x);
assign cmp0[2] = ({y, 30'h0} <= cmp3_x0);
assign cmp0[1] = ({y, 29'h0} <= cmp2_x0);
assign cmp0[0] = ({y, 28'h0} <= cmp1_x0);
wire [3:0] cmp;
wire [31:0] cmp3_x = cmp[3] ? div_x_r- div_y_r[63:1] : div_x_r;
wire [31:0] cmp2_x = cmp[2] ? cmp3_x - div_y_r[63:2] : cmp3_x;
wire [31:0] cmp1_x = cmp[1] ? cmp2_x - div_y_r[63:3] : cmp2_x;
wire [31:0] cmp0_x = cmp[0] ? cmp1_x - div_y_r[63:4] : cmp1_x;
assign cmp[3] = (div_y_r[63:1] <= div_x_r);
assign cmp[2] = (div_y_r[63:2] <= cmp3_x);
assign cmp[1] = (div_y_r[63:3] <= cmp2_x);
assign cmp[0] = (div_y_r[63:4] <= cmp1_x);
wire [63:0] div_y = (div_cntr == 3'h0) ? {y, 32'h0} : div_y_r;
assign div_result = {div_t[31-4:0], cmp};
wire [31:0] div_result0 = {div_t[31-4:0], ((div_cntr == 3'h0) ? cmp0 : cmp)};
always @(posedge rst or posedge clk)
if (rst) begin
div_y_r <= #1 64'h0000_0000;
div_x_r <= #1 32'h0000_0000;
div_t <= #1 32'h0000_0000;
div_cntr <= #1 3'h0;
end else begin
if (alu_op_div_divu) begin
div_cntr <= #1 div_cntr + 3'h1;
div_x_r <= #1 (div_cntr == 3'h0) ? cmp0_x0 : cmp0_x;
div_t <= #1 div_result0;
div_y_r <= #1 {4'h0, div_y[63:4]};
end else begin
div_cntr <= #1 3'h0;
end
end
`endif // OR1200_IMPL_DIV
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= #1 mac_op;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= #1 mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= #1 mac_op_r2;
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
if (rst)
mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= #1 spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= #1 spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= #1 mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= #1 mac_r - mul_prod_r;
else if (macrc_op & !ex_freeze)
mac_r <= #1 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
if (rst)
mac_stall_r <= #1 1'b0;
else
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_macc_mul_32s_bkb_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[32 - 1 : 0] a;
input[32 - 1 : 0] b;
output[32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
reg signed [32 - 1 : 0] buff1;
reg signed [32 - 1 : 0] buff2;
reg signed [32 - 1 : 0] buff3;
reg signed [32 - 1 : 0] buff4;
assign p = buff4;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end
end
endmodule
`timescale 1 ns / 1 ps
module hls_macc_mul_32s_bkb(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
hls_macc_mul_32s_bkb_MulnS_0 hls_macc_mul_32s_bkb_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives scatter gather address/length info and requests
// the scatter gather data from the RX engine. Monitors the state of the scatter
// gather FIFO to make sure it can accommodate the requested data. Also signals
// when the entire scatter gather data has been received so the buffer can be
// overwritten with new data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGREQ_IDLE 8'b0000_0001
`define S_SGREQ_WAIT_0 8'b0000_0010
`define S_SGREQ_WAIT_1 8'b0000_0100
`define S_SGREQ_CHECK 8'b0000_1000
`define S_SGREQ_ISSUE 8'b0001_0000
`define S_SGREQ_UPDATE 8'b0010_0000
`define S_SGREQ_COUNT 8'b0100_0000
`define S_SGREQ_FLUSH 8'b1000_0000
`timescale 1ns/1ns
module sg_list_requester #(
parameter C_FIFO_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_WORDS_PER_ELEM = 4,
parameter C_MAX_ELEMS = 200,
parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input USER_RST, // User reset, should clear FIFO data too
output BUF_RECVD, // Signals when scatter gather buffer received
input [31:0] BUF_DATA, // Buffer data
input BUF_LEN_VALID, // Buffer length valid
input BUF_ADDR_HI_VALID, // Buffer high address valid
input BUF_ADDR_LO_VALID, // Buffer low address valid
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Scatter gather FIFO count
output FIFO_FLUSH, // Scatter gather FIFO flush request
input FIFO_FLUSHED, // Scatter gather FIFO flushed
output FIFO_RST, // Scatter gather FIFO data reset request
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been issued
input RX_DONE // Request has completed (data received)
);
`include "functions.vh"
reg [31:0] rData=0, _rData=0;
reg rAddrHiValid=0, _rAddrHiValid=0;
reg rAddrLoValid=0, _rAddrLoValid=0;
reg rLenValid=0, _rLenValid=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg rDone=0, _rDone=0;
reg rDelay=0, _rDelay=0;
reg [2:0] rCarry=0, _rCarry=0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg [9:0] rLen=0, _rLen=0;
reg rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg rUserRst=0, _rUserRst=0;
reg rRecvdAll=0, _rRecvdAll=0;
reg [10:0] rAckCount=0, _rAckCount=0;
assign BUF_RECVD = rDone;
assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
// Buffer signals coming from outside the rx_port.
always @ (posedge CLK) begin
rData <= #1 _rData;
rAddrHiValid <= #1 _rAddrHiValid;
rAddrLoValid <= #1 _rAddrLoValid;
rLenValid <= #1 _rLenValid;
end
always @ (*) begin
_rData = BUF_DATA;
_rAddrHiValid = BUF_ADDR_HI_VALID;
_rAddrLoValid = BUF_ADDR_LO_VALID;
_rLenValid = BUF_LEN_VALID;
end
// Handle requesting the next scatter gather buffer data.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
rDone <= #1 (RST ? 1'd0 : _rDone);
rDelay <= #1 _rDelay;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rBufWords <= #1 _rBufWords;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rLen <= #1 _rLen;
rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end
always @ (*) begin
_rState = rState;
_rDone = rDone;
_rDelay = rDelay;
_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
case (rState)
`S_SGREQ_IDLE: begin // Wait for addr & length
_rDone = 0;
if (rLenValid)
_rState = `S_SGREQ_WAIT_0;
end
`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
_rDelay = 0;
_rState = `S_SGREQ_WAIT_1;
end
`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
_rDelay = 1;
if (rDelay)
_rState = `S_SGREQ_CHECK;
end
`S_SGREQ_CHECK: begin // Wait for space to be made available
if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
_rState = `S_SGREQ_ISSUE;
else if (rUserRst)
_rState = `S_SGREQ_COUNT;
end
`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
if (RX_REQ_ACK)
_rState = `S_SGREQ_UPDATE;
end
`S_SGREQ_UPDATE: begin // Update the address and length
if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
_rState = `S_SGREQ_COUNT;
else if (rValsProp[3])
_rState = `S_SGREQ_ISSUE;
end
`S_SGREQ_COUNT: begin // Wait for read data to arrive
if (rRecvdAll)
_rState = `S_SGREQ_FLUSH;
end
`S_SGREQ_FLUSH: begin // Wait for read data to arrive
if (FIFO_FLUSHED) begin
_rDone = !rUserRst;
_rState = `S_SGREQ_IDLE;
end
end
default: begin
_rState = `S_SGREQ_IDLE;
end
endcase
end
// Keep track of requests made and requests completed so we know when all
// the outstanding data has been received.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rRecvdAll <= #1 _rRecvdAll;
end
always @ (*) begin
// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
_rRecvdAll = (rAckCount == 10'd0);
if (rState[0]) // S_SGREQ_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_BLACKBOX_V
|
`timescale 1ns / 1ps
// KCP53002 Furcula to Wishbone bus bridge
//
// Note that Furcula is, in reality, a slight modification of Wishbone.
// Since these two interconnects share so many signals in common, the
// interface to the bridge is kept very small.
module bridge(
// FURCULA BUS
input f_signed_i,
input [1:0] f_siz_i,
input [2:0] f_adr_i,
input [63:0] f_dat_i,
output [63:0] f_dat_o,
// WISHBONE BUS
output [7:0] wb_sel_o,
output [63:0] wb_dat_o,
input [63:0] wb_dat_i
);
// Wishbone SEL_O signal generation.
wire size_byte = (f_siz_i == 2'b00);
wire size_hword = (f_siz_i == 2'b01);
wire size_word = (f_siz_i == 2'b10);
wire size_dword = (f_siz_i == 2'b11);
wire ab7 = f_adr_i[2:0] == 3'b111;
wire ab6 = f_adr_i[2:0] == 3'b110;
wire ab5 = f_adr_i[2:0] == 3'b101;
wire ab4 = f_adr_i[2:0] == 3'b100;
wire ab3 = f_adr_i[2:0] == 3'b011;
wire ab2 = f_adr_i[2:0] == 3'b010;
wire ab1 = f_adr_i[2:0] == 3'b001;
wire ab0 = f_adr_i[2:0] == 3'b000;
wire ah3 = f_adr_i[2:1] == 2'b11;
wire ah2 = f_adr_i[2:1] == 2'b10;
wire ah1 = f_adr_i[2:1] == 2'b01;
wire ah0 = f_adr_i[2:1] == 2'b00;
wire aw1 = f_adr_i[2] == 1'b1;
wire aw0 = f_adr_i[2] == 1'b0;
wire den = size_dword;
wire wen1 = size_word & aw1;
wire wen0 = size_word & aw0;
wire hen3 = size_hword & ah3;
wire hen2 = size_hword & ah2;
wire hen1 = size_hword & ah1;
wire hen0 = size_hword & ah0;
wire ben7 = size_byte & ab7;
wire ben6 = size_byte & ab6;
wire ben5 = size_byte & ab5;
wire ben4 = size_byte & ab4;
wire ben3 = size_byte & ab3;
wire ben2 = size_byte & ab2;
wire ben1 = size_byte & ab1;
wire ben0 = size_byte & ab0;
wire sel7 = den | wen1 | hen3 | ben7;
wire sel6 = den | wen1 | hen3 | ben6;
wire sel5 = den | wen1 | hen2 | ben5;
wire sel4 = den | wen1 | hen2 | ben4;
wire sel3 = den | wen0 | hen1 | ben3;
wire sel2 = den | wen0 | hen1 | ben2;
wire sel1 = den | wen0 | hen0 | ben1;
wire sel0 = den | wen0 | hen0 | ben0;
assign wb_sel_o = {sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0};
// Furcula-to-Wishbone Data Routing
wire [7:0] od7 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[63:56] : 0);
wire [7:0] od6 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[55:48] : 0);
wire [7:0] od5 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[47:40] : 0);
wire [7:0] od4 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[7:0] : 0) |
(size_dword ? f_dat_i[39:32] : 0);
wire [7:0] od3 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[31:24] : 0);
wire [7:0] od2 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[23:16] : 0);
wire [7:0] od1 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[15:8] : 0);
wire [7:0] od0 = f_dat_i[7:0];
assign wb_dat_o = {od7, od6, od5, od4, od3, od2, od1, od0};
// Wishbone to Furcula Data Routing
wire [31:0] id2 =
(wen1 ? wb_dat_i[63:32] : 0) |
(wen0 ? wb_dat_i[31:0] : 0);
wire [15:0] id1 =
(hen3 ? wb_dat_i[63:48] : 0) |
(hen2 ? wb_dat_i[47:32] : 0) |
(hen1 ? wb_dat_i[31:16] : 0) |
(hen0 ? wb_dat_i[15:0] : 0);
wire [7:0] id0 =
(ben7 ? wb_dat_i[63:56] : 0) |
(ben6 ? wb_dat_i[55:48] : 0) |
(ben5 ? wb_dat_i[47:40] : 0) |
(ben4 ? wb_dat_i[39:32] : 0) |
(ben3 ? wb_dat_i[31:24] : 0) |
(ben2 ? wb_dat_i[23:16] : 0) |
(ben1 ? wb_dat_i[15:8] : 0) |
(ben0 ? wb_dat_i[7:0] : 0);
wire [63:32] id2s = (f_signed_i ? {32{id2[31]}} : 32'd0);
wire [63:16] id1s = (f_signed_i ? {48{id1[15]}} : 48'd0);
wire [63:8] id0s = (f_signed_i ? {56{id0[7]}} : 56'd0);
assign f_dat_o =
(size_dword ? wb_dat_i : 0) |
(size_word ? {id2s, id2} : 0) |
(size_hword ? {id1s, id1} : 0) |
(size_byte ? {id0s, id0} : 0);
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(* ################################################################# *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (mostly works), and Scheme (a bit
out of date). *)
Require Coq.extraction.Extraction.
Extraction Language OCaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
From Coq Require Import Arith.Arith.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.EqNat.
From LF Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ################################################################# *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant eqb => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ################################################################# *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we first need
to set up the right correspondence between Coq strings and lists
of OCaml characters. *)
Require Import ExtrOcamlBasic.
Require Import ExtrOcamlString.
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
From LF Require Import Imp.
From LF Require Import ImpParser.
From LF Require Import Maps.
Extraction "imp.ml" empty_st ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ################################################################# *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(* ################################################################# *)
(** * Going Further *)
(** Further details about extraction can be found in the Extract
chapter in _Verified Functional Algorithms_ (_Software
Foundations_ volume 3). *)
(* Wed Jan 9 12:02:46 EST 2019 *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2016 01:13:48 PM
// Design Name:
// Module Name: Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Add_Subt
#(parameter SWR=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR-1:0] Data_Result_o,
//output wire [SWR-1:0] P_o,
//output wire [SWR-1:1] Cn_o,
output wire FSM_C_o
);
wire [SWR-1:0] Data_B;
wire [SWR:0] S_to_D;
wire [SWR-1:0] P_to_D;
wire [SWR-1:1] C_to_D;
wire Co_to_D;
//wire Co_to_gate;
/*
/////////////////////////////////////////7
genvar j;
for (j=0; j<SWR; j=j+1)begin
assign Data_B[j] = PreData_B_i[j] ^ Add_Sub_op_i;
end
Full_Adder_PG #(.SWR(SWR)) AS_Module(
.clk(clk),
.rst(rst),
.Op_A_i(Data_A_i),
.Op_B_i(Data_B),
.C_i(Add_Sub_op_i), //Carry in
.S_o(S_to_D), // Solution out
.Cn_o(C_to_D),
.C_o(Co_to_gate), //Carry out
.P_o(P_o) //Propagate (for LZA)
);*/
add_sub_carry_out #(.W(SWR)) Sgf_AS (
.op_mode(Add_Sub_op_i),
.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D)
);
assign Co_to_D = S_to_D[SWR] & ~Add_Sub_op_i;
RegisterAdd #(.W(SWR)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR-1:0]),
.Q (Data_Result_o)
);
/*RegisterAdd #(.W(SWR)) P_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (P_to_D),
.Q (P_o)
);*/
/*RegisterAdd #(.W(SWR-1)) C_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (C_to_D),
.Q (Cn_o)
);*/
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR]),
.Q (FSM_C_o)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_reset.v
*
* Date : 2012-11
*
* Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
* respective clocks.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_reset(
por_rst_n,
sys_rst_n,
rst_out_n,
m_axi_gp0_clk,
m_axi_gp1_clk,
s_axi_gp0_clk,
s_axi_gp1_clk,
s_axi_hp0_clk,
s_axi_hp1_clk,
s_axi_hp2_clk,
s_axi_hp3_clk,
s_axi_acp_clk,
m_axi_gp0_rstn,
m_axi_gp1_rstn,
s_axi_gp0_rstn,
s_axi_gp1_rstn,
s_axi_hp0_rstn,
s_axi_hp1_rstn,
s_axi_hp2_rstn,
s_axi_hp3_rstn,
s_axi_acp_rstn,
fclk_reset3_n,
fclk_reset2_n,
fclk_reset1_n,
fclk_reset0_n,
fpga_acp_reset_n,
fpga_gp_m0_reset_n,
fpga_gp_m1_reset_n,
fpga_gp_s0_reset_n,
fpga_gp_s1_reset_n,
fpga_hp_s0_reset_n,
fpga_hp_s1_reset_n,
fpga_hp_s2_reset_n,
fpga_hp_s3_reset_n
);
input por_rst_n;
input sys_rst_n;
input m_axi_gp0_clk;
input m_axi_gp1_clk;
input s_axi_gp0_clk;
input s_axi_gp1_clk;
input s_axi_hp0_clk;
input s_axi_hp1_clk;
input s_axi_hp2_clk;
input s_axi_hp3_clk;
input s_axi_acp_clk;
output reg m_axi_gp0_rstn;
output reg m_axi_gp1_rstn;
output reg s_axi_gp0_rstn;
output reg s_axi_gp1_rstn;
output reg s_axi_hp0_rstn;
output reg s_axi_hp1_rstn;
output reg s_axi_hp2_rstn;
output reg s_axi_hp3_rstn;
output reg s_axi_acp_rstn;
output rst_out_n;
output fclk_reset3_n;
output fclk_reset2_n;
output fclk_reset1_n;
output fclk_reset0_n;
output fpga_acp_reset_n;
output fpga_gp_m0_reset_n;
output fpga_gp_m1_reset_n;
output fpga_gp_s0_reset_n;
output fpga_gp_s1_reset_n;
output fpga_hp_s0_reset_n;
output fpga_hp_s1_reset_n;
output fpga_hp_s2_reset_n;
output fpga_hp_s3_reset_n;
reg [31:0] fabric_rst_n;
reg r_m_axi_gp0_rstn;
reg r_m_axi_gp1_rstn;
reg r_s_axi_gp0_rstn;
reg r_s_axi_gp1_rstn;
reg r_s_axi_hp0_rstn;
reg r_s_axi_hp1_rstn;
reg r_s_axi_hp2_rstn;
reg r_s_axi_hp3_rstn;
reg r_s_axi_acp_rstn;
assign rst_out_n = por_rst_n & sys_rst_n;
assign fclk_reset0_n = !fabric_rst_n[0];
assign fclk_reset1_n = !fabric_rst_n[1];
assign fclk_reset2_n = !fabric_rst_n[2];
assign fclk_reset3_n = !fabric_rst_n[3];
assign fpga_acp_reset_n = !fabric_rst_n[24];
assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
task fpga_soft_reset;
input[31:0] reset_ctrl;
begin
fabric_rst_n[0] = reset_ctrl[0];
fabric_rst_n[1] = reset_ctrl[1];
fabric_rst_n[2] = reset_ctrl[2];
fabric_rst_n[3] = reset_ctrl[3];
fabric_rst_n[12] = reset_ctrl[12];
fabric_rst_n[13] = reset_ctrl[13];
fabric_rst_n[16] = reset_ctrl[16];
fabric_rst_n[17] = reset_ctrl[17];
fabric_rst_n[20] = reset_ctrl[20];
fabric_rst_n[21] = reset_ctrl[21];
fabric_rst_n[22] = reset_ctrl[22];
fabric_rst_n[23] = reset_ctrl[23];
fabric_rst_n[24] = reset_ctrl[24];
end
endtask
always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp0_rstn = 1'b0;
else
m_axi_gp0_rstn = 1'b1;
end
always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp1_rstn = 1'b0;
else
m_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp0_rstn = 1'b0;
else
s_axi_gp0_rstn = 1'b1;
end
always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp1_rstn = 1'b0;
else
s_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp0_rstn = 1'b0;
else
s_axi_hp0_rstn = 1'b1;
end
always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp1_rstn = 1'b0;
else
s_axi_hp1_rstn = 1'b1;
end
always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp2_rstn = 1'b0;
else
s_axi_hp2_rstn = 1'b1;
end
always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp3_rstn = 1'b0;
else
s_axi_hp3_rstn = 1'b1;
end
always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_acp_rstn = 1'b0;
else
s_axi_acp_rstn = 1'b1;
end
always@(*) begin
if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin
$display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state");
$finish();
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module adds the missing end of packet signal to the video stream. *
* *
******************************************************************************/
//`define USE_CLIPPER_DROP
module altera_up_video_decoder_add_endofpacket (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire internal_ready;
// Internal Registers
reg [DW: 0] internal_data;
reg internal_startofpacket;
reg internal_endofpacket;
reg internal_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_in_ready & stream_in_valid)
begin
stream_out_data <= internal_data;
stream_out_startofpacket <= internal_startofpacket;
stream_out_endofpacket <= internal_endofpacket | stream_in_startofpacket;
stream_out_valid <= internal_valid;
end
else if (stream_out_ready)
stream_out_valid <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
internal_data <= 'h0;
internal_startofpacket <= 1'b0;
internal_endofpacket <= 1'b0;
internal_valid <= 1'b0;
end
else if (stream_in_ready & stream_in_valid)
begin
internal_data <= stream_in_data;
internal_startofpacket <= stream_in_startofpacket;
internal_endofpacket <= stream_in_endofpacket;
internal_valid <= stream_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : flash_interface
// Author : Caleb Fangmeier
// Description : This is the interface HDL for the FPGA Flash on the ZEM.
// One interacts with this interface by first pushing all bytes to be written
// into the write buffer. This includes all bytes to be written after the
// instruction ( Address *and* Data). This finished, assert execute
// during the same clock cycle as presenting the instruction and the number
// of bytes to be read. If the instruction has any data read back, it will
// be placed into the read buffer as it becomes available. After the
// operation is complete, the busy signal will go low.
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module flash_interface(
input wire clk, // 150 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire [7:0] instruction,
input wire execute,
input wire [8:0] bytes_to_read,
output wire busy,
input wire [7:0] write_buffer_data,
input wire write_buffer_write,
output wire write_buffer_full,
output wire [7:0] read_buffer_q,
output wire read_buffer_empty,
input wire read_buffer_read,
//--------------------------------------------------------------------------
//-----------HARDWARE INTERFACE---------------------------------------------
//--------------------------------------------------------------------------
output wire flash_dq0,
input wire flash_dq1,
output wire flash_wb,
output wire flash_holdb,
output wire flash_c,
output reg flash_sb
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 3'd0,
DATA_WRITE_0 = 3'd1,
DATA_WRITE = 3'd2,
DATA_READ_0 = 3'd3,
DATA_READ = 3'd4;
localparam CLK_DIV = 2;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire update_in; // Read-in on positive edge of clock
wire update_out; // Write-out on negative edge of clk
wire write_buffer_empty;
wire [7:0] write_buffer_q;
wire [8:0] write_buffer_usedw;
wire [8:0] read_buffer_usedw;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [CLK_DIV:0] clk_div1;
reg [CLK_DIV:0] clk_div2;
reg [7:0] input_shifter;
reg [7:0] output_shifter;
reg [3:0] bit_counter;
reg [8:0] bytes_read;
reg [8:0] bytes_to_read_int;
reg write_buffer_read;
reg read_buffer_write;
reg [7:0] read_buffer_data;
reg [2:0] state;
reg busy_int;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign update_in = clk_div1[CLK_DIV] & ~clk_div2[CLK_DIV]; // posedge serial clock
assign update_out = ~clk_div1[CLK_DIV] & clk_div2[CLK_DIV]; // negedge serial clock
assign flash_c = clk_div2[CLK_DIV] & ~flash_sb;
assign flash_dq0 = output_shifter[7];
assign flash_wb = 1;
assign flash_holdb = 1;
assign busy = busy_int | execute;
//----------------------------------------------------------------------------
// Clock Division
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
clk_div2 <= 0;
clk_div1 <= 0;
end
else begin
clk_div2 <= clk_div1;
clk_div1 <= clk_div1 + 1;
end
end
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
always @( posedge clk ) begin
write_buffer_read <= 0;
read_buffer_write <= 0;
if ( reset ) begin
flash_sb <= 1;
state <= IDLE;
busy_int <= 1;
end
else begin
case ( state )
IDLE: begin
busy_int <= 0;
if ( execute ) begin
state <= DATA_WRITE_0;
output_shifter <= instruction;
bytes_to_read_int <= bytes_to_read;
busy_int <= 1;
end
end
DATA_WRITE_0: begin
if ( update_out ) begin
state <= DATA_WRITE;
flash_sb <= 0;
bit_counter <= 0;
end
end
DATA_WRITE: begin
if ( update_out ) begin
bit_counter <= bit_counter + 4'd1;
output_shifter <= {output_shifter[6:0], 1'b0};
if ( bit_counter == 4'd7 ) begin
bit_counter <= 0;
if ( !write_buffer_empty ) begin
output_shifter <= write_buffer_q;
write_buffer_read <= 1;
end
else if ( bytes_to_read_int > 0 ) begin
state <= DATA_READ;
output_shifter <= 0;
bytes_read <= 0;
end
else begin
state <= IDLE;
flash_sb <= 1;
busy_int <= 0;
end
end
end
end
DATA_READ: begin
if ( update_in ) begin
bit_counter <= bit_counter + 4'd1;
input_shifter <= {input_shifter[6:0], flash_dq1};
if ( bit_counter == 4'd7 ) begin
read_buffer_data <= {input_shifter[6:0], flash_dq1};
read_buffer_write <= 1;
bytes_read <= bytes_read + 9'd1;
end
end
else if ( update_out ) begin
if ( bit_counter == 4'd8 ) begin
bit_counter <= 4'b0;
if ( bytes_read == bytes_to_read_int ) begin
flash_sb <= 1;
state <= IDLE;
busy_int <= 0;
end
end
end
end
endcase
end
end
fifo8_256 write_buffer (
.clock ( clk ),
.sclr ( reset ),
.data ( write_buffer_data ),
.wrreq ( write_buffer_write ),
.full ( write_buffer_full ),
.rdreq ( write_buffer_read ),
.empty ( write_buffer_empty ),
.q ( write_buffer_q ),
.usedw ( write_buffer_usedw )
);
fifo8_256 read_buffer (
.clock ( clk ),
.sclr ( reset ),
.data ( read_buffer_data ),
.wrreq ( read_buffer_write ),
.full ( ),
.rdreq ( read_buffer_read ),
.empty ( read_buffer_empty ),
.q ( read_buffer_q ),
.usedw ( read_buffer_usedw )
);
endmodule
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 06/14/2014 at 20:26
// Component: CD32Shifter
module CD32Shifter (
output db9_6_out,
output db9_9_oe,
output db9_9_out,
input clock,
input db9_5_in,
input db9_6_in
);
//`#start body` -- edit after this line, do not edit this line
// Your code goes here
localparam OPERATION_SHIFT=3'b000;
localparam OPERATION_NOP=3'b001;
localparam OPERATION_LOAD=3'b010;
localparam OPERATION_LOADSHIFT=3'b011;
reg[2:0] operation;
localparam STATE_IDLE=2'b00;
localparam STATE_SHIFT1=2'b01;
localparam STATE_SHIFT2=2'b11;
reg[1:0] shiftstate;
wire mode;
assign mode=db9_5_in; // Shift register enable signal on DB9 pin 5.
wire shift;
assign shift=db9_6_in; // Shift register clock signal on DB9 pin 6.
wire firebutton; // Gets its value from the DataPath z1 signal (1 when A1=0).
// If the mode signal is high, then buttons 0 and 1 are passed through to DB9 pins 6 and 9, respectively
// If the mode signal is low, then the output of the shifter is passed to DB9 pin 9,
// while pin 6 becomes a clock signal.
wire shifted_data;
assign db9_9_out = shifted_data;
assign db9_6_out = mode ? firebutton : 1'b1;
// Need to use strong drive on pin 9 for speed, so for safety we avoid driving the
// pin high when not actively shifting.
assign db9_9_oe = ((shiftstate!=STATE_IDLE) | shifted_data==1'b0);
// FIXME - do we need more filtering on DB9_6_in?
always @(posedge clock)
begin
if(shiftstate==STATE_IDLE)
begin
shiftstate<=STATE_IDLE;
// Contintually load the current button status into the shift register while idle.
// This allows the first button's status to reach the s0 signal.
operation<=OPERATION_LOAD;
// Wait for mode signal to drop. When it does, start shifting.
if(mode==1'b0 && shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
end
else if(shiftstate==STATE_SHIFT1)
begin
operation<=OPERATION_NOP;
// Wait for posedge of the shift signal, shift data on transition.
if(shift==1'b1)
begin
shiftstate<=STATE_SHIFT2;
operation<=OPERATION_SHIFT;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else if(shiftstate==STATE_SHIFT2)
begin
operation<=OPERATION_NOP;
// Wait for negedge of the shift signal.
if(shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else
shiftstate<=STATE_IDLE;
end
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: SHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: NOP*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: LOAD*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: LOADSHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'hFF, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) CD32Shifter_DP(
/* input */ .reset(1'b0),
/* input */ .clk(clock),
/* input [02:00] */ .cs_addr(operation),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(firebutton), // We use A1 to bring the fire button's status into the component
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(shifted_data),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_9_srl_rtl #
(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
)
(
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire q // Output Data
);
localparam integer P_SRLDEPTH = 2**C_A_WIDTH;
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge clk)
if (ce)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
assign q = shift_reg[a];
endmodule
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_9_axic_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
// C_REG_CONFIG:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// 9 => SI/MI_REG = Source side completely registered (including S_VALID input)
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 9
// Source (SI) interface completely registered
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000009) begin
reg [C_DATA_WIDTH-1:0] s_payload_d;
wire [C_DATA_WIDTH-1:0] srl_out;
reg s_ready_i;
reg m_valid_i;
reg payld_sel;
reg push;
reg pop;
wire s_handshake_d;
(* max_fanout = 66 *) reg s_valid_d;
(* max_fanout = 66 *) reg s_ready_d = 1'b0;
(* max_fanout = 66 *) reg s_ready_reg = 1'b0;
(* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;
reg areset_d = 1'b0;
always @(posedge ACLK) begin
areset_d <= ARESET;
end
assign s_handshake_d = s_valid_d & s_ready_d;
always @ * begin
case (fifoaddr)
3'b111: begin // EMPTY: No payload in SRL; pre-assert m_ready
s_ready_i = 1'b1;
payld_sel = 1'b0;
pop = 1'b0;
case ({s_handshake_d, M_READY})
2'b00, 2'b01: begin // Idle
m_valid_i = 1'b0;
push = 1'b0;
end
2'b10: begin // Payload received
m_valid_i = 1'b1;
push = 1'b1;
end
2'b11: begin // Payload received and read out combinatorially
m_valid_i = 1'b1;
push = 1'b0;
end
endcase
end
3'b000: begin // 1 payload item in SRL
m_valid_i = 1'b1;
payld_sel = 1'b1;
case ({s_handshake_d, M_READY})
2'b00: begin // Idle
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b0;
end
2'b01: begin // Pop
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b1;
end
2'b10: begin // Push
s_ready_i = 1'b0; // Doesn't de-assert on SI until next cycle
push = 1'b1;
pop = 1'b0;
end
2'b11: begin // Push and Pop
s_ready_i = 1'b1;
push = 1'b1;
pop = 1'b1;
end
endcase
end
3'b001: begin // 2 payload items in SRL
m_valid_i = 1'b1;
payld_sel = 1'b1;
case ({s_handshake_d, M_READY})
2'b00: begin // Idle
s_ready_i = 1'b0;
push = 1'b0;
pop = 1'b0;
end
2'b01: begin // Pop
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b1;
end
2'b10: begin // Push (Handshake completes on SI while pushing 2nd item into SRL)
s_ready_i = 1'b0;
push = 1'b1;
pop = 1'b0;
end
2'b11: begin // Push and Pop
s_ready_i = 1'b0;
push = 1'b1;
pop = 1'b1;
end
endcase
end
3'b010: begin // 3 payload items in SRL
m_valid_i = 1'b1;
s_ready_i = 1'b0;
payld_sel = 1'b1;
push = 1'b0;
if (M_READY) begin // Handshake cannot complete on SI
pop = 1'b1;
end else begin
pop = 1'b0;
end
end
default: begin // RESET state (fifoaddr = 3'b110)
m_valid_i = 1'b0;
s_ready_i = 1'b0;
payld_sel = 1'b0;
push = 1'b1; // Advance to Empty state
pop = 1'b0;
end // RESET
endcase
end
always @(posedge ACLK) begin
if (areset_d) begin
fifoaddr <= 3'b110;
s_ready_reg <= 1'b0;
s_ready_d <= 1'b0;
end else begin
s_ready_reg <= s_ready_i;
s_ready_d <= s_ready_reg;
if (push & ~pop) begin
fifoaddr <= fifoaddr + 1;
end else if (~push & pop) begin
fifoaddr <= fifoaddr - 1;
end
end
end
always @(posedge ACLK) begin
s_valid_d <= S_VALID;
s_payload_d <= S_PAYLOAD_DATA;
end
assign S_READY = s_ready_reg;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
genvar i;
for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls
axi_register_slice_v2_1_9_srl_rtl #
(
.C_A_WIDTH (2)
)
srl_nx1
(
.clk (ACLK),
.a (fifoaddr[1:0]),
.ce (push),
.d (s_payload_d[i]),
.q (srl_out[i])
);
end
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Asynchronous Preset
// /___/ /\ Filename : FDPE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDPE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input PRE
);
reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
reg [0:0] IS_PRE_INVERTED_REG = IS_PRE_INVERTED;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire PRE_dly;
`endif
wire PRE_in;
`ifdef XIL_TIMING
assign PRE_in = (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz);
`else
assign PRE_in = (PRE ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz);
`endif
// begin behavioral model
reg Q_out;
assign #100 Q = Q_out;
always @(glblGSR or PRE_in)
if (glblGSR)
assign Q_out = INIT;
else if (PRE_in === 1'b1)
assign Q_out = 1'b1;
else if (PRE_in === 1'bx)
assign Q_out = 1'bx;
else
deassign Q_out;
`ifdef XIL_TIMING
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C_dly or posedge PRE_in)
if (PRE_in || (PRE === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C_dly or posedge PRE_in)
if (PRE_in || (PRE === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end
endgenerate
`else
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C or posedge PRE_in)
if (PRE_in || (PRE === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C or posedge PRE_in)
if (PRE_in || (PRE === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end
endgenerate
`endif
`ifdef XIL_TIMING
reg notifier;
wire notifier1;
`endif
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nset;
wire in_clk_enable, in_clk_enable_p, in_clk_enable_n;
wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n;
reg init_enable = 1'b1;
wire set_clk_enable, set_clk_enable_p, set_clk_enable_n;
`endif
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out);
not (nset, (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz));
and (in_clk_enable, ngsr, nset, CE || (CE === 1'bz));
and (ce_clk_enable, ngsr, nset, in_out);
and (set_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG);
always @(negedge nset) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1);
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1);
assign set_clk_enable_n = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b1);
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0);
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0);
assign set_clk_enable_p = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b0);
`endif
// end behavioral model
`ifdef XIL_TIMING
specify
(C => Q) = (100:100:100, 100:100:100);
(negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(PRE => Q) = (0:0:0, 0:0:0);
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$recrem (negedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly);
$recrem (negedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly);
$recrem (posedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly);
$recrem (posedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge PRE &&& init_enable, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge PRE &&& init_enable, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: stat_cnt
*******************************************************************/
`timescale 1ns/1ns
module stat_cnt
#(parameter
C_CNT_BW = 32
)
(
input clk ,
input rstn ,
//-- to/from the datapath to be monitored----
input [31:0] din,
input [31:0] dout,
input din_valid,
input dout_valid
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
// indata & incnt register
reg [31:0] indata;
reg [C_CNT_BW-1:0] incnt;
// outdata & outcnt register
reg [31:0] outdata;
reg [C_CNT_BW-1:0] outcnt;
// dummy signals
wire [31:0] dummy_signal_0; reg [31:0] dummy_signal_1;
//-------------------------------------------------------------------
// Statistic Registers
//-------------------------------------------------------------------
/* indata & incnt register */
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
indata <= 32'h0;
incnt <= 'h0; // .OR. {C_CNT_BW{1'b0}};
end else begin
if (din_valid) indata <= din;
if (din_valid) incnt <= incnt + 'h1;
end
end
/* outdata & outcnt register */
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
outdata <= 32'h0;
outcnt <= {C_CNT_BW{1'b0}};
end else begin
if (dout_valid) outdata <= dout;
if (dout_valid) outcnt <= outcnt + 'h1;
end
end
/*
always @(posedge clk or negedge rstn) begin
if (~rstn)
reg_dout <= 32'h0;
else
if (reg_rd_en) begin
case (reg_addr)
(XADDRBASE + 12'h00) : reg_dout <= indata;
(XADDRBASE + 12'h04) : reg_dout <= incnt;
(XADDRBASE + 12'h08) : reg_dout <= outdata;
(XADDRBASE + 12'h0c) : reg_dout <= outcnt;
default: reg_dout <= 32'h0;
endcase
end
end
*/
/* dummy signals */
assign dummy_signal_0 = outdata;
always @(*) begin dummy_signal_1 = outdata; end
endmodule
/*
//-------------------------------------------------------------------
// Register Definitions
//-------------------------------------------------------------------
`define reg_begin(_name) \
always @(posedge clk or negedge rstn) begin \
if (~rstn) \
_name <= 32'h0; \
else begin
`define reg_end(_name) \
end \
end
`define map_to_address(_name, _addr) \
if ((reg_addr==_addr) && reg_wr_en) \
_name <= reg_din;
`define delay_1c(_name, _var) \
always @(posedge clk or negedge ~rstn) \
if(~rstn) _name <= 1'b0; else _name <= _var;
`define delay_1c_cond(_name, _var, _cond) \
always @(posedge clk or negedge rstn) \
if(~rstn) _name <= 1'b0; else if (_cond) _name <= _var;
//-------------------------------------------------------------------
// Statistic Registers
//-------------------------------------------------------------------
`reg_begin(indata)
if (din_valid) indata <= din;
`reg_end(indata)
`reg_begin(incnt)
if (din_valid) incnt <= incnt + 32'h1;
`reg_end(incnt)
`reg_begin(outdata)
if (dout_valid) outdata <= dout;
`reg_end(outdata)
`reg_begin(outcnt)
if (dout_valid) outcnt <= outcnt + 32'h1;
`reg_end(outcnt)
*/
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 04-13-2006
// unsigned iterative divider, 1 and 2 bit per clock
// tick versions
////////////////////////////////////////////////////
// 1 bit per tick version
////////////////////////////////////////////////////
module divider (clk,rst,load,n,d,q,r,ready);
`include "log2.inc"
parameter WIDTH_N = 32;
parameter WIDTH_D = 32;
localparam LOG2_WIDTH_N = log2(WIDTH_N);
localparam MIN_ND = (WIDTH_N <WIDTH_D ? WIDTH_N : WIDTH_D);
input clk,rst;
input load; // load the numer and denominator
input [WIDTH_N-1:0] n; // numerator
input [WIDTH_D-1:0] d; // denominator
output [WIDTH_N-1:0] q; // quotient
output [WIDTH_D-1:0] r; // remainder
output ready; // Q and R are valid now.
reg [WIDTH_N + MIN_ND : 0] working;
reg [WIDTH_D-1 : 0] denom;
wire [WIDTH_N-1:0] lower_working = working [WIDTH_N-1:0];
wire [MIN_ND:0] upper_working = working [WIDTH_N + MIN_ND : WIDTH_N];
wire [WIDTH_D:0] sub_result = upper_working - denom;
wire sub_result_neg = sub_result[WIDTH_D];
reg [LOG2_WIDTH_N:0] cntr;
wire cntr_zero = ~|cntr;
assign ready = cntr_zero;
always @(posedge clk or posedge rst) begin
if (rst) begin
working <= 0;
denom <= 0;
cntr <= 0;
end
else begin
if (load) begin
working <= {{WIDTH_D{1'b0}},n,1'b0};
cntr <= WIDTH_N;
denom <= d;
end
else begin
if (!cntr_zero) begin
cntr <= cntr - 1;
working <= sub_result_neg ? {working[WIDTH_N+MIN_ND-1:0],1'b0} :
{sub_result[WIDTH_D-1:0],lower_working,1'b1};
end
end
end
end
assign q = lower_working;
assign r = upper_working >> 1;
endmodule
////////////////////////////////////////////////////
// 2 bits per tick (radix 4) version
////////////////////////////////////////////////////
module divider_rad4 (clk,rst,load,n,d,q,r,ready,almost_done);
`include "log2.inc"
parameter WIDTH_N = 32; // assumed to be EVEN
parameter WIDTH_D = 32;
localparam LOG2_WIDTH_N = log2(WIDTH_N);
localparam MIN_ND = (WIDTH_N <WIDTH_D ? WIDTH_N : WIDTH_D);
input clk,rst;
input load; // load the numer and denominator
input [WIDTH_N-1:0] n; // numerator
input [WIDTH_D-1:0] d; // denominator
output [WIDTH_N-1:0] q; // quotient
output [WIDTH_D-1:0] r; // remainder
output ready; // Q and R are valid now.
output almost_done;
reg [WIDTH_N + MIN_ND + 1 : 0] working;
reg [WIDTH_D-1 : 0] denom;
reg [WIDTH_D+1 : 0] triple_denom;
reg ready;
reg almost_done;
wire [WIDTH_N-1:0] lower_working = working [WIDTH_N-1:0];
wire [MIN_ND + 1:0] upper_working = working [WIDTH_N + MIN_ND + 1: WIDTH_N];
wire [WIDTH_D + 2:0] minus_zero = upper_working;
wire [WIDTH_D + 2:0] minus_one = upper_working - denom;
wire [WIDTH_D + 2:0] minus_two = upper_working - (denom << 1);
wire [WIDTH_D + 2:0] minus_three = upper_working - triple_denom;
wire [1:0] quot_bits = {!minus_two[WIDTH_D+2],
!minus_one[WIDTH_D+2] &
!(minus_three[WIDTH_D+2] ^ minus_two[WIDTH_D+2])};
wire [WIDTH_D + 2:0] appro_minus =
quot_bits[1] ? (quot_bits[0] ? minus_three : minus_two) :
(quot_bits[0] ? minus_one : minus_zero);
reg [LOG2_WIDTH_N:0] cntr;
wire cntr_zero = ~|cntr;
//assign ready = cntr_zero;
always @(posedge clk or posedge rst) begin
if (rst) begin
working <= 0;
denom <= 0;
triple_denom <= 0;
cntr <= 0;
ready <= 0;
almost_done <= 0;
end
else begin
if (load) begin
working <= {{MIN_ND{1'b0}},n,2'b0};
cntr <= (WIDTH_N >> 1);
denom <= d;
triple_denom <= (d + (d << 1));
end
else begin
if (!cntr_zero) begin
cntr <= cntr - 1;
working <= {appro_minus[WIDTH_D-1:0],lower_working,quot_bits};
end
ready <= (cntr == 1) ? 1'b1 : 1'b0;
almost_done <= (cntr == 4) ? 1'b1 : 1'b0;
end
end
end
assign q = lower_working;
assign r = upper_working >> 2;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 15 18:05:39 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/mono_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 188 at 2015.01.20.10:18:06
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/* Is not working :-( */
`include "DEF.v"
/*
module icachel2(address, data, read, out_address, out_data, out_read);
input [31:0] address;
input [127:0] out_data;
output [127:0] data;
output [31:0] out_address;
input read;
output out_read;
reg [127:0] icache [12'hFFF:0];
reg [31:0] tag [12'hFFF:0];
reg [127:0] r_data;
reg [31:0] r_out_address;
reg r_out_read;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_address = r_out_address;
always @(posedge read)
begin
r_out_read <= 0;
if(tag[address % 13'h1000] === address)
begin
r_data <= icache[address % 13'h1000];
end
else
begin
r_out_read <= 1;
r_out_address <= address;
#0.001
icache[address % 13'h1000] <= out_data;
tag[address % 13'h1000] <= address;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_address <= address / 64 * 64 + i;
#0.001
icache[out_address % 13'h1000] <= out_data;
tag[out_address % 13'h1000] <= out_address;
end
end
end
endmodule
*/ |
`timescale 1ns / 1ps
module SHDScheduler #(parameter DNA_DATA_WIDTH = 128, NUM_CLUSTERS = 8) (
input clk,
input rst,
//Receiver Interface
output dna_rd_en,
input[DNA_DATA_WIDTH - 1:0] dna_data_in,
input dna_valid_in,
//Cluster Interface
input shd_clk,
input[NUM_CLUSTERS - 1:0] shd_rd_en_in,
output[NUM_CLUSTERS - 1:0] shd_valid_out,
output[NUM_CLUSTERS*DNA_DATA_WIDTH - 1:0] shd_dna_data_out
);
reg[DNA_DATA_WIDTH - 1:0] dna_data_r;
reg dna_valid_r = 0;
wire accept_dna_data;
reg dna_issued;
//Register incoming dna data
always@(posedge clk) begin
if(rst) begin
dna_data_r <= 0;
dna_valid_r <= 0;
end
else begin
if(accept_dna_data) begin
dna_data_r <= dna_data_in;
dna_valid_r <= dna_valid_in;
end
end
end
assign accept_dna_data = !dna_valid_r || dna_issued;
assign dna_rd_en = accept_dna_data;
//SHD FIFOs
wire[NUM_CLUSTERS - 1:0] shd_fifo_full, shd_fifo_empty;
reg[NUM_CLUSTERS - 1:0] shd_fifo_wr_en;
genvar i;
generate
for (i=0; i < NUM_CLUSTERS; i=i+1) begin
shd_fifo i_shd_fifo (
.rst(rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(shd_clk), // input wire rd_clk
.din(dna_data_r), // input wire [255 : 0] din
.wr_en(shd_fifo_wr_en[i]), // input wire wr_en
.rd_en(shd_rd_en_in[i]), // input wire rd_en
.dout(shd_dna_data_out[i*DNA_DATA_WIDTH +: DNA_DATA_WIDTH]), // output wire [255 : 0] dout
.full(shd_fifo_full[i]), // output wire full
.empty(shd_fifo_empty[i]) // output wire empty
);
end
endgenerate
assign shd_valid_out = ~shd_fifo_empty;
// --- ARBITRATION LOGIC ---
//SHD PE iterator
parameter CLUSTER_BITS = $clog2(NUM_CLUSTERS);
reg[CLUSTER_BITS - 1:0] cluster_iterator = 0;
wire advance_cluster_it;
always@(posedge clk) begin
if(rst) begin
cluster_iterator <= 0;
end
else begin
if(advance_cluster_it) begin
cluster_iterator <= cluster_iterator + 1'b1;
end
end
end
assign advance_cluster_it = dna_issued; //We want to preserve the order. Looking for non-full FIFOs may break it
//Issue to current FIFO if not full
always@* begin
shd_fifo_wr_en = {NUM_CLUSTERS{1'b0}};
dna_issued = 1'b0;
if(dna_valid_r && ~shd_fifo_full[cluster_iterator]) begin
shd_fifo_wr_en[cluster_iterator] = 1'b1;
dna_issued = 1'b1;
end
end
// --- END - ARBITRATION LOGIC ---
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: snescmd_buf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module snescmd_buf (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL snescmd_buf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for struct of ent_a
//
// Generated
// by: wig
// on: Fri Jul 7 06:37:54 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ent_a.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module struct of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sc_sig_1_go,
p_mix_sc_sig_2_go,
p_mix_sc_sig_4_go
);
// Generated Module Outputs:
output p_mix_sc_sig_1_go;
output [31:0] p_mix_sc_sig_2_go;
output [31:0] p_mix_sc_sig_4_go;
// Generated Wires:
wire p_mix_sc_sig_1_go;
wire [31:0] p_mix_sc_sig_2_go;
wire [31:0] p_mix_sc_sig_4_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sc_sig_1; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_2; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_4; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sc_sig_1_go = sc_sig_1; // __I_O_BIT_PORT
assign p_mix_sc_sig_2_go = sc_sig_2; // __I_O_BUS_PORT
assign p_mix_sc_sig_4_go = sc_sig_4; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa ( // is i_padframe / hier inst_aa inst_aa inst_a
.p_mix_sc_sig_2_go(sc_sig_2), // reverse orderreverse order
// multiline comments
.p_mix_sc_sig_4_go(sc_sig_4) // reverse order
// multiline comments
// line 3
// line 4
// line 5
// line 6
// line 7
// line 8
// line 9
// line 10
// ...[cut]...
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab ( // is i_vgca / hier inst_ab inst_ab inst_a
.p_mix_sc_sig_1_go(sc_sig_1), // bad conection bits detected
.p_mix_sc_sig_2_go(sc_sig_2) // reverse orderreverse order
// multiline comments
);
// End of Generated Instance Port Map for inst_ab
endmodule
//
// End of Generated Module struct of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Scale
:Function
Scaling an image by your given scale.
Give the first output after 1 cycle while the frame input ready.
:Module
Main module
:Version
1.0
:Modified
2015-05-28
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module Scale(
clk,
rst_n,
scale_x,
scale_y,
in_enable,
frame_in_ready,
frame_in_data,
frame_enable,
frame_out_count_x,
frame_out_count_y,
out_ready,
out_data);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Delay for multiplier.
::range
Depend on your multilpliers' configurations, 1 - 14
*/
parameter mul_delay = 3;
/*
::description
Delay for FrameController.
::range
Depend on your FrameController
*/
parameter ram_RL = 7;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Scale for horizontal, must be reciprocal of real scale.
::range
Fixed number, 6bits.18bits
*/
input [23 : 0] scale_x;
/*
::description
Scale for vertical, must be reciprocal of real scale.
::range
Fixed number, 4bits.20bits
*/
input [23 : 0] scale_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Connect to out_ready in FrameController.
*/
input frame_in_ready;
/*
::description
Connect to out_data in FrameController.
*/
input[data_width - 1 : 0] frame_in_data;
/*
::description
Connect to in_enable in FrameController.
*/
output frame_enable;
/*
::description
Connect to in_count_x in FrameController.
*/
output[im_width_bits - 1 : 0] frame_out_count_x;
/*
::description
Connect to in_count_y in FrameController.
*/
output[im_width_bits - 1 : 0] frame_out_count_y;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
reg reg_out_ready;
reg in_range_h, in_range_v;
wire[18 : 0] mul_x_p, mul_y_p;
wire[17 : 0] mul_x_r, mul_y_r;
reg[3 : 0] con_mul_enable;
reg[data_width - 1 : 0] reg_out_data;
wire[im_width_bits - 1 : 0] count_x, count_y;
generate
if(work_mode == 0) begin
reg [im_width_bits - 1 : 0] reg_count_x, reg_count_y;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_count_x <= 0;
else if(reg_count_x == im_width - 1)
reg_count_x <= 0;
else
reg_count_x <= reg_count_x + 1;
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_count_y <= 0;
else if(reg_count_x == im_width - 1 && reg_count_y == im_height - 1)
reg_count_y <= 0;
else if(reg_count_x == im_width - 1)
reg_count_y <= reg_count_y + 1;
else
reg_count_y <= reg_count_y;
end
assign count_x = reg_count_x;
assign count_y = reg_count_y;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_mul_enable <= 0;
else if(con_mul_enable == mul_delay + 1)
con_mul_enable <= con_mul_enable;
else
con_mul_enable <= con_mul_enable + 1;
end
assign frame_enable = con_mul_enable == mul_delay + 1 ? 1 : 0;
end else begin
reg signed [im_width_bits : 0] reg_count_x, reg_count_y;
reg in_enable_last;
always @(posedge clk)
in_enable_last <= in_enable;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_count_x <= -1;
else if(~in_enable_last & in_enable) begin
if(reg_count_x == im_width - 1)
reg_count_x <= 0;
else
reg_count_x <= reg_count_x + 1;
end else
reg_count_x <= reg_count_x;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_count_y <= 0;
else if(~in_enable_last & in_enable) begin
if(reg_count_x == im_width - 1 && reg_count_y == im_height - 1)
reg_count_y <= 0;
else if(reg_count_x == im_width - 1)
reg_count_y <= reg_count_y + 1;
else
reg_count_y <= reg_count_y;
end else
reg_count_y <= reg_count_y;
end
assign count_x = reg_count_x[im_width_bits - 1 : 0];
assign count_y = reg_count_y[im_width_bits - 1 : 0];
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_mul_enable <= 0;
else if(con_mul_enable == mul_delay + 2)
con_mul_enable <= con_mul_enable;
else
con_mul_enable <= con_mul_enable + 1;
end
assign frame_enable = con_mul_enable == mul_delay + 2 ? 1 : 0;
end
/*
::description
Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
Multiplier12x24SCL MulX(.CLK(clk), .A({{12 - im_width_bits{1'b0}}, count_x[im_width_bits - 1 : 0]}), .B(scale_x), .SCLR(~rst_n), .P(mul_x_p));
/*
::description
Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.
You can configure the multiplier by yourself, then change the "mul_delay".
All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
*/
Multiplier12x24SCL MulY(.CLK(clk), .A({{12 - im_width_bits{1'b0}}, count_y[im_width_bits - 1 : 0]}), .B(scale_y), .SCLR(~rst_n), .P(mul_y_p));
/*
::description
For rounding fixed number.
*/
FixedRoundUnsigned #(19, 1) FRUX(clk, mul_x_p, mul_x_r);
/*
::description
For rounding fixed number.
*/
FixedRoundUnsigned #(19, 1) FRUY(clk, mul_y_p, mul_y_r);
assign frame_out_count_x = mul_x_r[im_width_bits - 1 : 0];
assign frame_out_count_y = mul_y_r[im_width_bits - 1 : 0];
if(work_mode == 0) begin
genvar i;
for (i = 0; i < ram_RL - 1; i = i + 1) begin : buffer
reg in_range_h, in_range_v;
if(i == 0) begin
always @(posedge clk) begin
in_range_h <= mul_x_r < im_width ? 1 : 0;
in_range_v <= mul_y_r < im_height ? 1 : 0;
end
end else begin
always @(posedge clk) begin
in_range_h <= buffer[i - 1].in_range_h;
in_range_v <= buffer[i - 1].in_range_v;
end
end
end
always @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
if(~rst_n || ~frame_in_ready) begin
reg_out_ready <= 0;
in_range_h <= 0;
in_range_v <= 0;
reg_out_data <= 0;
end else begin
reg_out_ready <= 1;
in_range_h <= buffer[ram_RL - 2].in_range_h;
in_range_v <= buffer[ram_RL - 2].in_range_v;
reg_out_data <= frame_in_data;
end
end
end else begin
reg tmp_h, tmp_v;
always @(posedge clk or negedge rst_n or negedge frame_in_ready) begin
if(~rst_n || ~frame_in_ready) begin
reg_out_ready <= 0;
reg_out_data <= 0;
in_range_h <= 0;
in_range_v <= 0;
end else begin
reg_out_ready <= 1;
reg_out_data <= frame_in_data;
in_range_h <= tmp_h;
in_range_v <= tmp_v;
end
end
always @(posedge clk) begin
tmp_h <= mul_x_r < im_width ? 1 : 0;
tmp_v <= mul_y_r < im_height ? 1 : 0;
end
end
assign out_ready = reg_out_ready;
assign out_data = out_ready & in_range_h & in_range_v ? reg_out_data : 0;
endgenerate
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_SYMBOL_V
`define SKY130_FD_SC_LS__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Load Generator
// File : de3d_tc_load_gen.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_load_gen
#(parameter BYTES = 4)
(
input de_clk,
input [20:0] tex_org, // LOD origins.
input [11:0] tptch, // LOD origins.
input [3:0] tc_op_store, // Upper left texel address
input [8:0] ul_store_x, // Upper left texel address
input [8:0] ul_store_y, // Upper left texel address
input [8:0] ll_store_x, // Lower left texel address
input [8:0] ll_store_y, // Lower left texel address
input [8:0] ur_store_x, // Upper right texel address
input [8:0] ur_store_y, // Upper right texel address
input [8:0] lr_store_x, // Lower right texel address
input [8:0] lr_store_y, // Lower right texel address
input [2:0] bpt, // bpt
input [1:0] req_count, // Memory Request Count.
output reg [31:0] tex_address // X out to memory controller.
);
reg [6:0] tex_x1_r; // X out to memory controller.
reg [6:0] tex_x2_r; // X out to memory controller.
reg [31:0] p_mult;
reg [31:0] int_add;
reg [1:0] req_current;
always @* begin
case (bpt) /* synopsys parallel_case */
3: // 8 bpt.
begin
tex_x1_r = {2'b0,ul_store_x[8:5], 1'b0};
tex_x2_r = {2'b0,lr_store_x[8:5], 1'b0};
end
5: // 32 bpt.
begin
tex_x1_r = {ul_store_x[8:3], 1'b0};
tex_x2_r = {lr_store_x[8:3], 1'b0};
end
default: // 16 bpt.
begin
tex_x1_r = {1'b0,ul_store_x[8:4], 1'b0};
tex_x2_r = {1'b0,lr_store_x[8:4], 1'b0};
end
endcase
end
always @* begin
casex({tc_op_store, req_count}) /* synopsys parallel_case */
// Missed one of four texels, load one cache line.
6'b1000_xx: req_current = 2'b00; // UL.
6'b0100_xx: req_current = 2'b01; // LL.
6'b0010_xx: req_current = 2'b10; // UR.
6'b0001_xx: req_current = 2'b11; // LR.
// Missed two of four texels, load two cache lines.
6'b0011_01: req_current = 2'b10; // UR.
6'b0011_00: req_current = 2'b11; // LR.
6'b0101_01: req_current = 2'b01; // LL.
6'b0101_00: req_current = 2'b11; // LR.
6'b0110_01: req_current = 2'b01; // LL.
6'b0110_00: req_current = 2'b10; // UR.
6'b1001_01: req_current = 2'b00; // UL.
6'b1001_00: req_current = 2'b11; // LR.
6'b1010_01: req_current = 2'b00; // UL.
6'b1010_00: req_current = 2'b10; // UR.
6'b1100_01: req_current = 2'b00; // UL.
6'b1100_00: req_current = 2'b01; // LL.
// Missed three of four texels, load three cache lines.
6'b0111_10: req_current = 2'b01; // LL.
6'b0111_01: req_current = 2'b10; // UR.
6'b0111_00: req_current = 2'b11; // LR.
6'b1011_10: req_current = 2'b00; // UL.
6'b1011_01: req_current = 2'b10; // UR.
6'b1011_00: req_current = 2'b11; // LR.
6'b1101_10: req_current = 2'b00; // UL.
6'b1101_01: req_current = 2'b01; // LL.
6'b1101_00: req_current = 2'b11; // LR.
6'b1110_10: req_current = 2'b00; // UL.
6'b1110_01: req_current = 2'b01; // LL.
6'b1110_00: req_current = 2'b10; // UR.
// Missed four of four texels, load four cache lines.
6'b1111_11: req_current = 2'b00; // UL.
6'b1111_10: req_current = 2'b01; // LL.
6'b1111_01: req_current = 2'b10; // UR.
6'b1111_00: req_current = 2'b11; // LR.
default: req_current = 2'b00; // UL.
endcase
end
always @ (posedge de_clk) begin
case(req_current)
// Pitch conversion
2'b00: begin
p_mult <= (ul_store_y * {{4{tptch[11]}}, tptch}); // x1, y1
`ifdef BYTE16 int_add <= (tex_org + {25'h0, tex_x1_r}); `endif
`ifdef BYTE8 int_add <= ({tex_org, 1'b0} + {{14{tex_x1_r[13]}}, tex_x1_r}); `endif
`ifdef BYTE4 int_add <= ({tex_org, 2'b0} + {{14{tex_x1_r[13]}}, tex_x1_r}); `endif
end
2'b01: begin
p_mult <= (ll_store_y * {{4{tptch[11]}}, tptch}); // x1, y2
`ifdef BYTE16 int_add <= (tex_org + {25'h0, tex_x1_r}); `endif
`ifdef BYTE8 int_add <= ({tex_org, 1'b0} + {{14{tex_x1_r[13]}}, tex_x1_r}); `endif
`ifdef BYTE4 int_add <= ({tex_org, 2'b0} + {{14{tex_x1_r[13]}}, tex_x1_r}); `endif
end
2'b10: begin
p_mult <= (ur_store_y * {{4{tptch[11]}}, tptch}); // x2, y1
`ifdef BYTE16 int_add <= (tex_org + {25'h0, tex_x2_r}); `endif
`ifdef BYTE8 int_add <= ({tex_org, 1'b0} + {{14{tex_x2_r[13]}}, tex_x2_r}); `endif
`ifdef BYTE4 int_add <= ({tex_org, 2'b0} + {{14{tex_x2_r[13]}}, tex_x2_r}); `endif
end
2'b11: begin
p_mult <= (lr_store_y * {{4{tptch[11]}}, tptch}); // x2, y2
`ifdef BYTE16 int_add <= (tex_org + {25'h0, tex_x2_r}); `endif
`ifdef BYTE8 int_add <= ({tex_org, 1'b0} + {{14{tex_x2_r[13]}}, tex_x2_r}); `endif
`ifdef BYTE4 int_add <= ({tex_org, 2'b0} + {{14{tex_x2_r[13]}}, tex_x2_r}); `endif
end
endcase
end
always @* begin
if (BYTES == 16) tex_address = p_mult + int_add;
else if (BYTES == 8) tex_address = {p_mult, 1'b0} + int_add;
else tex_address = {p_mult, 2'b0} + int_add;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.305800,HLS_SYN_LAT=102544,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=80,HLS_SYN_FF=43626,HLS_SYN_LUT=24925}" *)
module convolve_kernel (
ap_clk,
ap_rst_n,
bufw_Addr_A,
bufw_EN_A,
bufw_WEN_A,
bufw_Din_A,
bufw_Dout_A,
bufw_Clk_A,
bufw_Rst_A,
bufi_Addr_A,
bufi_EN_A,
bufi_WEN_A,
bufi_Din_A,
bufi_Dout_A,
bufi_Clk_A,
bufi_Rst_A,
bufo_Addr_A,
bufo_EN_A,
bufo_WEN_A,
bufo_Din_A,
bufo_Dout_A,
bufo_Clk_A,
bufo_Rst_A,
s_axi_control_AWVALID,
s_axi_control_AWREADY,
s_axi_control_AWADDR,
s_axi_control_WVALID,
s_axi_control_WREADY,
s_axi_control_WDATA,
s_axi_control_WSTRB,
s_axi_control_ARVALID,
s_axi_control_ARREADY,
s_axi_control_ARADDR,
s_axi_control_RVALID,
s_axi_control_RREADY,
s_axi_control_RDATA,
s_axi_control_RRESP,
s_axi_control_BVALID,
s_axi_control_BREADY,
s_axi_control_BRESP,
interrupt
);
parameter ap_ST_fsm_state1 = 18'd1;
parameter ap_ST_fsm_pp0_stage0 = 18'd2;
parameter ap_ST_fsm_pp0_stage1 = 18'd4;
parameter ap_ST_fsm_pp0_stage2 = 18'd8;
parameter ap_ST_fsm_pp0_stage3 = 18'd16;
parameter ap_ST_fsm_pp0_stage4 = 18'd32;
parameter ap_ST_fsm_pp0_stage5 = 18'd64;
parameter ap_ST_fsm_pp0_stage6 = 18'd128;
parameter ap_ST_fsm_pp0_stage7 = 18'd256;
parameter ap_ST_fsm_pp0_stage8 = 18'd512;
parameter ap_ST_fsm_pp0_stage9 = 18'd1024;
parameter ap_ST_fsm_pp0_stage10 = 18'd2048;
parameter ap_ST_fsm_pp0_stage11 = 18'd4096;
parameter ap_ST_fsm_pp0_stage12 = 18'd8192;
parameter ap_ST_fsm_pp0_stage13 = 18'd16384;
parameter ap_ST_fsm_pp0_stage14 = 18'd32768;
parameter ap_ST_fsm_pp0_stage15 = 18'd65536;
parameter ap_ST_fsm_state161 = 18'd131072;
parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_ADDR_WIDTH = 4;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
output [31:0] bufw_Addr_A;
output bufw_EN_A;
output [63:0] bufw_WEN_A;
output [511:0] bufw_Din_A;
input [511:0] bufw_Dout_A;
output bufw_Clk_A;
output bufw_Rst_A;
output [31:0] bufi_Addr_A;
output bufi_EN_A;
output [63:0] bufi_WEN_A;
output [511:0] bufi_Din_A;
input [511:0] bufi_Dout_A;
output bufi_Clk_A;
output bufi_Rst_A;
output [31:0] bufo_Addr_A;
output bufo_EN_A;
output [63:0] bufo_WEN_A;
output [511:0] bufo_Din_A;
input [511:0] bufo_Dout_A;
output bufo_Clk_A;
output bufo_Rst_A;
input s_axi_control_AWVALID;
output s_axi_control_AWREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_AWADDR;
input s_axi_control_WVALID;
output s_axi_control_WREADY;
input [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_WDATA;
input [C_S_AXI_CONTROL_WSTRB_WIDTH - 1:0] s_axi_control_WSTRB;
input s_axi_control_ARVALID;
output s_axi_control_ARREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_ARADDR;
output s_axi_control_RVALID;
input s_axi_control_RREADY;
output [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_RDATA;
output [1:0] s_axi_control_RRESP;
output s_axi_control_BVALID;
input s_axi_control_BREADY;
output [1:0] s_axi_control_BRESP;
output interrupt;
reg bufw_EN_A;
reg bufi_EN_A;
reg bufo_EN_A;
reg[63:0] bufo_WEN_A;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [17:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_ready;
reg [12:0] indvar_flatten1_reg_351;
reg [2:0] i_reg_362;
reg [11:0] indvar_flatten2_reg_374;
reg [2:0] j_reg_385;
reg [9:0] indvar_flatten_reg_397;
reg [4:0] row_b_reg_409;
reg [4:0] col_b_reg_421;
reg [31:0] reg_711;
wire ap_CS_fsm_pp0_stage5;
reg ap_enable_reg_pp0_iter0;
wire ap_block_state7_pp0_stage5_iter0;
wire ap_block_state23_pp0_stage5_iter1;
wire ap_block_state39_pp0_stage5_iter2;
wire ap_block_state55_pp0_stage5_iter3;
wire ap_block_state71_pp0_stage5_iter4;
wire ap_block_state87_pp0_stage5_iter5;
wire ap_block_state103_pp0_stage5_iter6;
wire ap_block_state119_pp0_stage5_iter7;
wire ap_block_state135_pp0_stage5_iter8;
wire ap_block_state151_pp0_stage5_iter9;
wire ap_block_pp0_stage5_flag00011001;
reg [0:0] exitcond_flatten2_reg_3675;
wire ap_CS_fsm_pp0_stage9;
wire ap_block_state11_pp0_stage9_iter0;
wire ap_block_state27_pp0_stage9_iter1;
wire ap_block_state43_pp0_stage9_iter2;
wire ap_block_state59_pp0_stage9_iter3;
wire ap_block_state75_pp0_stage9_iter4;
wire ap_block_state91_pp0_stage9_iter5;
wire ap_block_state107_pp0_stage9_iter6;
wire ap_block_state123_pp0_stage9_iter7;
wire ap_block_state139_pp0_stage9_iter8;
wire ap_block_state155_pp0_stage9_iter9;
wire ap_block_pp0_stage9_flag00011001;
wire ap_CS_fsm_pp0_stage13;
wire ap_block_state15_pp0_stage13_iter0;
wire ap_block_state31_pp0_stage13_iter1;
wire ap_block_state47_pp0_stage13_iter2;
wire ap_block_state63_pp0_stage13_iter3;
wire ap_block_state79_pp0_stage13_iter4;
wire ap_block_state95_pp0_stage13_iter5;
wire ap_block_state111_pp0_stage13_iter6;
wire ap_block_state127_pp0_stage13_iter7;
wire ap_block_state143_pp0_stage13_iter8;
wire ap_block_state159_pp0_stage13_iter9;
wire ap_block_pp0_stage13_flag00011001;
reg [31:0] reg_715;
reg [31:0] reg_719;
reg [31:0] reg_723;
reg [31:0] reg_727;
reg [31:0] reg_731;
reg [31:0] reg_735;
reg [31:0] reg_739;
reg [31:0] reg_743;
reg [31:0] reg_747;
reg [31:0] reg_751;
reg [31:0] reg_755;
reg [31:0] reg_759;
reg [31:0] reg_763;
reg [31:0] reg_767;
reg [31:0] reg_771;
wire ap_CS_fsm_pp0_stage6;
wire ap_block_state8_pp0_stage6_iter0;
wire ap_block_state24_pp0_stage6_iter1;
wire ap_block_state40_pp0_stage6_iter2;
wire ap_block_state56_pp0_stage6_iter3;
wire ap_block_state72_pp0_stage6_iter4;
wire ap_block_state88_pp0_stage6_iter5;
wire ap_block_state104_pp0_stage6_iter6;
wire ap_block_state120_pp0_stage6_iter7;
wire ap_block_state136_pp0_stage6_iter8;
wire ap_block_state152_pp0_stage6_iter9;
wire ap_block_pp0_stage6_flag00011001;
wire ap_CS_fsm_pp0_stage10;
wire ap_block_state12_pp0_stage10_iter0;
wire ap_block_state28_pp0_stage10_iter1;
wire ap_block_state44_pp0_stage10_iter2;
wire ap_block_state60_pp0_stage10_iter3;
wire ap_block_state76_pp0_stage10_iter4;
wire ap_block_state92_pp0_stage10_iter5;
wire ap_block_state108_pp0_stage10_iter6;
wire ap_block_state124_pp0_stage10_iter7;
wire ap_block_state140_pp0_stage10_iter8;
wire ap_block_state156_pp0_stage10_iter9;
wire ap_block_pp0_stage10_flag00011001;
wire ap_CS_fsm_pp0_stage14;
wire ap_block_state16_pp0_stage14_iter0;
wire ap_block_state32_pp0_stage14_iter1;
wire ap_block_state48_pp0_stage14_iter2;
wire ap_block_state64_pp0_stage14_iter3;
wire ap_block_state80_pp0_stage14_iter4;
wire ap_block_state96_pp0_stage14_iter5;
wire ap_block_state112_pp0_stage14_iter6;
wire ap_block_state128_pp0_stage14_iter7;
wire ap_block_state144_pp0_stage14_iter8;
wire ap_block_state160_pp0_stage14_iter9;
wire ap_block_pp0_stage14_flag00011001;
reg [31:0] reg_775;
reg [31:0] reg_779;
reg [31:0] reg_783;
reg [31:0] reg_787;
reg [31:0] reg_791;
reg [31:0] reg_795;
reg [31:0] reg_799;
reg [31:0] reg_803;
reg [31:0] reg_807;
reg [31:0] reg_811;
reg [31:0] reg_815;
reg [31:0] reg_819;
reg [31:0] reg_823;
reg [31:0] reg_827;
reg [31:0] reg_831;
wire ap_CS_fsm_pp0_stage7;
wire ap_block_state9_pp0_stage7_iter0;
wire ap_block_state25_pp0_stage7_iter1;
wire ap_block_state41_pp0_stage7_iter2;
wire ap_block_state57_pp0_stage7_iter3;
wire ap_block_state73_pp0_stage7_iter4;
wire ap_block_state89_pp0_stage7_iter5;
wire ap_block_state105_pp0_stage7_iter6;
wire ap_block_state121_pp0_stage7_iter7;
wire ap_block_state137_pp0_stage7_iter8;
wire ap_block_state153_pp0_stage7_iter9;
wire ap_block_pp0_stage7_flag00011001;
wire ap_CS_fsm_pp0_stage11;
wire ap_block_state13_pp0_stage11_iter0;
wire ap_block_state29_pp0_stage11_iter1;
wire ap_block_state45_pp0_stage11_iter2;
wire ap_block_state61_pp0_stage11_iter3;
wire ap_block_state77_pp0_stage11_iter4;
wire ap_block_state93_pp0_stage11_iter5;
wire ap_block_state109_pp0_stage11_iter6;
wire ap_block_state125_pp0_stage11_iter7;
wire ap_block_state141_pp0_stage11_iter8;
wire ap_block_state157_pp0_stage11_iter9;
wire ap_block_pp0_stage11_flag00011001;
wire ap_CS_fsm_pp0_stage15;
wire ap_block_state17_pp0_stage15_iter0;
wire ap_block_state33_pp0_stage15_iter1;
wire ap_block_state49_pp0_stage15_iter2;
wire ap_block_state65_pp0_stage15_iter3;
wire ap_block_state81_pp0_stage15_iter4;
wire ap_block_state97_pp0_stage15_iter5;
wire ap_block_state113_pp0_stage15_iter6;
wire ap_block_state129_pp0_stage15_iter7;
wire ap_block_state145_pp0_stage15_iter8;
wire ap_block_pp0_stage15_flag00011001;
reg [31:0] reg_835;
reg [31:0] reg_839;
reg [31:0] reg_843;
reg [31:0] reg_847;
reg [31:0] reg_851;
reg [31:0] reg_855;
reg [31:0] reg_859;
reg [31:0] reg_863;
reg [31:0] reg_867;
reg [31:0] reg_871;
reg [31:0] reg_875;
reg [31:0] reg_879;
reg [31:0] reg_883;
reg [31:0] reg_887;
reg [31:0] reg_891;
wire ap_CS_fsm_pp0_stage8;
wire ap_block_state10_pp0_stage8_iter0;
wire ap_block_state26_pp0_stage8_iter1;
wire ap_block_state42_pp0_stage8_iter2;
wire ap_block_state58_pp0_stage8_iter3;
wire ap_block_state74_pp0_stage8_iter4;
wire ap_block_state90_pp0_stage8_iter5;
wire ap_block_state106_pp0_stage8_iter6;
wire ap_block_state122_pp0_stage8_iter7;
wire ap_block_state138_pp0_stage8_iter8;
wire ap_block_state154_pp0_stage8_iter9;
wire ap_block_pp0_stage8_flag00011001;
wire ap_CS_fsm_pp0_stage12;
wire ap_block_state14_pp0_stage12_iter0;
wire ap_block_state30_pp0_stage12_iter1;
wire ap_block_state46_pp0_stage12_iter2;
wire ap_block_state62_pp0_stage12_iter3;
wire ap_block_state78_pp0_stage12_iter4;
wire ap_block_state94_pp0_stage12_iter5;
wire ap_block_state110_pp0_stage12_iter6;
wire ap_block_state126_pp0_stage12_iter7;
wire ap_block_state142_pp0_stage12_iter8;
wire ap_block_state158_pp0_stage12_iter9;
wire ap_block_pp0_stage12_flag00011001;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_state2_pp0_stage0_iter0;
wire ap_block_state18_pp0_stage0_iter1;
wire ap_block_state34_pp0_stage0_iter2;
wire ap_block_state50_pp0_stage0_iter3;
wire ap_block_state66_pp0_stage0_iter4;
wire ap_block_state82_pp0_stage0_iter5;
wire ap_block_state98_pp0_stage0_iter6;
wire ap_block_state114_pp0_stage0_iter7;
wire ap_block_state130_pp0_stage0_iter8;
wire ap_block_state146_pp0_stage0_iter9;
wire ap_block_pp0_stage0_flag00011001;
reg [31:0] reg_895;
reg [31:0] reg_899;
reg [31:0] reg_903;
reg [31:0] reg_907;
reg [31:0] reg_911;
reg [31:0] reg_915;
reg [31:0] reg_919;
reg [31:0] reg_923;
reg [31:0] reg_927;
reg [31:0] reg_931;
reg [31:0] reg_935;
reg [31:0] reg_939;
reg [31:0] reg_943;
reg [31:0] reg_947;
wire [31:0] grp_fu_433_p2;
reg [31:0] reg_951;
reg [0:0] ap_reg_pp0_iter1_exitcond_flatten2_reg_3675;
reg ap_enable_reg_pp0_iter9;
reg [0:0] ap_reg_pp0_iter9_exitcond_flatten2_reg_3675;
wire [31:0] grp_fu_437_p2;
reg [31:0] reg_956;
wire [31:0] grp_fu_441_p2;
reg [31:0] reg_961;
wire [31:0] grp_fu_445_p2;
reg [31:0] reg_966;
wire [31:0] grp_fu_449_p2;
reg [31:0] reg_971;
wire [31:0] grp_fu_453_p2;
reg [31:0] reg_976;
wire [31:0] grp_fu_457_p2;
reg [31:0] reg_981;
wire [31:0] grp_fu_461_p2;
reg [31:0] reg_986;
wire [31:0] grp_fu_465_p2;
reg [31:0] reg_991;
wire [31:0] grp_fu_469_p2;
reg [31:0] reg_996;
wire [31:0] grp_fu_473_p2;
reg [31:0] reg_1001;
wire [31:0] grp_fu_477_p2;
reg [31:0] reg_1006;
wire [31:0] grp_fu_481_p2;
reg [31:0] reg_1011;
wire [31:0] grp_fu_485_p2;
reg [31:0] reg_1016;
wire [31:0] grp_fu_489_p2;
reg [31:0] reg_1021;
wire [31:0] grp_fu_493_p2;
reg [31:0] reg_1026;
wire [5:0] tmp_8_fu_1045_p2;
reg [5:0] tmp_8_reg_3670;
wire [0:0] exitcond_flatten2_fu_1051_p2;
reg [0:0] ap_reg_pp0_iter2_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter3_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter4_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter5_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter6_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter7_exitcond_flatten2_reg_3675;
reg [0:0] ap_reg_pp0_iter8_exitcond_flatten2_reg_3675;
wire [12:0] indvar_flatten_next2_fu_1057_p2;
reg [12:0] indvar_flatten_next2_reg_3679;
wire [0:0] exitcond_flatten_fu_1063_p2;
reg [0:0] exitcond_flatten_reg_3684;
wire [0:0] tmp_35_fu_1069_p2;
reg [0:0] tmp_35_reg_3696;
wire [0:0] exitcond_flatten1_fu_1075_p2;
reg [0:0] exitcond_flatten1_reg_3701;
wire [11:0] indvar_flatten40_op_fu_1081_p2;
reg [11:0] indvar_flatten40_op_reg_3707;
wire [2:0] i_1_fu_1087_p2;
reg [2:0] i_1_reg_3712;
wire ap_CS_fsm_pp0_stage1;
wire ap_block_state3_pp0_stage1_iter0;
wire ap_block_state19_pp0_stage1_iter1;
wire ap_block_state35_pp0_stage1_iter2;
wire ap_block_state51_pp0_stage1_iter3;
wire ap_block_state67_pp0_stage1_iter4;
wire ap_block_state83_pp0_stage1_iter5;
wire ap_block_state99_pp0_stage1_iter6;
wire ap_block_state115_pp0_stage1_iter7;
wire ap_block_state131_pp0_stage1_iter8;
wire ap_block_state147_pp0_stage1_iter9;
wire ap_block_pp0_stage1_flag00011001;
wire [2:0] j_mid_fu_1093_p3;
reg [2:0] j_mid_reg_3717;
wire [2:0] tmp_1_mid2_v_fu_1100_p3;
reg [2:0] tmp_1_mid2_v_reg_3722;
wire [0:0] exitcond_flatten_mid_fu_1117_p2;
reg [0:0] exitcond_flatten_mid_reg_3731;
wire [2:0] j_1_fu_1122_p2;
reg [2:0] j_1_reg_3739;
wire [0:0] tmp_9_mid1_fu_1138_p2;
reg [0:0] tmp_9_mid1_reg_3744;
wire [9:0] indvar_flatten_op_fu_1144_p2;
reg [9:0] indvar_flatten_op_reg_3752;
wire [11:0] indvar_flatten_next1_fu_1150_p3;
reg [11:0] indvar_flatten_next1_reg_3757;
wire [5:0] tmp_1_mid2_cast_fu_1156_p1;
reg [5:0] tmp_1_mid2_cast_reg_3762;
wire ap_CS_fsm_pp0_stage2;
wire ap_block_state4_pp0_stage2_iter0;
wire ap_block_state20_pp0_stage2_iter1;
wire ap_block_state36_pp0_stage2_iter2;
wire ap_block_state52_pp0_stage2_iter3;
wire ap_block_state68_pp0_stage2_iter4;
wire ap_block_state84_pp0_stage2_iter5;
wire ap_block_state100_pp0_stage2_iter6;
wire ap_block_state116_pp0_stage2_iter7;
wire ap_block_state132_pp0_stage2_iter8;
wire ap_block_state148_pp0_stage2_iter9;
wire ap_block_pp0_stage2_flag00011001;
wire [5:0] tmp_2_fu_1170_p2;
reg [5:0] tmp_2_reg_3767;
wire [4:0] row_b_mid_fu_1211_p3;
reg [4:0] row_b_mid_reg_3776;
wire [2:0] tmp_4_mid2_fu_1219_p3;
reg [2:0] tmp_4_mid2_reg_3783;
wire [9:0] tmp_75_fu_1228_p2;
reg [9:0] tmp_75_reg_3792;
wire [5:0] tmp_8_cast_mid5_fu_1234_p3;
reg [5:0] tmp_8_cast_mid5_reg_3797;
wire [4:0] col_b_mid2_fu_1250_p3;
reg [4:0] col_b_mid2_reg_3802;
wire [9:0] indvar_flatten_next_fu_1258_p3;
reg [9:0] indvar_flatten_next_reg_3809;
wire [5:0] tmp_5_fu_1265_p2;
reg [5:0] tmp_5_reg_3814;
wire ap_CS_fsm_pp0_stage3;
wire ap_block_state5_pp0_stage3_iter0;
wire ap_block_state21_pp0_stage3_iter1;
wire ap_block_state37_pp0_stage3_iter2;
wire ap_block_state53_pp0_stage3_iter3;
wire ap_block_state69_pp0_stage3_iter4;
wire ap_block_state85_pp0_stage3_iter5;
wire ap_block_state101_pp0_stage3_iter6;
wire ap_block_state117_pp0_stage3_iter7;
wire ap_block_state133_pp0_stage3_iter8;
wire ap_block_state149_pp0_stage3_iter9;
wire ap_block_pp0_stage3_flag00011001;
wire [5:0] tmp_4_mid2_cast_fu_1270_p1;
reg [5:0] tmp_4_mid2_cast_reg_3819;
wire [5:0] tmp_43_fu_1273_p2;
reg [5:0] tmp_43_reg_3824;
wire [4:0] row_b_1_fu_1282_p2;
reg [4:0] row_b_1_reg_3834;
wire [6:0] tmp_4_mid2_cast4_fu_1290_p1;
reg [6:0] tmp_4_mid2_cast4_reg_3841;
wire ap_CS_fsm_pp0_stage4;
wire ap_block_state6_pp0_stage4_iter0;
wire ap_block_state22_pp0_stage4_iter1;
wire ap_block_state38_pp0_stage4_iter2;
wire ap_block_state54_pp0_stage4_iter3;
wire ap_block_state70_pp0_stage4_iter4;
wire ap_block_state86_pp0_stage4_iter5;
wire ap_block_state102_pp0_stage4_iter6;
wire ap_block_state118_pp0_stage4_iter7;
wire ap_block_state134_pp0_stage4_iter8;
wire ap_block_state150_pp0_stage4_iter9;
wire ap_block_pp0_stage4_flag00011001;
wire [6:0] tmp_47_fu_1297_p2;
reg [6:0] tmp_47_reg_3852;
wire [5:0] tmp_8_mid1_fu_1329_p2;
reg [5:0] tmp_8_mid1_reg_3857;
wire [4:0] row_b_mid2_fu_1334_p3;
reg [4:0] row_b_mid2_reg_3862;
reg [7:0] bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter1_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter8_bufo_addr_reg_3867;
reg [7:0] ap_reg_pp0_iter9_bufo_addr_reg_3867;
wire [5:0] tmp_3_fu_1362_p2;
reg [5:0] tmp_3_reg_3872;
wire [31:0] tmp_635_fu_1367_p1;
reg [31:0] tmp_635_reg_3877;
reg [31:0] tmp_98_reg_3882;
reg [31:0] tmp_134_reg_3887;
reg [31:0] tmp_169_reg_3892;
reg [31:0] tmp_204_reg_3897;
reg [31:0] tmp_239_reg_3902;
reg [31:0] tmp_274_reg_3907;
reg [31:0] tmp_309_reg_3912;
reg [31:0] tmp_344_reg_3917;
reg [31:0] tmp_379_reg_3922;
reg [31:0] tmp_414_reg_3927;
reg [31:0] tmp_449_reg_3932;
reg [31:0] tmp_484_reg_3937;
reg [31:0] tmp_519_reg_3942;
reg [31:0] tmp_554_reg_3947;
reg [31:0] tmp_589_reg_3952;
wire [4:0] col_b_1_fu_1371_p2;
reg [4:0] col_b_1_reg_3957;
wire [6:0] tmp_51_fu_1395_p2;
reg [6:0] tmp_51_reg_3967;
wire [6:0] tmp_55_fu_1400_p2;
reg [6:0] tmp_55_reg_3972;
wire [5:0] tmp_8_cast_mid2_fu_1405_p3;
reg [5:0] tmp_8_cast_mid2_reg_3977;
wire [31:0] tmp_625_fu_1410_p1;
reg [31:0] tmp_625_reg_3983;
wire [11:0] tmp_624_fu_1449_p2;
reg [11:0] tmp_624_reg_3993;
wire [31:0] tmp_627_fu_1455_p1;
reg [31:0] tmp_627_reg_3998;
wire [31:0] tmp_628_fu_1459_p1;
reg [31:0] tmp_628_reg_4003;
reg [31:0] tmp_82_reg_4008;
reg [31:0] tmp_118_reg_4013;
reg [31:0] tmp_153_reg_4018;
reg [31:0] tmp_188_reg_4023;
reg [31:0] tmp_223_reg_4028;
reg [31:0] tmp_258_reg_4033;
reg [31:0] tmp_293_reg_4038;
reg [31:0] tmp_328_reg_4043;
reg [31:0] tmp_363_reg_4048;
reg [31:0] tmp_398_reg_4053;
reg [31:0] tmp_433_reg_4058;
reg [31:0] tmp_468_reg_4063;
reg [31:0] tmp_503_reg_4068;
reg [31:0] tmp_538_reg_4073;
reg [31:0] tmp_573_reg_4078;
wire [7:0] tmp_2_cast2_fu_1613_p1;
reg [7:0] tmp_2_cast2_reg_4083;
wire [7:0] tmp_4_mid2_cast3_fu_1622_p1;
reg [7:0] tmp_4_mid2_cast3_reg_4090;
wire [7:0] tmp_59_fu_1629_p2;
reg [7:0] tmp_59_reg_4102;
wire [31:0] tmp_629_fu_1639_p1;
reg [31:0] tmp_629_reg_4112;
wire [7:0] tmp_63_fu_1652_p2;
reg [7:0] tmp_63_reg_4122;
wire [31:0] tmp_626_fu_1657_p1;
reg [31:0] tmp_626_reg_4127;
reg [31:0] tmp_21_reg_4132;
reg [31:0] tmp_25_reg_4137;
wire [31:0] tmp_630_fu_1681_p1;
reg [31:0] tmp_630_reg_4142;
reg [31:0] tmp_29_reg_4147;
reg [31:0] tmp_33_reg_4152;
reg [31:0] tmp_37_reg_4157;
reg [31:0] tmp_41_reg_4162;
reg [31:0] tmp_45_reg_4167;
reg [31:0] tmp_49_reg_4172;
reg [31:0] tmp_53_reg_4177;
reg [31:0] tmp_57_reg_4182;
reg [31:0] tmp_61_reg_4187;
reg [31:0] tmp_65_reg_4192;
reg [31:0] tmp_69_reg_4197;
reg [31:0] tmp_73_reg_4202;
reg [31:0] tmp_77_reg_4207;
wire [7:0] tmp_67_fu_1829_p2;
reg [7:0] tmp_67_reg_4217;
wire [7:0] tmp_71_fu_1834_p2;
reg [7:0] tmp_71_reg_4222;
wire [31:0] tmp_14_fu_1839_p1;
wire [31:0] tmp_16_fu_1843_p1;
wire [31:0] tmp_631_fu_1862_p1;
reg [31:0] tmp_631_reg_4252;
wire [31:0] tmp_81_fu_1866_p1;
wire [31:0] tmp_117_fu_1871_p1;
wire [31:0] tmp_152_fu_1876_p1;
wire [31:0] tmp_187_fu_1881_p1;
wire [31:0] tmp_222_fu_1886_p1;
wire [31:0] tmp_257_fu_1891_p1;
wire [31:0] tmp_292_fu_1896_p1;
wire [31:0] tmp_327_fu_1901_p1;
wire [31:0] tmp_362_fu_1906_p1;
wire [31:0] tmp_397_fu_1911_p1;
wire [31:0] tmp_432_fu_1916_p1;
wire [31:0] tmp_467_fu_1921_p1;
wire [31:0] tmp_502_fu_1926_p1;
wire [31:0] tmp_537_fu_1931_p1;
wire [31:0] tmp_572_fu_1936_p1;
wire [31:0] tmp_20_fu_1945_p1;
wire [31:0] tmp_22_fu_1949_p1;
wire [31:0] tmp_632_fu_1968_p1;
reg [31:0] tmp_632_reg_4362;
wire [31:0] tmp_85_fu_1972_p1;
wire [31:0] tmp_121_fu_1977_p1;
wire [31:0] tmp_156_fu_1982_p1;
wire [31:0] tmp_191_fu_1987_p1;
wire [31:0] tmp_226_fu_1992_p1;
wire [31:0] tmp_261_fu_1997_p1;
wire [31:0] tmp_296_fu_2002_p1;
wire [31:0] tmp_331_fu_2007_p1;
wire [31:0] tmp_366_fu_2012_p1;
wire [31:0] tmp_401_fu_2017_p1;
wire [31:0] tmp_436_fu_2022_p1;
wire [31:0] tmp_471_fu_2027_p1;
wire [31:0] tmp_506_fu_2032_p1;
wire [31:0] tmp_541_fu_2037_p1;
wire [31:0] tmp_576_fu_2042_p1;
wire [8:0] tmp_2_cast1_fu_2047_p1;
reg [8:0] tmp_2_cast1_reg_4442;
wire [8:0] tmp_4_mid2_cast1_fu_2056_p1;
reg [8:0] tmp_4_mid2_cast1_reg_4452;
wire [8:0] tmp_608_fu_2063_p2;
reg [8:0] tmp_608_reg_4467;
wire [31:0] tmp_24_fu_2069_p1;
wire [31:0] tmp_26_fu_2073_p1;
wire [31:0] tmp_633_fu_2092_p1;
reg [31:0] tmp_633_reg_4497;
wire [31:0] tmp_87_fu_2096_p1;
wire [31:0] tmp_123_fu_2101_p1;
wire [31:0] tmp_158_fu_2106_p1;
wire [31:0] tmp_193_fu_2111_p1;
wire [31:0] tmp_228_fu_2116_p1;
wire [31:0] tmp_263_fu_2121_p1;
wire [31:0] tmp_298_fu_2126_p1;
wire [31:0] tmp_333_fu_2131_p1;
wire [31:0] tmp_368_fu_2136_p1;
wire [31:0] tmp_403_fu_2141_p1;
wire [31:0] tmp_438_fu_2146_p1;
wire [31:0] tmp_473_fu_2151_p1;
wire [31:0] tmp_508_fu_2156_p1;
wire [31:0] tmp_543_fu_2161_p1;
wire [31:0] tmp_578_fu_2166_p1;
wire [8:0] tmp_609_fu_2180_p2;
reg [8:0] tmp_609_reg_4582;
wire [31:0] tmp_28_fu_2185_p1;
wire [31:0] tmp_30_fu_2189_p1;
wire [31:0] tmp_634_fu_2208_p1;
reg [31:0] tmp_634_reg_4612;
wire [31:0] tmp_89_fu_2212_p1;
wire [31:0] tmp_125_fu_2217_p1;
wire [31:0] tmp_160_fu_2222_p1;
wire [31:0] tmp_195_fu_2227_p1;
wire [31:0] tmp_230_fu_2232_p1;
wire [31:0] tmp_265_fu_2237_p1;
wire [31:0] tmp_300_fu_2242_p1;
wire [31:0] tmp_335_fu_2247_p1;
wire [31:0] tmp_370_fu_2252_p1;
wire [31:0] tmp_405_fu_2257_p1;
wire [31:0] tmp_440_fu_2262_p1;
wire [31:0] tmp_475_fu_2267_p1;
wire [31:0] tmp_510_fu_2272_p1;
wire [31:0] tmp_545_fu_2277_p1;
wire [31:0] tmp_580_fu_2282_p1;
wire [8:0] tmp_610_fu_2296_p2;
reg [8:0] tmp_610_reg_4697;
wire [31:0] grp_fu_497_p2;
reg [31:0] tmp_116_reg_4702;
wire [31:0] tmp_32_fu_2301_p1;
wire [31:0] tmp_34_fu_2305_p1;
wire [31:0] tmp_636_fu_2324_p1;
reg [31:0] tmp_636_reg_4732;
wire [31:0] grp_fu_501_p2;
reg [31:0] tmp_11_1_reg_4737;
wire [31:0] tmp_91_fu_2328_p1;
wire [31:0] grp_fu_505_p2;
reg [31:0] tmp_11_2_reg_4747;
wire [31:0] tmp_127_fu_2333_p1;
wire [31:0] grp_fu_509_p2;
reg [31:0] tmp_11_3_reg_4757;
wire [31:0] tmp_162_fu_2338_p1;
wire [31:0] grp_fu_513_p2;
reg [31:0] tmp_11_4_reg_4767;
wire [31:0] tmp_197_fu_2343_p1;
wire [31:0] grp_fu_517_p2;
reg [31:0] tmp_11_5_reg_4777;
wire [31:0] tmp_232_fu_2348_p1;
wire [31:0] grp_fu_521_p2;
reg [31:0] tmp_11_6_reg_4787;
wire [31:0] tmp_267_fu_2353_p1;
wire [31:0] grp_fu_525_p2;
reg [31:0] tmp_11_7_reg_4797;
wire [31:0] tmp_302_fu_2358_p1;
wire [31:0] grp_fu_529_p2;
reg [31:0] tmp_11_8_reg_4807;
wire [31:0] tmp_337_fu_2363_p1;
wire [31:0] grp_fu_533_p2;
reg [31:0] tmp_11_9_reg_4817;
wire [31:0] tmp_372_fu_2368_p1;
wire [31:0] grp_fu_537_p2;
reg [31:0] tmp_11_s_reg_4827;
wire [31:0] tmp_407_fu_2373_p1;
wire [31:0] grp_fu_541_p2;
reg [31:0] tmp_11_10_reg_4837;
wire [31:0] tmp_442_fu_2378_p1;
wire [31:0] grp_fu_545_p2;
reg [31:0] tmp_11_11_reg_4847;
wire [31:0] tmp_477_fu_2383_p1;
wire [31:0] grp_fu_549_p2;
reg [31:0] tmp_11_12_reg_4857;
wire [31:0] tmp_512_fu_2388_p1;
wire [31:0] grp_fu_553_p2;
reg [31:0] tmp_11_13_reg_4867;
wire [31:0] tmp_547_fu_2393_p1;
wire [31:0] grp_fu_557_p2;
reg [31:0] tmp_11_14_reg_4877;
wire [31:0] tmp_582_fu_2398_p1;
wire [8:0] tmp_611_fu_2412_p2;
reg [8:0] tmp_611_reg_4892;
wire [31:0] tmp_18_fu_2417_p1;
reg [31:0] tmp_11_0_1_reg_4902;
wire [31:0] tmp_36_fu_2421_p1;
wire [31:0] tmp_38_fu_2425_p1;
wire [31:0] tmp_637_fu_2444_p1;
reg [31:0] tmp_637_reg_4932;
wire [31:0] tmp_83_fu_2448_p1;
reg [31:0] tmp_11_1_1_reg_4942;
wire [31:0] tmp_93_fu_2452_p1;
wire [31:0] tmp_119_fu_2457_p1;
reg [31:0] tmp_11_2_1_reg_4957;
wire [31:0] tmp_129_fu_2461_p1;
wire [31:0] tmp_154_fu_2466_p1;
reg [31:0] tmp_11_3_1_reg_4972;
wire [31:0] tmp_164_fu_2470_p1;
wire [31:0] tmp_189_fu_2475_p1;
reg [31:0] tmp_11_4_1_reg_4987;
wire [31:0] tmp_199_fu_2479_p1;
wire [31:0] tmp_224_fu_2484_p1;
reg [31:0] tmp_11_5_1_reg_5002;
wire [31:0] tmp_234_fu_2488_p1;
wire [31:0] tmp_259_fu_2493_p1;
reg [31:0] tmp_11_6_1_reg_5017;
wire [31:0] tmp_269_fu_2497_p1;
wire [31:0] tmp_294_fu_2502_p1;
reg [31:0] tmp_11_7_1_reg_5032;
wire [31:0] tmp_304_fu_2506_p1;
wire [31:0] tmp_329_fu_2511_p1;
reg [31:0] tmp_11_8_1_reg_5047;
wire [31:0] tmp_339_fu_2515_p1;
wire [31:0] tmp_364_fu_2520_p1;
reg [31:0] tmp_11_9_1_reg_5062;
wire [31:0] tmp_374_fu_2524_p1;
wire [31:0] tmp_399_fu_2529_p1;
reg [31:0] tmp_11_10_1_reg_5077;
wire [31:0] tmp_409_fu_2533_p1;
wire [31:0] tmp_434_fu_2538_p1;
reg [31:0] tmp_11_11_1_reg_5092;
wire [31:0] tmp_444_fu_2542_p1;
wire [31:0] tmp_469_fu_2547_p1;
reg [31:0] tmp_11_12_1_reg_5107;
wire [31:0] tmp_479_fu_2551_p1;
wire [31:0] tmp_504_fu_2556_p1;
reg [31:0] tmp_11_13_1_reg_5122;
wire [31:0] tmp_514_fu_2560_p1;
wire [31:0] tmp_539_fu_2565_p1;
reg [31:0] tmp_11_14_1_reg_5137;
wire [31:0] tmp_549_fu_2569_p1;
wire [31:0] tmp_574_fu_2574_p1;
reg [31:0] tmp_11_15_1_reg_5152;
wire [31:0] tmp_584_fu_2578_p1;
wire [8:0] tmp_612_fu_2592_p2;
reg [8:0] tmp_612_reg_5167;
reg [31:0] tmp_11_0_2_reg_5172;
reg [31:0] ap_reg_pp0_iter1_tmp_11_0_2_reg_5172;
wire [31:0] tmp_40_fu_2597_p1;
wire [31:0] tmp_42_fu_2601_p1;
wire [31:0] tmp_638_fu_2620_p1;
reg [31:0] tmp_638_reg_5202;
reg [31:0] tmp_11_1_2_reg_5207;
reg [31:0] ap_reg_pp0_iter1_tmp_11_1_2_reg_5207;
wire [31:0] tmp_95_fu_2624_p1;
reg [31:0] tmp_11_2_2_reg_5217;
reg [31:0] ap_reg_pp0_iter1_tmp_11_2_2_reg_5217;
wire [31:0] tmp_131_fu_2629_p1;
reg [31:0] tmp_11_3_2_reg_5227;
reg [31:0] ap_reg_pp0_iter1_tmp_11_3_2_reg_5227;
wire [31:0] tmp_166_fu_2634_p1;
reg [31:0] tmp_11_4_2_reg_5237;
reg [31:0] ap_reg_pp0_iter1_tmp_11_4_2_reg_5237;
wire [31:0] tmp_201_fu_2639_p1;
reg [31:0] tmp_11_5_2_reg_5247;
reg [31:0] ap_reg_pp0_iter1_tmp_11_5_2_reg_5247;
wire [31:0] tmp_236_fu_2644_p1;
reg [31:0] tmp_11_6_2_reg_5257;
reg [31:0] ap_reg_pp0_iter1_tmp_11_6_2_reg_5257;
wire [31:0] tmp_271_fu_2649_p1;
reg [31:0] tmp_11_7_2_reg_5267;
reg [31:0] ap_reg_pp0_iter1_tmp_11_7_2_reg_5267;
wire [31:0] tmp_306_fu_2654_p1;
reg [31:0] tmp_11_8_2_reg_5277;
reg [31:0] ap_reg_pp0_iter1_tmp_11_8_2_reg_5277;
wire [31:0] tmp_341_fu_2659_p1;
reg [31:0] tmp_11_9_2_reg_5287;
reg [31:0] ap_reg_pp0_iter1_tmp_11_9_2_reg_5287;
wire [31:0] tmp_376_fu_2664_p1;
reg [31:0] tmp_11_10_2_reg_5297;
reg [31:0] ap_reg_pp0_iter1_tmp_11_10_2_reg_5297;
wire [31:0] tmp_411_fu_2669_p1;
reg [31:0] tmp_11_11_2_reg_5307;
reg [31:0] ap_reg_pp0_iter1_tmp_11_11_2_reg_5307;
wire [31:0] tmp_446_fu_2674_p1;
reg [31:0] tmp_11_12_2_reg_5317;
reg [31:0] ap_reg_pp0_iter1_tmp_11_12_2_reg_5317;
wire [31:0] tmp_481_fu_2679_p1;
reg [31:0] tmp_11_13_2_reg_5327;
reg [31:0] ap_reg_pp0_iter1_tmp_11_13_2_reg_5327;
wire [31:0] tmp_516_fu_2684_p1;
reg [31:0] tmp_11_14_2_reg_5337;
reg [31:0] ap_reg_pp0_iter1_tmp_11_14_2_reg_5337;
wire [31:0] tmp_551_fu_2689_p1;
reg [31:0] tmp_11_15_2_reg_5347;
reg [31:0] ap_reg_pp0_iter1_tmp_11_15_2_reg_5347;
wire [31:0] tmp_586_fu_2694_p1;
wire [8:0] tmp_613_fu_2713_p2;
reg [8:0] tmp_613_reg_5362;
wire [8:0] tmp_614_fu_2718_p2;
reg [8:0] tmp_614_reg_5367;
reg [31:0] tmp_11_0_3_reg_5372;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_3_reg_5372;
wire [31:0] tmp_44_fu_2723_p1;
wire [31:0] tmp_46_fu_2727_p1;
wire [31:0] tmp_639_fu_2746_p1;
reg [31:0] tmp_639_reg_5402;
reg [31:0] tmp_11_1_3_reg_5407;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_3_reg_5407;
wire [31:0] tmp_97_fu_2750_p1;
reg [31:0] tmp_11_2_3_reg_5417;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_3_reg_5417;
wire [31:0] tmp_133_fu_2755_p1;
reg [31:0] tmp_11_3_3_reg_5427;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_3_reg_5427;
wire [31:0] tmp_168_fu_2760_p1;
reg [31:0] tmp_11_4_3_reg_5437;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_3_reg_5437;
wire [31:0] tmp_203_fu_2765_p1;
reg [31:0] tmp_11_5_3_reg_5447;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_3_reg_5447;
wire [31:0] tmp_238_fu_2770_p1;
reg [31:0] tmp_11_6_3_reg_5457;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_3_reg_5457;
wire [31:0] tmp_273_fu_2775_p1;
reg [31:0] tmp_11_7_3_reg_5467;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_3_reg_5467;
wire [31:0] tmp_308_fu_2780_p1;
reg [31:0] tmp_11_8_3_reg_5477;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_3_reg_5477;
wire [31:0] tmp_343_fu_2785_p1;
reg [31:0] tmp_11_9_3_reg_5487;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_3_reg_5487;
wire [31:0] tmp_378_fu_2790_p1;
reg [31:0] tmp_11_10_3_reg_5497;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_3_reg_5497;
wire [31:0] tmp_413_fu_2795_p1;
reg [31:0] tmp_11_11_3_reg_5507;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_3_reg_5507;
wire [31:0] tmp_448_fu_2800_p1;
reg [31:0] tmp_11_12_3_reg_5517;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_3_reg_5517;
wire [31:0] tmp_483_fu_2805_p1;
reg [31:0] tmp_11_13_3_reg_5527;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_3_reg_5527;
wire [31:0] tmp_518_fu_2810_p1;
reg [31:0] tmp_11_14_3_reg_5537;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_3_reg_5537;
wire [31:0] tmp_553_fu_2815_p1;
reg [31:0] tmp_11_15_3_reg_5547;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_3_reg_5547;
wire [31:0] tmp_588_fu_2820_p1;
reg [31:0] tmp_11_0_4_reg_5562;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_4_reg_5562;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_4_reg_5562;
wire [31:0] tmp_48_fu_2829_p1;
wire [31:0] tmp_50_fu_2833_p1;
wire [31:0] tmp_640_fu_2852_p1;
reg [31:0] tmp_640_reg_5592;
reg [31:0] tmp_11_1_4_reg_5597;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_4_reg_5597;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_4_reg_5597;
wire [31:0] tmp_99_fu_2856_p1;
reg [31:0] tmp_108_reg_5607;
reg [31:0] tmp_11_2_4_reg_5612;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_4_reg_5612;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_4_reg_5612;
wire [31:0] tmp_135_fu_2860_p1;
reg [31:0] tmp_144_reg_5622;
reg [31:0] tmp_11_3_4_reg_5627;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_4_reg_5627;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_4_reg_5627;
wire [31:0] tmp_170_fu_2864_p1;
reg [31:0] tmp_179_reg_5637;
reg [31:0] tmp_11_4_4_reg_5642;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_4_reg_5642;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_4_reg_5642;
wire [31:0] tmp_205_fu_2868_p1;
reg [31:0] tmp_214_reg_5652;
reg [31:0] tmp_11_5_4_reg_5657;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_4_reg_5657;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_4_reg_5657;
wire [31:0] tmp_240_fu_2872_p1;
reg [31:0] tmp_249_reg_5667;
reg [31:0] tmp_11_6_4_reg_5672;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_4_reg_5672;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_4_reg_5672;
wire [31:0] tmp_275_fu_2876_p1;
reg [31:0] tmp_284_reg_5682;
reg [31:0] tmp_11_7_4_reg_5687;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_4_reg_5687;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_4_reg_5687;
wire [31:0] tmp_310_fu_2880_p1;
reg [31:0] tmp_319_reg_5697;
reg [31:0] tmp_11_8_4_reg_5702;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_4_reg_5702;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_4_reg_5702;
wire [31:0] tmp_345_fu_2884_p1;
reg [31:0] tmp_354_reg_5712;
reg [31:0] tmp_11_9_4_reg_5717;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_4_reg_5717;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_4_reg_5717;
wire [31:0] tmp_380_fu_2888_p1;
reg [31:0] tmp_389_reg_5727;
reg [31:0] tmp_11_10_4_reg_5732;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_4_reg_5732;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_4_reg_5732;
wire [31:0] tmp_415_fu_2892_p1;
reg [31:0] tmp_424_reg_5742;
reg [31:0] tmp_11_11_4_reg_5747;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_4_reg_5747;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_4_reg_5747;
wire [31:0] tmp_450_fu_2896_p1;
reg [31:0] tmp_459_reg_5757;
reg [31:0] tmp_11_12_4_reg_5762;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_4_reg_5762;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_4_reg_5762;
wire [31:0] tmp_485_fu_2900_p1;
reg [31:0] tmp_494_reg_5772;
reg [31:0] tmp_11_13_4_reg_5777;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_4_reg_5777;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_4_reg_5777;
wire [31:0] tmp_520_fu_2904_p1;
reg [31:0] tmp_529_reg_5787;
reg [31:0] tmp_11_14_4_reg_5792;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_4_reg_5792;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_4_reg_5792;
wire [31:0] tmp_555_fu_2908_p1;
reg [31:0] tmp_564_reg_5802;
reg [31:0] tmp_11_15_4_reg_5807;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_4_reg_5807;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_4_reg_5807;
wire [31:0] tmp_590_fu_2912_p1;
reg [31:0] tmp_599_reg_5817;
reg [31:0] tmp_11_0_5_reg_5827;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_5_reg_5827;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_5_reg_5827;
wire [31:0] tmp_52_fu_2920_p1;
wire [31:0] tmp_54_fu_2924_p1;
wire [31:0] tmp_641_fu_2943_p1;
reg [31:0] tmp_641_reg_5857;
reg [31:0] tmp_11_1_5_reg_5862;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_5_reg_5862;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_5_reg_5862;
wire [31:0] tmp_101_fu_2947_p1;
reg [31:0] tmp_110_reg_5872;
reg [31:0] tmp_11_2_5_reg_5877;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_5_reg_5877;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_5_reg_5877;
wire [31:0] tmp_137_fu_2952_p1;
reg [31:0] tmp_146_reg_5887;
reg [31:0] tmp_11_3_5_reg_5892;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_5_reg_5892;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_5_reg_5892;
wire [31:0] tmp_172_fu_2957_p1;
reg [31:0] tmp_181_reg_5902;
reg [31:0] tmp_11_4_5_reg_5907;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_5_reg_5907;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_5_reg_5907;
wire [31:0] tmp_207_fu_2962_p1;
reg [31:0] tmp_216_reg_5917;
reg [31:0] tmp_11_5_5_reg_5922;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_5_reg_5922;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_5_reg_5922;
wire [31:0] tmp_242_fu_2967_p1;
reg [31:0] tmp_251_reg_5932;
reg [31:0] tmp_11_6_5_reg_5937;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_5_reg_5937;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_5_reg_5937;
wire [31:0] tmp_277_fu_2972_p1;
reg [31:0] tmp_286_reg_5947;
reg [31:0] tmp_11_7_5_reg_5952;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_5_reg_5952;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_5_reg_5952;
wire [31:0] tmp_312_fu_2977_p1;
reg [31:0] tmp_321_reg_5962;
reg [31:0] tmp_11_8_5_reg_5967;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_5_reg_5967;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_5_reg_5967;
wire [31:0] tmp_347_fu_2982_p1;
reg [31:0] tmp_356_reg_5977;
reg [31:0] tmp_11_9_5_reg_5982;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_5_reg_5982;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_5_reg_5982;
wire [31:0] tmp_382_fu_2987_p1;
reg [31:0] tmp_391_reg_5992;
reg [31:0] tmp_11_10_5_reg_5997;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_5_reg_5997;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_5_reg_5997;
wire [31:0] tmp_417_fu_2992_p1;
reg [31:0] tmp_426_reg_6007;
reg [31:0] tmp_11_11_5_reg_6012;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_5_reg_6012;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_5_reg_6012;
wire [31:0] tmp_452_fu_2997_p1;
reg [31:0] tmp_461_reg_6022;
reg [31:0] tmp_11_12_5_reg_6027;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_5_reg_6027;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_5_reg_6027;
wire [31:0] tmp_487_fu_3002_p1;
reg [31:0] tmp_496_reg_6037;
reg [31:0] tmp_11_13_5_reg_6042;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_5_reg_6042;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_5_reg_6042;
wire [31:0] tmp_522_fu_3007_p1;
reg [31:0] tmp_531_reg_6052;
reg [31:0] tmp_11_14_5_reg_6057;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_5_reg_6057;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_5_reg_6057;
wire [31:0] tmp_557_fu_3012_p1;
reg [31:0] tmp_566_reg_6067;
reg [31:0] tmp_11_15_5_reg_6072;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_5_reg_6072;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_5_reg_6072;
wire [31:0] tmp_592_fu_3017_p1;
reg [31:0] tmp_601_reg_6082;
reg [31:0] tmp_11_0_6_reg_6087;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_6_reg_6087;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_6_reg_6087;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_6_reg_6087;
wire [31:0] tmp_56_fu_3022_p1;
wire [31:0] tmp_58_fu_3026_p1;
wire [31:0] tmp_642_fu_3045_p1;
reg [31:0] tmp_642_reg_6117;
reg [31:0] tmp_11_1_6_reg_6122;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_6_reg_6122;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_6_reg_6122;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_6_reg_6122;
wire [31:0] tmp_103_fu_3049_p1;
reg [31:0] tmp_112_reg_6132;
reg [31:0] tmp_11_2_6_reg_6137;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_6_reg_6137;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_6_reg_6137;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_6_reg_6137;
wire [31:0] tmp_139_fu_3054_p1;
reg [31:0] tmp_148_reg_6147;
reg [31:0] tmp_11_3_6_reg_6152;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_6_reg_6152;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_6_reg_6152;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_6_reg_6152;
wire [31:0] tmp_174_fu_3059_p1;
reg [31:0] tmp_183_reg_6162;
reg [31:0] tmp_11_4_6_reg_6167;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_6_reg_6167;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_6_reg_6167;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_6_reg_6167;
wire [31:0] tmp_209_fu_3064_p1;
reg [31:0] tmp_218_reg_6177;
reg [31:0] tmp_11_5_6_reg_6182;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_6_reg_6182;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_6_reg_6182;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_6_reg_6182;
wire [31:0] tmp_244_fu_3069_p1;
reg [31:0] tmp_253_reg_6192;
reg [31:0] tmp_11_6_6_reg_6197;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_6_reg_6197;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_6_reg_6197;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_6_reg_6197;
wire [31:0] tmp_279_fu_3074_p1;
reg [31:0] tmp_288_reg_6207;
reg [31:0] tmp_11_7_6_reg_6212;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_6_reg_6212;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_6_reg_6212;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_6_reg_6212;
wire [31:0] tmp_314_fu_3079_p1;
reg [31:0] tmp_323_reg_6222;
reg [31:0] tmp_11_8_6_reg_6227;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_6_reg_6227;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_6_reg_6227;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_6_reg_6227;
wire [31:0] tmp_349_fu_3084_p1;
reg [31:0] tmp_358_reg_6237;
reg [31:0] tmp_11_9_6_reg_6242;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_6_reg_6242;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_6_reg_6242;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_6_reg_6242;
wire [31:0] tmp_384_fu_3089_p1;
reg [31:0] tmp_393_reg_6252;
reg [31:0] tmp_11_10_6_reg_6257;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_6_reg_6257;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_6_reg_6257;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_6_reg_6257;
wire [31:0] tmp_419_fu_3094_p1;
reg [31:0] tmp_428_reg_6267;
reg [31:0] tmp_11_11_6_reg_6272;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_6_reg_6272;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_6_reg_6272;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_6_reg_6272;
wire [31:0] tmp_454_fu_3099_p1;
reg [31:0] tmp_463_reg_6282;
reg [31:0] tmp_11_12_6_reg_6287;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_6_reg_6287;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_6_reg_6287;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_6_reg_6287;
wire [31:0] tmp_489_fu_3104_p1;
reg [31:0] tmp_498_reg_6297;
reg [31:0] tmp_11_13_6_reg_6302;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_6_reg_6302;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_6_reg_6302;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_6_reg_6302;
wire [31:0] tmp_524_fu_3109_p1;
reg [31:0] tmp_533_reg_6312;
reg [31:0] tmp_11_14_6_reg_6317;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_6_reg_6317;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_6_reg_6317;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_6_reg_6317;
wire [31:0] tmp_559_fu_3114_p1;
reg [31:0] tmp_568_reg_6327;
reg [31:0] tmp_11_15_6_reg_6332;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_6_reg_6332;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_6_reg_6332;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_6_reg_6332;
wire [31:0] tmp_594_fu_3119_p1;
reg [31:0] tmp_603_reg_6342;
reg [31:0] tmp_11_0_7_reg_6347;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_7_reg_6347;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_7_reg_6347;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_7_reg_6347;
wire [31:0] tmp_60_fu_3124_p1;
wire [31:0] tmp_62_fu_3128_p1;
reg [31:0] tmp_11_1_7_reg_6377;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_7_reg_6377;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_7_reg_6377;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_7_reg_6377;
wire [31:0] tmp_105_fu_3147_p1;
reg [31:0] tmp_11_2_7_reg_6387;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_7_reg_6387;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_7_reg_6387;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_7_reg_6387;
wire [31:0] tmp_141_fu_3152_p1;
reg [31:0] tmp_11_3_7_reg_6397;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_7_reg_6397;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_7_reg_6397;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_7_reg_6397;
wire [31:0] tmp_176_fu_3157_p1;
reg [31:0] tmp_11_4_7_reg_6407;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_7_reg_6407;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_7_reg_6407;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_7_reg_6407;
wire [31:0] tmp_211_fu_3162_p1;
reg [31:0] tmp_11_5_7_reg_6417;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_7_reg_6417;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_7_reg_6417;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_7_reg_6417;
wire [31:0] tmp_246_fu_3167_p1;
reg [31:0] tmp_11_6_7_reg_6427;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_7_reg_6427;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_7_reg_6427;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_7_reg_6427;
wire [31:0] tmp_281_fu_3172_p1;
reg [31:0] tmp_11_7_7_reg_6437;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_7_reg_6437;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_7_reg_6437;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_7_reg_6437;
wire [31:0] tmp_316_fu_3177_p1;
reg [31:0] tmp_11_8_7_reg_6447;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_7_reg_6447;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_7_reg_6447;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_7_reg_6447;
wire [31:0] tmp_351_fu_3182_p1;
reg [31:0] tmp_11_9_7_reg_6457;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_7_reg_6457;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_7_reg_6457;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_7_reg_6457;
wire [31:0] tmp_386_fu_3187_p1;
reg [31:0] tmp_11_10_7_reg_6467;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_7_reg_6467;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_7_reg_6467;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_7_reg_6467;
wire [31:0] tmp_421_fu_3192_p1;
reg [31:0] tmp_11_11_7_reg_6477;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_7_reg_6477;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_7_reg_6477;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_7_reg_6477;
wire [31:0] tmp_456_fu_3197_p1;
reg [31:0] tmp_11_12_7_reg_6487;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_7_reg_6487;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_7_reg_6487;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_7_reg_6487;
wire [31:0] tmp_491_fu_3202_p1;
reg [31:0] tmp_11_13_7_reg_6497;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_7_reg_6497;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_7_reg_6497;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_7_reg_6497;
wire [31:0] tmp_526_fu_3207_p1;
reg [31:0] tmp_11_14_7_reg_6507;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_7_reg_6507;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_7_reg_6507;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_7_reg_6507;
wire [31:0] tmp_561_fu_3212_p1;
reg [31:0] tmp_11_15_7_reg_6517;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_7_reg_6517;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_7_reg_6517;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_7_reg_6517;
wire [31:0] tmp_596_fu_3217_p1;
reg [31:0] tmp_11_0_8_reg_6527;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_8_reg_6527;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_8_reg_6527;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_8_reg_6527;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_8_reg_6527;
wire [31:0] tmp_64_fu_3222_p1;
wire [31:0] tmp_66_fu_3226_p1;
reg [31:0] tmp_11_1_8_reg_6557;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_8_reg_6557;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_8_reg_6557;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_8_reg_6557;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_8_reg_6557;
wire [31:0] tmp_107_fu_3245_p1;
reg [31:0] tmp_11_2_8_reg_6567;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_8_reg_6567;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_8_reg_6567;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_8_reg_6567;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_8_reg_6567;
wire [31:0] tmp_143_fu_3250_p1;
reg [31:0] tmp_11_3_8_reg_6577;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_8_reg_6577;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_8_reg_6577;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_8_reg_6577;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_8_reg_6577;
wire [31:0] tmp_178_fu_3255_p1;
reg [31:0] tmp_11_4_8_reg_6587;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_8_reg_6587;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_8_reg_6587;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_8_reg_6587;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_8_reg_6587;
wire [31:0] tmp_213_fu_3260_p1;
reg [31:0] tmp_11_5_8_reg_6597;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_8_reg_6597;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_8_reg_6597;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_8_reg_6597;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_8_reg_6597;
wire [31:0] tmp_248_fu_3265_p1;
reg [31:0] tmp_11_6_8_reg_6607;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_8_reg_6607;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_8_reg_6607;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_8_reg_6607;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_8_reg_6607;
wire [31:0] tmp_283_fu_3270_p1;
reg [31:0] tmp_11_7_8_reg_6617;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_8_reg_6617;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_8_reg_6617;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_8_reg_6617;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_8_reg_6617;
wire [31:0] tmp_318_fu_3275_p1;
reg [31:0] tmp_11_8_8_reg_6627;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_8_reg_6627;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_8_reg_6627;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_8_reg_6627;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_8_reg_6627;
wire [31:0] tmp_353_fu_3280_p1;
reg [31:0] tmp_11_9_8_reg_6637;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_8_reg_6637;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_8_reg_6637;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_8_reg_6637;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_8_reg_6637;
wire [31:0] tmp_388_fu_3285_p1;
reg [31:0] tmp_11_10_8_reg_6647;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_8_reg_6647;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_8_reg_6647;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_8_reg_6647;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_8_reg_6647;
wire [31:0] tmp_423_fu_3290_p1;
reg [31:0] tmp_11_11_8_reg_6657;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_8_reg_6657;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_8_reg_6657;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_8_reg_6657;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_8_reg_6657;
wire [31:0] tmp_458_fu_3295_p1;
reg [31:0] tmp_11_12_8_reg_6667;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_8_reg_6667;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_8_reg_6667;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_8_reg_6667;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_8_reg_6667;
wire [31:0] tmp_493_fu_3300_p1;
reg [31:0] tmp_11_13_8_reg_6677;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_8_reg_6677;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_8_reg_6677;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_8_reg_6677;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_8_reg_6677;
wire [31:0] tmp_528_fu_3305_p1;
reg [31:0] tmp_11_14_8_reg_6687;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_8_reg_6687;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_8_reg_6687;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_8_reg_6687;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_8_reg_6687;
wire [31:0] tmp_563_fu_3310_p1;
reg [31:0] tmp_11_15_8_reg_6697;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_8_reg_6697;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_8_reg_6697;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_8_reg_6697;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_8_reg_6697;
wire [31:0] tmp_598_fu_3315_p1;
reg [31:0] tmp_607_reg_6707;
reg [31:0] tmp_11_0_9_reg_6712;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_9_reg_6712;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_9_reg_6712;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_9_reg_6712;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_9_reg_6712;
wire [31:0] tmp_68_fu_3320_p1;
wire [31:0] tmp_70_fu_3324_p1;
reg [31:0] tmp_12_1_reg_6742;
reg [31:0] tmp_11_1_9_reg_6747;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_9_reg_6747;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_9_reg_6747;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_9_reg_6747;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_9_reg_6747;
wire [31:0] tmp_109_fu_3343_p1;
reg [31:0] tmp_12_2_reg_6757;
reg [31:0] tmp_11_2_9_reg_6762;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_9_reg_6762;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_9_reg_6762;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_9_reg_6762;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_9_reg_6762;
wire [31:0] tmp_145_fu_3347_p1;
reg [31:0] tmp_12_3_reg_6772;
reg [31:0] tmp_11_3_9_reg_6777;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_9_reg_6777;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_9_reg_6777;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_9_reg_6777;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_9_reg_6777;
wire [31:0] tmp_180_fu_3351_p1;
reg [31:0] tmp_12_4_reg_6787;
reg [31:0] tmp_11_4_9_reg_6792;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_9_reg_6792;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_9_reg_6792;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_9_reg_6792;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_9_reg_6792;
wire [31:0] tmp_215_fu_3355_p1;
reg [31:0] tmp_12_5_reg_6802;
reg [31:0] tmp_11_5_9_reg_6807;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_9_reg_6807;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_9_reg_6807;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_9_reg_6807;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_9_reg_6807;
wire [31:0] tmp_250_fu_3359_p1;
reg [31:0] tmp_12_6_reg_6817;
reg [31:0] tmp_11_6_9_reg_6822;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_9_reg_6822;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_9_reg_6822;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_9_reg_6822;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_9_reg_6822;
wire [31:0] tmp_285_fu_3363_p1;
reg [31:0] tmp_12_7_reg_6832;
reg [31:0] tmp_11_7_9_reg_6837;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_9_reg_6837;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_9_reg_6837;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_9_reg_6837;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_9_reg_6837;
wire [31:0] tmp_320_fu_3367_p1;
reg [31:0] tmp_12_8_reg_6847;
reg [31:0] tmp_11_8_9_reg_6852;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_9_reg_6852;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_9_reg_6852;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_9_reg_6852;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_9_reg_6852;
wire [31:0] tmp_355_fu_3371_p1;
reg [31:0] tmp_12_9_reg_6862;
reg [31:0] tmp_11_9_9_reg_6867;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_9_reg_6867;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_9_reg_6867;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_9_reg_6867;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_9_reg_6867;
wire [31:0] tmp_390_fu_3375_p1;
reg [31:0] tmp_12_s_reg_6877;
reg [31:0] tmp_11_10_9_reg_6882;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_9_reg_6882;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_9_reg_6882;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_9_reg_6882;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_9_reg_6882;
wire [31:0] tmp_425_fu_3379_p1;
reg [31:0] tmp_12_10_reg_6892;
reg [31:0] tmp_11_11_9_reg_6897;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_9_reg_6897;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_9_reg_6897;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_9_reg_6897;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_9_reg_6897;
wire [31:0] tmp_460_fu_3383_p1;
reg [31:0] tmp_12_11_reg_6907;
reg [31:0] tmp_11_12_9_reg_6912;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_9_reg_6912;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_9_reg_6912;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_9_reg_6912;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_9_reg_6912;
wire [31:0] tmp_495_fu_3387_p1;
reg [31:0] tmp_12_12_reg_6922;
reg [31:0] tmp_11_13_9_reg_6927;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_9_reg_6927;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_9_reg_6927;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_9_reg_6927;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_9_reg_6927;
wire [31:0] tmp_530_fu_3391_p1;
reg [31:0] tmp_12_13_reg_6937;
reg [31:0] tmp_11_14_9_reg_6942;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_9_reg_6942;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_9_reg_6942;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_9_reg_6942;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_9_reg_6942;
wire [31:0] tmp_565_fu_3395_p1;
reg [31:0] tmp_12_14_reg_6952;
reg [31:0] tmp_11_15_9_reg_6957;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_9_reg_6957;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_9_reg_6957;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_9_reg_6957;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_9_reg_6957;
wire [31:0] tmp_600_fu_3399_p1;
reg [31:0] tmp_11_0_s_reg_6967;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_s_reg_6967;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_s_reg_6967;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_s_reg_6967;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_s_reg_6967;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_s_reg_6967;
wire [31:0] tmp_72_fu_3403_p1;
wire [31:0] tmp_74_fu_3407_p1;
reg [31:0] tmp_11_1_s_reg_6997;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_s_reg_6997;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_s_reg_6997;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_s_reg_6997;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_s_reg_6997;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_s_reg_6997;
wire [31:0] tmp_111_fu_3426_p1;
reg [31:0] tmp_11_2_s_reg_7007;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_s_reg_7007;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_s_reg_7007;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_s_reg_7007;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_s_reg_7007;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_s_reg_7007;
wire [31:0] tmp_147_fu_3430_p1;
reg [31:0] tmp_11_3_s_reg_7017;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_s_reg_7017;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_s_reg_7017;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_s_reg_7017;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_s_reg_7017;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_s_reg_7017;
wire [31:0] tmp_182_fu_3434_p1;
reg [31:0] tmp_11_4_s_reg_7027;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_s_reg_7027;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_s_reg_7027;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_s_reg_7027;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_s_reg_7027;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_s_reg_7027;
wire [31:0] tmp_217_fu_3438_p1;
reg [31:0] tmp_11_5_s_reg_7037;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_s_reg_7037;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_s_reg_7037;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_s_reg_7037;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_s_reg_7037;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_s_reg_7037;
wire [31:0] tmp_252_fu_3442_p1;
reg [31:0] tmp_11_6_s_reg_7047;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_s_reg_7047;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_s_reg_7047;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_s_reg_7047;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_s_reg_7047;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_s_reg_7047;
wire [31:0] tmp_287_fu_3446_p1;
reg [31:0] tmp_11_7_s_reg_7057;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_s_reg_7057;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_s_reg_7057;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_s_reg_7057;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_s_reg_7057;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_s_reg_7057;
wire [31:0] tmp_322_fu_3450_p1;
reg [31:0] tmp_11_8_s_reg_7067;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_s_reg_7067;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_s_reg_7067;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_s_reg_7067;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_s_reg_7067;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_s_reg_7067;
wire [31:0] tmp_357_fu_3454_p1;
reg [31:0] tmp_11_9_s_reg_7077;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_s_reg_7077;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_s_reg_7077;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_s_reg_7077;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_s_reg_7077;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_s_reg_7077;
wire [31:0] tmp_392_fu_3458_p1;
reg [31:0] tmp_11_10_s_reg_7087;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_s_reg_7087;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_s_reg_7087;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_s_reg_7087;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_s_reg_7087;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_s_reg_7087;
wire [31:0] tmp_427_fu_3462_p1;
reg [31:0] tmp_11_11_s_reg_7097;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_s_reg_7097;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_s_reg_7097;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_s_reg_7097;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_s_reg_7097;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_s_reg_7097;
wire [31:0] tmp_462_fu_3466_p1;
reg [31:0] tmp_11_12_s_reg_7107;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_s_reg_7107;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_s_reg_7107;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_s_reg_7107;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_s_reg_7107;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_s_reg_7107;
wire [31:0] tmp_497_fu_3470_p1;
reg [31:0] tmp_11_13_s_reg_7117;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_s_reg_7117;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_s_reg_7117;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_s_reg_7117;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_s_reg_7117;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_s_reg_7117;
wire [31:0] tmp_532_fu_3474_p1;
reg [31:0] tmp_11_14_s_reg_7127;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_s_reg_7127;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_s_reg_7127;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_s_reg_7127;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_s_reg_7127;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_s_reg_7127;
wire [31:0] tmp_567_fu_3478_p1;
reg [31:0] tmp_11_15_s_reg_7137;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_s_reg_7137;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_s_reg_7137;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_s_reg_7137;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_s_reg_7137;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_s_reg_7137;
wire [31:0] tmp_602_fu_3482_p1;
reg [31:0] tmp_11_0_10_reg_7147;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_10_reg_7147;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_10_reg_7147;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_10_reg_7147;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_10_reg_7147;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_10_reg_7147;
wire [31:0] tmp_76_fu_3486_p1;
wire [31:0] tmp_78_fu_3490_p1;
reg [31:0] tmp_11_1_10_reg_7177;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_10_reg_7177;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_10_reg_7177;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_10_reg_7177;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_10_reg_7177;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_10_reg_7177;
wire [31:0] tmp_113_fu_3509_p1;
reg [31:0] tmp_11_2_10_reg_7187;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_10_reg_7187;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_10_reg_7187;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_10_reg_7187;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_10_reg_7187;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_10_reg_7187;
wire [31:0] tmp_149_fu_3513_p1;
reg [31:0] tmp_11_3_10_reg_7197;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_10_reg_7197;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_10_reg_7197;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_10_reg_7197;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_10_reg_7197;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_10_reg_7197;
wire [31:0] tmp_184_fu_3517_p1;
reg [31:0] tmp_11_4_10_reg_7207;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_10_reg_7207;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_10_reg_7207;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_10_reg_7207;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_10_reg_7207;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_10_reg_7207;
wire [31:0] tmp_219_fu_3521_p1;
reg [31:0] tmp_11_5_10_reg_7217;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_10_reg_7217;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_10_reg_7217;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_10_reg_7217;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_10_reg_7217;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_10_reg_7217;
wire [31:0] tmp_254_fu_3525_p1;
reg [31:0] tmp_11_6_10_reg_7227;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_10_reg_7227;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_10_reg_7227;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_10_reg_7227;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_10_reg_7227;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_10_reg_7227;
wire [31:0] tmp_289_fu_3529_p1;
reg [31:0] tmp_11_7_10_reg_7237;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_10_reg_7237;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_10_reg_7237;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_10_reg_7237;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_10_reg_7237;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_10_reg_7237;
wire [31:0] tmp_324_fu_3533_p1;
reg [31:0] tmp_11_8_10_reg_7247;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_10_reg_7247;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_10_reg_7247;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_10_reg_7247;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_10_reg_7247;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_10_reg_7247;
wire [31:0] tmp_359_fu_3537_p1;
reg [31:0] tmp_11_9_10_reg_7257;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_10_reg_7257;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_10_reg_7257;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_10_reg_7257;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_10_reg_7257;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_10_reg_7257;
wire [31:0] tmp_394_fu_3541_p1;
reg [31:0] tmp_11_10_10_reg_7267;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_10_reg_7267;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_10_reg_7267;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_10_reg_7267;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_10_reg_7267;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_10_reg_7267;
wire [31:0] tmp_429_fu_3545_p1;
reg [31:0] tmp_11_11_10_reg_7277;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_10_reg_7277;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_10_reg_7277;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_10_reg_7277;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_10_reg_7277;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_10_reg_7277;
wire [31:0] tmp_464_fu_3549_p1;
reg [31:0] tmp_11_12_10_reg_7287;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_10_reg_7287;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_10_reg_7287;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_10_reg_7287;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_10_reg_7287;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_10_reg_7287;
wire [31:0] tmp_499_fu_3553_p1;
reg [31:0] tmp_11_13_10_reg_7297;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_10_reg_7297;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_10_reg_7297;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_10_reg_7297;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_10_reg_7297;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_10_reg_7297;
wire [31:0] tmp_534_fu_3557_p1;
reg [31:0] tmp_11_14_10_reg_7307;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_10_reg_7307;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_10_reg_7307;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_10_reg_7307;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_10_reg_7307;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_10_reg_7307;
wire [31:0] tmp_569_fu_3561_p1;
reg [31:0] tmp_11_15_10_reg_7317;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_10_reg_7317;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_10_reg_7317;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_10_reg_7317;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_10_reg_7317;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_10_reg_7317;
wire [31:0] tmp_604_fu_3565_p1;
reg [31:0] tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_11_reg_7327;
reg [31:0] ap_reg_pp0_iter7_tmp_11_0_11_reg_7327;
reg [31:0] tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_11_reg_7332;
reg [31:0] ap_reg_pp0_iter7_tmp_11_1_11_reg_7332;
reg [31:0] tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_11_reg_7337;
reg [31:0] ap_reg_pp0_iter7_tmp_11_2_11_reg_7337;
reg [31:0] tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_11_reg_7342;
reg [31:0] ap_reg_pp0_iter7_tmp_11_3_11_reg_7342;
reg [31:0] tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_11_reg_7347;
reg [31:0] ap_reg_pp0_iter7_tmp_11_4_11_reg_7347;
reg [31:0] tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_11_reg_7352;
reg [31:0] ap_reg_pp0_iter7_tmp_11_5_11_reg_7352;
reg [31:0] tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_11_reg_7357;
reg [31:0] ap_reg_pp0_iter7_tmp_11_6_11_reg_7357;
reg [31:0] tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_11_reg_7362;
reg [31:0] ap_reg_pp0_iter7_tmp_11_7_11_reg_7362;
reg [31:0] tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_11_reg_7367;
reg [31:0] ap_reg_pp0_iter7_tmp_11_8_11_reg_7367;
reg [31:0] tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_11_reg_7372;
reg [31:0] ap_reg_pp0_iter7_tmp_11_9_11_reg_7372;
reg [31:0] tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_11_reg_7377;
reg [31:0] ap_reg_pp0_iter7_tmp_11_10_11_reg_7377;
reg [31:0] tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_11_reg_7382;
reg [31:0] ap_reg_pp0_iter7_tmp_11_11_11_reg_7382;
reg [31:0] tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_11_reg_7387;
reg [31:0] ap_reg_pp0_iter7_tmp_11_12_11_reg_7387;
reg [31:0] tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_11_reg_7392;
reg [31:0] ap_reg_pp0_iter7_tmp_11_13_11_reg_7392;
reg [31:0] tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_11_reg_7397;
reg [31:0] ap_reg_pp0_iter7_tmp_11_14_11_reg_7397;
reg [31:0] tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_11_reg_7402;
reg [31:0] ap_reg_pp0_iter7_tmp_11_15_11_reg_7402;
reg [31:0] tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_12_reg_7407;
reg [31:0] ap_reg_pp0_iter7_tmp_11_0_12_reg_7407;
reg [31:0] tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_12_reg_7412;
reg [31:0] ap_reg_pp0_iter7_tmp_11_1_12_reg_7412;
reg [31:0] tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_12_reg_7417;
reg [31:0] ap_reg_pp0_iter7_tmp_11_2_12_reg_7417;
reg [31:0] tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_12_reg_7422;
reg [31:0] ap_reg_pp0_iter7_tmp_11_3_12_reg_7422;
reg [31:0] tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_12_reg_7427;
reg [31:0] ap_reg_pp0_iter7_tmp_11_4_12_reg_7427;
reg [31:0] tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_12_reg_7432;
reg [31:0] ap_reg_pp0_iter7_tmp_11_5_12_reg_7432;
reg [31:0] tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_12_reg_7437;
reg [31:0] ap_reg_pp0_iter7_tmp_11_6_12_reg_7437;
reg [31:0] tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_12_reg_7442;
reg [31:0] ap_reg_pp0_iter7_tmp_11_7_12_reg_7442;
reg [31:0] tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_12_reg_7447;
reg [31:0] ap_reg_pp0_iter7_tmp_11_8_12_reg_7447;
reg [31:0] tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_12_reg_7452;
reg [31:0] ap_reg_pp0_iter7_tmp_11_9_12_reg_7452;
reg [31:0] tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_12_reg_7457;
reg [31:0] ap_reg_pp0_iter7_tmp_11_10_12_reg_7457;
reg [31:0] tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_12_reg_7462;
reg [31:0] ap_reg_pp0_iter7_tmp_11_11_12_reg_7462;
reg [31:0] tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_12_reg_7467;
reg [31:0] ap_reg_pp0_iter7_tmp_11_12_12_reg_7467;
reg [31:0] tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_12_reg_7472;
reg [31:0] ap_reg_pp0_iter7_tmp_11_13_12_reg_7472;
reg [31:0] tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_12_reg_7477;
reg [31:0] ap_reg_pp0_iter7_tmp_11_14_12_reg_7477;
reg [31:0] tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_12_reg_7482;
reg [31:0] ap_reg_pp0_iter7_tmp_11_15_12_reg_7482;
reg [31:0] tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter7_tmp_11_0_13_reg_7487;
reg [31:0] ap_reg_pp0_iter8_tmp_11_0_13_reg_7487;
reg [31:0] tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter7_tmp_11_1_13_reg_7492;
reg [31:0] ap_reg_pp0_iter8_tmp_11_1_13_reg_7492;
reg [31:0] tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter7_tmp_11_2_13_reg_7497;
reg [31:0] ap_reg_pp0_iter8_tmp_11_2_13_reg_7497;
reg [31:0] tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter7_tmp_11_3_13_reg_7502;
reg [31:0] ap_reg_pp0_iter8_tmp_11_3_13_reg_7502;
reg [31:0] tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter7_tmp_11_4_13_reg_7507;
reg [31:0] ap_reg_pp0_iter8_tmp_11_4_13_reg_7507;
reg [31:0] tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter7_tmp_11_5_13_reg_7512;
reg [31:0] ap_reg_pp0_iter8_tmp_11_5_13_reg_7512;
reg [31:0] tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter7_tmp_11_6_13_reg_7517;
reg [31:0] ap_reg_pp0_iter8_tmp_11_6_13_reg_7517;
reg [31:0] tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter7_tmp_11_7_13_reg_7522;
reg [31:0] ap_reg_pp0_iter8_tmp_11_7_13_reg_7522;
reg [31:0] tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter7_tmp_11_8_13_reg_7527;
reg [31:0] ap_reg_pp0_iter8_tmp_11_8_13_reg_7527;
reg [31:0] tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter7_tmp_11_9_13_reg_7532;
reg [31:0] ap_reg_pp0_iter8_tmp_11_9_13_reg_7532;
reg [31:0] tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter7_tmp_11_10_13_reg_7537;
reg [31:0] ap_reg_pp0_iter8_tmp_11_10_13_reg_7537;
reg [31:0] tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter7_tmp_11_11_13_reg_7542;
reg [31:0] ap_reg_pp0_iter8_tmp_11_11_13_reg_7542;
reg [31:0] tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter7_tmp_11_12_13_reg_7547;
reg [31:0] ap_reg_pp0_iter8_tmp_11_12_13_reg_7547;
reg [31:0] tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter7_tmp_11_13_13_reg_7552;
reg [31:0] ap_reg_pp0_iter8_tmp_11_13_13_reg_7552;
reg [31:0] tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter7_tmp_11_14_13_reg_7557;
reg [31:0] ap_reg_pp0_iter8_tmp_11_14_13_reg_7557;
reg [31:0] tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter7_tmp_11_15_13_reg_7562;
reg [31:0] ap_reg_pp0_iter8_tmp_11_15_13_reg_7562;
reg [31:0] tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter2_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter3_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter4_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter5_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter6_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter7_tmp_11_0_14_reg_7567;
reg [31:0] ap_reg_pp0_iter8_tmp_11_0_14_reg_7567;
reg [31:0] tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter2_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter3_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter4_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter5_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter6_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter7_tmp_11_1_14_reg_7572;
reg [31:0] ap_reg_pp0_iter8_tmp_11_1_14_reg_7572;
reg [31:0] tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter2_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter3_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter4_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter5_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter6_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter7_tmp_11_2_14_reg_7577;
reg [31:0] ap_reg_pp0_iter8_tmp_11_2_14_reg_7577;
reg [31:0] tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter2_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter3_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter4_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter5_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter6_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter7_tmp_11_3_14_reg_7582;
reg [31:0] ap_reg_pp0_iter8_tmp_11_3_14_reg_7582;
reg [31:0] tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter2_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter3_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter4_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter5_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter6_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter7_tmp_11_4_14_reg_7587;
reg [31:0] ap_reg_pp0_iter8_tmp_11_4_14_reg_7587;
reg [31:0] tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter2_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter3_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter4_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter5_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter6_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter7_tmp_11_5_14_reg_7592;
reg [31:0] ap_reg_pp0_iter8_tmp_11_5_14_reg_7592;
reg [31:0] tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter2_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter3_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter4_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter5_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter6_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter7_tmp_11_6_14_reg_7597;
reg [31:0] ap_reg_pp0_iter8_tmp_11_6_14_reg_7597;
reg [31:0] tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter2_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter3_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter4_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter5_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter6_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter7_tmp_11_7_14_reg_7602;
reg [31:0] ap_reg_pp0_iter8_tmp_11_7_14_reg_7602;
reg [31:0] tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter2_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter3_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter4_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter5_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter6_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter7_tmp_11_8_14_reg_7607;
reg [31:0] ap_reg_pp0_iter8_tmp_11_8_14_reg_7607;
reg [31:0] tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter2_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter3_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter4_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter5_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter6_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter7_tmp_11_9_14_reg_7612;
reg [31:0] ap_reg_pp0_iter8_tmp_11_9_14_reg_7612;
reg [31:0] tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter2_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter3_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter4_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter5_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter6_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter7_tmp_11_10_14_reg_7617;
reg [31:0] ap_reg_pp0_iter8_tmp_11_10_14_reg_7617;
reg [31:0] tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter2_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter3_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter4_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter5_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter6_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter7_tmp_11_11_14_reg_7622;
reg [31:0] ap_reg_pp0_iter8_tmp_11_11_14_reg_7622;
reg [31:0] tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter2_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter3_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter4_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter5_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter6_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter7_tmp_11_12_14_reg_7627;
reg [31:0] ap_reg_pp0_iter8_tmp_11_12_14_reg_7627;
reg [31:0] tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter2_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter3_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter4_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter5_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter6_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter7_tmp_11_13_14_reg_7632;
reg [31:0] ap_reg_pp0_iter8_tmp_11_13_14_reg_7632;
reg [31:0] tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter2_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter3_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter4_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter5_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter6_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter7_tmp_11_14_14_reg_7637;
reg [31:0] ap_reg_pp0_iter8_tmp_11_14_14_reg_7637;
reg [31:0] tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter2_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter3_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter4_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter5_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter6_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter7_tmp_11_15_14_reg_7642;
reg [31:0] ap_reg_pp0_iter8_tmp_11_15_14_reg_7642;
reg [31:0] tmp_12_0_2_reg_7647;
reg ap_enable_reg_pp0_iter2;
reg [31:0] tmp_12_1_2_reg_7652;
reg [31:0] tmp_12_2_2_reg_7657;
reg [31:0] tmp_12_3_2_reg_7662;
reg [31:0] tmp_12_4_2_reg_7667;
reg [31:0] tmp_12_5_2_reg_7672;
reg [31:0] tmp_12_6_2_reg_7677;
reg [31:0] tmp_12_7_2_reg_7682;
reg [31:0] tmp_12_8_2_reg_7687;
reg [31:0] tmp_12_9_2_reg_7692;
reg [31:0] tmp_12_10_2_reg_7697;
reg [31:0] tmp_12_11_2_reg_7702;
reg [31:0] tmp_12_12_2_reg_7707;
reg [31:0] tmp_12_13_2_reg_7712;
reg [31:0] tmp_12_14_2_reg_7717;
reg [31:0] tmp_12_15_2_reg_7722;
reg [31:0] tmp_12_0_3_reg_7727;
reg ap_enable_reg_pp0_iter3;
reg [31:0] tmp_12_1_3_reg_7732;
reg [31:0] tmp_12_2_3_reg_7737;
reg [31:0] tmp_12_3_3_reg_7742;
reg [31:0] tmp_12_4_3_reg_7747;
reg [31:0] tmp_12_5_3_reg_7752;
reg [31:0] tmp_12_6_3_reg_7757;
reg [31:0] tmp_12_7_3_reg_7762;
reg [31:0] tmp_12_8_3_reg_7767;
reg [31:0] tmp_12_9_3_reg_7772;
reg [31:0] tmp_12_10_3_reg_7777;
reg [31:0] tmp_12_11_3_reg_7782;
reg [31:0] tmp_12_12_3_reg_7787;
reg [31:0] tmp_12_13_3_reg_7792;
reg [31:0] tmp_12_14_3_reg_7797;
reg [31:0] tmp_12_15_3_reg_7802;
reg [31:0] tmp_12_0_4_reg_7807;
reg [31:0] tmp_12_1_4_reg_7812;
reg [31:0] tmp_12_2_4_reg_7817;
reg [31:0] tmp_12_3_4_reg_7822;
reg [31:0] tmp_12_4_4_reg_7827;
reg [31:0] tmp_12_5_4_reg_7832;
reg [31:0] tmp_12_6_4_reg_7837;
reg [31:0] tmp_12_7_4_reg_7842;
reg [31:0] tmp_12_8_4_reg_7847;
reg [31:0] tmp_12_9_4_reg_7852;
reg [31:0] tmp_12_10_4_reg_7857;
reg [31:0] tmp_12_11_4_reg_7862;
reg [31:0] tmp_12_12_4_reg_7867;
reg [31:0] tmp_12_13_4_reg_7872;
reg [31:0] tmp_12_14_4_reg_7877;
reg [31:0] tmp_12_15_4_reg_7882;
reg [31:0] tmp_12_0_5_reg_7887;
reg ap_enable_reg_pp0_iter4;
reg [31:0] tmp_12_1_5_reg_7892;
reg [31:0] tmp_12_2_5_reg_7897;
reg [31:0] tmp_12_3_5_reg_7902;
reg [31:0] tmp_12_4_5_reg_7907;
reg [31:0] tmp_12_5_5_reg_7912;
reg [31:0] tmp_12_6_5_reg_7917;
reg [31:0] tmp_12_7_5_reg_7922;
reg [31:0] tmp_12_8_5_reg_7927;
reg [31:0] tmp_12_9_5_reg_7932;
reg [31:0] tmp_12_10_5_reg_7937;
reg [31:0] tmp_12_11_5_reg_7942;
reg [31:0] tmp_12_12_5_reg_7947;
reg [31:0] tmp_12_13_5_reg_7952;
reg [31:0] tmp_12_14_5_reg_7957;
reg [31:0] tmp_12_15_5_reg_7962;
reg [31:0] tmp_12_0_6_reg_7967;
reg [31:0] tmp_12_1_6_reg_7972;
reg [31:0] tmp_12_2_6_reg_7977;
reg [31:0] tmp_12_3_6_reg_7982;
reg [31:0] tmp_12_4_6_reg_7987;
reg [31:0] tmp_12_5_6_reg_7992;
reg [31:0] tmp_12_6_6_reg_7997;
reg [31:0] tmp_12_7_6_reg_8002;
reg [31:0] tmp_12_8_6_reg_8007;
reg [31:0] tmp_12_9_6_reg_8012;
reg [31:0] tmp_12_10_6_reg_8017;
reg [31:0] tmp_12_11_6_reg_8022;
reg [31:0] tmp_12_12_6_reg_8027;
reg [31:0] tmp_12_13_6_reg_8032;
reg [31:0] tmp_12_14_6_reg_8037;
reg [31:0] tmp_12_15_6_reg_8042;
reg [31:0] tmp_12_0_7_reg_8047;
reg ap_enable_reg_pp0_iter5;
reg [31:0] tmp_12_1_7_reg_8052;
reg [31:0] tmp_12_2_7_reg_8057;
reg [31:0] tmp_12_3_7_reg_8062;
reg [31:0] tmp_12_4_7_reg_8067;
reg [31:0] tmp_12_5_7_reg_8072;
reg [31:0] tmp_12_6_7_reg_8077;
reg [31:0] tmp_12_7_7_reg_8082;
reg [31:0] tmp_12_8_7_reg_8087;
reg [31:0] tmp_12_9_7_reg_8092;
reg [31:0] tmp_12_10_7_reg_8097;
reg [31:0] tmp_12_11_7_reg_8102;
reg [31:0] tmp_12_12_7_reg_8107;
reg [31:0] tmp_12_13_7_reg_8112;
reg [31:0] tmp_12_14_7_reg_8117;
reg [31:0] tmp_12_15_7_reg_8122;
reg [31:0] tmp_12_0_8_reg_8127;
reg [31:0] tmp_12_1_8_reg_8132;
reg [31:0] tmp_12_2_8_reg_8137;
reg [31:0] tmp_12_3_8_reg_8142;
reg [31:0] tmp_12_4_8_reg_8147;
reg [31:0] tmp_12_5_8_reg_8152;
reg [31:0] tmp_12_6_8_reg_8157;
reg [31:0] tmp_12_7_8_reg_8162;
reg [31:0] tmp_12_8_8_reg_8167;
reg [31:0] tmp_12_9_8_reg_8172;
reg [31:0] tmp_12_10_8_reg_8177;
reg [31:0] tmp_12_11_8_reg_8182;
reg [31:0] tmp_12_12_8_reg_8187;
reg [31:0] tmp_12_13_8_reg_8192;
reg [31:0] tmp_12_14_8_reg_8197;
reg [31:0] tmp_12_15_8_reg_8202;
reg [31:0] tmp_12_0_9_reg_8207;
reg ap_enable_reg_pp0_iter6;
reg [31:0] tmp_12_1_9_reg_8212;
reg [31:0] tmp_12_2_9_reg_8217;
reg [31:0] tmp_12_3_9_reg_8222;
reg [31:0] tmp_12_4_9_reg_8227;
reg [31:0] tmp_12_5_9_reg_8232;
reg [31:0] tmp_12_6_9_reg_8237;
reg [31:0] tmp_12_7_9_reg_8242;
reg [31:0] tmp_12_8_9_reg_8247;
reg [31:0] tmp_12_9_9_reg_8252;
reg [31:0] tmp_12_10_9_reg_8257;
reg [31:0] tmp_12_11_9_reg_8262;
reg [31:0] tmp_12_12_9_reg_8267;
reg [31:0] tmp_12_13_9_reg_8272;
reg [31:0] tmp_12_14_9_reg_8277;
reg [31:0] tmp_12_15_9_reg_8282;
reg [31:0] tmp_12_0_s_reg_8287;
reg ap_enable_reg_pp0_iter7;
reg [31:0] tmp_12_1_s_reg_8292;
reg [31:0] tmp_12_2_s_reg_8297;
reg [31:0] tmp_12_3_s_reg_8302;
reg [31:0] tmp_12_4_s_reg_8307;
reg [31:0] tmp_12_5_s_reg_8312;
reg [31:0] tmp_12_6_s_reg_8317;
reg [31:0] tmp_12_7_s_reg_8322;
reg [31:0] tmp_12_8_s_reg_8327;
reg [31:0] tmp_12_9_s_reg_8332;
reg [31:0] tmp_12_10_s_reg_8337;
reg [31:0] tmp_12_11_s_reg_8342;
reg [31:0] tmp_12_12_s_reg_8347;
reg [31:0] tmp_12_13_s_reg_8352;
reg [31:0] tmp_12_14_s_reg_8357;
reg [31:0] tmp_12_15_s_reg_8362;
reg [31:0] tmp_12_0_10_reg_8367;
reg [31:0] tmp_12_1_10_reg_8372;
reg [31:0] tmp_12_2_10_reg_8377;
reg [31:0] tmp_12_3_10_reg_8382;
reg [31:0] tmp_12_4_10_reg_8387;
reg [31:0] tmp_12_5_10_reg_8392;
reg [31:0] tmp_12_6_10_reg_8397;
reg [31:0] tmp_12_7_10_reg_8402;
reg [31:0] tmp_12_8_10_reg_8407;
reg [31:0] tmp_12_9_10_reg_8412;
reg [31:0] tmp_12_10_10_reg_8417;
reg [31:0] tmp_12_11_10_reg_8422;
reg [31:0] tmp_12_12_10_reg_8427;
reg [31:0] tmp_12_13_10_reg_8432;
reg [31:0] tmp_12_14_10_reg_8437;
reg [31:0] tmp_12_15_10_reg_8442;
reg [31:0] tmp_12_0_11_reg_8447;
reg ap_enable_reg_pp0_iter8;
reg [31:0] tmp_12_1_11_reg_8452;
reg [31:0] tmp_12_2_11_reg_8457;
reg [31:0] tmp_12_3_11_reg_8462;
reg [31:0] tmp_12_4_11_reg_8467;
reg [31:0] tmp_12_5_11_reg_8472;
reg [31:0] tmp_12_6_11_reg_8477;
reg [31:0] tmp_12_7_11_reg_8482;
reg [31:0] tmp_12_8_11_reg_8487;
reg [31:0] tmp_12_9_11_reg_8492;
reg [31:0] tmp_12_10_11_reg_8497;
reg [31:0] tmp_12_11_11_reg_8502;
reg [31:0] tmp_12_12_11_reg_8507;
reg [31:0] tmp_12_13_11_reg_8512;
reg [31:0] tmp_12_14_11_reg_8517;
reg [31:0] tmp_12_15_11_reg_8522;
reg [31:0] tmp_12_0_12_reg_8527;
reg [31:0] tmp_12_1_12_reg_8532;
reg [31:0] tmp_12_2_12_reg_8537;
reg [31:0] tmp_12_3_12_reg_8542;
reg [31:0] tmp_12_4_12_reg_8547;
reg [31:0] tmp_12_5_12_reg_8552;
reg [31:0] tmp_12_6_12_reg_8557;
reg [31:0] tmp_12_7_12_reg_8562;
reg [31:0] tmp_12_8_12_reg_8567;
reg [31:0] tmp_12_9_12_reg_8572;
reg [31:0] tmp_12_10_12_reg_8577;
reg [31:0] tmp_12_11_12_reg_8582;
reg [31:0] tmp_12_12_12_reg_8587;
reg [31:0] tmp_12_13_12_reg_8592;
reg [31:0] tmp_12_14_12_reg_8597;
reg [31:0] tmp_12_15_12_reg_8602;
reg [31:0] tmp_12_0_13_reg_8607;
reg [31:0] tmp_12_1_13_reg_8612;
reg [31:0] tmp_12_2_13_reg_8617;
reg [31:0] tmp_12_3_13_reg_8622;
reg [31:0] tmp_12_4_13_reg_8627;
reg [31:0] tmp_12_5_13_reg_8632;
reg [31:0] tmp_12_6_13_reg_8637;
reg [31:0] tmp_12_7_13_reg_8642;
reg [31:0] tmp_12_8_13_reg_8647;
reg [31:0] tmp_12_9_13_reg_8652;
reg [31:0] tmp_12_10_13_reg_8657;
reg [31:0] tmp_12_11_13_reg_8662;
reg [31:0] tmp_12_12_13_reg_8667;
reg [31:0] tmp_12_13_13_reg_8672;
reg [31:0] tmp_12_14_13_reg_8677;
reg [31:0] tmp_12_15_13_reg_8682;
wire ap_block_pp0_stage0_flag00011011;
reg ap_condition_pp0_exit_iter0_state2;
wire ap_block_pp0_stage15_flag00011011;
wire ap_block_pp0_stage14_flag00011011;
reg [12:0] indvar_flatten1_phi_fu_355_p4;
wire ap_block_pp0_stage0_flag00000000;
reg [2:0] i_phi_fu_366_p4;
reg [11:0] indvar_flatten2_phi_fu_378_p4;
reg [2:0] j_phi_fu_389_p4;
wire ap_block_pp0_stage1_flag00000000;
reg [9:0] indvar_flatten_phi_fu_401_p4;
reg [4:0] row_b_phi_fu_413_p4;
reg [4:0] col_b_phi_fu_425_p4;
wire [63:0] tmp_629_cast_fu_1278_p1;
wire ap_block_pp0_stage3_flag00000000;
wire [63:0] tmp_621_cast_fu_1293_p1;
wire ap_block_pp0_stage4_flag00000000;
wire [63:0] tmp_647_cast_fu_1348_p1;
wire [63:0] tmp_622_cast_fu_1391_p1;
wire ap_block_pp0_stage5_flag00000000;
wire [63:0] tmp_623_cast_fu_1414_p1;
wire ap_block_pp0_stage6_flag00000000;
wire [63:0] tmp_624_cast_fu_1625_p1;
wire ap_block_pp0_stage7_flag00000000;
wire [63:0] tmp_649_cast_fu_1635_p1;
wire [63:0] tmp_625_cast_fu_1648_p1;
wire ap_block_pp0_stage8_flag00000000;
wire [63:0] tmp_626_cast_fu_1825_p1;
wire ap_block_pp0_stage9_flag00000000;
wire [63:0] tmp_627_cast_fu_1941_p1;
wire ap_block_pp0_stage10_flag00000000;
wire [63:0] tmp_628_cast_fu_2059_p1;
wire ap_block_pp0_stage11_flag00000000;
wire [63:0] tmp_630_cast_fu_2176_p1;
wire ap_block_pp0_stage12_flag00000000;
wire [63:0] tmp_631_cast_fu_2292_p1;
wire ap_block_pp0_stage13_flag00000000;
wire [63:0] tmp_632_cast_fu_2408_p1;
wire ap_block_pp0_stage14_flag00000000;
wire [63:0] tmp_633_cast_fu_2588_p1;
wire ap_block_pp0_stage15_flag00000000;
wire [63:0] tmp_634_cast_fu_2709_p1;
wire [63:0] tmp_635_cast_fu_2825_p1;
wire [63:0] tmp_636_cast_fu_2916_p1;
wire ap_block_pp0_stage2_flag00000000;
reg [31:0] bufw_Addr_A_orig;
reg [31:0] bufo_Addr_A_orig;
wire [31:0] bufi_Addr_A_orig;
reg [31:0] grp_fu_433_p0;
reg [31:0] grp_fu_433_p1;
reg [31:0] grp_fu_437_p0;
reg [31:0] grp_fu_437_p1;
reg [31:0] grp_fu_441_p0;
reg [31:0] grp_fu_441_p1;
reg [31:0] grp_fu_445_p0;
reg [31:0] grp_fu_445_p1;
reg [31:0] grp_fu_449_p0;
reg [31:0] grp_fu_449_p1;
reg [31:0] grp_fu_453_p0;
reg [31:0] grp_fu_453_p1;
reg [31:0] grp_fu_457_p0;
reg [31:0] grp_fu_457_p1;
reg [31:0] grp_fu_461_p0;
reg [31:0] grp_fu_461_p1;
reg [31:0] grp_fu_465_p0;
reg [31:0] grp_fu_465_p1;
reg [31:0] grp_fu_469_p0;
reg [31:0] grp_fu_469_p1;
reg [31:0] grp_fu_473_p0;
reg [31:0] grp_fu_473_p1;
reg [31:0] grp_fu_477_p0;
reg [31:0] grp_fu_477_p1;
reg [31:0] grp_fu_481_p0;
reg [31:0] grp_fu_481_p1;
reg [31:0] grp_fu_485_p0;
reg [31:0] grp_fu_485_p1;
reg [31:0] grp_fu_489_p0;
reg [31:0] grp_fu_489_p1;
reg [31:0] grp_fu_493_p0;
reg [31:0] grp_fu_493_p1;
reg [31:0] grp_fu_497_p0;
reg [31:0] grp_fu_497_p1;
reg [31:0] grp_fu_501_p0;
reg [31:0] grp_fu_501_p1;
reg [31:0] grp_fu_505_p0;
reg [31:0] grp_fu_505_p1;
reg [31:0] grp_fu_509_p0;
reg [31:0] grp_fu_509_p1;
reg [31:0] grp_fu_513_p0;
reg [31:0] grp_fu_513_p1;
reg [31:0] grp_fu_517_p0;
reg [31:0] grp_fu_517_p1;
reg [31:0] grp_fu_521_p0;
reg [31:0] grp_fu_521_p1;
reg [31:0] grp_fu_525_p0;
reg [31:0] grp_fu_525_p1;
reg [31:0] grp_fu_529_p0;
reg [31:0] grp_fu_529_p1;
reg [31:0] grp_fu_533_p0;
reg [31:0] grp_fu_533_p1;
reg [31:0] grp_fu_537_p0;
reg [31:0] grp_fu_537_p1;
reg [31:0] grp_fu_541_p0;
reg [31:0] grp_fu_541_p1;
reg [31:0] grp_fu_545_p0;
reg [31:0] grp_fu_545_p1;
reg [31:0] grp_fu_549_p0;
reg [31:0] grp_fu_549_p1;
reg [31:0] grp_fu_553_p0;
reg [31:0] grp_fu_553_p1;
reg [31:0] grp_fu_557_p0;
reg [31:0] grp_fu_557_p1;
wire [4:0] tmp_fu_1035_p2;
wire [5:0] tmp_1_cast_fu_1031_p1;
wire [5:0] tmp_7_cast_fu_1041_p1;
wire [0:0] not_exitcond_flatten_fu_1107_p2;
wire [0:0] exitcond_flatten_not_fu_1128_p2;
wire [0:0] tmp_9_mid_fu_1112_p2;
wire [0:0] not_exitcond_flatten_1_fu_1133_p2;
wire [4:0] tmp_1_fu_1159_p3;
wire [5:0] p_shl4_cast_fu_1166_p1;
wire [9:0] p_shl3_cast_fu_1183_p4;
wire [9:0] tmp_611_cast_fu_1176_p3;
wire [5:0] tmp_8_cast_mid_cast_fu_1198_p1;
wire [0:0] tmp_39_fu_1207_p2;
wire [9:0] tmp_4_mid2_cast2_fu_1224_p1;
wire [9:0] tmp_11_fu_1192_p2;
wire [5:0] tmp_8_cast_mid3_fu_1201_p3;
wire [0:0] tmp_615_fu_1241_p2;
wire [0:0] tmp_616_fu_1245_p2;
wire [6:0] tmp_5_cast_fu_1287_p1;
wire [4:0] p_v_fu_1303_p3;
wire [8:0] tmp_617_fu_1308_p3;
wire [4:0] tmp_618_fu_1320_p2;
wire [5:0] tmp_7_cast_mid1_fu_1325_p1;
wire [9:0] col_b_cast1_cast_fu_1339_p1;
wire [9:0] tmp_642_cast_fu_1316_p1;
wire [9:0] tmp_622_fu_1342_p2;
wire [4:0] tmp_623_fu_1353_p2;
wire [5:0] tmp_cast_fu_1358_p1;
wire [6:0] tmp_2_cast_fu_1376_p1;
wire [6:0] tmp_6_fu_1379_p2;
wire [6:0] tmp_s_fu_1385_p2;
wire [10:0] tmp_619_fu_1418_p3;
wire [7:0] tmp_620_fu_1429_p3;
wire [11:0] p_shl_cast_fu_1425_p1;
wire [11:0] p_shl2_cast_fu_1436_p1;
wire [11:0] tmp_3_cast_cast_fu_1446_p1;
wire [11:0] tmp_621_fu_1440_p2;
wire [7:0] tmp_4_fu_1616_p2;
wire [7:0] tmp_7_fu_1643_p2;
wire [7:0] tmp_9_fu_1815_p2;
wire [7:0] tmp_10_fu_1820_p2;
wire [8:0] tmp_13_fu_2050_p2;
wire [8:0] tmp_15_fu_2171_p2;
wire [8:0] tmp_17_fu_2287_p2;
wire [8:0] tmp_19_fu_2403_p2;
wire [8:0] tmp_23_fu_2583_p2;
wire [8:0] tmp_27_fu_2699_p2;
wire [8:0] tmp_31_fu_2704_p2;
wire [31:0] tmp_605_fu_3629_p1;
wire [31:0] tmp_570_fu_3625_p1;
wire [31:0] tmp_535_fu_3621_p1;
wire [31:0] tmp_500_fu_3617_p1;
wire [31:0] tmp_465_fu_3613_p1;
wire [31:0] tmp_430_fu_3609_p1;
wire [31:0] tmp_395_fu_3605_p1;
wire [31:0] tmp_360_fu_3601_p1;
wire [31:0] tmp_325_fu_3597_p1;
wire [31:0] tmp_290_fu_3593_p1;
wire [31:0] tmp_255_fu_3589_p1;
wire [31:0] tmp_220_fu_3585_p1;
wire [31:0] tmp_185_fu_3581_p1;
wire [31:0] tmp_150_fu_3577_p1;
wire [31:0] tmp_114_fu_3573_p1;
wire [31:0] tmp_79_fu_3569_p1;
wire ap_CS_fsm_state161;
reg [17:0] ap_NS_fsm;
wire ap_block_pp0_stage1_flag00011011;
wire ap_block_pp0_stage2_flag00011011;
wire ap_block_pp0_stage3_flag00011011;
wire ap_block_pp0_stage4_flag00011011;
wire ap_block_pp0_stage5_flag00011011;
wire ap_block_pp0_stage6_flag00011011;
wire ap_block_pp0_stage7_flag00011011;
wire ap_block_pp0_stage8_flag00011011;
wire ap_block_pp0_stage9_flag00011011;
wire ap_block_pp0_stage10_flag00011011;
wire ap_block_pp0_stage11_flag00011011;
wire ap_block_pp0_stage12_flag00011011;
wire ap_block_pp0_stage13_flag00011011;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 18'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
end
convolve_kernel_control_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CONTROL_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CONTROL_DATA_WIDTH ))
convolve_kernel_control_s_axi_U(
.AWVALID(s_axi_control_AWVALID),
.AWREADY(s_axi_control_AWREADY),
.AWADDR(s_axi_control_AWADDR),
.WVALID(s_axi_control_WVALID),
.WREADY(s_axi_control_WREADY),
.WDATA(s_axi_control_WDATA),
.WSTRB(s_axi_control_WSTRB),
.ARVALID(s_axi_control_ARVALID),
.ARREADY(s_axi_control_ARREADY),
.ARADDR(s_axi_control_ARADDR),
.RVALID(s_axi_control_RVALID),
.RREADY(s_axi_control_RREADY),
.RDATA(s_axi_control_RDATA),
.RRESP(s_axi_control_RRESP),
.BVALID(s_axi_control_BVALID),
.BREADY(s_axi_control_BREADY),
.BRESP(s_axi_control_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U1(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_433_p0),
.din1(grp_fu_433_p1),
.ce(1'b1),
.dout(grp_fu_433_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U2(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_437_p0),
.din1(grp_fu_437_p1),
.ce(1'b1),
.dout(grp_fu_437_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U3(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_441_p0),
.din1(grp_fu_441_p1),
.ce(1'b1),
.dout(grp_fu_441_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U4(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_445_p0),
.din1(grp_fu_445_p1),
.ce(1'b1),
.dout(grp_fu_445_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U5(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_449_p0),
.din1(grp_fu_449_p1),
.ce(1'b1),
.dout(grp_fu_449_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U6(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_453_p0),
.din1(grp_fu_453_p1),
.ce(1'b1),
.dout(grp_fu_453_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U7(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_457_p0),
.din1(grp_fu_457_p1),
.ce(1'b1),
.dout(grp_fu_457_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U8(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_461_p0),
.din1(grp_fu_461_p1),
.ce(1'b1),
.dout(grp_fu_461_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U9(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_465_p0),
.din1(grp_fu_465_p1),
.ce(1'b1),
.dout(grp_fu_465_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U10(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_469_p0),
.din1(grp_fu_469_p1),
.ce(1'b1),
.dout(grp_fu_469_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U11(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_473_p0),
.din1(grp_fu_473_p1),
.ce(1'b1),
.dout(grp_fu_473_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U12(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_477_p0),
.din1(grp_fu_477_p1),
.ce(1'b1),
.dout(grp_fu_477_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U13(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_481_p0),
.din1(grp_fu_481_p1),
.ce(1'b1),
.dout(grp_fu_481_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U14(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_485_p0),
.din1(grp_fu_485_p1),
.ce(1'b1),
.dout(grp_fu_485_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U15(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_489_p0),
.din1(grp_fu_489_p1),
.ce(1'b1),
.dout(grp_fu_489_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U16(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_493_p0),
.din1(grp_fu_493_p1),
.ce(1'b1),
.dout(grp_fu_493_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U17(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_497_p0),
.din1(grp_fu_497_p1),
.ce(1'b1),
.dout(grp_fu_497_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U18(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_501_p0),
.din1(grp_fu_501_p1),
.ce(1'b1),
.dout(grp_fu_501_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U19(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_505_p0),
.din1(grp_fu_505_p1),
.ce(1'b1),
.dout(grp_fu_505_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U20(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_509_p0),
.din1(grp_fu_509_p1),
.ce(1'b1),
.dout(grp_fu_509_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U21(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_513_p0),
.din1(grp_fu_513_p1),
.ce(1'b1),
.dout(grp_fu_513_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U22(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_517_p0),
.din1(grp_fu_517_p1),
.ce(1'b1),
.dout(grp_fu_517_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U23(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_521_p0),
.din1(grp_fu_521_p1),
.ce(1'b1),
.dout(grp_fu_521_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U24(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_525_p0),
.din1(grp_fu_525_p1),
.ce(1'b1),
.dout(grp_fu_525_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U25(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_529_p0),
.din1(grp_fu_529_p1),
.ce(1'b1),
.dout(grp_fu_529_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U26(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_533_p0),
.din1(grp_fu_533_p1),
.ce(1'b1),
.dout(grp_fu_533_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U27(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_537_p0),
.din1(grp_fu_537_p1),
.ce(1'b1),
.dout(grp_fu_537_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U28(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_541_p0),
.din1(grp_fu_541_p1),
.ce(1'b1),
.dout(grp_fu_541_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U29(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_545_p0),
.din1(grp_fu_545_p1),
.ce(1'b1),
.dout(grp_fu_545_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U30(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_549_p0),
.din1(grp_fu_549_p1),
.ce(1'b1),
.dout(grp_fu_549_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U31(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_553_p0),
.din1(grp_fu_553_p1),
.ce(1'b1),
.dout(grp_fu_553_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U32(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_557_p0),
.din1(grp_fu_557_p1),
.ce(1'b1),
.dout(grp_fu_557_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 ^ 1'b1);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011011 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011011 == 1'b0)))) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
col_b_reg_421 <= col_b_1_reg_3957;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
col_b_reg_421 <= 5'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
i_reg_362 <= tmp_1_mid2_v_reg_3722;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
i_reg_362 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
indvar_flatten1_reg_351 <= indvar_flatten_next2_reg_3679;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten1_reg_351 <= 13'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
indvar_flatten2_reg_374 <= indvar_flatten_next1_reg_3757;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten2_reg_374 <= 12'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
indvar_flatten_reg_397 <= indvar_flatten_next_reg_3809;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten_reg_397 <= 10'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
j_reg_385 <= tmp_4_mid2_reg_3783;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
j_reg_385 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
row_b_reg_409 <= row_b_mid2_reg_3862;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
row_b_reg_409 <= 5'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_bufo_addr_reg_3867 <= bufo_addr_reg_3867;
ap_reg_pp0_iter2_bufo_addr_reg_3867 <= ap_reg_pp0_iter1_bufo_addr_reg_3867;
ap_reg_pp0_iter2_tmp_11_0_7_reg_6347 <= tmp_11_0_7_reg_6347;
ap_reg_pp0_iter2_tmp_11_10_7_reg_6467 <= tmp_11_10_7_reg_6467;
ap_reg_pp0_iter2_tmp_11_11_7_reg_6477 <= tmp_11_11_7_reg_6477;
ap_reg_pp0_iter2_tmp_11_12_7_reg_6487 <= tmp_11_12_7_reg_6487;
ap_reg_pp0_iter2_tmp_11_13_7_reg_6497 <= tmp_11_13_7_reg_6497;
ap_reg_pp0_iter2_tmp_11_14_7_reg_6507 <= tmp_11_14_7_reg_6507;
ap_reg_pp0_iter2_tmp_11_15_7_reg_6517 <= tmp_11_15_7_reg_6517;
ap_reg_pp0_iter2_tmp_11_1_7_reg_6377 <= tmp_11_1_7_reg_6377;
ap_reg_pp0_iter2_tmp_11_2_7_reg_6387 <= tmp_11_2_7_reg_6387;
ap_reg_pp0_iter2_tmp_11_3_7_reg_6397 <= tmp_11_3_7_reg_6397;
ap_reg_pp0_iter2_tmp_11_4_7_reg_6407 <= tmp_11_4_7_reg_6407;
ap_reg_pp0_iter2_tmp_11_5_7_reg_6417 <= tmp_11_5_7_reg_6417;
ap_reg_pp0_iter2_tmp_11_6_7_reg_6427 <= tmp_11_6_7_reg_6427;
ap_reg_pp0_iter2_tmp_11_7_7_reg_6437 <= tmp_11_7_7_reg_6437;
ap_reg_pp0_iter2_tmp_11_8_7_reg_6447 <= tmp_11_8_7_reg_6447;
ap_reg_pp0_iter2_tmp_11_9_7_reg_6457 <= tmp_11_9_7_reg_6457;
ap_reg_pp0_iter3_bufo_addr_reg_3867 <= ap_reg_pp0_iter2_bufo_addr_reg_3867;
ap_reg_pp0_iter3_tmp_11_0_7_reg_6347 <= ap_reg_pp0_iter2_tmp_11_0_7_reg_6347;
ap_reg_pp0_iter3_tmp_11_10_7_reg_6467 <= ap_reg_pp0_iter2_tmp_11_10_7_reg_6467;
ap_reg_pp0_iter3_tmp_11_11_7_reg_6477 <= ap_reg_pp0_iter2_tmp_11_11_7_reg_6477;
ap_reg_pp0_iter3_tmp_11_12_7_reg_6487 <= ap_reg_pp0_iter2_tmp_11_12_7_reg_6487;
ap_reg_pp0_iter3_tmp_11_13_7_reg_6497 <= ap_reg_pp0_iter2_tmp_11_13_7_reg_6497;
ap_reg_pp0_iter3_tmp_11_14_7_reg_6507 <= ap_reg_pp0_iter2_tmp_11_14_7_reg_6507;
ap_reg_pp0_iter3_tmp_11_15_7_reg_6517 <= ap_reg_pp0_iter2_tmp_11_15_7_reg_6517;
ap_reg_pp0_iter3_tmp_11_1_7_reg_6377 <= ap_reg_pp0_iter2_tmp_11_1_7_reg_6377;
ap_reg_pp0_iter3_tmp_11_2_7_reg_6387 <= ap_reg_pp0_iter2_tmp_11_2_7_reg_6387;
ap_reg_pp0_iter3_tmp_11_3_7_reg_6397 <= ap_reg_pp0_iter2_tmp_11_3_7_reg_6397;
ap_reg_pp0_iter3_tmp_11_4_7_reg_6407 <= ap_reg_pp0_iter2_tmp_11_4_7_reg_6407;
ap_reg_pp0_iter3_tmp_11_5_7_reg_6417 <= ap_reg_pp0_iter2_tmp_11_5_7_reg_6417;
ap_reg_pp0_iter3_tmp_11_6_7_reg_6427 <= ap_reg_pp0_iter2_tmp_11_6_7_reg_6427;
ap_reg_pp0_iter3_tmp_11_7_7_reg_6437 <= ap_reg_pp0_iter2_tmp_11_7_7_reg_6437;
ap_reg_pp0_iter3_tmp_11_8_7_reg_6447 <= ap_reg_pp0_iter2_tmp_11_8_7_reg_6447;
ap_reg_pp0_iter3_tmp_11_9_7_reg_6457 <= ap_reg_pp0_iter2_tmp_11_9_7_reg_6457;
ap_reg_pp0_iter4_bufo_addr_reg_3867 <= ap_reg_pp0_iter3_bufo_addr_reg_3867;
ap_reg_pp0_iter4_tmp_11_0_7_reg_6347 <= ap_reg_pp0_iter3_tmp_11_0_7_reg_6347;
ap_reg_pp0_iter4_tmp_11_10_7_reg_6467 <= ap_reg_pp0_iter3_tmp_11_10_7_reg_6467;
ap_reg_pp0_iter4_tmp_11_11_7_reg_6477 <= ap_reg_pp0_iter3_tmp_11_11_7_reg_6477;
ap_reg_pp0_iter4_tmp_11_12_7_reg_6487 <= ap_reg_pp0_iter3_tmp_11_12_7_reg_6487;
ap_reg_pp0_iter4_tmp_11_13_7_reg_6497 <= ap_reg_pp0_iter3_tmp_11_13_7_reg_6497;
ap_reg_pp0_iter4_tmp_11_14_7_reg_6507 <= ap_reg_pp0_iter3_tmp_11_14_7_reg_6507;
ap_reg_pp0_iter4_tmp_11_15_7_reg_6517 <= ap_reg_pp0_iter3_tmp_11_15_7_reg_6517;
ap_reg_pp0_iter4_tmp_11_1_7_reg_6377 <= ap_reg_pp0_iter3_tmp_11_1_7_reg_6377;
ap_reg_pp0_iter4_tmp_11_2_7_reg_6387 <= ap_reg_pp0_iter3_tmp_11_2_7_reg_6387;
ap_reg_pp0_iter4_tmp_11_3_7_reg_6397 <= ap_reg_pp0_iter3_tmp_11_3_7_reg_6397;
ap_reg_pp0_iter4_tmp_11_4_7_reg_6407 <= ap_reg_pp0_iter3_tmp_11_4_7_reg_6407;
ap_reg_pp0_iter4_tmp_11_5_7_reg_6417 <= ap_reg_pp0_iter3_tmp_11_5_7_reg_6417;
ap_reg_pp0_iter4_tmp_11_6_7_reg_6427 <= ap_reg_pp0_iter3_tmp_11_6_7_reg_6427;
ap_reg_pp0_iter4_tmp_11_7_7_reg_6437 <= ap_reg_pp0_iter3_tmp_11_7_7_reg_6437;
ap_reg_pp0_iter4_tmp_11_8_7_reg_6447 <= ap_reg_pp0_iter3_tmp_11_8_7_reg_6447;
ap_reg_pp0_iter4_tmp_11_9_7_reg_6457 <= ap_reg_pp0_iter3_tmp_11_9_7_reg_6457;
ap_reg_pp0_iter5_bufo_addr_reg_3867 <= ap_reg_pp0_iter4_bufo_addr_reg_3867;
ap_reg_pp0_iter6_bufo_addr_reg_3867 <= ap_reg_pp0_iter5_bufo_addr_reg_3867;
ap_reg_pp0_iter7_bufo_addr_reg_3867 <= ap_reg_pp0_iter6_bufo_addr_reg_3867;
ap_reg_pp0_iter8_bufo_addr_reg_3867 <= ap_reg_pp0_iter7_bufo_addr_reg_3867;
ap_reg_pp0_iter9_bufo_addr_reg_3867 <= ap_reg_pp0_iter8_bufo_addr_reg_3867;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_exitcond_flatten2_reg_3675 <= exitcond_flatten2_reg_3675;
ap_reg_pp0_iter2_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter1_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter2_tmp_11_0_3_reg_5372 <= tmp_11_0_3_reg_5372;
ap_reg_pp0_iter2_tmp_11_10_3_reg_5497 <= tmp_11_10_3_reg_5497;
ap_reg_pp0_iter2_tmp_11_11_3_reg_5507 <= tmp_11_11_3_reg_5507;
ap_reg_pp0_iter2_tmp_11_12_3_reg_5517 <= tmp_11_12_3_reg_5517;
ap_reg_pp0_iter2_tmp_11_13_3_reg_5527 <= tmp_11_13_3_reg_5527;
ap_reg_pp0_iter2_tmp_11_14_3_reg_5537 <= tmp_11_14_3_reg_5537;
ap_reg_pp0_iter2_tmp_11_15_3_reg_5547 <= tmp_11_15_3_reg_5547;
ap_reg_pp0_iter2_tmp_11_1_3_reg_5407 <= tmp_11_1_3_reg_5407;
ap_reg_pp0_iter2_tmp_11_2_3_reg_5417 <= tmp_11_2_3_reg_5417;
ap_reg_pp0_iter2_tmp_11_3_3_reg_5427 <= tmp_11_3_3_reg_5427;
ap_reg_pp0_iter2_tmp_11_4_3_reg_5437 <= tmp_11_4_3_reg_5437;
ap_reg_pp0_iter2_tmp_11_5_3_reg_5447 <= tmp_11_5_3_reg_5447;
ap_reg_pp0_iter2_tmp_11_6_3_reg_5457 <= tmp_11_6_3_reg_5457;
ap_reg_pp0_iter2_tmp_11_7_3_reg_5467 <= tmp_11_7_3_reg_5467;
ap_reg_pp0_iter2_tmp_11_8_3_reg_5477 <= tmp_11_8_3_reg_5477;
ap_reg_pp0_iter2_tmp_11_9_3_reg_5487 <= tmp_11_9_3_reg_5487;
ap_reg_pp0_iter3_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter2_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter4_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter3_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter5_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter4_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter6_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter5_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter7_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter6_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter8_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter7_exitcond_flatten2_reg_3675;
ap_reg_pp0_iter9_exitcond_flatten2_reg_3675 <= ap_reg_pp0_iter8_exitcond_flatten2_reg_3675;
exitcond_flatten2_reg_3675 <= exitcond_flatten2_fu_1051_p2;
tmp_8_reg_3670 <= tmp_8_fu_1045_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_tmp_11_0_2_reg_5172 <= tmp_11_0_2_reg_5172;
ap_reg_pp0_iter1_tmp_11_10_2_reg_5297 <= tmp_11_10_2_reg_5297;
ap_reg_pp0_iter1_tmp_11_11_2_reg_5307 <= tmp_11_11_2_reg_5307;
ap_reg_pp0_iter1_tmp_11_12_2_reg_5317 <= tmp_11_12_2_reg_5317;
ap_reg_pp0_iter1_tmp_11_13_2_reg_5327 <= tmp_11_13_2_reg_5327;
ap_reg_pp0_iter1_tmp_11_14_2_reg_5337 <= tmp_11_14_2_reg_5337;
ap_reg_pp0_iter1_tmp_11_15_2_reg_5347 <= tmp_11_15_2_reg_5347;
ap_reg_pp0_iter1_tmp_11_1_2_reg_5207 <= tmp_11_1_2_reg_5207;
ap_reg_pp0_iter1_tmp_11_2_2_reg_5217 <= tmp_11_2_2_reg_5217;
ap_reg_pp0_iter1_tmp_11_3_2_reg_5227 <= tmp_11_3_2_reg_5227;
ap_reg_pp0_iter1_tmp_11_4_2_reg_5237 <= tmp_11_4_2_reg_5237;
ap_reg_pp0_iter1_tmp_11_5_2_reg_5247 <= tmp_11_5_2_reg_5247;
ap_reg_pp0_iter1_tmp_11_6_2_reg_5257 <= tmp_11_6_2_reg_5257;
ap_reg_pp0_iter1_tmp_11_7_2_reg_5267 <= tmp_11_7_2_reg_5267;
ap_reg_pp0_iter1_tmp_11_8_2_reg_5277 <= tmp_11_8_2_reg_5277;
ap_reg_pp0_iter1_tmp_11_9_2_reg_5287 <= tmp_11_9_2_reg_5287;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_10_reg_7147 <= tmp_11_0_10_reg_7147;
ap_reg_pp0_iter2_tmp_11_10_10_reg_7267 <= tmp_11_10_10_reg_7267;
ap_reg_pp0_iter2_tmp_11_11_10_reg_7277 <= tmp_11_11_10_reg_7277;
ap_reg_pp0_iter2_tmp_11_12_10_reg_7287 <= tmp_11_12_10_reg_7287;
ap_reg_pp0_iter2_tmp_11_13_10_reg_7297 <= tmp_11_13_10_reg_7297;
ap_reg_pp0_iter2_tmp_11_14_10_reg_7307 <= tmp_11_14_10_reg_7307;
ap_reg_pp0_iter2_tmp_11_15_10_reg_7317 <= tmp_11_15_10_reg_7317;
ap_reg_pp0_iter2_tmp_11_1_10_reg_7177 <= tmp_11_1_10_reg_7177;
ap_reg_pp0_iter2_tmp_11_2_10_reg_7187 <= tmp_11_2_10_reg_7187;
ap_reg_pp0_iter2_tmp_11_3_10_reg_7197 <= tmp_11_3_10_reg_7197;
ap_reg_pp0_iter2_tmp_11_4_10_reg_7207 <= tmp_11_4_10_reg_7207;
ap_reg_pp0_iter2_tmp_11_5_10_reg_7217 <= tmp_11_5_10_reg_7217;
ap_reg_pp0_iter2_tmp_11_6_10_reg_7227 <= tmp_11_6_10_reg_7227;
ap_reg_pp0_iter2_tmp_11_7_10_reg_7237 <= tmp_11_7_10_reg_7237;
ap_reg_pp0_iter2_tmp_11_8_10_reg_7247 <= tmp_11_8_10_reg_7247;
ap_reg_pp0_iter2_tmp_11_9_10_reg_7257 <= tmp_11_9_10_reg_7257;
ap_reg_pp0_iter3_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter2_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter3_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter2_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter3_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter2_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter3_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter2_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter3_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter2_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter3_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter2_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter3_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter2_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter3_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter2_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter3_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter2_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter3_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter2_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter3_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter2_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter3_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter2_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter3_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter2_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter3_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter2_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter3_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter2_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter3_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter2_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter4_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter3_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter4_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter3_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter4_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter3_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter4_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter3_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter4_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter3_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter4_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter3_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter4_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter3_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter4_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter3_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter4_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter3_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter4_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter3_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter4_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter3_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter4_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter3_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter4_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter3_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter4_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter3_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter4_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter3_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter4_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter3_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter5_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter4_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter5_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter4_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter5_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter4_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter5_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter4_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter5_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter4_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter5_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter4_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter5_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter4_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter5_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter4_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter5_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter4_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter5_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter4_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter5_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter4_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter5_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter4_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter5_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter4_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter5_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter4_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter5_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter4_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter5_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter4_tmp_11_9_10_reg_7257;
ap_reg_pp0_iter6_tmp_11_0_10_reg_7147 <= ap_reg_pp0_iter5_tmp_11_0_10_reg_7147;
ap_reg_pp0_iter6_tmp_11_10_10_reg_7267 <= ap_reg_pp0_iter5_tmp_11_10_10_reg_7267;
ap_reg_pp0_iter6_tmp_11_11_10_reg_7277 <= ap_reg_pp0_iter5_tmp_11_11_10_reg_7277;
ap_reg_pp0_iter6_tmp_11_12_10_reg_7287 <= ap_reg_pp0_iter5_tmp_11_12_10_reg_7287;
ap_reg_pp0_iter6_tmp_11_13_10_reg_7297 <= ap_reg_pp0_iter5_tmp_11_13_10_reg_7297;
ap_reg_pp0_iter6_tmp_11_14_10_reg_7307 <= ap_reg_pp0_iter5_tmp_11_14_10_reg_7307;
ap_reg_pp0_iter6_tmp_11_15_10_reg_7317 <= ap_reg_pp0_iter5_tmp_11_15_10_reg_7317;
ap_reg_pp0_iter6_tmp_11_1_10_reg_7177 <= ap_reg_pp0_iter5_tmp_11_1_10_reg_7177;
ap_reg_pp0_iter6_tmp_11_2_10_reg_7187 <= ap_reg_pp0_iter5_tmp_11_2_10_reg_7187;
ap_reg_pp0_iter6_tmp_11_3_10_reg_7197 <= ap_reg_pp0_iter5_tmp_11_3_10_reg_7197;
ap_reg_pp0_iter6_tmp_11_4_10_reg_7207 <= ap_reg_pp0_iter5_tmp_11_4_10_reg_7207;
ap_reg_pp0_iter6_tmp_11_5_10_reg_7217 <= ap_reg_pp0_iter5_tmp_11_5_10_reg_7217;
ap_reg_pp0_iter6_tmp_11_6_10_reg_7227 <= ap_reg_pp0_iter5_tmp_11_6_10_reg_7227;
ap_reg_pp0_iter6_tmp_11_7_10_reg_7237 <= ap_reg_pp0_iter5_tmp_11_7_10_reg_7237;
ap_reg_pp0_iter6_tmp_11_8_10_reg_7247 <= ap_reg_pp0_iter5_tmp_11_8_10_reg_7247;
ap_reg_pp0_iter6_tmp_11_9_10_reg_7257 <= ap_reg_pp0_iter5_tmp_11_9_10_reg_7257;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_11_reg_7327 <= tmp_11_0_11_reg_7327;
ap_reg_pp0_iter2_tmp_11_10_11_reg_7377 <= tmp_11_10_11_reg_7377;
ap_reg_pp0_iter2_tmp_11_11_11_reg_7382 <= tmp_11_11_11_reg_7382;
ap_reg_pp0_iter2_tmp_11_12_11_reg_7387 <= tmp_11_12_11_reg_7387;
ap_reg_pp0_iter2_tmp_11_13_11_reg_7392 <= tmp_11_13_11_reg_7392;
ap_reg_pp0_iter2_tmp_11_14_11_reg_7397 <= tmp_11_14_11_reg_7397;
ap_reg_pp0_iter2_tmp_11_15_11_reg_7402 <= tmp_11_15_11_reg_7402;
ap_reg_pp0_iter2_tmp_11_1_11_reg_7332 <= tmp_11_1_11_reg_7332;
ap_reg_pp0_iter2_tmp_11_2_11_reg_7337 <= tmp_11_2_11_reg_7337;
ap_reg_pp0_iter2_tmp_11_3_11_reg_7342 <= tmp_11_3_11_reg_7342;
ap_reg_pp0_iter2_tmp_11_4_11_reg_7347 <= tmp_11_4_11_reg_7347;
ap_reg_pp0_iter2_tmp_11_5_11_reg_7352 <= tmp_11_5_11_reg_7352;
ap_reg_pp0_iter2_tmp_11_6_11_reg_7357 <= tmp_11_6_11_reg_7357;
ap_reg_pp0_iter2_tmp_11_7_11_reg_7362 <= tmp_11_7_11_reg_7362;
ap_reg_pp0_iter2_tmp_11_8_11_reg_7367 <= tmp_11_8_11_reg_7367;
ap_reg_pp0_iter2_tmp_11_9_11_reg_7372 <= tmp_11_9_11_reg_7372;
ap_reg_pp0_iter3_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter2_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter3_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter2_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter3_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter2_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter3_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter2_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter3_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter2_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter3_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter2_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter3_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter2_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter3_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter2_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter3_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter2_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter3_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter2_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter3_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter2_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter3_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter2_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter3_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter2_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter3_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter2_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter3_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter2_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter3_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter2_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter4_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter3_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter4_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter3_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter4_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter3_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter4_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter3_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter4_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter3_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter4_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter3_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter4_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter3_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter4_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter3_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter4_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter3_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter4_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter3_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter4_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter3_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter4_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter3_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter4_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter3_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter4_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter3_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter4_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter3_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter4_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter3_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter5_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter4_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter5_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter4_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter5_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter4_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter5_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter4_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter5_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter4_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter5_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter4_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter5_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter4_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter5_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter4_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter5_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter4_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter5_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter4_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter5_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter4_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter5_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter4_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter5_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter4_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter5_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter4_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter5_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter4_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter5_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter4_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter6_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter5_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter6_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter5_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter6_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter5_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter6_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter5_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter6_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter5_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter6_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter5_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter6_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter5_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter6_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter5_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter6_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter5_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter6_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter5_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter6_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter5_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter6_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter5_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter6_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter5_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter6_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter5_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter6_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter5_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter6_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter5_tmp_11_9_11_reg_7372;
ap_reg_pp0_iter7_tmp_11_0_11_reg_7327 <= ap_reg_pp0_iter6_tmp_11_0_11_reg_7327;
ap_reg_pp0_iter7_tmp_11_10_11_reg_7377 <= ap_reg_pp0_iter6_tmp_11_10_11_reg_7377;
ap_reg_pp0_iter7_tmp_11_11_11_reg_7382 <= ap_reg_pp0_iter6_tmp_11_11_11_reg_7382;
ap_reg_pp0_iter7_tmp_11_12_11_reg_7387 <= ap_reg_pp0_iter6_tmp_11_12_11_reg_7387;
ap_reg_pp0_iter7_tmp_11_13_11_reg_7392 <= ap_reg_pp0_iter6_tmp_11_13_11_reg_7392;
ap_reg_pp0_iter7_tmp_11_14_11_reg_7397 <= ap_reg_pp0_iter6_tmp_11_14_11_reg_7397;
ap_reg_pp0_iter7_tmp_11_15_11_reg_7402 <= ap_reg_pp0_iter6_tmp_11_15_11_reg_7402;
ap_reg_pp0_iter7_tmp_11_1_11_reg_7332 <= ap_reg_pp0_iter6_tmp_11_1_11_reg_7332;
ap_reg_pp0_iter7_tmp_11_2_11_reg_7337 <= ap_reg_pp0_iter6_tmp_11_2_11_reg_7337;
ap_reg_pp0_iter7_tmp_11_3_11_reg_7342 <= ap_reg_pp0_iter6_tmp_11_3_11_reg_7342;
ap_reg_pp0_iter7_tmp_11_4_11_reg_7347 <= ap_reg_pp0_iter6_tmp_11_4_11_reg_7347;
ap_reg_pp0_iter7_tmp_11_5_11_reg_7352 <= ap_reg_pp0_iter6_tmp_11_5_11_reg_7352;
ap_reg_pp0_iter7_tmp_11_6_11_reg_7357 <= ap_reg_pp0_iter6_tmp_11_6_11_reg_7357;
ap_reg_pp0_iter7_tmp_11_7_11_reg_7362 <= ap_reg_pp0_iter6_tmp_11_7_11_reg_7362;
ap_reg_pp0_iter7_tmp_11_8_11_reg_7367 <= ap_reg_pp0_iter6_tmp_11_8_11_reg_7367;
ap_reg_pp0_iter7_tmp_11_9_11_reg_7372 <= ap_reg_pp0_iter6_tmp_11_9_11_reg_7372;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_12_reg_7407 <= tmp_11_0_12_reg_7407;
ap_reg_pp0_iter2_tmp_11_10_12_reg_7457 <= tmp_11_10_12_reg_7457;
ap_reg_pp0_iter2_tmp_11_11_12_reg_7462 <= tmp_11_11_12_reg_7462;
ap_reg_pp0_iter2_tmp_11_12_12_reg_7467 <= tmp_11_12_12_reg_7467;
ap_reg_pp0_iter2_tmp_11_13_12_reg_7472 <= tmp_11_13_12_reg_7472;
ap_reg_pp0_iter2_tmp_11_14_12_reg_7477 <= tmp_11_14_12_reg_7477;
ap_reg_pp0_iter2_tmp_11_15_12_reg_7482 <= tmp_11_15_12_reg_7482;
ap_reg_pp0_iter2_tmp_11_1_12_reg_7412 <= tmp_11_1_12_reg_7412;
ap_reg_pp0_iter2_tmp_11_2_12_reg_7417 <= tmp_11_2_12_reg_7417;
ap_reg_pp0_iter2_tmp_11_3_12_reg_7422 <= tmp_11_3_12_reg_7422;
ap_reg_pp0_iter2_tmp_11_4_12_reg_7427 <= tmp_11_4_12_reg_7427;
ap_reg_pp0_iter2_tmp_11_5_12_reg_7432 <= tmp_11_5_12_reg_7432;
ap_reg_pp0_iter2_tmp_11_6_12_reg_7437 <= tmp_11_6_12_reg_7437;
ap_reg_pp0_iter2_tmp_11_7_12_reg_7442 <= tmp_11_7_12_reg_7442;
ap_reg_pp0_iter2_tmp_11_8_12_reg_7447 <= tmp_11_8_12_reg_7447;
ap_reg_pp0_iter2_tmp_11_9_12_reg_7452 <= tmp_11_9_12_reg_7452;
ap_reg_pp0_iter3_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter2_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter3_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter2_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter3_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter2_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter3_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter2_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter3_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter2_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter3_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter2_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter3_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter2_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter3_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter2_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter3_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter2_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter3_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter2_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter3_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter2_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter3_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter2_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter3_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter2_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter3_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter2_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter3_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter2_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter3_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter2_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter4_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter3_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter4_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter3_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter4_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter3_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter4_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter3_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter4_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter3_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter4_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter3_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter4_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter3_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter4_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter3_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter4_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter3_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter4_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter3_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter4_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter3_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter4_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter3_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter4_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter3_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter4_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter3_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter4_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter3_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter4_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter3_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter5_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter4_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter5_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter4_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter5_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter4_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter5_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter4_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter5_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter4_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter5_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter4_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter5_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter4_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter5_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter4_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter5_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter4_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter5_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter4_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter5_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter4_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter5_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter4_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter5_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter4_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter5_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter4_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter5_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter4_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter5_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter4_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter6_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter5_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter6_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter5_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter6_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter5_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter6_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter5_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter6_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter5_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter6_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter5_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter6_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter5_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter6_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter5_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter6_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter5_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter6_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter5_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter6_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter5_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter6_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter5_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter6_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter5_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter6_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter5_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter6_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter5_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter6_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter5_tmp_11_9_12_reg_7452;
ap_reg_pp0_iter7_tmp_11_0_12_reg_7407 <= ap_reg_pp0_iter6_tmp_11_0_12_reg_7407;
ap_reg_pp0_iter7_tmp_11_10_12_reg_7457 <= ap_reg_pp0_iter6_tmp_11_10_12_reg_7457;
ap_reg_pp0_iter7_tmp_11_11_12_reg_7462 <= ap_reg_pp0_iter6_tmp_11_11_12_reg_7462;
ap_reg_pp0_iter7_tmp_11_12_12_reg_7467 <= ap_reg_pp0_iter6_tmp_11_12_12_reg_7467;
ap_reg_pp0_iter7_tmp_11_13_12_reg_7472 <= ap_reg_pp0_iter6_tmp_11_13_12_reg_7472;
ap_reg_pp0_iter7_tmp_11_14_12_reg_7477 <= ap_reg_pp0_iter6_tmp_11_14_12_reg_7477;
ap_reg_pp0_iter7_tmp_11_15_12_reg_7482 <= ap_reg_pp0_iter6_tmp_11_15_12_reg_7482;
ap_reg_pp0_iter7_tmp_11_1_12_reg_7412 <= ap_reg_pp0_iter6_tmp_11_1_12_reg_7412;
ap_reg_pp0_iter7_tmp_11_2_12_reg_7417 <= ap_reg_pp0_iter6_tmp_11_2_12_reg_7417;
ap_reg_pp0_iter7_tmp_11_3_12_reg_7422 <= ap_reg_pp0_iter6_tmp_11_3_12_reg_7422;
ap_reg_pp0_iter7_tmp_11_4_12_reg_7427 <= ap_reg_pp0_iter6_tmp_11_4_12_reg_7427;
ap_reg_pp0_iter7_tmp_11_5_12_reg_7432 <= ap_reg_pp0_iter6_tmp_11_5_12_reg_7432;
ap_reg_pp0_iter7_tmp_11_6_12_reg_7437 <= ap_reg_pp0_iter6_tmp_11_6_12_reg_7437;
ap_reg_pp0_iter7_tmp_11_7_12_reg_7442 <= ap_reg_pp0_iter6_tmp_11_7_12_reg_7442;
ap_reg_pp0_iter7_tmp_11_8_12_reg_7447 <= ap_reg_pp0_iter6_tmp_11_8_12_reg_7447;
ap_reg_pp0_iter7_tmp_11_9_12_reg_7452 <= ap_reg_pp0_iter6_tmp_11_9_12_reg_7452;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_13_reg_7487 <= tmp_11_0_13_reg_7487;
ap_reg_pp0_iter2_tmp_11_10_13_reg_7537 <= tmp_11_10_13_reg_7537;
ap_reg_pp0_iter2_tmp_11_11_13_reg_7542 <= tmp_11_11_13_reg_7542;
ap_reg_pp0_iter2_tmp_11_12_13_reg_7547 <= tmp_11_12_13_reg_7547;
ap_reg_pp0_iter2_tmp_11_13_13_reg_7552 <= tmp_11_13_13_reg_7552;
ap_reg_pp0_iter2_tmp_11_14_13_reg_7557 <= tmp_11_14_13_reg_7557;
ap_reg_pp0_iter2_tmp_11_15_13_reg_7562 <= tmp_11_15_13_reg_7562;
ap_reg_pp0_iter2_tmp_11_1_13_reg_7492 <= tmp_11_1_13_reg_7492;
ap_reg_pp0_iter2_tmp_11_2_13_reg_7497 <= tmp_11_2_13_reg_7497;
ap_reg_pp0_iter2_tmp_11_3_13_reg_7502 <= tmp_11_3_13_reg_7502;
ap_reg_pp0_iter2_tmp_11_4_13_reg_7507 <= tmp_11_4_13_reg_7507;
ap_reg_pp0_iter2_tmp_11_5_13_reg_7512 <= tmp_11_5_13_reg_7512;
ap_reg_pp0_iter2_tmp_11_6_13_reg_7517 <= tmp_11_6_13_reg_7517;
ap_reg_pp0_iter2_tmp_11_7_13_reg_7522 <= tmp_11_7_13_reg_7522;
ap_reg_pp0_iter2_tmp_11_8_13_reg_7527 <= tmp_11_8_13_reg_7527;
ap_reg_pp0_iter2_tmp_11_9_13_reg_7532 <= tmp_11_9_13_reg_7532;
ap_reg_pp0_iter3_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter2_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter3_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter2_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter3_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter2_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter3_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter2_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter3_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter2_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter3_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter2_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter3_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter2_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter3_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter2_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter3_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter2_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter3_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter2_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter3_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter2_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter3_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter2_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter3_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter2_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter3_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter2_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter3_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter2_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter3_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter2_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter4_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter3_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter4_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter3_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter4_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter3_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter4_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter3_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter4_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter3_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter4_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter3_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter4_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter3_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter4_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter3_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter4_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter3_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter4_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter3_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter4_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter3_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter4_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter3_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter4_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter3_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter4_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter3_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter4_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter3_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter4_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter3_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter5_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter4_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter5_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter4_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter5_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter4_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter5_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter4_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter5_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter4_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter5_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter4_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter5_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter4_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter5_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter4_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter5_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter4_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter5_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter4_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter5_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter4_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter5_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter4_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter5_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter4_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter5_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter4_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter5_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter4_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter5_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter4_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter6_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter5_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter6_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter5_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter6_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter5_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter6_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter5_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter6_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter5_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter6_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter5_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter6_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter5_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter6_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter5_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter6_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter5_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter6_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter5_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter6_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter5_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter6_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter5_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter6_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter5_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter6_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter5_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter6_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter5_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter6_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter5_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter7_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter6_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter7_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter6_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter7_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter6_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter7_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter6_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter7_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter6_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter7_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter6_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter7_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter6_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter7_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter6_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter7_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter6_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter7_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter6_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter7_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter6_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter7_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter6_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter7_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter6_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter7_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter6_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter7_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter6_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter7_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter6_tmp_11_9_13_reg_7532;
ap_reg_pp0_iter8_tmp_11_0_13_reg_7487 <= ap_reg_pp0_iter7_tmp_11_0_13_reg_7487;
ap_reg_pp0_iter8_tmp_11_10_13_reg_7537 <= ap_reg_pp0_iter7_tmp_11_10_13_reg_7537;
ap_reg_pp0_iter8_tmp_11_11_13_reg_7542 <= ap_reg_pp0_iter7_tmp_11_11_13_reg_7542;
ap_reg_pp0_iter8_tmp_11_12_13_reg_7547 <= ap_reg_pp0_iter7_tmp_11_12_13_reg_7547;
ap_reg_pp0_iter8_tmp_11_13_13_reg_7552 <= ap_reg_pp0_iter7_tmp_11_13_13_reg_7552;
ap_reg_pp0_iter8_tmp_11_14_13_reg_7557 <= ap_reg_pp0_iter7_tmp_11_14_13_reg_7557;
ap_reg_pp0_iter8_tmp_11_15_13_reg_7562 <= ap_reg_pp0_iter7_tmp_11_15_13_reg_7562;
ap_reg_pp0_iter8_tmp_11_1_13_reg_7492 <= ap_reg_pp0_iter7_tmp_11_1_13_reg_7492;
ap_reg_pp0_iter8_tmp_11_2_13_reg_7497 <= ap_reg_pp0_iter7_tmp_11_2_13_reg_7497;
ap_reg_pp0_iter8_tmp_11_3_13_reg_7502 <= ap_reg_pp0_iter7_tmp_11_3_13_reg_7502;
ap_reg_pp0_iter8_tmp_11_4_13_reg_7507 <= ap_reg_pp0_iter7_tmp_11_4_13_reg_7507;
ap_reg_pp0_iter8_tmp_11_5_13_reg_7512 <= ap_reg_pp0_iter7_tmp_11_5_13_reg_7512;
ap_reg_pp0_iter8_tmp_11_6_13_reg_7517 <= ap_reg_pp0_iter7_tmp_11_6_13_reg_7517;
ap_reg_pp0_iter8_tmp_11_7_13_reg_7522 <= ap_reg_pp0_iter7_tmp_11_7_13_reg_7522;
ap_reg_pp0_iter8_tmp_11_8_13_reg_7527 <= ap_reg_pp0_iter7_tmp_11_8_13_reg_7527;
ap_reg_pp0_iter8_tmp_11_9_13_reg_7532 <= ap_reg_pp0_iter7_tmp_11_9_13_reg_7532;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_14_reg_7567 <= tmp_11_0_14_reg_7567;
ap_reg_pp0_iter2_tmp_11_10_14_reg_7617 <= tmp_11_10_14_reg_7617;
ap_reg_pp0_iter2_tmp_11_11_14_reg_7622 <= tmp_11_11_14_reg_7622;
ap_reg_pp0_iter2_tmp_11_12_14_reg_7627 <= tmp_11_12_14_reg_7627;
ap_reg_pp0_iter2_tmp_11_13_14_reg_7632 <= tmp_11_13_14_reg_7632;
ap_reg_pp0_iter2_tmp_11_14_14_reg_7637 <= tmp_11_14_14_reg_7637;
ap_reg_pp0_iter2_tmp_11_15_14_reg_7642 <= tmp_11_15_14_reg_7642;
ap_reg_pp0_iter2_tmp_11_1_14_reg_7572 <= tmp_11_1_14_reg_7572;
ap_reg_pp0_iter2_tmp_11_2_14_reg_7577 <= tmp_11_2_14_reg_7577;
ap_reg_pp0_iter2_tmp_11_3_14_reg_7582 <= tmp_11_3_14_reg_7582;
ap_reg_pp0_iter2_tmp_11_4_14_reg_7587 <= tmp_11_4_14_reg_7587;
ap_reg_pp0_iter2_tmp_11_5_14_reg_7592 <= tmp_11_5_14_reg_7592;
ap_reg_pp0_iter2_tmp_11_6_14_reg_7597 <= tmp_11_6_14_reg_7597;
ap_reg_pp0_iter2_tmp_11_7_14_reg_7602 <= tmp_11_7_14_reg_7602;
ap_reg_pp0_iter2_tmp_11_8_14_reg_7607 <= tmp_11_8_14_reg_7607;
ap_reg_pp0_iter2_tmp_11_9_14_reg_7612 <= tmp_11_9_14_reg_7612;
ap_reg_pp0_iter3_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter2_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter3_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter2_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter3_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter2_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter3_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter2_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter3_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter2_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter3_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter2_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter3_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter2_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter3_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter2_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter3_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter2_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter3_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter2_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter3_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter2_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter3_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter2_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter3_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter2_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter3_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter2_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter3_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter2_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter3_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter2_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter4_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter3_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter4_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter3_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter4_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter3_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter4_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter3_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter4_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter3_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter4_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter3_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter4_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter3_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter4_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter3_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter4_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter3_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter4_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter3_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter4_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter3_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter4_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter3_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter4_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter3_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter4_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter3_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter4_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter3_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter4_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter3_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter5_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter4_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter5_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter4_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter5_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter4_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter5_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter4_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter5_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter4_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter5_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter4_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter5_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter4_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter5_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter4_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter5_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter4_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter5_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter4_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter5_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter4_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter5_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter4_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter5_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter4_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter5_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter4_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter5_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter4_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter5_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter4_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter6_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter5_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter6_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter5_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter6_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter5_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter6_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter5_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter6_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter5_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter6_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter5_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter6_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter5_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter6_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter5_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter6_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter5_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter6_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter5_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter6_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter5_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter6_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter5_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter6_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter5_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter6_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter5_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter6_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter5_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter6_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter5_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter7_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter6_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter7_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter6_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter7_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter6_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter7_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter6_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter7_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter6_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter7_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter6_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter7_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter6_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter7_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter6_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter7_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter6_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter7_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter6_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter7_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter6_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter7_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter6_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter7_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter6_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter7_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter6_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter7_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter6_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter7_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter6_tmp_11_9_14_reg_7612;
ap_reg_pp0_iter8_tmp_11_0_14_reg_7567 <= ap_reg_pp0_iter7_tmp_11_0_14_reg_7567;
ap_reg_pp0_iter8_tmp_11_10_14_reg_7617 <= ap_reg_pp0_iter7_tmp_11_10_14_reg_7617;
ap_reg_pp0_iter8_tmp_11_11_14_reg_7622 <= ap_reg_pp0_iter7_tmp_11_11_14_reg_7622;
ap_reg_pp0_iter8_tmp_11_12_14_reg_7627 <= ap_reg_pp0_iter7_tmp_11_12_14_reg_7627;
ap_reg_pp0_iter8_tmp_11_13_14_reg_7632 <= ap_reg_pp0_iter7_tmp_11_13_14_reg_7632;
ap_reg_pp0_iter8_tmp_11_14_14_reg_7637 <= ap_reg_pp0_iter7_tmp_11_14_14_reg_7637;
ap_reg_pp0_iter8_tmp_11_15_14_reg_7642 <= ap_reg_pp0_iter7_tmp_11_15_14_reg_7642;
ap_reg_pp0_iter8_tmp_11_1_14_reg_7572 <= ap_reg_pp0_iter7_tmp_11_1_14_reg_7572;
ap_reg_pp0_iter8_tmp_11_2_14_reg_7577 <= ap_reg_pp0_iter7_tmp_11_2_14_reg_7577;
ap_reg_pp0_iter8_tmp_11_3_14_reg_7582 <= ap_reg_pp0_iter7_tmp_11_3_14_reg_7582;
ap_reg_pp0_iter8_tmp_11_4_14_reg_7587 <= ap_reg_pp0_iter7_tmp_11_4_14_reg_7587;
ap_reg_pp0_iter8_tmp_11_5_14_reg_7592 <= ap_reg_pp0_iter7_tmp_11_5_14_reg_7592;
ap_reg_pp0_iter8_tmp_11_6_14_reg_7597 <= ap_reg_pp0_iter7_tmp_11_6_14_reg_7597;
ap_reg_pp0_iter8_tmp_11_7_14_reg_7602 <= ap_reg_pp0_iter7_tmp_11_7_14_reg_7602;
ap_reg_pp0_iter8_tmp_11_8_14_reg_7607 <= ap_reg_pp0_iter7_tmp_11_8_14_reg_7607;
ap_reg_pp0_iter8_tmp_11_9_14_reg_7612 <= ap_reg_pp0_iter7_tmp_11_9_14_reg_7612;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_4_reg_5562 <= tmp_11_0_4_reg_5562;
ap_reg_pp0_iter2_tmp_11_10_4_reg_5732 <= tmp_11_10_4_reg_5732;
ap_reg_pp0_iter2_tmp_11_11_4_reg_5747 <= tmp_11_11_4_reg_5747;
ap_reg_pp0_iter2_tmp_11_12_4_reg_5762 <= tmp_11_12_4_reg_5762;
ap_reg_pp0_iter2_tmp_11_13_4_reg_5777 <= tmp_11_13_4_reg_5777;
ap_reg_pp0_iter2_tmp_11_14_4_reg_5792 <= tmp_11_14_4_reg_5792;
ap_reg_pp0_iter2_tmp_11_15_4_reg_5807 <= tmp_11_15_4_reg_5807;
ap_reg_pp0_iter2_tmp_11_1_4_reg_5597 <= tmp_11_1_4_reg_5597;
ap_reg_pp0_iter2_tmp_11_2_4_reg_5612 <= tmp_11_2_4_reg_5612;
ap_reg_pp0_iter2_tmp_11_3_4_reg_5627 <= tmp_11_3_4_reg_5627;
ap_reg_pp0_iter2_tmp_11_4_4_reg_5642 <= tmp_11_4_4_reg_5642;
ap_reg_pp0_iter2_tmp_11_5_4_reg_5657 <= tmp_11_5_4_reg_5657;
ap_reg_pp0_iter2_tmp_11_6_4_reg_5672 <= tmp_11_6_4_reg_5672;
ap_reg_pp0_iter2_tmp_11_7_4_reg_5687 <= tmp_11_7_4_reg_5687;
ap_reg_pp0_iter2_tmp_11_8_4_reg_5702 <= tmp_11_8_4_reg_5702;
ap_reg_pp0_iter2_tmp_11_9_4_reg_5717 <= tmp_11_9_4_reg_5717;
ap_reg_pp0_iter3_tmp_11_0_4_reg_5562 <= ap_reg_pp0_iter2_tmp_11_0_4_reg_5562;
ap_reg_pp0_iter3_tmp_11_10_4_reg_5732 <= ap_reg_pp0_iter2_tmp_11_10_4_reg_5732;
ap_reg_pp0_iter3_tmp_11_11_4_reg_5747 <= ap_reg_pp0_iter2_tmp_11_11_4_reg_5747;
ap_reg_pp0_iter3_tmp_11_12_4_reg_5762 <= ap_reg_pp0_iter2_tmp_11_12_4_reg_5762;
ap_reg_pp0_iter3_tmp_11_13_4_reg_5777 <= ap_reg_pp0_iter2_tmp_11_13_4_reg_5777;
ap_reg_pp0_iter3_tmp_11_14_4_reg_5792 <= ap_reg_pp0_iter2_tmp_11_14_4_reg_5792;
ap_reg_pp0_iter3_tmp_11_15_4_reg_5807 <= ap_reg_pp0_iter2_tmp_11_15_4_reg_5807;
ap_reg_pp0_iter3_tmp_11_1_4_reg_5597 <= ap_reg_pp0_iter2_tmp_11_1_4_reg_5597;
ap_reg_pp0_iter3_tmp_11_2_4_reg_5612 <= ap_reg_pp0_iter2_tmp_11_2_4_reg_5612;
ap_reg_pp0_iter3_tmp_11_3_4_reg_5627 <= ap_reg_pp0_iter2_tmp_11_3_4_reg_5627;
ap_reg_pp0_iter3_tmp_11_4_4_reg_5642 <= ap_reg_pp0_iter2_tmp_11_4_4_reg_5642;
ap_reg_pp0_iter3_tmp_11_5_4_reg_5657 <= ap_reg_pp0_iter2_tmp_11_5_4_reg_5657;
ap_reg_pp0_iter3_tmp_11_6_4_reg_5672 <= ap_reg_pp0_iter2_tmp_11_6_4_reg_5672;
ap_reg_pp0_iter3_tmp_11_7_4_reg_5687 <= ap_reg_pp0_iter2_tmp_11_7_4_reg_5687;
ap_reg_pp0_iter3_tmp_11_8_4_reg_5702 <= ap_reg_pp0_iter2_tmp_11_8_4_reg_5702;
ap_reg_pp0_iter3_tmp_11_9_4_reg_5717 <= ap_reg_pp0_iter2_tmp_11_9_4_reg_5717;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_5_reg_5827 <= tmp_11_0_5_reg_5827;
ap_reg_pp0_iter2_tmp_11_10_5_reg_5997 <= tmp_11_10_5_reg_5997;
ap_reg_pp0_iter2_tmp_11_11_5_reg_6012 <= tmp_11_11_5_reg_6012;
ap_reg_pp0_iter2_tmp_11_12_5_reg_6027 <= tmp_11_12_5_reg_6027;
ap_reg_pp0_iter2_tmp_11_13_5_reg_6042 <= tmp_11_13_5_reg_6042;
ap_reg_pp0_iter2_tmp_11_14_5_reg_6057 <= tmp_11_14_5_reg_6057;
ap_reg_pp0_iter2_tmp_11_15_5_reg_6072 <= tmp_11_15_5_reg_6072;
ap_reg_pp0_iter2_tmp_11_1_5_reg_5862 <= tmp_11_1_5_reg_5862;
ap_reg_pp0_iter2_tmp_11_2_5_reg_5877 <= tmp_11_2_5_reg_5877;
ap_reg_pp0_iter2_tmp_11_3_5_reg_5892 <= tmp_11_3_5_reg_5892;
ap_reg_pp0_iter2_tmp_11_4_5_reg_5907 <= tmp_11_4_5_reg_5907;
ap_reg_pp0_iter2_tmp_11_5_5_reg_5922 <= tmp_11_5_5_reg_5922;
ap_reg_pp0_iter2_tmp_11_6_5_reg_5937 <= tmp_11_6_5_reg_5937;
ap_reg_pp0_iter2_tmp_11_7_5_reg_5952 <= tmp_11_7_5_reg_5952;
ap_reg_pp0_iter2_tmp_11_8_5_reg_5967 <= tmp_11_8_5_reg_5967;
ap_reg_pp0_iter2_tmp_11_9_5_reg_5982 <= tmp_11_9_5_reg_5982;
ap_reg_pp0_iter3_tmp_11_0_5_reg_5827 <= ap_reg_pp0_iter2_tmp_11_0_5_reg_5827;
ap_reg_pp0_iter3_tmp_11_10_5_reg_5997 <= ap_reg_pp0_iter2_tmp_11_10_5_reg_5997;
ap_reg_pp0_iter3_tmp_11_11_5_reg_6012 <= ap_reg_pp0_iter2_tmp_11_11_5_reg_6012;
ap_reg_pp0_iter3_tmp_11_12_5_reg_6027 <= ap_reg_pp0_iter2_tmp_11_12_5_reg_6027;
ap_reg_pp0_iter3_tmp_11_13_5_reg_6042 <= ap_reg_pp0_iter2_tmp_11_13_5_reg_6042;
ap_reg_pp0_iter3_tmp_11_14_5_reg_6057 <= ap_reg_pp0_iter2_tmp_11_14_5_reg_6057;
ap_reg_pp0_iter3_tmp_11_15_5_reg_6072 <= ap_reg_pp0_iter2_tmp_11_15_5_reg_6072;
ap_reg_pp0_iter3_tmp_11_1_5_reg_5862 <= ap_reg_pp0_iter2_tmp_11_1_5_reg_5862;
ap_reg_pp0_iter3_tmp_11_2_5_reg_5877 <= ap_reg_pp0_iter2_tmp_11_2_5_reg_5877;
ap_reg_pp0_iter3_tmp_11_3_5_reg_5892 <= ap_reg_pp0_iter2_tmp_11_3_5_reg_5892;
ap_reg_pp0_iter3_tmp_11_4_5_reg_5907 <= ap_reg_pp0_iter2_tmp_11_4_5_reg_5907;
ap_reg_pp0_iter3_tmp_11_5_5_reg_5922 <= ap_reg_pp0_iter2_tmp_11_5_5_reg_5922;
ap_reg_pp0_iter3_tmp_11_6_5_reg_5937 <= ap_reg_pp0_iter2_tmp_11_6_5_reg_5937;
ap_reg_pp0_iter3_tmp_11_7_5_reg_5952 <= ap_reg_pp0_iter2_tmp_11_7_5_reg_5952;
ap_reg_pp0_iter3_tmp_11_8_5_reg_5967 <= ap_reg_pp0_iter2_tmp_11_8_5_reg_5967;
ap_reg_pp0_iter3_tmp_11_9_5_reg_5982 <= ap_reg_pp0_iter2_tmp_11_9_5_reg_5982;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_6_reg_6087 <= tmp_11_0_6_reg_6087;
ap_reg_pp0_iter2_tmp_11_10_6_reg_6257 <= tmp_11_10_6_reg_6257;
ap_reg_pp0_iter2_tmp_11_11_6_reg_6272 <= tmp_11_11_6_reg_6272;
ap_reg_pp0_iter2_tmp_11_12_6_reg_6287 <= tmp_11_12_6_reg_6287;
ap_reg_pp0_iter2_tmp_11_13_6_reg_6302 <= tmp_11_13_6_reg_6302;
ap_reg_pp0_iter2_tmp_11_14_6_reg_6317 <= tmp_11_14_6_reg_6317;
ap_reg_pp0_iter2_tmp_11_15_6_reg_6332 <= tmp_11_15_6_reg_6332;
ap_reg_pp0_iter2_tmp_11_1_6_reg_6122 <= tmp_11_1_6_reg_6122;
ap_reg_pp0_iter2_tmp_11_2_6_reg_6137 <= tmp_11_2_6_reg_6137;
ap_reg_pp0_iter2_tmp_11_3_6_reg_6152 <= tmp_11_3_6_reg_6152;
ap_reg_pp0_iter2_tmp_11_4_6_reg_6167 <= tmp_11_4_6_reg_6167;
ap_reg_pp0_iter2_tmp_11_5_6_reg_6182 <= tmp_11_5_6_reg_6182;
ap_reg_pp0_iter2_tmp_11_6_6_reg_6197 <= tmp_11_6_6_reg_6197;
ap_reg_pp0_iter2_tmp_11_7_6_reg_6212 <= tmp_11_7_6_reg_6212;
ap_reg_pp0_iter2_tmp_11_8_6_reg_6227 <= tmp_11_8_6_reg_6227;
ap_reg_pp0_iter2_tmp_11_9_6_reg_6242 <= tmp_11_9_6_reg_6242;
ap_reg_pp0_iter3_tmp_11_0_6_reg_6087 <= ap_reg_pp0_iter2_tmp_11_0_6_reg_6087;
ap_reg_pp0_iter3_tmp_11_10_6_reg_6257 <= ap_reg_pp0_iter2_tmp_11_10_6_reg_6257;
ap_reg_pp0_iter3_tmp_11_11_6_reg_6272 <= ap_reg_pp0_iter2_tmp_11_11_6_reg_6272;
ap_reg_pp0_iter3_tmp_11_12_6_reg_6287 <= ap_reg_pp0_iter2_tmp_11_12_6_reg_6287;
ap_reg_pp0_iter3_tmp_11_13_6_reg_6302 <= ap_reg_pp0_iter2_tmp_11_13_6_reg_6302;
ap_reg_pp0_iter3_tmp_11_14_6_reg_6317 <= ap_reg_pp0_iter2_tmp_11_14_6_reg_6317;
ap_reg_pp0_iter3_tmp_11_15_6_reg_6332 <= ap_reg_pp0_iter2_tmp_11_15_6_reg_6332;
ap_reg_pp0_iter3_tmp_11_1_6_reg_6122 <= ap_reg_pp0_iter2_tmp_11_1_6_reg_6122;
ap_reg_pp0_iter3_tmp_11_2_6_reg_6137 <= ap_reg_pp0_iter2_tmp_11_2_6_reg_6137;
ap_reg_pp0_iter3_tmp_11_3_6_reg_6152 <= ap_reg_pp0_iter2_tmp_11_3_6_reg_6152;
ap_reg_pp0_iter3_tmp_11_4_6_reg_6167 <= ap_reg_pp0_iter2_tmp_11_4_6_reg_6167;
ap_reg_pp0_iter3_tmp_11_5_6_reg_6182 <= ap_reg_pp0_iter2_tmp_11_5_6_reg_6182;
ap_reg_pp0_iter3_tmp_11_6_6_reg_6197 <= ap_reg_pp0_iter2_tmp_11_6_6_reg_6197;
ap_reg_pp0_iter3_tmp_11_7_6_reg_6212 <= ap_reg_pp0_iter2_tmp_11_7_6_reg_6212;
ap_reg_pp0_iter3_tmp_11_8_6_reg_6227 <= ap_reg_pp0_iter2_tmp_11_8_6_reg_6227;
ap_reg_pp0_iter3_tmp_11_9_6_reg_6242 <= ap_reg_pp0_iter2_tmp_11_9_6_reg_6242;
ap_reg_pp0_iter4_tmp_11_0_6_reg_6087 <= ap_reg_pp0_iter3_tmp_11_0_6_reg_6087;
ap_reg_pp0_iter4_tmp_11_10_6_reg_6257 <= ap_reg_pp0_iter3_tmp_11_10_6_reg_6257;
ap_reg_pp0_iter4_tmp_11_11_6_reg_6272 <= ap_reg_pp0_iter3_tmp_11_11_6_reg_6272;
ap_reg_pp0_iter4_tmp_11_12_6_reg_6287 <= ap_reg_pp0_iter3_tmp_11_12_6_reg_6287;
ap_reg_pp0_iter4_tmp_11_13_6_reg_6302 <= ap_reg_pp0_iter3_tmp_11_13_6_reg_6302;
ap_reg_pp0_iter4_tmp_11_14_6_reg_6317 <= ap_reg_pp0_iter3_tmp_11_14_6_reg_6317;
ap_reg_pp0_iter4_tmp_11_15_6_reg_6332 <= ap_reg_pp0_iter3_tmp_11_15_6_reg_6332;
ap_reg_pp0_iter4_tmp_11_1_6_reg_6122 <= ap_reg_pp0_iter3_tmp_11_1_6_reg_6122;
ap_reg_pp0_iter4_tmp_11_2_6_reg_6137 <= ap_reg_pp0_iter3_tmp_11_2_6_reg_6137;
ap_reg_pp0_iter4_tmp_11_3_6_reg_6152 <= ap_reg_pp0_iter3_tmp_11_3_6_reg_6152;
ap_reg_pp0_iter4_tmp_11_4_6_reg_6167 <= ap_reg_pp0_iter3_tmp_11_4_6_reg_6167;
ap_reg_pp0_iter4_tmp_11_5_6_reg_6182 <= ap_reg_pp0_iter3_tmp_11_5_6_reg_6182;
ap_reg_pp0_iter4_tmp_11_6_6_reg_6197 <= ap_reg_pp0_iter3_tmp_11_6_6_reg_6197;
ap_reg_pp0_iter4_tmp_11_7_6_reg_6212 <= ap_reg_pp0_iter3_tmp_11_7_6_reg_6212;
ap_reg_pp0_iter4_tmp_11_8_6_reg_6227 <= ap_reg_pp0_iter3_tmp_11_8_6_reg_6227;
ap_reg_pp0_iter4_tmp_11_9_6_reg_6242 <= ap_reg_pp0_iter3_tmp_11_9_6_reg_6242;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_8_reg_6527 <= tmp_11_0_8_reg_6527;
ap_reg_pp0_iter2_tmp_11_10_8_reg_6647 <= tmp_11_10_8_reg_6647;
ap_reg_pp0_iter2_tmp_11_11_8_reg_6657 <= tmp_11_11_8_reg_6657;
ap_reg_pp0_iter2_tmp_11_12_8_reg_6667 <= tmp_11_12_8_reg_6667;
ap_reg_pp0_iter2_tmp_11_13_8_reg_6677 <= tmp_11_13_8_reg_6677;
ap_reg_pp0_iter2_tmp_11_14_8_reg_6687 <= tmp_11_14_8_reg_6687;
ap_reg_pp0_iter2_tmp_11_15_8_reg_6697 <= tmp_11_15_8_reg_6697;
ap_reg_pp0_iter2_tmp_11_1_8_reg_6557 <= tmp_11_1_8_reg_6557;
ap_reg_pp0_iter2_tmp_11_2_8_reg_6567 <= tmp_11_2_8_reg_6567;
ap_reg_pp0_iter2_tmp_11_3_8_reg_6577 <= tmp_11_3_8_reg_6577;
ap_reg_pp0_iter2_tmp_11_4_8_reg_6587 <= tmp_11_4_8_reg_6587;
ap_reg_pp0_iter2_tmp_11_5_8_reg_6597 <= tmp_11_5_8_reg_6597;
ap_reg_pp0_iter2_tmp_11_6_8_reg_6607 <= tmp_11_6_8_reg_6607;
ap_reg_pp0_iter2_tmp_11_7_8_reg_6617 <= tmp_11_7_8_reg_6617;
ap_reg_pp0_iter2_tmp_11_8_8_reg_6627 <= tmp_11_8_8_reg_6627;
ap_reg_pp0_iter2_tmp_11_9_8_reg_6637 <= tmp_11_9_8_reg_6637;
ap_reg_pp0_iter3_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter2_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter3_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter2_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter3_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter2_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter3_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter2_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter3_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter2_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter3_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter2_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter3_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter2_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter3_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter2_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter3_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter2_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter3_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter2_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter3_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter2_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter3_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter2_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter3_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter2_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter3_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter2_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter3_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter2_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter3_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter2_tmp_11_9_8_reg_6637;
ap_reg_pp0_iter4_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter3_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter4_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter3_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter4_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter3_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter4_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter3_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter4_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter3_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter4_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter3_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter4_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter3_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter4_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter3_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter4_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter3_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter4_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter3_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter4_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter3_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter4_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter3_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter4_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter3_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter4_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter3_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter4_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter3_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter4_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter3_tmp_11_9_8_reg_6637;
ap_reg_pp0_iter5_tmp_11_0_8_reg_6527 <= ap_reg_pp0_iter4_tmp_11_0_8_reg_6527;
ap_reg_pp0_iter5_tmp_11_10_8_reg_6647 <= ap_reg_pp0_iter4_tmp_11_10_8_reg_6647;
ap_reg_pp0_iter5_tmp_11_11_8_reg_6657 <= ap_reg_pp0_iter4_tmp_11_11_8_reg_6657;
ap_reg_pp0_iter5_tmp_11_12_8_reg_6667 <= ap_reg_pp0_iter4_tmp_11_12_8_reg_6667;
ap_reg_pp0_iter5_tmp_11_13_8_reg_6677 <= ap_reg_pp0_iter4_tmp_11_13_8_reg_6677;
ap_reg_pp0_iter5_tmp_11_14_8_reg_6687 <= ap_reg_pp0_iter4_tmp_11_14_8_reg_6687;
ap_reg_pp0_iter5_tmp_11_15_8_reg_6697 <= ap_reg_pp0_iter4_tmp_11_15_8_reg_6697;
ap_reg_pp0_iter5_tmp_11_1_8_reg_6557 <= ap_reg_pp0_iter4_tmp_11_1_8_reg_6557;
ap_reg_pp0_iter5_tmp_11_2_8_reg_6567 <= ap_reg_pp0_iter4_tmp_11_2_8_reg_6567;
ap_reg_pp0_iter5_tmp_11_3_8_reg_6577 <= ap_reg_pp0_iter4_tmp_11_3_8_reg_6577;
ap_reg_pp0_iter5_tmp_11_4_8_reg_6587 <= ap_reg_pp0_iter4_tmp_11_4_8_reg_6587;
ap_reg_pp0_iter5_tmp_11_5_8_reg_6597 <= ap_reg_pp0_iter4_tmp_11_5_8_reg_6597;
ap_reg_pp0_iter5_tmp_11_6_8_reg_6607 <= ap_reg_pp0_iter4_tmp_11_6_8_reg_6607;
ap_reg_pp0_iter5_tmp_11_7_8_reg_6617 <= ap_reg_pp0_iter4_tmp_11_7_8_reg_6617;
ap_reg_pp0_iter5_tmp_11_8_8_reg_6627 <= ap_reg_pp0_iter4_tmp_11_8_8_reg_6627;
ap_reg_pp0_iter5_tmp_11_9_8_reg_6637 <= ap_reg_pp0_iter4_tmp_11_9_8_reg_6637;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_9_reg_6712 <= tmp_11_0_9_reg_6712;
ap_reg_pp0_iter2_tmp_11_10_9_reg_6882 <= tmp_11_10_9_reg_6882;
ap_reg_pp0_iter2_tmp_11_11_9_reg_6897 <= tmp_11_11_9_reg_6897;
ap_reg_pp0_iter2_tmp_11_12_9_reg_6912 <= tmp_11_12_9_reg_6912;
ap_reg_pp0_iter2_tmp_11_13_9_reg_6927 <= tmp_11_13_9_reg_6927;
ap_reg_pp0_iter2_tmp_11_14_9_reg_6942 <= tmp_11_14_9_reg_6942;
ap_reg_pp0_iter2_tmp_11_15_9_reg_6957 <= tmp_11_15_9_reg_6957;
ap_reg_pp0_iter2_tmp_11_1_9_reg_6747 <= tmp_11_1_9_reg_6747;
ap_reg_pp0_iter2_tmp_11_2_9_reg_6762 <= tmp_11_2_9_reg_6762;
ap_reg_pp0_iter2_tmp_11_3_9_reg_6777 <= tmp_11_3_9_reg_6777;
ap_reg_pp0_iter2_tmp_11_4_9_reg_6792 <= tmp_11_4_9_reg_6792;
ap_reg_pp0_iter2_tmp_11_5_9_reg_6807 <= tmp_11_5_9_reg_6807;
ap_reg_pp0_iter2_tmp_11_6_9_reg_6822 <= tmp_11_6_9_reg_6822;
ap_reg_pp0_iter2_tmp_11_7_9_reg_6837 <= tmp_11_7_9_reg_6837;
ap_reg_pp0_iter2_tmp_11_8_9_reg_6852 <= tmp_11_8_9_reg_6852;
ap_reg_pp0_iter2_tmp_11_9_9_reg_6867 <= tmp_11_9_9_reg_6867;
ap_reg_pp0_iter3_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter2_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter3_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter2_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter3_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter2_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter3_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter2_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter3_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter2_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter3_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter2_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter3_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter2_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter3_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter2_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter3_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter2_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter3_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter2_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter3_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter2_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter3_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter2_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter3_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter2_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter3_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter2_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter3_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter2_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter3_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter2_tmp_11_9_9_reg_6867;
ap_reg_pp0_iter4_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter3_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter4_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter3_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter4_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter3_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter4_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter3_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter4_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter3_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter4_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter3_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter4_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter3_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter4_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter3_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter4_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter3_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter4_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter3_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter4_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter3_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter4_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter3_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter4_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter3_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter4_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter3_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter4_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter3_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter4_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter3_tmp_11_9_9_reg_6867;
ap_reg_pp0_iter5_tmp_11_0_9_reg_6712 <= ap_reg_pp0_iter4_tmp_11_0_9_reg_6712;
ap_reg_pp0_iter5_tmp_11_10_9_reg_6882 <= ap_reg_pp0_iter4_tmp_11_10_9_reg_6882;
ap_reg_pp0_iter5_tmp_11_11_9_reg_6897 <= ap_reg_pp0_iter4_tmp_11_11_9_reg_6897;
ap_reg_pp0_iter5_tmp_11_12_9_reg_6912 <= ap_reg_pp0_iter4_tmp_11_12_9_reg_6912;
ap_reg_pp0_iter5_tmp_11_13_9_reg_6927 <= ap_reg_pp0_iter4_tmp_11_13_9_reg_6927;
ap_reg_pp0_iter5_tmp_11_14_9_reg_6942 <= ap_reg_pp0_iter4_tmp_11_14_9_reg_6942;
ap_reg_pp0_iter5_tmp_11_15_9_reg_6957 <= ap_reg_pp0_iter4_tmp_11_15_9_reg_6957;
ap_reg_pp0_iter5_tmp_11_1_9_reg_6747 <= ap_reg_pp0_iter4_tmp_11_1_9_reg_6747;
ap_reg_pp0_iter5_tmp_11_2_9_reg_6762 <= ap_reg_pp0_iter4_tmp_11_2_9_reg_6762;
ap_reg_pp0_iter5_tmp_11_3_9_reg_6777 <= ap_reg_pp0_iter4_tmp_11_3_9_reg_6777;
ap_reg_pp0_iter5_tmp_11_4_9_reg_6792 <= ap_reg_pp0_iter4_tmp_11_4_9_reg_6792;
ap_reg_pp0_iter5_tmp_11_5_9_reg_6807 <= ap_reg_pp0_iter4_tmp_11_5_9_reg_6807;
ap_reg_pp0_iter5_tmp_11_6_9_reg_6822 <= ap_reg_pp0_iter4_tmp_11_6_9_reg_6822;
ap_reg_pp0_iter5_tmp_11_7_9_reg_6837 <= ap_reg_pp0_iter4_tmp_11_7_9_reg_6837;
ap_reg_pp0_iter5_tmp_11_8_9_reg_6852 <= ap_reg_pp0_iter4_tmp_11_8_9_reg_6852;
ap_reg_pp0_iter5_tmp_11_9_9_reg_6867 <= ap_reg_pp0_iter4_tmp_11_9_9_reg_6867;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter2_tmp_11_0_s_reg_6967 <= tmp_11_0_s_reg_6967;
ap_reg_pp0_iter2_tmp_11_10_s_reg_7087 <= tmp_11_10_s_reg_7087;
ap_reg_pp0_iter2_tmp_11_11_s_reg_7097 <= tmp_11_11_s_reg_7097;
ap_reg_pp0_iter2_tmp_11_12_s_reg_7107 <= tmp_11_12_s_reg_7107;
ap_reg_pp0_iter2_tmp_11_13_s_reg_7117 <= tmp_11_13_s_reg_7117;
ap_reg_pp0_iter2_tmp_11_14_s_reg_7127 <= tmp_11_14_s_reg_7127;
ap_reg_pp0_iter2_tmp_11_15_s_reg_7137 <= tmp_11_15_s_reg_7137;
ap_reg_pp0_iter2_tmp_11_1_s_reg_6997 <= tmp_11_1_s_reg_6997;
ap_reg_pp0_iter2_tmp_11_2_s_reg_7007 <= tmp_11_2_s_reg_7007;
ap_reg_pp0_iter2_tmp_11_3_s_reg_7017 <= tmp_11_3_s_reg_7017;
ap_reg_pp0_iter2_tmp_11_4_s_reg_7027 <= tmp_11_4_s_reg_7027;
ap_reg_pp0_iter2_tmp_11_5_s_reg_7037 <= tmp_11_5_s_reg_7037;
ap_reg_pp0_iter2_tmp_11_6_s_reg_7047 <= tmp_11_6_s_reg_7047;
ap_reg_pp0_iter2_tmp_11_7_s_reg_7057 <= tmp_11_7_s_reg_7057;
ap_reg_pp0_iter2_tmp_11_8_s_reg_7067 <= tmp_11_8_s_reg_7067;
ap_reg_pp0_iter2_tmp_11_9_s_reg_7077 <= tmp_11_9_s_reg_7077;
ap_reg_pp0_iter3_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter2_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter3_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter2_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter3_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter2_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter3_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter2_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter3_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter2_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter3_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter2_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter3_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter2_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter3_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter2_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter3_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter2_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter3_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter2_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter3_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter2_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter3_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter2_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter3_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter2_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter3_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter2_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter3_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter2_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter3_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter2_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter4_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter3_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter4_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter3_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter4_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter3_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter4_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter3_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter4_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter3_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter4_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter3_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter4_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter3_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter4_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter3_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter4_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter3_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter4_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter3_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter4_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter3_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter4_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter3_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter4_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter3_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter4_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter3_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter4_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter3_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter4_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter3_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter5_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter4_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter5_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter4_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter5_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter4_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter5_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter4_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter5_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter4_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter5_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter4_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter5_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter4_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter5_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter4_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter5_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter4_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter5_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter4_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter5_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter4_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter5_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter4_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter5_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter4_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter5_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter4_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter5_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter4_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter5_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter4_tmp_11_9_s_reg_7077;
ap_reg_pp0_iter6_tmp_11_0_s_reg_6967 <= ap_reg_pp0_iter5_tmp_11_0_s_reg_6967;
ap_reg_pp0_iter6_tmp_11_10_s_reg_7087 <= ap_reg_pp0_iter5_tmp_11_10_s_reg_7087;
ap_reg_pp0_iter6_tmp_11_11_s_reg_7097 <= ap_reg_pp0_iter5_tmp_11_11_s_reg_7097;
ap_reg_pp0_iter6_tmp_11_12_s_reg_7107 <= ap_reg_pp0_iter5_tmp_11_12_s_reg_7107;
ap_reg_pp0_iter6_tmp_11_13_s_reg_7117 <= ap_reg_pp0_iter5_tmp_11_13_s_reg_7117;
ap_reg_pp0_iter6_tmp_11_14_s_reg_7127 <= ap_reg_pp0_iter5_tmp_11_14_s_reg_7127;
ap_reg_pp0_iter6_tmp_11_15_s_reg_7137 <= ap_reg_pp0_iter5_tmp_11_15_s_reg_7137;
ap_reg_pp0_iter6_tmp_11_1_s_reg_6997 <= ap_reg_pp0_iter5_tmp_11_1_s_reg_6997;
ap_reg_pp0_iter6_tmp_11_2_s_reg_7007 <= ap_reg_pp0_iter5_tmp_11_2_s_reg_7007;
ap_reg_pp0_iter6_tmp_11_3_s_reg_7017 <= ap_reg_pp0_iter5_tmp_11_3_s_reg_7017;
ap_reg_pp0_iter6_tmp_11_4_s_reg_7027 <= ap_reg_pp0_iter5_tmp_11_4_s_reg_7027;
ap_reg_pp0_iter6_tmp_11_5_s_reg_7037 <= ap_reg_pp0_iter5_tmp_11_5_s_reg_7037;
ap_reg_pp0_iter6_tmp_11_6_s_reg_7047 <= ap_reg_pp0_iter5_tmp_11_6_s_reg_7047;
ap_reg_pp0_iter6_tmp_11_7_s_reg_7057 <= ap_reg_pp0_iter5_tmp_11_7_s_reg_7057;
ap_reg_pp0_iter6_tmp_11_8_s_reg_7067 <= ap_reg_pp0_iter5_tmp_11_8_s_reg_7067;
ap_reg_pp0_iter6_tmp_11_9_s_reg_7077 <= ap_reg_pp0_iter5_tmp_11_9_s_reg_7077;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
bufo_addr_reg_3867 <= tmp_647_cast_fu_1348_p1;
tmp_3_reg_3872 <= tmp_3_fu_1362_p2;
tmp_47_reg_3852 <= tmp_47_fu_1297_p2;
tmp_4_mid2_cast4_reg_3841[2 : 0] <= tmp_4_mid2_cast4_fu_1290_p1[2 : 0];
tmp_635_reg_3877 <= tmp_635_fu_1367_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
col_b_1_reg_3957 <= col_b_1_fu_1371_p2;
row_b_mid2_reg_3862 <= row_b_mid2_fu_1334_p3;
tmp_134_reg_3887 <= {{bufw_Dout_A[95:64]}};
tmp_169_reg_3892 <= {{bufw_Dout_A[127:96]}};
tmp_204_reg_3897 <= {{bufw_Dout_A[159:128]}};
tmp_239_reg_3902 <= {{bufw_Dout_A[191:160]}};
tmp_274_reg_3907 <= {{bufw_Dout_A[223:192]}};
tmp_309_reg_3912 <= {{bufw_Dout_A[255:224]}};
tmp_344_reg_3917 <= {{bufw_Dout_A[287:256]}};
tmp_379_reg_3922 <= {{bufw_Dout_A[319:288]}};
tmp_414_reg_3927 <= {{bufw_Dout_A[351:320]}};
tmp_449_reg_3932 <= {{bufw_Dout_A[383:352]}};
tmp_484_reg_3937 <= {{bufw_Dout_A[415:384]}};
tmp_519_reg_3942 <= {{bufw_Dout_A[447:416]}};
tmp_554_reg_3947 <= {{bufw_Dout_A[479:448]}};
tmp_589_reg_3952 <= {{bufw_Dout_A[511:480]}};
tmp_98_reg_3882 <= {{bufw_Dout_A[63:32]}};
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
col_b_mid2_reg_3802 <= col_b_mid2_fu_1250_p3;
row_b_mid_reg_3776 <= row_b_mid_fu_1211_p3;
tmp_1_mid2_cast_reg_3762[2 : 0] <= tmp_1_mid2_cast_fu_1156_p1[2 : 0];
tmp_2_reg_3767 <= tmp_2_fu_1170_p2;
tmp_75_reg_3792 <= tmp_75_fu_1228_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond_flatten2_fu_1051_p2))) begin
exitcond_flatten1_reg_3701 <= exitcond_flatten1_fu_1075_p2;
exitcond_flatten_reg_3684 <= exitcond_flatten_fu_1063_p2;
indvar_flatten40_op_reg_3707 <= indvar_flatten40_op_fu_1081_p2;
tmp_35_reg_3696 <= tmp_35_fu_1069_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
exitcond_flatten_mid_reg_3731 <= exitcond_flatten_mid_fu_1117_p2;
i_1_reg_3712 <= i_1_fu_1087_p2;
indvar_flatten_op_reg_3752 <= indvar_flatten_op_fu_1144_p2;
j_1_reg_3739 <= j_1_fu_1122_p2;
j_mid_reg_3717 <= j_mid_fu_1093_p3;
tmp_9_mid1_reg_3744 <= tmp_9_mid1_fu_1138_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
indvar_flatten_next1_reg_3757 <= indvar_flatten_next1_fu_1150_p3;
tmp_1_mid2_v_reg_3722 <= tmp_1_mid2_v_fu_1100_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
indvar_flatten_next2_reg_3679 <= indvar_flatten_next2_fu_1057_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
indvar_flatten_next_reg_3809 <= indvar_flatten_next_fu_1258_p3;
tmp_4_mid2_reg_3783 <= tmp_4_mid2_fu_1219_p3;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675)) | ((1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9) & (1'd0 == ap_reg_pp0_iter9_exitcond_flatten2_reg_3675)))) begin
reg_1001 <= grp_fu_473_p2;
reg_1006 <= grp_fu_477_p2;
reg_1011 <= grp_fu_481_p2;
reg_1016 <= grp_fu_485_p2;
reg_1021 <= grp_fu_489_p2;
reg_1026 <= grp_fu_493_p2;
reg_951 <= grp_fu_433_p2;
reg_956 <= grp_fu_437_p2;
reg_961 <= grp_fu_441_p2;
reg_966 <= grp_fu_445_p2;
reg_971 <= grp_fu_449_p2;
reg_976 <= grp_fu_453_p2;
reg_981 <= grp_fu_457_p2;
reg_986 <= grp_fu_461_p2;
reg_991 <= grp_fu_465_p2;
reg_996 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (exitcond_flatten2_reg_3675 == 1'd0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)))) begin
reg_711 <= {{bufw_Dout_A[63:32]}};
reg_715 <= {{bufw_Dout_A[95:64]}};
reg_719 <= {{bufw_Dout_A[127:96]}};
reg_723 <= {{bufw_Dout_A[159:128]}};
reg_727 <= {{bufw_Dout_A[191:160]}};
reg_731 <= {{bufw_Dout_A[223:192]}};
reg_735 <= {{bufw_Dout_A[255:224]}};
reg_739 <= {{bufw_Dout_A[287:256]}};
reg_743 <= {{bufw_Dout_A[319:288]}};
reg_747 <= {{bufw_Dout_A[351:320]}};
reg_751 <= {{bufw_Dout_A[383:352]}};
reg_755 <= {{bufw_Dout_A[415:384]}};
reg_759 <= {{bufw_Dout_A[447:416]}};
reg_763 <= {{bufw_Dout_A[479:448]}};
reg_767 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)))) begin
reg_771 <= {{bufw_Dout_A[63:32]}};
reg_775 <= {{bufw_Dout_A[95:64]}};
reg_779 <= {{bufw_Dout_A[127:96]}};
reg_783 <= {{bufw_Dout_A[159:128]}};
reg_787 <= {{bufw_Dout_A[191:160]}};
reg_791 <= {{bufw_Dout_A[223:192]}};
reg_795 <= {{bufw_Dout_A[255:224]}};
reg_799 <= {{bufw_Dout_A[287:256]}};
reg_803 <= {{bufw_Dout_A[319:288]}};
reg_807 <= {{bufw_Dout_A[351:320]}};
reg_811 <= {{bufw_Dout_A[383:352]}};
reg_815 <= {{bufw_Dout_A[415:384]}};
reg_819 <= {{bufw_Dout_A[447:416]}};
reg_823 <= {{bufw_Dout_A[479:448]}};
reg_827 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)))) begin
reg_831 <= {{bufw_Dout_A[63:32]}};
reg_835 <= {{bufw_Dout_A[95:64]}};
reg_839 <= {{bufw_Dout_A[127:96]}};
reg_843 <= {{bufw_Dout_A[159:128]}};
reg_847 <= {{bufw_Dout_A[191:160]}};
reg_851 <= {{bufw_Dout_A[223:192]}};
reg_855 <= {{bufw_Dout_A[255:224]}};
reg_859 <= {{bufw_Dout_A[287:256]}};
reg_863 <= {{bufw_Dout_A[319:288]}};
reg_867 <= {{bufw_Dout_A[351:320]}};
reg_871 <= {{bufw_Dout_A[383:352]}};
reg_875 <= {{bufw_Dout_A[415:384]}};
reg_879 <= {{bufw_Dout_A[447:416]}};
reg_883 <= {{bufw_Dout_A[479:448]}};
reg_887 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if ((((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0)))) begin
reg_891 <= {{bufw_Dout_A[63:32]}};
reg_895 <= {{bufw_Dout_A[95:64]}};
reg_899 <= {{bufw_Dout_A[127:96]}};
reg_903 <= {{bufw_Dout_A[159:128]}};
reg_907 <= {{bufw_Dout_A[191:160]}};
reg_911 <= {{bufw_Dout_A[223:192]}};
reg_915 <= {{bufw_Dout_A[255:224]}};
reg_919 <= {{bufw_Dout_A[287:256]}};
reg_923 <= {{bufw_Dout_A[319:288]}};
reg_927 <= {{bufw_Dout_A[351:320]}};
reg_931 <= {{bufw_Dout_A[383:352]}};
reg_935 <= {{bufw_Dout_A[415:384]}};
reg_939 <= {{bufw_Dout_A[447:416]}};
reg_943 <= {{bufw_Dout_A[479:448]}};
reg_947 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
row_b_1_reg_3834 <= row_b_1_fu_1282_p2;
tmp_43_reg_3824 <= tmp_43_fu_1273_p2;
tmp_4_mid2_cast_reg_3819[2 : 0] <= tmp_4_mid2_cast_fu_1270_p1[2 : 0];
tmp_5_reg_3814 <= tmp_5_fu_1265_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
tmp_108_reg_5607 <= {{bufw_Dout_A[63:32]}};
tmp_11_0_4_reg_5562 <= grp_fu_497_p2;
tmp_11_10_4_reg_5732 <= grp_fu_537_p2;
tmp_11_11_4_reg_5747 <= grp_fu_541_p2;
tmp_11_12_4_reg_5762 <= grp_fu_545_p2;
tmp_11_13_4_reg_5777 <= grp_fu_549_p2;
tmp_11_14_4_reg_5792 <= grp_fu_553_p2;
tmp_11_15_4_reg_5807 <= grp_fu_557_p2;
tmp_11_1_4_reg_5597 <= grp_fu_501_p2;
tmp_11_2_4_reg_5612 <= grp_fu_505_p2;
tmp_11_3_4_reg_5627 <= grp_fu_509_p2;
tmp_11_4_4_reg_5642 <= grp_fu_513_p2;
tmp_11_5_4_reg_5657 <= grp_fu_517_p2;
tmp_11_6_4_reg_5672 <= grp_fu_521_p2;
tmp_11_7_4_reg_5687 <= grp_fu_525_p2;
tmp_11_8_4_reg_5702 <= grp_fu_529_p2;
tmp_11_9_4_reg_5717 <= grp_fu_533_p2;
tmp_144_reg_5622 <= {{bufw_Dout_A[95:64]}};
tmp_179_reg_5637 <= {{bufw_Dout_A[127:96]}};
tmp_214_reg_5652 <= {{bufw_Dout_A[159:128]}};
tmp_249_reg_5667 <= {{bufw_Dout_A[191:160]}};
tmp_284_reg_5682 <= {{bufw_Dout_A[223:192]}};
tmp_319_reg_5697 <= {{bufw_Dout_A[255:224]}};
tmp_354_reg_5712 <= {{bufw_Dout_A[287:256]}};
tmp_389_reg_5727 <= {{bufw_Dout_A[319:288]}};
tmp_424_reg_5742 <= {{bufw_Dout_A[351:320]}};
tmp_459_reg_5757 <= {{bufw_Dout_A[383:352]}};
tmp_494_reg_5772 <= {{bufw_Dout_A[415:384]}};
tmp_529_reg_5787 <= {{bufw_Dout_A[447:416]}};
tmp_564_reg_5802 <= {{bufw_Dout_A[479:448]}};
tmp_599_reg_5817 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
tmp_110_reg_5872 <= {{bufw_Dout_A[63:32]}};
tmp_11_0_5_reg_5827 <= grp_fu_497_p2;
tmp_11_10_5_reg_5997 <= grp_fu_537_p2;
tmp_11_11_5_reg_6012 <= grp_fu_541_p2;
tmp_11_12_5_reg_6027 <= grp_fu_545_p2;
tmp_11_13_5_reg_6042 <= grp_fu_549_p2;
tmp_11_14_5_reg_6057 <= grp_fu_553_p2;
tmp_11_15_5_reg_6072 <= grp_fu_557_p2;
tmp_11_1_5_reg_5862 <= grp_fu_501_p2;
tmp_11_2_5_reg_5877 <= grp_fu_505_p2;
tmp_11_3_5_reg_5892 <= grp_fu_509_p2;
tmp_11_4_5_reg_5907 <= grp_fu_513_p2;
tmp_11_5_5_reg_5922 <= grp_fu_517_p2;
tmp_11_6_5_reg_5937 <= grp_fu_521_p2;
tmp_11_7_5_reg_5952 <= grp_fu_525_p2;
tmp_11_8_5_reg_5967 <= grp_fu_529_p2;
tmp_11_9_5_reg_5982 <= grp_fu_533_p2;
tmp_146_reg_5887 <= {{bufw_Dout_A[95:64]}};
tmp_181_reg_5902 <= {{bufw_Dout_A[127:96]}};
tmp_216_reg_5917 <= {{bufw_Dout_A[159:128]}};
tmp_251_reg_5932 <= {{bufw_Dout_A[191:160]}};
tmp_286_reg_5947 <= {{bufw_Dout_A[223:192]}};
tmp_321_reg_5962 <= {{bufw_Dout_A[255:224]}};
tmp_356_reg_5977 <= {{bufw_Dout_A[287:256]}};
tmp_391_reg_5992 <= {{bufw_Dout_A[319:288]}};
tmp_426_reg_6007 <= {{bufw_Dout_A[351:320]}};
tmp_461_reg_6022 <= {{bufw_Dout_A[383:352]}};
tmp_496_reg_6037 <= {{bufw_Dout_A[415:384]}};
tmp_531_reg_6052 <= {{bufw_Dout_A[447:416]}};
tmp_566_reg_6067 <= {{bufw_Dout_A[479:448]}};
tmp_601_reg_6082 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
tmp_112_reg_6132 <= {{bufw_Dout_A[63:32]}};
tmp_11_0_6_reg_6087 <= grp_fu_497_p2;
tmp_11_10_6_reg_6257 <= grp_fu_537_p2;
tmp_11_11_6_reg_6272 <= grp_fu_541_p2;
tmp_11_12_6_reg_6287 <= grp_fu_545_p2;
tmp_11_13_6_reg_6302 <= grp_fu_549_p2;
tmp_11_14_6_reg_6317 <= grp_fu_553_p2;
tmp_11_15_6_reg_6332 <= grp_fu_557_p2;
tmp_11_1_6_reg_6122 <= grp_fu_501_p2;
tmp_11_2_6_reg_6137 <= grp_fu_505_p2;
tmp_11_3_6_reg_6152 <= grp_fu_509_p2;
tmp_11_4_6_reg_6167 <= grp_fu_513_p2;
tmp_11_5_6_reg_6182 <= grp_fu_517_p2;
tmp_11_6_6_reg_6197 <= grp_fu_521_p2;
tmp_11_7_6_reg_6212 <= grp_fu_525_p2;
tmp_11_8_6_reg_6227 <= grp_fu_529_p2;
tmp_11_9_6_reg_6242 <= grp_fu_533_p2;
tmp_148_reg_6147 <= {{bufw_Dout_A[95:64]}};
tmp_183_reg_6162 <= {{bufw_Dout_A[127:96]}};
tmp_218_reg_6177 <= {{bufw_Dout_A[159:128]}};
tmp_253_reg_6192 <= {{bufw_Dout_A[191:160]}};
tmp_288_reg_6207 <= {{bufw_Dout_A[223:192]}};
tmp_323_reg_6222 <= {{bufw_Dout_A[255:224]}};
tmp_358_reg_6237 <= {{bufw_Dout_A[287:256]}};
tmp_393_reg_6252 <= {{bufw_Dout_A[319:288]}};
tmp_428_reg_6267 <= {{bufw_Dout_A[351:320]}};
tmp_463_reg_6282 <= {{bufw_Dout_A[383:352]}};
tmp_498_reg_6297 <= {{bufw_Dout_A[415:384]}};
tmp_533_reg_6312 <= {{bufw_Dout_A[447:416]}};
tmp_568_reg_6327 <= {{bufw_Dout_A[479:448]}};
tmp_603_reg_6342 <= {{bufw_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0))) begin
tmp_116_reg_4702 <= grp_fu_497_p2;
tmp_11_10_reg_4837 <= grp_fu_541_p2;
tmp_11_11_reg_4847 <= grp_fu_545_p2;
tmp_11_12_reg_4857 <= grp_fu_549_p2;
tmp_11_13_reg_4867 <= grp_fu_553_p2;
tmp_11_14_reg_4877 <= grp_fu_557_p2;
tmp_11_1_reg_4737 <= grp_fu_501_p2;
tmp_11_2_reg_4747 <= grp_fu_505_p2;
tmp_11_3_reg_4757 <= grp_fu_509_p2;
tmp_11_4_reg_4767 <= grp_fu_513_p2;
tmp_11_5_reg_4777 <= grp_fu_517_p2;
tmp_11_6_reg_4787 <= grp_fu_521_p2;
tmp_11_7_reg_4797 <= grp_fu_525_p2;
tmp_11_8_reg_4807 <= grp_fu_529_p2;
tmp_11_9_reg_4817 <= grp_fu_533_p2;
tmp_11_s_reg_4827 <= grp_fu_537_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0))) begin
tmp_118_reg_4013 <= {{bufo_Dout_A[95:64]}};
tmp_153_reg_4018 <= {{bufo_Dout_A[127:96]}};
tmp_188_reg_4023 <= {{bufo_Dout_A[159:128]}};
tmp_223_reg_4028 <= {{bufo_Dout_A[191:160]}};
tmp_258_reg_4033 <= {{bufo_Dout_A[223:192]}};
tmp_293_reg_4038 <= {{bufo_Dout_A[255:224]}};
tmp_328_reg_4043 <= {{bufo_Dout_A[287:256]}};
tmp_363_reg_4048 <= {{bufo_Dout_A[319:288]}};
tmp_398_reg_4053 <= {{bufo_Dout_A[351:320]}};
tmp_433_reg_4058 <= {{bufo_Dout_A[383:352]}};
tmp_468_reg_4063 <= {{bufo_Dout_A[415:384]}};
tmp_503_reg_4068 <= {{bufo_Dout_A[447:416]}};
tmp_538_reg_4073 <= {{bufo_Dout_A[479:448]}};
tmp_573_reg_4078 <= {{bufo_Dout_A[511:480]}};
tmp_624_reg_3993 <= tmp_624_fu_1449_p2;
tmp_627_reg_3998 <= tmp_627_fu_1455_p1;
tmp_628_reg_4003 <= tmp_628_fu_1459_p1;
tmp_82_reg_4008 <= {{bufo_Dout_A[63:32]}};
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_10_reg_7147 <= grp_fu_497_p2;
tmp_11_10_10_reg_7267 <= grp_fu_537_p2;
tmp_11_11_10_reg_7277 <= grp_fu_541_p2;
tmp_11_12_10_reg_7287 <= grp_fu_545_p2;
tmp_11_13_10_reg_7297 <= grp_fu_549_p2;
tmp_11_14_10_reg_7307 <= grp_fu_553_p2;
tmp_11_15_10_reg_7317 <= grp_fu_557_p2;
tmp_11_1_10_reg_7177 <= grp_fu_501_p2;
tmp_11_2_10_reg_7187 <= grp_fu_505_p2;
tmp_11_3_10_reg_7197 <= grp_fu_509_p2;
tmp_11_4_10_reg_7207 <= grp_fu_513_p2;
tmp_11_5_10_reg_7217 <= grp_fu_517_p2;
tmp_11_6_10_reg_7227 <= grp_fu_521_p2;
tmp_11_7_10_reg_7237 <= grp_fu_525_p2;
tmp_11_8_10_reg_7247 <= grp_fu_529_p2;
tmp_11_9_10_reg_7257 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_11_reg_7327 <= grp_fu_497_p2;
tmp_11_10_11_reg_7377 <= grp_fu_537_p2;
tmp_11_11_11_reg_7382 <= grp_fu_541_p2;
tmp_11_12_11_reg_7387 <= grp_fu_545_p2;
tmp_11_13_11_reg_7392 <= grp_fu_549_p2;
tmp_11_14_11_reg_7397 <= grp_fu_553_p2;
tmp_11_15_11_reg_7402 <= grp_fu_557_p2;
tmp_11_1_11_reg_7332 <= grp_fu_501_p2;
tmp_11_2_11_reg_7337 <= grp_fu_505_p2;
tmp_11_3_11_reg_7342 <= grp_fu_509_p2;
tmp_11_4_11_reg_7347 <= grp_fu_513_p2;
tmp_11_5_11_reg_7352 <= grp_fu_517_p2;
tmp_11_6_11_reg_7357 <= grp_fu_521_p2;
tmp_11_7_11_reg_7362 <= grp_fu_525_p2;
tmp_11_8_11_reg_7367 <= grp_fu_529_p2;
tmp_11_9_11_reg_7372 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_12_reg_7407 <= grp_fu_497_p2;
tmp_11_10_12_reg_7457 <= grp_fu_537_p2;
tmp_11_11_12_reg_7462 <= grp_fu_541_p2;
tmp_11_12_12_reg_7467 <= grp_fu_545_p2;
tmp_11_13_12_reg_7472 <= grp_fu_549_p2;
tmp_11_14_12_reg_7477 <= grp_fu_553_p2;
tmp_11_15_12_reg_7482 <= grp_fu_557_p2;
tmp_11_1_12_reg_7412 <= grp_fu_501_p2;
tmp_11_2_12_reg_7417 <= grp_fu_505_p2;
tmp_11_3_12_reg_7422 <= grp_fu_509_p2;
tmp_11_4_12_reg_7427 <= grp_fu_513_p2;
tmp_11_5_12_reg_7432 <= grp_fu_517_p2;
tmp_11_6_12_reg_7437 <= grp_fu_521_p2;
tmp_11_7_12_reg_7442 <= grp_fu_525_p2;
tmp_11_8_12_reg_7447 <= grp_fu_529_p2;
tmp_11_9_12_reg_7452 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_13_reg_7487 <= grp_fu_497_p2;
tmp_11_10_13_reg_7537 <= grp_fu_537_p2;
tmp_11_11_13_reg_7542 <= grp_fu_541_p2;
tmp_11_12_13_reg_7547 <= grp_fu_545_p2;
tmp_11_13_13_reg_7552 <= grp_fu_549_p2;
tmp_11_14_13_reg_7557 <= grp_fu_553_p2;
tmp_11_15_13_reg_7562 <= grp_fu_557_p2;
tmp_11_1_13_reg_7492 <= grp_fu_501_p2;
tmp_11_2_13_reg_7497 <= grp_fu_505_p2;
tmp_11_3_13_reg_7502 <= grp_fu_509_p2;
tmp_11_4_13_reg_7507 <= grp_fu_513_p2;
tmp_11_5_13_reg_7512 <= grp_fu_517_p2;
tmp_11_6_13_reg_7517 <= grp_fu_521_p2;
tmp_11_7_13_reg_7522 <= grp_fu_525_p2;
tmp_11_8_13_reg_7527 <= grp_fu_529_p2;
tmp_11_9_13_reg_7532 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_14_reg_7567 <= grp_fu_497_p2;
tmp_11_10_14_reg_7617 <= grp_fu_537_p2;
tmp_11_11_14_reg_7622 <= grp_fu_541_p2;
tmp_11_12_14_reg_7627 <= grp_fu_545_p2;
tmp_11_13_14_reg_7632 <= grp_fu_549_p2;
tmp_11_14_14_reg_7637 <= grp_fu_553_p2;
tmp_11_15_14_reg_7642 <= grp_fu_557_p2;
tmp_11_1_14_reg_7572 <= grp_fu_501_p2;
tmp_11_2_14_reg_7577 <= grp_fu_505_p2;
tmp_11_3_14_reg_7582 <= grp_fu_509_p2;
tmp_11_4_14_reg_7587 <= grp_fu_513_p2;
tmp_11_5_14_reg_7592 <= grp_fu_517_p2;
tmp_11_6_14_reg_7597 <= grp_fu_521_p2;
tmp_11_7_14_reg_7602 <= grp_fu_525_p2;
tmp_11_8_14_reg_7607 <= grp_fu_529_p2;
tmp_11_9_14_reg_7612 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0))) begin
tmp_11_0_1_reg_4902 <= grp_fu_497_p2;
tmp_11_10_1_reg_5077 <= grp_fu_537_p2;
tmp_11_11_1_reg_5092 <= grp_fu_541_p2;
tmp_11_12_1_reg_5107 <= grp_fu_545_p2;
tmp_11_13_1_reg_5122 <= grp_fu_549_p2;
tmp_11_14_1_reg_5137 <= grp_fu_553_p2;
tmp_11_15_1_reg_5152 <= grp_fu_557_p2;
tmp_11_1_1_reg_4942 <= grp_fu_501_p2;
tmp_11_2_1_reg_4957 <= grp_fu_505_p2;
tmp_11_3_1_reg_4972 <= grp_fu_509_p2;
tmp_11_4_1_reg_4987 <= grp_fu_513_p2;
tmp_11_5_1_reg_5002 <= grp_fu_517_p2;
tmp_11_6_1_reg_5017 <= grp_fu_521_p2;
tmp_11_7_1_reg_5032 <= grp_fu_525_p2;
tmp_11_8_1_reg_5047 <= grp_fu_529_p2;
tmp_11_9_1_reg_5062 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0))) begin
tmp_11_0_2_reg_5172 <= grp_fu_497_p2;
tmp_11_10_2_reg_5297 <= grp_fu_537_p2;
tmp_11_11_2_reg_5307 <= grp_fu_541_p2;
tmp_11_12_2_reg_5317 <= grp_fu_545_p2;
tmp_11_13_2_reg_5327 <= grp_fu_549_p2;
tmp_11_14_2_reg_5337 <= grp_fu_553_p2;
tmp_11_15_2_reg_5347 <= grp_fu_557_p2;
tmp_11_1_2_reg_5207 <= grp_fu_501_p2;
tmp_11_2_2_reg_5217 <= grp_fu_505_p2;
tmp_11_3_2_reg_5227 <= grp_fu_509_p2;
tmp_11_4_2_reg_5237 <= grp_fu_513_p2;
tmp_11_5_2_reg_5247 <= grp_fu_517_p2;
tmp_11_6_2_reg_5257 <= grp_fu_521_p2;
tmp_11_7_2_reg_5267 <= grp_fu_525_p2;
tmp_11_8_2_reg_5277 <= grp_fu_529_p2;
tmp_11_9_2_reg_5287 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
tmp_11_0_3_reg_5372 <= grp_fu_497_p2;
tmp_11_10_3_reg_5497 <= grp_fu_537_p2;
tmp_11_11_3_reg_5507 <= grp_fu_541_p2;
tmp_11_12_3_reg_5517 <= grp_fu_545_p2;
tmp_11_13_3_reg_5527 <= grp_fu_549_p2;
tmp_11_14_3_reg_5537 <= grp_fu_553_p2;
tmp_11_15_3_reg_5547 <= grp_fu_557_p2;
tmp_11_1_3_reg_5407 <= grp_fu_501_p2;
tmp_11_2_3_reg_5417 <= grp_fu_505_p2;
tmp_11_3_3_reg_5427 <= grp_fu_509_p2;
tmp_11_4_3_reg_5437 <= grp_fu_513_p2;
tmp_11_5_3_reg_5447 <= grp_fu_517_p2;
tmp_11_6_3_reg_5457 <= grp_fu_521_p2;
tmp_11_7_3_reg_5467 <= grp_fu_525_p2;
tmp_11_8_3_reg_5477 <= grp_fu_529_p2;
tmp_11_9_3_reg_5487 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
tmp_11_0_7_reg_6347 <= grp_fu_497_p2;
tmp_11_10_7_reg_6467 <= grp_fu_537_p2;
tmp_11_11_7_reg_6477 <= grp_fu_541_p2;
tmp_11_12_7_reg_6487 <= grp_fu_545_p2;
tmp_11_13_7_reg_6497 <= grp_fu_549_p2;
tmp_11_14_7_reg_6507 <= grp_fu_553_p2;
tmp_11_15_7_reg_6517 <= grp_fu_557_p2;
tmp_11_1_7_reg_6377 <= grp_fu_501_p2;
tmp_11_2_7_reg_6387 <= grp_fu_505_p2;
tmp_11_3_7_reg_6397 <= grp_fu_509_p2;
tmp_11_4_7_reg_6407 <= grp_fu_513_p2;
tmp_11_5_7_reg_6417 <= grp_fu_517_p2;
tmp_11_6_7_reg_6427 <= grp_fu_521_p2;
tmp_11_7_7_reg_6437 <= grp_fu_525_p2;
tmp_11_8_7_reg_6447 <= grp_fu_529_p2;
tmp_11_9_7_reg_6457 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_8_reg_6527 <= grp_fu_497_p2;
tmp_11_10_8_reg_6647 <= grp_fu_537_p2;
tmp_11_11_8_reg_6657 <= grp_fu_541_p2;
tmp_11_12_8_reg_6667 <= grp_fu_545_p2;
tmp_11_13_8_reg_6677 <= grp_fu_549_p2;
tmp_11_14_8_reg_6687 <= grp_fu_553_p2;
tmp_11_15_8_reg_6697 <= grp_fu_557_p2;
tmp_11_1_8_reg_6557 <= grp_fu_501_p2;
tmp_11_2_8_reg_6567 <= grp_fu_505_p2;
tmp_11_3_8_reg_6577 <= grp_fu_509_p2;
tmp_11_4_8_reg_6587 <= grp_fu_513_p2;
tmp_11_5_8_reg_6597 <= grp_fu_517_p2;
tmp_11_6_8_reg_6607 <= grp_fu_521_p2;
tmp_11_7_8_reg_6617 <= grp_fu_525_p2;
tmp_11_8_8_reg_6627 <= grp_fu_529_p2;
tmp_11_9_8_reg_6637 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_9_reg_6712 <= grp_fu_497_p2;
tmp_11_10_9_reg_6882 <= grp_fu_537_p2;
tmp_11_11_9_reg_6897 <= grp_fu_541_p2;
tmp_11_12_9_reg_6912 <= grp_fu_545_p2;
tmp_11_13_9_reg_6927 <= grp_fu_549_p2;
tmp_11_14_9_reg_6942 <= grp_fu_553_p2;
tmp_11_15_9_reg_6957 <= grp_fu_557_p2;
tmp_11_1_9_reg_6747 <= grp_fu_501_p2;
tmp_11_2_9_reg_6762 <= grp_fu_505_p2;
tmp_11_3_9_reg_6777 <= grp_fu_509_p2;
tmp_11_4_9_reg_6792 <= grp_fu_513_p2;
tmp_11_5_9_reg_6807 <= grp_fu_517_p2;
tmp_11_6_9_reg_6822 <= grp_fu_521_p2;
tmp_11_7_9_reg_6837 <= grp_fu_525_p2;
tmp_11_8_9_reg_6852 <= grp_fu_529_p2;
tmp_11_9_9_reg_6867 <= grp_fu_533_p2;
tmp_12_10_reg_6892 <= grp_fu_477_p2;
tmp_12_11_reg_6907 <= grp_fu_481_p2;
tmp_12_12_reg_6922 <= grp_fu_485_p2;
tmp_12_13_reg_6937 <= grp_fu_489_p2;
tmp_12_14_reg_6952 <= grp_fu_493_p2;
tmp_12_1_reg_6742 <= grp_fu_437_p2;
tmp_12_2_reg_6757 <= grp_fu_441_p2;
tmp_12_3_reg_6772 <= grp_fu_445_p2;
tmp_12_4_reg_6787 <= grp_fu_449_p2;
tmp_12_5_reg_6802 <= grp_fu_453_p2;
tmp_12_6_reg_6817 <= grp_fu_457_p2;
tmp_12_7_reg_6832 <= grp_fu_461_p2;
tmp_12_8_reg_6847 <= grp_fu_465_p2;
tmp_12_9_reg_6862 <= grp_fu_469_p2;
tmp_12_s_reg_6877 <= grp_fu_473_p2;
tmp_607_reg_6707 <= grp_fu_433_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675))) begin
tmp_11_0_s_reg_6967 <= grp_fu_497_p2;
tmp_11_10_s_reg_7087 <= grp_fu_537_p2;
tmp_11_11_s_reg_7097 <= grp_fu_541_p2;
tmp_11_12_s_reg_7107 <= grp_fu_545_p2;
tmp_11_13_s_reg_7117 <= grp_fu_549_p2;
tmp_11_14_s_reg_7127 <= grp_fu_553_p2;
tmp_11_15_s_reg_7137 <= grp_fu_557_p2;
tmp_11_1_s_reg_6997 <= grp_fu_501_p2;
tmp_11_2_s_reg_7007 <= grp_fu_505_p2;
tmp_11_3_s_reg_7017 <= grp_fu_509_p2;
tmp_11_4_s_reg_7027 <= grp_fu_513_p2;
tmp_11_5_s_reg_7037 <= grp_fu_517_p2;
tmp_11_6_s_reg_7047 <= grp_fu_521_p2;
tmp_11_7_s_reg_7057 <= grp_fu_525_p2;
tmp_11_8_s_reg_7067 <= grp_fu_529_p2;
tmp_11_9_s_reg_7077 <= grp_fu_533_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter7) & (1'd0 == ap_reg_pp0_iter7_exitcond_flatten2_reg_3675))) begin
tmp_12_0_10_reg_8367 <= grp_fu_433_p2;
tmp_12_10_10_reg_8417 <= grp_fu_473_p2;
tmp_12_11_10_reg_8422 <= grp_fu_477_p2;
tmp_12_12_10_reg_8427 <= grp_fu_481_p2;
tmp_12_13_10_reg_8432 <= grp_fu_485_p2;
tmp_12_14_10_reg_8437 <= grp_fu_489_p2;
tmp_12_15_10_reg_8442 <= grp_fu_493_p2;
tmp_12_1_10_reg_8372 <= grp_fu_437_p2;
tmp_12_2_10_reg_8377 <= grp_fu_441_p2;
tmp_12_3_10_reg_8382 <= grp_fu_445_p2;
tmp_12_4_10_reg_8387 <= grp_fu_449_p2;
tmp_12_5_10_reg_8392 <= grp_fu_453_p2;
tmp_12_6_10_reg_8397 <= grp_fu_457_p2;
tmp_12_7_10_reg_8402 <= grp_fu_461_p2;
tmp_12_8_10_reg_8407 <= grp_fu_465_p2;
tmp_12_9_10_reg_8412 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'd0 == ap_reg_pp0_iter8_exitcond_flatten2_reg_3675))) begin
tmp_12_0_11_reg_8447 <= grp_fu_433_p2;
tmp_12_10_11_reg_8497 <= grp_fu_473_p2;
tmp_12_11_11_reg_8502 <= grp_fu_477_p2;
tmp_12_12_11_reg_8507 <= grp_fu_481_p2;
tmp_12_13_11_reg_8512 <= grp_fu_485_p2;
tmp_12_14_11_reg_8517 <= grp_fu_489_p2;
tmp_12_15_11_reg_8522 <= grp_fu_493_p2;
tmp_12_1_11_reg_8452 <= grp_fu_437_p2;
tmp_12_2_11_reg_8457 <= grp_fu_441_p2;
tmp_12_3_11_reg_8462 <= grp_fu_445_p2;
tmp_12_4_11_reg_8467 <= grp_fu_449_p2;
tmp_12_5_11_reg_8472 <= grp_fu_453_p2;
tmp_12_6_11_reg_8477 <= grp_fu_457_p2;
tmp_12_7_11_reg_8482 <= grp_fu_461_p2;
tmp_12_8_11_reg_8487 <= grp_fu_465_p2;
tmp_12_9_11_reg_8492 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'd0 == ap_reg_pp0_iter8_exitcond_flatten2_reg_3675))) begin
tmp_12_0_12_reg_8527 <= grp_fu_433_p2;
tmp_12_10_12_reg_8577 <= grp_fu_473_p2;
tmp_12_11_12_reg_8582 <= grp_fu_477_p2;
tmp_12_12_12_reg_8587 <= grp_fu_481_p2;
tmp_12_13_12_reg_8592 <= grp_fu_485_p2;
tmp_12_14_12_reg_8597 <= grp_fu_489_p2;
tmp_12_15_12_reg_8602 <= grp_fu_493_p2;
tmp_12_1_12_reg_8532 <= grp_fu_437_p2;
tmp_12_2_12_reg_8537 <= grp_fu_441_p2;
tmp_12_3_12_reg_8542 <= grp_fu_445_p2;
tmp_12_4_12_reg_8547 <= grp_fu_449_p2;
tmp_12_5_12_reg_8552 <= grp_fu_453_p2;
tmp_12_6_12_reg_8557 <= grp_fu_457_p2;
tmp_12_7_12_reg_8562 <= grp_fu_461_p2;
tmp_12_8_12_reg_8567 <= grp_fu_465_p2;
tmp_12_9_12_reg_8572 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_enable_reg_pp0_iter9) & (1'd0 == ap_reg_pp0_iter9_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
tmp_12_0_13_reg_8607 <= grp_fu_433_p2;
tmp_12_10_13_reg_8657 <= grp_fu_473_p2;
tmp_12_11_13_reg_8662 <= grp_fu_477_p2;
tmp_12_12_13_reg_8667 <= grp_fu_481_p2;
tmp_12_13_13_reg_8672 <= grp_fu_485_p2;
tmp_12_14_13_reg_8677 <= grp_fu_489_p2;
tmp_12_15_13_reg_8682 <= grp_fu_493_p2;
tmp_12_1_13_reg_8612 <= grp_fu_437_p2;
tmp_12_2_13_reg_8617 <= grp_fu_441_p2;
tmp_12_3_13_reg_8622 <= grp_fu_445_p2;
tmp_12_4_13_reg_8627 <= grp_fu_449_p2;
tmp_12_5_13_reg_8632 <= grp_fu_453_p2;
tmp_12_6_13_reg_8637 <= grp_fu_457_p2;
tmp_12_7_13_reg_8642 <= grp_fu_461_p2;
tmp_12_8_13_reg_8647 <= grp_fu_465_p2;
tmp_12_9_13_reg_8652 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2) & (1'd0 == ap_reg_pp0_iter2_exitcond_flatten2_reg_3675))) begin
tmp_12_0_2_reg_7647 <= grp_fu_433_p2;
tmp_12_10_2_reg_7697 <= grp_fu_473_p2;
tmp_12_11_2_reg_7702 <= grp_fu_477_p2;
tmp_12_12_2_reg_7707 <= grp_fu_481_p2;
tmp_12_13_2_reg_7712 <= grp_fu_485_p2;
tmp_12_14_2_reg_7717 <= grp_fu_489_p2;
tmp_12_15_2_reg_7722 <= grp_fu_493_p2;
tmp_12_1_2_reg_7652 <= grp_fu_437_p2;
tmp_12_2_2_reg_7657 <= grp_fu_441_p2;
tmp_12_3_2_reg_7662 <= grp_fu_445_p2;
tmp_12_4_2_reg_7667 <= grp_fu_449_p2;
tmp_12_5_2_reg_7672 <= grp_fu_453_p2;
tmp_12_6_2_reg_7677 <= grp_fu_457_p2;
tmp_12_7_2_reg_7682 <= grp_fu_461_p2;
tmp_12_8_2_reg_7687 <= grp_fu_465_p2;
tmp_12_9_2_reg_7692 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter3) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten2_reg_3675))) begin
tmp_12_0_3_reg_7727 <= grp_fu_433_p2;
tmp_12_10_3_reg_7777 <= grp_fu_473_p2;
tmp_12_11_3_reg_7782 <= grp_fu_477_p2;
tmp_12_12_3_reg_7787 <= grp_fu_481_p2;
tmp_12_13_3_reg_7792 <= grp_fu_485_p2;
tmp_12_14_3_reg_7797 <= grp_fu_489_p2;
tmp_12_15_3_reg_7802 <= grp_fu_493_p2;
tmp_12_1_3_reg_7732 <= grp_fu_437_p2;
tmp_12_2_3_reg_7737 <= grp_fu_441_p2;
tmp_12_3_3_reg_7742 <= grp_fu_445_p2;
tmp_12_4_3_reg_7747 <= grp_fu_449_p2;
tmp_12_5_3_reg_7752 <= grp_fu_453_p2;
tmp_12_6_3_reg_7757 <= grp_fu_457_p2;
tmp_12_7_3_reg_7762 <= grp_fu_461_p2;
tmp_12_8_3_reg_7767 <= grp_fu_465_p2;
tmp_12_9_3_reg_7772 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter3) & (1'd0 == ap_reg_pp0_iter3_exitcond_flatten2_reg_3675))) begin
tmp_12_0_4_reg_7807 <= grp_fu_433_p2;
tmp_12_10_4_reg_7857 <= grp_fu_473_p2;
tmp_12_11_4_reg_7862 <= grp_fu_477_p2;
tmp_12_12_4_reg_7867 <= grp_fu_481_p2;
tmp_12_13_4_reg_7872 <= grp_fu_485_p2;
tmp_12_14_4_reg_7877 <= grp_fu_489_p2;
tmp_12_15_4_reg_7882 <= grp_fu_493_p2;
tmp_12_1_4_reg_7812 <= grp_fu_437_p2;
tmp_12_2_4_reg_7817 <= grp_fu_441_p2;
tmp_12_3_4_reg_7822 <= grp_fu_445_p2;
tmp_12_4_4_reg_7827 <= grp_fu_449_p2;
tmp_12_5_4_reg_7832 <= grp_fu_453_p2;
tmp_12_6_4_reg_7837 <= grp_fu_457_p2;
tmp_12_7_4_reg_7842 <= grp_fu_461_p2;
tmp_12_8_4_reg_7847 <= grp_fu_465_p2;
tmp_12_9_4_reg_7852 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter4) & (1'd0 == ap_reg_pp0_iter4_exitcond_flatten2_reg_3675))) begin
tmp_12_0_5_reg_7887 <= grp_fu_433_p2;
tmp_12_10_5_reg_7937 <= grp_fu_473_p2;
tmp_12_11_5_reg_7942 <= grp_fu_477_p2;
tmp_12_12_5_reg_7947 <= grp_fu_481_p2;
tmp_12_13_5_reg_7952 <= grp_fu_485_p2;
tmp_12_14_5_reg_7957 <= grp_fu_489_p2;
tmp_12_15_5_reg_7962 <= grp_fu_493_p2;
tmp_12_1_5_reg_7892 <= grp_fu_437_p2;
tmp_12_2_5_reg_7897 <= grp_fu_441_p2;
tmp_12_3_5_reg_7902 <= grp_fu_445_p2;
tmp_12_4_5_reg_7907 <= grp_fu_449_p2;
tmp_12_5_5_reg_7912 <= grp_fu_453_p2;
tmp_12_6_5_reg_7917 <= grp_fu_457_p2;
tmp_12_7_5_reg_7922 <= grp_fu_461_p2;
tmp_12_8_5_reg_7927 <= grp_fu_465_p2;
tmp_12_9_5_reg_7932 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter4) & (1'd0 == ap_reg_pp0_iter4_exitcond_flatten2_reg_3675))) begin
tmp_12_0_6_reg_7967 <= grp_fu_433_p2;
tmp_12_10_6_reg_8017 <= grp_fu_473_p2;
tmp_12_11_6_reg_8022 <= grp_fu_477_p2;
tmp_12_12_6_reg_8027 <= grp_fu_481_p2;
tmp_12_13_6_reg_8032 <= grp_fu_485_p2;
tmp_12_14_6_reg_8037 <= grp_fu_489_p2;
tmp_12_15_6_reg_8042 <= grp_fu_493_p2;
tmp_12_1_6_reg_7972 <= grp_fu_437_p2;
tmp_12_2_6_reg_7977 <= grp_fu_441_p2;
tmp_12_3_6_reg_7982 <= grp_fu_445_p2;
tmp_12_4_6_reg_7987 <= grp_fu_449_p2;
tmp_12_5_6_reg_7992 <= grp_fu_453_p2;
tmp_12_6_6_reg_7997 <= grp_fu_457_p2;
tmp_12_7_6_reg_8002 <= grp_fu_461_p2;
tmp_12_8_6_reg_8007 <= grp_fu_465_p2;
tmp_12_9_6_reg_8012 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter5) & (1'd0 == ap_reg_pp0_iter5_exitcond_flatten2_reg_3675))) begin
tmp_12_0_7_reg_8047 <= grp_fu_433_p2;
tmp_12_10_7_reg_8097 <= grp_fu_473_p2;
tmp_12_11_7_reg_8102 <= grp_fu_477_p2;
tmp_12_12_7_reg_8107 <= grp_fu_481_p2;
tmp_12_13_7_reg_8112 <= grp_fu_485_p2;
tmp_12_14_7_reg_8117 <= grp_fu_489_p2;
tmp_12_15_7_reg_8122 <= grp_fu_493_p2;
tmp_12_1_7_reg_8052 <= grp_fu_437_p2;
tmp_12_2_7_reg_8057 <= grp_fu_441_p2;
tmp_12_3_7_reg_8062 <= grp_fu_445_p2;
tmp_12_4_7_reg_8067 <= grp_fu_449_p2;
tmp_12_5_7_reg_8072 <= grp_fu_453_p2;
tmp_12_6_7_reg_8077 <= grp_fu_457_p2;
tmp_12_7_7_reg_8082 <= grp_fu_461_p2;
tmp_12_8_7_reg_8087 <= grp_fu_465_p2;
tmp_12_9_7_reg_8092 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter5) & (1'd0 == ap_reg_pp0_iter5_exitcond_flatten2_reg_3675))) begin
tmp_12_0_8_reg_8127 <= grp_fu_433_p2;
tmp_12_10_8_reg_8177 <= grp_fu_473_p2;
tmp_12_11_8_reg_8182 <= grp_fu_477_p2;
tmp_12_12_8_reg_8187 <= grp_fu_481_p2;
tmp_12_13_8_reg_8192 <= grp_fu_485_p2;
tmp_12_14_8_reg_8197 <= grp_fu_489_p2;
tmp_12_15_8_reg_8202 <= grp_fu_493_p2;
tmp_12_1_8_reg_8132 <= grp_fu_437_p2;
tmp_12_2_8_reg_8137 <= grp_fu_441_p2;
tmp_12_3_8_reg_8142 <= grp_fu_445_p2;
tmp_12_4_8_reg_8147 <= grp_fu_449_p2;
tmp_12_5_8_reg_8152 <= grp_fu_453_p2;
tmp_12_6_8_reg_8157 <= grp_fu_457_p2;
tmp_12_7_8_reg_8162 <= grp_fu_461_p2;
tmp_12_8_8_reg_8167 <= grp_fu_465_p2;
tmp_12_9_8_reg_8172 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6) & (1'd0 == ap_reg_pp0_iter6_exitcond_flatten2_reg_3675))) begin
tmp_12_0_9_reg_8207 <= grp_fu_433_p2;
tmp_12_10_9_reg_8257 <= grp_fu_473_p2;
tmp_12_11_9_reg_8262 <= grp_fu_477_p2;
tmp_12_12_9_reg_8267 <= grp_fu_481_p2;
tmp_12_13_9_reg_8272 <= grp_fu_485_p2;
tmp_12_14_9_reg_8277 <= grp_fu_489_p2;
tmp_12_15_9_reg_8282 <= grp_fu_493_p2;
tmp_12_1_9_reg_8212 <= grp_fu_437_p2;
tmp_12_2_9_reg_8217 <= grp_fu_441_p2;
tmp_12_3_9_reg_8222 <= grp_fu_445_p2;
tmp_12_4_9_reg_8227 <= grp_fu_449_p2;
tmp_12_5_9_reg_8232 <= grp_fu_453_p2;
tmp_12_6_9_reg_8237 <= grp_fu_457_p2;
tmp_12_7_9_reg_8242 <= grp_fu_461_p2;
tmp_12_8_9_reg_8247 <= grp_fu_465_p2;
tmp_12_9_9_reg_8252 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == ap_reg_pp0_iter6_exitcond_flatten2_reg_3675) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
tmp_12_0_s_reg_8287 <= grp_fu_433_p2;
tmp_12_10_s_reg_8337 <= grp_fu_473_p2;
tmp_12_11_s_reg_8342 <= grp_fu_477_p2;
tmp_12_12_s_reg_8347 <= grp_fu_481_p2;
tmp_12_13_s_reg_8352 <= grp_fu_485_p2;
tmp_12_14_s_reg_8357 <= grp_fu_489_p2;
tmp_12_15_s_reg_8362 <= grp_fu_493_p2;
tmp_12_1_s_reg_8292 <= grp_fu_437_p2;
tmp_12_2_s_reg_8297 <= grp_fu_441_p2;
tmp_12_3_s_reg_8302 <= grp_fu_445_p2;
tmp_12_4_s_reg_8307 <= grp_fu_449_p2;
tmp_12_5_s_reg_8312 <= grp_fu_453_p2;
tmp_12_6_s_reg_8317 <= grp_fu_457_p2;
tmp_12_7_s_reg_8322 <= grp_fu_461_p2;
tmp_12_8_s_reg_8327 <= grp_fu_465_p2;
tmp_12_9_s_reg_8332 <= grp_fu_469_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0))) begin
tmp_21_reg_4132 <= {{bufi_Dout_A[63:32]}};
tmp_25_reg_4137 <= {{bufi_Dout_A[95:64]}};
tmp_29_reg_4147 <= {{bufi_Dout_A[127:96]}};
tmp_33_reg_4152 <= {{bufi_Dout_A[159:128]}};
tmp_37_reg_4157 <= {{bufi_Dout_A[191:160]}};
tmp_41_reg_4162 <= {{bufi_Dout_A[223:192]}};
tmp_45_reg_4167 <= {{bufi_Dout_A[255:224]}};
tmp_49_reg_4172 <= {{bufi_Dout_A[287:256]}};
tmp_53_reg_4177 <= {{bufi_Dout_A[319:288]}};
tmp_57_reg_4182 <= {{bufi_Dout_A[351:320]}};
tmp_61_reg_4187 <= {{bufi_Dout_A[383:352]}};
tmp_626_reg_4127 <= tmp_626_fu_1657_p1;
tmp_630_reg_4142 <= tmp_630_fu_1681_p1;
tmp_63_reg_4122 <= tmp_63_fu_1652_p2;
tmp_65_reg_4192 <= {{bufi_Dout_A[415:384]}};
tmp_69_reg_4197 <= {{bufi_Dout_A[447:416]}};
tmp_73_reg_4202 <= {{bufi_Dout_A[479:448]}};
tmp_77_reg_4207 <= {{bufi_Dout_A[511:480]}};
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0))) begin
tmp_2_cast1_reg_4442[5 : 0] <= tmp_2_cast1_fu_2047_p1[5 : 0];
tmp_4_mid2_cast1_reg_4452[2 : 0] <= tmp_4_mid2_cast1_fu_2056_p1[2 : 0];
tmp_608_reg_4467 <= tmp_608_fu_2063_p2;
tmp_633_reg_4497 <= tmp_633_fu_2092_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0))) begin
tmp_2_cast2_reg_4083[5 : 0] <= tmp_2_cast2_fu_1613_p1[5 : 0];
tmp_4_mid2_cast3_reg_4090[2 : 0] <= tmp_4_mid2_cast3_fu_1622_p1[2 : 0];
tmp_59_reg_4102 <= tmp_59_fu_1629_p2;
tmp_629_reg_4112 <= tmp_629_fu_1639_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0) & (exitcond_flatten2_reg_3675 == 1'd0))) begin
tmp_51_reg_3967 <= tmp_51_fu_1395_p2;
tmp_55_reg_3972 <= tmp_55_fu_1400_p2;
tmp_625_reg_3983 <= tmp_625_fu_1410_p1;
tmp_8_cast_mid2_reg_3977 <= tmp_8_cast_mid2_fu_1405_p3;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0))) begin
tmp_609_reg_4582 <= tmp_609_fu_2180_p2;
tmp_634_reg_4612 <= tmp_634_fu_2208_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0))) begin
tmp_610_reg_4697 <= tmp_610_fu_2296_p2;
tmp_636_reg_4732 <= tmp_636_fu_2324_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0))) begin
tmp_611_reg_4892 <= tmp_611_fu_2412_p2;
tmp_637_reg_4932 <= tmp_637_fu_2444_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0))) begin
tmp_612_reg_5167 <= tmp_612_fu_2592_p2;
tmp_638_reg_5202 <= tmp_638_fu_2620_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
tmp_613_reg_5362 <= tmp_613_fu_2713_p2;
tmp_614_reg_5367 <= tmp_614_fu_2718_p2;
tmp_639_reg_5402 <= tmp_639_fu_2746_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0))) begin
tmp_631_reg_4252 <= tmp_631_fu_1862_p1;
tmp_67_reg_4217 <= tmp_67_fu_1829_p2;
tmp_71_reg_4222 <= tmp_71_fu_1834_p2;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0))) begin
tmp_632_reg_4362 <= tmp_632_fu_1968_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
tmp_640_reg_5592 <= tmp_640_fu_2852_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
tmp_641_reg_5857 <= tmp_641_fu_2943_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
tmp_642_reg_6117 <= tmp_642_fu_3045_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0) & (1'd0 == tmp_9_mid1_reg_3744))) begin
tmp_8_cast_mid5_reg_3797 <= tmp_8_cast_mid5_fu_1234_p3;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0) & (tmp_9_mid1_reg_3744 == 1'd1))) begin
tmp_8_mid1_reg_3857 <= tmp_8_mid1_fu_1329_p2;
end
end
always @ (*) begin
if ((exitcond_flatten2_fu_1051_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state2 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state161)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state161)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0))) begin
bufi_EN_A = 1'b1;
end else begin
bufi_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage14) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
bufo_Addr_A_orig = ap_reg_pp0_iter9_bufo_addr_reg_3867;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
bufo_Addr_A_orig = bufo_addr_reg_3867;
end else begin
bufo_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage5_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9)))) begin
bufo_EN_A = 1'b1;
end else begin
bufo_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter9) & (1'd0 == ap_reg_pp0_iter9_exitcond_flatten2_reg_3675))) begin
bufo_WEN_A = 64'd18446744073709551615;
end else begin
bufo_WEN_A = 64'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_636_cast_fu_2916_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_635_cast_fu_2825_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_634_cast_fu_2709_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_633_cast_fu_2588_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_632_cast_fu_2408_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_631_cast_fu_2292_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_630_cast_fu_2176_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_628_cast_fu_2059_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_627_cast_fu_1941_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_626_cast_fu_1825_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_625_cast_fu_1648_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_624_cast_fu_1625_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_623_cast_fu_1414_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_622_cast_fu_1391_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_621_cast_fu_1293_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
bufw_Addr_A_orig = tmp_629_cast_fu_1278_p1;
end else begin
bufw_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage5_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0)))) begin
bufw_EN_A = 1'b1;
end else begin
bufw_EN_A = 1'b0;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
col_b_phi_fu_425_p4 = col_b_1_reg_3957;
end else begin
col_b_phi_fu_425_p4 = col_b_reg_421;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_13_reg_8607;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_12_reg_8527;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_11_reg_8447;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_10_reg_8367;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_s_reg_8287;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_9_reg_8207;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_8_reg_8127;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_7_reg_8047;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_6_reg_7967;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_5_reg_7887;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_4_reg_7807;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_3_reg_7727;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_12_0_2_reg_7647;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = reg_951;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_607_reg_6707;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_433_p0 = tmp_18_fu_2417_p1;
end else begin
grp_fu_433_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter8_tmp_11_0_14_reg_7567;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter8_tmp_11_0_13_reg_7487;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter7_tmp_11_0_12_reg_7407;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter7_tmp_11_0_11_reg_7327;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter6_tmp_11_0_10_reg_7147;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter6_tmp_11_0_s_reg_6967;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter5_tmp_11_0_9_reg_6712;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter5_tmp_11_0_8_reg_6527;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter4_tmp_11_0_7_reg_6347;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter4_tmp_11_0_6_reg_6087;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter3_tmp_11_0_5_reg_5827;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter3_tmp_11_0_4_reg_5562;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter2_tmp_11_0_3_reg_5372;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = ap_reg_pp0_iter1_tmp_11_0_2_reg_5172;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = tmp_11_0_1_reg_4902;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_433_p1 = tmp_116_reg_4702;
end else begin
grp_fu_433_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_13_reg_8612;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_12_reg_8532;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_11_reg_8452;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_10_reg_8372;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_s_reg_8292;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_9_reg_8212;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_8_reg_8132;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_7_reg_8052;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_6_reg_7972;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_5_reg_7892;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_4_reg_7812;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_3_reg_7732;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_2_reg_7652;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = reg_956;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_12_1_reg_6742;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_437_p0 = tmp_83_fu_2448_p1;
end else begin
grp_fu_437_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter8_tmp_11_1_14_reg_7572;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter8_tmp_11_1_13_reg_7492;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter7_tmp_11_1_12_reg_7412;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter7_tmp_11_1_11_reg_7332;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter6_tmp_11_1_10_reg_7177;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter6_tmp_11_1_s_reg_6997;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter5_tmp_11_1_9_reg_6747;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter5_tmp_11_1_8_reg_6557;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter4_tmp_11_1_7_reg_6377;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter4_tmp_11_1_6_reg_6122;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter3_tmp_11_1_5_reg_5862;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter3_tmp_11_1_4_reg_5597;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter2_tmp_11_1_3_reg_5407;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = ap_reg_pp0_iter1_tmp_11_1_2_reg_5207;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = tmp_11_1_1_reg_4942;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_437_p1 = tmp_11_1_reg_4737;
end else begin
grp_fu_437_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_13_reg_8617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_12_reg_8537;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_11_reg_8457;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_10_reg_8377;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_s_reg_8297;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_9_reg_8217;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_8_reg_8137;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_7_reg_8057;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_6_reg_7977;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_5_reg_7897;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_4_reg_7817;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_3_reg_7737;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_2_reg_7657;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = reg_961;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_12_2_reg_6757;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_441_p0 = tmp_119_fu_2457_p1;
end else begin
grp_fu_441_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter8_tmp_11_2_14_reg_7577;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter8_tmp_11_2_13_reg_7497;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter7_tmp_11_2_12_reg_7417;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter7_tmp_11_2_11_reg_7337;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter6_tmp_11_2_10_reg_7187;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter6_tmp_11_2_s_reg_7007;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter5_tmp_11_2_9_reg_6762;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter5_tmp_11_2_8_reg_6567;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter4_tmp_11_2_7_reg_6387;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter4_tmp_11_2_6_reg_6137;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter3_tmp_11_2_5_reg_5877;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter3_tmp_11_2_4_reg_5612;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter2_tmp_11_2_3_reg_5417;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = ap_reg_pp0_iter1_tmp_11_2_2_reg_5217;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = tmp_11_2_1_reg_4957;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_441_p1 = tmp_11_2_reg_4747;
end else begin
grp_fu_441_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_13_reg_8622;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_12_reg_8542;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_11_reg_8462;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_10_reg_8382;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_s_reg_8302;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_9_reg_8222;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_8_reg_8142;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_7_reg_8062;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_6_reg_7982;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_5_reg_7902;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_4_reg_7822;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_3_reg_7742;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_2_reg_7662;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = reg_966;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_12_3_reg_6772;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_445_p0 = tmp_154_fu_2466_p1;
end else begin
grp_fu_445_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter8_tmp_11_3_14_reg_7582;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter8_tmp_11_3_13_reg_7502;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter7_tmp_11_3_12_reg_7422;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter7_tmp_11_3_11_reg_7342;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter6_tmp_11_3_10_reg_7197;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter6_tmp_11_3_s_reg_7017;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter5_tmp_11_3_9_reg_6777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter5_tmp_11_3_8_reg_6577;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter4_tmp_11_3_7_reg_6397;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter4_tmp_11_3_6_reg_6152;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter3_tmp_11_3_5_reg_5892;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter3_tmp_11_3_4_reg_5627;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter2_tmp_11_3_3_reg_5427;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = ap_reg_pp0_iter1_tmp_11_3_2_reg_5227;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = tmp_11_3_1_reg_4972;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_445_p1 = tmp_11_3_reg_4757;
end else begin
grp_fu_445_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_13_reg_8627;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_12_reg_8547;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_11_reg_8467;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_10_reg_8387;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_s_reg_8307;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_9_reg_8227;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_8_reg_8147;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_7_reg_8067;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_6_reg_7987;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_5_reg_7907;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_4_reg_7827;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_3_reg_7747;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_2_reg_7667;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = reg_971;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_12_4_reg_6787;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_449_p0 = tmp_189_fu_2475_p1;
end else begin
grp_fu_449_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter8_tmp_11_4_14_reg_7587;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter8_tmp_11_4_13_reg_7507;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter7_tmp_11_4_12_reg_7427;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter7_tmp_11_4_11_reg_7347;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter6_tmp_11_4_10_reg_7207;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter6_tmp_11_4_s_reg_7027;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter5_tmp_11_4_9_reg_6792;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter5_tmp_11_4_8_reg_6587;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter4_tmp_11_4_7_reg_6407;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter4_tmp_11_4_6_reg_6167;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter3_tmp_11_4_5_reg_5907;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter3_tmp_11_4_4_reg_5642;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter2_tmp_11_4_3_reg_5437;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = ap_reg_pp0_iter1_tmp_11_4_2_reg_5237;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = tmp_11_4_1_reg_4987;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_449_p1 = tmp_11_4_reg_4767;
end else begin
grp_fu_449_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_13_reg_8632;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_12_reg_8552;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_11_reg_8472;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_10_reg_8392;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_s_reg_8312;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_9_reg_8232;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_8_reg_8152;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_7_reg_8072;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_6_reg_7992;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_5_reg_7912;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_4_reg_7832;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_3_reg_7752;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_2_reg_7672;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = reg_976;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_12_5_reg_6802;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_453_p0 = tmp_224_fu_2484_p1;
end else begin
grp_fu_453_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter8_tmp_11_5_14_reg_7592;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter8_tmp_11_5_13_reg_7512;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter7_tmp_11_5_12_reg_7432;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter7_tmp_11_5_11_reg_7352;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter6_tmp_11_5_10_reg_7217;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter6_tmp_11_5_s_reg_7037;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter5_tmp_11_5_9_reg_6807;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter5_tmp_11_5_8_reg_6597;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter4_tmp_11_5_7_reg_6417;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter4_tmp_11_5_6_reg_6182;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter3_tmp_11_5_5_reg_5922;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter3_tmp_11_5_4_reg_5657;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter2_tmp_11_5_3_reg_5447;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = ap_reg_pp0_iter1_tmp_11_5_2_reg_5247;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = tmp_11_5_1_reg_5002;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_453_p1 = tmp_11_5_reg_4777;
end else begin
grp_fu_453_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_13_reg_8637;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_12_reg_8557;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_11_reg_8477;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_10_reg_8397;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_s_reg_8317;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_9_reg_8237;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_8_reg_8157;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_7_reg_8077;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_6_reg_7997;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_5_reg_7917;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_4_reg_7837;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_3_reg_7757;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_2_reg_7677;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = reg_981;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_12_6_reg_6817;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_457_p0 = tmp_259_fu_2493_p1;
end else begin
grp_fu_457_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter8_tmp_11_6_14_reg_7597;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter8_tmp_11_6_13_reg_7517;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter7_tmp_11_6_12_reg_7437;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter7_tmp_11_6_11_reg_7357;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter6_tmp_11_6_10_reg_7227;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter6_tmp_11_6_s_reg_7047;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter5_tmp_11_6_9_reg_6822;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter5_tmp_11_6_8_reg_6607;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter4_tmp_11_6_7_reg_6427;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter4_tmp_11_6_6_reg_6197;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter3_tmp_11_6_5_reg_5937;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter3_tmp_11_6_4_reg_5672;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter2_tmp_11_6_3_reg_5457;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = ap_reg_pp0_iter1_tmp_11_6_2_reg_5257;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = tmp_11_6_1_reg_5017;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_457_p1 = tmp_11_6_reg_4787;
end else begin
grp_fu_457_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_13_reg_8642;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_12_reg_8562;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_11_reg_8482;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_10_reg_8402;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_s_reg_8322;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_9_reg_8242;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_8_reg_8162;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_7_reg_8082;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_6_reg_8002;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_5_reg_7922;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_4_reg_7842;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_3_reg_7762;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_2_reg_7682;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = reg_986;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_12_7_reg_6832;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_461_p0 = tmp_294_fu_2502_p1;
end else begin
grp_fu_461_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter8_tmp_11_7_14_reg_7602;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter8_tmp_11_7_13_reg_7522;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter7_tmp_11_7_12_reg_7442;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter7_tmp_11_7_11_reg_7362;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter6_tmp_11_7_10_reg_7237;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter6_tmp_11_7_s_reg_7057;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter5_tmp_11_7_9_reg_6837;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter5_tmp_11_7_8_reg_6617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter4_tmp_11_7_7_reg_6437;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter4_tmp_11_7_6_reg_6212;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter3_tmp_11_7_5_reg_5952;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter3_tmp_11_7_4_reg_5687;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter2_tmp_11_7_3_reg_5467;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = ap_reg_pp0_iter1_tmp_11_7_2_reg_5267;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = tmp_11_7_1_reg_5032;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_461_p1 = tmp_11_7_reg_4797;
end else begin
grp_fu_461_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_13_reg_8647;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_12_reg_8567;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_11_reg_8487;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_10_reg_8407;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_s_reg_8327;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_9_reg_8247;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_8_reg_8167;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_7_reg_8087;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_6_reg_8007;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_5_reg_7927;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_4_reg_7847;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_3_reg_7767;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_2_reg_7687;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = reg_991;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_12_8_reg_6847;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_465_p0 = tmp_329_fu_2511_p1;
end else begin
grp_fu_465_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter8_tmp_11_8_14_reg_7607;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter8_tmp_11_8_13_reg_7527;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter7_tmp_11_8_12_reg_7447;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter7_tmp_11_8_11_reg_7367;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter6_tmp_11_8_10_reg_7247;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter6_tmp_11_8_s_reg_7067;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter5_tmp_11_8_9_reg_6852;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter5_tmp_11_8_8_reg_6627;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter4_tmp_11_8_7_reg_6447;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter4_tmp_11_8_6_reg_6227;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter3_tmp_11_8_5_reg_5967;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter3_tmp_11_8_4_reg_5702;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter2_tmp_11_8_3_reg_5477;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = ap_reg_pp0_iter1_tmp_11_8_2_reg_5277;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = tmp_11_8_1_reg_5047;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_465_p1 = tmp_11_8_reg_4807;
end else begin
grp_fu_465_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_13_reg_8652;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_12_reg_8572;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_11_reg_8492;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_10_reg_8412;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_s_reg_8332;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_9_reg_8252;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_8_reg_8172;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_7_reg_8092;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_6_reg_8012;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_5_reg_7932;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_4_reg_7852;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_3_reg_7772;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_2_reg_7692;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = reg_996;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_12_9_reg_6862;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_469_p0 = tmp_364_fu_2520_p1;
end else begin
grp_fu_469_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter8_tmp_11_9_14_reg_7612;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter8_tmp_11_9_13_reg_7532;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter7_tmp_11_9_12_reg_7452;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter7_tmp_11_9_11_reg_7372;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter6_tmp_11_9_10_reg_7257;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter6_tmp_11_9_s_reg_7077;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter5_tmp_11_9_9_reg_6867;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter5_tmp_11_9_8_reg_6637;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter4_tmp_11_9_7_reg_6457;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter4_tmp_11_9_6_reg_6242;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter3_tmp_11_9_5_reg_5982;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter3_tmp_11_9_4_reg_5717;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter2_tmp_11_9_3_reg_5487;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = ap_reg_pp0_iter1_tmp_11_9_2_reg_5287;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = tmp_11_9_1_reg_5062;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_469_p1 = tmp_11_9_reg_4817;
end else begin
grp_fu_469_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_13_reg_8657;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_12_reg_8577;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_11_reg_8497;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_10_reg_8417;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_s_reg_8337;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_9_reg_8257;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_8_reg_8177;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_7_reg_8097;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_6_reg_8017;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_5_reg_7937;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_4_reg_7857;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_3_reg_7777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_10_2_reg_7697;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = reg_1001;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_12_s_reg_6877;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_473_p0 = tmp_399_fu_2529_p1;
end else begin
grp_fu_473_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter8_tmp_11_10_14_reg_7617;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter8_tmp_11_10_13_reg_7537;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter7_tmp_11_10_12_reg_7457;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter7_tmp_11_10_11_reg_7377;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter6_tmp_11_10_10_reg_7267;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter6_tmp_11_10_s_reg_7087;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter5_tmp_11_10_9_reg_6882;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter5_tmp_11_10_8_reg_6647;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter4_tmp_11_10_7_reg_6467;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter4_tmp_11_10_6_reg_6257;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter3_tmp_11_10_5_reg_5997;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter3_tmp_11_10_4_reg_5732;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter2_tmp_11_10_3_reg_5497;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = ap_reg_pp0_iter1_tmp_11_10_2_reg_5297;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = tmp_11_10_1_reg_5077;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_473_p1 = tmp_11_s_reg_4827;
end else begin
grp_fu_473_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_13_reg_8662;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_12_reg_8582;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_11_reg_8502;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_10_reg_8422;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_s_reg_8342;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_9_reg_8262;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_8_reg_8182;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_7_reg_8102;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_6_reg_8022;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_5_reg_7942;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_4_reg_7862;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_3_reg_7782;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_11_2_reg_7702;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = reg_1006;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_12_10_reg_6892;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_477_p0 = tmp_434_fu_2538_p1;
end else begin
grp_fu_477_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter8_tmp_11_11_14_reg_7622;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter8_tmp_11_11_13_reg_7542;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter7_tmp_11_11_12_reg_7462;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter7_tmp_11_11_11_reg_7382;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter6_tmp_11_11_10_reg_7277;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter6_tmp_11_11_s_reg_7097;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter5_tmp_11_11_9_reg_6897;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter5_tmp_11_11_8_reg_6657;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter4_tmp_11_11_7_reg_6477;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter4_tmp_11_11_6_reg_6272;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter3_tmp_11_11_5_reg_6012;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter3_tmp_11_11_4_reg_5747;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter2_tmp_11_11_3_reg_5507;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = ap_reg_pp0_iter1_tmp_11_11_2_reg_5307;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = tmp_11_11_1_reg_5092;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_477_p1 = tmp_11_10_reg_4837;
end else begin
grp_fu_477_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_13_reg_8667;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_12_reg_8587;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_11_reg_8507;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_10_reg_8427;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_s_reg_8347;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_9_reg_8267;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_8_reg_8187;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_7_reg_8107;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_6_reg_8027;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_5_reg_7947;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_4_reg_7867;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_3_reg_7787;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_12_2_reg_7707;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = reg_1011;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_12_11_reg_6907;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_481_p0 = tmp_469_fu_2547_p1;
end else begin
grp_fu_481_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter8_tmp_11_12_14_reg_7627;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter8_tmp_11_12_13_reg_7547;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter7_tmp_11_12_12_reg_7467;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter7_tmp_11_12_11_reg_7387;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter6_tmp_11_12_10_reg_7287;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter6_tmp_11_12_s_reg_7107;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter5_tmp_11_12_9_reg_6912;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter5_tmp_11_12_8_reg_6667;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter4_tmp_11_12_7_reg_6487;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter4_tmp_11_12_6_reg_6287;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter3_tmp_11_12_5_reg_6027;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter3_tmp_11_12_4_reg_5762;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter2_tmp_11_12_3_reg_5517;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = ap_reg_pp0_iter1_tmp_11_12_2_reg_5317;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = tmp_11_12_1_reg_5107;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_481_p1 = tmp_11_11_reg_4847;
end else begin
grp_fu_481_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_13_reg_8672;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_12_reg_8592;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_11_reg_8512;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_10_reg_8432;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_s_reg_8352;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_9_reg_8272;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_8_reg_8192;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_7_reg_8112;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_6_reg_8032;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_5_reg_7952;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_4_reg_7872;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_3_reg_7792;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_13_2_reg_7712;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = reg_1016;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_12_12_reg_6922;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_485_p0 = tmp_504_fu_2556_p1;
end else begin
grp_fu_485_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter8_tmp_11_13_14_reg_7632;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter8_tmp_11_13_13_reg_7552;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter7_tmp_11_13_12_reg_7472;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter7_tmp_11_13_11_reg_7392;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter6_tmp_11_13_10_reg_7297;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter6_tmp_11_13_s_reg_7117;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter5_tmp_11_13_9_reg_6927;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter5_tmp_11_13_8_reg_6677;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter4_tmp_11_13_7_reg_6497;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter4_tmp_11_13_6_reg_6302;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter3_tmp_11_13_5_reg_6042;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter3_tmp_11_13_4_reg_5777;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter2_tmp_11_13_3_reg_5527;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = ap_reg_pp0_iter1_tmp_11_13_2_reg_5327;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = tmp_11_13_1_reg_5122;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_485_p1 = tmp_11_12_reg_4857;
end else begin
grp_fu_485_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_13_reg_8677;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_12_reg_8597;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_11_reg_8517;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_10_reg_8437;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_s_reg_8357;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_9_reg_8277;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_8_reg_8197;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_7_reg_8117;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_6_reg_8037;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_5_reg_7957;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_4_reg_7877;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_3_reg_7797;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_14_2_reg_7717;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = reg_1021;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_12_13_reg_6937;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_489_p0 = tmp_539_fu_2565_p1;
end else begin
grp_fu_489_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter8_tmp_11_14_14_reg_7637;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter8_tmp_11_14_13_reg_7557;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter7_tmp_11_14_12_reg_7477;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter7_tmp_11_14_11_reg_7397;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter6_tmp_11_14_10_reg_7307;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter6_tmp_11_14_s_reg_7127;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter5_tmp_11_14_9_reg_6942;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter5_tmp_11_14_8_reg_6687;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter4_tmp_11_14_7_reg_6507;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter4_tmp_11_14_6_reg_6317;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter3_tmp_11_14_5_reg_6057;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter3_tmp_11_14_4_reg_5792;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter2_tmp_11_14_3_reg_5537;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = ap_reg_pp0_iter1_tmp_11_14_2_reg_5337;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = tmp_11_14_1_reg_5137;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_489_p1 = tmp_11_13_reg_4867;
end else begin
grp_fu_489_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_13_reg_8682;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_12_reg_8602;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_11_reg_8522;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_10_reg_8442;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_s_reg_8362;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_9_reg_8282;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_8_reg_8202;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_7_reg_8122;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_6_reg_8042;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_5_reg_7962;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_4_reg_7882;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_3_reg_7802;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_15_2_reg_7722;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = reg_1026;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_12_14_reg_6952;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_493_p0 = tmp_574_fu_2574_p1;
end else begin
grp_fu_493_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter8_tmp_11_15_14_reg_7642;
end else if (((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter8_tmp_11_15_13_reg_7562;
end else if (((1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter8) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter7_tmp_11_15_12_reg_7482;
end else if (((1'b1 == ap_CS_fsm_pp0_stage10) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter7_tmp_11_15_11_reg_7402;
end else if (((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter6_tmp_11_15_10_reg_7317;
end else if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter6) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter6_tmp_11_15_s_reg_7137;
end else if (((1'b1 == ap_CS_fsm_pp0_stage15) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter5_tmp_11_15_9_reg_6957;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter5_tmp_11_15_8_reg_6697;
end else if (((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter4_tmp_11_15_7_reg_6517;
end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter4_tmp_11_15_6_reg_6332;
end else if (((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter3_tmp_11_15_5_reg_6072;
end else if (((1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter3) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter3_tmp_11_15_4_reg_5807;
end else if (((1'b1 == ap_CS_fsm_pp0_stage9) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter2_tmp_11_15_3_reg_5547;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = ap_reg_pp0_iter1_tmp_11_15_2_reg_5347;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = tmp_11_15_1_reg_5152;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_493_p1 = tmp_11_14_reg_4877;
end else begin
grp_fu_493_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_76_fu_3486_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_72_fu_3403_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_68_fu_3320_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_64_fu_3222_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_60_fu_3124_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_56_fu_3022_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_52_fu_2920_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_48_fu_2829_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_44_fu_2723_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_40_fu_2597_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_36_fu_2421_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_32_fu_2301_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_28_fu_2185_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_24_fu_2069_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_20_fu_1945_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_497_p0 = tmp_14_fu_1839_p1;
end else begin
grp_fu_497_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_497_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_497_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_113_fu_3509_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_111_fu_3426_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_109_fu_3343_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_107_fu_3245_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_105_fu_3147_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_103_fu_3049_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_101_fu_2947_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_99_fu_2856_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_97_fu_2750_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_95_fu_2624_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_93_fu_2452_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_91_fu_2328_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_89_fu_2212_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_87_fu_2096_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_85_fu_1972_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_501_p0 = tmp_81_fu_1866_p1;
end else begin
grp_fu_501_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_501_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_501_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_149_fu_3513_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_147_fu_3430_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_145_fu_3347_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_143_fu_3250_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_141_fu_3152_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_139_fu_3054_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_137_fu_2952_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_135_fu_2860_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_133_fu_2755_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_131_fu_2629_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_129_fu_2461_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_127_fu_2333_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_125_fu_2217_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_123_fu_2101_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_121_fu_1977_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_505_p0 = tmp_117_fu_1871_p1;
end else begin
grp_fu_505_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_505_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_505_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_184_fu_3517_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_182_fu_3434_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_180_fu_3351_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_178_fu_3255_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_176_fu_3157_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_174_fu_3059_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_172_fu_2957_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_170_fu_2864_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_168_fu_2760_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_166_fu_2634_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_164_fu_2470_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_162_fu_2338_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_160_fu_2222_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_158_fu_2106_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_156_fu_1982_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_509_p0 = tmp_152_fu_1876_p1;
end else begin
grp_fu_509_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_509_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_509_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_219_fu_3521_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_217_fu_3438_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_215_fu_3355_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_213_fu_3260_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_211_fu_3162_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_209_fu_3064_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_207_fu_2962_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_205_fu_2868_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_203_fu_2765_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_201_fu_2639_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_199_fu_2479_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_197_fu_2343_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_195_fu_2227_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_193_fu_2111_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_191_fu_1987_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_513_p0 = tmp_187_fu_1881_p1;
end else begin
grp_fu_513_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_513_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_513_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_254_fu_3525_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_252_fu_3442_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_250_fu_3359_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_248_fu_3265_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_246_fu_3167_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_244_fu_3069_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_242_fu_2967_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_240_fu_2872_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_238_fu_2770_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_236_fu_2644_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_234_fu_2488_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_232_fu_2348_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_230_fu_2232_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_228_fu_2116_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_226_fu_1992_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_517_p0 = tmp_222_fu_1886_p1;
end else begin
grp_fu_517_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_517_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_517_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_289_fu_3529_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_287_fu_3446_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_285_fu_3363_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_283_fu_3270_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_281_fu_3172_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_279_fu_3074_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_277_fu_2972_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_275_fu_2876_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_273_fu_2775_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_271_fu_2649_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_269_fu_2497_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_267_fu_2353_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_265_fu_2237_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_263_fu_2121_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_261_fu_1997_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_521_p0 = tmp_257_fu_1891_p1;
end else begin
grp_fu_521_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_521_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_521_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_324_fu_3533_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_322_fu_3450_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_320_fu_3367_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_318_fu_3275_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_316_fu_3177_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_314_fu_3079_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_312_fu_2977_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_310_fu_2880_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_308_fu_2780_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_306_fu_2654_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_304_fu_2506_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_302_fu_2358_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_300_fu_2242_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_298_fu_2126_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_296_fu_2002_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_525_p0 = tmp_292_fu_1896_p1;
end else begin
grp_fu_525_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_525_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_525_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_359_fu_3537_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_357_fu_3454_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_355_fu_3371_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_353_fu_3280_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_351_fu_3182_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_349_fu_3084_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_347_fu_2982_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_345_fu_2884_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_343_fu_2785_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_341_fu_2659_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_339_fu_2515_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_337_fu_2363_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_335_fu_2247_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_333_fu_2131_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_331_fu_2007_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_529_p0 = tmp_327_fu_1901_p1;
end else begin
grp_fu_529_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_529_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_529_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_394_fu_3541_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_392_fu_3458_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_390_fu_3375_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_388_fu_3285_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_386_fu_3187_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_384_fu_3089_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_382_fu_2987_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_380_fu_2888_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_378_fu_2790_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_376_fu_2664_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_374_fu_2524_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_372_fu_2368_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_370_fu_2252_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_368_fu_2136_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_366_fu_2012_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_533_p0 = tmp_362_fu_1906_p1;
end else begin
grp_fu_533_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_533_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_533_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_429_fu_3545_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_427_fu_3462_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_425_fu_3379_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_423_fu_3290_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_421_fu_3192_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_419_fu_3094_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_417_fu_2992_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_415_fu_2892_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_413_fu_2795_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_411_fu_2669_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_409_fu_2533_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_407_fu_2373_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_405_fu_2257_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_403_fu_2141_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_401_fu_2017_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_537_p0 = tmp_397_fu_1911_p1;
end else begin
grp_fu_537_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_537_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_537_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_464_fu_3549_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_462_fu_3466_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_460_fu_3383_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_458_fu_3295_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_456_fu_3197_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_454_fu_3099_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_452_fu_2997_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_450_fu_2896_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_448_fu_2800_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_446_fu_2674_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_444_fu_2542_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_442_fu_2378_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_440_fu_2262_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_438_fu_2146_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_436_fu_2022_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_541_p0 = tmp_432_fu_1916_p1;
end else begin
grp_fu_541_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_541_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_541_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_499_fu_3553_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_497_fu_3470_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_495_fu_3387_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_493_fu_3300_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_491_fu_3202_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_489_fu_3104_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_487_fu_3002_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_485_fu_2900_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_483_fu_2805_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_481_fu_2679_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_479_fu_2551_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_477_fu_2383_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_475_fu_2267_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_473_fu_2151_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_471_fu_2027_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_545_p0 = tmp_467_fu_1921_p1;
end else begin
grp_fu_545_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_545_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_545_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_534_fu_3557_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_532_fu_3474_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_530_fu_3391_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_528_fu_3305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_526_fu_3207_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_524_fu_3109_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_522_fu_3007_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_520_fu_2904_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_518_fu_2810_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_516_fu_2684_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_514_fu_2560_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_512_fu_2388_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_510_fu_2272_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_508_fu_2156_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_506_fu_2032_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_549_p0 = tmp_502_fu_1926_p1;
end else begin
grp_fu_549_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_549_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_549_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_569_fu_3561_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_567_fu_3478_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_565_fu_3395_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_563_fu_3310_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_561_fu_3212_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_559_fu_3114_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_557_fu_3012_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_555_fu_2908_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_553_fu_2815_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_551_fu_2689_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_549_fu_2569_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_547_fu_2393_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_545_fu_2277_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_543_fu_2161_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_541_fu_2037_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_553_p0 = tmp_537_fu_1931_p1;
end else begin
grp_fu_553_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_553_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_553_p1 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_604_fu_3565_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_602_fu_3482_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_600_fu_3399_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_598_fu_3315_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_596_fu_3217_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_594_fu_3119_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_592_fu_3017_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_590_fu_2912_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_588_fu_2820_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_586_fu_2694_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_584_fu_2578_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_582_fu_2398_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_580_fu_2282_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_578_fu_2166_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_576_fu_2042_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_557_p0 = tmp_572_fu_1936_p1;
end else begin
grp_fu_557_p0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage8_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_78_fu_3490_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage7_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_74_fu_3407_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage6_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_70_fu_3324_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage5_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_66_fu_3226_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_62_fu_3128_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_58_fu_3026_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_54_fu_2924_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_50_fu_2833_p1;
end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_46_fu_2727_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage15) & (ap_block_pp0_stage15_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_42_fu_2601_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_block_pp0_stage14_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_38_fu_2425_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage13) & (ap_block_pp0_stage13_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_34_fu_2305_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage12) & (ap_block_pp0_stage12_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_30_fu_2189_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage11) & (ap_block_pp0_stage11_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_26_fu_2073_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage10) & (ap_block_pp0_stage10_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_22_fu_1949_p1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_block_pp0_stage9_flag00000000 == 1'b0))) begin
grp_fu_557_p1 = tmp_16_fu_1843_p1;
end else begin
grp_fu_557_p1 = 'bx;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
i_phi_fu_366_p4 = tmp_1_mid2_v_reg_3722;
end else begin
i_phi_fu_366_p4 = i_reg_362;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
indvar_flatten1_phi_fu_355_p4 = indvar_flatten_next2_reg_3679;
end else begin
indvar_flatten1_phi_fu_355_p4 = indvar_flatten1_reg_351;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
indvar_flatten2_phi_fu_378_p4 = indvar_flatten_next1_reg_3757;
end else begin
indvar_flatten2_phi_fu_378_p4 = indvar_flatten2_reg_374;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
indvar_flatten_phi_fu_401_p4 = indvar_flatten_next_reg_3809;
end else begin
indvar_flatten_phi_fu_401_p4 = indvar_flatten_reg_397;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == ap_reg_pp0_iter1_exitcond_flatten2_reg_3675) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0))) begin
j_phi_fu_389_p4 = tmp_4_mid2_reg_3783;
end else begin
j_phi_fu_389_p4 = j_reg_385;
end
end
always @ (*) begin
if (((exitcond_flatten2_reg_3675 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
row_b_phi_fu_413_p4 = row_b_mid2_reg_3862;
end else begin
row_b_phi_fu_413_p4 = row_b_reg_409;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten2_fu_1051_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_flatten2_fu_1051_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state161;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage1 : begin
if ((ap_block_pp0_stage1_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end
end
ap_ST_fsm_pp0_stage2 : begin
if ((ap_block_pp0_stage2_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end
end
ap_ST_fsm_pp0_stage3 : begin
if ((ap_block_pp0_stage3_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end
end
ap_ST_fsm_pp0_stage4 : begin
if ((ap_block_pp0_stage4_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end
end
ap_ST_fsm_pp0_stage5 : begin
if ((ap_block_pp0_stage5_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end
end
ap_ST_fsm_pp0_stage6 : begin
if ((ap_block_pp0_stage6_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end
end
ap_ST_fsm_pp0_stage7 : begin
if ((ap_block_pp0_stage7_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage8;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end
end
ap_ST_fsm_pp0_stage8 : begin
if ((ap_block_pp0_stage8_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage8;
end
end
ap_ST_fsm_pp0_stage9 : begin
if ((ap_block_pp0_stage9_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage10;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage9;
end
end
ap_ST_fsm_pp0_stage10 : begin
if ((ap_block_pp0_stage10_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage11;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage10;
end
end
ap_ST_fsm_pp0_stage11 : begin
if ((ap_block_pp0_stage11_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage12;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage11;
end
end
ap_ST_fsm_pp0_stage12 : begin
if ((ap_block_pp0_stage12_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage13;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage12;
end
end
ap_ST_fsm_pp0_stage13 : begin
if ((ap_block_pp0_stage13_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage14;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage13;
end
end
ap_ST_fsm_pp0_stage14 : begin
if (((ap_block_pp0_stage14_flag00011011 == 1'b0) & ~((1'b1 == ap_CS_fsm_pp0_stage14) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage14_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage15;
end else if (((1'b1 == ap_CS_fsm_pp0_stage14) & (1'b1 == ap_enable_reg_pp0_iter9) & (ap_block_pp0_stage14_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_state161;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage14;
end
end
ap_ST_fsm_pp0_stage15 : begin
if ((ap_block_pp0_stage15_flag00011011 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage15;
end
end
ap_ST_fsm_state161 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_pp0_stage10 = ap_CS_fsm[32'd11];
assign ap_CS_fsm_pp0_stage11 = ap_CS_fsm[32'd12];
assign ap_CS_fsm_pp0_stage12 = ap_CS_fsm[32'd13];
assign ap_CS_fsm_pp0_stage13 = ap_CS_fsm[32'd14];
assign ap_CS_fsm_pp0_stage14 = ap_CS_fsm[32'd15];
assign ap_CS_fsm_pp0_stage15 = ap_CS_fsm[32'd16];
assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5];
assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd8];
assign ap_CS_fsm_pp0_stage8 = ap_CS_fsm[32'd9];
assign ap_CS_fsm_pp0_stage9 = ap_CS_fsm[32'd10];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state161 = ap_CS_fsm[32'd17];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage10_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage10_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage10_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage11_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage11_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage11_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage12_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage12_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage12_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage13_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage13_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage13_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage14_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage14_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage14_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage15_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage15_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage15_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage8_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage8_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage8_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage9_flag00000000 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage9_flag00011001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage9_flag00011011 = ~(1'b1 == 1'b1);
assign ap_block_state100_pp0_stage2_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state101_pp0_stage3_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state102_pp0_stage4_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state103_pp0_stage5_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state104_pp0_stage6_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state105_pp0_stage7_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state106_pp0_stage8_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state107_pp0_stage9_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state108_pp0_stage10_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state109_pp0_stage11_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state10_pp0_stage8_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state110_pp0_stage12_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state111_pp0_stage13_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state112_pp0_stage14_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state113_pp0_stage15_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state114_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state115_pp0_stage1_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state116_pp0_stage2_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state117_pp0_stage3_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state118_pp0_stage4_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state119_pp0_stage5_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage9_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state120_pp0_stage6_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state121_pp0_stage7_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state122_pp0_stage8_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state123_pp0_stage9_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state124_pp0_stage10_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state125_pp0_stage11_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state126_pp0_stage12_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state127_pp0_stage13_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state128_pp0_stage14_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state129_pp0_stage15_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage10_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state130_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state131_pp0_stage1_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state132_pp0_stage2_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state133_pp0_stage3_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state134_pp0_stage4_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state135_pp0_stage5_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state136_pp0_stage6_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state137_pp0_stage7_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state138_pp0_stage8_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state139_pp0_stage9_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state13_pp0_stage11_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state140_pp0_stage10_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state141_pp0_stage11_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state142_pp0_stage12_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state143_pp0_stage13_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state144_pp0_stage14_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state145_pp0_stage15_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state146_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state147_pp0_stage1_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state148_pp0_stage2_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state149_pp0_stage3_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state14_pp0_stage12_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state150_pp0_stage4_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state151_pp0_stage5_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state152_pp0_stage6_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state153_pp0_stage7_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state154_pp0_stage8_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state155_pp0_stage9_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state156_pp0_stage10_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state157_pp0_stage11_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state158_pp0_stage12_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state159_pp0_stage13_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state15_pp0_stage13_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state160_pp0_stage14_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state16_pp0_stage14_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state17_pp0_stage15_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state18_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state19_pp0_stage1_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state20_pp0_stage2_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state21_pp0_stage3_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state22_pp0_stage4_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state23_pp0_stage5_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state24_pp0_stage6_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state25_pp0_stage7_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state26_pp0_stage8_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state27_pp0_stage9_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state28_pp0_stage10_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state29_pp0_stage11_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state30_pp0_stage12_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state31_pp0_stage13_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state32_pp0_stage14_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state33_pp0_stage15_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state34_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state35_pp0_stage1_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state36_pp0_stage2_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state37_pp0_stage3_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state38_pp0_stage4_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state39_pp0_stage5_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state40_pp0_stage6_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state41_pp0_stage7_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state42_pp0_stage8_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state43_pp0_stage9_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state44_pp0_stage10_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state45_pp0_stage11_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state46_pp0_stage12_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state47_pp0_stage13_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state48_pp0_stage14_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state49_pp0_stage15_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state50_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state51_pp0_stage1_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state52_pp0_stage2_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state53_pp0_stage3_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state54_pp0_stage4_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state55_pp0_stage5_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state56_pp0_stage6_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state57_pp0_stage7_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state58_pp0_stage8_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state59_pp0_stage9_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state60_pp0_stage10_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state61_pp0_stage11_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state62_pp0_stage12_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state63_pp0_stage13_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state64_pp0_stage14_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state65_pp0_stage15_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state66_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state67_pp0_stage1_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state68_pp0_stage2_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state69_pp0_stage3_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state70_pp0_stage4_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state71_pp0_stage5_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state72_pp0_stage6_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state73_pp0_stage7_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state74_pp0_stage8_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state75_pp0_stage9_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state76_pp0_stage10_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state77_pp0_stage11_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state78_pp0_stage12_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state79_pp0_stage13_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state80_pp0_stage14_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state81_pp0_stage15_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state82_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state83_pp0_stage1_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state84_pp0_stage2_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state85_pp0_stage3_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state86_pp0_stage4_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state87_pp0_stage5_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state88_pp0_stage6_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state89_pp0_stage7_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state90_pp0_stage8_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state91_pp0_stage9_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state92_pp0_stage10_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state93_pp0_stage11_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state94_pp0_stage12_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state95_pp0_stage13_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state96_pp0_stage14_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state97_pp0_stage15_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state98_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state99_pp0_stage1_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage7_iter0 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign bufi_Addr_A = bufi_Addr_A_orig << 32'd6;
assign bufi_Addr_A_orig = tmp_649_cast_fu_1635_p1;
assign bufi_Clk_A = ap_clk;
assign bufi_Din_A = 512'd0;
assign bufi_Rst_A = ap_rst_n_inv;
assign bufi_WEN_A = 64'd0;
assign bufo_Addr_A = bufo_Addr_A_orig << 32'd6;
assign bufo_Clk_A = ap_clk;
assign bufo_Din_A = {{{{{{{{{{{{{{{{tmp_605_fu_3629_p1}, {tmp_570_fu_3625_p1}}, {tmp_535_fu_3621_p1}}, {tmp_500_fu_3617_p1}}, {tmp_465_fu_3613_p1}}, {tmp_430_fu_3609_p1}}, {tmp_395_fu_3605_p1}}, {tmp_360_fu_3601_p1}}, {tmp_325_fu_3597_p1}}, {tmp_290_fu_3593_p1}}, {tmp_255_fu_3589_p1}}, {tmp_220_fu_3585_p1}}, {tmp_185_fu_3581_p1}}, {tmp_150_fu_3577_p1}}, {tmp_114_fu_3573_p1}}, {tmp_79_fu_3569_p1}};
assign bufo_Rst_A = ap_rst_n_inv;
assign bufw_Addr_A = bufw_Addr_A_orig << 32'd6;
assign bufw_Clk_A = ap_clk;
assign bufw_Din_A = 512'd0;
assign bufw_Rst_A = ap_rst_n_inv;
assign bufw_WEN_A = 64'd0;
assign col_b_1_fu_1371_p2 = (5'd1 + col_b_mid2_reg_3802);
assign col_b_cast1_cast_fu_1339_p1 = col_b_mid2_reg_3802;
assign col_b_mid2_fu_1250_p3 = ((tmp_616_fu_1245_p2[0:0] === 1'b1) ? 5'd0 : col_b_reg_421);
assign exitcond_flatten1_fu_1075_p2 = ((indvar_flatten_phi_fu_401_p4 == 10'd256) ? 1'b1 : 1'b0);
assign exitcond_flatten2_fu_1051_p2 = ((indvar_flatten1_phi_fu_355_p4 == 13'd6400) ? 1'b1 : 1'b0);
assign exitcond_flatten_fu_1063_p2 = ((indvar_flatten2_phi_fu_378_p4 == 12'd1280) ? 1'b1 : 1'b0);
assign exitcond_flatten_mid_fu_1117_p2 = (exitcond_flatten1_reg_3701 & not_exitcond_flatten_fu_1107_p2);
assign exitcond_flatten_not_fu_1128_p2 = (exitcond_flatten1_reg_3701 ^ 1'd1);
assign i_1_fu_1087_p2 = (3'd1 + i_reg_362);
assign indvar_flatten40_op_fu_1081_p2 = (12'd1 + indvar_flatten2_phi_fu_378_p4);
assign indvar_flatten_next1_fu_1150_p3 = ((exitcond_flatten_reg_3684[0:0] === 1'b1) ? 12'd1 : indvar_flatten40_op_reg_3707);
assign indvar_flatten_next2_fu_1057_p2 = (13'd1 + indvar_flatten1_phi_fu_355_p4);
assign indvar_flatten_next_fu_1258_p3 = ((tmp_39_fu_1207_p2[0:0] === 1'b1) ? 10'd1 : indvar_flatten_op_reg_3752);
assign indvar_flatten_op_fu_1144_p2 = (10'd1 + indvar_flatten_reg_397);
assign j_1_fu_1122_p2 = (3'd1 + j_mid_fu_1093_p3);
assign j_mid_fu_1093_p3 = ((exitcond_flatten_reg_3684[0:0] === 1'b1) ? 3'd0 : j_phi_fu_389_p4);
assign not_exitcond_flatten_1_fu_1133_p2 = (exitcond_flatten_reg_3684 | exitcond_flatten_not_fu_1128_p2);
assign not_exitcond_flatten_fu_1107_p2 = (exitcond_flatten_reg_3684 ^ 1'd1);
assign p_shl2_cast_fu_1436_p1 = tmp_620_fu_1429_p3;
assign p_shl3_cast_fu_1183_p4 = {{{{5'd5}, {tmp_1_mid2_v_reg_3722}}}, {2'd0}};
assign p_shl4_cast_fu_1166_p1 = tmp_1_fu_1159_p3;
assign p_shl_cast_fu_1425_p1 = tmp_619_fu_1418_p3;
assign p_v_fu_1303_p3 = ((tmp_9_mid1_reg_3744[0:0] === 1'b1) ? row_b_1_reg_3834 : row_b_mid_reg_3776);
assign row_b_1_fu_1282_p2 = (5'd1 + row_b_mid_reg_3776);
assign row_b_mid2_fu_1334_p3 = ((tmp_9_mid1_reg_3744[0:0] === 1'b1) ? row_b_1_reg_3834 : row_b_mid_reg_3776);
assign row_b_mid_fu_1211_p3 = ((tmp_39_fu_1207_p2[0:0] === 1'b1) ? 5'd0 : row_b_reg_409);
assign tmp_101_fu_2947_p1 = reg_711;
assign tmp_103_fu_3049_p1 = reg_771;
assign tmp_105_fu_3147_p1 = reg_831;
assign tmp_107_fu_3245_p1 = reg_891;
assign tmp_109_fu_3343_p1 = tmp_108_reg_5607;
assign tmp_10_fu_1820_p2 = ($signed(8'd175) + $signed(tmp_2_cast2_reg_4083));
assign tmp_111_fu_3426_p1 = tmp_110_reg_5872;
assign tmp_113_fu_3509_p1 = tmp_112_reg_6132;
assign tmp_114_fu_3573_p1 = reg_956;
assign tmp_117_fu_1871_p1 = reg_715;
assign tmp_119_fu_2457_p1 = tmp_118_reg_4013;
assign tmp_11_fu_1192_p2 = (p_shl3_cast_fu_1183_p4 + tmp_611_cast_fu_1176_p3);
assign tmp_121_fu_1977_p1 = reg_775;
assign tmp_123_fu_2101_p1 = reg_835;
assign tmp_125_fu_2217_p1 = reg_895;
assign tmp_127_fu_2333_p1 = reg_715;
assign tmp_129_fu_2461_p1 = reg_775;
assign tmp_131_fu_2629_p1 = reg_835;
assign tmp_133_fu_2755_p1 = reg_895;
assign tmp_135_fu_2860_p1 = tmp_134_reg_3887;
assign tmp_137_fu_2952_p1 = reg_715;
assign tmp_139_fu_3054_p1 = reg_775;
assign tmp_13_fu_2050_p2 = (9'd225 + tmp_2_cast1_fu_2047_p1);
assign tmp_141_fu_3152_p1 = reg_835;
assign tmp_143_fu_3250_p1 = reg_895;
assign tmp_145_fu_3347_p1 = tmp_144_reg_5622;
assign tmp_147_fu_3430_p1 = tmp_146_reg_5887;
assign tmp_149_fu_3513_p1 = tmp_148_reg_6147;
assign tmp_14_fu_1839_p1 = tmp_625_reg_3983;
assign tmp_150_fu_3577_p1 = reg_961;
assign tmp_152_fu_1876_p1 = reg_719;
assign tmp_154_fu_2466_p1 = tmp_153_reg_4018;
assign tmp_156_fu_1982_p1 = reg_779;
assign tmp_158_fu_2106_p1 = reg_839;
assign tmp_15_fu_2171_p2 = (9'd250 + tmp_2_cast1_reg_4442);
assign tmp_160_fu_2222_p1 = reg_899;
assign tmp_162_fu_2338_p1 = reg_719;
assign tmp_164_fu_2470_p1 = reg_779;
assign tmp_166_fu_2634_p1 = reg_839;
assign tmp_168_fu_2760_p1 = reg_899;
assign tmp_16_fu_1843_p1 = tmp_626_reg_4127;
assign tmp_170_fu_2864_p1 = tmp_169_reg_3892;
assign tmp_172_fu_2957_p1 = reg_719;
assign tmp_174_fu_3059_p1 = reg_779;
assign tmp_176_fu_3157_p1 = reg_839;
assign tmp_178_fu_3255_p1 = reg_899;
assign tmp_17_fu_2287_p2 = ($signed(9'd275) + $signed(tmp_2_cast1_reg_4442));
assign tmp_180_fu_3351_p1 = tmp_179_reg_5637;
assign tmp_182_fu_3434_p1 = tmp_181_reg_5902;
assign tmp_184_fu_3517_p1 = tmp_183_reg_6162;
assign tmp_185_fu_3581_p1 = reg_966;
assign tmp_187_fu_1881_p1 = reg_723;
assign tmp_189_fu_2475_p1 = tmp_188_reg_4023;
assign tmp_18_fu_2417_p1 = tmp_627_reg_3998;
assign tmp_191_fu_1987_p1 = reg_783;
assign tmp_193_fu_2111_p1 = reg_843;
assign tmp_195_fu_2227_p1 = reg_903;
assign tmp_197_fu_2343_p1 = reg_723;
assign tmp_199_fu_2479_p1 = reg_783;
assign tmp_19_fu_2403_p2 = ($signed(9'd300) + $signed(tmp_2_cast1_reg_4442));
assign tmp_1_cast_fu_1031_p1 = i_phi_fu_366_p4;
assign tmp_1_fu_1159_p3 = {{tmp_1_mid2_v_reg_3722}, {2'd0}};
assign tmp_1_mid2_cast_fu_1156_p1 = tmp_1_mid2_v_reg_3722;
assign tmp_1_mid2_v_fu_1100_p3 = ((exitcond_flatten_reg_3684[0:0] === 1'b1) ? i_1_fu_1087_p2 : i_reg_362);
assign tmp_201_fu_2639_p1 = reg_843;
assign tmp_203_fu_2765_p1 = reg_903;
assign tmp_205_fu_2868_p1 = tmp_204_reg_3897;
assign tmp_207_fu_2962_p1 = reg_723;
assign tmp_209_fu_3064_p1 = reg_783;
assign tmp_20_fu_1945_p1 = tmp_628_reg_4003;
assign tmp_211_fu_3162_p1 = reg_843;
assign tmp_213_fu_3260_p1 = reg_903;
assign tmp_215_fu_3355_p1 = tmp_214_reg_5652;
assign tmp_217_fu_3438_p1 = tmp_216_reg_5917;
assign tmp_219_fu_3521_p1 = tmp_218_reg_6177;
assign tmp_220_fu_3585_p1 = reg_971;
assign tmp_222_fu_1886_p1 = reg_727;
assign tmp_224_fu_2484_p1 = tmp_223_reg_4028;
assign tmp_226_fu_1992_p1 = reg_787;
assign tmp_228_fu_2116_p1 = reg_847;
assign tmp_22_fu_1949_p1 = tmp_21_reg_4132;
assign tmp_230_fu_2232_p1 = reg_907;
assign tmp_232_fu_2348_p1 = reg_727;
assign tmp_234_fu_2488_p1 = reg_787;
assign tmp_236_fu_2644_p1 = reg_847;
assign tmp_238_fu_2770_p1 = reg_907;
assign tmp_23_fu_2583_p2 = ($signed(9'd325) + $signed(tmp_2_cast1_reg_4442));
assign tmp_240_fu_2872_p1 = tmp_239_reg_3902;
assign tmp_242_fu_2967_p1 = reg_727;
assign tmp_244_fu_3069_p1 = reg_787;
assign tmp_246_fu_3167_p1 = reg_847;
assign tmp_248_fu_3265_p1 = reg_907;
assign tmp_24_fu_2069_p1 = tmp_629_reg_4112;
assign tmp_250_fu_3359_p1 = tmp_249_reg_5667;
assign tmp_252_fu_3442_p1 = tmp_251_reg_5932;
assign tmp_254_fu_3525_p1 = tmp_253_reg_6192;
assign tmp_255_fu_3589_p1 = reg_976;
assign tmp_257_fu_1891_p1 = reg_731;
assign tmp_259_fu_2493_p1 = tmp_258_reg_4033;
assign tmp_261_fu_1997_p1 = reg_791;
assign tmp_263_fu_2121_p1 = reg_851;
assign tmp_265_fu_2237_p1 = reg_911;
assign tmp_267_fu_2353_p1 = reg_731;
assign tmp_269_fu_2497_p1 = reg_791;
assign tmp_26_fu_2073_p1 = tmp_25_reg_4137;
assign tmp_271_fu_2649_p1 = reg_851;
assign tmp_273_fu_2775_p1 = reg_911;
assign tmp_275_fu_2876_p1 = tmp_274_reg_3907;
assign tmp_277_fu_2972_p1 = reg_731;
assign tmp_279_fu_3074_p1 = reg_791;
assign tmp_27_fu_2699_p2 = ($signed(9'd350) + $signed(tmp_2_cast1_reg_4442));
assign tmp_281_fu_3172_p1 = reg_851;
assign tmp_283_fu_3270_p1 = reg_911;
assign tmp_285_fu_3363_p1 = tmp_284_reg_5682;
assign tmp_287_fu_3446_p1 = tmp_286_reg_5947;
assign tmp_289_fu_3529_p1 = tmp_288_reg_6207;
assign tmp_28_fu_2185_p1 = tmp_630_reg_4142;
assign tmp_290_fu_3593_p1 = reg_981;
assign tmp_292_fu_1896_p1 = reg_735;
assign tmp_294_fu_2502_p1 = tmp_293_reg_4038;
assign tmp_296_fu_2002_p1 = reg_795;
assign tmp_298_fu_2126_p1 = reg_855;
assign tmp_2_cast1_fu_2047_p1 = tmp_2_reg_3767;
assign tmp_2_cast2_fu_1613_p1 = tmp_2_reg_3767;
assign tmp_2_cast_fu_1376_p1 = tmp_2_reg_3767;
assign tmp_2_fu_1170_p2 = (p_shl4_cast_fu_1166_p1 + tmp_1_mid2_cast_fu_1156_p1);
assign tmp_300_fu_2242_p1 = reg_915;
assign tmp_302_fu_2358_p1 = reg_735;
assign tmp_304_fu_2506_p1 = reg_795;
assign tmp_306_fu_2654_p1 = reg_855;
assign tmp_308_fu_2780_p1 = reg_915;
assign tmp_30_fu_2189_p1 = tmp_29_reg_4147;
assign tmp_310_fu_2880_p1 = tmp_309_reg_3912;
assign tmp_312_fu_2977_p1 = reg_735;
assign tmp_314_fu_3079_p1 = reg_795;
assign tmp_316_fu_3177_p1 = reg_855;
assign tmp_318_fu_3275_p1 = reg_915;
assign tmp_31_fu_2704_p2 = ($signed(9'd375) + $signed(tmp_2_cast1_reg_4442));
assign tmp_320_fu_3367_p1 = tmp_319_reg_5697;
assign tmp_322_fu_3450_p1 = tmp_321_reg_5962;
assign tmp_324_fu_3533_p1 = tmp_323_reg_6222;
assign tmp_325_fu_3597_p1 = reg_986;
assign tmp_327_fu_1901_p1 = reg_739;
assign tmp_329_fu_2511_p1 = tmp_328_reg_4043;
assign tmp_32_fu_2301_p1 = tmp_631_reg_4252;
assign tmp_331_fu_2007_p1 = reg_799;
assign tmp_333_fu_2131_p1 = reg_859;
assign tmp_335_fu_2247_p1 = reg_919;
assign tmp_337_fu_2363_p1 = reg_739;
assign tmp_339_fu_2515_p1 = reg_799;
assign tmp_341_fu_2659_p1 = reg_859;
assign tmp_343_fu_2785_p1 = reg_919;
assign tmp_345_fu_2884_p1 = tmp_344_reg_3917;
assign tmp_347_fu_2982_p1 = reg_739;
assign tmp_349_fu_3084_p1 = reg_799;
assign tmp_34_fu_2305_p1 = tmp_33_reg_4152;
assign tmp_351_fu_3182_p1 = reg_859;
assign tmp_353_fu_3280_p1 = reg_919;
assign tmp_355_fu_3371_p1 = tmp_354_reg_5712;
assign tmp_357_fu_3454_p1 = tmp_356_reg_5977;
assign tmp_359_fu_3537_p1 = tmp_358_reg_6237;
assign tmp_35_fu_1069_p2 = ((col_b_phi_fu_425_p4 == 5'd16) ? 1'b1 : 1'b0);
assign tmp_360_fu_3601_p1 = reg_991;
assign tmp_362_fu_1906_p1 = reg_743;
assign tmp_364_fu_2520_p1 = tmp_363_reg_4048;
assign tmp_366_fu_2012_p1 = reg_803;
assign tmp_368_fu_2136_p1 = reg_863;
assign tmp_36_fu_2421_p1 = tmp_632_reg_4362;
assign tmp_370_fu_2252_p1 = reg_923;
assign tmp_372_fu_2368_p1 = reg_743;
assign tmp_374_fu_2524_p1 = reg_803;
assign tmp_376_fu_2664_p1 = reg_863;
assign tmp_378_fu_2790_p1 = reg_923;
assign tmp_380_fu_2888_p1 = tmp_379_reg_3922;
assign tmp_382_fu_2987_p1 = reg_743;
assign tmp_384_fu_3089_p1 = reg_803;
assign tmp_386_fu_3187_p1 = reg_863;
assign tmp_388_fu_3285_p1 = reg_923;
assign tmp_38_fu_2425_p1 = tmp_37_reg_4157;
assign tmp_390_fu_3375_p1 = tmp_389_reg_5727;
assign tmp_392_fu_3458_p1 = tmp_391_reg_5992;
assign tmp_394_fu_3541_p1 = tmp_393_reg_6252;
assign tmp_395_fu_3605_p1 = reg_996;
assign tmp_397_fu_1911_p1 = reg_747;
assign tmp_399_fu_2529_p1 = tmp_398_reg_4053;
assign tmp_39_fu_1207_p2 = (exitcond_flatten_mid_reg_3731 | exitcond_flatten_reg_3684);
assign tmp_3_cast_cast_fu_1446_p1 = tmp_3_reg_3872;
assign tmp_3_fu_1362_p2 = (tmp_cast_fu_1358_p1 + tmp_4_mid2_cast_reg_3819);
assign tmp_401_fu_2017_p1 = reg_807;
assign tmp_403_fu_2141_p1 = reg_867;
assign tmp_405_fu_2257_p1 = reg_927;
assign tmp_407_fu_2373_p1 = reg_747;
assign tmp_409_fu_2533_p1 = reg_807;
assign tmp_40_fu_2597_p1 = tmp_633_reg_4497;
assign tmp_411_fu_2669_p1 = reg_867;
assign tmp_413_fu_2795_p1 = reg_927;
assign tmp_415_fu_2892_p1 = tmp_414_reg_3927;
assign tmp_417_fu_2992_p1 = reg_747;
assign tmp_419_fu_3094_p1 = reg_807;
assign tmp_421_fu_3192_p1 = reg_867;
assign tmp_423_fu_3290_p1 = reg_927;
assign tmp_425_fu_3379_p1 = tmp_424_reg_5742;
assign tmp_427_fu_3462_p1 = tmp_426_reg_6007;
assign tmp_429_fu_3545_p1 = tmp_428_reg_6267;
assign tmp_42_fu_2601_p1 = tmp_41_reg_4162;
assign tmp_430_fu_3609_p1 = reg_1001;
assign tmp_432_fu_1916_p1 = reg_751;
assign tmp_434_fu_2538_p1 = tmp_433_reg_4058;
assign tmp_436_fu_2022_p1 = reg_811;
assign tmp_438_fu_2146_p1 = reg_871;
assign tmp_43_fu_1273_p2 = (tmp_4_mid2_cast_fu_1270_p1 + tmp_2_reg_3767);
assign tmp_440_fu_2262_p1 = reg_931;
assign tmp_442_fu_2378_p1 = reg_751;
assign tmp_444_fu_2542_p1 = reg_811;
assign tmp_446_fu_2674_p1 = reg_871;
assign tmp_448_fu_2800_p1 = reg_931;
assign tmp_44_fu_2723_p1 = tmp_634_reg_4612;
assign tmp_450_fu_2896_p1 = tmp_449_reg_3932;
assign tmp_452_fu_2997_p1 = reg_751;
assign tmp_454_fu_3099_p1 = reg_811;
assign tmp_456_fu_3197_p1 = reg_871;
assign tmp_458_fu_3295_p1 = reg_931;
assign tmp_460_fu_3383_p1 = tmp_459_reg_5757;
assign tmp_462_fu_3466_p1 = tmp_461_reg_6022;
assign tmp_464_fu_3549_p1 = tmp_463_reg_6282;
assign tmp_465_fu_3613_p1 = reg_1006;
assign tmp_467_fu_1921_p1 = reg_755;
assign tmp_469_fu_2547_p1 = tmp_468_reg_4063;
assign tmp_46_fu_2727_p1 = tmp_45_reg_4167;
assign tmp_471_fu_2027_p1 = reg_815;
assign tmp_473_fu_2151_p1 = reg_875;
assign tmp_475_fu_2267_p1 = reg_935;
assign tmp_477_fu_2383_p1 = reg_755;
assign tmp_479_fu_2551_p1 = reg_815;
assign tmp_47_fu_1297_p2 = (tmp_4_mid2_cast4_fu_1290_p1 + tmp_5_cast_fu_1287_p1);
assign tmp_481_fu_2679_p1 = reg_875;
assign tmp_483_fu_2805_p1 = reg_935;
assign tmp_485_fu_2900_p1 = tmp_484_reg_3937;
assign tmp_487_fu_3002_p1 = reg_755;
assign tmp_489_fu_3104_p1 = reg_815;
assign tmp_48_fu_2829_p1 = tmp_635_reg_3877;
assign tmp_491_fu_3202_p1 = reg_875;
assign tmp_493_fu_3300_p1 = reg_935;
assign tmp_495_fu_3387_p1 = tmp_494_reg_5772;
assign tmp_497_fu_3470_p1 = tmp_496_reg_6037;
assign tmp_499_fu_3553_p1 = tmp_498_reg_6297;
assign tmp_4_fu_1616_p2 = (8'd100 + tmp_2_cast2_fu_1613_p1);
assign tmp_4_mid2_cast1_fu_2056_p1 = tmp_4_mid2_reg_3783;
assign tmp_4_mid2_cast2_fu_1224_p1 = tmp_4_mid2_fu_1219_p3;
assign tmp_4_mid2_cast3_fu_1622_p1 = tmp_4_mid2_reg_3783;
assign tmp_4_mid2_cast4_fu_1290_p1 = tmp_4_mid2_reg_3783;
assign tmp_4_mid2_cast_fu_1270_p1 = tmp_4_mid2_reg_3783;
assign tmp_4_mid2_fu_1219_p3 = ((exitcond_flatten_mid_reg_3731[0:0] === 1'b1) ? j_1_reg_3739 : j_mid_reg_3717);
assign tmp_500_fu_3617_p1 = reg_1011;
assign tmp_502_fu_1926_p1 = reg_759;
assign tmp_504_fu_2556_p1 = tmp_503_reg_4068;
assign tmp_506_fu_2032_p1 = reg_819;
assign tmp_508_fu_2156_p1 = reg_879;
assign tmp_50_fu_2833_p1 = tmp_49_reg_4172;
assign tmp_510_fu_2272_p1 = reg_939;
assign tmp_512_fu_2388_p1 = reg_759;
assign tmp_514_fu_2560_p1 = reg_819;
assign tmp_516_fu_2684_p1 = reg_879;
assign tmp_518_fu_2810_p1 = reg_939;
assign tmp_51_fu_1395_p2 = (tmp_4_mid2_cast4_reg_3841 + tmp_6_fu_1379_p2);
assign tmp_520_fu_2904_p1 = tmp_519_reg_3942;
assign tmp_522_fu_3007_p1 = reg_759;
assign tmp_524_fu_3109_p1 = reg_819;
assign tmp_526_fu_3207_p1 = reg_879;
assign tmp_528_fu_3305_p1 = reg_939;
assign tmp_52_fu_2920_p1 = tmp_636_reg_4732;
assign tmp_530_fu_3391_p1 = tmp_529_reg_5787;
assign tmp_532_fu_3474_p1 = tmp_531_reg_6052;
assign tmp_534_fu_3557_p1 = tmp_533_reg_6312;
assign tmp_535_fu_3621_p1 = reg_1016;
assign tmp_537_fu_1931_p1 = reg_763;
assign tmp_539_fu_2565_p1 = tmp_538_reg_4073;
assign tmp_541_fu_2037_p1 = reg_823;
assign tmp_543_fu_2161_p1 = reg_883;
assign tmp_545_fu_2277_p1 = reg_943;
assign tmp_547_fu_2393_p1 = reg_763;
assign tmp_549_fu_2569_p1 = reg_823;
assign tmp_54_fu_2924_p1 = tmp_53_reg_4177;
assign tmp_551_fu_2689_p1 = reg_883;
assign tmp_553_fu_2815_p1 = reg_943;
assign tmp_555_fu_2908_p1 = tmp_554_reg_3947;
assign tmp_557_fu_3012_p1 = reg_763;
assign tmp_559_fu_3114_p1 = reg_823;
assign tmp_55_fu_1400_p2 = (tmp_4_mid2_cast4_reg_3841 + tmp_s_fu_1385_p2);
assign tmp_561_fu_3212_p1 = reg_883;
assign tmp_563_fu_3310_p1 = reg_943;
assign tmp_565_fu_3395_p1 = tmp_564_reg_5802;
assign tmp_567_fu_3478_p1 = tmp_566_reg_6067;
assign tmp_569_fu_3561_p1 = tmp_568_reg_6327;
assign tmp_56_fu_3022_p1 = tmp_637_reg_4932;
assign tmp_570_fu_3625_p1 = reg_1021;
assign tmp_572_fu_1936_p1 = reg_767;
assign tmp_574_fu_2574_p1 = tmp_573_reg_4078;
assign tmp_576_fu_2042_p1 = reg_827;
assign tmp_578_fu_2166_p1 = reg_887;
assign tmp_580_fu_2282_p1 = reg_947;
assign tmp_582_fu_2398_p1 = reg_767;
assign tmp_584_fu_2578_p1 = reg_827;
assign tmp_586_fu_2694_p1 = reg_887;
assign tmp_588_fu_2820_p1 = reg_947;
assign tmp_58_fu_3026_p1 = tmp_57_reg_4182;
assign tmp_590_fu_2912_p1 = tmp_589_reg_3952;
assign tmp_592_fu_3017_p1 = reg_767;
assign tmp_594_fu_3119_p1 = reg_827;
assign tmp_596_fu_3217_p1 = reg_887;
assign tmp_598_fu_3315_p1 = reg_947;
assign tmp_59_fu_1629_p2 = (tmp_4_mid2_cast3_fu_1622_p1 + tmp_4_fu_1616_p2);
assign tmp_5_cast_fu_1287_p1 = tmp_5_reg_3814;
assign tmp_5_fu_1265_p2 = (6'd25 + tmp_2_reg_3767);
assign tmp_600_fu_3399_p1 = tmp_599_reg_5817;
assign tmp_602_fu_3482_p1 = tmp_601_reg_6082;
assign tmp_604_fu_3565_p1 = tmp_603_reg_6342;
assign tmp_605_fu_3629_p1 = reg_1026;
assign tmp_608_fu_2063_p2 = (tmp_4_mid2_cast1_fu_2056_p1 + tmp_13_fu_2050_p2);
assign tmp_609_fu_2180_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_15_fu_2171_p2);
assign tmp_60_fu_3124_p1 = tmp_638_reg_5202;
assign tmp_610_fu_2296_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_17_fu_2287_p2);
assign tmp_611_cast_fu_1176_p3 = {{7'd5}, {tmp_1_mid2_v_reg_3722}};
assign tmp_611_fu_2412_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_19_fu_2403_p2);
assign tmp_612_fu_2592_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_23_fu_2583_p2);
assign tmp_613_fu_2713_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_27_fu_2699_p2);
assign tmp_614_fu_2718_p2 = (tmp_4_mid2_cast1_reg_4452 + tmp_31_fu_2704_p2);
assign tmp_615_fu_1241_p2 = (tmp_9_mid1_reg_3744 | exitcond_flatten_mid_reg_3731);
assign tmp_616_fu_1245_p2 = (tmp_615_fu_1241_p2 | exitcond_flatten_reg_3684);
assign tmp_617_fu_1308_p3 = {{p_v_fu_1303_p3}, {4'd0}};
assign tmp_618_fu_1320_p2 = row_b_1_reg_3834 << 5'd1;
assign tmp_619_fu_1418_p3 = {{tmp_8_cast_mid2_reg_3977}, {5'd0}};
assign tmp_620_fu_1429_p3 = {{tmp_8_cast_mid2_reg_3977}, {2'd0}};
assign tmp_621_cast_fu_1293_p1 = tmp_43_reg_3824;
assign tmp_621_fu_1440_p2 = (p_shl_cast_fu_1425_p1 + p_shl2_cast_fu_1436_p1);
assign tmp_622_cast_fu_1391_p1 = tmp_47_reg_3852;
assign tmp_622_fu_1342_p2 = (col_b_cast1_cast_fu_1339_p1 + tmp_642_cast_fu_1316_p1);
assign tmp_623_cast_fu_1414_p1 = tmp_51_reg_3967;
assign tmp_623_fu_1353_p2 = col_b_mid2_reg_3802 << 5'd1;
assign tmp_624_cast_fu_1625_p1 = tmp_55_reg_3972;
assign tmp_624_fu_1449_p2 = (tmp_3_cast_cast_fu_1446_p1 + tmp_621_fu_1440_p2);
assign tmp_625_cast_fu_1648_p1 = tmp_59_reg_4102;
assign tmp_625_fu_1410_p1 = bufw_Dout_A[31:0];
assign tmp_626_cast_fu_1825_p1 = tmp_63_reg_4122;
assign tmp_626_fu_1657_p1 = bufi_Dout_A[31:0];
assign tmp_627_cast_fu_1941_p1 = tmp_67_reg_4217;
assign tmp_627_fu_1455_p1 = bufo_Dout_A[31:0];
assign tmp_628_cast_fu_2059_p1 = tmp_71_reg_4222;
assign tmp_628_fu_1459_p1 = bufw_Dout_A[31:0];
assign tmp_629_cast_fu_1278_p1 = tmp_75_reg_3792;
assign tmp_629_fu_1639_p1 = bufw_Dout_A[31:0];
assign tmp_62_fu_3128_p1 = tmp_61_reg_4187;
assign tmp_630_cast_fu_2176_p1 = tmp_608_reg_4467;
assign tmp_630_fu_1681_p1 = bufw_Dout_A[31:0];
assign tmp_631_cast_fu_2292_p1 = tmp_609_reg_4582;
assign tmp_631_fu_1862_p1 = bufw_Dout_A[31:0];
assign tmp_632_cast_fu_2408_p1 = tmp_610_reg_4697;
assign tmp_632_fu_1968_p1 = bufw_Dout_A[31:0];
assign tmp_633_cast_fu_2588_p1 = tmp_611_reg_4892;
assign tmp_633_fu_2092_p1 = bufw_Dout_A[31:0];
assign tmp_634_cast_fu_2709_p1 = tmp_612_reg_5167;
assign tmp_634_fu_2208_p1 = bufw_Dout_A[31:0];
assign tmp_635_cast_fu_2825_p1 = tmp_613_reg_5362;
assign tmp_635_fu_1367_p1 = bufw_Dout_A[31:0];
assign tmp_636_cast_fu_2916_p1 = tmp_614_reg_5367;
assign tmp_636_fu_2324_p1 = bufw_Dout_A[31:0];
assign tmp_637_fu_2444_p1 = bufw_Dout_A[31:0];
assign tmp_638_fu_2620_p1 = bufw_Dout_A[31:0];
assign tmp_639_fu_2746_p1 = bufw_Dout_A[31:0];
assign tmp_63_fu_1652_p2 = (tmp_4_mid2_cast3_reg_4090 + tmp_7_fu_1643_p2);
assign tmp_640_fu_2852_p1 = bufw_Dout_A[31:0];
assign tmp_641_fu_2943_p1 = bufw_Dout_A[31:0];
assign tmp_642_cast_fu_1316_p1 = tmp_617_fu_1308_p3;
assign tmp_642_fu_3045_p1 = bufw_Dout_A[31:0];
assign tmp_647_cast_fu_1348_p1 = tmp_622_fu_1342_p2;
assign tmp_649_cast_fu_1635_p1 = tmp_624_reg_3993;
assign tmp_64_fu_3222_p1 = tmp_639_reg_5402;
assign tmp_66_fu_3226_p1 = tmp_65_reg_4192;
assign tmp_67_fu_1829_p2 = (tmp_4_mid2_cast3_reg_4090 + tmp_9_fu_1815_p2);
assign tmp_68_fu_3320_p1 = tmp_640_reg_5592;
assign tmp_6_fu_1379_p2 = (7'd50 + tmp_2_cast_fu_1376_p1);
assign tmp_70_fu_3324_p1 = tmp_69_reg_4197;
assign tmp_71_fu_1834_p2 = (tmp_4_mid2_cast3_reg_4090 + tmp_10_fu_1820_p2);
assign tmp_72_fu_3403_p1 = tmp_641_reg_5857;
assign tmp_74_fu_3407_p1 = tmp_73_reg_4202;
assign tmp_75_fu_1228_p2 = (tmp_4_mid2_cast2_fu_1224_p1 + tmp_11_fu_1192_p2);
assign tmp_76_fu_3486_p1 = tmp_642_reg_6117;
assign tmp_78_fu_3490_p1 = tmp_77_reg_4207;
assign tmp_79_fu_3569_p1 = reg_951;
assign tmp_7_cast_fu_1041_p1 = tmp_fu_1035_p2;
assign tmp_7_cast_mid1_fu_1325_p1 = tmp_618_fu_1320_p2;
assign tmp_7_fu_1643_p2 = (8'd125 + tmp_2_cast2_reg_4083);
assign tmp_81_fu_1866_p1 = reg_711;
assign tmp_83_fu_2448_p1 = tmp_82_reg_4008;
assign tmp_85_fu_1972_p1 = reg_771;
assign tmp_87_fu_2096_p1 = reg_831;
assign tmp_89_fu_2212_p1 = reg_891;
assign tmp_8_cast_mid2_fu_1405_p3 = ((tmp_9_mid1_reg_3744[0:0] === 1'b1) ? tmp_8_mid1_reg_3857 : tmp_8_cast_mid5_reg_3797);
assign tmp_8_cast_mid3_fu_1201_p3 = ((exitcond_flatten_reg_3684[0:0] === 1'b1) ? tmp_8_cast_mid_cast_fu_1198_p1 : tmp_8_reg_3670);
assign tmp_8_cast_mid5_fu_1234_p3 = ((exitcond_flatten_mid_reg_3731[0:0] === 1'b1) ? tmp_1_mid2_cast_fu_1156_p1 : tmp_8_cast_mid3_fu_1201_p3);
assign tmp_8_cast_mid_cast_fu_1198_p1 = i_1_reg_3712;
assign tmp_8_fu_1045_p2 = (tmp_1_cast_fu_1031_p1 + tmp_7_cast_fu_1041_p1);
assign tmp_8_mid1_fu_1329_p2 = (tmp_7_cast_mid1_fu_1325_p1 + tmp_1_mid2_cast_reg_3762);
assign tmp_91_fu_2328_p1 = reg_711;
assign tmp_93_fu_2452_p1 = reg_771;
assign tmp_95_fu_2624_p1 = reg_831;
assign tmp_97_fu_2750_p1 = reg_891;
assign tmp_99_fu_2856_p1 = tmp_98_reg_3882;
assign tmp_9_fu_1815_p2 = ($signed(8'd150) + $signed(tmp_2_cast2_reg_4083));
assign tmp_9_mid1_fu_1138_p2 = (tmp_9_mid_fu_1112_p2 & not_exitcond_flatten_1_fu_1133_p2);
assign tmp_9_mid_fu_1112_p2 = (tmp_35_reg_3696 & not_exitcond_flatten_fu_1107_p2);
assign tmp_cast_fu_1358_p1 = tmp_623_fu_1353_p2;
assign tmp_fu_1035_p2 = row_b_phi_fu_413_p4 << 5'd1;
assign tmp_s_fu_1385_p2 = ($signed(7'd75) + $signed(tmp_2_cast_fu_1376_p1));
always @ (posedge ap_clk) begin
tmp_1_mid2_cast_reg_3762[5:3] <= 3'b000;
tmp_4_mid2_cast_reg_3819[5:3] <= 3'b000;
tmp_4_mid2_cast4_reg_3841[6:3] <= 4'b0000;
tmp_2_cast2_reg_4083[7:6] <= 2'b00;
tmp_4_mid2_cast3_reg_4090[7:3] <= 5'b00000;
tmp_2_cast1_reg_4442[8:6] <= 3'b000;
tmp_4_mid2_cast1_reg_4452[8:3] <= 6'b000000;
end
endmodule //convolve_kernel
|
// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2____15.000______0.000______50.0______303.688____300.991
// CLK_OUT3____30.000______0.000______50.0______270.092____300.991
// CLK_OUT4____90.000______0.000______50.0______226.688____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ClockDivider
(
// Clock in ports
input clkIn,
// Clock out ports
output clk108M,
output clk_cpu,
output clk2cpu,
output clk6cpu
);
ClockDivider_clk_wiz inst
(
// Clock in ports
.clkIn(clkIn),
// Clock out ports
.clk108M(clk108M),
.clk_cpu(clk_cpu),
.clk2cpu(clk2cpu),
.clk6cpu(clk6cpu)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_PP_BLACKBOX_V
|
// megafunction wizard: %ALTFP_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_MULT
// ============================================================
// File Name: acl_fp_mul_dblpumped.v
// Megafunction Name(s):
// ALTFP_MULT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix IV" EXCEPTION_HANDLING="NO" PIPELINE=10 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_alt_ded_mult_y 2011:04:27:21:05:53:SJ cbx_altbarrel_shift 2011:04:27:21:05:53:SJ cbx_altera_mult_add 2011:04:27:21:05:53:SJ cbx_altfp_mult 2011:04:27:21:05:53:SJ cbx_altmult_add 2011:04:27:21:05:53:SJ cbx_cycloneii 2011:04:27:21:05:53:SJ cbx_lpm_add_sub 2011:04:27:21:05:53:SJ cbx_lpm_compare 2011:04:27:21:05:53:SJ cbx_lpm_counter 2011:04:27:21:05:53:SJ cbx_lpm_decode 2011:04:27:21:05:53:SJ cbx_lpm_mult 2011:04:27:21:05:53:SJ cbx_mgl 2011:04:27:21:20:02:SJ cbx_padd 2011:04:27:21:05:53:SJ cbx_parallel_add 2011:04:27:21:05:53:SJ cbx_stratix 2011:04:27:21:05:53:SJ cbx_stratixii 2011:04:27:21:05:53:SJ cbx_stratixiii 2011:04:27:21:05:53:SJ cbx_stratixv 2011:04:27:21:05:53:SJ cbx_util_mgl 2011:04:27:21:05:53:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 254
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_mul_dblpumped_altfp_mult_ieo
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg dataa_exp_all_one_ff_p1;
reg dataa_exp_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p2;
reg datab_exp_all_one_ff_p1;
reg datab_exp_not_zero_ff_p1;
reg datab_man_not_zero_ff_p1;
reg datab_man_not_zero_ff_p2;
reg [9:0] delay_exp2_bias;
reg [9:0] delay_exp3_bias;
reg [9:0] delay_exp_bias;
reg delay_man_product_msb;
reg delay_man_product_msb2;
reg delay_man_product_msb_p0;
reg [23:0] delay_round;
reg [8:0] exp_add_p1;
reg [9:0] exp_adj_p1;
reg [9:0] exp_adj_p2;
reg [8:0] exp_bias_p1;
reg [8:0] exp_bias_p2;
reg [7:0] exp_result_ff;
reg input_is_infinity_dffe_0;
reg input_is_infinity_dffe_1;
reg input_is_infinity_dffe_2;
reg input_is_infinity_dffe_3;
reg input_is_infinity_ff1;
reg input_is_infinity_ff2;
reg input_is_infinity_ff3;
reg input_is_infinity_ff4;
reg input_is_nan_dffe_0;
reg input_is_nan_dffe_1;
reg input_is_nan_dffe_2;
reg input_is_nan_dffe_3;
reg input_is_nan_ff1;
reg input_is_nan_ff2;
reg input_is_nan_ff3;
reg input_is_nan_ff4;
reg input_not_zero_dffe_0;
reg input_not_zero_dffe_1;
reg input_not_zero_dffe_2;
reg input_not_zero_dffe_3;
reg input_not_zero_ff1;
reg input_not_zero_ff2;
reg input_not_zero_ff3;
reg input_not_zero_ff4;
reg lsb_dffe;
reg [22:0] man_result_ff;
reg man_round_carry_p0;
reg [23:0] man_round_p;
reg [23:0] man_round_p0;
reg [24:0] man_round_p2;
reg round_dffe;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg sticky_dffe;
wire [8:0] wire_exp_add_adder_result;
wire [9:0] wire_exp_adj_adder_result;
wire [9:0] wire_exp_bias_subtr_result;
wire [24:0] wire_man_round_adder_result;
wire [47:0] wire_man_product2_mult_result;
wire aclr;
wire [9:0] bias;
wire [7:0] dataa_exp_all_one;
wire [7:0] dataa_exp_not_zero;
wire [22:0] dataa_man_not_zero;
wire [7:0] datab_exp_all_one;
wire [7:0] datab_exp_not_zero;
wire [22:0] datab_man_not_zero;
wire exp_is_inf;
wire exp_is_zero;
wire [9:0] expmod;
wire [7:0] inf_num;
wire lsb_bit;
wire [24:0] man_shift_full;
wire [7:0] result_exp_all_one;
wire [8:0] result_exp_not_zero;
wire round_bit;
wire round_carry;
wire [22:0] sticky_bit;
// synopsys translate_off
initial
dataa_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_all_one_ff_p1 <= dataa_exp_all_one[7];
// synopsys translate_off
initial
dataa_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero[7];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p1 <= dataa_man_not_zero[10];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p2 <= dataa_man_not_zero[22];
// synopsys translate_off
initial
datab_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_all_one_ff_p1 <= datab_exp_all_one[7];
// synopsys translate_off
initial
datab_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_not_zero_ff_p1 <= datab_exp_not_zero[7];
// synopsys translate_off
initial
datab_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p1 <= datab_man_not_zero[10];
// synopsys translate_off
initial
datab_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p2 <= datab_man_not_zero[22];
// synopsys translate_off
initial
delay_exp2_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp2_bias <= 10'b0;
else if (clk_en == 1'b1) delay_exp2_bias <= delay_exp_bias;
// synopsys translate_off
initial
delay_exp3_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp3_bias <= 10'b0;
else if (clk_en == 1'b1) delay_exp3_bias <= delay_exp2_bias;
// synopsys translate_off
initial
delay_exp_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp_bias <= 10'b0;
else if (clk_en == 1'b1) delay_exp_bias <= wire_exp_bias_subtr_result;
// synopsys translate_off
initial
delay_man_product_msb = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb <= delay_man_product_msb_p0;
// synopsys translate_off
initial
delay_man_product_msb2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb2 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb2 <= delay_man_product_msb;
// synopsys translate_off
initial
delay_man_product_msb_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p0 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p0 <= wire_man_product2_mult_result[47];
// synopsys translate_off
initial
delay_round = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_round <= 24'b0;
else if (clk_en == 1'b1) delay_round <= ((man_round_p2[23:0] & {24{(~ man_round_p2[24])}}) | (man_round_p2[24:1] & {24{man_round_p2[24]}}));
// synopsys translate_off
initial
exp_add_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_add_p1 <= 9'b0;
else if (clk_en == 1'b1) exp_add_p1 <= wire_exp_add_adder_result;
// synopsys translate_off
initial
exp_adj_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p1 <= 10'b0;
else if (clk_en == 1'b1) exp_adj_p1 <= delay_exp3_bias;
// synopsys translate_off
initial
exp_adj_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p2 <= 10'b0;
else if (clk_en == 1'b1) exp_adj_p2 <= wire_exp_adj_adder_result;
// synopsys translate_off
initial
exp_bias_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p1 <= 9'b0;
else if (clk_en == 1'b1) exp_bias_p1 <= exp_add_p1[8:0];
// synopsys translate_off
initial
exp_bias_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p2 <= 9'b0;
else if (clk_en == 1'b1) exp_bias_p2 <= exp_bias_p1;
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 8'b0;
else if (clk_en == 1'b1) exp_result_ff <= ((inf_num & {8{((exp_is_inf | input_is_infinity_ff4) | input_is_nan_ff4)}}) | ((exp_adj_p2[7:0] & {8{(~ exp_is_zero)}}) & {8{input_not_zero_ff4}}));
// synopsys translate_off
initial
input_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (~ (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2))) | (datab_exp_all_one_ff_p1 & (~ (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2))));
// synopsys translate_off
initial
input_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
// synopsys translate_off
initial
input_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_2 <= input_is_infinity_dffe_1;
// synopsys translate_off
initial
input_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_3 <= input_is_infinity_dffe_2;
// synopsys translate_off
initial
input_is_infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff1 <= input_is_infinity_dffe_3;
// synopsys translate_off
initial
input_is_infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff2 <= input_is_infinity_ff1;
// synopsys translate_off
initial
input_is_infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff3 <= input_is_infinity_ff2;
// synopsys translate_off
initial
input_is_infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff4 <= input_is_infinity_ff3;
// synopsys translate_off
initial
input_is_nan_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2)) | (datab_exp_all_one_ff_p1 & (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2)));
// synopsys translate_off
initial
input_is_nan_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_1 <= input_is_nan_dffe_0;
// synopsys translate_off
initial
input_is_nan_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_2 <= input_is_nan_dffe_1;
// synopsys translate_off
initial
input_is_nan_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_3 <= input_is_nan_dffe_2;
// synopsys translate_off
initial
input_is_nan_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff1 <= input_is_nan_dffe_3;
// synopsys translate_off
initial
input_is_nan_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff2 <= input_is_nan_ff1;
// synopsys translate_off
initial
input_is_nan_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff3 <= input_is_nan_ff2;
// synopsys translate_off
initial
input_is_nan_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff4 <= input_is_nan_ff3;
// synopsys translate_off
initial
input_not_zero_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 & datab_exp_not_zero_ff_p1);
// synopsys translate_off
initial
input_not_zero_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_1 <= input_not_zero_dffe_0;
// synopsys translate_off
initial
input_not_zero_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_2 <= input_not_zero_dffe_1;
// synopsys translate_off
initial
input_not_zero_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_3 <= input_not_zero_dffe_2;
// synopsys translate_off
initial
input_not_zero_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff1 <= input_not_zero_dffe_3;
// synopsys translate_off
initial
input_not_zero_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff2 <= input_not_zero_ff1;
// synopsys translate_off
initial
input_not_zero_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff3 <= input_not_zero_ff2;
// synopsys translate_off
initial
input_not_zero_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff4 <= input_not_zero_ff3;
// synopsys translate_off
initial
lsb_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_dffe <= 1'b0;
else if (clk_en == 1'b1) lsb_dffe <= lsb_bit;
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 23'b0;
else if (clk_en == 1'b1) man_result_ff <= {((((((delay_round[22] & input_not_zero_ff4) & (~ input_is_infinity_ff4)) & (~ exp_is_inf)) & (~ exp_is_zero)) | (input_is_infinity_ff4 & (~ input_not_zero_ff4))) | input_is_nan_ff4), (((((delay_round[21:0] & {22{input_not_zero_ff4}}) & {22{(~ input_is_infinity_ff4)}}) & {22{(~ exp_is_inf)}}) & {22{(~ exp_is_zero)}}) & {22{(~ input_is_nan_ff4)}})};
// synopsys translate_off
initial
man_round_carry_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_carry_p0 <= 1'b0;
else if (clk_en == 1'b1) man_round_carry_p0 <= round_carry;
// synopsys translate_off
initial
man_round_p = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p <= 24'b0;
else if (clk_en == 1'b1) man_round_p <= man_shift_full[24:1];
// synopsys translate_off
initial
man_round_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p0 <= 24'b0;
else if (clk_en == 1'b1) man_round_p0 <= man_round_p;
// synopsys translate_off
initial
man_round_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p2 <= 25'b0;
else if (clk_en == 1'b1) man_round_p2 <= wire_man_round_adder_result;
// synopsys translate_off
initial
round_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_dffe <= 1'b0;
else if (clk_en == 1'b1) round_dffe <= round_bit;
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= (dataa[31] ^ datab[31]);
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sticky_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_dffe <= 1'b0;
else if (clk_en == 1'b1) sticky_dffe <= sticky_bit[22];
lpm_add_sub exp_add_adder
(
.aclr(aclr),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, dataa[30:23]}),
.datab({1'b0, datab[30:23]}),
.overflow(),
.result(wire_exp_add_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_add_adder.lpm_pipeline = 1,
exp_add_adder.lpm_width = 9,
exp_add_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_adj_adder
(
.cin(1'b0),
.cout(),
.dataa(exp_adj_p1),
.datab({expmod[9:0]}),
.overflow(),
.result(wire_exp_adj_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_adj_adder.lpm_pipeline = 0,
exp_adj_adder.lpm_width = 10,
exp_adj_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_bias_subtr
(
.cout(),
.dataa({1'b0, exp_bias_p2}),
.datab({bias[9:0]}),
.overflow(),
.result(wire_exp_bias_subtr_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_bias_subtr.lpm_direction = "SUB",
exp_bias_subtr.lpm_pipeline = 0,
exp_bias_subtr.lpm_representation = "UNSIGNED",
exp_bias_subtr.lpm_width = 10,
exp_bias_subtr.lpm_type = "lpm_add_sub";
lpm_add_sub man_round_adder
(
.cout(),
.dataa({1'b0, man_round_p0}),
.datab({{24{1'b0}}, man_round_carry_p0}),
.overflow(),
.result(wire_man_round_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round_adder.lpm_pipeline = 0,
man_round_adder.lpm_width = 25,
man_round_adder.lpm_type = "lpm_add_sub";
lpm_mult man_product2_mult
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b1, dataa[22:0]}),
.datab({1'b1, datab[22:0]}),
.result(wire_man_product2_mult_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_product2_mult.lpm_pipeline = 5,
man_product2_mult.lpm_representation = "UNSIGNED",
man_product2_mult.lpm_widtha = 24,
man_product2_mult.lpm_widthb = 24,
man_product2_mult.lpm_widthp = 48,
man_product2_mult.lpm_widths = 1,
man_product2_mult.lpm_type = "lpm_mult",
man_product2_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
aclr = 1'b0,
bias = {{3{1'b0}}, {7{1'b1}}},
dataa_exp_all_one = {(dataa[30] & dataa_exp_all_one[6]), (dataa[29] & dataa_exp_all_one[5]), (dataa[28] & dataa_exp_all_one[4]), (dataa[27] & dataa_exp_all_one[3]), (dataa[26] & dataa_exp_all_one[2]), (dataa[25] & dataa_exp_all_one[1]), (dataa[24] & dataa_exp_all_one[0]), dataa[23]},
dataa_exp_not_zero = {(dataa[30] | dataa_exp_not_zero[6]), (dataa[29] | dataa_exp_not_zero[5]), (dataa[28] | dataa_exp_not_zero[4]), (dataa[27] | dataa_exp_not_zero[3]), (dataa[26] | dataa_exp_not_zero[2]), (dataa[25] | dataa_exp_not_zero[1]), (dataa[24] | dataa_exp_not_zero[0]), dataa[23]},
dataa_man_not_zero = {(dataa[22] | dataa_man_not_zero[21]), (dataa[21] | dataa_man_not_zero[20]), (dataa[20] | dataa_man_not_zero[19]), (dataa[19] | dataa_man_not_zero[18]), (dataa[18] | dataa_man_not_zero[17]), (dataa[17] | dataa_man_not_zero[16]), (dataa[16] | dataa_man_not_zero[15]), (dataa[15] | dataa_man_not_zero[14]), (dataa[14] | dataa_man_not_zero[13]), (dataa[13] | dataa_man_not_zero[12]), (dataa[12] | dataa_man_not_zero[11]), dataa[11], (dataa[10] | dataa_man_not_zero[9]), (dataa[9] | dataa_man_not_zero[8]), (dataa[8] | dataa_man_not_zero[7]), (dataa[7] | dataa_man_not_zero[6]), (dataa[6] | dataa_man_not_zero[5]), (dataa[5] | dataa_man_not_zero[4]), (dataa[4] | dataa_man_not_zero[3]), (dataa[3] | dataa_man_not_zero[2]), (dataa[2] | dataa_man_not_zero[1]), (dataa[1] | dataa_man_not_zero[0]), dataa[0]},
datab_exp_all_one = {(datab[30] & datab_exp_all_one[6]), (datab[29] & datab_exp_all_one[5]), (datab[28] & datab_exp_all_one[4]), (datab[27] & datab_exp_all_one[3]), (datab[26] & datab_exp_all_one[2]), (datab[25] & datab_exp_all_one[1]), (datab[24] & datab_exp_all_one[0]), datab[23]},
datab_exp_not_zero = {(datab[30] | datab_exp_not_zero[6]), (datab[29] | datab_exp_not_zero[5]), (datab[28] | datab_exp_not_zero[4]), (datab[27] | datab_exp_not_zero[3]), (datab[26] | datab_exp_not_zero[2]), (datab[25] | datab_exp_not_zero[1]), (datab[24] | datab_exp_not_zero[0]), datab[23]},
datab_man_not_zero = {(datab[22] | datab_man_not_zero[21]), (datab[21] | datab_man_not_zero[20]), (datab[20] | datab_man_not_zero[19]), (datab[19] | datab_man_not_zero[18]), (datab[18] | datab_man_not_zero[17]), (datab[17] | datab_man_not_zero[16]), (datab[16] | datab_man_not_zero[15]), (datab[15] | datab_man_not_zero[14]), (datab[14] | datab_man_not_zero[13]), (datab[13] | datab_man_not_zero[12]), (datab[12] | datab_man_not_zero[11]), datab[11], (datab[10] | datab_man_not_zero[9]), (datab[9] | datab_man_not_zero[8]), (datab[8] | datab_man_not_zero[7]), (datab[7] | datab_man_not_zero[6]), (datab[6] | datab_man_not_zero[5]), (datab[5] | datab_man_not_zero[4]), (datab[4] | datab_man_not_zero[3]), (datab[3] | datab_man_not_zero[2]), (datab[2] | datab_man_not_zero[1]), (datab[1] | datab_man_not_zero[0]), datab[0]},
exp_is_inf = (((~ exp_adj_p2[9]) & exp_adj_p2[8]) | ((~ exp_adj_p2[8]) & result_exp_all_one[7])),
exp_is_zero = (exp_adj_p2[9] | (~ result_exp_not_zero[8])),
expmod = {{8{1'b0}}, (delay_man_product_msb2 & man_round_p2[24]), (delay_man_product_msb2 ^ man_round_p2[24])},
inf_num = {8{1'b1}},
lsb_bit = man_shift_full[1],
man_shift_full = ((wire_man_product2_mult_result[46:22] & {25{(~ wire_man_product2_mult_result[47])}}) | (wire_man_product2_mult_result[47:23] & {25{wire_man_product2_mult_result[47]}})),
result = {sign_node_ff9[0:0], exp_result_ff[7:0], man_result_ff[22:0]},
result_exp_all_one = {(result_exp_all_one[6] & exp_adj_p2[7]), (result_exp_all_one[5] & exp_adj_p2[6]), (result_exp_all_one[4] & exp_adj_p2[5]), (result_exp_all_one[3] & exp_adj_p2[4]), (result_exp_all_one[2] & exp_adj_p2[3]), (result_exp_all_one[1] & exp_adj_p2[2]), (result_exp_all_one[0] & exp_adj_p2[1]), exp_adj_p2[0]},
result_exp_not_zero = {(result_exp_not_zero[7] | exp_adj_p2[8]), (result_exp_not_zero[6] | exp_adj_p2[7]), (result_exp_not_zero[5] | exp_adj_p2[6]), (result_exp_not_zero[4] | exp_adj_p2[5]), (result_exp_not_zero[3] | exp_adj_p2[4]), (result_exp_not_zero[2] | exp_adj_p2[3]), (result_exp_not_zero[1] | exp_adj_p2[2]), (result_exp_not_zero[0] | exp_adj_p2[1]), exp_adj_p2[0]},
round_bit = man_shift_full[0],
round_carry = (round_dffe & (lsb_dffe | sticky_dffe)),
sticky_bit = {(sticky_bit[21] | (wire_man_product2_mult_result[47] & wire_man_product2_mult_result[22])), (sticky_bit[20] | wire_man_product2_mult_result[21]), (sticky_bit[19] | wire_man_product2_mult_result[20]), (sticky_bit[18] | wire_man_product2_mult_result[19]), (sticky_bit[17] | wire_man_product2_mult_result[18]), (sticky_bit[16] | wire_man_product2_mult_result[17]), (sticky_bit[15] | wire_man_product2_mult_result[16]), (sticky_bit[14] | wire_man_product2_mult_result[15]), (sticky_bit[13] | wire_man_product2_mult_result[14]), (sticky_bit[12] | wire_man_product2_mult_result[13]), (sticky_bit[11] | wire_man_product2_mult_result[12]), (sticky_bit[10] | wire_man_product2_mult_result[11]), (sticky_bit[9] | wire_man_product2_mult_result[10]), (sticky_bit[8] | wire_man_product2_mult_result[9]), (sticky_bit[7] | wire_man_product2_mult_result[8]), (sticky_bit[6] | wire_man_product2_mult_result[7]), (sticky_bit[5] | wire_man_product2_mult_result[6]), (sticky_bit[4] | wire_man_product2_mult_result[5]), (sticky_bit[3] | wire_man_product2_mult_result[4]), (sticky_bit[2] | wire_man_product2_mult_result[3]), (sticky_bit[1] | wire_man_product2_mult_result[2]), (sticky_bit[0] | wire_man_product2_mult_result[1]), wire_man_product2_mult_result[0]};
endmodule //acl_fp_mul_dblpumped_altfp_mult_ieo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_mul_fast (
clk_en,
clock,
dataa,
datab,
result);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_mul_dblpumped_altfp_mult_ieo acl_fp_mul_dblpumped_altfp_mult_ieo_component (
.clk_en (clk_en),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: FPM_FORMAT STRING "Single"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "10"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_dblpumped.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
module pc_block (
new_pc_init,
wf_id,
wr,
rd_en,
wf_id_rd,
pc_read2ibuff,
clk,
rst
);
parameter BITWIDTH = 32;
input [31:0] new_pc_init;
input [5:0] wf_id;
input wr;
input clk, rst;
input rd_en;
input [5:0] wf_id_rd;
output [32:0]pc_read2ibuff;
wire write;
wire [31:0] pc_read;
wire [32:0] data0, data_flop0;
wire [32:0] data1, data_flop1;
wire [32:0] data2, data_flop2;
wire [32:0] data3, data_flop3;
wire [32:0] data4, data_flop4;
wire [32:0] data5, data_flop5;
wire [32:0] data6, data_flop6;
wire [32:0] data7, data_flop7;
wire [32:0] data8, data_flop8;
wire [32:0] data9, data_flop9;
wire [32:0] data10, data_flop10;
wire [32:0] data11, data_flop11;
wire [32:0] data12, data_flop12;
wire [32:0] data13, data_flop13;
wire [32:0] data14, data_flop14;
wire [32:0] data15, data_flop15;
wire [32:0] data16, data_flop16;
wire [32:0] data17, data_flop17;
wire [32:0] data18, data_flop18;
wire [32:0] data19, data_flop19;
wire [32:0] data20, data_flop20;
wire [32:0] data21, data_flop21;
wire [32:0] data22, data_flop22;
wire [32:0] data23, data_flop23;
wire [32:0] data24, data_flop24;
wire [32:0] data25, data_flop25;
wire [32:0] data26, data_flop26;
wire [32:0] data27, data_flop27;
wire [32:0] data28, data_flop28;
wire [32:0] data29, data_flop29;
wire [32:0] data30, data_flop30;
wire [32:0] data31, data_flop31;
wire [32:0] data32, data_flop32;
wire [32:0] data33, data_flop33;
wire [32:0] data34, data_flop34;
wire [32:0] data35, data_flop35;
wire [32:0] data36, data_flop36;
wire [32:0] data37, data_flop37;
wire [32:0] data38, data_flop38;
wire [32:0] data39, data_flop39;
assign write = 1'b1;
regfile #(33) rfile0 (data0, write, data_flop0, clk, rst);
regfile #(33) rfile1 (data1, write, data_flop1, clk, rst);
regfile #(33) rfile2 (data2, write, data_flop2, clk, rst);
regfile #(33) rfile3 (data3, write, data_flop3, clk, rst);
regfile #(33) rfile4 (data4, write, data_flop4, clk, rst);
regfile #(33) rfile5 (data5, write, data_flop5, clk, rst);
regfile #(33) rfile6 (data6, write, data_flop6, clk, rst);
regfile #(33) rfile7 (data7, write, data_flop7, clk, rst);
regfile #(33) rfile8 (data8, write, data_flop8, clk, rst);
regfile #(33) rfile9 (data9, write, data_flop9, clk, rst);
regfile #(33) rfile10 (data10, write, data_flop10, clk, rst);
regfile #(33) rfile11 (data11, write, data_flop11, clk, rst);
regfile #(33) rfile12 (data12, write, data_flop12, clk, rst);
regfile #(33) rfile13 (data13, write, data_flop13, clk, rst);
regfile #(33) rfile14 (data14, write, data_flop14, clk, rst);
regfile #(33) rfile15 (data15, write, data_flop15, clk, rst);
regfile #(33) rfile16 (data16, write, data_flop16, clk, rst);
regfile #(33) rfile17 (data17, write, data_flop17, clk, rst);
regfile #(33) rfile18 (data18, write, data_flop18, clk, rst);
regfile #(33) rfile19 (data19, write, data_flop19, clk, rst);
regfile #(33) rfile20 (data20, write, data_flop20, clk, rst);
regfile #(33) rfile21 (data21, write, data_flop21, clk, rst);
regfile #(33) rfile22 (data22, write, data_flop22, clk, rst);
regfile #(33) rfile23 (data23, write, data_flop23, clk, rst);
regfile #(33) rfile24 (data24, write, data_flop24, clk, rst);
regfile #(33) rfile25 (data25, write, data_flop25, clk, rst);
regfile #(33) rfile26 (data26, write, data_flop26, clk, rst);
regfile #(33) rfile27 (data27, write, data_flop27, clk, rst);
regfile #(33) rfile28 (data28, write, data_flop28, clk, rst);
regfile #(33) rfile29 (data29, write, data_flop29, clk, rst);
regfile #(33) rfile30 (data30, write, data_flop30, clk, rst);
regfile #(33) rfile31 (data31, write, data_flop31, clk, rst);
regfile #(33) rfile32 (data32, write, data_flop32, clk, rst);
regfile #(33) rfile33 (data33, write, data_flop33, clk, rst);
regfile #(33) rfile34 (data34, write, data_flop34, clk, rst);
regfile #(33) rfile35 (data35, write, data_flop35, clk, rst);
regfile #(33) rfile36 (data36, write, data_flop36, clk, rst);
regfile #(33) rfile37 (data37, write, data_flop37, clk, rst);
regfile #(33) rfile38 (data38, write, data_flop38, clk, rst);
regfile #(33) rfile39 (data39, write, data_flop39, clk, rst);
adder a1(pc_read2ibuff[31:0],pc_read);
assign pc_read2ibuff = (wf_id_rd==6'd0)?data_flop0:
(wf_id_rd==6'd1)?data_flop1:
(wf_id_rd==6'd2)?data_flop2:
(wf_id_rd==6'd3)?data_flop3:
(wf_id_rd==6'd4)?data_flop4:
(wf_id_rd==6'd5)?data_flop5:
(wf_id_rd==6'd6)?data_flop6:
(wf_id_rd==6'd7)?data_flop7:
(wf_id_rd==6'd8)?data_flop8:
(wf_id_rd==6'd9)?data_flop9:
(wf_id_rd==6'd10)?data_flop10:
(wf_id_rd==6'd11)?data_flop11:
(wf_id_rd==6'd12)?data_flop12:
(wf_id_rd==6'd13)?data_flop13:
(wf_id_rd==6'd14)?data_flop14:
(wf_id_rd==6'd15)?data_flop15:
(wf_id_rd==6'd16)?data_flop16:
(wf_id_rd==6'd17)?data_flop17:
(wf_id_rd==6'd18)?data_flop18:
(wf_id_rd==6'd19)?data_flop19:
(wf_id_rd==6'd20)?data_flop20:
(wf_id_rd==6'd21)?data_flop21:
(wf_id_rd==6'd22)?data_flop22:
(wf_id_rd==6'd23)?data_flop23:
(wf_id_rd==6'd24)?data_flop24:
(wf_id_rd==6'd25)?data_flop25:
(wf_id_rd==6'd26)?data_flop26:
(wf_id_rd==6'd27)?data_flop27:
(wf_id_rd==6'd28)?data_flop28:
(wf_id_rd==6'd29)?data_flop29:
(wf_id_rd==6'd30)?data_flop30:
(wf_id_rd==6'd31)?data_flop31:
(wf_id_rd==6'd32)?data_flop32:
(wf_id_rd==6'd33)?data_flop33:
(wf_id_rd==6'd34)?data_flop34:
(wf_id_rd==6'd35)?data_flop35:
(wf_id_rd==6'd36)?data_flop36:
(wf_id_rd==6'd37)?data_flop37:
(wf_id_rd==6'd38)?data_flop38:
(wf_id_rd==6'd39)?data_flop39:
33'd0;
assign data0=(wr & (wf_id==6'd0))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd0))?{1'b0,pc_read}:data_flop0;
assign data1=(wr & (wf_id==6'd1))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd1))?{1'b0,pc_read}:data_flop1;
assign data2=(wr & (wf_id==6'd2))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd2))?{1'b0,pc_read}:data_flop2;
assign data3=(wr & (wf_id==6'd3))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd3))?{1'b0,pc_read}:data_flop3;
assign data4=(wr & (wf_id==6'd4))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd4))?{1'b0,pc_read}:data_flop4;
assign data5=(wr & (wf_id==6'd5))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd5))?{1'b0,pc_read}:data_flop5;
assign data6=(wr & (wf_id==6'd6))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd6))?{1'b0,pc_read}:data_flop6;
assign data7=(wr & (wf_id==6'd7))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd7))?{1'b0,pc_read}:data_flop7;
assign data8=(wr & (wf_id==6'd8))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd8))?{1'b0,pc_read}:data_flop8;
assign data9=(wr & (wf_id==6'd9))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd9))?{1'b0,pc_read}:data_flop9;
assign data10=(wr & (wf_id==6'd10))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd10))?{1'b0,pc_read}:data_flop10;
assign data11=(wr & (wf_id==6'd11))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd11))?{1'b0,pc_read}:data_flop11;
assign data12=(wr & (wf_id==6'd12))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd12))?{1'b0,pc_read}:data_flop12;
assign data13=(wr & (wf_id==6'd13))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd13))?{1'b0,pc_read}:data_flop13;
assign data14=(wr & (wf_id==6'd14))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd14))?{1'b0,pc_read}:data_flop14;
assign data15=(wr & (wf_id==6'd15))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd15))?{1'b0,pc_read}:data_flop15;
assign data16=(wr & (wf_id==6'd16))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd16))?{1'b0,pc_read}:data_flop16;
assign data17=(wr & (wf_id==6'd17))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd17))?{1'b0,pc_read}:data_flop17;
assign data18=(wr & (wf_id==6'd18))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd18))?{1'b0,pc_read}:data_flop18;
assign data19=(wr & (wf_id==6'd19))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd19))?{1'b0,pc_read}:data_flop19;
assign data20=(wr & (wf_id==6'd20))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd20))?{1'b0,pc_read}:data_flop20;
assign data21=(wr & (wf_id==6'd21))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd21))?{1'b0,pc_read}:data_flop21;
assign data22=(wr & (wf_id==6'd22))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd22))?{1'b0,pc_read}:data_flop22;
assign data23=(wr & (wf_id==6'd23))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd23))?{1'b0,pc_read}:data_flop23;
assign data24=(wr & (wf_id==6'd24))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd24))?{1'b0,pc_read}:data_flop24;
assign data25=(wr & (wf_id==6'd25))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd25))?{1'b0,pc_read}:data_flop25;
assign data26=(wr & (wf_id==6'd26))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd26))?{1'b0,pc_read}:data_flop26;
assign data27=(wr & (wf_id==6'd27))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd27))?{1'b0,pc_read}:data_flop27;
assign data28=(wr & (wf_id==6'd28))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd28))?{1'b0,pc_read}:data_flop28;
assign data29=(wr & (wf_id==6'd29))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd29))?{1'b0,pc_read}:data_flop29;
assign data30=(wr & (wf_id==6'd30))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd30))?{1'b0,pc_read}:data_flop30;
assign data31=(wr & (wf_id==6'd31))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd31))?{1'b0,pc_read}:data_flop31;
assign data32=(wr & (wf_id==6'd32))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd32))?{1'b0,pc_read}:data_flop32;
assign data33=(wr & (wf_id==6'd33))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd33))?{1'b0,pc_read}:data_flop33;
assign data34=(wr & (wf_id==6'd34))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd34))?{1'b0,pc_read}:data_flop34;
assign data35=(wr & (wf_id==6'd35))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd35))?{1'b0,pc_read}:data_flop35;
assign data36=(wr & (wf_id==6'd36))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd36))?{1'b0,pc_read}:data_flop36;
assign data37=(wr & (wf_id==6'd37))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd37))?{1'b0,pc_read}:data_flop37;
assign data38=(wr & (wf_id==6'd38))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd38))?{1'b0,pc_read}:data_flop38;
assign data39=(wr & (wf_id==6'd39))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd39))?{1'b0,pc_read}:data_flop39;
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("tee_local.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 17;
reg [STACK_DEPTH:0] index = 1;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("tee_local_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#39
`assert(result, 2);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_tb.v: Multiported-RAM testbench //
// //
// Author: Ameer M. Abdelhadi ([email protected], [email protected]) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// set default value for the following parameters, if not defined from command-line
// memory depth
`ifndef MEMD
`define MEMD 64
`endif
// data width
`ifndef DATAW
`define DATAW 8
`endif
// number of reading ports
`ifndef nWPORTS
`define nWPORTS 3
`endif
// number of writing ports
`ifndef nRPORTS
`define nRPORTS 2
`endif
// Simulation cycles count
`ifndef CYCC
`define CYCC 1000
`endif
// set data-dependency perotection/allowance
// WDW (Write-During-Write) protection
`ifndef WDW
`define WDW 0
`endif
// WAW (Write-After-Write) protection
`ifndef WAW
`define WAW 1
`endif
// RDW (Read-During-Write) protection
`ifndef RDW
`define RDW 1
`endif
// RAW (Read-After-Write) protection
`ifndef RAW
`define RAW 1
`endif
module mpram_tb;
localparam MEMD = `MEMD ; // memory depth
localparam DATAW = `DATAW ; // data width
localparam nRPORTS = `nRPORTS ; // number of reading ports
localparam nWPORTS = `nWPORTS ; // number of writing ports
localparam CYCC = `CYCC ; // simulation cycles count
localparam WAW = `WAW ; // WAW (Write-After-Write ) protection
localparam WDW = `WDW ; // WDW (Write-During-Write) protection
localparam RAW = `RAW ; // RAW (Read-After-Write ) protection
localparam RDW = `RDW ; // RDW (Read-During-Write ) protection
localparam ADDRW = `log2(MEMD) ; // address size
localparam LVTWBIN = `log2(nWPORTS); // LVT width for binary coding
localparam LVTW1HT = nWPORTS-1 ; // LVT width for onehot coding
localparam VERBOSE = 0 ; // verbose logging (1:yes; 0:no)
localparam CYCT = 10 ; // cycle time
localparam RSTT = 5.2*CYCT ; // reset time
localparam TERFAIL = 0 ; // terminate if fail?
localparam TIMEOUT = 2*CYCT*CYCC ; // simulation time
reg clk = 1'b0 ; // global clock
reg rst = 1'b1 ; // global reset
reg [nWPORTS-1:0 ] WEnb ; // write enable for each writing port
reg [ADDRW*nWPORTS-1:0] WAddr_pck ; // write addresses - packed from nWPORTS write ports
reg [ADDRW-1:0 ] WAddr_upk [nWPORTS-1:0]; // write addresses - unpacked 2D array
reg [ADDRW*nRPORTS-1:0] RAddr_pck ; // read addresses - packed from nRPORTS read ports
reg [ADDRW-1:0 ] RAddr_upk [nRPORTS-1:0]; // read addresses - unpacked 2D array
reg [DATAW*nWPORTS-1:0] WData_pck ; // write data - packed from nWPORTS read ports
reg [DATAW-1:0 ] WData_upk [nWPORTS-1:0]; // write data - unpacked 2D array
wire [DATAW*nRPORTS-1:0] RData_pck_reg ; // read data - packed from nRPORTS read ports
reg [DATAW-1:0 ] RData_upk_reg [nRPORTS-1:0]; // read data - unpacked 2D array
wire [DATAW*nRPORTS-1:0] RData_pck_xor ; // read data - packed from nRPORTS read ports
reg [DATAW-1:0 ] RData_upk_xor [nRPORTS-1:0]; // read data - unpacked 2D array
wire [DATAW*nRPORTS-1:0] RData_pck_lvtreg ; // read data - packed from nRPORTS read ports
reg [DATAW-1:0 ] RData_upk_lvtreg [nRPORTS-1:0]; // read data - unpacked 2D array
wire [DATAW*nRPORTS-1:0] RData_pck_lvtbin ; // read data - packed from nRPORTS read ports
reg [DATAW-1:0 ] RData_upk_lvtbin [nRPORTS-1:0]; // read data - unpacked 2D array
wire [DATAW*nRPORTS-1:0] RData_pck_lvt1ht ; // read data - packed from nRPORTS read ports
reg [DATAW-1:0 ] RData_upk_lvt1ht [nRPORTS-1:0]; // read data - unpacked 2D array
integer i,j; // general indeces
// generates random ram hex/mif initializing files
task genInitFiles;
input [31 :0] DEPTH ; // memory depth
input [31 :0] WIDTH ; // memoty width
input [255 :0] INITVAL; // initial vlaue (if not random)
input RAND ; // random value?
input [1:8*20] FILEN ; // memory initializing file name
reg [255 :0] ramdata;
integer addr,hex_fd,mif_fd;
begin
// open hex/mif file descriptors
hex_fd = $fopen({FILEN,".hex"},"w");
mif_fd = $fopen({FILEN,".mif"},"w");
// write mif header
$fwrite(mif_fd,"WIDTH = %0d;\n",WIDTH);
$fwrite(mif_fd,"DEPTH = %0d;\n",DEPTH);
$fwrite(mif_fd,"ADDRESS_RADIX = HEX;\n" );
$fwrite(mif_fd,"DATA_RADIX = HEX;\n\n" );
$fwrite(mif_fd,"CONTENT BEGIN\n" );
// write random memory lines
for(addr=0;addr<DEPTH;addr=addr+1) begin
if (RAND) begin
`GETRAND(ramdata,WIDTH);
end else ramdata = INITVAL;
$fwrite(hex_fd,"%0h\n",ramdata);
$fwrite(mif_fd," %0h : %0h;\n",addr,ramdata);
end
// write mif tail
$fwrite(mif_fd,"END;\n");
// close hex/mif file descriptors
$fclose(hex_fd);
$fclose(mif_fd);
end
endtask
integer rep_fd, ferr;
initial begin
// write header
rep_fd = $fopen("sim.res","r"); // try to open report file for read
$ferror(rep_fd,ferr); // detect error
$fclose(rep_fd);
rep_fd = $fopen("sim.res","a+"); // open report file for append
if (ferr) begin // if file is new (can't open for read); write header
$fwrite(rep_fd,"Multiported RAM Architectural Parameters Simulation Results for Different Designs \n");
$fwrite(rep_fd,"=========================================== =========================================\n");
$fwrite(rep_fd,"Memory Data Write Read Simulation XOR-based Reg-LVT SRAM-LVT SRAM-LVT\n");
$fwrite(rep_fd,"Depth Width Ports Ports Cycles Binary Onehot \n");
$fwrite(rep_fd,"=======================================================================================\n");
end
$write("Simulating multi-ported RAM:\n");
$write("Write ports : %0d\n" ,nWPORTS );
$write("Read ports : %0d\n" ,nRPORTS );
$write("Data width : %0d\n" ,DATAW );
$write("RAM depth : %0d\n" ,MEMD );
$write("Address width: %0d\n\n",ADDRW );
// generate random ram hex/mif initializing file
genInitFiles(MEMD,DATAW ,0,1,"init_ram");
// finish simulation
#(TIMEOUT) begin
$write("*** Simulation terminated due to timeout\n");
$finish;
end
end
// generate clock and reset
always #(CYCT/2) clk = ~clk; // toggle clock
initial #(RSTT ) rst = 1'b0; // lower reset
// pack/unpack data and addresses
`ARRINIT;
always @* begin
`ARR2D1D(nRPORTS,ADDRW,RAddr_upk ,RAddr_pck );
`ARR2D1D(nWPORTS,ADDRW,WAddr_upk ,WAddr_pck );
`ARR1D2D(nWPORTS,DATAW,WData_pck ,WData_upk );
`ARR1D2D(nRPORTS,DATAW,RData_pck_reg ,RData_upk_reg );
`ARR1D2D(nRPORTS,DATAW,RData_pck_xor ,RData_upk_xor );
`ARR1D2D(nRPORTS,DATAW,RData_pck_lvtreg,RData_upk_lvtreg);
`ARR1D2D(nRPORTS,DATAW,RData_pck_lvtbin,RData_upk_lvtbin);
`ARR1D2D(nRPORTS,DATAW,RData_pck_lvt1ht,RData_upk_lvt1ht);
end
// register write addresses
reg [ADDRW-1:0 ] WAddr_r_upk [nWPORTS-1:0]; // previous (registerd) write addresses - unpacked 2D array
always @(negedge clk)
//WAddr_r_pck <= WAddr_pck;
for (i=0;i<nWPORTS;i=i+1) WAddr_r_upk[i] <= WAddr_upk[i];
// generate random write data and random write/read addresses; on falling edge
reg wdw_addr; // indicates same write addresses on same cycle (Write-During-Write)
reg waw_addr; // indicates same write addresses on next cycle (Write-After-Write)
reg rdw_addr; // indicates same read/write addresses on same cycle (Read-During-Write)
reg raw_addr; // indicates same read address on next cycle (Read-After-Write)
always @(negedge clk) begin
// generate random write addresses; different that current and previous write addresses
for (i=0;i<nWPORTS;i=i+1) begin
wdw_addr = 1; waw_addr = 1;
while (wdw_addr || waw_addr) begin
`GETRAND(WAddr_upk[i],ADDRW);
wdw_addr = 0; waw_addr = 0;
if (!WDW) for (j=0;j<i ;j=j+1) wdw_addr = wdw_addr || (WAddr_upk[i] == WAddr_upk[j] );
if (!WAW) for (j=0;j<nWPORTS;j=j+1) waw_addr = waw_addr || (WAddr_upk[i] == WAddr_r_upk[j]);
end
end
// generate random read addresses; different that current and previous write addresses
for (i=0;i<nRPORTS;i=i+1) begin
rdw_addr = 1; raw_addr = 1;
while (rdw_addr || raw_addr) begin
`GETRAND(RAddr_upk[i],ADDRW);
rdw_addr = 0; raw_addr = 0;
if (!RDW) for (j=0;j<nWPORTS;j=j+1) rdw_addr = rdw_addr || (RAddr_upk[i] == WAddr_upk[j] );
if (!RAW) for (j=0;j<nWPORTS;j=j+1) raw_addr = raw_addr || (RAddr_upk[i] == WAddr_r_upk[j]);
end
end
// generate random write data and write enables
`GETRAND(WData_pck,DATAW*nWPORTS);
`GETRAND(WEnb , nWPORTS); if (rst) WEnb={nWPORTS{1'b0}};
end
integer cycc=1; // cycles count
integer cycp=0; // cycles percentage
integer errc=0; // errors count
integer fail;
integer pass_xor_cur ; // xor multiported-ram passed in current cycle
integer pass_lvt_reg_cur; // lvt_reg multiported-ram passed in current cycle
integer pass_lvt_bin_cur; // lvt_bin multiported-ram passed in current cycle
integer pass_lvt_1ht_cur; // lvt_1ht multiported-ram passed in current cycle
integer pass_xor = 1; // xor multiported-ram passed
integer pass_lvt_reg = 1; // lvt_reg multiported-ram passed
integer pass_lvt_bin = 1; // lvt_bin multiported-ram passed
integer pass_lvt_1ht = 1; // lvt_qht multiported-ram passed
always @(negedge clk)
if (!rst) begin
#(CYCT/10) // a little after falling edge
if (VERBOSE) begin // write input data
$write("%-7d:\t",cycc);
$write("BeforeRise: ");
$write("WEnb=" ); `ARRPRN(nWPORTS,WEnb ); $write("; ");
$write("WAddr=" ); `ARRPRN(nWPORTS,WAddr_upk ); $write("; ");
$write("WData=" ); `ARRPRN(nWPORTS,WData_upk ); $write("; ");
$write("RAddr=" ); `ARRPRN(nRPORTS,RAddr_upk ); $write(" - ");
end
#(CYCT/2) // a little after rising edge
// compare results
pass_xor_cur = (RData_pck_reg===RData_pck_xor );
pass_lvt_reg_cur = (RData_pck_reg===RData_pck_lvtreg);
pass_lvt_bin_cur = (RData_pck_reg===RData_pck_lvtbin);
pass_lvt_1ht_cur = (RData_pck_reg===RData_pck_lvt1ht);
pass_xor = pass_xor && pass_xor_cur ;
pass_lvt_reg = pass_lvt_reg && pass_lvt_reg_cur;
pass_lvt_bin = pass_lvt_bin && pass_lvt_bin_cur;
pass_lvt_1ht = pass_lvt_1ht && pass_lvt_1ht_cur;
fail = !(pass_xor && pass_lvt_reg && pass_lvt_bin && pass_lvt_1ht);
if (VERBOSE) begin // write outputs
$write("AfterRise: ");
$write("RData_reg=" ); `ARRPRN(nRPORTS,RData_upk_reg ); $write("; ");
$write("RData_xor=" ); `ARRPRN(nRPORTS,RData_upk_xor ); $write(":%s",pass_xor_cur ? "pass" : "fail"); $write("; " );
$write("RData_lvt_reg="); `ARRPRN(nRPORTS,RData_upk_lvtreg); $write(":%s",pass_lvt_reg_cur ? "pass" : "fail"); $write("; " );
$write("RData_lvt_bin="); `ARRPRN(nRPORTS,RData_upk_lvtbin); $write(":%s",pass_lvt_bin_cur ? "pass" : "fail"); $write("; " );
$write("RData_lvt_1ht="); `ARRPRN(nRPORTS,RData_upk_lvt1ht); $write(":%s",pass_lvt_1ht_cur ? "pass" : "fail"); $write(";\n");
end else begin
if ((100*cycc/CYCC)!=cycp) begin cycp=100*cycc/CYCC; $write("%-3d%% passed\t(%-7d / %-7d) cycles\n",cycp,cycc,CYCC); end
end
if (fail && TERFAIL) begin
$write("*** Simulation terminated due to a mismatch\n");
$finish;
end
if (cycc==CYCC) begin
$write("*** Simulation terminated after %0d cycles. Simulation results:\n",CYCC);
$write("XOR-based = %s",pass_xor ? "pass;\n" : "fail;\n");
$write("Register-based LVT = %s",pass_lvt_reg ? "pass;\n" : "fail;\n");
$write("Binary I-LVT = %s",pass_lvt_bin ? "pass;\n" : "fail;\n");
$write("Onehot I-LVT = %s",pass_lvt_1ht ? "pass;\n" : "fail;\n");
// Append report file
$fwrite(rep_fd,"%-7d %-5d %-5d %-5d %-10d %-9s %-7s %-8s %-08s\n",MEMD,DATAW,nWPORTS,nRPORTS,CYCC,pass_xor?"pass":"fail",pass_lvt_reg?"pass":"fail",pass_lvt_bin?"pass":"fail",pass_lvt_1ht?"pass":"fail");
$fclose(rep_fd);
$finish;
end
cycc=cycc+1;
end
// Bypassing indicators
localparam BYP = RDW ? "RDW" : (RAW ? "RAW" : (WAW ? "WAW" : "NON"));
// instantiate multiported register-based ram as reference for all other implementations
mpram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.TYPE ("REG" ), // multi-port RAM implementation type
.BYP (BYP ), // Bypassing type: NON, WAW, RAW, RDW
.IFILE ("init_ram" )) // initializtion file, optional
mpram_reg_ref ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr_pck ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData_pck ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr_pck ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_pck_reg )); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// instantiate XOR-based multiported-RAM
mpram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.TYPE ("XOR" ), // multi-port RAM implementation type
.BYP (BYP ), // Bypassing type: NON, WAW, RAW, RDW
.IFILE ("init_ram" )) // initializtion file, optional
mpram_xor_dut ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr_pck ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData_pck ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr_pck ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_pck_xor )); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// instantiate a multiported-RAM with binary-coded register-based LVT
mpram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.TYPE ("LVTREG" ), // multi-port RAM implementation type
.BYP (BYP ), // Bypassing type: NON, WAW, RAW, RDW
.IFILE ("init_ram" )) // initializtion file, optional
mpram_lvtreg_dut ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr_pck ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData_pck ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr_pck ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_pck_lvtreg)); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// instantiate a multiported-RAM with binary-coded SRAM LVT
mpram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.TYPE ("LVTBIN" ), // multi-port RAM implementation type
.BYP (BYP ), // Bypassing type: NON, WAW, RAW, RDW
.IFILE ("init_ram" )) // initializtion file, optional
mpram_lvtbin_dut ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr_pck ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData_pck ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr_pck ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_pck_lvtbin)); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// instantiate a multiported-RAM with onehot-coded SRAM LVT
mpram #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.TYPE ("LVT1HT" ), // multi-port RAM implementation type
.BYP (BYP ), // Bypassing type: NON, WAW, RAW, RDW
.IFILE ("init_ram" )) // initializtion file, optional
mpram_lvt1ht_dut ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr_pck ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData_pck ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr_pck ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_pck_lvt1ht)); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
endmodule
|
`include "hrfp_defs.vh"
module tb;
// Valid options: 5/0, 8/1
parameter PIPELINESTAGES = 8;
parameter ISMULT = 1;
parameter datafile = "input.txt";
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`MSBBIT:0] result; // From dut of adder.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To dut of adder.v
reg [`MSBBIT:0] op_a; // To dut of adder.v
reg [`MSBBIT:0] op_b; // To dut of adder.v
// End of automatics
generate
if (ISMULT) begin : dutmult
mult #(.MULT_LATENCY(PIPELINESTAGES-2))
dut (/*AUTOINST*/
// Outputs
.result (result[`MSBBIT:0]),
// Inputs
.clk (clk),
.op_a (op_a[`MSBBIT:0]),
.op_b (op_b[`MSBBIT:0]));
end else begin : dutadd
adder dut (/*AUTOINST*/
// Outputs
.result (result[`MSBBIT:0]),
// Inputs
.clk (clk),
.op_a (op_a[`MSBBIT:0]),
.op_b (op_b[`MSBBIT:0]));
end
endgenerate
reg isrunning = 1;
initial begin
clk = 0;
while(isrunning) begin
#10;
clk = 1;
#10;
clk = 0;
end
end
reg nocheck = 1;
integer fd;
integer exponent, grr;
reg sign;
reg [26:0] mantissa;
integer num1, num2, num_expected;
integer expected_result;
integer numiterations = 0;
reg [`MSBBIT:0] delayed_result;
reg [31:0] delayed_expected = 0;
reg [31:0] delayed_ieeeopa, delayed_ieeeopb;
task report_failure;
input integer iterations;
begin
$display("Expected result: %x (ieeeopa: %x, ieeeopb: %x), got the result %x", delayed_expected, delayed_ieeeopa, delayed_ieeeopb, {sign, exponent[7:0], mantissa[22:0]});
// The exact number of iterations will differ slightly due to the pipeline of the operators
$display("Rough number of iterations: %d", iterations);
$finish_and_return(1);
$stop;
end
endtask
// Convert the mantissa of an IEEE754 based float to the HRFP_16 format
function [26:0] conv_mant_to_hr;
input [31:0] ieee754_float;
integer tmpexp;
begin
if(!ieee754_float[30:0]) begin
conv_mant_to_hr = 0;
end else begin
tmpexp = ieee754_float[30:23] + 1; // Add a bias to ensure nice alignment
if(ieee754_float[30:23] > 0) begin
conv_mant_to_hr = (ieee754_float & 32'h7fffff) + 32'h800000;
end else begin
// Handle subnormals here
conv_mant_to_hr = (ieee754_float & 32'h7fffff) << 1; // Shift left by one since we now have an explicit one!
// Use 25:22 here to compensate for the bias above!
while(!conv_mant_to_hr[25:22]) conv_mant_to_hr = conv_mant_to_hr << 4;
end
conv_mant_to_hr = conv_mant_to_hr << tmpexp[1:0];
end
end
endfunction
// Convert the exponent of an IEEE754 based float to the HRFP_16 format
function [`EXPONENTBITS-1:0] conv_exp_to_hr;
input [31:0] ieee754_float;
integer tmpexp;
reg [26:0] tmp;
begin
if(!ieee754_float[30:0]) begin // Handle +/- zero
conv_exp_to_hr = 0;
end else begin
tmpexp = ieee754_float[30:23] + 1; // Add a bias to ensure nice alignment
conv_exp_to_hr = tmpexp[7:2] + 8'b01000000;
// Handle subnormals here
if(ieee754_float[30:23] == 0) begin
tmp = (ieee754_float & 32'h7fffff) << 1;
// Use 25:22 here to compensate for the bias above
while(!tmp[25:22]) begin
tmp = tmp << 4;
conv_exp_to_hr = conv_exp_to_hr - 1;
if(!tmp) begin
$display("INTERNAL FAILURE"); // +/- zero is handled above
$stop;
end
end
end
if (ieee754_float[30:23] == 255) begin
if (ieee754_float[22:0]) begin
conv_exp_to_hr = 8'b11000000; // NaN
end else begin
conv_exp_to_hr = 8'b10000000; // Inf
end
end
end
end
endfunction
initial begin : TESTER
integer i;
op_a = 0;
op_b = 0;
num1 = 0;
num2 = 0;
num_expected = 0;
repeat(26) @(posedge clk);
fd=$fopen(datafile,"r");
nocheck = 0;
for(i=1; i < 64; i = i * 2) begin
$display("Converting 0x%08x to HRFP: %b %b", i, conv_exp_to_hr(i), conv_mant_to_hr(i));
end
while($fscanf(fd, "%x %x %x",num1, num2, num_expected) == 3) begin
`ifdef DEBUG
$display("**********************************************************************");
$display(" Adding %08x to %08x", num1, num2);
$display(" %b %b %b", num1[31], num1[30:23], num1[22:0]);
$display(" %b %b %b", num2[31], num2[30:23], num2[22:0]);
$display(" Expdiff is %d", num1[30:23] - num2[30:23]);
$display("**********************************************************************");
$display("IEEE: mantissa: %b, exp: %d",num1[22:0], num1[30:23]);
`endif
sign = num1[31];
op_a`MANTISSA <= conv_mant_to_hr(num1);
op_a`EXPONENT <= conv_exp_to_hr(num1);
op_a`SIGN <= sign;
if(num1[30:23] == 8'hff) begin
op_a`IS_NAN_OR_INF <= 1;
op_a`HRFP_IS_NAN <= 0;
if(num1[22:0]) begin
op_a`HRFP_IS_NAN <= 1;
end
end
#1;
`ifdef DEBUG
$display("opa %x (mantissa is %b, exponent is %x, sign is %x)", op_a, mantissa, exponent, sign);
$display("IEEE2: mantissa: %b, exp: %d",num2[22:0], num2[30:23]);
`endif
sign = num2[31];
op_b`MANTISSA <= conv_mant_to_hr(num2);
op_b`EXPONENT <= conv_exp_to_hr(num2);
op_b`SIGN <= sign;
if(num2[30:23] == 8'hff) begin
op_b`IS_NAN_OR_INF <= 1;
op_b`HRFP_IS_NAN <= 0;
if(num2[22:0]) begin
op_b`HRFP_IS_NAN <= 1;
end
end
#1;
`ifdef DEBUG
$display("opb %x (mantissa is %b, exponent is %x, sign is %x)", op_b, mantissa, exponent, sign);
`endif
delayed_expected <= repeat(PIPELINESTAGES) @(posedge clk) num_expected;
delayed_ieeeopa <= repeat(PIPELINESTAGES) @(posedge clk) num1;
delayed_ieeeopb <= repeat(PIPELINESTAGES) @(posedge clk) num2;
@(posedge clk);
numiterations = numiterations + 1;
end
isrunning = 0;
#5000; // Make sure we can detect an error in the last couple of cycles...
$display("No errors detected during roughly %d iterations!",numiterations);
end // initial begin
// This always block is responsible for converting a HRFP_16 number to IEEE-754 format and then
// checking that the number is equal to the expected IEEE_754 value.
always @(posedge clk) begin
while(nocheck) begin // Wait here until the testbench releases us by deactivating nocheck
@(posedge clk);
end
mantissa = result`MANTISSA;
exponent = result`EXPONENT;
sign = result`SIGN;
`ifdef DEBUG
$display(" Result is %x (mantissa is %b, exponent is %x, sign is %x)", result, result[26:0], result[32:27], result[33]);
$display("Expected pattern is %x (mantissa %b)", delayed_expected, delayed_expected[22:0]);
`endif
//
exponent = exponent << 2;
casez(mantissa[26:23])
4'b1???: begin mantissa = mantissa; exponent = exponent+3; end
4'b01??: begin mantissa = mantissa << 1; exponent = exponent + 2; end
4'b001?: begin mantissa = mantissa << 2; exponent = exponent + 1; end
4'b0001: begin mantissa = mantissa << 3; exponent = exponent + 0; end
4'b0000: begin mantissa = mantissa << 3; end
endcase // casez (mantissa[26:23])
if(exponent) begin
exponent = exponent - 1; // Adjust for bias added above.
// Unless exponent is zero in which case we shouldn't wrap around.
end
if(mantissa[2:0] !== 0) begin
$display("ERROR (iteration %d): Some bits were not masked out as needed!", numiterations);
report_failure(numiterations);
$stop;
end
if(exponent == 10'b0100000000) begin // subnormals!
mantissa = mantissa >> 4;
end else if(exponent < 58) begin // This is a zero...
mantissa = 0;
exponent = 10'b0100000000;
end else if(exponent < 10'b0100000000) begin
mantissa = mantissa >> 4;
mantissa = mantissa >> ((10'b0100000000 - exponent));
exponent = 10'b0100000000; // Normalized...
end else begin
mantissa = mantissa >> 3;
mantissa = mantissa & 23'h7fffff; // Remove explicit one!
end
exponent = exponent - 10'b0100000000; // Bias
`ifdef DEBUG
$display("Result is 0x%08x (raw result is %x)",{sign,exponent[7:0],mantissa[22:0]}, result);
`endif
if(delayed_expected[30:23] == 255) begin
if(delayed_expected[22:0] != 0) begin
`ifdef DEBUG
$display(" This is not a number!");
`endif
if(! (result`IS_NAN_OR_INF && result`HRFP_IS_NAN)) begin
$display("ERROR: Expected a NaN but didn't receive it!");
report_failure(numiterations);
$stop;
end
end else begin
if(! (result`IS_NAN_OR_INF && !result`HRFP_IS_NAN)) begin
$display("Expected an inf but didn't receive it!");
report_failure(numiterations);
$stop;
end
if (sign !== delayed_expected[31]) begin
$display("Got wrong inf sign!");
report_failure(numiterations);
$stop;
end
end
end else if({sign,exponent[7:0],mantissa[22:0]} !== delayed_expected) begin
if(result`IS_NAN_OR_INF) begin
$display("ERROR: IS_NAN_OR_INF was set even though expected number is not NaN or inf!");
report_failure(numiterations);
$stop;
end
$display("ERROR: gotten pattern (%08x) is not identical to expected pattern (%08x) (iteration is %d)",
{sign,exponent[7:0],mantissa[22:0]}, delayed_expected, numiterations);
report_failure(numiterations);
$stop;
end // if ({sign,exponent[7:0],mantissa[22:0]} !== delayed_expected)
end
endmodule // tb_adder
|
module env_io (/*AUTOARG*/
// Outputs
DI,
// Inputs
clk, iorq_n, rd_n, wr_n, addr, DO
);
input clk;
input iorq_n;
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
inout [7:0] DI;
reg [7:0] io_data;
reg [7:0] str_buf [0:255];
reg io_cs;
integer buf_ptr, i;
reg [7:0] timeout_ctl;
reg [15:0] cur_timeout;
reg [15:0] max_timeout;
reg [7:0] int_countdown;
reg [7:0] checksum;
reg [7:0] ior_value; // increment-on-read value
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
initial
begin
io_cs = 0;
buf_ptr = 0;
cur_timeout = 0;
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
end
always @*
begin
if (!iorq_n & !rd_n)
begin
io_cs = (addr[7:5] == 3'b100);
case (addr)
8'h82 : io_data = timeout_ctl;
8'h83 : io_data = max_timeout[7:0];
8'h84 : io_data = max_timeout[15:8];
8'h90 : io_data = int_countdown;
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
default : io_data = 8'hzz;
endcase // case(addr)
end // if (!iorq_n & !rd_n)
end // always @ *
wire wr_stb;
reg last_iowrite;
assign wr_stb = (!iorq_n & !wr_n);
always @(posedge clk)
begin
last_iowrite <= #1 wr_stb;
if (!wr_stb & last_iowrite)
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
2 : tb_top.test_fail;
3 : tb_top.dumpon;
4 : tb_top.dumpoff;
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
end
endcase // case(DO)
end // case: :...
8'h81 :
begin
str_buf[buf_ptr] = DO;
buf_ptr = buf_ptr + 1;
//$display ("%t: DEBUG : Detected write of character %x", $time, DO);
if (DO == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
for (i=0; i<buf_ptr; i=i+1)
$write ("%s", str_buf[i]);
buf_ptr = 0;
end
end // case: 8'h81
8'h82 :
begin
timeout_ctl = DO;
end
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
endcase // case(addr)
end // always @ (posedge clk)
always @(posedge clk)
begin
if (timeout_ctl[1])
cur_timeout = 0;
else if (timeout_ctl[0])
cur_timeout = cur_timeout + 1;
if (cur_timeout >= max_timeout)
begin
$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
tb_top.test_fail;
end
end // always @ (posedge clk)
always @(posedge clk)
begin
if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
end
else if (int_countdown > 1)
begin
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
end
endmodule // env_io
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Reduced Normalization module
//
// This module performs realignment of data such that the most significant bit is
// 1 for any number with exponent >= 1, and zero otherwise.
//
module acl_fp_custom_reduced_normalize_double(
clock, resetn,
mantissa, exponent, sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable,
mantissa_out, exponent_out, sign_out);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [56:0] mantissa;
input [11:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [55:0] mantissa_out; // When mantissa_out[54] = 1 and exponent_out[11] == 1 then the number is NaN.
output [11:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
// Stall/valid and enable signals on per-stage basis.
reg c1_valid;
reg c2_valid;
reg c3_valid;
reg c4_valid;
reg c5_valid;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
// Cycle 1 - We are just doing the shifting here.
reg [56:0] c1_mantissa;
reg [11:0] c1_exponent;
reg [5:0] c1_max_shift;
reg c1_sign;
reg c1_exponent_is_max;
reg c1_exponent_is_nonzero;
reg [13:0] c1_mantissa_nonzero;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 57'dx;
c1_exponent <= 12'dx;
c1_sign <= 1'bx;
c1_exponent_is_max <= 1'bx;
c1_exponent_is_nonzero <= 1'bx;
c1_mantissa_nonzero <= 14'dx;
c1_max_shift <= 6'dx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent <= exponent;
c1_exponent_is_max <= (&exponent[10:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[10:0];
c1_mantissa_nonzero <= {|mantissa[55:52], |mantissa[51:48], |mantissa[47:44], |mantissa[43:40], |mantissa[39:36], |mantissa[35:32], |mantissa[31:28], |mantissa[27:24], |mantissa[23:20], |mantissa[19:16], |mantissa[15:12], |mantissa[11:8], |mantissa[7:4], |mantissa[3:0]};
if ((FINITE_MATH_ONLY == 0) && (exponent == 12'h7fe) && mantissa[56])
begin
c1_mantissa[56] <= 1'b1;
c1_mantissa[55:0] <= 56'd0;
end
else
c1_mantissa <= mantissa;
c1_max_shift <= exponent[11] ? 6'd0 : ({6{|exponent[10:6]}} | {exponent[5:0] - 1'b1});
end
end
// Cycle 2 - Shift by 32, 0 or -1.
reg [55:0] c2_mantissa;
reg [11:0] c2_exponent;
reg c2_sign;
reg [4:0] c2_max_shift;
reg [2:0] c2_mantissa_nonzero;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa <= 56'dx;
c2_exponent <= 12'dx;
c2_sign <= 1'bx;
c2_mantissa_nonzero <= 3'dx;
c2_max_shift <= 5'dx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if (c1_mantissa[56])
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[56:1];
else
c2_mantissa <= {c1_mantissa[56:2], |c1_mantissa[1:0]};
c2_mantissa_nonzero <= 3'b111;
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 12'hfff;
else
c2_exponent <= c1_exponent + {1'b0, ~c1_exponent_is_nonzero, c1_exponent_is_nonzero};
end
else
if (~(|c1_mantissa_nonzero[13:6]) && (c1_max_shift[5]) && c1_exponent_is_nonzero)
begin
// 32
c2_mantissa <= {c1_mantissa[23:0], 32'd0};
c2_exponent <= c1_exponent - 7'd32;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[5:4], |c1_mantissa_nonzero[3:2], |c1_mantissa_nonzero[1:0]};
c2_max_shift <= (c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
else
begin
// 0
c2_mantissa <= c1_mantissa[55:0];
c2_exponent <= c1_exponent;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[13:12], |c1_mantissa_nonzero[11:10], |c1_mantissa_nonzero[9:8]};
c2_max_shift <= ({5{c1_max_shift[5]}} | c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
end
end
end
else
begin
// Do not register this stage in low-latency mode.
always@(*)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if (c1_mantissa[56])
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[56:1];
else
c2_mantissa <= {c1_mantissa[56:2], |c1_mantissa[1:0]};
c2_mantissa_nonzero <= 3'b111;
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 12'hfff;
else
c2_exponent <= c1_exponent + {1'b0, ~c1_exponent_is_nonzero, c1_exponent_is_nonzero};
end
else
if (~(|c1_mantissa_nonzero[13:6]) && (c1_max_shift[5]) && c1_exponent_is_nonzero)
begin
// 32
c2_mantissa <= {c1_mantissa[23:0], 32'd0};
c2_exponent <= c1_exponent - 7'd32;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[5:4], |c1_mantissa_nonzero[3:2], |c1_mantissa_nonzero[1:0]};
c2_max_shift <= (c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
else
begin
// 0
c2_mantissa <= c1_mantissa[55:0];
c2_exponent <= c1_exponent;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[13:12], |c1_mantissa_nonzero[11:10], |c1_mantissa_nonzero[9:8]};
c2_max_shift <= ({5{c1_max_shift[5]}} | c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
end
end
endgenerate
// Cycle 3 - Shift by 16 or 0 here.
reg [55:0] c3_mantissa;
reg [11:0] c3_exponent;
reg [3:0] c3_max_shift;
reg c3_mantissa_nonzero;
reg c3_sign;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_mantissa <= 56'dx;
c3_exponent <= 12'dx;
c3_sign <= 1'bx;
c3_max_shift <= 4'dx;
c3_mantissa_nonzero <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_sign <= c2_sign;
if (~(|c2_mantissa_nonzero[2:1]) && (c2_max_shift[4]))
begin
// 16
c3_mantissa <= {c2_mantissa[39:0], 16'd0};
c3_exponent <= c2_exponent - 6'd16;
c3_max_shift <= c2_max_shift[3:0];
c3_mantissa_nonzero <= c2_mantissa_nonzero[0];
end
else
begin
// 0
c3_mantissa <= c2_mantissa;
c3_exponent <= c2_exponent;
c3_max_shift <= c2_max_shift[3:0] | {4{c2_max_shift[4]}};
c3_mantissa_nonzero <= c2_mantissa_nonzero[2];
end
end
end
// Cycle 4 - Shift by 12, 8, 4 or 0 here.
reg [55:0] c4_mantissa;
reg [11:0] c4_exponent;
reg [1:0] c4_max_shift;
reg c4_sign;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_mantissa <= 56'dx;
c4_exponent <= 12'dx;
c4_sign <= 1'bx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_sign <= c3_sign;
if (~c3_mantissa_nonzero && (~|c3_mantissa[47:44]) && (&c3_max_shift[3:2]))
begin
// 12
c4_mantissa <= {c3_mantissa[43:0], 12'd0};
c4_exponent <= c3_exponent - 6'd12;
c4_max_shift <= c3_max_shift[1:0];
end
else
if (~c3_mantissa_nonzero && (c3_max_shift[3]))
begin
// 8
c4_mantissa <= {c3_mantissa[47:0], 8'd0};
c4_exponent <= c3_exponent - 6'd8;
c4_max_shift <= c3_max_shift[1:0] | {2{c3_max_shift[2]}};
end
else
if ((~|c3_mantissa[55:52]) && (c3_max_shift[2]))
begin
// 4
c4_mantissa <= {c3_mantissa[51:0], 4'd0};
c4_exponent <= c3_exponent - 6'd4;
c4_max_shift <= c3_max_shift[1:0] | {2{c3_max_shift[3]}};
end
else
begin
// 0
c4_mantissa <= c3_mantissa;
c4_exponent <= c3_exponent;
c4_max_shift <= c3_max_shift[1:0] | {2{|c3_max_shift[3:2]}};
end
end
end
// Cycle 5 - Shift by 3,2,1 or 0 here.
reg [55:0] c5_mantissa;
reg [11:0] c5_exponent;
reg c5_sign;
assign c5_enable = (HIGH_CAPACITY == 1) ? (~c5_valid | ~c5_stall) : enable;
assign c4_stall = c5_valid & c5_stall;
reg [1:0] shift_by;
always@(*)
begin
if (~|c4_mantissa[55:53])
shift_by = c4_max_shift;
else if (~|c4_mantissa[55:54])
shift_by = {c4_max_shift[1], c4_max_shift[0] & ~c4_max_shift[1]};
else if (~c4_mantissa[55])
shift_by = {1'b0, |c4_max_shift};
else
shift_by = 2'b00;
end
wire [55:0] resulting_mantissa = c4_mantissa << shift_by;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_mantissa <= 56'dx;
c5_exponent <= 12'dx;
c5_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_sign <= c4_sign;
c5_mantissa <= resulting_mantissa;
if (~resulting_mantissa[55] && ~c4_exponent[11])
begin
// This number just became denormalized
c5_exponent <= 12'd0;
end
else
begin
c5_exponent <= c4_exponent - {1'b0, shift_by};
end
end
end
assign mantissa_out = c5_mantissa;
assign exponent_out = c5_exponent;
assign sign_out = c5_sign;
assign valid_out = c5_valid;
assign c5_stall = stall_in;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/14/2016 05:02:16 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// select 300 DPI or 600 DPI mode
`define DPI_300
// `define DPI_600
// Period of CIS clock is equal to 60MHz/USB_CLK_DIV
// Must be an even number
`define USB_CLK_DIV 'd12
// Sample ADC 16.7ns before the next rising edge of CIS_CLK
`define ADC_CLK_DELAY (`USB_CLK_DIV/2)-1
// Issue write pulse immediately before next rising edge of ADC_CLK
// `define WR_PULSE_DELAY (`USB_CLK_DIV/2)-2
`define WR_PULSE_DELAY 4
// define the clock window when the LED needs to be off
`define CIS_LED_OFF 'd40
`define CIS_LED_ON 'd70
// define the clock cycle at which the oscilloscope should be triggered
`define SCOPE_SYNC_POS 'd1000
`ifdef DPI_300
`define CIS_CLK_PER_LINE 'd2700
`else
`define CIS_CLK_PER_LINE 'd5300
`endif
module top(
// Inputs from USB IC
input USB_CLK,
// Inputs from ADC
input [7:0] ADC_DATA,
// Outputs to CIS module
output CIS_MODE,
output reg CIS_CLK,
output reg CIS_SP,
output reg CIS_LED_BLUE,
output reg CIS_LED_GREEN,
output reg CIS_LED_RED,
// Outputs to USB IC
output [7:0] USB_DATA,
output reg USB_WR_L,
// Outputs to ADC
output reg ADC_CLK,
// Outputs to oscilloscope
output reg SCOPE_SYNC
);
// internal reg variables
reg [3:0] counter_usb_clk;
reg [12:0] counter_cis_clk;
// Set the DPI mode of the scanner
`ifdef DPI_300
assign CIS_MODE = 'b0;
`else
assign CIS_MODE = 'b1;
`endif
assign USB_DATA = ADC_DATA;
initial begin
// output initializations
USB_WR_L = 'b0;
CIS_CLK = 'b0;
CIS_SP = 'b1;
CIS_LED_BLUE = 'b1;
CIS_LED_GREEN = 'b1;
CIS_LED_RED = 'b1;
SCOPE_SYNC = 'b0;
// internal counter variables
counter_usb_clk = 'd1;
counter_cis_clk = 'd1;
end
// Generate the clock used to read out from the CIS module
// by dividing down the 60MHz clock
always @(posedge USB_CLK) begin
// Generate the CIS clock signal
if (0 <= counter_usb_clk && counter_usb_clk < (`USB_CLK_DIV/2)) begin
CIS_CLK <= 'b1;
end else begin
CIS_CLK <= 'b0;
end
// Generate the shifted ADC sampling clock
if (`ADC_CLK_DELAY <= counter_usb_clk && counter_usb_clk < (`ADC_CLK_DELAY+`USB_CLK_DIV/2)) begin
ADC_CLK <= 'b1;
end else begin
ADC_CLK <= 'b0;
end
// Increment the clock counter
if (counter_usb_clk == (`USB_CLK_DIV-1)) begin
counter_usb_clk <= 'd0;
end else begin
counter_usb_clk <= counter_usb_clk + 'd1;
end
end
always @(negedge USB_CLK) begin
if (counter_usb_clk == `WR_PULSE_DELAY) begin
USB_WR_L <= 'b0;
end else begin
USB_WR_L <= 'b1;
end
end
always @(posedge CIS_CLK) begin
// update LED settings
if (counter_cis_clk == `CIS_LED_OFF) begin
CIS_LED_BLUE <= 'b0;
CIS_LED_GREEN <= 'b0;
CIS_LED_RED <= 'b0;
end else if (counter_cis_clk == `CIS_LED_ON) begin
CIS_LED_BLUE <= 'b1;
CIS_LED_GREEN <= 'b1;
CIS_LED_RED <= 'b1;
end
// update CIS counter
if (counter_cis_clk == `CIS_CLK_PER_LINE) begin
counter_cis_clk <= 'd1;
CIS_SP <= 'b1;
end else begin
counter_cis_clk <= counter_cis_clk + 'd1;
CIS_SP <= 'b0;
end
// update SCOPE_SYNC signal
if (counter_cis_clk == `SCOPE_SYNC_POS) begin
SCOPE_SYNC <= 1'b1;
end else begin
SCOPE_SYNC <= 1'b0;
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////
module arduino_switch_digital_uart_bit(
// configuration
input gpio_sel, // 0=digital I/O, 1= uart
// Shield connector side
input tri_i_out, // data from shield pin to switch
output reg tri_o_out, // data from switch to shield pin
output reg tri_t_out, // tri state control from switch to shield pin
// PL side
// digital I/O
output tri_i_in, // data from switch to PL
input tri_o_in, // data from PL to switch
input tri_t_in, // tri state control from PL to switch
// RX and TX of UART
output rx_i_in, // rx data from switch to UART
input tx_o_in, // tx data from UART to switch
input tx_t_in // tx tri state control from UART to switch
);
reg [1:0] tri_i_out_demux;
assign {rx_i_in, tri_i_in} = tri_i_out_demux;
always @(gpio_sel, tri_o_in, tx_o_in)
case (gpio_sel)
1'h0: tri_o_out = tri_o_in; // digital I/O
1'h1: tri_o_out = tx_o_in; // tx
endcase
always @(gpio_sel, tri_i_out)
begin
tri_i_out_demux = {2{1'b0}};
case (gpio_sel)
1'h0: tri_i_out_demux[0] = tri_i_out; // digital I/O
1'h1: tri_i_out_demux[1] = tri_i_out; // rx
endcase
end
always @(gpio_sel, tri_t_in, tx_t_in)
case (gpio_sel)
1'h0: tri_t_out = tri_t_in; // digital I/O
1'h1: tri_t_out = tx_t_in; // tx
endcase
endmodule
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 1:0] rvfi_mode,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax).
begin end
endtask
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// Internal PCPI Cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
generate if (ENABLE_FAST_MUL) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (ENABLE_MUL) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (ENABLE_DIV) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
ENABLE_PCPI && pcpi_ready: begin
pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
end
(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
ENABLE_DIV && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// Memory Interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // C.LW
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // C.ADDI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // C.LI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // C.LUI
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (COMPRESSED_ISA && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (COMPRESSED_ISA && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// Instruction Decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_uj;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef DEBUGASM
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // C.LW
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // C.SW
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // C.JAL
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // C.LI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // C.LUI
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_uj;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
end
end
// Main State Machine
localparam cpu_state_trap = 8'b10000000;
localparam cpu_state_fetch = 8'b01000000;
localparam cpu_state_ld_rs1 = 8'b00100000;
localparam cpu_state_ld_rs2 = 8'b00010000;
localparam cpu_state_exec = 8'b00001000;
localparam cpu_state_shift = 8'b00000100;
localparam cpu_state_stmem = 8'b00000010;
localparam cpu_state_ldmem = 8'b00000001;
reg [7:0] cpu_state;
reg [1:0] irq_state;
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = COMPRESSED_ISA;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef PICORV32_REGS
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
`PICORV32_REGS cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (WITH_PCPI && CATCH_ILLINSN) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (ENABLE_COUNTERS) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!ENABLE_TRACE)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
if (ENABLE_COUNTERS)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~STACKADDR) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= STACKADDR;
end
cpu_state <= cpu_state_fetch;
end else
(* parallel_case, full_case *)
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
ENABLE_IRQ && irq_state[0]: begin
current_pc = PROGADDR_IRQ;
irq_active <= 1;
mem_do_rinst <= 1;
end
ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (ENABLE_IRQ_QREGS)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
latched_trace <= 1;
if (ENABLE_COUNTERS) begin
count_instr <= count_instr + 1;
if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_uj;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
pcpi_valid <= 1;
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && ENABLE_COUNTERS64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && ENABLE_COUNTERS64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | MASKED_IRQ;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (ENABLE_TRACE)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (!CATCH_MISALIGN) begin
if (COMPRESSED_ISA) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef RISCV_FORMAL
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
rvfi_mode <= 3;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// Formal Verification
`ifdef FORMAL
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
// This is a simple example implementation of PICORV32_REGS.
// Use the PICORV32_REGS mechanism if you want to use custom
// memory resources to implement the processor register file.
// Note that your implementation must match the requirements of
// the PicoRV32 configuration. (e.g. QREGS, etc)
module picorv32_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:30];
always @(posedge clk)
if (wen) regs[~waddr[4:0]] <= wdata;
assign rdata1 = regs[~raddr1[4:0]];
assign rdata2 = regs[~raddr2[4:0]];
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
parameter STEPS_AT_ONCE = 1,
parameter CARRY_CHAIN = 4
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg pcpi_wait_q;
wire mul_start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_mul <= 0;
instr_mulh <= 0;
instr_mulhsu <= 0;
instr_mulhu <= 0;
if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b000: instr_mul <= 1;
3'b001: instr_mulh <= 1;
3'b010: instr_mulhsu <= 1;
3'b011: instr_mulhu <= 1;
endcase
end
pcpi_wait <= instr_any_mul;
pcpi_wait_q <= pcpi_wait;
end
reg [63:0] rs1, rs2, rd, rdx;
reg [63:0] next_rs1, next_rs2, this_rs2;
reg [63:0] next_rd, next_rdx, next_rdt;
reg [6:0] mul_counter;
reg mul_waiting;
reg mul_finish;
integer i, j;
// carry save accumulator
always @* begin
next_rd = rd;
next_rdx = rdx;
next_rs1 = rs1;
next_rs2 = rs2;
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
this_rs2 = next_rs1[0] ? next_rs2 : 0;
if (CARRY_CHAIN == 0) begin
next_rdt = next_rd ^ next_rdx ^ this_rs2;
next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
next_rd = next_rdt;
end else begin
next_rdt = 0;
for (j = 0; j < 64; j = j + CARRY_CHAIN)
{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
next_rdx = next_rdt << 1;
end
next_rs1 = next_rs1 >> 1;
next_rs2 = next_rs2 << 1;
end
end
always @(posedge clk) begin
mul_finish <= 0;
if (!resetn) begin
mul_waiting <= 1;
end else
if (mul_waiting) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
rd <= 0;
rdx <= 0;
mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
mul_waiting <= !mul_start;
end else begin
rd <= next_rd;
rdx <= next_rdx;
rs1 <= next_rs1;
rs2 <= next_rs2;
mul_counter <= mul_counter - STEPS_AT_ONCE;
if (mul_counter[6]) begin
mul_finish <= 1;
mul_waiting <= 1;
end
end
end
always @(posedge clk) begin
pcpi_wr <= 0;
pcpi_ready <= 0;
if (mul_finish && resetn) begin
pcpi_wr <= 1;
pcpi_ready <= 1;
pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
end
end
endmodule
module picorv32_pcpi_fast_mul #(
parameter EXTRA_MUL_FFS = 0,
parameter EXTRA_INSN_FFS = 0,
parameter MUL_CLKGATE = 0
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output pcpi_wr,
output [31:0] pcpi_rd,
output pcpi_wait,
output pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg shift_out;
reg [3:0] active;
reg [32:0] rs1, rs2, rs1_q, rs2_q;
reg [63:0] rd, rd_q;
wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
reg pcpi_insn_valid_q;
always @* begin
instr_mul = 0;
instr_mulh = 0;
instr_mulhsu = 0;
instr_mulhu = 0;
if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
case (pcpi_insn[14:12])
3'b000: instr_mul = 1;
3'b001: instr_mulh = 1;
3'b010: instr_mulhsu = 1;
3'b011: instr_mulhu = 1;
endcase
end
end
always @(posedge clk) begin
pcpi_insn_valid_q <= pcpi_insn_valid;
if (!MUL_CLKGATE || active[0]) begin
rs1_q <= rs1;
rs2_q <= rs2;
end
if (!MUL_CLKGATE || active[1]) begin
rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
end
if (!MUL_CLKGATE || active[2]) begin
rd_q <= rd;
end
end
always @(posedge clk) begin
if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
active[0] <= 1;
end else begin
active[0] <= 0;
end
active[3:1] <= active;
shift_out <= instr_any_mulh;
if (!resetn)
active <= 0;
end
assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
assign pcpi_wait = 0;
assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
`ifdef RISCV_FORMAL_ALTOPS
assign pcpi_rd =
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
`else
assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
`endif
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_div, instr_divu, instr_rem, instr_remu;
wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
reg pcpi_wait_q;
wire start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_div <= 0;
instr_divu <= 0;
instr_rem <= 0;
instr_remu <= 0;
if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b100: instr_div <= 1;
3'b101: instr_divu <= 1;
3'b110: instr_rem <= 1;
3'b111: instr_remu <= 1;
endcase
end
pcpi_wait <= instr_any_div_rem && resetn;
pcpi_wait_q <= pcpi_wait && resetn;
end
reg [31:0] dividend;
reg [62:0] divisor;
reg [31:0] quotient;
reg [31:0] quotient_msk;
reg running;
reg outsign;
always @(posedge clk) begin
pcpi_ready <= 0;
pcpi_wr <= 0;
pcpi_rd <= 'bx;
if (!resetn) begin
running <= 0;
end else
if (start) begin
running <= 1;
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
quotient <= 0;
quotient_msk <= 1 << 31;
end else
if (!quotient_msk && running) begin
running <= 0;
pcpi_ready <= 1;
pcpi_wr <= 1;
`ifdef RISCV_FORMAL_ALTOPS
case (1)
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
endcase
`else
if (instr_div || instr_divu)
pcpi_rd <= outsign ? -quotient : quotient;
else
pcpi_rd <= outsign ? -dividend : dividend;
`endif
end else begin
if (divisor <= dividend) begin
dividend <= dividend - divisor;
quotient <= quotient | quotient_msk;
end
divisor <= divisor >> 1;
`ifdef RISCV_FORMAL_ALTOPS
quotient_msk <= quotient_msk >> 5;
`else
quotient_msk <= quotient_msk >> 1;
`endif
end
end
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output trap,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_rdata;
picorv32_axi_adapter axi_adapter (
.clk (clk ),
.resetn (resetn ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
input clk, resetn,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Native PicoRV32 memory interface
input mem_valid,
input mem_instr,
output mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
always @(posedge clk) begin
if (!resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_valid && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_valid) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_vref_logic_high.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_vref_logic_high(in,vrefcode,vdd18);
input vdd18;
input [7:1] in;
output [7:0] vrefcode;
assign vrefcode[7:0] = {in[7:1],1'b0};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR2_PP_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_PP_BLACKBOX_V
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/05/2009
This FIFO module behaves similar to scfifo in legacy mode. It has an
output latency of 1 or 2 clock cycles and does not support look ahead
mode. Unlike scfifo this FIFO allows you to write to any of the byte
lanes before committing the word. This allows you to write the full
word in multiple clock cycles and then you assert the "push" signal to
commit the data. To read data out of the FIFO assert "pop" and wait
1 or 2 clock cycles for valid data to arrive.
Version 1.1
1.0 - Uses 'altsyncram' which will not be optimized away if the
FIFO inputs are grounded. This will need to be replaced
with inferred memory once Quartus II supports inferred
with byte enables (currently it instantiates multiple
seperate memories.
1.1 - Seperated the asynchronous reset into seperate async. and sync.
resets.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
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