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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_TB_V
`define SKY130_FD_SC_HD__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_TB_V
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming decoder
*/
module decoder4to16 (in,out);
// Output signals representing the 11-bit decoded vector
output reg [15:1] out;
// Input signals representing the 15-bit input
input [3:0] in;
// Declare "reg" signals...
reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
// Invert the inputs...
in_bar=~in;
// Don't define out[0] because you don't wanna flip correct outputs
//out[0]=in_bar[0] & in_bar[1] & in_bar[2] & in_bar[3];
out[1]=in[0] & in_bar[1] & in_bar[2] & in_bar[3];
out[2]=in_bar[0] & in[1] & in_bar[2] & in_bar[3];
out[3]=in[0] & in[1] & in_bar[2] & in_bar[3];
out[4]=in_bar[0] & in_bar[1] & in[2] & in_bar[3];
out[5]=in[0] & in_bar[1] & in[2] & in_bar[3];
out[6]=in_bar[0] & in[1] & in[2] & in_bar[3];
out[7]=in[0] & in[1] & in[2] & in_bar[3];
out[8]=in_bar[0] & in_bar[1] & in_bar[2] & in[3];
out[9]=in[0] & in_bar[1] & in_bar[2] & in[3];
out[10]=in_bar[0] & in[1] & in_bar[2] & in[3];
out[11]=in[0] & in[1] & in_bar[2] & in[3];
out[12]=in_bar[0] & in_bar[1] & in[2] & in[3];
out[13]=in[0] & in_bar[1] & in[2] & in[3];
out[14]=in_bar[0] & in[1] & in[2] & in[3];
out[15]=in[0] & in[1] & in[2] & in[3];
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_BEHAVIORAL_V |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [23:0] SNES_ADDR, // requested address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK
);
wire [23:0] SRAM_SNES_ADDR;
/* static mapper:
menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
);
assign SRAM_SNES_ADDR = (IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hC00000)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_SAVERAM;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized 16/32 word deep FIFO.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_SYMBOL_V
`define SKY130_FD_SC_LP__O32A_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_SYMBOL_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: A small shadow-RAM to qualify the data entries in the dual-port
// compram
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modification by zjs, 2009-6-18, pending
// (1) move posted packet generator and non-posted packet generator out --- done
// (2) add dma write data fifo --------------- done
// (3) modify tx sm
// scheduling -------------------------- done
// disable write dma done -------------- done
// register/memory read ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pending_comp_ram_32x1(
input clk,
input d_in,
input [4:0] addr,
input we,
output reg [31:0] d_out = 32'h00000000
);
wire [31:0] addr_decode;
//binary-to-onehot address decoder for ram
assign addr_decode[31:0] = 32'h00000001 << addr[4:0];
//generate a 32-entry ram with
//addressable inputs entries
//and outputs which are always present;
//essentially this is a 32x1 register file
genvar i;
generate
for(i=0;i<32;i=i+1)begin: bitram
always@(posedge clk)begin
if(addr_decode[i] && we)begin
d_out[i] <= d_in;
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 19:48:37 09/12/2015
// Design Name: SN74LS177Abehavior
// Module Name: C:/Users/adam/Documents/GitHub/Lab1SN74LS177A/SN74LS177AAbsoluteTime.v
// Project Name: Lab1SN74LS177A
////////////////////////////////////////////////////////////////////////////////
module SN74LS195AAbsoluteTime;
reg [3:0] P;
reg PE, J, K, CP, MR;
wire Q3not_gate, Q3not_behavior;
wire [3:0] Qbehavior, Qgates;
SN74LS195Agates GatesChip (Qgates, P, Q3not_gate, PE, J, K, CP, MR);
SN74LS195Abehavior BehaviorChip (Qbehavior, P, Q3not_behavior, PE, J, K, CP, MR);
always #5 CP = ~CP;
initial fork
MR = 1; P = 4'b1010; PE=0; J = 0; K = 0; CP = 0;
#5 MR = 0; #5 P = 4'b1010; #5 PE=0; #5 J = 0; #5 K = 0;
#23 MR = 1; #23 P = 4'b1010; #23 PE=0; #23 J = 1; #23 K = 1;
#41 MR = 1; #41 P = 4'b1010; #41 PE=1; #41 J = 1; #41 K = 1;
#59 MR = 1; #59 P = 4'b1010; #59 PE=1; #59 J = 0; #59 K = 0;
#77 MR = 1; #77 P = 4'b1010; #77 PE=1; #77 J = 1; #77 K = 0;
#103 MR = 1; #103 P = 4'b1010; #103 PE=1; #103 J = 0; #103 K = 1;
#153 $stop;
join
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
// verilator lint_off LITENDIAN
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */;
// verilator lint_on LITENDIAN
reg [31:0] count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
integer status;
sub sub();
// Test loop
initial begin
count = 0;
onebit = 1'b0;
fourthreetwoone[3] = 0; // stop icarus optimizing away
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef IVERILOG
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("%%Info: Checking results\n");
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1; i<=6; i=i+1) begin : arr
arr #(.LENGTH(i)) arr();
end endgenerate
endmodule : t
module sub;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
`ifdef IVERILOG
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2;
`endif
endmodule : sub
module arr;
parameter LENGTH = 1;
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
reg check /*verilator public_flat_rw*/;
reg verbose /*verilator public_flat_rw*/;
initial begin
sig = {LENGTH{1'b0}};
rfr = {LENGTH{1'b0}};
end
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <[email protected]>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
/* verilator lint_off UNUSED */
module qm_icache(
input wire [31:0] address,
input wire reset,
input wire clk,
// to the consumer (CPU fetch stage)
output reg hit,
output reg stall,
output reg [31:0] data,
input wire enable,
// to the memory controller (no wishbone yet...)
// the cache is currently only backed in 1GBit RAM via this controller
// this RAM is mapped 0x80000000 - 0x90000000
output wire mem_cmd_clk, // we will keep this synchronous to the input clock
output reg mem_cmd_en,
output reg [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_addr,
input wire mem_cmd_full,
input wire mem_cmd_empty,
output wire mem_rd_clk,
output reg mem_rd_en,
input wire [6:0] mem_rd_count,
input wire mem_rd_full,
input wire [31:0] mem_rd_data,
input wire mem_rd_empty
);
// 4k cache lines -> 16kword cache
reg [144:0] lines [4095:0];
/// internal signals
// the bit used to mark valid lines (flips when we flush the cache)
reg valid_bit;
wire [11:0] index;
wire index_valid;
wire [15:0] index_tag;
wire [15:0] address_tag;
wire [1:0] address_word;
assign index = address[15:4];
assign index_valid = lines[index][144];
assign index_tag = lines[index][143:128];
assign address_tag = address[31:16];
assign address_word = address[3:2];
assign mem_rd_clk = clk;
assign mem_cmd_clk = clk;
// reset condition
generate
genvar i;
for (i = 0; i < 4096; i = i + 1) begin: ruchanie
always @(posedge clk) begin
if (reset) begin
lines[0] <= {145'b0};
end
end
end
endgenerate
always @(posedge clk) begin
if (reset) begin
valid_bit <= 1;
memory_read_state <= 0;
mem_cmd_en <= 0;
mem_cmd_bl <= 0;
mem_cmd_instr <= 0;
mem_cmd_addr <= 0;
mem_rd_en <= 0;
end
end
// read condition
always @(*) begin
if (enable) begin
// is this in the RAM region?
if (32'h80000000 <= address && address < 32'h90000000) begin
// do we have a hit?
if (index_valid == valid_bit && index_tag == address_tag) begin
if (address_word == 2'b00)
data = lines[index][31:0];
else if (address_word == 2'b01)
data = lines[index][63:32];
else if (address_word == 2'b10)
data = lines[index][95:64];
else
data = lines[index][127:96];
hit = 1;
stall = 0;
end else begin
hit = 0;
stall = 1;
end
end else begin
hit = 1;
stall = 0;
data = 32'h00000000;
end
end else begin
hit = 0;
stall = 0;
end
end
// if we are stalling, it means that our consumer is waiting for us to
// read memory and provide it data
reg [2:0] memory_read_state;
always @(posedge clk) begin
if (stall && !reset && enable) begin
case (memory_read_state)
0: begin // assert command
mem_cmd_instr <= 1; // read
mem_cmd_bl <= 3; // four words
mem_cmd_addr <= {1'b0, address[28:0]};
mem_cmd_en <= 0;
memory_read_state <= 1;
end
1: begin // assert enable
mem_cmd_en <= 1;
memory_read_state <= 2;
mem_rd_en <= 1;
end
2: begin // wait for first word
mem_cmd_en <= 0;
if (!mem_rd_empty) begin
lines[index][31:0] <= mem_rd_data;
memory_read_state <= 3;
end
end
3: begin // wait for second word
if (!mem_rd_empty) begin
lines[index][63:32] <= mem_rd_data;
memory_read_state <= 4;
end
end
4: begin // wait for third word
if (!mem_rd_empty) begin
lines[index][95:64] <= mem_rd_data;
memory_read_state <= 5;
end
end
5: begin // wait for fourth word
if (!mem_rd_empty) begin
lines[index][127:96] <= mem_rd_data;
memory_read_state <= 0;
mem_rd_en <= 0;
// write tag
lines[index][143:128] <= address_tag;
// and valid bit - our cominatorial logic will now turn
// off stalling and indicate a hit to the consumer
lines[index][144] <= valid_bit;
end
end
endcase
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Low-latency RAM-based FIFO. Uses a low-latency register-based FIFO to
// mask the latency of the RAM-based FIFO.
//
// This FIFO uses additional area beyond the FIFO capacity and
// counters in order to compensate for the latency in a normal RAM FIFO.
//
//===----------------------------------------------------------------------===//
module acl_ll_ram_fifo
#(
parameter integer DATA_WIDTH = 32, // >0
parameter integer DEPTH = 32 // >3
)
(
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_out,
output logic empty,
output logic full
);
localparam SEL_RAM = 0;
localparam SEL_LL = 1;
// Three FIFOs:
// 1. data - RAM FIFO (normal latency)
// 2. data - LL REG FIFO
// 3. selector - LL REG FIFO
//
// Selector determines which of the two data FIFOs to select the current
// output from.
//
// TODO Implementation note:
// It's probably possible to use a more compact storage mechanism than
// a FIFO for the selector because the sequence of selector values
// should be highly compressible (e.g. long sequences of SEL_RAM). The
// selector FIFO can probably be replaced with a small number of counters.
// A future enhancement.
logic [DATA_WIDTH-1:0] ram_data_in, ram_data_out;
logic ram_valid_in, ram_valid_out, ram_stall_in, ram_stall_out;
logic [DATA_WIDTH-1:0] ll_data_in, ll_data_out;
logic ll_valid_in, ll_valid_out, ll_stall_in, ll_stall_out;
logic sel_data_in, sel_data_out;
logic sel_valid_in, sel_valid_out, sel_stall_in, sel_stall_out;
// Top-level outputs.
assign data_out = sel_data_out == SEL_LL ? ll_data_out : ram_data_out;
assign valid_out = sel_valid_out; // the required ll_valid_out/ram_valid_out must also be asserted
assign stall_out = sel_stall_out;
// RAM FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH - 3),
.IMPL("ram")
)
ram_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ram_data_in),
.data_out(ram_data_out),
.valid_in(ram_valid_in),
.valid_out(ram_valid_out),
.stall_in(ram_stall_in),
.stall_out(ram_stall_out)
);
assign ram_data_in = data_in;
assign ram_valid_in = valid_in & ll_stall_out; // only write to RAM FIFO if LL FIFO is stalled
assign ram_stall_in = (sel_data_out != SEL_RAM) | stall_in;
// Low-latency FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(3),
.IMPL("ll_reg")
)
ll_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ll_data_in),
.data_out(ll_data_out),
.valid_in(ll_valid_in),
.valid_out(ll_valid_out),
.stall_in(ll_stall_in),
.stall_out(ll_stall_out)
);
assign ll_data_in = data_in;
assign ll_valid_in = valid_in & ~ll_stall_out; // write to LL FIFO if it is not stalled
assign ll_stall_in = (sel_data_out != SEL_LL) | stall_in;
// Selector FIFO.
acl_data_fifo #(
.DATA_WIDTH(1),
.DEPTH(DEPTH),
.IMPL("ll_reg")
)
sel_fifo (
.clock(clock),
.resetn(resetn),
.data_in(sel_data_in),
.data_out(sel_data_out),
.valid_in(sel_valid_in),
.valid_out(sel_valid_out),
.stall_in(sel_stall_in),
.stall_out(sel_stall_out),
.empty(empty),
.full(full)
);
assign sel_data_in = ll_valid_in ? SEL_LL : SEL_RAM;
assign sel_valid_in = valid_in;
assign sel_stall_in = stall_in;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module mig_7series_v4_0_ddr_phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter USE_PRE_POST_FIFO = "FALSE",
parameter RCLK_SELECT_LANE = "B",
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
parameter PI_SEL_CLK_OFFSET = 0,
// phy_control paramter used in other paramsters
parameter PC_CLK_RATIO = 4,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
,parameter CKE_ODT_AUX = "FALSE"
,parameter PI_DIV2_INCDEC = "FALSE"
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input clk_div2,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input phyGo,
input input_sink,
output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output byte_rd_en,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
input [1:0] byte_rd_en_oth_banks,
output [AUXOUT_WIDTH-1:0] aux_out,
output reg rst_out = 0,
output reg mcGo=0,
output phy_ctl_ready,
output ref_dll_lock,
input if_rst,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input [HIGHEST_LANE-1:0] calib_zero_lanes,
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_pi_rst_dqs_find;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg A_idelay_ld;
reg [29:0] A_fine_delay;
reg A_fine_delay_sel;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_pi_rst_dqs_find;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg B_idelay_ld;
reg [29:0] B_fine_delay;
reg B_fine_delay_sel;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
reg C_idelay_ld;
reg D_idelay_ld;
reg C_pi_rst_dqs_find;
reg D_pi_rst_dqs_find;
reg [29:0] C_fine_delay;
reg [29:0] D_fine_delay;
reg C_fine_delay_sel;
reg D_fine_delay_sel;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_byte_rd_en;
wire B_byte_rd_en;
wire C_byte_rd_en;
wire D_byte_rd_en;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
//wire A_if_full;
//wire B_if_full;
//wire C_if_full;
//wire D_if_full;
//wire A_of_empty;
//wire B_of_empty;
//wire C_of_empty;
//wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_pre_fifo_a_full;
wire B_pre_fifo_a_full;
wire C_pre_fifo_a_full;
wire D_pre_fifo_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire A_pre_data_a_full;
wire B_pre_data_a_full;
wire C_pre_data_a_full;
wire D_pre_data_a_full;
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
wire [3:0] dummy_data;
wire [31:0] _phy_ctl_wd;
wire [1:0] phy_encalib;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
// which is combined into another signals such that
// the other signal isn't changed. The purpose
// is to fake the tools into ignoring dangling inputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives=0;
reg A_rst_primitives=0;
reg B_rst_primitives=0;
reg C_rst_primitives=0;
reg D_rst_primitives=0;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
genvar i;
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
endgenerate
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
assign pi_phase_locked_lanes =
{(! PRESENT_DATA_D[0] | D_pi_phase_locked),
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
(! PRESENT_DATA_A[0] | A_pi_phase_locked)};
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
// this block scrubs X from rclk_delay[11]
reg rclk_delay_11;
always @(rclk_delay[11]) begin : rclk_delay_11_blk
if ( rclk_delay[11])
rclk_delay_11 = 1;
else
rclk_delay_11 = 0;
end
always @(posedge phy_clk or posedge rst ) begin
// scrub 4-state values from rclk_delay[11]
if ( rst) begin
rst_out <= #1 0;
end
else begin
if ( rclk_delay_11)
rst_out <= #1 1;
end
end
always @(posedge phy_clk ) begin
// phy_ctl_ready drives reset of the system
rst_primitives <= !phy_ctl_ready ;
A_rst_primitives <= rst_primitives ;
B_rst_primitives <= rst_primitives ;
C_rst_primitives <= rst_primitives ;
D_rst_primitives <= rst_primitives ;
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
mcGo <= #1 rst_out ;
end
//reset synchronized to clk_div2
(* ASYNC_REG = "TRUE" *) reg A_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg B_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg C_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg D_pi_rst_div2;
generate
if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2
(* ASYNC_REG = "TRUE" *) reg pi_rst_div2r1;
(* ASYNC_REG = "TRUE" *) reg pi_rst_div2r2;
always @(posedge clk_div2) begin
pi_rst_div2r1 <= rst_primitives;
pi_rst_div2r2 <= pi_rst_div2r1;
A_pi_rst_div2 <= pi_rst_div2r2;
B_pi_rst_div2 <= pi_rst_div2r2;
C_pi_rst_div2 <= pi_rst_div2r2;
D_pi_rst_div2 <= pi_rst_div2r2;
end
end else begin: phaser_in_div4
always @ (*) begin
A_pi_rst_div2 <= 1'b0;
B_pi_rst_div2 <= 1'b0;
C_pi_rst_div2 <= 1'b0;
D_pi_rst_div2 <= 1'b0;
end
end
endgenerate
generate
if (BYTE_LANES[0]) begin
assign dummy_data[0] = 0;
end
else begin
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
end
if (BYTE_LANES[1]) begin
assign dummy_data[1] = 0;
end
else begin
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
end
if (BYTE_LANES[2]) begin
assign dummy_data[2] = 0;
end
else begin
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
end
if (BYTE_LANES[3]) begin
assign dummy_data[3] = 0;
end
else begin
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
end
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
assign A_pre_data_a_full = A_pre_fifo_a_full;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
assign A_pre_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
assign B_pre_data_a_full = B_pre_fifo_a_full;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
assign B_pre_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
assign C_pre_data_a_full = C_pre_fifo_a_full;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
assign C_pre_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
assign D_pre_data_a_full = D_pre_fifo_a_full;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
assign D_pre_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd = phy_ctl_wd;
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v4_0_ddr_byte_lane #
(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (A_rst_primitives),
.rst_pi_div2 (A_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*A_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*A_of_empty*/),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.pre_fifo_a_full (A_pre_fifo_a_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (A_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (A_idelay_ld),
.pi_rst_dqs_find (A_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked),
.fine_delay (A_fine_delay),
.fine_delay_sel (A_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_pre_fifo_a_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_byte_rd_en = 1'b1;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v4_0_ddr_byte_lane #
(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (B_rst_primitives),
.rst_pi_div2 (B_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*B_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*B_of_empty*/),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.pre_fifo_a_full (B_pre_fifo_a_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (B_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (B_idelay_ld),
.pi_rst_dqs_find (B_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked),
.fine_delay (B_fine_delay),
.fine_delay_sel (B_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_pre_fifo_a_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_byte_rd_en = 1'b1;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v4_0_ddr_byte_lane #
(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (C_rst_primitives),
.rst_pi_div2 (C_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*C_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*C_of_empty*/),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.pre_fifo_a_full (C_pre_fifo_a_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (C_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (C_idelay_ld),
.pi_rst_dqs_find (C_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked),
.fine_delay (C_fine_delay),
.fine_delay_sel (C_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_pre_fifo_a_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_byte_rd_en = 1'b1;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v4_0_ddr_byte_lane #
(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (D_rst_primitives),
.rst_pi_div2 (D_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*D_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*D_of_empty*/),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.pre_fifo_a_full (D_pre_fifo_a_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (D_idelay_ld),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (D_byte_rd_en),
// calibration signals
.pi_rst_dqs_find (D_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked),
.fine_delay (D_fine_delay),
.fine_delay_sel (D_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_pre_fifo_a_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_byte_rd_en = 1'b1;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk ) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
wire B_mux_ctrl;
wire C_mux_ctrl;
wire D_mux_ctrl;
generate
if (HIGHEST_LANE > 1)
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
else
assign B_mux_ctrl = 0;
if (HIGHEST_LANE > 2)
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
else
assign C_mux_ctrl = 0;
if (HIGHEST_LANE > 3)
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
else
assign D_mux_ctrl = 0;
endgenerate
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
if ( B_mux_ctrl) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
if ( C_mux_ctrl) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
if ( D_mux_ctrl) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST ( ! pll_lock)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's mem2reg alignment ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Two versions of Memory to register data alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] memdata;
output [width-1:0] regdata;
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO 4'b0000
reg [7:0] regdata_hh;
reg [7:0] regdata_hl;
reg [7:0] regdata_lh;
reg [7:0] regdata_ll;
reg [width-1:0] aligned;
reg [3:0] sel_byte0, sel_byte1,
sel_byte2, sel_byte3;
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
//
// Byte select 0
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b01x, 2'b00}: // lbz/lbs 0
sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
{3'b01x, 2'b01}, // lbz/lbs 1
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
{3'b01x, 2'b10}: // lbz/lbs 2
sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
default: // all other cases
sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
endcase
end
//
// Byte select 1
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}: // lbz
sel_byte1 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}: // lbs 0
sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}: // lbs 2
sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
default: // all other cases
sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
endcase
end
//
// Byte select 2
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte2 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
endcase
end
//
// Byte select 3
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte3 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
endcase
end
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte0) // synopsys parallel_case infer_mux
`else
case(sel_byte0) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte0) // synopsys parallel_case
`else
case(sel_byte0) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_BYTE0: begin
regdata_ll = memdata[7:0];
end
`OR1200_M2R_BYTE1: begin
regdata_ll = memdata[15:8];
end
`OR1200_M2R_BYTE2: begin
regdata_ll = memdata[23:16];
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_BYTE3: begin
`endif
regdata_ll = memdata[31:24];
end
endcase
end
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte1) // synopsys parallel_case infer_mux
`else
case(sel_byte1) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte1) // synopsys parallel_case
`else
case(sel_byte1) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_lh = 8'h00;
end
`OR1200_M2R_BYTE1: begin
regdata_lh = memdata[15:8];
end
`OR1200_M2R_BYTE3: begin
regdata_lh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_lh = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_lh = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_lh = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_lh = {8{memdata[31]}};
end
endcase
end
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte2) // synopsys parallel_case infer_mux
`else
case(sel_byte2) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte2) // synopsys parallel_case
`else
case(sel_byte2) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_hl = 8'h00;
end
`OR1200_M2R_BYTE2: begin
regdata_hl = memdata[23:16];
end
`OR1200_M2R_EXTB0: begin
regdata_hl = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_hl = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_hl = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_hl = {8{memdata[31]}};
end
endcase
end
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte3) // synopsys parallel_case infer_mux
`else
case(sel_byte3) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte3) // synopsys parallel_case
`else
case(sel_byte3) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_hh = 8'h00;
end
`OR1200_M2R_BYTE3: begin
regdata_hh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_hh = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_hh = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_hh = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
`OR1200_M2R_EXTB3: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_hh = {8{memdata[31]}};
end
endcase
end
`else
//
// Straightforward implementation of mem2reg
//
reg [width-1:0] regdata;
reg [width-1:0] aligned;
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(addr) // synopsys parallel_case infer_mux
`else
case(addr) // synopsys parallel_case
`endif
2'b00:
aligned = memdata;
2'b01:
aligned = {memdata[23:0], 8'b0};
2'b10:
aligned = {memdata[15:0], 16'b0};
2'b11:
aligned = {memdata[7:0], 24'b0};
endcase
end
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(lsu_op) // synopsys parallel_case infer_mux
`else
case(lsu_op) // synopsys parallel_case
`endif
`OR1200_LSUOP_LBZ: begin
regdata[7:0] = aligned[31:24];
regdata[31:8] = 24'b0;
end
`OR1200_LSUOP_LBS: begin
regdata[7:0] = aligned[31:24];
regdata[31:8] = {24{aligned[31]}};
end
`OR1200_LSUOP_LHZ: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = 16'b0;
end
`OR1200_LSUOP_LHS: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = {16{aligned[31]}};
end
default:
regdata = aligned;
endcase
end
`endif
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for pipelined memory access.
//
// Properties - Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time.
// Pipelined read unit:
// Accept read requests on the upstream interface. When a request is
// received, store the requested byte address in the request fifo and
// pass the request through to the avalon interface. Response data
// is buffered in the response fifo and the appropriate word is muxed
// out of the response fifo based on the address in the request fifo.
// The response fifo has limited capacity, so a counter is used to track
// the number of pending responses to generate an upstream stall if
// we run out of room.
module lsu_pipelined_read
(
clk, reset, o_stall, i_valid, i_address, i_burstcount, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid,
o_input_fifo_depth,
avm_burstcount
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads
parameter USEBURST=0;
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USEINPUTFIFO=1;
parameter USEOUTPUTFIFO=1;
parameter INPUTFIFOSIZE=32;
parameter PIPELINE_INPUT=0;
parameter SUPERPIPELINE=0; // Enable extremely aggressive pipelining of the LSU
parameter HIGH_FMAX=1;
localparam INPUTFIFO_USEDW_MAXBITS=$clog2(INPUTFIFOSIZE);
// Derived parameters
localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
//
// We only o_stall if we have more than KERNEL_SIDE_MEM_LATENCY inflight requests
//
localparam RETURN_FIFO_SIZE=KERNEL_SIDE_MEM_LATENCY+(USEBURST ? 0 : 1);
localparam COUNTER_WIDTH=USEBURST ? $clog2(RETURN_FIFO_SIZE+1+MAX_BURST) : $clog2(RETURN_FIFO_SIZE+1);
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [BURSTCOUNT_WIDTH-1:0] i_burstcount;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// For profiler/performance monitor
output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;
/***************
* Architecture *
***************/
wire i_valid_from_fifo;
wire [AWIDTH-1:0] i_address_from_fifo;
wire o_stall_to_fifo;
wire [BURSTCOUNT_WIDTH-1:0] i_burstcount_from_fifo;
wire read_accepted;
wire read_used;
wire [BYTE_SELECT_BITS-1:0] byte_select;
wire ready;
wire out_fifo_wait;
localparam FIFO_DEPTH_BITS=USEINPUTFIFO ? $clog2(INPUTFIFOSIZE) : 0;
wire [FIFO_DEPTH_BITS-1:0] usedw_true_width;
generate
if (USEINPUTFIFO)
assign o_input_fifo_depth[FIFO_DEPTH_BITS-1:0] = usedw_true_width;
// Set unused bits to 0
genvar bit_index;
for(bit_index = FIFO_DEPTH_BITS; bit_index < INPUTFIFO_USEDW_MAXBITS; bit_index = bit_index + 1)
begin: read_fifo_depth_zero_assign
assign o_input_fifo_depth[bit_index] = 1'b0;
end
endgenerate
generate
if(USEINPUTFIFO && SUPERPIPELINE)
begin
wire int_stall;
wire int_valid;
wire [AWIDTH+BURSTCOUNT_WIDTH-1:0] int_data;
acl_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) input_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_burstcount} ),
.data_out( int_data ),
.valid_in( i_valid ),
.valid_out( int_valid ),
.stall_in( int_stall ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
// Add a pipeline and stall-breaking FIFO
// TODO: Consider making this parameterizeable
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_fifo_buffer (
.clock(clk),
.resetn(!reset),
.data_in( int_data ),
.valid_in( int_valid ),
.data_out( {i_address_from_fifo,i_burstcount_from_fifo} ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( int_stall )
);
end
else if(USEINPUTFIFO && !SUPERPIPELINE)
begin
acl_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) input_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_burstcount} ),
.data_out( {i_address_from_fifo,i_burstcount_from_fifo} ),
.valid_in( i_valid ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
end
else if(PIPELINE_INPUT)
begin
reg r_valid;
reg [AWIDTH-1:0] r_address;
reg [BURSTCOUNT_WIDTH-1:0] r_burstcount;
assign o_stall = r_valid && o_stall_to_fifo;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
r_valid <= 1'b0;
else
begin
if (!o_stall)
begin
r_valid <= i_valid;
r_address <= i_address;
r_burstcount <= i_burstcount;
end
end
end
assign i_valid_from_fifo = r_valid;
assign i_address_from_fifo = r_address;
assign i_burstcount_from_fifo = r_burstcount;
end
else
begin
assign i_valid_from_fifo = i_valid;
assign i_address_from_fifo = i_address;
assign o_stall = o_stall_to_fifo;
assign i_burstcount_from_fifo = i_burstcount;
end
endgenerate
// Track the number of transactions waiting in the pipeline here
reg [COUNTER_WIDTH-1:0] counter;
wire incr, decr;
assign incr = read_accepted;
assign decr = read_used;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
counter <= {COUNTER_WIDTH{1'b0}};
o_active <= 1'b0;
end
else
begin
o_active <= (counter != {COUNTER_WIDTH{1'b0}});
// incr - add one or i_burstcount_from_fifo; decr - subtr one;
if (USEBURST==1)
counter <= counter + (incr ? i_burstcount_from_fifo : 0) - decr;
else
counter <= counter + incr - decr;
end
end
generate
if(USEBURST)
// Use the burstcount to figure out if there is enough space
assign ready = ((counter+i_burstcount_from_fifo) <= RETURN_FIFO_SIZE);
//
// Can also use decr in this calaculation to make ready respond faster
// but this seems to hurt Fmax ( ie. not worth it )
//assign ready = ((counter+i_burstcount_from_fifo-decr) <= RETURN_FIFO_SIZE);
else
// Can we hold one more item
assign ready = (counter <= (RETURN_FIFO_SIZE-1));
endgenerate
assign o_stall_to_fifo = !ready || out_fifo_wait;
// Optional Pipeline register before return
//
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata;
generate
if(SUPERPIPELINE)
begin
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_avm_readdata <= 'x;
r_avm_readdatavalid <= 1'b0;
end
else
begin
r_avm_readdata <= avm_readdata;
r_avm_readdatavalid <= avm_readdatavalid;
end
end
end
else
begin
// Don't register the return
always@(*)
begin
r_avm_readdata = avm_readdata;
r_avm_readdatavalid = avm_readdatavalid;
end
end
endgenerate
wire [WIDTH-1:0] rdata;
// Byte-addresses enter a FIFO so we can demux the appropriate data back out.
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_address_out;
wire [SEGMENT_SELECT_BITS-1:0] segment_address_in;
assign segment_address_in = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
acl_ll_fifo #(
.WIDTH(SEGMENT_SELECT_BITS),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) req_fifo (
.clk(clk),
.reset(reset),
.data_in( segment_address_in ),
.data_out( segment_address_out ),
.write( read_accepted ),
.read( r_avm_readdatavalid ),
.empty(),
.full()
);
assign byte_select = (segment_address_out << ALIGNMENT_ABITS);
assign rdata = r_avm_readdata[8*byte_select +: WIDTH];
end
else
begin
assign byte_select = '0;
assign rdata = r_avm_readdata;
end
endgenerate
// Status bits
assign read_accepted = i_valid_from_fifo && ready && !out_fifo_wait;
assign read_used = o_valid && !i_stall;
assign avm_byteenable = {MWIDTH_BYTES{1'b1}};
// Optional: Pipelining FIFO on the AVM interface
//
generate
if(SUPERPIPELINE)
begin
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) avm_buffer (
.clock(clk),
.resetn(!reset),
.data_in({((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS),i_burstcount_from_fifo}),
.valid_in( i_valid_from_fifo && ready ),
.data_out( {avm_address,avm_burstcount} ),
.valid_out( avm_read ),
.stall_in( avm_waitrequest ),
.stall_out( out_fifo_wait )
);
end
else
begin
// No interface pipelining
assign out_fifo_wait = avm_waitrequest;
assign avm_address = ((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_read = i_valid_from_fifo && ready;
assign avm_burstcount = i_burstcount_from_fifo;
end
endgenerate
// ---------------------------------------------------------------------------------
// Output fifo - must be at least as deep as the maximum number of pending requests
// so that we can guarantee a place for the response data if the downstream blocks
// are stalling.
//
generate
if(USEOUTPUTFIFO)
begin
acl_data_fifo #(
.DATA_WIDTH(WIDTH),
.DEPTH(RETURN_FIFO_SIZE),
.IMPL((SUPERPIPELINE && HIGH_FMAX) ? "ram_plus_reg" : "ram")
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( rdata ),
.data_out( o_readdata ),
.valid_in( r_avm_readdatavalid ),
.valid_out( o_valid ),
.stall_in( i_stall ),
.stall_out()
);
end
else
begin
assign o_valid = r_avm_readdatavalid;
assign o_readdata = rdata;
end
endgenerate
endmodule
/******************************************************************************/
// Pipelined write unit:
// Accept write requests on the upstream interface. Mux the data into the
// appropriate word lines based on the segment select bits. Also toggle
// the appropriate byte-enable lines to preserve data we are not
// overwriting. A counter keeps track of how many requests have been
// send but not yet acknowledged by downstream blocks.
module lsu_pipelined_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest, o_input_fifo_depth
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access
parameter MWIDTH_BYTES=32; // Width of the global memory bus
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter COUNTER_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=32;
parameter USEINPUTFIFO=1;
parameter USE_BYTE_EN=0;
parameter INPUTFIFOSIZE=32;
parameter INPUTFIFO_USEDW_MAXBITS=$clog2(INPUTFIFOSIZE);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input [WIDTH_BYTES-1:0] i_byteenable;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output reg [MWIDTH-1:0] avm_writedata;
output reg [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
// For profiler/performance monitor
output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;
/***************
* Architecture *
***************/
reg transaction_complete;
wire write_accepted;
wire ready;
wire sr_stall;
wire i_valid_from_fifo;
wire [AWIDTH-1:0] i_address_from_fifo;
wire [WIDTH-1:0] i_writedata_from_fifo;
wire [WIDTH_BYTES-1:0] i_byteenable_from_fifo;
wire o_stall_to_fifo;
localparam FIFO_DEPTH_BITS=USEINPUTFIFO ? $clog2(INPUTFIFOSIZE) : 0;
wire [FIFO_DEPTH_BITS-1:0] usedw_true_width;
generate
if (USEINPUTFIFO)
assign o_input_fifo_depth[FIFO_DEPTH_BITS-1:0] = usedw_true_width;
// Set unused bits to 0
genvar bit_index;
for(bit_index = FIFO_DEPTH_BITS; bit_index < INPUTFIFO_USEDW_MAXBITS; bit_index = bit_index + 1)
begin: write_fifo_depth_zero_assign
assign o_input_fifo_depth[bit_index] = 1'b0;
end
endgenerate
localparam DATA_WIDTH = AWIDTH+WIDTH+(USE_BYTE_EN ? WIDTH_BYTES : 0);
generate
if(USEINPUTFIFO)
begin
wire valid_int;
wire stall_int;
wire [DATA_WIDTH-1:0] data_int;
if(!USE_BYTE_EN)
begin
acl_fifo #(
.DATA_WIDTH(AWIDTH+WIDTH),
.DEPTH(INPUTFIFOSIZE)
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_writedata} ),
.data_out( data_int ),
.valid_in( i_valid ),
.valid_out( valid_int ),
.stall_in( stall_int ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_buf (
.clock(clk),
.resetn(!reset),
.data_in( data_int ),
.data_out( {i_address_from_fifo,i_writedata_from_fifo} ),
.valid_in( valid_int ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( stall_int )
);
assign i_byteenable_from_fifo = {WIDTH_BYTES{1'b1}};
end else begin
acl_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_byteenable, i_address,i_writedata}),
.data_out( data_int ),
.valid_in( i_valid ),
.valid_out( valid_int ),
.stall_in( stall_int ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_buf (
.clock(clk),
.resetn(!reset),
.data_in( data_int ),
.data_out({i_byteenable_from_fifo,i_address_from_fifo,i_writedata_from_fifo}),
.valid_in( valid_int ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( stall_int )
);
end
end
else
begin
assign i_valid_from_fifo = i_valid;
assign i_address_from_fifo = i_address;
assign i_writedata_from_fifo = i_writedata;
assign o_stall = o_stall_to_fifo;
assign i_byteenable_from_fifo = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
end
endgenerate
// Avalon interface
assign avm_address = ((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_write = ready && i_valid_from_fifo;
// Mux in the correct data
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
always@(*)
begin
avm_writedata = {MWIDTH{1'bx}};
avm_writedata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata_from_fifo;
avm_byteenable = {MWIDTH_BYTES{1'b0}};
avm_byteenable[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = i_byteenable_from_fifo;
end
end
else
begin
always@(*)
begin
avm_writedata = i_writedata_from_fifo;
avm_byteenable = i_byteenable_from_fifo;
end
end
endgenerate
// Control logic
reg [COUNTER_WIDTH-1:0] occ_counter; // occupancy counter
wire occ_incr, occ_decr;
reg [COUNTER_WIDTH-1:0] ack_counter; // acknowledge writes counter
wire ack_incr, ack_decr;
// Track the number of transactions waiting in the pipeline here
assign occ_incr = write_accepted;
assign occ_decr = o_valid && !i_stall;
assign ack_incr = avm_writeack;
assign ack_decr = o_valid && !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
o_active <= 1'b0;
end
else
begin
// incr - add one; decr - subtr one; both - stay the same
occ_counter <= occ_counter + { {(COUNTER_WIDTH-1){!occ_incr && occ_decr}}, (occ_incr ^ occ_decr) };
ack_counter <= ack_counter + { {(COUNTER_WIDTH-1){!ack_incr && ack_decr}}, (ack_incr ^ ack_decr) };
o_active <= (occ_counter != {COUNTER_WIDTH{1'b0}});
end
end
assign ready = (occ_counter != {COUNTER_WIDTH{1'b1}});
assign write_accepted = avm_write && !avm_waitrequest;
assign o_stall_to_fifo = !ready || avm_waitrequest;
assign o_valid = (ack_counter != {COUNTER_WIDTH{1'b0}});
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_SYMBOL_V
`define SKY130_FD_SC_LP__BUFINV_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_SYMBOL_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eicAhb;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
/*
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present
);
*/
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); //enable eic
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01); //any logical change for irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05); //enable irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); //clear irq 33 (pin 32)
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01); //set EIFR word0
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04); //set EIFR bit3
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
wire CLK2;
wire dspx_dp_enable;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [11:0] SA1_PGM_ADDR;
wire [7:0] SA1_PGM_DATA;
wire [7:0] SA1_SNES_DATA_IN;
wire [7:0] SA1_SNES_DATA_OUT;
wire [15:0] SA1_SNV;
wire [15:0] SA1_SIV;
wire [11:0] SA1_XXB;
wire [3:0] SA1_XXB_EN;
wire [15:0] featurebits;
wire feat_cmd_unlock = featurebits[5];
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [15:0] dsp_feat;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
// config
wire [7:0] reg_group;
wire [7:0] reg_index;
wire [7:0] reg_value;
wire [7:0] reg_invmask;
wire reg_we;
wire [7:0] reg_read;
// unit level configuration output
wire [7:0] sa1_config_data;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [7:0] SNES_PULSEr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
reg ram_free_strobe = 0;
wire [23:0] SNES_ADDR = SNES_ADDRr[1] & SNES_ADDRr[0]; //(SNES_ADDRr[6] & SNES_ADDRr[5]);
//wire [23:0] SNES_ADDR_early = SNES_ADDRr[0];
wire [7:0] SNES_PA = SNES_PAr[0]; //(SNES_PAr[6] & SNES_PAr[5]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire SNES_PULSE_IN = SNES_READ_IN & SNES_WRITE_IN & ~SNES_CPU_CLK_IN;
wire SNES_PULSE_end = (SNES_PULSEr[6:1] == 6'b000011);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
wire SNES_PARD_end = (SNES_PARDr[6:1] == 6'b000001);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[6:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 6'b111000 : 6'b100000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_cycle_end_early = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_READ_late = SNES_READr[5] & SNES_READr[4];
wire SNES_READ_narrow = SNES_READ | SNES_READ_late;
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire ROM_HIT;
wire IS_ROM;
assign DCM_RST=0;
wire IS_SAVERAM;
//wire mcu_free_slot = SNES_cycle_end | free_strobe;
// TODO does this free_slot style cause problems with SA1 performance?
wire SD_DMA_TO_ROM;
wire free_slot = (SNES_PULSE_end | free_strobe) & ~SD_DMA_TO_ROM;
// TODO: Provide full bandwidth if snes is not accessing the bus.
reg [7:0] SNES_cycle_end_delay;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= (~ROM_HIT);
end
always @(posedge CLK2) begin
SNES_PULSEr <= {SNES_PULSEr[6:0], SNES_PULSE_IN};
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
SNES_cycle_end_delay <= {SNES_cycle_end_delay[6:1],SNES_cycle_end};
end
parameter ST_IDLE = 11'b00000000001;
parameter ST_MCU_RD_ADDR = 11'b00000000010;
parameter ST_MCU_RD_END = 11'b00000000100;
parameter ST_MCU_WR_ADDR = 11'b00000001000;
parameter ST_MCU_WR_END = 11'b00000010000;
parameter ST_SA1_ROM_RD_ADDR = 11'b00000100000;
parameter ST_SA1_ROM_RD_END = 11'b00001000000;
parameter ST_SA1_RAM_RD_ADDR = 11'b00010000000;
parameter ST_SA1_RAM_RD_END = 11'b00100000000;
parameter ST_SA1_RAM_WR_ADDR = 11'b01000000000;
parameter ST_SA1_RAM_WR_END = 11'b10000000000;
`ifdef MK2
parameter SNES_DEAD_TIMEOUT = 17'd85714; // 1ms
`endif
`ifdef MK3
// Cyclone IV PLL allows us to get a bit closer to original speed
parameter SNES_DEAD_TIMEOUT = 17'd85867; // 1ms
`endif
parameter ROM_CYCLE_LEN = 4'd7; // Increased from 6 due to tight timing on some sd2snes. Two pics from boards with errors had a Micron chip with 0LA41/PW510. Same build lot.
reg [10:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign SA1_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
assign SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
// SA1 address mapping
wire [4:0] SA1_BMAPS_SBM;
// SA1 ROM access
reg [15:0] SA1_ROM_DINr;
wire [23:0] SA1_ROM_ADDR;
wire SA1_ROM_WORD;
wire [15:0] SA1_ROM_DATA;
reg [7:0] SA1_RAM_DINr;
wire [23:0] SA1_RAM_ADDR;
wire [7:0] SA1_RAM_DOUT;
wire SA1_RAM_WORD;
// SA1
sa1 snes_sa1 (
.RST(SNES_reset_strobe),
.CLK(CLK2),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
// MMIO interface
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.SNES_RD_start(SNES_RD_start),
.SNES_RD_end(SNES_RD_end),
.SNES_WR_start(SNES_WR_start),
.SNES_WR_end(SNES_WR_end),
.SNES_cycle_end(SNES_cycle_end),
.SNES_ADDR(SNES_ADDR),
.DATA_IN(SA1_SNES_DATA_IN),
.DATA_ENABLE(sa1_data_enable),
.DATA_OUT(SA1_SNES_DATA_OUT),
// ROM interface
.ROM_BUS_RDY(SA1_ROM_RDY),
.ROM_BUS_RRQ(SA1_ROM_RRQ),
.ROM_BUS_WRQ(SA1_ROM_WRQ),
.ROM_BUS_WORD(SA1_ROM_WORD),
.ROM_BUS_ADDR(SA1_ROM_ADDR),
.ROM_BUS_WRDATA(SA1_ROM_DATA),
.ROM_BUS_RDDATA(SA1_ROM_DINr),
// RAM interface
.RAM_BUS_RDY(SA1_RAM_RDY),
.RAM_BUS_RRQ(SA1_RAM_RRQ),
.RAM_BUS_WRQ(SA1_RAM_WRQ),
.RAM_BUS_WORD(SA1_RAM_WORD),
.RAM_BUS_ADDR(SA1_RAM_ADDR),
.RAM_BUS_RDDATA(SA1_RAM_DINr),
.RAM_BUS_WRDATA(SA1_RAM_DOUT),
.BMAPS_SBM(SA1_BMAPS_SBM),
.SNV(SA1_SNV),
.SIV(SA1_SIV),
.SCNT_NVSW(SA1_SCNT_NVSW),
.SCNT_IVSW(SA1_SCNT_IVSW),
.DMA_CC1_EN(SA1_DMA_CC1_EN),
.XXB_OUT(SA1_XXB),
.XXB_EN_OUT(SA1_XXB_EN),
// ACTIVE interface
//.ACTIVE(SA1_ACTIVE),
.IRQ(SA1_IRQ),
.SPEED(dsp_feat[0]),
// State debug read interface
.PGM_ADDR(SA1_PGM_ADDR), // [11:0]
.PGM_DATA(SA1_PGM_DATA), // [7:0]
// config
.reg_group_in(reg_group),
.reg_index_in(reg_index),
.reg_value_in(reg_value),
.reg_invmask_in(reg_invmask),
.reg_we_in(reg_we),
.reg_read_in(reg_read),
.config_data_out(sa1_config_data),
.DBG(DBG_SA1)
);
reg [7:0] MCU_DINr;
reg [7:0] MCU_ROM_DINr;
reg [7:0] MCU_RAM_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.sa1_addr_out(SA1_PGM_ADDR),
.sa1_data(SA1_PGM_DATA),
// config
.reg_group_out(reg_group),
.reg_index_out(reg_index),
.reg_value_out(reg_value),
.reg_invmask_out(reg_invmask),
.reg_we_out(reg_we),
.reg_read_out(reg_read),
// vv config data in vv
.sa1_config_data_in(sa1_config_data),
// ^^ config data in ^^
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
// sa1
.sa1_bmaps_sbm(SA1_BMAPS_SBM),
.sa1_dma_cc1_en(SA1_DMA_CC1_EN),
.sa1_xxb(SA1_XXB),
.sa1_xxb_en(SA1_XXB_EN),
.r213f_enable(r213f_enable),
.r2100_hit(r2100_hit),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
parameter ST_R213F_ARMED = 4'b0001;
parameter ST_R213F_WAITBUS = 4'b0010;
parameter ST_R213F_OVERRIDE = 4'b0100;
parameter ST_R213F_HOLD = 4'b1000;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
wire [3:0] r2100_limit = featurebits[10:7];
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
wire r2100_patch = featurebits[6];
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
reg nmi_match; initial nmi_match = 0;
reg irq_match; initial irq_match = 0;
always @(posedge CLK2) nmi_match <= {SNES_ADDR[23:1],1'b0} == 24'h00FFEA;
always @(posedge CLK2) irq_match <= {SNES_ADDR[23:1],1'b0} == 24'h00FFEE;
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:((~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE & ~sa1_data_enable))
? ( msu_enable ? MSU_SNES_DATA_OUT
: sa1_data_enable ? SA1_SNES_DATA_OUT // SA1 MMIO read
: (cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
: ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable) ? snescmd_dout
: (ROM_HIT & IS_SAVERAM) ? RAM_DATA
: (SA1_SCNT_NVSW & nmi_match) ? (SNES_ADDR[0] ? SA1_SNV[15:8] : SA1_SNV[7:0])
: (SA1_SCNT_IVSW & irq_match) ? (SNES_ADDR[0] ? SA1_SIV[15:8] : SA1_SIV[7:0])
: (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
// MCU
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
// SA1 ROM
reg SA1_ROM_RD_PENDr; initial SA1_ROM_RD_PENDr = 0;
reg SA1_ROM_WR_PENDr; initial SA1_ROM_WR_PENDr = 0;
reg [23:0] SA1_ROM_ADDRr;
reg [15:0] SA1_ROM_DATAr;
reg SA1_ROM_WORDr;
reg RQ_SA1_ROM_RDYr; initial RQ_SA1_ROM_RDYr = 1;
assign SA1_ROM_RDY = RQ_SA1_ROM_RDYr;
wire SA1_ROM_RD_HIT = |(STATE & ST_SA1_ROM_RD_ADDR);
wire SA1_ROM_HIT = SA1_ROM_RD_HIT;
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : SA1_ROM_HIT ? SA1_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : SA1_ROM_HIT ? SA1_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : SA1_ROM_HIT ? SA1_ROM_ADDRr[1] : MCU_HIT ? ROM_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : SA1_ROM_HIT ? SA1_ROM_ADDRr[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : SA1_ROM_HIT ? SA1_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.address_a(SNES_ADDR[8:0]), // input [8 : 0] addra
.data_a(SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [8 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
reg ROM_ADDR0_r;
always @(posedge CLK2) ROM_ADDR0_r <= ROM_ADDR0;
// MCU r/w request
always @(posedge CLK2) begin
if(MCU_RRQ && MCU_ADDR[23:19] != 5'b11100) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ && MCU_ADDR[23:19] != 5'b11100) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
// SA1 r/w request
always @(posedge CLK2) begin
if(SA1_ROM_RRQ) begin
SA1_ROM_RD_PENDr <= 1'b1;
RQ_SA1_ROM_RDYr <= 1'b0;
SA1_ROM_ADDRr <= SA1_ROM_ADDR;
SA1_ROM_WORDr <= SA1_ROM_WORD;
end else if(SA1_ROM_WRQ) begin
SA1_ROM_WR_PENDr <= 1'b1;
RQ_SA1_ROM_RDYr <= 1'b0;
SA1_ROM_ADDRr <= SA1_ROM_ADDR;
SA1_ROM_WORDr <= SA1_ROM_WORD;
SA1_ROM_DATAr <= SA1_ROM_DATA;
end else if(|(STATE & (ST_SA1_ROM_RD_ADDR)) & ~|ST_MEM_DELAYr) begin
// enable rdy/response 1 cycle earlier
RQ_SA1_ROM_RDYr <= 1'b1;
end else if(STATE & (ST_SA1_ROM_RD_END)) begin
SA1_ROM_RD_PENDr <= 1'b0;
SA1_ROM_WR_PENDr <= 1'b0;
RQ_SA1_ROM_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
// early notify from SA1 to save a clock
if (SA1_ROM_RD_PENDr | SA1_ROM_RRQ) begin
STATE <= ST_SA1_ROM_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_ROM_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_SA1_ROM_RD_ADDR: begin
STATE <= ST_SA1_ROM_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_SA1_ROM_RD_END;
SA1_ROM_DINr <= (ROM_ADDR0_r ? ROM_DATA[15:0] : {ROM_DATA[7:0],ROM_DATA[15:8]});
end
ST_MCU_RD_END, ST_MCU_WR_END, ST_SA1_ROM_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
/***********************
* R213F read patching *
***********************/
always @(posedge CLK2) begin
case(r213f_state)
ST_R213F_HOLD: begin
r213f_state <= ST_R213F_HOLD;
if(SNES_PULSE_end) begin
r213f_forceread <= 1'b1;
r213f_state <= ST_R213F_ARMED;
end
end
ST_R213F_ARMED: begin
r213f_state <= ST_R213F_ARMED;
if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= ST_R213F_WAITBUS;
end
end
ST_R213F_WAITBUS: begin
r213f_state <= ST_R213F_WAITBUS;
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_state <= ST_R213F_OVERRIDE;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
ST_R213F_OVERRIDE: begin
r213f_state <= ST_R213F_HOLD;
r213f_forceread <= 1'b0;
end
endcase
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_PULSE_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
// odd addresses xxx1
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT
& ~IS_SAVERAM
& ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
// even addresses xxx0
assign ROM_DATA[15:8] = ROM_ADDR0
? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT
& ~IS_SAVERAM
& ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE
& ~IS_SAVERAM
& SNES_CPU_CLK) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
// force word enable for SA1
assign ROM_BHE = ROM_ADDR0 && !(!SD_DMA_TO_ROM && SA1_ROM_HIT && SA1_ROM_WORDr);
assign ROM_BLE = !ROM_ADDR0 && !(!SD_DMA_TO_ROM && SA1_ROM_HIT && SA1_ROM_WORDr);
//--------------
// RAM Pipeline
//--------------
parameter ST_RAM_IDLE = 9'b000000001;
parameter ST_RAM_MCU_RD_ADDR = 9'b000000010;
parameter ST_RAM_MCU_RD_END = 9'b000000100;
parameter ST_RAM_MCU_WR_ADDR = 9'b000001000;
parameter ST_RAM_MCU_WR_END = 9'b000010000;
parameter ST_RAM_SA1_RD_ADDR = 9'b000100000;
parameter ST_RAM_SA1_RD_END = 9'b001000000;
parameter ST_RAM_SA1_WR_ADDR = 9'b010000000;
parameter ST_RAM_SA1_WR_END = 9'b100000000;
parameter RAM_CYCLE_LEN = 4'd5;
reg [8:0] RAM_STATE; initial RAM_STATE = ST_RAM_IDLE;
reg [3:0] ST_RAM_DELAYr;
//wire ram_free_slot = SNES_cycle_end | ram_free_strobe;
wire ram_free_slot = SNES_cycle_end | ~IS_SAVERAM;
// Provide full bandwidth if snes is not accessing the bus.
always @(posedge CLK2) begin
if (SNES_cycle_start) ram_free_strobe <= ~ROM_HIT | ~IS_SAVERAM;
else if (SNES_cycle_end) ram_free_strobe <= 1'b0;
end
// MCU state machine
reg MCU_RAM_RD_PENDr = 0;
reg MCU_RAM_WR_PENDr = 0;
reg [18:0] RAM_ADDRr;
reg RQ_RAM_MCU_RDYr;
initial RQ_RAM_MCU_RDYr = 1'b1;
wire MCU_RAM_WE_HIT = |(RAM_STATE & ST_RAM_MCU_WR_ADDR);
wire MCU_RAM_WR_HIT = |(RAM_STATE & (ST_RAM_MCU_WR_ADDR | ST_RAM_MCU_WR_END));
wire MCU_RAM_RD_HIT = |(RAM_STATE & (ST_RAM_MCU_RD_ADDR | ST_RAM_MCU_RD_END));
wire MCU_RAM_HIT = MCU_RAM_WR_HIT | MCU_RAM_RD_HIT;
// MCU RAM1 r/w request
always @(posedge CLK2) begin
if(MCU_RRQ && MCU_ADDR[23:19] == 5'b11100) begin
MCU_RAM_RD_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ && MCU_ADDR[23:19] == 5'b11100) begin
MCU_RAM_WR_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(RAM_STATE & (ST_RAM_MCU_RD_END | ST_RAM_MCU_WR_END)) begin
MCU_RAM_RD_PENDr <= 1'b0;
MCU_RAM_WR_PENDr <= 1'b0;
RQ_RAM_MCU_RDYr <= 1'b1;
end
end
// SA1 RAM
reg SA1_RAM_RD_PENDr; initial SA1_RAM_RD_PENDr = 0;
reg SA1_RAM_WR_PENDr; initial SA1_RAM_WR_PENDr = 0;
// TODO: how much ram does sa1 support? more than 512KB?
reg [18:0] SA1_RAM_ADDRr;
reg [7:0] SA1_RAM_DATAr;
reg SA1_RAM_WORDr;
reg RQ_SA1_RAM_RDYr; initial RQ_SA1_RAM_RDYr = 1;
assign SA1_RAM_RDY = RQ_SA1_RAM_RDYr;
wire SA1_RAM_WE_HIT = |(RAM_STATE & ST_RAM_SA1_WR_ADDR);
wire SA1_RAM_WR_HIT = |(RAM_STATE & (ST_RAM_SA1_WR_ADDR | ST_RAM_SA1_WR_END));
wire SA1_RAM_RD_HIT = |(RAM_STATE & (ST_RAM_SA1_RD_ADDR | ST_RAM_SA1_RD_END));
wire SA1_RAM_HIT = SA1_RAM_WR_HIT | SA1_RAM_RD_HIT;
// SA1 RAM1 r/w request
always @(posedge CLK2) begin
if(SA1_RAM_RRQ) begin
SA1_RAM_RD_PENDr <= 1'b1;
RQ_SA1_RAM_RDYr <= 1'b0;
SA1_RAM_ADDRr <= SA1_RAM_ADDR;
SA1_RAM_WORDr <= SA1_RAM_WORD;
end else if(SA1_RAM_WRQ) begin
SA1_RAM_WR_PENDr <= 1'b1;
RQ_SA1_RAM_RDYr <= 1'b0;
SA1_RAM_ADDRr <= SA1_RAM_ADDR;
SA1_RAM_WORDr <= SA1_RAM_WORD;
SA1_RAM_DATAr <= SA1_RAM_DOUT;
end else if(RAM_STATE & (ST_RAM_SA1_RD_END | ST_RAM_SA1_WR_END)) begin
SA1_RAM_RD_PENDr <= 1'b0;
SA1_RAM_WR_PENDr <= 1'b0;
RQ_SA1_RAM_RDYr <= 1'b1;
end
end
// RAM state machine
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) RAM_STATE <= ST_RAM_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(RAM_STATE)
ST_RAM_IDLE: begin
if(ram_free_slot | SNES_DEADr) begin
// early notify from SA1 to save a clock
if (SA1_RAM_RD_PENDr | SA1_RAM_RRQ) begin
RAM_STATE <= ST_RAM_SA1_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if (SA1_RAM_WR_PENDr | SA1_RAM_WRQ) begin
RAM_STATE <= ST_RAM_SA1_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if(MCU_RAM_RD_PENDr) begin
RAM_STATE <= ST_RAM_MCU_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if(MCU_RAM_WR_PENDr) begin
RAM_STATE <= ST_RAM_MCU_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
end
end
ST_RAM_MCU_RD_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_RD_END;
MCU_RAM_DINr <= RAM_DATA;
end
ST_RAM_MCU_WR_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_WR_END;
end
ST_RAM_SA1_RD_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_SA1_RD_END;
SA1_RAM_DINr <= RAM_DATA;
end
ST_RAM_SA1_WR_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_SA1_WR_END;
end
ST_RAM_MCU_RD_END, ST_RAM_MCU_WR_END, ST_RAM_SA1_RD_END, ST_RAM_SA1_WR_END: begin
RAM_STATE <= ST_RAM_IDLE;
end
endcase
end
assign RAM_ADDR = SA1_RAM_HIT ? SA1_RAM_ADDRr[18:0] : MCU_RAM_HIT ? RAM_ADDRr[18:0] : MAPPED_SNES_ADDR[18:0];
assign RAM_DATA[7:0] = ( SA1_RAM_WR_HIT ? SA1_RAM_DATAr[7:0]
: (ROM_HIT & IS_SAVERAM & ~SNES_WRITE) ? SNES_DATA
: MCU_RAM_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign RAM_WE = ( SA1_RAM_WE_HIT ? 1'b0
: (ROM_HIT & IS_SAVERAM & SNES_CPU_CLK) ? SNES_WRITE
: MCU_RAM_WE_HIT ? 1'b0
: 1'b1
);
assign RAM_OE = 1'b0;
always @(posedge CLK2) begin
// flop data based on source
if (STATE & ST_MCU_RD_END) begin
MCU_DINr <= MCU_ROM_DINr;
end
else if (RAM_STATE & ST_RAM_MCU_RD_END) begin
MCU_DINr <= MCU_RAM_DINr;
end
end
assign MCU_RDY = RQ_MCU_RDYr & RQ_RAM_MCU_RDYr;
//--------------
assign SNES_DATABUS_OE = msu_enable & ~(SNES_READ_narrow & SNES_WRITE) ? 1'b0 :
sa1_data_enable ? 1'b0 : // accounts for read/write
snescmd_enable & ~(SNES_READ_narrow & SNES_WRITE) ? ~(snescmd_unlock | feat_cmd_unlock) :
(r213f_enable & ~SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
snoop_4200_enable & ~SNES_WRITE ? 1'b0 :
( (IS_ROM & SNES_ROMSEL)
| (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
| (SNES_READ_narrow & SNES_WRITE)
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE & ~sa1_data_enable))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = SA1_IRQ;
endmodule
|
module wb_arbiter_tb
#(parameter NUM_MASTERS = 5)
(input wb_clk_i,
input wb_rst_i,
output done);
localparam aw = 32;
localparam dw = 32;
localparam MEMORY_SIZE_BITS = 8;
localparam MEMORY_SIZE_WORDS = 2**MEMORY_SIZE_BITS;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [dw-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [NUM_MASTERS*aw-1:0] wbm_m2s_adr;
wire [NUM_MASTERS*dw-1:0] wbm_m2s_dat;
wire [NUM_MASTERS*4-1:0] wbm_m2s_sel;
wire [NUM_MASTERS-1:0] wbm_m2s_we ;
wire [NUM_MASTERS-1:0] wbm_m2s_cyc;
wire [NUM_MASTERS-1:0] wbm_m2s_stb;
wire [NUM_MASTERS*3-1:0] wbm_m2s_cti;
wire [NUM_MASTERS*2-1:0] wbm_m2s_bte;
wire [NUM_MASTERS*dw-1:0] wbm_s2m_dat;
wire [NUM_MASTERS-1:0] wbm_s2m_ack;
wire [NUM_MASTERS-1:0] wbm_s2m_err;
wire [NUM_MASTERS-1:0] wbm_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wire [NUM_MASTERS-1:0] done_int;
genvar i;
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : masters
wb_bfm_transactor
#(.MEM_HIGH((i+1)*MEMORY_SIZE_WORDS-1),
.MEM_LOW (i*MEMORY_SIZE_WORDS))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr[i*aw+:aw]),
.wb_dat_o (wbm_m2s_dat[i*dw+:dw]),
.wb_sel_o (wbm_m2s_sel[i*4+:4]),
.wb_we_o (wbm_m2s_we[i] ),
.wb_cyc_o (wbm_m2s_cyc[i]),
.wb_stb_o (wbm_m2s_stb[i]),
.wb_cti_o (wbm_m2s_cti[i*3+:3]),
.wb_bte_o (wbm_m2s_bte[i*2+:2]),
.wb_dat_i (wbm_s2m_dat[i*dw+:dw]),
.wb_ack_i (wbm_s2m_ack[i]),
.wb_err_i (wbm_s2m_err[i]),
.wb_rty_i (wbm_s2m_rty[i]),
//Test Control
.done(done_int[i]));
end // block: slaves
endgenerate
integer idx;
assign done = &done_int;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
for(idx=0;idx<NUM_MASTERS;idx=idx+1)
$display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
$display("All tests passed!");
end
end
wb_arbiter
#(.num_masters(NUM_MASTERS))
wb_arbiter0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_cti_i (wbm_m2s_cti),
.wbm_bte_i (wbm_m2s_bte),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
.wbm_err_o (wbm_s2m_err),
.wbm_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
assign slave_writes = wb_mem_model0.writes;
assign slave_reads = wb_mem_model0.reads;
time start_time[NUM_MASTERS-1:0];
time ack_delay[NUM_MASTERS-1:0];
integer num_transactions[NUM_MASTERS-1:0];
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : wait_time
initial begin
ack_delay[i] = 0;
num_transactions[i] = 0;
while(1) begin
@(posedge wbm_m2s_cyc[i]);
start_time[i] = $time;
@(posedge wbm_s2m_ack[i]);
ack_delay[i] = ack_delay[i] + $time-start_time[i];
num_transactions[i] = num_transactions[i]+1;
end
end
end
endgenerate
wb_bfm_memory #(.DEBUG (0),
.mem_size_bytes(MEMORY_SIZE_WORDS*(dw/8)*NUM_MASTERS))
wb_mem_model0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_V |
`timescale 1 ps / 1 ps
module zynq_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [31:0]gpio;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [31:0]gpio;
zynq_1 zynq_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.gpio(gpio));
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_tx_pipeline.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_tx_pipeline.v //
// //
// Description: //
// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to //
// TRN. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
output trn_tecrc_gen, // TX ECRC generate
input trn_lnk_up, // PCIe link up
// System
//-----------
input tready_thrtl, // TREADY from thrtl ctl
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Input register stage
reg [C_DATA_WIDTH-1:0] reg_tdata;
reg reg_tvalid;
reg [KEEP_WIDTH-1:0] reg_tkeep;
reg [3:0] reg_tuser;
reg reg_tlast;
reg reg_tready;
// Pipeline utility signals
reg trn_in_packet;
reg axi_in_packet;
reg flush_axi;
wire disable_trn;
reg reg_disable_trn;
wire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready;
wire axi_end_packet = axi_beat_live && s_axis_tx_tlast;
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
// 128-bit: 64-bit: 32-bit: //
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 //
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 //
// TRN DW2 maps to AXI DW1 //
// TRN DW3 maps to AXI DW0 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
assign trn_td = {reg_tdata[31:0],
reg_tdata[63:32],
reg_tdata[95:64],
reg_tdata[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
end
else begin : td_DW_swap_32
assign trn_td = reg_tdata;
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_tsof. If we're not currently in a packet and TVALID goes high, //
// assert TSOF. //
//----------------------------------------------------------------------------//
assign trn_tsof = reg_tvalid && !trn_in_packet;
//----------------------------------------------------------------------------//
// Create trn_in_packet. This signal tracks if the TRN interface is currently //
// in the middle of a packet, which is needed to generate trn_tsof //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
trn_in_packet <= #TCQ 1'b1;
end
else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_in_packet. This signal tracks if the AXI interface is currently //
// in the middle of a packet, which is needed in case the link goes down. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
axi_in_packet <= #TCQ 1'b0;
end
else begin
if(axi_beat_live && !s_axis_tx_tlast) begin
axi_in_packet <= #TCQ 1'b1;
end
else if(axi_beat_live) begin
axi_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create disable_trn. This signal asserts when the link goes down and //
// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn //
// depends on C_PM_PRIORITY, as described below. //
//----------------------------------------------------------------------------//
generate
// In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
// the link goes down until the the AXI interface is ready to accept packets
// again (via assertion of TREADY). By waiting for TREADY, we allow the
// previous value buffer to fill, so we're ready for any throttling by the
// user or the block.
if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b1;
end
else begin
// When the link goes down, disable the TRN interface.
if(!trn_lnk_up)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// When the link comes back up and the AXI interface is ready, we can
// release the pipeline and return to normal operation.
else if(!flush_axi && s_axis_tx_tready) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
assign disable_trn = reg_disable_trn;
end
// In the throttle-controlled pipeline, we don't have a previous value buffer.
// The throttle control mechanism handles TREADY, so all we need to do is
// detect when the link goes down and disable the TRN interface until the link
// comes back up and the AXI interface is finished flushing any packets.
else begin : thrtl_ctl_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b0;
end
else begin
// If the link is down and AXI is in packet, disable TRN and look for
// the end of the packet
if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// AXI packet is ending, so we're done flushing
else if(axi_end_packet) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
// Disable the TRN interface if link is down or we're still flushing the AXI
// interface.
assign disable_trn = reg_disable_trn || !trn_lnk_up;
end
endgenerate
//----------------------------------------------------------------------------//
// Convert STRB to RREM. Here, we are converting the encoding method for the //
// location of the EOF from AXI (tkeep) to TRN flavor (rrem). //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
//---------------------------------------//
// Conversion table: //
// trem | tkeep //
// [1] [0] | [15:12] [11:8] [7:4] [3:0] //
// ------------------------------------- //
// 1 1 | D3 D2 D1 D0 //
// 1 0 | -- D2 D1 D0 //
// 0 1 | -- -- D1 D0 //
// 0 0 | -- -- -- D0 //
//---------------------------------------//
wire axi_DW_1 = reg_tkeep[7];
wire axi_DW_2 = reg_tkeep[11];
wire axi_DW_3 = reg_tkeep[15];
assign trn_trem[1] = axi_DW_2;
assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
end
else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
assign trn_trem = reg_tkeep[7];
end
else begin : tkeep_to_trem_32
assign trn_trem = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Create remaining TRN signals //
//----------------------------------------------------------------------------//
assign trn_teof = reg_tlast;
assign trn_tecrc_gen = reg_tuser[0];
assign trn_terrfwd = reg_tuser[1];
assign trn_tstr = reg_tuser[2];
assign trn_tsrc_dsc = reg_tuser[3];
//----------------------------------------------------------------------------//
// Pipeline stage //
//----------------------------------------------------------------------------//
// We need one of two approaches for the pipeline stage depending on the
// C_PM_PRIORITY parameter.
generate
reg reg_tsrc_rdy;
// If set to FALSE, that means the user wants to use the TX packet boundary
// throttling feature. Since all Block throttling will now be predicted, we
// can use a simple straight-through pipeline.
if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tsrc_rdy <= #TCQ 1'b0;
end
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
// Hold trn_tsrc_rdy low when flushing a packet.
reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn;
end
end
assign trn_tsrc_rdy = reg_tsrc_rdy;
// With TX packet boundary throttling, TREADY is pipelined in
// axi_basic_tx_thrtl_ctl and wired through here.
assign s_axis_tx_tready = tready_thrtl;
end
//**************************************************************************//
// If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
// functionality intact isntead of TX packet boundary throttling. Now the
// Block could back-pressure at any time, which creates the standard problem
// of potential data loss due to the handshaking latency. Here we need a
// previous value buffer, just like the RX data path.
else begin : pm_prioity_pipeline
reg [C_DATA_WIDTH-1:0] tdata_prev;
reg tvalid_prev;
reg [KEEP_WIDTH-1:0] tkeep_prev;
reg tlast_prev;
reg [3:0] tuser_prev;
reg reg_tdst_rdy;
wire data_hold;
reg data_prev;
//------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between AXI and TRN, which causes //
// some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. //
// The added cycle of latency in the path causes the Block to fall behind //
// the AXI interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all //
// s_axis_tx_* signals in case the Block throttles. //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
tvalid_prev <= #TCQ 1'b0;
tkeep_prev <= #TCQ {KEEP_WIDTH{1'b0}};
tlast_prev <= #TCQ 1'b0;
tuser_prev <= #TCQ 4'h 0;
end
else begin
// prev buffer works by checking s_axis_tx_tready. When
// s_axis_tx_tready is asserted, a new value is present on the
// interface.
if(!s_axis_tx_tready) begin
tdata_prev <= #TCQ tdata_prev;
tvalid_prev <= #TCQ tvalid_prev;
tkeep_prev <= #TCQ tkeep_prev;
tlast_prev <= #TCQ tlast_prev;
tuser_prev <= #TCQ tuser_prev;
end
else begin
tdata_prev <= #TCQ s_axis_tx_tdata;
tvalid_prev <= #TCQ s_axis_tx_tvalid;
tkeep_prev <= #TCQ s_axis_tx_tkeep;
tlast_prev <= #TCQ s_axis_tx_tlast;
tuser_prev <= #TCQ s_axis_tx_tuser;
end
end
end
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the Block has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on TDATA
// - the Block has finished throttling, and is a little
// behind the user
// CURRENT state: the buffer passes the current value on TDATA
// - the Block is caught up and ready to receive the
// latest data from the user
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tdst_rdy <= #TCQ 1'b0;
end
else begin
reg_tdst_rdy <= #TCQ trn_tdst_rdy;
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
reg_tdata <= #TCQ tdata_prev;
reg_tvalid <= #TCQ tvalid_prev;
reg_tkeep <= #TCQ tkeep_prev;
reg_tlast <= #TCQ tlast_prev;
reg_tuser <= #TCQ tuser_prev;
end
// CURRENT state
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
// Logic to instruct pipeline to use previous bus values. Always use
// previous value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//------------------------------------------------------------------------//
// Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. //
//------------------------------------------------------------------------//
assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
//------------------------------------------------------------------------//
// Create TREADY //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_tready <= #TCQ 1'b0;
end
else begin
// If the link went down and we need to flush a packet in flight, hold
// TREADY high
if(flush_axi && !axi_end_packet) begin
reg_tready <= #TCQ 1'b1;
end
// If the link is up, TREADY is as follows:
// TREADY = 1 when trn_tsrc_rdy == 0
// - While idle, keep the pipeline primed and ready for the next
// packet
//
// TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
// - While in packet, throttle pipeline based on state of TRN
else if(trn_lnk_up) begin
reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
end
// If the link is down and we're not flushing a packet, hold TREADY low
// wait for link to come back up
else begin
reg_tready <= #TCQ 1'b0;
end
end
end
assign s_axis_tx_tready = reg_tready;
end
//--------------------------------------------------------------------------//
// Create flush_axi. This signal detects if the link goes down while the //
// AXI interface is in packet. In this situation, we need to flush the //
// packet through the AXI interface and discard it. //
//--------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
flush_axi <= #TCQ 1'b0;
end
else begin
// If the AXI interface is in packet and the link goes down, purge it.
if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
flush_axi <= #TCQ 1'b1;
end
// The packet is finished, so we're done flushing.
else if(axi_end_packet) begin
flush_axi <= #TCQ 1'b0;
end
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_pipe_pipeline.v
// Version : 1.3
//
// Description: PIPE module for Virtex7 PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_pipe_pipeline #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k_o ,
output wire [15:0] pipe_rx0_data_o ,
output wire pipe_rx0_valid_o ,
output wire pipe_rx0_chanisaligned_o ,
output wire [ 2:0] pipe_rx0_status_o ,
output wire pipe_rx0_phy_status_o ,
output wire pipe_rx0_elec_idle_o ,
input wire pipe_rx0_polarity_i ,
input wire pipe_tx0_compliance_i ,
input wire [ 1:0] pipe_tx0_char_is_k_i ,
input wire [15:0] pipe_tx0_data_i ,
input wire pipe_tx0_elec_idle_i ,
input wire [ 1:0] pipe_tx0_powerdown_i ,
input wire [ 1:0] pipe_rx0_char_is_k_i ,
input wire [15:0] pipe_rx0_data_i ,
input wire pipe_rx0_valid_i ,
input wire pipe_rx0_chanisaligned_i ,
input wire [ 2:0] pipe_rx0_status_i ,
input wire pipe_rx0_phy_status_i ,
input wire pipe_rx0_elec_idle_i ,
output wire pipe_rx0_polarity_o ,
output wire pipe_tx0_compliance_o ,
output wire [ 1:0] pipe_tx0_char_is_k_o ,
output wire [15:0] pipe_tx0_data_o ,
output wire pipe_tx0_elec_idle_o ,
output wire [ 1:0] pipe_tx0_powerdown_o ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k_o ,
output wire [15:0] pipe_rx1_data_o ,
output wire pipe_rx1_valid_o ,
output wire pipe_rx1_chanisaligned_o ,
output wire [ 2:0] pipe_rx1_status_o ,
output wire pipe_rx1_phy_status_o ,
output wire pipe_rx1_elec_idle_o ,
input wire pipe_rx1_polarity_i ,
input wire pipe_tx1_compliance_i ,
input wire [ 1:0] pipe_tx1_char_is_k_i ,
input wire [15:0] pipe_tx1_data_i ,
input wire pipe_tx1_elec_idle_i ,
input wire [ 1:0] pipe_tx1_powerdown_i ,
input wire [ 1:0] pipe_rx1_char_is_k_i ,
input wire [15:0] pipe_rx1_data_i ,
input wire pipe_rx1_valid_i ,
input wire pipe_rx1_chanisaligned_i ,
input wire [ 2:0] pipe_rx1_status_i ,
input wire pipe_rx1_phy_status_i ,
input wire pipe_rx1_elec_idle_i ,
output wire pipe_rx1_polarity_o ,
output wire pipe_tx1_compliance_o ,
output wire [ 1:0] pipe_tx1_char_is_k_o ,
output wire [15:0] pipe_tx1_data_o ,
output wire pipe_tx1_elec_idle_o ,
output wire [ 1:0] pipe_tx1_powerdown_o ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k_o ,
output wire [15:0] pipe_rx2_data_o ,
output wire pipe_rx2_valid_o ,
output wire pipe_rx2_chanisaligned_o ,
output wire [ 2:0] pipe_rx2_status_o ,
output wire pipe_rx2_phy_status_o ,
output wire pipe_rx2_elec_idle_o ,
input wire pipe_rx2_polarity_i ,
input wire pipe_tx2_compliance_i ,
input wire [ 1:0] pipe_tx2_char_is_k_i ,
input wire [15:0] pipe_tx2_data_i ,
input wire pipe_tx2_elec_idle_i ,
input wire [ 1:0] pipe_tx2_powerdown_i ,
input wire [ 1:0] pipe_rx2_char_is_k_i ,
input wire [15:0] pipe_rx2_data_i ,
input wire pipe_rx2_valid_i ,
input wire pipe_rx2_chanisaligned_i ,
input wire [ 2:0] pipe_rx2_status_i ,
input wire pipe_rx2_phy_status_i ,
input wire pipe_rx2_elec_idle_i ,
output wire pipe_rx2_polarity_o ,
output wire pipe_tx2_compliance_o ,
output wire [ 1:0] pipe_tx2_char_is_k_o ,
output wire [15:0] pipe_tx2_data_o ,
output wire pipe_tx2_elec_idle_o ,
output wire [ 1:0] pipe_tx2_powerdown_o ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k_o ,
output wire [15:0] pipe_rx3_data_o ,
output wire pipe_rx3_valid_o ,
output wire pipe_rx3_chanisaligned_o ,
output wire [ 2:0] pipe_rx3_status_o ,
output wire pipe_rx3_phy_status_o ,
output wire pipe_rx3_elec_idle_o ,
input wire pipe_rx3_polarity_i ,
input wire pipe_tx3_compliance_i ,
input wire [ 1:0] pipe_tx3_char_is_k_i ,
input wire [15:0] pipe_tx3_data_i ,
input wire pipe_tx3_elec_idle_i ,
input wire [ 1:0] pipe_tx3_powerdown_i ,
input wire [ 1:0] pipe_rx3_char_is_k_i ,
input wire [15:0] pipe_rx3_data_i ,
input wire pipe_rx3_valid_i ,
input wire pipe_rx3_chanisaligned_i ,
input wire [ 2:0] pipe_rx3_status_i ,
input wire pipe_rx3_phy_status_i ,
input wire pipe_rx3_elec_idle_i ,
output wire pipe_rx3_polarity_o ,
output wire pipe_tx3_compliance_o ,
output wire [ 1:0] pipe_tx3_char_is_k_o ,
output wire [15:0] pipe_tx3_data_o ,
output wire pipe_tx3_elec_idle_o ,
output wire [ 1:0] pipe_tx3_powerdown_o ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k_o ,
output wire [15:0] pipe_rx4_data_o ,
output wire pipe_rx4_valid_o ,
output wire pipe_rx4_chanisaligned_o ,
output wire [ 2:0] pipe_rx4_status_o ,
output wire pipe_rx4_phy_status_o ,
output wire pipe_rx4_elec_idle_o ,
input wire pipe_rx4_polarity_i ,
input wire pipe_tx4_compliance_i ,
input wire [ 1:0] pipe_tx4_char_is_k_i ,
input wire [15:0] pipe_tx4_data_i ,
input wire pipe_tx4_elec_idle_i ,
input wire [ 1:0] pipe_tx4_powerdown_i ,
input wire [ 1:0] pipe_rx4_char_is_k_i ,
input wire [15:0] pipe_rx4_data_i ,
input wire pipe_rx4_valid_i ,
input wire pipe_rx4_chanisaligned_i ,
input wire [ 2:0] pipe_rx4_status_i ,
input wire pipe_rx4_phy_status_i ,
input wire pipe_rx4_elec_idle_i ,
output wire pipe_rx4_polarity_o ,
output wire pipe_tx4_compliance_o ,
output wire [ 1:0] pipe_tx4_char_is_k_o ,
output wire [15:0] pipe_tx4_data_o ,
output wire pipe_tx4_elec_idle_o ,
output wire [ 1:0] pipe_tx4_powerdown_o ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k_o ,
output wire [15:0] pipe_rx5_data_o ,
output wire pipe_rx5_valid_o ,
output wire pipe_rx5_chanisaligned_o ,
output wire [ 2:0] pipe_rx5_status_o ,
output wire pipe_rx5_phy_status_o ,
output wire pipe_rx5_elec_idle_o ,
input wire pipe_rx5_polarity_i ,
input wire pipe_tx5_compliance_i ,
input wire [ 1:0] pipe_tx5_char_is_k_i ,
input wire [15:0] pipe_tx5_data_i ,
input wire pipe_tx5_elec_idle_i ,
input wire [ 1:0] pipe_tx5_powerdown_i ,
input wire [ 1:0] pipe_rx5_char_is_k_i ,
input wire [15:0] pipe_rx5_data_i ,
input wire pipe_rx5_valid_i ,
input wire pipe_rx5_chanisaligned_i ,
input wire [ 2:0] pipe_rx5_status_i ,
input wire pipe_rx5_phy_status_i ,
input wire pipe_rx5_elec_idle_i ,
output wire pipe_rx5_polarity_o ,
output wire pipe_tx5_compliance_o ,
output wire [ 1:0] pipe_tx5_char_is_k_o ,
output wire [15:0] pipe_tx5_data_o ,
output wire pipe_tx5_elec_idle_o ,
output wire [ 1:0] pipe_tx5_powerdown_o ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k_o ,
output wire [15:0] pipe_rx6_data_o ,
output wire pipe_rx6_valid_o ,
output wire pipe_rx6_chanisaligned_o ,
output wire [ 2:0] pipe_rx6_status_o ,
output wire pipe_rx6_phy_status_o ,
output wire pipe_rx6_elec_idle_o ,
input wire pipe_rx6_polarity_i ,
input wire pipe_tx6_compliance_i ,
input wire [ 1:0] pipe_tx6_char_is_k_i ,
input wire [15:0] pipe_tx6_data_i ,
input wire pipe_tx6_elec_idle_i ,
input wire [ 1:0] pipe_tx6_powerdown_i ,
input wire [ 1:0] pipe_rx6_char_is_k_i ,
input wire [15:0] pipe_rx6_data_i ,
input wire pipe_rx6_valid_i ,
input wire pipe_rx6_chanisaligned_i ,
input wire [ 2:0] pipe_rx6_status_i ,
input wire pipe_rx6_phy_status_i ,
input wire pipe_rx6_elec_idle_i ,
output wire pipe_rx6_polarity_o ,
output wire pipe_tx6_compliance_o ,
output wire [ 1:0] pipe_tx6_char_is_k_o ,
output wire [15:0] pipe_tx6_data_o ,
output wire pipe_tx6_elec_idle_o ,
output wire [ 1:0] pipe_tx6_powerdown_o ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k_o ,
output wire [15:0] pipe_rx7_data_o ,
output wire pipe_rx7_valid_o ,
output wire pipe_rx7_chanisaligned_o ,
output wire [ 2:0] pipe_rx7_status_o ,
output wire pipe_rx7_phy_status_o ,
output wire pipe_rx7_elec_idle_o ,
input wire pipe_rx7_polarity_i ,
input wire pipe_tx7_compliance_i ,
input wire [ 1:0] pipe_tx7_char_is_k_i ,
input wire [15:0] pipe_tx7_data_i ,
input wire pipe_tx7_elec_idle_i ,
input wire [ 1:0] pipe_tx7_powerdown_i ,
input wire [ 1:0] pipe_rx7_char_is_k_i ,
input wire [15:0] pipe_rx7_data_i ,
input wire pipe_rx7_valid_i ,
input wire pipe_rx7_chanisaligned_i ,
input wire [ 2:0] pipe_rx7_status_i ,
input wire pipe_rx7_phy_status_i ,
input wire pipe_rx7_elec_idle_i ,
output wire pipe_rx7_polarity_o ,
output wire pipe_tx7_compliance_o ,
output wire [ 1:0] pipe_tx7_char_is_k_o ,
output wire [15:0] pipe_tx7_data_o ,
output wire pipe_tx7_elec_idle_o ,
output wire [ 1:0] pipe_tx7_powerdown_o ,
// Non PIPE signals
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
//synthesis translate_off
// initial begin
// $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d",
// $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES);
// end
//synthesis translate_on
generate
pcie_7x_v1_3_pcie_pipe_misc # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_misc_i (
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
.pipe_tx_reset_i(pipe_tx_reset_i),
.pipe_tx_rate_i(pipe_tx_rate_i),
.pipe_tx_deemph_i(pipe_tx_deemph_i),
.pipe_tx_margin_i(pipe_tx_margin_i),
.pipe_tx_swing_i(pipe_tx_swing_i),
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
.pipe_tx_reset_o(pipe_tx_reset_o),
.pipe_tx_rate_o(pipe_tx_rate_o),
.pipe_tx_deemph_o(pipe_tx_deemph_o),
.pipe_tx_margin_o(pipe_tx_margin_o),
.pipe_tx_swing_o(pipe_tx_swing_o) ,
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_0_i (
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o),
.pipe_rx_data_o(pipe_rx0_data_o),
.pipe_rx_valid_o(pipe_rx0_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
.pipe_rx_status_o(pipe_rx0_status_o),
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
.pipe_tx_data_i(pipe_tx0_data_i),
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
.pipe_rx_data_i(pipe_rx0_data_i),
.pipe_rx_valid_i(pipe_rx0_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
.pipe_rx_status_i(pipe_rx0_status_i),
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
.pipe_tx_data_o(pipe_tx0_data_o),
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_1_i (
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o),
.pipe_rx_data_o(pipe_rx1_data_o),
.pipe_rx_valid_o(pipe_rx1_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
.pipe_rx_status_o(pipe_rx1_status_o),
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
.pipe_tx_data_i(pipe_tx1_data_i),
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
.pipe_rx_data_i(pipe_rx1_data_i),
.pipe_rx_valid_i(pipe_rx1_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
.pipe_rx_status_i(pipe_rx1_status_i),
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
.pipe_tx_data_o(pipe_tx1_data_o),
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 2)
else
begin
assign pipe_rx1_char_is_k_o = 2'b00;
assign pipe_rx1_data_o = 16'h0000;
assign pipe_rx1_valid_o = 1'b0;
assign pipe_rx1_chanisaligned_o = 1'b0;
assign pipe_rx1_status_o = 3'b000;
assign pipe_rx1_phy_status_o = 1'b0;
assign pipe_rx1_elec_idle_o = 1'b1;
assign pipe_rx1_polarity_o = 1'b0;
assign pipe_tx1_compliance_o = 1'b0;
assign pipe_tx1_char_is_k_o = 2'b00;
assign pipe_tx1_data_o = 16'h0000;
assign pipe_tx1_elec_idle_o = 1'b1;
assign pipe_tx1_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2)
if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_2_i (
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o),
.pipe_rx_data_o(pipe_rx2_data_o),
.pipe_rx_valid_o(pipe_rx2_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
.pipe_rx_status_o(pipe_rx2_status_o),
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
.pipe_tx_data_i(pipe_tx2_data_i),
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
.pipe_rx_data_i(pipe_rx2_data_i),
.pipe_rx_valid_i(pipe_rx2_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
.pipe_rx_status_i(pipe_rx2_status_i),
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
.pipe_tx_data_o(pipe_tx2_data_o),
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_3_i (
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o),
.pipe_rx_data_o(pipe_rx3_data_o),
.pipe_rx_valid_o(pipe_rx3_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
.pipe_rx_status_o(pipe_rx3_status_o),
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
.pipe_tx_data_i(pipe_tx3_data_i),
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
.pipe_rx_data_i(pipe_rx3_data_i),
.pipe_rx_valid_i(pipe_rx3_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
.pipe_rx_status_i(pipe_rx3_status_i),
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
.pipe_tx_data_o(pipe_tx3_data_o),
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 4)
else
begin
assign pipe_rx2_char_is_k_o = 2'b00;
assign pipe_rx2_data_o = 16'h0000;
assign pipe_rx2_valid_o = 1'b0;
assign pipe_rx2_chanisaligned_o = 1'b0;
assign pipe_rx2_status_o = 3'b000;
assign pipe_rx2_phy_status_o = 1'b0;
assign pipe_rx2_elec_idle_o = 1'b1;
assign pipe_rx2_polarity_o = 1'b0;
assign pipe_tx2_compliance_o = 1'b0;
assign pipe_tx2_char_is_k_o = 2'b00;
assign pipe_tx2_data_o = 16'h0000;
assign pipe_tx2_elec_idle_o = 1'b1;
assign pipe_tx2_powerdown_o = 2'b00;
assign pipe_rx3_char_is_k_o = 2'b00;
assign pipe_rx3_data_o = 16'h0000;
assign pipe_rx3_valid_o = 1'b0;
assign pipe_rx3_chanisaligned_o = 1'b0;
assign pipe_rx3_status_o = 3'b000;
assign pipe_rx3_phy_status_o = 1'b0;
assign pipe_rx3_elec_idle_o = 1'b1;
assign pipe_rx3_polarity_o = 1'b0;
assign pipe_tx3_compliance_o = 1'b0;
assign pipe_tx3_char_is_k_o = 2'b00;
assign pipe_tx3_data_o = 16'h0000;
assign pipe_tx3_elec_idle_o = 1'b1;
assign pipe_tx3_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4)
if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_4_i (
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o),
.pipe_rx_data_o(pipe_rx4_data_o),
.pipe_rx_valid_o(pipe_rx4_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
.pipe_rx_status_o(pipe_rx4_status_o),
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
.pipe_tx_data_i(pipe_tx4_data_i),
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
.pipe_rx_data_i(pipe_rx4_data_i),
.pipe_rx_valid_i(pipe_rx4_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
.pipe_rx_status_i(pipe_rx4_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
.pipe_tx_data_o(pipe_tx4_data_o),
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_5_i (
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o),
.pipe_rx_data_o(pipe_rx5_data_o),
.pipe_rx_valid_o(pipe_rx5_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
.pipe_rx_status_o(pipe_rx5_status_o),
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
.pipe_tx_data_i(pipe_tx5_data_i),
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
.pipe_rx_data_i(pipe_rx5_data_i),
.pipe_rx_valid_i(pipe_rx5_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
.pipe_rx_status_i(pipe_rx5_status_i),
.pipe_rx_phy_status_i(pipe_rx5_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
.pipe_tx_data_o(pipe_tx5_data_o),
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_6_i (
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o),
.pipe_rx_data_o(pipe_rx6_data_o),
.pipe_rx_valid_o(pipe_rx6_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
.pipe_rx_status_o(pipe_rx6_status_o),
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
.pipe_tx_data_i(pipe_tx6_data_i),
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
.pipe_rx_data_i(pipe_rx6_data_i),
.pipe_rx_valid_i(pipe_rx6_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
.pipe_rx_status_i(pipe_rx6_status_i),
.pipe_rx_phy_status_i(pipe_rx6_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
.pipe_tx_data_o(pipe_tx6_data_o),
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_v1_3_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_7_i (
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o),
.pipe_rx_data_o(pipe_rx7_data_o),
.pipe_rx_valid_o(pipe_rx7_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
.pipe_rx_status_o(pipe_rx7_status_o),
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
.pipe_tx_data_i(pipe_tx7_data_i),
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
.pipe_rx_data_i(pipe_rx7_data_i),
.pipe_rx_valid_i(pipe_rx7_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
.pipe_rx_status_i(pipe_rx7_status_i),
.pipe_rx_phy_status_i(pipe_rx7_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
.pipe_tx_data_o(pipe_tx7_data_o),
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 8)
else
begin
assign pipe_rx4_char_is_k_o = 2'b00;
assign pipe_rx4_data_o = 16'h0000;
assign pipe_rx4_valid_o = 1'b0;
assign pipe_rx4_chanisaligned_o = 1'b0;
assign pipe_rx4_status_o = 3'b000;
assign pipe_rx4_phy_status_o = 1'b0;
assign pipe_rx4_elec_idle_o = 1'b1;
assign pipe_rx4_polarity_o = 1'b0;
assign pipe_tx4_compliance_o = 1'b0;
assign pipe_tx4_char_is_k_o = 2'b00;
assign pipe_tx4_data_o = 16'h0000;
assign pipe_tx4_elec_idle_o = 1'b1;
assign pipe_tx4_powerdown_o = 2'b00;
assign pipe_rx5_char_is_k_o = 2'b00;
assign pipe_rx5_data_o = 16'h0000;
assign pipe_rx5_valid_o = 1'b0;
assign pipe_rx5_chanisaligned_o = 1'b0;
assign pipe_rx5_status_o = 3'b000;
assign pipe_rx5_phy_status_o = 1'b0;
assign pipe_rx5_elec_idle_o = 1'b1;
assign pipe_rx5_polarity_o = 1'b0;
assign pipe_tx5_compliance_o = 1'b0;
assign pipe_tx5_char_is_k_o = 2'b00;
assign pipe_tx5_data_o = 16'h0000;
assign pipe_tx5_elec_idle_o = 1'b1;
assign pipe_tx5_powerdown_o = 2'b00;
assign pipe_rx6_char_is_k_o = 2'b00;
assign pipe_rx6_data_o = 16'h0000;
assign pipe_rx6_valid_o = 1'b0;
assign pipe_rx6_chanisaligned_o = 1'b0;
assign pipe_rx6_status_o = 3'b000;
assign pipe_rx6_phy_status_o = 1'b0;
assign pipe_rx6_elec_idle_o = 1'b1;
assign pipe_rx6_polarity_o = 1'b0;
assign pipe_tx6_compliance_o = 1'b0;
assign pipe_tx6_char_is_k_o = 2'b00;
assign pipe_tx6_data_o = 16'h0000;
assign pipe_tx6_elec_idle_o = 1'b1;
assign pipe_tx6_powerdown_o = 2'b00;
assign pipe_rx7_char_is_k_o = 2'b00;
assign pipe_rx7_data_o = 16'h0000;
assign pipe_rx7_valid_o = 1'b0;
assign pipe_rx7_chanisaligned_o = 1'b0;
assign pipe_rx7_status_o = 3'b000;
assign pipe_rx7_phy_status_o = 1'b0;
assign pipe_rx7_elec_idle_o = 1'b1;
assign pipe_rx7_polarity_o = 1'b0;
assign pipe_tx7_compliance_o = 1'b0;
assign pipe_tx7_char_is_k_o = 2'b00;
assign pipe_tx7_data_o = 16'h0000;
assign pipe_tx7_elec_idle_o = 1'b1;
assign pipe_tx7_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8)
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_SYMBOL_V
`define SKY130_FD_SC_LS__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:30
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display(
input clk_display,
input [31:0] num,
input [7:0] puntos,
output [7:0] segmentos,
output reg [7:0] anodos
);
reg [2:0] counter;
reg [3:0] X;
always @(posedge clk_display) begin
counter <= counter+3'b1;
end
always @(counter) begin
case (counter)
4'd0: anodos= 8'b01111111;
4'd1: anodos= 8'b10111111;
4'd2: anodos= 8'b11011111;
4'd3: anodos= 8'b11101111;
4'd4: anodos= 8'b11110111;
4'd5: anodos= 8'b11111011;
4'd6: anodos= 8'b11111101;
4'd7: anodos= 8'b11111110;
default: anodos=8'b11111111;
endcase
end
always @(*) begin
case(anodos)
8'b01111111: X=num[31:28];
8'b10111111: X=num[27:24];
8'b11011111: X=num[23:20];
8'b11101111: X=num[19:16];
8'b11110111: X=num[15:12];
8'b11111011: X=num[11:8];
8'b11111101: X=num[7:4];
8'b11111110: X=num[3:0];
default: X=4'b0 ;
endcase
end
Dec_4b_seg Dec(
. NUM(X),
. CATODOS({segmentos})
);
endmodule |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ([email protected])
//Last Modified: Feb 25 2014
//Description: MBUS Register File
// Semi Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module lc_mbc_iso
(
//**************************************
//Power Domain
//Input - Always On
//Output - N/A
//**************************************
//Signals
//Input
MBC_ISOLATE,
// LC --> MBC
//Input
ADDROUT_uniso,
DATAOUT_uniso,
PENDOUT_uniso,
REQOUT_uniso,
PRIORITYOUT_uniso,
ACKOUT_uniso,
RESPOUT_uniso,
//Output
ADDROUT, // ISOL value = Low
DATAOUT, // ISOL value = Low
PENDOUT, // ISOL value = Low
REQOUT, // ISOL value = Low
PRIORITYOUT, // ISOL value = Low
ACKOUT, // ISOL value = Low
RESPOUT, // ISOL value = Low
// MBC --> LC
//Input
LRC_SLEEP_uniso,
LRC_RESET_uniso,
LRC_ISOLATE_uniso,
//Output
LRC_SLEEP, // ISOL value = High
LRC_RESET, // ISOL value = High
LRC_ISOLATE, // ISOL value = High
// MBC --> SC
//Input
SLEEP_REQ_uniso,
//Output
SLEEP_REQ // ISOL value = Low
);
//Input
input MBC_ISOLATE;
// LC --> MBC
//Input
input [31:0] ADDROUT_uniso;
input [31:0] DATAOUT_uniso;
input PENDOUT_uniso;
input REQOUT_uniso;
input PRIORITYOUT_uniso;
input ACKOUT_uniso;
input RESPOUT_uniso;
//Output
output [31:0] ADDROUT;
output [31:0] DATAOUT;
output PENDOUT;
output REQOUT;
output PRIORITYOUT;
output ACKOUT;
output RESPOUT;
// MBC --> LC
//Input
input LRC_SLEEP_uniso;
input LRC_RESET_uniso;
input LRC_ISOLATE_uniso;
//Output
output LRC_SLEEP;
output LRC_RESET;
output LRC_ISOLATE;
// MBC --> SC
input SLEEP_REQ_uniso;
output SLEEP_REQ;
// LC --> MBC
assign ADDROUT = ~LRC_ISOLATE & ADDROUT_uniso;
assign DATAOUT = ~LRC_ISOLATE & DATAOUT_uniso;
assign PENDOUT = ~LRC_ISOLATE & PENDOUT_uniso;
assign REQOUT = ~LRC_ISOLATE & REQOUT_uniso;
assign PRIORITYOUT = ~LRC_ISOLATE & PRIORITYOUT_uniso;
assign ACKOUT = ~LRC_ISOLATE & ACKOUT_uniso;
assign RESPOUT = ~LRC_ISOLATE & RESPOUT_uniso;
// MBC --> LC
assign LRC_SLEEP = MBC_ISOLATE | LRC_SLEEP_uniso;
assign LRC_RESET = MBC_ISOLATE | LRC_RESET_uniso;
assign LRC_ISOLATE = MBC_ISOLATE | LRC_ISOLATE_uniso;
// MBC --> SC
assign SLEEP_REQ = ~MBC_ISOLATE & SLEEP_REQ_uniso;
endmodule // lc_mbc_iso
|
//
module spree (
clk,
resetn,
boot_iaddr,
boot_idata,
boot_iwe,
boot_daddr,
boot_ddata,
boot_dwe,
pipereg20_q
);
/************************* IO Declarations *********************/
/****************************************************************************
ISA definition file
- The MIPS I ISA has a 6 bit opcode in the upper 6 bits.
- The opcode can also specify a "class". There are two classes:
1. SPECIAL - look in lowest 6 bits to find operation
2. REGIMM - look in [20:16] to find type of branch
****************************************************************************/
/****** OPCODES - bits 31...26 *******/
parameter OP_SPECIAL = 6'b000000;
parameter OP_REGIMM = 6'b000001;
parameter OP_J = 6'b000010;
parameter OP_JAL = 6'b000011;
parameter OP_BEQ = 6'b000100;
parameter OP_BNE = 6'b000101;
parameter OP_BLEZ = 6'b000110;
parameter OP_BGTZ = 6'b000111;
parameter OP_ADDI = 6'b001000;
parameter OP_ADDIU = 6'b001001;
parameter OP_SLTI = 6'b001010;
parameter OP_SLTIU = 6'b001011;
parameter OP_ANDI = 6'b001100;
parameter OP_ORI = 6'b001101;
parameter OP_XORI = 6'b001110;
parameter OP_LUI = 6'b001111;
parameter OP_LB = 6'b100000;
parameter OP_LH = 6'b100001;
parameter OP_LWL = 6'b100010;
parameter OP_LW = 6'b100011;
parameter OP_LBU = 6'b100100;
parameter OP_LHU = 6'b100101;
parameter OP_LWR = 6'b100110;
parameter OP_SB = 6'b101x00;
parameter OP_SH = 6'b101x01;
parameter OP_SWL = 6'b101010;
parameter OP_SW = 6'b101x11;
parameter OP_SWR = 6'b101110;
/****** FUNCTION CLASS - bits 5...0 *******/
parameter FUNC_SLL = 6'b000000;
parameter FUNC_SRL = 6'b000010;
parameter FUNC_SRA = 6'b000011;
parameter FUNC_SLLV = 6'b000100;
parameter FUNC_SRLV = 6'b000110;
parameter FUNC_SRAV = 6'b000111;
parameter FUNC_JR = 6'b001xx0;
parameter FUNC_JALR = 6'b001xx1;
parameter FUNC_MFHI = 6'bx10x00;
parameter FUNC_MTHI = 6'bx10x01;
parameter FUNC_MFLO = 6'bx10x10;
parameter FUNC_MTLO = 6'bx10x11;
parameter FUNC_MULT = 6'bx11x00;
parameter FUNC_MULTU = 6'bx11x01;
parameter FUNC_DIV = 6'bx11x10;
parameter FUNC_DIVU = 6'bx11x11;
parameter FUNC_ADD = 6'b100000;
parameter FUNC_ADDU = 6'b100001;
parameter FUNC_SUB = 6'b100010;
parameter FUNC_SUBU = 6'b100011;
parameter FUNC_AND = 6'b100100;
parameter FUNC_OR = 6'b100101;
parameter FUNC_XOR = 6'b100110;
parameter FUNC_NOR = 6'b100111;
parameter FUNC_SLT = 6'b101010;
parameter FUNC_SLTU = 6'b101011;
/****** REGIMM Class - bits 20...16 *******/
parameter FUNC_BLTZ = 1'b0;
parameter FUNC_BGEZ = 1'b1;
parameter OP_COP2 = 6'b010010;
parameter COP2_FUNC_CFC2 = 6'b111000;
parameter COP2_FUNC_CTC2 = 6'b111010;
parameter COP2_FUNC_MTC2 = 6'b111011;
//parameter FUNC_BLTZAL = 5'b10000;
//parameter FUNC_BGEZAL = 5'b10001;
/******
* Original REGIMM class, compressed above to save decode logic
parameter FUNC_BLTZ = 5'b00000;
parameter FUNC_BGEZ = 5'b00001;
parameter FUNC_BLTZAL = 5'b10000;
parameter FUNC_BGEZAL = 5'b10001;
*/
input clk;
input resetn;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
output [31:0] pipereg20_q;
/*********************** Signal Declarations *******************/
wire branch_mispred;
wire stall_2nd_delayslot;
wire has_delayslot;
wire haz_pipereg5_q_pipereg29_q;
wire haz_pipereg4_q_pipereg29_q;
wire haz_pipereg5_q_pipereg28_q;
wire haz_pipereg4_q_pipereg28_q;
wire haz_pipereg5_q_pipereg27_q;
wire haz_pipereg4_q_pipereg27_q;
wire haz_pipereg5_q_pipereg12_q;
wire haz_pipereg4_q_pipereg12_q;
// Datapath signals declarations
wire addersub_result_slt;
wire [ 31 : 0 ] addersub_result;
wire [ 31 : 0 ] shifter_result;
wire [ 31 : 0 ] mul_lo;
wire [ 31 : 0 ] mul_hi;
wire [ 31 : 0 ] data_mem_d_loadresult;
wire [ 31 : 0 ] logic_unit_result;
wire [ 31 : 0 ] ifetch_pc_out;
wire [ 31 : 0 ] ifetch_instr;
wire [ 5 : 0 ] ifetch_opcode;
wire [ 5 : 0 ] ifetch_func;
wire [ 4 : 0 ] ifetch_rs;
wire [ 4 : 0 ] ifetch_rt;
wire [ 4 : 0 ] ifetch_rd;
wire [ 25 : 0 ] ifetch_instr_index;
wire [ 15 : 0 ] ifetch_offset;
wire [ 4 : 0 ] ifetch_sa;
wire [ 31 : 0 ] ifetch_next_pc;
wire [ 31 : 0 ] signext16_out;
wire [ 31 : 0 ] reg_file_b_readdataout;
wire [ 31 : 0 ] reg_file_a_readdataout;
wire [ 31 : 0 ] pcadder_result;
wire [ 31 : 0 ] lo_reg_q;
wire [ 31 : 0 ] const21_out;
wire [ 31 : 0 ] merge26lo_out;
wire branchresolve_eqz;
wire branchresolve_gez;
wire branchresolve_gtz;
wire branchresolve_lez;
wire branchresolve_ltz;
wire branchresolve_ne;
wire branchresolve_eq;
wire [ 31 : 0 ] hi_reg_q;
wire [ 31 : 0 ] const_out;
wire [ 31 : 0 ] const22_out;
wire [ 4 : 0 ] pipereg5_q;
wire [ 4 : 0 ] pipereg4_q;
wire [ 15 : 0 ] pipereg1_q;
wire [ 4 : 0 ] pipereg11_q;
wire [ 25 : 0 ] pipereg2_q;
wire [ 4 : 0 ] pipereg_q;
wire [ 31 : 0 ] pipereg6_q;
wire [ 31 : 0 ] pipereg3_q;
wire [ 25 : 0 ] pipereg7_q;
wire [ 31 : 0 ] pipereg9_q;
wire [ 4 : 0 ] pipereg8_q;
wire [ 31 : 0 ] pipereg17_q;
wire [ 31 : 0 ] pipereg20_q;
wire [ 31 : 0 ] pipereg18_q;
wire [ 31 : 0 ] pipereg16_q;
wire [ 31 : 0 ] pipereg15_q;
wire [ 31 : 0 ] pipereg13_q;
wire [ 31 : 0 ] pipereg14_q;
wire [ 31 : 0 ] pipereg23_q;
wire [ 31 : 0 ] pipereg25_q;
wire [ 31 : 0 ] pipereg24_q;
wire [ 4 : 0 ] pipereg12_q;
wire [ 4 : 0 ] pipereg27_q;
wire [ 4 : 0 ] pipereg28_q;
wire [ 31 : 0 ] pipereg47_q;
wire [ 4 : 0 ] pipereg29_q;
wire [ 31 : 0 ] nop19_q;
wire [ 31 : 0 ] nop26_q;
wire [ 4 : 0 ] zeroer0_q;
wire [ 4 : 0 ] zeroer_q;
wire [ 4 : 0 ] zeroer10_q;
wire [ 31 : 0 ] fakedelay_q;
wire [ 31 : 0 ] nop_q;
wire [ 31 : 0 ] mux2to1_addersub_opA_out;
wire [ 31 : 0 ] mux2to1_pipereg6_d_out;
wire [ 31 : 0 ] mux3to1_pipereg16_d_out;
wire [ 31 : 0 ] mux3to1_pipereg18_d_out;
wire [ 31 : 0 ] mux6to1_pipereg14_d_out;
wire [ 31 : 0 ] mux3to1_pipereg13_d_out;
wire [ 31 : 0 ] mux3to1_pipereg23_d_out;
wire [ 31 : 0 ] mux2to1_pipereg25_d_out;
wire [ 31 : 0 ] mux4to1_nop26_d_out;
wire [ 4 : 0 ] mux3to1_zeroer10_d_out;
wire [ 5 : 0 ] pipereg30_q;
wire [ 5 : 0 ] pipereg33_q;
wire [ 5 : 0 ] pipereg34_q;
wire [ 4 : 0 ] pipereg35_q;
wire [ 5 : 0 ] pipereg36_q;
wire [ 5 : 0 ] pipereg37_q;
wire [ 4 : 0 ] pipereg38_q;
wire [ 4 : 0 ] pipereg41_q;
wire [ 5 : 0 ] pipereg40_q;
wire [ 5 : 0 ] pipereg39_q;
wire [ 5 : 0 ] pipereg31_q;
wire [ 4 : 0 ] pipereg32_q;
wire [ 5 : 0 ] pipereg42_q;
wire [ 5 : 0 ] pipereg43_q;
wire [ 4 : 0 ] pipereg44_q;
wire branch_detector_is_branch;
wire pipereg45_q;
wire pipereg46_q;
wire [ 31 : 0 ] mux2to1_nop_d_out;
wire pipereg48_q;
wire pipereg49_q;
wire [ 31 : 0 ] mux2to1_nop19_d_out;
/***************** Control Signals ***************/
//Decoded Opcode signal declarations
reg [ 2 : 0 ] ctrl_mux6to1_pipereg14_d_sel;
reg ctrl_mux2to1_pipereg6_d_sel;
reg ctrl_mux2to1_addersub_opA_sel;
reg [ 1 : 0 ] ctrl_mux4to1_nop26_d_sel;
reg ctrl_mux2to1_pipereg25_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg23_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg18_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg16_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg13_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_zeroer10_d_sel;
reg ctrl_zeroer10_en;
reg ctrl_zeroer_en;
reg ctrl_zeroer0_en;
reg [ 2 : 0 ] ctrl_addersub_op;
reg ctrl_ifetch_op;
reg [ 3 : 0 ] ctrl_data_mem_op;
reg ctrl_mul_op;
reg [ 1 : 0 ] ctrl_shifter_op;
reg [ 1 : 0 ] ctrl_logic_unit_op;
//Enable signal declarations
reg ctrl_hi_reg_en;
reg ctrl_lo_reg_en;
reg ctrl_branchresolve_en;
reg ctrl_reg_file_c_we;
reg ctrl_reg_file_b_en;
reg ctrl_reg_file_a_en;
reg ctrl_ifetch_we;
reg ctrl_data_mem_en;
reg ctrl_ifetch_en;
//Other Signals
wire squash_stage6;
wire stall_out_stage6;
wire squash_stage5;
wire stall_out_stage5;
wire ctrl_pipereg25_squashn;
wire ctrl_pipereg29_squashn;
wire ctrl_pipereg24_squashn;
wire ctrl_pipereg42_squashn;
wire ctrl_pipereg43_squashn;
wire ctrl_pipereg44_squashn;
wire ctrl_pipereg25_resetn;
wire ctrl_pipereg29_resetn;
wire ctrl_pipereg24_resetn;
wire ctrl_pipereg42_resetn;
wire ctrl_pipereg43_resetn;
wire ctrl_pipereg44_resetn;
wire ctrl_pipereg25_en;
wire ctrl_pipereg29_en;
wire ctrl_pipereg24_en;
wire ctrl_pipereg42_en;
wire ctrl_pipereg43_en;
wire ctrl_pipereg44_en;
wire squash_stage4;
wire stall_out_stage4;
wire ctrl_pipereg23_squashn;
wire ctrl_pipereg28_squashn;
wire ctrl_pipereg39_squashn;
wire ctrl_pipereg40_squashn;
wire ctrl_pipereg41_squashn;
wire ctrl_pipereg23_resetn;
wire ctrl_pipereg28_resetn;
wire ctrl_pipereg39_resetn;
wire ctrl_pipereg40_resetn;
wire ctrl_pipereg41_resetn;
wire ctrl_pipereg23_en;
wire ctrl_pipereg28_en;
wire ctrl_pipereg39_en;
wire ctrl_pipereg40_en;
wire ctrl_pipereg41_en;
wire squash_stage3;
wire stall_out_stage3;
wire ctrl_pipereg16_squashn;
wire ctrl_pipereg27_squashn;
wire ctrl_pipereg17_squashn;
wire ctrl_pipereg18_squashn;
wire ctrl_pipereg20_squashn;
wire ctrl_pipereg13_squashn;
wire ctrl_pipereg15_squashn;
wire ctrl_pipereg14_squashn;
wire ctrl_pipereg36_squashn;
wire ctrl_pipereg37_squashn;
wire ctrl_pipereg38_squashn;
wire ctrl_pipereg16_resetn;
wire ctrl_pipereg27_resetn;
wire ctrl_pipereg17_resetn;
wire ctrl_pipereg18_resetn;
wire ctrl_pipereg20_resetn;
wire ctrl_pipereg13_resetn;
wire ctrl_pipereg15_resetn;
wire ctrl_pipereg14_resetn;
wire ctrl_pipereg36_resetn;
wire ctrl_pipereg37_resetn;
wire ctrl_pipereg38_resetn;
wire ctrl_pipereg16_en;
wire ctrl_pipereg27_en;
wire ctrl_pipereg17_en;
wire ctrl_pipereg18_en;
wire ctrl_pipereg20_en;
wire ctrl_pipereg13_en;
wire ctrl_pipereg15_en;
wire ctrl_pipereg14_en;
wire ctrl_pipereg36_en;
wire ctrl_pipereg37_en;
wire ctrl_pipereg38_en;
wire squash_stage2;
wire stall_out_stage2;
wire ctrl_pipereg49_squashn;
wire ctrl_pipereg48_squashn;
wire ctrl_pipereg47_squashn;
wire ctrl_pipereg6_squashn;
wire ctrl_pipereg12_squashn;
wire ctrl_pipereg8_squashn;
wire ctrl_pipereg9_squashn;
wire ctrl_pipereg7_squashn;
wire ctrl_pipereg33_squashn;
wire ctrl_pipereg34_squashn;
wire ctrl_pipereg35_squashn;
wire ctrl_pipereg49_resetn;
wire ctrl_pipereg48_resetn;
wire ctrl_pipereg47_resetn;
wire ctrl_pipereg6_resetn;
wire ctrl_pipereg12_resetn;
wire ctrl_pipereg8_resetn;
wire ctrl_pipereg9_resetn;
wire ctrl_pipereg7_resetn;
wire ctrl_pipereg33_resetn;
wire ctrl_pipereg34_resetn;
wire ctrl_pipereg35_resetn;
wire ctrl_pipereg49_en;
wire ctrl_pipereg48_en;
wire ctrl_pipereg47_en;
wire ctrl_pipereg6_en;
wire ctrl_pipereg12_en;
wire ctrl_pipereg8_en;
wire ctrl_pipereg9_en;
wire ctrl_pipereg7_en;
wire ctrl_pipereg33_en;
wire ctrl_pipereg34_en;
wire ctrl_pipereg35_en;
wire squash_stage1;
wire stall_out_stage1;
wire ctrl_pipereg46_squashn;
wire ctrl_pipereg1_squashn;
wire ctrl_pipereg11_squashn;
wire ctrl_pipereg4_squashn;
wire ctrl_pipereg5_squashn;
wire ctrl_pipereg_squashn;
wire ctrl_pipereg3_squashn;
wire ctrl_pipereg2_squashn;
wire ctrl_pipereg30_squashn;
wire ctrl_pipereg31_squashn;
wire ctrl_pipereg32_squashn;
wire ctrl_pipereg46_resetn;
wire ctrl_pipereg1_resetn;
wire ctrl_pipereg11_resetn;
wire ctrl_pipereg4_resetn;
wire ctrl_pipereg5_resetn;
wire ctrl_pipereg_resetn;
wire ctrl_pipereg3_resetn;
wire ctrl_pipereg2_resetn;
wire ctrl_pipereg30_resetn;
wire ctrl_pipereg31_resetn;
wire ctrl_pipereg32_resetn;
wire ctrl_pipereg46_en;
wire ctrl_pipereg1_en;
wire ctrl_pipereg11_en;
wire ctrl_pipereg4_en;
wire ctrl_pipereg5_en;
wire ctrl_pipereg_en;
wire ctrl_pipereg3_en;
wire ctrl_pipereg2_en;
wire ctrl_pipereg30_en;
wire ctrl_pipereg31_en;
wire ctrl_pipereg32_en;
/****************************** Control **************************/
//Decode Logic for Opcode and Multiplex Select signals
always@(ifetch_opcode or ifetch_func or ifetch_rt)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_zeroer10_d_sel = 0;
ctrl_zeroer10_en = 0;
ctrl_zeroer_en = 0;
ctrl_zeroer0_en = 0;
casex (ifetch_opcode)
OP_ADDI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ADDIU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ANDI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_BEQ:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_BGTZ:
ctrl_zeroer0_en = 1;
OP_BLEZ:
ctrl_zeroer0_en = 1;
OP_BNE:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_JAL:
begin
ctrl_mux3to1_zeroer10_d_sel = 0;
ctrl_zeroer10_en = 1;
end
OP_LB:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LBU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LH:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LHU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LUI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
end
OP_LW:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ORI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_REGIMM:
casex (ifetch_rt[0])
FUNC_BGEZ:
ctrl_zeroer0_en = 1;
FUNC_BLTZ:
ctrl_zeroer0_en = 1;
endcase
OP_SB:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SH:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SLTI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SLTIU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SPECIAL:
casex (ifetch_func)
FUNC_ADD:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_ADDU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_AND:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_JALR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_JR:
ctrl_zeroer0_en = 1;
FUNC_MFHI:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
end
FUNC_MFLO:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
end
FUNC_MULT:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_MULTU:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_NOR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_OR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLL:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SLLV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLT:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLTU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SRA:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SRAV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SRL:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SRLV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SUB:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SUBU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_XOR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
endcase
OP_SW:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_XORI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
endcase
end
//Logic for enable signals in Pipe Stage 1
always@(ifetch_opcode or ifetch_func or ifetch_rt[0] or stall_out_stage2 or stall_2nd_delayslot)
begin
ctrl_ifetch_en = 1 &~stall_2nd_delayslot&~stall_out_stage2;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg30_q or pipereg31_q or pipereg32_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_pipereg6_d_sel = 0;
casex (pipereg30_q)
OP_ADDI:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ADDIU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ANDI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_BEQ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BGTZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BLEZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BNE:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LB:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LBU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LH:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LHU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LUI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_LW:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ORI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_REGIMM:
casex (pipereg32_q[0])
FUNC_BGEZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
FUNC_BLTZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
endcase
OP_SB:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SH:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SLTI:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SLTIU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SW:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_XORI:
ctrl_mux2to1_pipereg6_d_sel = 1;
endcase
end
//Logic for enable signals in Pipe Stage 2
always@(pipereg30_q or pipereg31_q or pipereg32_q[0] or stall_out_stage3 or haz_pipereg5_q_pipereg12_q or haz_pipereg4_q_pipereg12_q or haz_pipereg4_q_pipereg27_q or haz_pipereg5_q_pipereg27_q or haz_pipereg4_q_pipereg28_q or haz_pipereg5_q_pipereg28_q)
begin
ctrl_reg_file_b_en = 1 &~haz_pipereg5_q_pipereg28_q&~haz_pipereg4_q_pipereg28_q&~haz_pipereg5_q_pipereg27_q&~haz_pipereg4_q_pipereg27_q&~haz_pipereg4_q_pipereg12_q&~haz_pipereg5_q_pipereg12_q&~stall_out_stage3;
ctrl_reg_file_a_en = 1 &~haz_pipereg5_q_pipereg28_q&~haz_pipereg4_q_pipereg28_q&~haz_pipereg5_q_pipereg27_q&~haz_pipereg4_q_pipereg27_q&~haz_pipereg4_q_pipereg12_q&~haz_pipereg5_q_pipereg12_q&~stall_out_stage3;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg33_q or pipereg34_q or pipereg35_q)
begin
// Initialize control opcodes to zero
ctrl_mux6to1_pipereg14_d_sel = 0;
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 0;
ctrl_mux3to1_pipereg13_d_sel = 0;
casex (pipereg33_q)
OP_ADDI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ADDIU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ANDI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_BEQ:
begin
ctrl_mux6to1_pipereg14_d_sel = 5;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BGTZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 0;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BLEZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 3;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BNE:
begin
ctrl_mux6to1_pipereg14_d_sel = 4;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_J:
ctrl_mux3to1_pipereg13_d_sel = 1;
OP_JAL:
ctrl_mux3to1_pipereg13_d_sel = 1;
OP_LB:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LBU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LH:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LHU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LUI:
begin
ctrl_mux3to1_pipereg18_d_sel = 1;
ctrl_mux3to1_pipereg16_d_sel = 2;
end
OP_LW:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ORI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_REGIMM:
casex (pipereg35_q[0])
FUNC_BGEZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 1;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
FUNC_BLTZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 2;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
endcase
OP_SB:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SH:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SLTI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SLTIU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SPECIAL:
casex (pipereg34_q)
FUNC_ADD:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_ADDU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_AND:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_JALR:
ctrl_mux3to1_pipereg13_d_sel = 0;
FUNC_JR:
ctrl_mux3to1_pipereg13_d_sel = 0;
FUNC_NOR:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_OR:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SLL:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SLLV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SLT:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SLTU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SRA:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRAV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRL:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRLV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SUB:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SUBU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_XOR:
ctrl_mux3to1_pipereg16_d_sel = 1;
endcase
OP_SW:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_XORI:
ctrl_mux3to1_pipereg16_d_sel = 2;
endcase
end
//Logic for enable signals in Pipe Stage 3
always@(pipereg33_q or pipereg34_q or pipereg35_q[0] or stall_out_stage4)
begin
ctrl_branchresolve_en = 0;
casex (pipereg33_q)
OP_BEQ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BGTZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BLEZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BNE:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_REGIMM:
casex (pipereg35_q[0])
FUNC_BGEZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
FUNC_BLTZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
endcase
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg36_q or pipereg37_q or pipereg38_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_addersub_op = 0;
ctrl_ifetch_op = 0;
ctrl_data_mem_op = 0;
ctrl_mul_op = 0;
ctrl_shifter_op = 0;
ctrl_logic_unit_op = 0;
casex (pipereg36_q)
OP_ADDI:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 3;
end
OP_ADDIU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 1;
end
OP_ANDI:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 0;
end
OP_BEQ:
ctrl_ifetch_op = 0;
OP_BGTZ:
ctrl_ifetch_op = 0;
OP_BLEZ:
ctrl_ifetch_op = 0;
OP_BNE:
ctrl_ifetch_op = 0;
OP_J:
ctrl_ifetch_op = 1;
OP_JAL:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
OP_LB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 7;
end
OP_LBU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 3;
end
OP_LH:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 5;
end
OP_LHU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 1;
end
OP_LUI:
ctrl_shifter_op = 0;
OP_LW:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 0;
end
OP_ORI:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 1;
end
OP_REGIMM:
casex (pipereg38_q[0])
FUNC_BGEZ:
ctrl_ifetch_op = 0;
FUNC_BLTZ:
ctrl_ifetch_op = 0;
endcase
OP_SB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 11;
end
OP_SH:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 9;
end
OP_SLTI:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 1;
ctrl_addersub_op = 6;
end
OP_SLTIU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 1;
ctrl_addersub_op = 4;
end
OP_SPECIAL:
casex (pipereg37_q)
FUNC_ADD:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 3;
end
FUNC_ADDU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 1;
end
FUNC_AND:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 0;
end
FUNC_JALR:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
FUNC_JR:
ctrl_ifetch_op = 1;
FUNC_MULT:
ctrl_mul_op = 1;
FUNC_MULTU:
ctrl_mul_op = 0;
FUNC_NOR:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 3;
end
FUNC_OR:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 1;
end
FUNC_SLL:
ctrl_shifter_op = 0;
FUNC_SLLV:
ctrl_shifter_op = 0;
FUNC_SLT:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 1;
ctrl_addersub_op = 6;
end
FUNC_SLTU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 1;
ctrl_addersub_op = 4;
end
FUNC_SRA:
ctrl_shifter_op = 3;
FUNC_SRAV:
ctrl_shifter_op = 3;
FUNC_SRL:
ctrl_shifter_op = 1;
FUNC_SRLV:
ctrl_shifter_op = 1;
FUNC_SUB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 0;
end
FUNC_SUBU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg23_d_sel = 2;
ctrl_addersub_op = 2;
end
FUNC_XOR:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 2;
end
endcase
OP_SW:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 8;
end
OP_XORI:
begin
ctrl_mux3to1_pipereg23_d_sel = 0;
ctrl_logic_unit_op = 2;
end
endcase
end
//Logic for enable signals in Pipe Stage 4
always@(pipereg36_q or pipereg37_q or pipereg38_q[0] or stall_out_stage5)
begin
ctrl_ifetch_we = 0;
ctrl_data_mem_en = 0;
casex (pipereg36_q)
OP_BEQ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BGTZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BLEZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BNE:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_J:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_JAL:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_LB:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LBU:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LH:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LHU:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LW:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_REGIMM:
casex (pipereg38_q[0])
FUNC_BGEZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
FUNC_BLTZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
endcase
OP_SB:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_SH:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_SPECIAL:
casex (pipereg37_q)
FUNC_JALR:
ctrl_ifetch_we = 1 &~stall_out_stage5;
FUNC_JR:
ctrl_ifetch_we = 1 &~stall_out_stage5;
endcase
OP_SW:
ctrl_data_mem_en = 1 &~stall_out_stage5;
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg39_q or pipereg40_q or pipereg41_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_pipereg25_d_sel = 0;
casex (pipereg39_q)
OP_ADDI:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_ADDIU:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_ANDI:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_JAL:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_LUI:
ctrl_mux2to1_pipereg25_d_sel = 0;
OP_ORI:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_SLTI:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_SLTIU:
ctrl_mux2to1_pipereg25_d_sel = 1;
OP_SPECIAL:
casex (pipereg40_q)
FUNC_ADD:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_ADDU:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_AND:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_JALR:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_NOR:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_OR:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_SLL:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SLLV:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SLT:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_SLTU:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_SRA:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SRAV:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SRL:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SRLV:
ctrl_mux2to1_pipereg25_d_sel = 0;
FUNC_SUB:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_SUBU:
ctrl_mux2to1_pipereg25_d_sel = 1;
FUNC_XOR:
ctrl_mux2to1_pipereg25_d_sel = 1;
endcase
OP_XORI:
ctrl_mux2to1_pipereg25_d_sel = 1;
endcase
end
//Logic for enable signals in Pipe Stage 5
always@(pipereg39_q or pipereg40_q or pipereg41_q[0] or stall_out_stage6)
begin
ctrl_lo_reg_en = 0;
ctrl_hi_reg_en = 0;
casex (pipereg39_q)
OP_SPECIAL:
casex (pipereg40_q)
FUNC_MULT:
begin
ctrl_lo_reg_en = 1 &~stall_out_stage6;
ctrl_hi_reg_en = 1 &~stall_out_stage6;
end
FUNC_MULTU:
begin
ctrl_lo_reg_en = 1 &~stall_out_stage6;
ctrl_hi_reg_en = 1 &~stall_out_stage6;
end
endcase
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg42_q or pipereg43_q or pipereg44_q)
begin
// Initialize control opcodes to zero
ctrl_mux4to1_nop26_d_sel = 0;
casex (pipereg42_q)
OP_ADDI:
ctrl_mux4to1_nop26_d_sel = 3;
OP_ADDIU:
ctrl_mux4to1_nop26_d_sel = 3;
OP_ANDI:
ctrl_mux4to1_nop26_d_sel = 3;
OP_JAL:
ctrl_mux4to1_nop26_d_sel = 3;
OP_LB:
ctrl_mux4to1_nop26_d_sel = 2;
OP_LBU:
ctrl_mux4to1_nop26_d_sel = 2;
OP_LH:
ctrl_mux4to1_nop26_d_sel = 2;
OP_LHU:
ctrl_mux4to1_nop26_d_sel = 2;
OP_LUI:
ctrl_mux4to1_nop26_d_sel = 3;
OP_LW:
ctrl_mux4to1_nop26_d_sel = 2;
OP_ORI:
ctrl_mux4to1_nop26_d_sel = 3;
OP_SLTI:
ctrl_mux4to1_nop26_d_sel = 3;
OP_SLTIU:
ctrl_mux4to1_nop26_d_sel = 3;
OP_SPECIAL:
casex (pipereg43_q)
FUNC_ADD:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_ADDU:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_AND:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_JALR:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_MFHI:
ctrl_mux4to1_nop26_d_sel = 1;
FUNC_MFLO:
ctrl_mux4to1_nop26_d_sel = 0;
FUNC_NOR:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_OR:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SLL:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SLLV:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SLT:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SLTU:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SRA:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SRAV:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SRL:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SRLV:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SUB:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_SUBU:
ctrl_mux4to1_nop26_d_sel = 3;
FUNC_XOR:
ctrl_mux4to1_nop26_d_sel = 3;
endcase
OP_XORI:
ctrl_mux4to1_nop26_d_sel = 3;
endcase
end
//Logic for enable signals in Pipe Stage 6
always@(pipereg42_q or pipereg43_q or pipereg44_q[0] or 1'b0)
begin
ctrl_reg_file_c_we = 0;
casex (pipereg42_q)
OP_ADDI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ADDIU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ANDI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_JAL:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LB:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LBU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LH:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LHU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LUI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LW:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ORI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SLTI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SLTIU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SPECIAL:
casex (pipereg43_q)
FUNC_ADD:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_ADDU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_AND:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_JALR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_MFHI:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_MFLO:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_NOR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_OR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLL:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLLV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLT:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLTU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRA:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRAV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRL:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRLV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SUB:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SUBU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_XOR:
ctrl_reg_file_c_we = 1 &~1'b0;
endcase
OP_XORI:
ctrl_reg_file_c_we = 1 &~1'b0;
endcase
end
/********* Stall Network & PipeReg Control ********/
assign stall_out_stage1 = stall_out_stage2|stall_2nd_delayslot;
assign ctrl_pipereg32_en = ~stall_out_stage1;
assign ctrl_pipereg31_en = ~stall_out_stage1;
assign ctrl_pipereg30_en = ~stall_out_stage1;
assign ctrl_pipereg2_en = ~stall_out_stage1;
assign ctrl_pipereg3_en = ~stall_out_stage1;
assign ctrl_pipereg_en = ~stall_out_stage1;
assign ctrl_pipereg5_en = ~stall_out_stage1;
assign ctrl_pipereg4_en = ~stall_out_stage1;
assign ctrl_pipereg11_en = ~stall_out_stage1;
assign ctrl_pipereg1_en = ~stall_out_stage1;
assign ctrl_pipereg46_en = ~stall_out_stage1;
assign stall_out_stage2 = stall_out_stage3|haz_pipereg5_q_pipereg28_q|haz_pipereg4_q_pipereg28_q|haz_pipereg5_q_pipereg27_q|haz_pipereg4_q_pipereg27_q|haz_pipereg4_q_pipereg12_q|haz_pipereg5_q_pipereg12_q;
assign ctrl_pipereg35_en = ~stall_out_stage2;
assign ctrl_pipereg34_en = ~stall_out_stage2;
assign ctrl_pipereg33_en = ~stall_out_stage2;
assign ctrl_pipereg7_en = ~stall_out_stage2;
assign ctrl_pipereg9_en = ~stall_out_stage2;
assign ctrl_pipereg8_en = ~stall_out_stage2;
assign ctrl_pipereg12_en = ~stall_out_stage2;
assign ctrl_pipereg6_en = ~stall_out_stage2;
assign ctrl_pipereg47_en = ~stall_out_stage2;
assign ctrl_pipereg48_en = ~stall_out_stage2;
assign ctrl_pipereg49_en = ~stall_out_stage2;
assign stall_out_stage3 = stall_out_stage4;
assign ctrl_pipereg38_en = ~stall_out_stage3;
assign ctrl_pipereg37_en = ~stall_out_stage3;
assign ctrl_pipereg36_en = ~stall_out_stage3;
assign ctrl_pipereg14_en = ~stall_out_stage3;
assign ctrl_pipereg15_en = ~stall_out_stage3;
assign ctrl_pipereg13_en = ~stall_out_stage3;
assign ctrl_pipereg20_en = ~stall_out_stage3;
assign ctrl_pipereg18_en = ~stall_out_stage3;
assign ctrl_pipereg17_en = ~stall_out_stage3;
assign ctrl_pipereg27_en = ~stall_out_stage3;
assign ctrl_pipereg16_en = ~stall_out_stage3;
assign stall_out_stage4 = stall_out_stage5;
assign ctrl_pipereg41_en = ~stall_out_stage4;
assign ctrl_pipereg40_en = ~stall_out_stage4;
assign ctrl_pipereg39_en = ~stall_out_stage4;
assign ctrl_pipereg28_en = ~stall_out_stage4;
assign ctrl_pipereg23_en = ~stall_out_stage4;
assign stall_out_stage5 = stall_out_stage6;
assign ctrl_pipereg44_en = ~stall_out_stage5;
assign ctrl_pipereg43_en = ~stall_out_stage5;
assign ctrl_pipereg42_en = ~stall_out_stage5;
assign ctrl_pipereg24_en = ~stall_out_stage5;
assign ctrl_pipereg29_en = ~stall_out_stage5;
assign ctrl_pipereg25_en = ~stall_out_stage5;
assign stall_out_stage6 = 1'b0;
assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && pipereg14_q)) & ctrl_ifetch_we);
assign stall_2nd_delayslot = branch_detector_is_branch&has_delayslot;
assign has_delayslot = pipereg46_q|pipereg45_q;
assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn;
assign ctrl_pipereg32_resetn = ~squash_stage1;
assign ctrl_pipereg31_resetn = ~squash_stage1;
assign ctrl_pipereg30_resetn = ~squash_stage1;
assign ctrl_pipereg2_resetn = ~squash_stage1;
assign ctrl_pipereg3_resetn = ~squash_stage1;
assign ctrl_pipereg_resetn = ~squash_stage1;
assign ctrl_pipereg5_resetn = ~squash_stage1;
assign ctrl_pipereg4_resetn = ~squash_stage1;
assign ctrl_pipereg11_resetn = ~squash_stage1;
assign ctrl_pipereg1_resetn = ~squash_stage1;
assign ctrl_pipereg46_resetn = ~squash_stage1;
assign ctrl_pipereg46_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg1_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg11_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg4_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg5_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg3_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg2_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg30_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg31_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_pipereg32_squashn = ~(branch_mispred&~(pipereg45_q&~stall_out_stage1 | pipereg46_q&stall_out_stage1));
assign ctrl_ifetch_squashn = ~(branch_mispred&~(pipereg45_q));
assign squash_stage2 = ((stall_out_stage2&~stall_out_stage3))|~resetn;
assign ctrl_pipereg35_resetn = ~squash_stage2;
assign ctrl_pipereg34_resetn = ~squash_stage2;
assign ctrl_pipereg33_resetn = ~squash_stage2;
assign ctrl_pipereg7_resetn = ~squash_stage2;
assign ctrl_pipereg9_resetn = ~squash_stage2;
assign ctrl_pipereg8_resetn = ~squash_stage2;
assign ctrl_pipereg12_resetn = ~squash_stage2;
assign ctrl_pipereg6_resetn = ~squash_stage2;
assign ctrl_pipereg47_resetn = ~squash_stage2;
assign ctrl_pipereg48_resetn = ~squash_stage2;
assign ctrl_pipereg49_resetn = ~squash_stage2;
assign ctrl_pipereg49_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg48_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg47_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg6_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg12_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg8_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg9_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg7_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg33_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg34_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg35_squashn = ~(branch_mispred&~(pipereg46_q&~stall_out_stage2 | 1&stall_out_stage2));
assign squash_stage3 = ((stall_out_stage3&~stall_out_stage4))|~resetn;
assign ctrl_pipereg38_resetn = ~squash_stage3;
assign ctrl_pipereg37_resetn = ~squash_stage3;
assign ctrl_pipereg36_resetn = ~squash_stage3;
assign ctrl_pipereg14_resetn = ~squash_stage3;
assign ctrl_pipereg15_resetn = ~squash_stage3;
assign ctrl_pipereg13_resetn = ~squash_stage3;
assign ctrl_pipereg20_resetn = ~squash_stage3;
assign ctrl_pipereg18_resetn = ~squash_stage3;
assign ctrl_pipereg17_resetn = ~squash_stage3;
assign ctrl_pipereg27_resetn = ~squash_stage3;
assign ctrl_pipereg16_resetn = ~squash_stage3;
assign ctrl_pipereg16_squashn = ~(0);
assign ctrl_pipereg27_squashn = ~(0);
assign ctrl_pipereg17_squashn = ~(0);
assign ctrl_pipereg18_squashn = ~(0);
assign ctrl_pipereg20_squashn = ~(0);
assign ctrl_pipereg13_squashn = ~(0);
assign ctrl_pipereg15_squashn = ~(0);
assign ctrl_pipereg14_squashn = ~(0);
assign ctrl_pipereg36_squashn = ~(0);
assign ctrl_pipereg37_squashn = ~(0);
assign ctrl_pipereg38_squashn = ~(0);
assign squash_stage4 = ((stall_out_stage4&~stall_out_stage5))|~resetn;
assign ctrl_pipereg41_resetn = ~squash_stage4;
assign ctrl_pipereg40_resetn = ~squash_stage4;
assign ctrl_pipereg39_resetn = ~squash_stage4;
assign ctrl_pipereg28_resetn = ~squash_stage4;
assign ctrl_pipereg23_resetn = ~squash_stage4;
assign ctrl_pipereg23_squashn = ~(0);
assign ctrl_pipereg28_squashn = ~(0);
assign ctrl_pipereg39_squashn = ~(0);
assign ctrl_pipereg40_squashn = ~(0);
assign ctrl_pipereg41_squashn = ~(0);
assign squash_stage5 = ((stall_out_stage5&~stall_out_stage6))|~resetn;
assign ctrl_pipereg44_resetn = ~squash_stage5;
assign ctrl_pipereg43_resetn = ~squash_stage5;
assign ctrl_pipereg42_resetn = ~squash_stage5;
assign ctrl_pipereg24_resetn = ~squash_stage5;
assign ctrl_pipereg29_resetn = ~squash_stage5;
assign ctrl_pipereg25_resetn = ~squash_stage5;
assign ctrl_pipereg25_squashn = ~(0);
assign ctrl_pipereg29_squashn = ~(0);
assign ctrl_pipereg24_squashn = ~(0);
assign ctrl_pipereg42_squashn = ~(0);
assign ctrl_pipereg43_squashn = ~(0);
assign ctrl_pipereg44_squashn = ~(0);
assign squash_stage6 = ((stall_out_stage6&~1'b0))|~resetn;
/****************************** Datapath **************************/
/******************** Hazard Detection Logic ***********************/
assign haz_pipereg5_q_pipereg29_q = (pipereg5_q==pipereg29_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg29_q = (pipereg4_q==pipereg29_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg28_q = (pipereg5_q==pipereg28_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg28_q = (pipereg4_q==pipereg28_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg27_q = (pipereg5_q==pipereg27_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg27_q = (pipereg4_q==pipereg27_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg12_q = (pipereg5_q==pipereg12_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg12_q = (pipereg4_q==pipereg12_q) && (|pipereg4_q);
/*************** DATAPATH COMPONENTS **************/
addersub addersub (
.opB(pipereg16_q),
.opA(mux2to1_addersub_opA_out),
.op(ctrl_addersub_op),
.result_slt(addersub_result_slt),
.result(addersub_result));
defparam
addersub.WIDTH=32;
shifter shifter (
.clk(clk),
.resetn(resetn),
.sa(pipereg18_q),
.opB(pipereg16_q),
.op(ctrl_shifter_op),
.result(shifter_result));
defparam
shifter.WIDTH=32;
mul mul (
.clk(clk),
.resetn(resetn),
.opB(pipereg20_q),
.opA(pipereg17_q),
.op(ctrl_mul_op),
.lo(mul_lo),
.hi(mul_hi));
defparam
mul.WIDTH=32;
data_mem data_mem (
.clk(clk),
.resetn(resetn),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe),
.d_address(addersub_result),
.d_writedata(pipereg20_q),
.op(ctrl_data_mem_op),
.en(ctrl_data_mem_en),
.d_loadresult(data_mem_d_loadresult));
logic_unit logic_unit (
.opB(pipereg16_q),
.opA(pipereg17_q),
.op(ctrl_logic_unit_op),
.result(logic_unit_result));
defparam
logic_unit.WIDTH=32;
ifetch ifetch (
.clk(clk),
.resetn(resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe),
.load(pipereg14_q),
.load_data(pipereg13_q),
.op(ctrl_ifetch_op),
.we(ctrl_ifetch_we),
.squashn(ctrl_ifetch_squashn),
.en(ctrl_ifetch_en),
.pc_out(ifetch_pc_out),
.instr(ifetch_instr),
.opcode(ifetch_opcode),
.func(ifetch_func),
.rs(ifetch_rs),
.rt(ifetch_rt),
.rd(ifetch_rd),
.instr_index(ifetch_instr_index),
.offset(ifetch_offset),
.sa(ifetch_sa),
.next_pc(ifetch_next_pc));
signext16 signext16 (
.in(pipereg1_q),
.out(signext16_out));
reg_file reg_file (
.clk(clk),
.resetn(resetn),
.c_writedatain(nop26_q),
.c_reg(pipereg29_q),
.b_reg(pipereg5_q),
.a_reg(pipereg4_q),
.c_we(ctrl_reg_file_c_we),
.b_en(ctrl_reg_file_b_en),
.a_en(ctrl_reg_file_a_en),
.b_readdataout(reg_file_b_readdataout),
.a_readdataout(reg_file_a_readdataout));
pcadder pcadder (
.offset(pipereg6_q),
.pc(pipereg9_q),
.result(pcadder_result));
lo_reg lo_reg (
.clk(clk),
.resetn(resetn),
.d(mul_lo),
.en(ctrl_lo_reg_en),
.q(lo_reg_q));
defparam
lo_reg.WIDTH=32;
const const21 (
.out(const21_out));
defparam
const21.WIDTH=32,
const21.VAL=0;
merge26lo merge26lo (
.in2(pipereg7_q),
.in1(pipereg9_q),
.out(merge26lo_out));
branchresolve branchresolve (
.rt(nop19_q),
.rs(nop_q),
.en(ctrl_branchresolve_en),
.eqz(branchresolve_eqz),
.gez(branchresolve_gez),
.gtz(branchresolve_gtz),
.lez(branchresolve_lez),
.ltz(branchresolve_ltz),
.ne(branchresolve_ne),
.eq(branchresolve_eq));
defparam
branchresolve.WIDTH=32;
hi_reg hi_reg (
.clk(clk),
.resetn(resetn),
.d(mul_hi),
.en(ctrl_hi_reg_en),
.q(hi_reg_q));
defparam
hi_reg.WIDTH=32;
const const (
.out(const_out));
defparam
const.WIDTH=32,
const.VAL=31;
const const22 (
.out(const22_out));
defparam
const22.WIDTH=32,
const22.VAL=16;
pipereg pipereg5 (
.clk(clk),
.resetn(ctrl_pipereg5_resetn),
.d(zeroer_q),
.squashn(ctrl_pipereg5_squashn),
.en(ctrl_pipereg5_en),
.q(pipereg5_q));
defparam
pipereg5.WIDTH=5;
pipereg pipereg4 (
.clk(clk),
.resetn(ctrl_pipereg4_resetn),
.d(zeroer0_q),
.squashn(ctrl_pipereg4_squashn),
.en(ctrl_pipereg4_en),
.q(pipereg4_q));
defparam
pipereg4.WIDTH=5;
pipereg pipereg1 (
.clk(clk),
.resetn(ctrl_pipereg1_resetn),
.d(ifetch_offset),
.squashn(ctrl_pipereg1_squashn),
.en(ctrl_pipereg1_en),
.q(pipereg1_q));
defparam
pipereg1.WIDTH=16;
pipereg pipereg11 (
.clk(clk),
.resetn(ctrl_pipereg11_resetn),
.d(zeroer10_q),
.squashn(ctrl_pipereg11_squashn),
.en(ctrl_pipereg11_en),
.q(pipereg11_q));
defparam
pipereg11.WIDTH=5;
pipereg pipereg2 (
.clk(clk),
.resetn(ctrl_pipereg2_resetn),
.d(ifetch_instr_index),
.squashn(ctrl_pipereg2_squashn),
.en(ctrl_pipereg2_en),
.q(pipereg2_q));
defparam
pipereg2.WIDTH=26;
pipereg pipereg (
.clk(clk),
.resetn(ctrl_pipereg_resetn),
.d(ifetch_sa),
.squashn(ctrl_pipereg_squashn),
.en(ctrl_pipereg_en),
.q(pipereg_q));
defparam
pipereg.WIDTH=5;
pipereg pipereg6 (
.clk(clk),
.resetn(ctrl_pipereg6_resetn),
.d(mux2to1_pipereg6_d_out),
.squashn(ctrl_pipereg6_squashn),
.en(ctrl_pipereg6_en),
.q(pipereg6_q));
defparam
pipereg6.WIDTH=32;
pipereg pipereg3 (
.clk(clk),
.resetn(ctrl_pipereg3_resetn),
.d(ifetch_pc_out),
.squashn(ctrl_pipereg3_squashn),
.en(ctrl_pipereg3_en),
.q(pipereg3_q));
defparam
pipereg3.WIDTH=32;
pipereg pipereg7 (
.clk(clk),
.resetn(ctrl_pipereg7_resetn),
.d(pipereg2_q),
.squashn(ctrl_pipereg7_squashn),
.en(ctrl_pipereg7_en),
.q(pipereg7_q));
defparam
pipereg7.WIDTH=26;
pipereg pipereg9 (
.clk(clk),
.resetn(ctrl_pipereg9_resetn),
.d(pipereg3_q),
.squashn(ctrl_pipereg9_squashn),
.en(ctrl_pipereg9_en),
.q(pipereg9_q));
defparam
pipereg9.WIDTH=32;
pipereg pipereg8 (
.clk(clk),
.resetn(ctrl_pipereg8_resetn),
.d(pipereg_q),
.squashn(ctrl_pipereg8_squashn),
.en(ctrl_pipereg8_en),
.q(pipereg8_q));
defparam
pipereg8.WIDTH=5;
pipereg pipereg17 (
.clk(clk),
.resetn(ctrl_pipereg17_resetn),
.d(nop_q),
.squashn(ctrl_pipereg17_squashn),
.en(ctrl_pipereg17_en),
.q(pipereg17_q));
defparam
pipereg17.WIDTH=32;
pipereg pipereg20 (
.clk(clk),
.resetn(ctrl_pipereg20_resetn),
.d(nop19_q),
.squashn(ctrl_pipereg20_squashn),
.en(ctrl_pipereg20_en),
.q(pipereg20_q));
defparam
pipereg20.WIDTH=32;
pipereg pipereg18 (
.clk(clk),
.resetn(ctrl_pipereg18_resetn),
.d(mux3to1_pipereg18_d_out),
.squashn(ctrl_pipereg18_squashn),
.en(ctrl_pipereg18_en),
.q(pipereg18_q));
defparam
pipereg18.WIDTH=32;
pipereg pipereg16 (
.clk(clk),
.resetn(ctrl_pipereg16_resetn),
.d(mux3to1_pipereg16_d_out),
.squashn(ctrl_pipereg16_squashn),
.en(ctrl_pipereg16_en),
.q(pipereg16_q));
defparam
pipereg16.WIDTH=32;
pipereg pipereg15 (
.clk(clk),
.resetn(ctrl_pipereg15_resetn),
.d(fakedelay_q),
.squashn(ctrl_pipereg15_squashn),
.en(ctrl_pipereg15_en),
.q(pipereg15_q));
defparam
pipereg15.WIDTH=32;
pipereg pipereg13 (
.clk(clk),
.resetn(ctrl_pipereg13_resetn),
.d(mux3to1_pipereg13_d_out),
.squashn(ctrl_pipereg13_squashn),
.en(ctrl_pipereg13_en),
.q(pipereg13_q));
defparam
pipereg13.WIDTH=32;
pipereg pipereg14 (
.clk(clk),
.resetn(ctrl_pipereg14_resetn),
.d(mux6to1_pipereg14_d_out),
.squashn(ctrl_pipereg14_squashn),
.en(ctrl_pipereg14_en),
.q(pipereg14_q));
defparam
pipereg14.WIDTH=32;
pipereg pipereg23 (
.clk(clk),
.resetn(ctrl_pipereg23_resetn),
.d(mux3to1_pipereg23_d_out),
.squashn(ctrl_pipereg23_squashn),
.en(ctrl_pipereg23_en),
.q(pipereg23_q));
defparam
pipereg23.WIDTH=32;
pipereg pipereg25 (
.clk(clk),
.resetn(ctrl_pipereg25_resetn),
.d(mux2to1_pipereg25_d_out),
.squashn(ctrl_pipereg25_squashn),
.en(ctrl_pipereg25_en),
.q(pipereg25_q));
defparam
pipereg25.WIDTH=32;
pipereg pipereg24 (
.clk(clk),
.resetn(ctrl_pipereg24_resetn),
.d(data_mem_d_loadresult),
.squashn(ctrl_pipereg24_squashn),
.en(ctrl_pipereg24_en),
.q(pipereg24_q));
defparam
pipereg24.WIDTH=32;
pipereg pipereg12 (
.clk(clk),
.resetn(ctrl_pipereg12_resetn),
.d(pipereg11_q),
.squashn(ctrl_pipereg12_squashn),
.en(ctrl_pipereg12_en),
.q(pipereg12_q));
defparam
pipereg12.WIDTH=5;
pipereg pipereg27 (
.clk(clk),
.resetn(ctrl_pipereg27_resetn),
.d(pipereg12_q),
.squashn(ctrl_pipereg27_squashn),
.en(ctrl_pipereg27_en),
.q(pipereg27_q));
defparam
pipereg27.WIDTH=5;
pipereg pipereg28 (
.clk(clk),
.resetn(ctrl_pipereg28_resetn),
.d(pipereg27_q),
.squashn(ctrl_pipereg28_squashn),
.en(ctrl_pipereg28_en),
.q(pipereg28_q));
defparam
pipereg28.WIDTH=5;
pipereg pipereg47 (
.clk(clk),
.resetn(ctrl_pipereg47_resetn),
.d(nop26_q),
.squashn(ctrl_pipereg47_squashn),
.en(ctrl_pipereg47_en),
.q(pipereg47_q));
defparam
pipereg47.WIDTH=32;
pipereg pipereg29 (
.clk(clk),
.resetn(ctrl_pipereg29_resetn),
.d(pipereg28_q),
.squashn(ctrl_pipereg29_squashn),
.en(ctrl_pipereg29_en),
.q(pipereg29_q));
defparam
pipereg29.WIDTH=5;
nop nop19 (
.d(mux2to1_nop19_d_out),
.q(nop19_q));
defparam
nop19.WIDTH=32;
nop nop26 (
.d(mux4to1_nop26_d_out),
.q(nop26_q));
defparam
nop26.WIDTH=32;
zeroer zeroer0 (
.d(ifetch_rs),
.en(ctrl_zeroer0_en),
.q(zeroer0_q));
defparam
zeroer0.WIDTH=5;
zeroer zeroer (
.d(ifetch_rt),
.en(ctrl_zeroer_en),
.q(zeroer_q));
defparam
zeroer.WIDTH=5;
zeroer zeroer10 (
.d(mux3to1_zeroer10_d_out),
.en(ctrl_zeroer10_en),
.q(zeroer10_q));
defparam
zeroer10.WIDTH=5;
fakedelay fakedelay (
.clk(clk),
.d(pipereg3_q),
.q(fakedelay_q));
defparam
fakedelay.WIDTH=32;
nop nop (
.d(mux2to1_nop_d_out),
.q(nop_q));
defparam
nop.WIDTH=32;
// Multiplexor mux2to1_addersub_opA instantiation
assign mux2to1_addersub_opA_out =
(ctrl_mux2to1_addersub_opA_sel==1) ? pipereg15_q :
pipereg17_q;
// Multiplexor mux2to1_pipereg6_d instantiation
assign mux2to1_pipereg6_d_out =
(ctrl_mux2to1_pipereg6_d_sel==1) ? pipereg1_q :
signext16_out;
// Multiplexor mux3to1_pipereg16_d instantiation
assign mux3to1_pipereg16_d_out =
(ctrl_mux3to1_pipereg16_d_sel==2) ? pipereg6_q :
(ctrl_mux3to1_pipereg16_d_sel==1) ? nop19_q :
const21_out;
// Multiplexor mux3to1_pipereg18_d instantiation
assign mux3to1_pipereg18_d_out =
(ctrl_mux3to1_pipereg18_d_sel==2) ? nop_q :
(ctrl_mux3to1_pipereg18_d_sel==1) ? const22_out :
pipereg8_q;
// Multiplexor mux6to1_pipereg14_d instantiation
assign mux6to1_pipereg14_d_out =
(ctrl_mux6to1_pipereg14_d_sel==5) ? branchresolve_eq :
(ctrl_mux6to1_pipereg14_d_sel==4) ? branchresolve_ne :
(ctrl_mux6to1_pipereg14_d_sel==3) ? branchresolve_lez :
(ctrl_mux6to1_pipereg14_d_sel==2) ? branchresolve_ltz :
(ctrl_mux6to1_pipereg14_d_sel==1) ? branchresolve_gez :
branchresolve_gtz;
// Multiplexor mux3to1_pipereg13_d instantiation
assign mux3to1_pipereg13_d_out =
(ctrl_mux3to1_pipereg13_d_sel==2) ? pcadder_result :
(ctrl_mux3to1_pipereg13_d_sel==1) ? merge26lo_out :
nop_q;
// Multiplexor mux3to1_pipereg23_d instantiation
assign mux3to1_pipereg23_d_out =
(ctrl_mux3to1_pipereg23_d_sel==2) ? addersub_result :
(ctrl_mux3to1_pipereg23_d_sel==1) ? addersub_result_slt :
logic_unit_result;
// Multiplexor mux2to1_pipereg25_d instantiation
assign mux2to1_pipereg25_d_out =
(ctrl_mux2to1_pipereg25_d_sel==1) ? pipereg23_q :
shifter_result;
// Multiplexor mux4to1_nop26_d instantiation
assign mux4to1_nop26_d_out =
(ctrl_mux4to1_nop26_d_sel==3) ? pipereg25_q :
(ctrl_mux4to1_nop26_d_sel==2) ? pipereg24_q :
(ctrl_mux4to1_nop26_d_sel==1) ? hi_reg_q :
lo_reg_q;
// Multiplexor mux3to1_zeroer10_d instantiation
assign mux3to1_zeroer10_d_out =
(ctrl_mux3to1_zeroer10_d_sel==2) ? ifetch_rt :
(ctrl_mux3to1_zeroer10_d_sel==1) ? ifetch_rd :
const_out;
pipereg pipereg30 (
.clk(clk),
.resetn(ctrl_pipereg30_resetn),
.d(ifetch_opcode),
.squashn(ctrl_pipereg30_squashn),
.en(ctrl_pipereg30_en),
.q(pipereg30_q));
defparam
pipereg30.WIDTH=6;
pipereg pipereg33 (
.clk(clk),
.resetn(ctrl_pipereg33_resetn),
.d(pipereg30_q),
.squashn(ctrl_pipereg33_squashn),
.en(ctrl_pipereg33_en),
.q(pipereg33_q));
defparam
pipereg33.WIDTH=6;
pipereg pipereg34 (
.clk(clk),
.resetn(ctrl_pipereg34_resetn),
.d(pipereg31_q),
.squashn(ctrl_pipereg34_squashn),
.en(ctrl_pipereg34_en),
.q(pipereg34_q));
defparam
pipereg34.WIDTH=6;
pipereg pipereg35 (
.clk(clk),
.resetn(ctrl_pipereg35_resetn),
.d(pipereg32_q),
.squashn(ctrl_pipereg35_squashn),
.en(ctrl_pipereg35_en),
.q(pipereg35_q));
defparam
pipereg35.WIDTH=5;
pipereg pipereg36 (
.clk(clk),
.resetn(ctrl_pipereg36_resetn),
.d(pipereg33_q),
.squashn(ctrl_pipereg36_squashn),
.en(ctrl_pipereg36_en),
.q(pipereg36_q));
defparam
pipereg36.WIDTH=6;
pipereg pipereg37 (
.clk(clk),
.resetn(ctrl_pipereg37_resetn),
.d(pipereg34_q),
.squashn(ctrl_pipereg37_squashn),
.en(ctrl_pipereg37_en),
.q(pipereg37_q));
defparam
pipereg37.WIDTH=6;
pipereg pipereg38 (
.clk(clk),
.resetn(ctrl_pipereg38_resetn),
.d(pipereg35_q),
.squashn(ctrl_pipereg38_squashn),
.en(ctrl_pipereg38_en),
.q(pipereg38_q));
defparam
pipereg38.WIDTH=5;
pipereg pipereg41 (
.clk(clk),
.resetn(ctrl_pipereg41_resetn),
.d(pipereg38_q),
.squashn(ctrl_pipereg41_squashn),
.en(ctrl_pipereg41_en),
.q(pipereg41_q));
defparam
pipereg41.WIDTH=5;
pipereg pipereg40 (
.clk(clk),
.resetn(ctrl_pipereg40_resetn),
.d(pipereg37_q),
.squashn(ctrl_pipereg40_squashn),
.en(ctrl_pipereg40_en),
.q(pipereg40_q));
defparam
pipereg40.WIDTH=6;
pipereg pipereg39 (
.clk(clk),
.resetn(ctrl_pipereg39_resetn),
.d(pipereg36_q),
.squashn(ctrl_pipereg39_squashn),
.en(ctrl_pipereg39_en),
.q(pipereg39_q));
defparam
pipereg39.WIDTH=6;
pipereg pipereg31 (
.clk(clk),
.resetn(ctrl_pipereg31_resetn),
.d(ifetch_func),
.squashn(ctrl_pipereg31_squashn),
.en(ctrl_pipereg31_en),
.q(pipereg31_q));
defparam
pipereg31.WIDTH=6;
pipereg pipereg32 (
.clk(clk),
.resetn(ctrl_pipereg32_resetn),
.d(ifetch_rt),
.squashn(ctrl_pipereg32_squashn),
.en(ctrl_pipereg32_en),
.q(pipereg32_q));
defparam
pipereg32.WIDTH=5;
pipereg pipereg42 (
.clk(clk),
.resetn(ctrl_pipereg42_resetn),
.d(pipereg39_q),
.squashn(ctrl_pipereg42_squashn),
.en(ctrl_pipereg42_en),
.q(pipereg42_q));
defparam
pipereg42.WIDTH=6;
pipereg pipereg43 (
.clk(clk),
.resetn(ctrl_pipereg43_resetn),
.d(pipereg40_q),
.squashn(ctrl_pipereg43_squashn),
.en(ctrl_pipereg43_en),
.q(pipereg43_q));
defparam
pipereg43.WIDTH=6;
pipereg pipereg44 (
.clk(clk),
.resetn(ctrl_pipereg44_resetn),
.d(pipereg41_q),
.squashn(ctrl_pipereg44_squashn),
.en(ctrl_pipereg44_en),
.q(pipereg44_q));
defparam
pipereg44.WIDTH=5;
branch_detector branch_detector (
.func(ifetch_func),
.opcode(ifetch_opcode),
.is_branch(branch_detector_is_branch));
pipereg pipereg45 (
.clk(clk),
.resetn(resetn),
.d(branch_detector_is_branch),
.squashn(~branch_mispred),
.en(~stall_out_stage1),
.q(pipereg45_q));
defparam
pipereg45.WIDTH=1;
pipereg pipereg46 (
.clk(clk),
.resetn(ctrl_pipereg46_resetn),
.d(pipereg45_q),
.squashn(ctrl_pipereg46_squashn),
.en(ctrl_pipereg46_en),
.q(pipereg46_q));
defparam
pipereg46.WIDTH=1;
// Multiplexor mux2to1_nop_d instantiation
assign mux2to1_nop_d_out =
(pipereg48_q==1) ? pipereg47_q :
reg_file_a_readdataout;
pipereg pipereg48 (
.clk(clk),
.resetn(ctrl_pipereg48_resetn),
.d(haz_pipereg4_q_pipereg29_q),
.squashn(ctrl_pipereg48_squashn),
.en(ctrl_pipereg48_en),
.q(pipereg48_q));
defparam
pipereg48.WIDTH=1;
pipereg pipereg49 (
.clk(clk),
.resetn(ctrl_pipereg49_resetn),
.d(haz_pipereg5_q_pipereg29_q),
.squashn(ctrl_pipereg49_squashn),
.en(ctrl_pipereg49_en),
.q(pipereg49_q));
defparam
pipereg49.WIDTH=1;
// Multiplexor mux2to1_nop19_d instantiation
assign mux2to1_nop19_d_out =
(pipereg49_q==1) ? pipereg47_q :
reg_file_b_readdataout;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Manages the interrupt vector and sends interrupts.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTR_IDLE 2'd0
`define S_INTR_INTR 2'd1
`define S_INTR_CLR_0 2'd2
`define S_INTR_CLR_1 2'd3
`timescale 1ns/1ns
module interrupt #(
parameter C_NUM_CHNL = 4'd12
)
(
input CLK,
input RST,
input [C_NUM_CHNL-1:0] RX_SG_BUF_RECVD, // The scatter gather data for a rx_port transaction has been read
input [C_NUM_CHNL-1:0] RX_TXN_DONE, // The rx_port transaction is done
input [C_NUM_CHNL-1:0] TX_TXN, // New tx_port transaction
input [C_NUM_CHNL-1:0] TX_SG_BUF_RECVD, // The scatter gather data for a tx_port transaction has been read
input [C_NUM_CHNL-1:0] TX_TXN_DONE, // The tx_port transaction is done
input VECT_0_RST, // Interrupt vector 0 reset
input VECT_1_RST, // Interrupt vector 1 reset
input [31:0] VECT_RST, // Interrupt vector reset value
output [31:0] VECT_0, // Interrupt vector 0
output [31:0] VECT_1, // Interrupt vector 1
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [1:0] rState=0;
reg [31:0] rVect0=0;
reg [31:0] rVect1=0;
wire [31:0] wVect0;
wire [31:0] wVect1;
wire wIntr = (rState == `S_INTR_INTR);
wire wIntrDone;
assign VECT_0 = rVect0;
assign VECT_1 = rVect1;
// Align the input signals to the interrupt vector.
// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:
// [ 0] TX_TXN for channel 0 in VECT_0, channel 6 in VECT_1
// [ 1] TX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
// [ 2] TX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
// [ 3] RX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
// [ 4] RX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
// ...
// [25] TX_TXN for channel 5 in VECT_0, channel 11 in VECT_1
// [26] TX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
// [27] TX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
// [28] RX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
// [29] RX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin: vectMap
if (i < 6) begin : vectMap0
assign wVect0[(5*i)+0] = TX_TXN[i];
assign wVect0[(5*i)+1] = TX_SG_BUF_RECVD[i];
assign wVect0[(5*i)+2] = TX_TXN_DONE[i];
assign wVect0[(5*i)+3] = RX_SG_BUF_RECVD[i];
assign wVect0[(5*i)+4] = RX_TXN_DONE[i];
end
else begin : vectMap1
assign wVect1[(5*(i-6))+0] = TX_TXN[i];
assign wVect1[(5*(i-6))+1] = TX_SG_BUF_RECVD[i];
assign wVect1[(5*(i-6))+2] = TX_TXN_DONE[i];
assign wVect1[(5*(i-6))+3] = RX_SG_BUF_RECVD[i];
assign wVect1[(5*(i-6))+4] = RX_TXN_DONE[i];
end
end
for (i = C_NUM_CHNL; i < 12; i = i + 1) begin: vectZero
if (i < 6) begin : vectZero0
assign wVect0[(5*i)+0] = 1'b0;
assign wVect0[(5*i)+1] = 1'b0;
assign wVect0[(5*i)+2] = 1'b0;
assign wVect0[(5*i)+3] = 1'b0;
assign wVect0[(5*i)+4] = 1'b0;
end
else begin : vectZero1
assign wVect1[(5*(i-6))+0] = 1'b0;
assign wVect1[(5*(i-6))+1] = 1'b0;
assign wVect1[(5*(i-6))+2] = 1'b0;
assign wVect1[(5*(i-6))+3] = 1'b0;
assign wVect1[(5*(i-6))+4] = 1'b0;
end
end
assign wVect0[30] = 1'b0;
assign wVect0[31] = 1'b0;
assign wVect1[30] = 1'b0;
assign wVect1[31] = 1'b0;
endgenerate
// Interrupt controller
interrupt_controller intrCtlr (
.CLK(CLK),
.RST(RST),
.INTR(wIntr),
.INTR_LEGACY_CLR(INTR_LEGACY_CLR),
.INTR_DONE(wIntrDone),
.CFG_INTERRUPT_ASSERT(),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST)
);
// Update the interrupt vector when new signals come in (pulse in) and on reset.
always @(posedge CLK) begin
if (RST) begin
rVect0 <= #1 0;
rVect1 <= #1 0;
end
else begin
if (VECT_0_RST) begin
rVect0 <= #1 (wVect0 | (rVect0 & ~VECT_RST));
rVect1 <= #1 (wVect1 | rVect1);
end
else if (VECT_1_RST) begin
rVect0 <= #1 (wVect0 | rVect0);
rVect1 <= #1 (wVect1 | (rVect1 & ~VECT_RST));
end
else begin
rVect0 <= #1 (wVect0 | rVect0);
rVect1 <= #1 (wVect1 | rVect1);
end
end
end
// Fire the interrupt when we have a non-zero vector.
always @(posedge CLK) begin
if (RST) begin
rState <= #1 `S_INTR_IDLE;
end
else begin
case (rState)
`S_INTR_IDLE : rState <= #1 ((rVect0 | rVect1) == 0 ? `S_INTR_IDLE : `S_INTR_INTR);
`S_INTR_INTR : rState <= #1 (wIntrDone ? `S_INTR_CLR_0 : `S_INTR_INTR);
`S_INTR_CLR_0 : rState <= #1 (VECT_0_RST ? (C_NUM_CHNL > 6 ? `S_INTR_CLR_1 : `S_INTR_IDLE) : `S_INTR_CLR_0);
`S_INTR_CLR_1 : rState <= #1 (VECT_1_RST ? `S_INTR_IDLE : `S_INTR_CLR_1);
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busreceiver (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ed Lander.
// SPDX-License-Identifier: CC0-1.0
// verilator lint_off WIDTH
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
initial begin
p1 = 8'h01;
p2 = 8'h02;
p3 = 8'h03;
end
parameter int param1 = 8'h11;
parameter int param2 = 8'h12;
parameter int param3 = 8'h13;
targetmod i_targetmod (/*AUTOINST*/
// Inputs
.clk (clk));
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
//param1 not over-riden (as mycheck) (=> 0x31)
//param2 explicitly bound to targetmod value (=> 0x22)
//param3 explicitly bound to top value (=> 0x13)
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
//p2 explictly bound to targetmod (=> 0x05)
//p3 explictly bound to top (=> 0x03)
// Alternative unsupported form is i_targetmod
bind targetmod mycheck
#(
.param2(param2),
.param3(param3)
)
i_mycheck (.p2(p2), .p3(p3), .*);
endmodule
module targetmod (input clk);
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
parameter int param1 = 8'h21;
parameter int param2 = 8'h22;
parameter int param3 = 8'h23;
initial begin
p1 = 8'h04;
p2 = 8'h05;
p3 = 8'h06;
end
endmodule
module mycheck (/*AUTOARG*/
// Inputs
clk, p1, p2, p3
);
input clk;
input [7:0] p1;
input [7:0] p2;
input [7:0] p3;
parameter int param1 = 8'h31;
parameter int param2 = 8'h32;
parameter int param3 = 8'h33;
always @ (posedge clk) begin
`checkh(param1,8'h31);
`checkh(param2,8'h22);
`checkh(param3,8'h23);
`checkh(p1,8'h04);
`checkh(p2,8'h05);
`checkh(p3,8'h06);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverybkb_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverybkb_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverybkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverybkb_ram contact_discoverybkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_dctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_dctl (/*AUTOARG*/
// Outputs
que_margin_reg, readqbank0vld0, readqbank0vld1, readqbank0vld2,
readqbank0vld3, writeqbank0vld0, writeqbank0vld1, writeqbank0vld2,
writeqbank0vld3, readqbank0vld4, readqbank0vld5, readqbank0vld6,
readqbank0vld7, writeqbank0vld4, writeqbank0vld5, writeqbank0vld6,
writeqbank0vld7, que_wr_req, dp_data_in, dp_ecc_in, que_scrb_addr,
dram_fail_over_mode, que_wr_entry_free, config_reg,
que_rank1_present, que_addr_bank_low_sel, que_eight_bank_mode,
que_mem_addr, dram_io_data_out, dram_io_addr, dram_io_bank,
dram_io_cas_l, dram_io_cke, dram_io_cs_l, dram_io_drive_data,
dram_io_drive_enable, dram_io_ras_l, dram_io_write_en_l,
dram_io_pad_enable, dram_io_clk_enable, dram_io_pad_clk_inv,
dram_io_ptr_clk_inv, dram_io_channel_disabled, que_l2if_ack_vld,
que_l2if_nack_vld, que_l2if_data, que_dram_clk_toggle,
dp_data_valid, que_l2if_send_info, dram_local_pt_opened_bank,
que_max_banks_open_valid, que_max_banks_open, que_max_time_valid,
que_int_wr_que_inv_info, que_ras_int_picked, que_b0_data_addr,
que_l2req_valids, que_b0_addr_picked, que_b0_id_picked,
que_b0_index_picked, que_b0_cmd_picked, que_channel_picked,
que_int_pos, que_channel_disabled, dp_data_mecc0, dp_data_mecc1,
dp_data_mecc2, dp_data_mecc3, dp_data_mecc4, dp_data_mecc5,
dp_data_mecc6, dp_data_mecc7, que_cas_int_picked,
que_wr_cas_ch01_picked, que_mux_write_en,
// Inputs
clk, rst_l, arst_l, sehold, l2if_que_selfrsh, dram_dbginit_l,
l2if_data_mecc0, l2if_data_mecc1, l2if_data_mecc2,
l2if_data_mecc3, l2if_data_mecc4, l2if_data_mecc5,
l2if_data_mecc6, l2if_data_mecc7, l2if_rd_id, l2if_rd_addr,
l2if_wr_addr, l2if_wr_req, l2if_rd_req, l2if_dbg_trig_en,
l2if_data_wr_addr, l2if_err_addr_reg, l2if_err_sts_reg,
l2if_err_loc, l2if_err_cnt, que_mem_data, io_dram_data_valid,
io_dram_data_in, io_dram_ecc_in, l2if_que_rd_req_vld,
l2if_que_wr_req_vld, l2if_que_addr, l2if_que_data,
l2if_scrb_data_en, l2if_scrb_data, l2if_scrb_ecc,
pt_ch_blk_new_openbank, pt_max_banks_open, pt_max_time,
ch0_que_ras_int_picked, ch0_que_b0_data_addr,
ch0_que_channel_picked, ch1_que_l2req_valids,
ch1_que_b0_addr_picked, ch1_que_b0_id_picked,
ch1_que_b0_index_picked, ch1_que_b0_cmd_picked,
other_que_channel_disabled, ch1_que_int_wr_que_inv_info,
other_que_pos, ch1_que_mem_data, ch1_dp_data_mecc0,
ch1_dp_data_mecc1, ch1_dp_data_mecc2, ch1_dp_data_mecc3,
ch1_dp_data_mecc4, ch1_dp_data_mecc5, ch1_dp_data_mecc6,
ch1_dp_data_mecc7, ch0_que_cas_int_picked,
ch0_que_wr_cas_ch01_picked, ch0_que_mux_write_en
);
input clk;
input rst_l;
input arst_l;
input sehold;
input l2if_que_selfrsh;
input dram_dbginit_l;
output [4:0] que_margin_reg;
// CPU CLK DOMAIN INTERFACE
input [3:0] l2if_data_mecc0;
input [3:0] l2if_data_mecc1;
input [3:0] l2if_data_mecc2;
input [3:0] l2if_data_mecc3;
input [3:0] l2if_data_mecc4;
input [3:0] l2if_data_mecc5;
input [3:0] l2if_data_mecc6;
input [3:0] l2if_data_mecc7;
input [2:0] l2if_rd_id;
input [35:0] l2if_rd_addr;
input [35:0] l2if_wr_addr;
input l2if_wr_req;
input l2if_rd_req;
input l2if_dbg_trig_en;
output readqbank0vld0;
output readqbank0vld1;
output readqbank0vld2;
output readqbank0vld3;
output writeqbank0vld0;
output writeqbank0vld1;
output writeqbank0vld2;
output writeqbank0vld3;
output readqbank0vld4;
output readqbank0vld5;
output readqbank0vld6;
output readqbank0vld7;
output writeqbank0vld4;
output writeqbank0vld5;
output writeqbank0vld6;
output writeqbank0vld7;
output que_wr_req;
output [255:0] dp_data_in;
output [31:0] dp_ecc_in;
input [2:0] l2if_data_wr_addr;
output [32:0] que_scrb_addr;
input [35:0] l2if_err_addr_reg;
input [22:0] l2if_err_sts_reg;
output dram_fail_over_mode;
output [3:0] que_wr_entry_free;
input [35:0] l2if_err_loc;
input [17:0] l2if_err_cnt;
output [8:0] config_reg;
output que_rank1_present;
output que_addr_bank_low_sel;
output que_eight_bank_mode;
// MEMORY INTERFACE
input [255:0] que_mem_data;
output [4:0] que_mem_addr;
// FROM THE PADS
input io_dram_data_valid;
input [255:0] io_dram_data_in;
input [31:0] io_dram_ecc_in;
// TO THE PADS
output [287:0] dram_io_data_out;
output [14:0] dram_io_addr;
output [2:0] dram_io_bank;
output dram_io_cas_l;
output dram_io_cke;
output [3:0] dram_io_cs_l;
output dram_io_drive_data;
output dram_io_drive_enable;
output dram_io_ras_l;
output dram_io_write_en_l;
output dram_io_pad_enable;
output dram_io_clk_enable;
output dram_io_pad_clk_inv;
output [4:0] dram_io_ptr_clk_inv;
output dram_io_channel_disabled;
// FROM L2if UCB
input l2if_que_rd_req_vld;
input l2if_que_wr_req_vld;
input [31:0] l2if_que_addr;
input [63:0] l2if_que_data;
// TO l2if UCB
output que_l2if_ack_vld;
output que_l2if_nack_vld;
output [63:0] que_l2if_data;
input l2if_scrb_data_en;
input [255:0] l2if_scrb_data;
input [33:0] l2if_scrb_ecc;
output que_dram_clk_toggle;
output dp_data_valid;
output [9:0] que_l2if_send_info;
// FROM POWER THROTTLE
output dram_local_pt_opened_bank;
output que_max_banks_open_valid;
output [16:0] que_max_banks_open;
output que_max_time_valid;
input pt_ch_blk_new_openbank;
input [16:0] pt_max_banks_open;
input [15:0] pt_max_time;
// NEW ADDITION DUE TO 2 CHANNEL MODE
input [7:0] ch0_que_ras_int_picked;
input [5:0] ch0_que_b0_data_addr;
input ch0_que_channel_picked;
input [7:0] ch1_que_l2req_valids;
input [35:0] ch1_que_b0_addr_picked;
input [2:0] ch1_que_b0_id_picked;
input [2:0] ch1_que_b0_index_picked;
input ch1_que_b0_cmd_picked;
input other_que_channel_disabled;
input [6:0] ch1_que_int_wr_que_inv_info;
input [4:0] other_que_pos;
output [6:0] que_int_wr_que_inv_info;
output [7:0] que_ras_int_picked;
output [5:0] que_b0_data_addr;
output [7:0] que_l2req_valids;
output [35:0] que_b0_addr_picked;
output [2:0] que_b0_id_picked;
output [2:0] que_b0_index_picked;
output que_b0_cmd_picked;
output que_channel_picked;
output [4:0] que_int_pos;
output que_channel_disabled;
input [255:0] ch1_que_mem_data;
input [3:0] ch1_dp_data_mecc0;
input [3:0] ch1_dp_data_mecc1;
input [3:0] ch1_dp_data_mecc2;
input [3:0] ch1_dp_data_mecc3;
input [3:0] ch1_dp_data_mecc4;
input [3:0] ch1_dp_data_mecc5;
input [3:0] ch1_dp_data_mecc6;
input [3:0] ch1_dp_data_mecc7;
output [3:0] dp_data_mecc0;
output [3:0] dp_data_mecc1;
output [3:0] dp_data_mecc2;
output [3:0] dp_data_mecc3;
output [3:0] dp_data_mecc4;
output [3:0] dp_data_mecc5;
output [3:0] dp_data_mecc6;
output [3:0] dp_data_mecc7;
// FOR PERF
input [7:0] ch0_que_cas_int_picked;
input ch0_que_wr_cas_ch01_picked;
input ch0_que_mux_write_en;
output [7:0] que_cas_int_picked;
output que_wr_cas_ch01_picked;
output que_mux_write_en;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [34:0] dram_fail_over_mask; // From dram_que of dram_que.v
wire err_inj_reg; // From dram_que of dram_que.v
wire [15:0] err_mask_reg; // From dram_que of dram_que.v
wire que_bypass_scrb_data; // From dram_que of dram_que.v
wire que_st_cmd_addr_parity; // From dram_que of dram_que.v
wire que_wr_channel_mux; // From dram_que of dram_que.v
// End of automatics
dram_que dram_que(/*AUTOINST*/
// Outputs
.sshot_err_reg(sshot_err_reg),
.que_margin_reg(que_margin_reg[4:0]),
.readqbank0vld0(readqbank0vld0),
.readqbank0vld1(readqbank0vld1),
.readqbank0vld2(readqbank0vld2),
.readqbank0vld3(readqbank0vld3),
.writeqbank0vld0(writeqbank0vld0),
.writeqbank0vld1(writeqbank0vld1),
.writeqbank0vld2(writeqbank0vld2),
.writeqbank0vld3(writeqbank0vld3),
.readqbank0vld4(readqbank0vld4),
.readqbank0vld5(readqbank0vld5),
.readqbank0vld6(readqbank0vld6),
.readqbank0vld7(readqbank0vld7),
.writeqbank0vld4(writeqbank0vld4),
.writeqbank0vld5(writeqbank0vld5),
.writeqbank0vld6(writeqbank0vld6),
.writeqbank0vld7(writeqbank0vld7),
.que_wr_req (que_wr_req),
.que_scrb_addr (que_scrb_addr[32:0]),
.dram_fail_over_mode(dram_fail_over_mode),
.que_wr_entry_free(que_wr_entry_free[3:0]),
.config_reg (config_reg[8:0]),
.que_rank1_present(que_rank1_present),
.que_addr_bank_low_sel(que_addr_bank_low_sel),
.dram_io_pad_enable(dram_io_pad_enable),
.dram_io_addr (dram_io_addr[14:0]),
.dram_io_bank (dram_io_bank[2:0]),
.dram_io_cs_l (dram_io_cs_l[3:0]),
.dram_io_ras_l (dram_io_ras_l),
.dram_io_cas_l (dram_io_cas_l),
.dram_io_cke (dram_io_cke),
.dram_io_write_en_l(dram_io_write_en_l),
.dram_io_drive_enable(dram_io_drive_enable),
.dram_io_drive_data(dram_io_drive_data),
.dram_io_clk_enable(dram_io_clk_enable),
.dram_io_pad_clk_inv(dram_io_pad_clk_inv),
.dram_io_ptr_clk_inv(dram_io_ptr_clk_inv[4:0]),
.dram_io_channel_disabled(dram_io_channel_disabled),
.dram_fail_over_mask(dram_fail_over_mask[34:0]),
.que_mem_addr (que_mem_addr[4:0]),
.que_bypass_scrb_data(que_bypass_scrb_data),
.que_l2if_ack_vld(que_l2if_ack_vld),
.que_l2if_nack_vld(que_l2if_nack_vld),
.que_l2if_data (que_l2if_data[63:0]),
.que_dram_clk_toggle(que_dram_clk_toggle),
.dram_local_pt_opened_bank(dram_local_pt_opened_bank),
.que_max_banks_open_valid(que_max_banks_open_valid),
.que_max_banks_open(que_max_banks_open[16:0]),
.que_max_time_valid(que_max_time_valid),
.err_inj_reg (err_inj_reg),
.err_mask_reg (err_mask_reg[15:0]),
.que_st_cmd_addr_parity(que_st_cmd_addr_parity),
.que_cas_int_picked(que_cas_int_picked[7:0]),
.que_wr_cas_ch01_picked(que_wr_cas_ch01_picked),
.que_mux_write_en(que_mux_write_en),
.que_l2if_send_info(que_l2if_send_info[9:0]),
.que_ras_int_picked(que_ras_int_picked[7:0]),
.que_b0_data_addr(que_b0_data_addr[5:0]),
.que_l2req_valids(que_l2req_valids[7:0]),
.que_b0_addr_picked(que_b0_addr_picked[35:0]),
.que_b0_id_picked(que_b0_id_picked[2:0]),
.que_b0_index_picked(que_b0_index_picked[2:0]),
.que_b0_cmd_picked(que_b0_cmd_picked),
.que_channel_picked(que_channel_picked),
.que_int_wr_que_inv_info(que_int_wr_que_inv_info[6:0]),
.que_int_pos (que_int_pos[4:0]),
.que_channel_disabled(que_channel_disabled),
.que_wr_channel_mux(que_wr_channel_mux),
.que_eight_bank_mode(que_eight_bank_mode),
// Inputs
.clk (clk),
.rst_l (rst_l),
.arst_l (arst_l),
.sehold (sehold),
.l2if_que_selfrsh(l2if_que_selfrsh),
.dram_dbginit_l(dram_dbginit_l),
.l2if_rd_id (l2if_rd_id[2:0]),
.l2if_rd_addr (l2if_rd_addr[35:0]),
.l2if_wr_addr (l2if_wr_addr[35:0]),
.l2if_wr_req (l2if_wr_req),
.l2if_rd_req (l2if_rd_req),
.l2if_que_rd_req_vld(l2if_que_rd_req_vld),
.l2if_que_wr_req_vld(l2if_que_wr_req_vld),
.l2if_que_addr (l2if_que_addr[31:0]),
.l2if_que_data (l2if_que_data[63:0]),
.pt_ch_blk_new_openbank(pt_ch_blk_new_openbank),
.pt_max_banks_open(pt_max_banks_open[16:0]),
.pt_max_time (pt_max_time[15:0]),
.l2if_data_wr_addr(l2if_data_wr_addr[2:0]),
.l2if_err_addr_reg(l2if_err_addr_reg[35:0]),
.l2if_err_sts_reg(l2if_err_sts_reg[22:0]),
.l2if_err_loc (l2if_err_loc[35:0]),
.l2if_err_cnt (l2if_err_cnt[17:0]),
.l2if_dbg_trig_en(l2if_dbg_trig_en),
.ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]),
.ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
.ch0_que_mux_write_en(ch0_que_mux_write_en),
.ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]),
.ch0_que_b0_data_addr(ch0_que_b0_data_addr[5:0]),
.ch0_que_channel_picked(ch0_que_channel_picked),
.ch1_que_l2req_valids(ch1_que_l2req_valids[7:0]),
.ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]),
.ch1_que_b0_id_picked(ch1_que_b0_id_picked[2:0]),
.ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]),
.ch1_que_b0_cmd_picked(ch1_que_b0_cmd_picked),
.other_que_channel_disabled(other_que_channel_disabled),
.other_que_pos (other_que_pos[4:0]),
.ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]));
dram_dp dram_dp(/*AUTOINST*/
// Outputs
.dp_data_mecc0 (dp_data_mecc0[3:0]),
.dp_data_mecc1 (dp_data_mecc1[3:0]),
.dp_data_mecc2 (dp_data_mecc2[3:0]),
.dp_data_mecc3 (dp_data_mecc3[3:0]),
.dp_data_mecc4 (dp_data_mecc4[3:0]),
.dp_data_mecc5 (dp_data_mecc5[3:0]),
.dp_data_mecc6 (dp_data_mecc6[3:0]),
.dp_data_mecc7 (dp_data_mecc7[3:0]),
.dram_io_data_out(dram_io_data_out[287:0]),
.dp_data_in (dp_data_in[255:0]),
.dp_ecc_in (dp_ecc_in[31:0]),
.dp_data_valid (dp_data_valid),
// Inputs
.clk (clk),
.rst_l (rst_l),
.l2if_data_mecc0(l2if_data_mecc0[3:0]),
.l2if_data_mecc1(l2if_data_mecc1[3:0]),
.l2if_data_mecc2(l2if_data_mecc2[3:0]),
.l2if_data_mecc3(l2if_data_mecc3[3:0]),
.l2if_data_mecc4(l2if_data_mecc4[3:0]),
.l2if_data_mecc5(l2if_data_mecc5[3:0]),
.l2if_data_mecc6(l2if_data_mecc6[3:0]),
.l2if_data_mecc7(l2if_data_mecc7[3:0]),
.io_dram_data_in(io_dram_data_in[255:0]),
.io_dram_ecc_in (io_dram_ecc_in[31:0]),
.io_dram_data_valid(io_dram_data_valid),
.que_bypass_scrb_data(que_bypass_scrb_data),
.que_mem_addr (que_mem_addr[4:0]),
.que_mem_data (que_mem_data[255:0]),
.que_st_cmd_addr_parity(que_st_cmd_addr_parity),
.que_channel_disabled(que_channel_disabled),
.dram_fail_over_mask(dram_fail_over_mask[34:0]),
.l2if_scrb_data_en(l2if_scrb_data_en),
.l2if_scrb_data (l2if_scrb_data[255:0]),
.l2if_scrb_ecc (l2if_scrb_ecc[33:0]),
.err_inj_reg (err_inj_reg),
.err_mask_reg (err_mask_reg[15:0]),
.que_wr_channel_mux(que_wr_channel_mux),
.ch1_que_mem_data(ch1_que_mem_data[255:0]),
.ch1_dp_data_mecc0(ch1_dp_data_mecc0[3:0]),
.ch1_dp_data_mecc1(ch1_dp_data_mecc1[3:0]),
.ch1_dp_data_mecc2(ch1_dp_data_mecc2[3:0]),
.ch1_dp_data_mecc3(ch1_dp_data_mecc3[3:0]),
.ch1_dp_data_mecc4(ch1_dp_data_mecc4[3:0]),
.ch1_dp_data_mecc5(ch1_dp_data_mecc5[3:0]),
.ch1_dp_data_mecc6(ch1_dp_data_mecc6[3:0]),
.ch1_dp_data_mecc7(ch1_dp_data_mecc7[3:0]),
.sshot_err_reg(sshot_err_reg));
endmodule // dram_dctl
|
module top;
reg pass, pass_f1, pass_f2, pass_f3, pass_f4, pass_f5;
reg [8*30:1] res;
initial begin
pass = 1'b1;
// Verify that the initial scope is correct.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed initial, got \"%0s\"", res);
pass = 1'b0;
end
// Test %m in a named begin.
begin : my_begin
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (1st), got \"%0s\"", res);
pass = 1'b0;
end
begin : my_begin_begin
// Test %m in a nested named begin.
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_begin") begin
$display("Failed nested named begin, got \"%0s\"", res);
pass = 1'b0;
end
end
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (2nd), got \"%0s\"", res);
pass = 1'b0;
end
// Test a named fork inside a named begin.
pass_f1 = 1'b1;
pass_f2 = 1'b1;
fork : my_begin_fork
begin
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_fork") begin
$display("Failed after named begin/fork (1), got \"%0s\"", res);
pass_f1 = 1'b0;
end
end
begin
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_fork") begin
$display("Failed after named begin/fork (2), got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
join
pass = pass & pass_f1 & pass_f2;
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (3rd), got \"%0s\"", res);
pass = 1'b0;
end
end
// Verify that the scope is back to normal.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed after named begin, got \"%0s\"", res);
pass = 1'b0;
end
// Test %m in a named fork.
pass_f1 = 1'b1;
pass_f2 = 1'b1;
pass_f3 = 1'b1;
pass_f4 = 1'b1;
pass_f5 = 1'b1;
fork : my_fork
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (1), got \"%0s\"", res);
pass_f1 = 1'b0;
end
end
// Test a %m in a nested named begin.
begin : my_fork_begin
$swrite(res, "%m");
if (res != "top.my_fork.my_fork_begin") begin
$display("Failed after named fork/begin, got \"%0s\"", res);
pass_f4 = 1'b0;
end
end
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (2), got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
fork : my_fork_fork
begin
$swrite(res, "%m");
if (res != "top.my_fork.my_fork_fork") begin
$display("Failed after named fork/fork, got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
join
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (3), got \"%0s\"", res);
pass_f3 = 1'b0;
end
end
join
pass = pass & pass_f1 & pass_f2 & pass_f3;
// Verify that the scope is back to normal.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed final, got \"%0s\"", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This test demonstrates an issue with sign extension.
// Assigning to localparms larger than 32 bits broke in 3.862
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Mike Thyer.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;
localparam [ 2:0] one3_lp = 1;
localparam [ 3:0] one4_lp = 1;
localparam [ 4:0] one5_lp = 1;
localparam [ 5:0] one6_lp = 1;
localparam [ 6:0] one7_lp = 1;
localparam [ 7:0] one8_lp = 1;
localparam [ 8:0] one9_lp = 1;
localparam [ 9:0] one10_lp = 1;
localparam [19:0] one20_lp = 1;
localparam [29:0] one30_lp = 1;
localparam [30:0] one31_lp = 1;
localparam [31:0] one32_lp = 1;
localparam [32:0] one33_lp = 1;
localparam [33:0] one34_lp = 1;
localparam [34:0] one35_lp = 1;
localparam [35:0] one36_lp = 1;
localparam [36:0] one37_lp = 1;
localparam [37:0] one38_lp = 1;
localparam [38:0] one39_lp = 1;
localparam [39:0] one40_lp = 1;
localparam [49:0] one50_lp = 1;
localparam [59:0] one60_lp = 1;
localparam [60:0] one61_lp = 1;
localparam [61:0] one62_lp = 1;
localparam [62:0] one63_lp = 1;
localparam [63:0] one64_lp = 1;
localparam [64:0] one65_lp = 1;
localparam [65:0] one66_lp = 1;
localparam [66:0] one67_lp = 1;
localparam [67:0] one68_lp = 1;
localparam [68:0] one69_lp = 1;
localparam [69:0] one70_lp = 1;
bit all_ok = 1;
initial begin
`ifdef TEST_VERBOSE
$display("one1_lp : %x %d", one1_lp, one1_lp==1);
$display("one2_lp : %x %d", one2_lp, one2_lp==1);
$display("one3_lp : %x %d", one3_lp, one3_lp==1);
$display("one4_lp : %x %d", one4_lp, one4_lp==1);
$display("one5_lp : %x %d", one5_lp, one5_lp==1);
$display("one6_lp : %x %d", one6_lp, one6_lp==1);
$display("one7_lp : %x %d", one7_lp, one7_lp==1);
$display("one8_lp : %x %d", one8_lp, one8_lp==1);
$display("one9_lp : %x %d", one9_lp, one9_lp==1);
$display("one10_lp: %x %d", one10_lp, one10_lp==1);
$display("one20_lp: %x %d", one20_lp, one20_lp==1);
$display("one30_lp: %x %d", one30_lp, one30_lp==1);
$display("one31_lp: %x %d", one31_lp, one31_lp==1);
$display("one32_lp: %x %d", one32_lp, one32_lp==1);
$display("one33_lp: %x %d", one33_lp, one33_lp==1);
$display("one34_lp: %x %d", one34_lp, one34_lp==1);
$display("one35_lp: %x %d", one35_lp, one35_lp==1);
$display("one36_lp: %x %d", one36_lp, one36_lp==1);
$display("one37_lp: %x %d", one37_lp, one37_lp==1);
$display("one38_lp: %x %d", one38_lp, one38_lp==1);
$display("one39_lp: %x %d", one39_lp, one39_lp==1);
$display("one40_lp: %x %d", one40_lp, one40_lp==1);
$display("one50_lp: %x %d", one50_lp, one50_lp==1);
$display("one60_lp: %x %d", one60_lp, one60_lp==1);
$display("one61_lp: %x %d", one61_lp, one61_lp==1);
$display("one62_lp: %x %d", one62_lp, one62_lp==1);
$display("one63_lp: %x %d", one63_lp, one63_lp==1);
$display("one64_lp: %x %d", one64_lp, one64_lp==1);
$display("one65_lp: %x %d", one65_lp, one65_lp==1);
$display("one66_lp: %x %d", one66_lp, one66_lp==1);
$display("one67_lp: %x %d", one67_lp, one67_lp==1);
$display("one68_lp: %x %d", one68_lp, one68_lp==1);
$display("one69_lp: %x %d", one69_lp, one69_lp==1);
$display("one70_lp: %x %d", one70_lp, one70_lp==1);
`endif
all_ok &= one1_lp == 1;
all_ok &= one2_lp == 1;
all_ok &= one3_lp == 1;
all_ok &= one4_lp == 1;
all_ok &= one5_lp == 1;
all_ok &= one6_lp == 1;
all_ok &= one7_lp == 1;
all_ok &= one8_lp == 1;
all_ok &= one9_lp == 1;
all_ok &= one10_lp == 1;
all_ok &= one20_lp == 1;
all_ok &= one30_lp == 1;
all_ok &= one31_lp == 1;
all_ok &= one32_lp == 1;
all_ok &= one33_lp == 1;
all_ok &= one34_lp == 1;
all_ok &= one35_lp == 1;
all_ok &= one36_lp == 1;
all_ok &= one37_lp == 1;
all_ok &= one38_lp == 1;
all_ok &= one39_lp == 1;
all_ok &= one40_lp == 1;
all_ok &= one50_lp == 1;
all_ok &= one60_lp == 1;
all_ok &= one61_lp == 1;
all_ok &= one62_lp == 1;
all_ok &= one63_lp == 1;
all_ok &= one64_lp == 1;
all_ok &= one65_lp == 1;
all_ok &= one66_lp == 1;
all_ok &= one67_lp == 1;
all_ok &= one68_lp == 1;
all_ok &= one69_lp == 1;
all_ok &= one70_lp == 1;
if (!all_ok) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_FUNCTIONAL_PP_V |
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate assign procedural assign ident = expr;
module main ;
reg [31:0] value;
reg control;
reg clock;
reg error;
always @(posedge clock)
value = 3;
always @(control)
if(control)
assign value = 2;
else
deassign value ;
// Setup a clock generator.
always begin
#2;
clock = ~clock;
end
initial
begin
clock = 0;
error = 0;
# 3;
if(value != 3)
begin
$display("FAILED - assign3.2C - procedural assignment(1)");
error = 1;
end
# 2;
control = 1;
# 1;
if(value != 2)
begin
$display("FAILED - assign3.2C - procedural assignment(2)");
error = 1;
end
# 3 ;
control = 0;
# 2;
if(value != 3)
begin
$display("FAILED - assign3.2C - procedural assignment(3)");
error = 1;
end
if(error == 0) $display ("PASSED");
$finish ;
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This is a check of the implementation of division and multiplication
* within more complex expressions.
*/
module test;
task mod;
input [31:0] a;
input [15:0] b;
output [31:0] out;
begin
out = a-(a/b)*b;
end
endtask
reg [31:0] result,c, nl;
initial begin
c = 13; nl = 3;
mod(c, nl, result);
$display("13 %% 3 = %d", result);
if (result !== 32'h00_00_00_01) begin
$display("FAILED -- result is %b", result);
$finish;
end
$display("PASSED");
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
module tb_fmlbrg();
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg [3:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [25:0] fml_adr;
wire fml_stb;
wire fml_we;
reg fml_ack;
wire [7:0] fml_sel;
wire [63:0] fml_dw;
reg [63:0] fml_dr;
reg dcb_stb;
reg [25:0] dcb_adr;
wire [63:0] dcb_dat;
wire dcb_hit;
/* Process FML requests */
reg [1:0] fml_wcount;
reg [1:0] fml_rcount;
initial begin
fml_ack = 1'b0;
fml_wcount = 0;
fml_rcount = 0;
end
always @(posedge clk) begin
if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
fml_ack <= 1'b1;
if(fml_we) begin
$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
fml_wcount <= 3;
end else begin
fml_dr = 64'hcafebabedeadbeef;
$display("%t FML R addr %x data %x", $time, fml_adr, fml_dr);
fml_rcount <= 3;
end
end else
fml_ack <= 1'b0;
if(fml_wcount != 0) begin
#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
fml_wcount <= fml_wcount - 1;
end
if(fml_rcount != 0) begin
fml_dr = #1 {24'hdeadbe, 6'd0, fml_rcount, 24'hcafeba, 6'd0, fml_rcount};
$display("%t FML R continuing %x / %d", $time, fml_dr, fml_rcount);
fml_rcount <= fml_rcount - 1;
end
end
fmlbrg dut(
.sys_clk(clk),
.sys_rst(rst),
.wb_adr_i(wb_adr_i),
.wb_cti_i(3'd0),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_do(fml_dw),
.fml_di(fml_dr),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_sel_i = 4'hf;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_adr_i = 32'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_adr_i = 32'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
always begin
`ifdef ENABLE_VCD
$dumpfile("fmlbrg.vcd");
$dumpvars(0, dut);
`endif
rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
dcb_stb = 1'b0;
dcb_adr = 26'd0;
waitclock;
rst = 1'b0;
waitclock;
$display("Testing: read miss");
wbread(26'h0);
$display("Testing: write hit");
wbwrite(26'h0, 32'h12345678);
wbread(26'h0);
$display("Testing: read miss on a dirty line");
wbread(26'h10000);
$display("Testing: read hit");
wbread(26'h10004);
$display("Testing: write miss");
wbwrite(26'h0, 32'habadface);
wbread(26'h0);
wbread(26'h4);
$display("Testing: DCB miss");
dcb_adr = 26'hfebabe;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 26'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$finish;
end
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`include "~/ee577b/syn/src/control.h"
// shift functrions only
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
result<=128'b0;
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
default:
result[0:7]<=8'b0;
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
default:
result[8:15]<=8'b0;
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
default:
result[16:23]<=8'b0;
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
default:
result[24:31]<=8'b0;
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
default:
result[32:39]<=8'b0;
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
default:
result[40:47]<=8'b0;
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
default:
result[48:55]<=8'b0;
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
default:
result[56:63]<=8'b0;
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
default:
result[64:71]<=8'b0;
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
default:
result[72:79]<=8'b0;
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
default:
result[80:87]<=8'b0;
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
default:
result[88:95]<=8'b0;
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
default:
result[96:103]<=8'b0;
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
default:
result[104:111]<=8'b0;
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
default:
result[112:119]<=8'b0;
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
default:
result[120:127]<=8'b0;
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
default:
result[0:15]<=16'b0;
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
default:
result[16:31]<=16'b0;
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
default:
result[48:63]<=16'b0;
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
default:
result[64:79]<=16'b0;
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
default:
result[80:95]<=16'b0;
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
default:
result[96:111]<=16'b0;
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
default:
result[112:127]<=16'b0;
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
default:
result[0:31]<=32'b0;
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
default:
result[32:63]<=32'b0;
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
default:
result[64:95]<=32'b0;
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
default:
result[96:127]<=32'b0;
endcase
end
default
result<=128'b0;
endcase
end
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
// soc_design_niosII_core.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_niosII_core (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire [3:0] d_burstcount, // .burstcount
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [26:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
output wire [3:0] i_burstcount, // .burstcount
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
soc_design_niosII_core_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_burstcount (d_burstcount), // .burstcount
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_burstcount (i_burstcount), // .burstcount
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program catches some glitches in the MUXZ that Icarus Verilog
* uses to implement the ?: in structural cases.
*/
module main;
reg [6:0] a, b;
reg sel;
wire [6:0] test = sel? a : b;
wire [7:0] test2 = test;
initial begin
sel = 0;
// At this point, test2 should be x.
#1 $display("sel=%b, test2=%b", sel, test2);
b = 0;
#1 $display("sel=b, test2=%b", sel, test2);
if (test2 !== 8'b0_0000000) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//////////////////////////////////////////////////////////////////////////////////
// d_CS_top.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_CS_top
// File Name: d_CS_top.v
//
// Version: v2.0.0-256B_T14
//
// Description:
// - BCH decoder: Chien search (CS) TOP module
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v2.0.0
// - data fowarding, output pause
//
// * v1.0.2
// - minor modification for releasing
//
// * v1.0.1
// - state machine: minor change
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_CS_parameters.vh"
`timescale 1ns / 1ps
module d_BCH_CS_top
(
input wire i_clk,
input wire i_RESET,
input wire i_stop_dec,
output wire o_cs_available, // [indicate] Chien search ready
input wire i_exe_cs, // Chien search start command signal
input wire i_data_fowarding,
input wire i_MUX_data_ready,
output wire o_cs_start, // [indicate] Chien search start
output wire o_cs_cmplt, // [indicate] Chien search complete
output wire o_cs_pause, // [indicate] Ch
output wire o_BRAM_read_enable,
output wire [`D_CS_O_CNT_BIT-2:0] o_BRAM_read_address,
input wire [`D_CS_P_LVL-1:0] i_BRAM_read_data, // received code
output wire o_c_message_valid, // [indicate] corrected message BUS strobe signal
output wire o_c_message_output_start, // [indicate] corrected message output start
output wire o_c_message_output_cmplt, // [indicate] corrected message output complete
output reg [`D_CS_P_LVL-1:0] o_c_message, // corrected message BUS
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 15
input wire [`D_CS_GF_ORDER-1:0] i_v_000,
input wire [`D_CS_GF_ORDER-1:0] i_v_001,
input wire [`D_CS_GF_ORDER-1:0] i_v_002,
input wire [`D_CS_GF_ORDER-1:0] i_v_003,
input wire [`D_CS_GF_ORDER-1:0] i_v_004,
input wire [`D_CS_GF_ORDER-1:0] i_v_005,
input wire [`D_CS_GF_ORDER-1:0] i_v_006,
input wire [`D_CS_GF_ORDER-1:0] i_v_007,
input wire [`D_CS_GF_ORDER-1:0] i_v_008,
input wire [`D_CS_GF_ORDER-1:0] i_v_009,
input wire [`D_CS_GF_ORDER-1:0] i_v_010,
input wire [`D_CS_GF_ORDER-1:0] i_v_011,
input wire [`D_CS_GF_ORDER-1:0] i_v_012,
input wire [`D_CS_GF_ORDER-1:0] i_v_013,
input wire [`D_CS_GF_ORDER-1:0] i_v_014
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
);
parameter CS_FSM_BIT = 13;
parameter RESET = 13'b0000000000001; // RESET
parameter DELAY = 13'b0000000000010;
parameter DELAY_FWD = 13'b0000000000100;
parameter EVAL_SHT = 13'b0000000001000; // evaluation shortening
parameter CS_STRT = 13'b0000000010000; // Chien search, start
parameter CS_FBCK = 13'b0000000100000; // Chien search, feedback
parameter CS_STBY = 13'b0000001000000; // Chien search, pause
parameter CS_FNLS = 13'b0000010000000; // final stage, output last corrected message
parameter FWD_MODE = 13'b0000100000000;
parameter FWD_STRT = 13'b0001000000000; // Forwarding, Correction is not needed or possible
parameter FWD_FBCK = 13'b0010000000000; // Forwarding
parameter FWD_STBY = 13'b0100000000000; // Forwarding
parameter FWD_FNLS = 13'b1000000000000; // Forwarding
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 8, 8
wire w_slot_001_flip;
wire w_slot_002_flip;
wire w_slot_003_flip;
wire w_slot_004_flip;
wire w_slot_005_flip;
wire w_slot_006_flip;
wire w_slot_007_flip;
wire w_slot_008_flip;
wire w_slot_001_flipped_message;
wire w_slot_002_flipped_message;
wire w_slot_003_flipped_message;
wire w_slot_004_flipped_message;
wire w_slot_005_flipped_message;
wire w_slot_006_flipped_message;
wire w_slot_007_flipped_message;
wire w_slot_008_flipped_message;
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 14
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_001;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_002;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_003;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_004;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_005;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_006;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_007;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_008;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_009;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_010;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_011;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_012;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_013;
wire [`D_CS_GF_ORDER -1:0] w_shortened_v_014;
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 15
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_000;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_001;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_002;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_003;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_004;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_005;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_006;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_007;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_008;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_009;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_010;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_011;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_012;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_013;
wire [`D_CS_GF_ORDER -1:0] w_ELP_term_014;
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 15 * 8 = 120
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S001_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S002_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S003_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S004_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S005_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S006_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S007_014;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_000;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_001;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_002;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_003;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_004;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_005;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_006;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_007;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_008;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_009;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_010;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_011;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_012;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_013;
wire [`D_CS_GF_ORDER-1:0] w_evaluated_term_S008_014;
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
// encoder FSM state
reg [CS_FSM_BIT-1:0] r_cur_state;
reg [CS_FSM_BIT-1:0] r_nxt_state;
// internal counter
reg [`D_CS_O_CNT_BIT:0] r_counter;
// internal variable
wire [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] w_v_input_wire_e000; // i_v_014 ~ i_v_001, except i_v_000
reg [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] r_v_buffer_e000; // i_v_014 ~ i_v_001, except i_v_000
reg [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] r_v_buffer_e000_delay;
reg [`D_CS_GF_ORDER -1:0] r_v_buffer_000; // i_v_000
reg [`D_CS_GF_ORDER -1:0] r_v_buffer_000_delay;
wire [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] w_shortened_v; // i_v_014 ~ i_v_001
wire [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] w_feedback_wire; // i_v_014 ~ i_v_001
reg [(`D_CS_ECC_T+1)*`D_CS_GF_ORDER -1:`D_CS_GF_ORDER ] r_feedback_buffer; // i_v_014 ~ i_v_001
reg [`D_CS_P_LVL-1:0] r_received_code_buffer;
reg [`D_CS_P_LVL-1:0] r_BRAM_read_buffer;
reg [`D_CS_P_LVL-1:0] r_waiting_buffer;
wire [`D_CS_P_LVL-1:0] w_flipped_message;
// generate control/indicate signal
assign o_BRAM_read_enable = (i_exe_cs) | ( ((r_cur_state == DELAY) | (r_cur_state == DELAY_FWD) | (r_cur_state == EVAL_SHT) | (r_cur_state == CS_STRT) | (r_cur_state == CS_FBCK) | (r_cur_state == FWD_MODE) | (r_cur_state == FWD_STRT) | (r_cur_state == FWD_FBCK)) & (r_counter != `D_CS_O_CNT) & (r_counter != `D_CS_O_CNT+1) & (r_counter != `D_CS_O_CNT+2) );
assign o_BRAM_read_address = r_counter[`D_CS_O_CNT_BIT-2:0];
assign o_cs_start = (r_cur_state == EVAL_SHT) || (r_cur_state == FWD_MODE);
assign o_cs_available = (r_cur_state == RESET);
assign o_cs_cmplt = ((r_cur_state == CS_FNLS) | (r_cur_state == FWD_FNLS)) & i_MUX_data_ready & o_c_message_valid;
assign o_c_message_valid = (r_cur_state == CS_FBCK) | (r_cur_state == CS_FNLS) | (r_cur_state == CS_STBY) | (r_cur_state == FWD_FBCK) | (r_cur_state == FWD_FNLS) | (r_cur_state == FWD_STBY) ;
assign o_c_message_output_start = (r_counter == 4);
assign o_c_message_output_cmplt = o_cs_cmplt;
assign o_cs_pause = (r_cur_state == CS_STBY) || (r_cur_state == FWD_STBY);
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// wire mapping
assign w_v_input_wire_e000[(`D_CS_ECC_T+1)*`D_CS_GF_ORDER-1:`D_CS_GF_ORDER] = { i_v_014[`D_CS_GF_ORDER-1:0], i_v_013[`D_CS_GF_ORDER-1:0], i_v_012[`D_CS_GF_ORDER-1:0], i_v_011[`D_CS_GF_ORDER-1:0], i_v_010[`D_CS_GF_ORDER-1:0], i_v_009[`D_CS_GF_ORDER-1:0], i_v_008[`D_CS_GF_ORDER-1:0], i_v_007[`D_CS_GF_ORDER-1:0], i_v_006[`D_CS_GF_ORDER-1:0], i_v_005[`D_CS_GF_ORDER-1:0], i_v_004[`D_CS_GF_ORDER-1:0], i_v_003[`D_CS_GF_ORDER-1:0], i_v_002[`D_CS_GF_ORDER-1:0], i_v_001[`D_CS_GF_ORDER-1:0] };
assign w_shortened_v[(`D_CS_ECC_T+1)*`D_CS_GF_ORDER-1:`D_CS_GF_ORDER] = { w_shortened_v_014[`D_CS_GF_ORDER-1:0], w_shortened_v_013[`D_CS_GF_ORDER-1:0], w_shortened_v_012[`D_CS_GF_ORDER-1:0], w_shortened_v_011[`D_CS_GF_ORDER-1:0], w_shortened_v_010[`D_CS_GF_ORDER-1:0], w_shortened_v_009[`D_CS_GF_ORDER-1:0], w_shortened_v_008[`D_CS_GF_ORDER-1:0], w_shortened_v_007[`D_CS_GF_ORDER-1:0], w_shortened_v_006[`D_CS_GF_ORDER-1:0], w_shortened_v_005[`D_CS_GF_ORDER-1:0], w_shortened_v_004[`D_CS_GF_ORDER-1:0], w_shortened_v_003[`D_CS_GF_ORDER-1:0], w_shortened_v_002[`D_CS_GF_ORDER-1:0], w_shortened_v_001[`D_CS_GF_ORDER-1:0] };
assign w_feedback_wire[(`D_CS_ECC_T+1)*`D_CS_GF_ORDER-1:`D_CS_GF_ORDER] = { w_evaluated_term_S008_014[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_013[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_012[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_011[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_010[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_009[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_008[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_007[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_006[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_005[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_004[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_003[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_002[`D_CS_GF_ORDER-1:0], w_evaluated_term_S008_001[`D_CS_GF_ORDER-1:0] };
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
assign w_ELP_term_000[`D_CS_GF_ORDER -1:0] = r_v_buffer_000[`D_CS_GF_ORDER -1:0];
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 14
assign w_ELP_term_001[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 1+1)*`D_CS_GF_ORDER-1:( 1+0)*`D_CS_GF_ORDER];
assign w_ELP_term_002[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 2+1)*`D_CS_GF_ORDER-1:( 2+0)*`D_CS_GF_ORDER];
assign w_ELP_term_003[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 3+1)*`D_CS_GF_ORDER-1:( 3+0)*`D_CS_GF_ORDER];
assign w_ELP_term_004[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 4+1)*`D_CS_GF_ORDER-1:( 4+0)*`D_CS_GF_ORDER];
assign w_ELP_term_005[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 5+1)*`D_CS_GF_ORDER-1:( 5+0)*`D_CS_GF_ORDER];
assign w_ELP_term_006[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 6+1)*`D_CS_GF_ORDER-1:( 6+0)*`D_CS_GF_ORDER];
assign w_ELP_term_007[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 7+1)*`D_CS_GF_ORDER-1:( 7+0)*`D_CS_GF_ORDER];
assign w_ELP_term_008[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 8+1)*`D_CS_GF_ORDER-1:( 8+0)*`D_CS_GF_ORDER];
assign w_ELP_term_009[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 9+1)*`D_CS_GF_ORDER-1:( 9+0)*`D_CS_GF_ORDER];
assign w_ELP_term_010[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 10+1)*`D_CS_GF_ORDER-1:( 10+0)*`D_CS_GF_ORDER];
assign w_ELP_term_011[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 11+1)*`D_CS_GF_ORDER-1:( 11+0)*`D_CS_GF_ORDER];
assign w_ELP_term_012[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 12+1)*`D_CS_GF_ORDER-1:( 12+0)*`D_CS_GF_ORDER];
assign w_ELP_term_013[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 13+1)*`D_CS_GF_ORDER-1:( 13+0)*`D_CS_GF_ORDER];
assign w_ELP_term_014[`D_CS_GF_ORDER-1:0] = r_feedback_buffer[( 14+1)*`D_CS_GF_ORDER-1:( 14+0)*`D_CS_GF_ORDER];
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET) || (i_stop_dec))
r_cur_state <= RESET;
else
r_cur_state <= r_nxt_state;
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
RESET: begin
r_nxt_state <= (i_exe_cs)? ((i_data_fowarding)? DELAY_FWD:DELAY):RESET;
end
DELAY: begin
r_nxt_state <= EVAL_SHT;
end
EVAL_SHT: begin
r_nxt_state <= CS_STRT;
end
CS_STRT: begin
r_nxt_state <= CS_FBCK;
end
CS_FBCK: begin
r_nxt_state <= (!i_MUX_data_ready)? CS_STBY : ((r_counter == `D_CS_O_CNT+2)? (CS_FNLS):(CS_FBCK));
end
CS_STBY: begin
r_nxt_state <= (!i_MUX_data_ready)? CS_STBY: ((r_counter == `D_CS_O_CNT+2)? CS_FNLS: CS_FBCK);
end
CS_FNLS: begin
r_nxt_state <= (!i_MUX_data_ready)? CS_FNLS: ((i_exe_cs)? ((i_data_fowarding)? FWD_MODE:EVAL_SHT):RESET);
end
DELAY_FWD: begin
r_nxt_state <= FWD_MODE;
end
FWD_MODE: begin
r_nxt_state <= FWD_STRT;
end
FWD_STRT: begin
r_nxt_state <= FWD_FBCK;
end
FWD_FBCK: begin
r_nxt_state <= (!i_MUX_data_ready)? FWD_STBY : ((r_counter == `D_CS_O_CNT+2)? (FWD_FNLS):(FWD_FBCK));
end
FWD_STBY: begin
r_nxt_state <= (!i_MUX_data_ready)? FWD_STBY : ((r_counter == `D_CS_O_CNT+2)? (FWD_FNLS):(FWD_FBCK));
end
FWD_FNLS: begin
r_nxt_state <= (!i_MUX_data_ready)? FWD_FNLS : ((i_exe_cs)? ((i_data_fowarding)? FWD_MODE:EVAL_SHT):RESET);
end
default: begin
r_nxt_state <= RESET;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
case (r_nxt_state)
RESET:begin
r_counter <= 0;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
DELAY: begin
r_counter <= 1;
r_v_buffer_e000_delay <= w_v_input_wire_e000;
r_v_buffer_000_delay <= i_v_000;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
EVAL_SHT: begin
r_counter <= 2;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= r_v_buffer_000_delay;
r_v_buffer_e000 <= r_v_buffer_e000_delay;
r_v_buffer_000 <= r_v_buffer_000_delay;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= i_BRAM_read_data;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
CS_STRT: begin
r_counter <= 3;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= r_v_buffer_000;
r_feedback_buffer <= w_shortened_v;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= i_BRAM_read_data;
r_received_code_buffer <= r_BRAM_read_buffer;
o_c_message <= 0;
end
CS_FBCK:
begin
r_counter <= r_counter + 1'b1;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= r_v_buffer_000;
r_feedback_buffer <= w_feedback_wire;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= (r_cur_state == CS_STBY) ? r_BRAM_read_buffer:i_BRAM_read_data;
r_received_code_buffer <= r_waiting_buffer;
o_c_message <= w_flipped_message;
end
CS_STBY:
begin
r_counter <= r_counter;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= r_v_buffer_000;
r_feedback_buffer <= r_feedback_buffer;
r_BRAM_read_buffer <= (r_cur_state == CS_STBY)? r_BRAM_read_buffer:i_BRAM_read_data;
r_waiting_buffer <= r_waiting_buffer;
r_received_code_buffer <= r_received_code_buffer;
o_c_message <= o_c_message;
end
CS_FNLS: begin
if (r_cur_state == CS_FNLS) begin
r_counter <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= o_c_message;
end
else begin
r_counter <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= w_flipped_message;
end
end
DELAY_FWD: begin
r_counter <= 1;
r_v_buffer_e000_delay <= w_v_input_wire_e000;
r_v_buffer_000_delay <= i_v_000;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
FWD_MODE: begin
r_counter <= 2;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= r_v_buffer_000_delay;
r_v_buffer_e000 <= r_v_buffer_e000_delay;
r_v_buffer_000 <= r_v_buffer_000_delay;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= i_BRAM_read_data;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
FWD_STRT: begin
r_counter <= 3;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= i_BRAM_read_data;
r_received_code_buffer <= r_BRAM_read_buffer;
o_c_message <= 0;
end
FWD_FBCK: begin
r_counter <= r_counter + 1'b1;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= i_BRAM_read_data;
r_waiting_buffer <= (r_cur_state == FWD_STBY) ? r_BRAM_read_buffer:i_BRAM_read_data;
r_received_code_buffer <= r_waiting_buffer;
o_c_message <= r_received_code_buffer;
end
FWD_STBY: begin
r_counter <= r_counter;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= (r_cur_state == FWD_STBY)? r_BRAM_read_buffer:i_BRAM_read_data;
r_waiting_buffer <= r_waiting_buffer;
r_received_code_buffer <= r_received_code_buffer;
o_c_message <= o_c_message;
end
FWD_FNLS: begin
if (r_cur_state == FWD_FNLS) begin
r_counter <= 0;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= o_c_message;
end
else begin
r_counter <= 0;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= r_received_code_buffer;
end
end
default: begin
r_counter <= 0;
r_v_buffer_e000_delay <= 0;
r_v_buffer_000_delay <= 0;
r_v_buffer_e000 <= 0;
r_v_buffer_000 <= 0;
r_feedback_buffer <= 0;
r_BRAM_read_buffer <= 0;
r_waiting_buffer <= 0;
r_received_code_buffer <= 0;
o_c_message <= 0;
end
endcase
end
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 8
assign w_evaluated_term_S001_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S002_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S003_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S004_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S005_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S006_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S007_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
assign w_evaluated_term_S008_000[`D_CS_GF_ORDER -1:0] = w_ELP_term_000[`D_CS_GF_ORDER -1:0];
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 14
d_CS_shortening_matrix_alpha_to_001 SM_001 ( // shortened by alpha_to_1879, 1879
.i_in(r_v_buffer_e000[( 1+1)*`D_CS_GF_ORDER-1:( 1+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_001[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_002 SM_002 ( // shortened by alpha_to_1879, 3758
.i_in(r_v_buffer_e000[( 2+1)*`D_CS_GF_ORDER-1:( 2+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_002[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_003 SM_003 ( // shortened by alpha_to_1879, 1542
.i_in(r_v_buffer_e000[( 3+1)*`D_CS_GF_ORDER-1:( 3+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_003[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_004 SM_004 ( // shortened by alpha_to_1879, 3421
.i_in(r_v_buffer_e000[( 4+1)*`D_CS_GF_ORDER-1:( 4+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_004[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_005 SM_005 ( // shortened by alpha_to_1879, 1205
.i_in(r_v_buffer_e000[( 5+1)*`D_CS_GF_ORDER-1:( 5+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_005[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_006 SM_006 ( // shortened by alpha_to_1879, 3084
.i_in(r_v_buffer_e000[( 6+1)*`D_CS_GF_ORDER-1:( 6+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_006[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_007 SM_007 ( // shortened by alpha_to_1879, 868
.i_in(r_v_buffer_e000[( 7+1)*`D_CS_GF_ORDER-1:( 7+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_007[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_008 SM_008 ( // shortened by alpha_to_1879, 2747
.i_in(r_v_buffer_e000[( 8+1)*`D_CS_GF_ORDER-1:( 8+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_008[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_009 SM_009 ( // shortened by alpha_to_1879, 531
.i_in(r_v_buffer_e000[( 9+1)*`D_CS_GF_ORDER-1:( 9+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_009[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_010 SM_010 ( // shortened by alpha_to_1879, 2410
.i_in(r_v_buffer_e000[( 10+1)*`D_CS_GF_ORDER-1:( 10+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_010[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_011 SM_011 ( // shortened by alpha_to_1879, 194
.i_in(r_v_buffer_e000[( 11+1)*`D_CS_GF_ORDER-1:( 11+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_011[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_012 SM_012 ( // shortened by alpha_to_1879, 2073
.i_in(r_v_buffer_e000[( 12+1)*`D_CS_GF_ORDER-1:( 12+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_012[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_013 SM_013 ( // shortened by alpha_to_1879, 3952
.i_in(r_v_buffer_e000[( 13+1)*`D_CS_GF_ORDER-1:( 13+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_013[`D_CS_GF_ORDER-1:0]) );
d_CS_shortening_matrix_alpha_to_014 SM_014 ( // shortened by alpha_to_1879, 1736
.i_in(r_v_buffer_e000[( 14+1)*`D_CS_GF_ORDER-1:( 14+0)*`D_CS_GF_ORDER]), .o_out(w_shortened_v_014[`D_CS_GF_ORDER-1:0]) );
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 14 * 8 = 112
d_CS_evaluation_matrix_slot_001_alpha_to_001 EM_S001_001 ( // evaluated by alpha_to_1, 1
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_002 EM_S001_002 ( // evaluated by alpha_to_1, 2
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_003 EM_S001_003 ( // evaluated by alpha_to_1, 3
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_004 EM_S001_004 ( // evaluated by alpha_to_1, 4
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_005 EM_S001_005 ( // evaluated by alpha_to_1, 5
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_006 EM_S001_006 ( // evaluated by alpha_to_1, 6
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_007 EM_S001_007 ( // evaluated by alpha_to_1, 7
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_008 EM_S001_008 ( // evaluated by alpha_to_1, 8
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_009 EM_S001_009 ( // evaluated by alpha_to_1, 9
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_010 EM_S001_010 ( // evaluated by alpha_to_1, 10
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_011 EM_S001_011 ( // evaluated by alpha_to_1, 11
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_012 EM_S001_012 ( // evaluated by alpha_to_1, 12
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_013 EM_S001_013 ( // evaluated by alpha_to_1, 13
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_001_alpha_to_014 EM_S001_014 ( // evaluated by alpha_to_1, 14
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S001_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_001 EM_S002_001 ( // evaluated by alpha_to_2, 2
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_002 EM_S002_002 ( // evaluated by alpha_to_2, 4
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_003 EM_S002_003 ( // evaluated by alpha_to_2, 6
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_004 EM_S002_004 ( // evaluated by alpha_to_2, 8
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_005 EM_S002_005 ( // evaluated by alpha_to_2, 10
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_006 EM_S002_006 ( // evaluated by alpha_to_2, 12
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_007 EM_S002_007 ( // evaluated by alpha_to_2, 14
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_008 EM_S002_008 ( // evaluated by alpha_to_2, 16
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_009 EM_S002_009 ( // evaluated by alpha_to_2, 18
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_010 EM_S002_010 ( // evaluated by alpha_to_2, 20
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_011 EM_S002_011 ( // evaluated by alpha_to_2, 22
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_012 EM_S002_012 ( // evaluated by alpha_to_2, 24
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_013 EM_S002_013 ( // evaluated by alpha_to_2, 26
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_002_alpha_to_014 EM_S002_014 ( // evaluated by alpha_to_2, 28
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S002_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_001 EM_S003_001 ( // evaluated by alpha_to_3, 3
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_002 EM_S003_002 ( // evaluated by alpha_to_3, 6
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_003 EM_S003_003 ( // evaluated by alpha_to_3, 9
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_004 EM_S003_004 ( // evaluated by alpha_to_3, 12
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_005 EM_S003_005 ( // evaluated by alpha_to_3, 15
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_006 EM_S003_006 ( // evaluated by alpha_to_3, 18
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_007 EM_S003_007 ( // evaluated by alpha_to_3, 21
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_008 EM_S003_008 ( // evaluated by alpha_to_3, 24
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_009 EM_S003_009 ( // evaluated by alpha_to_3, 27
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_010 EM_S003_010 ( // evaluated by alpha_to_3, 30
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_011 EM_S003_011 ( // evaluated by alpha_to_3, 33
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_012 EM_S003_012 ( // evaluated by alpha_to_3, 36
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_013 EM_S003_013 ( // evaluated by alpha_to_3, 39
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_003_alpha_to_014 EM_S003_014 ( // evaluated by alpha_to_3, 42
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S003_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_001 EM_S004_001 ( // evaluated by alpha_to_4, 4
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_002 EM_S004_002 ( // evaluated by alpha_to_4, 8
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_003 EM_S004_003 ( // evaluated by alpha_to_4, 12
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_004 EM_S004_004 ( // evaluated by alpha_to_4, 16
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_005 EM_S004_005 ( // evaluated by alpha_to_4, 20
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_006 EM_S004_006 ( // evaluated by alpha_to_4, 24
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_007 EM_S004_007 ( // evaluated by alpha_to_4, 28
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_008 EM_S004_008 ( // evaluated by alpha_to_4, 32
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_009 EM_S004_009 ( // evaluated by alpha_to_4, 36
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_010 EM_S004_010 ( // evaluated by alpha_to_4, 40
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_011 EM_S004_011 ( // evaluated by alpha_to_4, 44
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_012 EM_S004_012 ( // evaluated by alpha_to_4, 48
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_013 EM_S004_013 ( // evaluated by alpha_to_4, 52
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_004_alpha_to_014 EM_S004_014 ( // evaluated by alpha_to_4, 56
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S004_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_001 EM_S005_001 ( // evaluated by alpha_to_5, 5
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_002 EM_S005_002 ( // evaluated by alpha_to_5, 10
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_003 EM_S005_003 ( // evaluated by alpha_to_5, 15
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_004 EM_S005_004 ( // evaluated by alpha_to_5, 20
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_005 EM_S005_005 ( // evaluated by alpha_to_5, 25
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_006 EM_S005_006 ( // evaluated by alpha_to_5, 30
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_007 EM_S005_007 ( // evaluated by alpha_to_5, 35
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_008 EM_S005_008 ( // evaluated by alpha_to_5, 40
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_009 EM_S005_009 ( // evaluated by alpha_to_5, 45
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_010 EM_S005_010 ( // evaluated by alpha_to_5, 50
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_011 EM_S005_011 ( // evaluated by alpha_to_5, 55
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_012 EM_S005_012 ( // evaluated by alpha_to_5, 60
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_013 EM_S005_013 ( // evaluated by alpha_to_5, 65
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_005_alpha_to_014 EM_S005_014 ( // evaluated by alpha_to_5, 70
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S005_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_001 EM_S006_001 ( // evaluated by alpha_to_6, 6
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_002 EM_S006_002 ( // evaluated by alpha_to_6, 12
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_003 EM_S006_003 ( // evaluated by alpha_to_6, 18
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_004 EM_S006_004 ( // evaluated by alpha_to_6, 24
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_005 EM_S006_005 ( // evaluated by alpha_to_6, 30
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_006 EM_S006_006 ( // evaluated by alpha_to_6, 36
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_007 EM_S006_007 ( // evaluated by alpha_to_6, 42
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_008 EM_S006_008 ( // evaluated by alpha_to_6, 48
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_009 EM_S006_009 ( // evaluated by alpha_to_6, 54
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_010 EM_S006_010 ( // evaluated by alpha_to_6, 60
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_011 EM_S006_011 ( // evaluated by alpha_to_6, 66
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_012 EM_S006_012 ( // evaluated by alpha_to_6, 72
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_013 EM_S006_013 ( // evaluated by alpha_to_6, 78
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_006_alpha_to_014 EM_S006_014 ( // evaluated by alpha_to_6, 84
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S006_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_001 EM_S007_001 ( // evaluated by alpha_to_7, 7
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_002 EM_S007_002 ( // evaluated by alpha_to_7, 14
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_003 EM_S007_003 ( // evaluated by alpha_to_7, 21
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_004 EM_S007_004 ( // evaluated by alpha_to_7, 28
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_005 EM_S007_005 ( // evaluated by alpha_to_7, 35
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_006 EM_S007_006 ( // evaluated by alpha_to_7, 42
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_007 EM_S007_007 ( // evaluated by alpha_to_7, 49
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_008 EM_S007_008 ( // evaluated by alpha_to_7, 56
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_009 EM_S007_009 ( // evaluated by alpha_to_7, 63
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_010 EM_S007_010 ( // evaluated by alpha_to_7, 70
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_011 EM_S007_011 ( // evaluated by alpha_to_7, 77
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_012 EM_S007_012 ( // evaluated by alpha_to_7, 84
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_013 EM_S007_013 ( // evaluated by alpha_to_7, 91
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_007_alpha_to_014 EM_S007_014 ( // evaluated by alpha_to_7, 98
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S007_014[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_001 EM_S008_001 ( // evaluated by alpha_to_8, 8
.i_in(w_ELP_term_001[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_001[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_002 EM_S008_002 ( // evaluated by alpha_to_8, 16
.i_in(w_ELP_term_002[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_002[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_003 EM_S008_003 ( // evaluated by alpha_to_8, 24
.i_in(w_ELP_term_003[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_003[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_004 EM_S008_004 ( // evaluated by alpha_to_8, 32
.i_in(w_ELP_term_004[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_004[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_005 EM_S008_005 ( // evaluated by alpha_to_8, 40
.i_in(w_ELP_term_005[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_005[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_006 EM_S008_006 ( // evaluated by alpha_to_8, 48
.i_in(w_ELP_term_006[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_006[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_007 EM_S008_007 ( // evaluated by alpha_to_8, 56
.i_in(w_ELP_term_007[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_007[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_008 EM_S008_008 ( // evaluated by alpha_to_8, 64
.i_in(w_ELP_term_008[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_008[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_009 EM_S008_009 ( // evaluated by alpha_to_8, 72
.i_in(w_ELP_term_009[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_009[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_010 EM_S008_010 ( // evaluated by alpha_to_8, 80
.i_in(w_ELP_term_010[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_010[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_011 EM_S008_011 ( // evaluated by alpha_to_8, 88
.i_in(w_ELP_term_011[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_011[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_012 EM_S008_012 ( // evaluated by alpha_to_8, 96
.i_in(w_ELP_term_012[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_012[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_013 EM_S008_013 ( // evaluated by alpha_to_8, 104
.i_in(w_ELP_term_013[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_013[`D_CS_GF_ORDER-1:0]) );
d_CS_evaluation_matrix_slot_008_alpha_to_014 EM_S008_014 ( // evaluated by alpha_to_8, 112
.i_in(w_ELP_term_014[`D_CS_GF_ORDER-1:0]), .o_out(w_evaluated_term_S008_014[`D_CS_GF_ORDER-1:0]) );
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// total: 8, 8, 1
assign w_slot_001_flip = |( w_evaluated_term_S001_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S001_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_002_flip = |( w_evaluated_term_S002_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S002_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_003_flip = |( w_evaluated_term_S003_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S003_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_004_flip = |( w_evaluated_term_S004_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S004_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_005_flip = |( w_evaluated_term_S005_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S005_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_006_flip = |( w_evaluated_term_S006_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S006_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_007_flip = |( w_evaluated_term_S007_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S007_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_008_flip = |( w_evaluated_term_S008_000[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_001[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_002[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_003[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_004[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_005[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_006[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_007[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_008[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_009[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_010[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_011[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_012[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_013[`D_CS_GF_ORDER-1:0] ^ w_evaluated_term_S008_014[`D_CS_GF_ORDER-1:0] );
assign w_slot_001_flipped_message = ~( w_slot_001_flip ^ r_received_code_buffer[7] );
assign w_slot_002_flipped_message = ~( w_slot_002_flip ^ r_received_code_buffer[6] );
assign w_slot_003_flipped_message = ~( w_slot_003_flip ^ r_received_code_buffer[5] );
assign w_slot_004_flipped_message = ~( w_slot_004_flip ^ r_received_code_buffer[4] );
assign w_slot_005_flipped_message = ~( w_slot_005_flip ^ r_received_code_buffer[3] );
assign w_slot_006_flipped_message = ~( w_slot_006_flip ^ r_received_code_buffer[2] );
assign w_slot_007_flipped_message = ~( w_slot_007_flip ^ r_received_code_buffer[1] );
assign w_slot_008_flipped_message = ~( w_slot_008_flip ^ r_received_code_buffer[0] );
assign w_flipped_message[`D_CS_P_LVL-1:0] = { w_slot_001_flipped_message, w_slot_002_flipped_message, w_slot_003_flipped_message, w_slot_004_flipped_message, w_slot_005_flipped_message, w_slot_006_flipped_message, w_slot_007_flipped_message, w_slot_008_flipped_message };
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
endmodule
|
// a simple test case extracted from systemcaes (as included in iwls2005)
// this design has latches (or logic loops) for the two temp variables.
// this latches (or logic loops) must be removed in the final synthesis results
module aes(
// inputs
input [3:0] addroundkey_data_i,
input [3:0] addroundkey_data_reg,
input [3:0] addroundkey_round,
input [3:0] key_i,
input [3:0] keysched_new_key_o,
input [3:0] round,
input addroundkey_start_i,
input keysched_ready_o,
// outputs
output reg [3:0] keysched_last_key_i,
output reg [3:0] keysched_round_i,
output reg [3:0] next_addroundkey_data_reg,
output reg [3:0] next_addroundkey_round,
output reg [3:0] round_data_var,
output reg keysched_start_i,
output reg next_addroundkey_ready_o
);
// temp variables
reg [3:0] data_var;
reg [3:0] round_key_var;
always @*
begin
keysched_start_i = 0;
keysched_round_i = addroundkey_round;
round_data_var = addroundkey_data_reg;
next_addroundkey_data_reg = addroundkey_data_reg;
next_addroundkey_ready_o = 0;
next_addroundkey_round = addroundkey_round;
if (addroundkey_round == 1 || addroundkey_round == 0)
keysched_last_key_i = key_i;
else
keysched_last_key_i = keysched_new_key_o;
if (round == 0 && addroundkey_start_i)
begin
data_var = addroundkey_data_i;
round_key_var = key_i;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;
next_addroundkey_ready_o = 1;
end
else if (addroundkey_start_i && round != 0)
begin
keysched_last_key_i = key_i;
keysched_start_i = 1;
keysched_round_i = 1;
next_addroundkey_round = 1;
end
else if (addroundkey_round != round && keysched_ready_o)
begin
next_addroundkey_round = addroundkey_round + 1;
keysched_last_key_i = keysched_new_key_o;
keysched_start_i = 1;
keysched_round_i = addroundkey_round + 1;
end
else if (addroundkey_round == round && keysched_ready_o)
begin
data_var = addroundkey_data_i;
round_key_var = keysched_new_key_o;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;
next_addroundkey_ready_o = 1;
next_addroundkey_round = 0;
end
end
endmodule
|
module data_packet_fifo
( input reset,
input clock,
input [31:0]ram_data_in,
input write_enable,
output reg have_space,
output reg [31:0]ram_data_out,
output reg pkt_waiting,
output reg isfull,
output reg [1:0]usb_ram_packet_out,
output reg [1:0]usb_ram_packet_in,
input read_enable,
input pkt_complete,
input skip_packet) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 32 ;
parameter PKT_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [6:0] usb_ram_offset_out ;
//reg [1:0] usb_ram_packet_out ;
reg [6:0] usb_ram_offset_in ;
//reg [1:0] usb_ram_packet_in ;
wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
//reg isfull;
assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull ;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
else
pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0;
else
have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
/* RAM Writing/Reading process */
always @(posedge clock)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
ram_data_out <= usb_ram[usb_ram_aout] ;
end
/* RAM Write/Read Address process */
always @(posedge clock)
begin
if( reset )
begin
usb_ram_packet_out <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_offset_in <= 0 ;
usb_ram_packet_in <= 0 ;
isfull <= 0;
end
else
begin
if( skip_packet )
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
isfull <= 0;
end
else if(read_enable)
begin
if( usb_ram_offset_out == 7'b1111111 )
begin
isfull <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
end
if( pkt_complete )
begin
usb_ram_packet_in <= usb_ram_packet_in + 1 ;
usb_ram_offset_in <= 0 ;
if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
isfull <= 1 ;
end
else if( write_enable )
begin
if (usb_ram_offset_in == 7'b1111111)
usb_ram_offset_in <= 7'b1111111 ;
else
usb_ram_offset_in <= usb_ram_offset_in + 1 ;
end
end
end
endmodule
|
module br918d;
reg pass;
reg [1:0] v1, v2, v3, v4;
wire [3:0] w1, w2, w3, w4;
// Assign as pieces with matching strengths.
assign (pull1,strong0) w1[1:0] = v1;
assign (pull1,strong0) w1[1:0] = v2;
assign (pull1,strong0) w1[3:2] = v3;
assign (pull1,strong0) w1[3:2] = v4;
// Assign with a concat.
assign (pull1,strong0) w2 = {v3, v1};
assign (pull1,strong0) w2 = {v4, v2};
// Only assign part
assign (pull1,strong0) w3[1:0] = v1;
assign (pull1,strong0) w3[1:0] = v2;
// Assign as pieces with different strengths.
assign (pull1,strong0) w4[1:0] = v1;
assign (pull1,strong0) w4[1:0] = v2;
assign (strong1,pull0) w4[3:2] = v3;
assign (strong1,pull0) w4[3:2] = v4;
initial begin
pass = 1'b1;
v1 = 2'b00;
v2 = 2'b10;
v3 = 2'b11;
v4 = 2'b10;
#1;
// Check the assign as pieces (this is the same as br918a)
if (w1 !== 4'b1000) begin
$display("FAILED: assign with pieces (1), expected 4'b1000, got %b", w1);
pass = 1'b0;
end
// Check the assign with a concat.
if (w2 !== 4'b1000) begin
$display("FAILED: assign with concat, expected 4'b1000, got %b", w2);
pass = 1'b0;
end
// Check when only a piece is assigned (other compilers may return xx00).
if ((w3 !== 4'bzz00) && (w3 !== 4'bxx00)) begin
$display("FAILED: assign part, expected 4'bzz00 or 4'bxx00, got %b", w3);
pass = 1'b0;
end
// Check the assign as pieces (this is the same as br918a)
if (w4 !== 4'b1100) begin
$display("FAILED: assign with pieces (2), expected 4'b1000, got %b", w4);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_TB_V
`define SKY130_FD_SC_HDLL__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_TB_V
|
`default_nettype none
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH:0] ALM_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 1'b0) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
);
end
endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
) alm_i (
.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
.CI(ALM_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:18:50 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360;
NAND2X1TS U41 ( .A(n228), .B(n227), .Y(n229) );
NAND2X1TS U42 ( .A(n240), .B(n239), .Y(n241) );
NOR2X1TS U43 ( .A(n53), .B(n51), .Y(n320) );
NAND2XLTS U44 ( .A(n73), .B(n299), .Y(n300) );
NAND2X1TS U45 ( .A(n64), .B(n216), .Y(n211) );
NAND2XLTS U46 ( .A(n67), .B(n292), .Y(n293) );
NAND2XLTS U47 ( .A(n220), .B(n219), .Y(n221) );
NAND2X1TS U48 ( .A(n256), .B(n255), .Y(n257) );
NAND2X1TS U49 ( .A(n263), .B(n262), .Y(n264) );
NAND2X1TS U50 ( .A(n270), .B(n269), .Y(n271) );
NAND2XLTS U51 ( .A(n285), .B(n284), .Y(n287) );
NAND2XLTS U52 ( .A(n274), .B(n273), .Y(n275) );
NAND2XLTS U53 ( .A(n280), .B(n279), .Y(n281) );
NAND2X1TS U54 ( .A(n66), .B(n235), .Y(n236) );
CLKMX2X2TS U55 ( .A(in2[31]), .B(n209), .S0(add_sub), .Y(n210) );
INVX2TS U56 ( .A(n21), .Y(n327) );
NAND2X6TS U57 ( .A(n72), .B(n220), .Y(n206) );
NOR2X1TS U58 ( .A(n207), .B(in2[30]), .Y(n208) );
OR2X6TS U59 ( .A(n203), .B(in1[30]), .Y(n72) );
INVX2TS U60 ( .A(n235), .Y(n193) );
NOR2X2TS U61 ( .A(n283), .B(n278), .Y(n152) );
NAND2X2TS U62 ( .A(n231), .B(n66), .Y(n225) );
MX2X2TS U63 ( .A(in2[29]), .B(n201), .S0(add_sub), .Y(n202) );
MX2X2TS U64 ( .A(in2[28]), .B(n190), .S0(add_sub), .Y(n194) );
NAND2X2TS U65 ( .A(n18), .B(in1[26]), .Y(n239) );
NAND2X2TS U66 ( .A(n170), .B(in1[22]), .Y(n269) );
NAND2X2TS U67 ( .A(n150), .B(in1[20]), .Y(n279) );
OR2X4TS U68 ( .A(n192), .B(in1[27]), .Y(n66) );
NOR2X2TS U69 ( .A(n169), .B(in1[21]), .Y(n266) );
NAND2X2TS U70 ( .A(n171), .B(in1[23]), .Y(n262) );
NOR2X4TS U71 ( .A(n243), .B(n238), .Y(n231) );
NAND2X1TS U72 ( .A(n131), .B(in1[16]), .Y(n295) );
MX2X2TS U73 ( .A(in2[23]), .B(n154), .S0(n182), .Y(n171) );
OR2X4TS U74 ( .A(n138), .B(in1[18]), .Y(n70) );
OR2X4TS U75 ( .A(n137), .B(in1[17]), .Y(n67) );
NAND2X2TS U76 ( .A(n138), .B(in1[18]), .Y(n289) );
XNOR2X1TS U77 ( .A(n143), .B(in2[19]), .Y(n144) );
XOR2X2TS U78 ( .A(n161), .B(in2[22]), .Y(n162) );
NAND2X4TS U79 ( .A(n302), .B(n303), .Y(n37) );
OR2X2TS U80 ( .A(n188), .B(in2[27]), .Y(n197) );
NOR2X2TS U81 ( .A(n164), .B(in2[20]), .Y(n165) );
NOR2X2TS U82 ( .A(n142), .B(in2[18]), .Y(n143) );
CLKMX2X4TS U83 ( .A(in2[15]), .B(n124), .S0(n166), .Y(n125) );
NAND2X1TS U84 ( .A(n185), .B(n184), .Y(n188) );
NOR2X6TS U85 ( .A(n120), .B(in1[14]), .Y(n302) );
NOR2X4TS U86 ( .A(n198), .B(in2[24]), .Y(n177) );
NAND2X2TS U87 ( .A(n115), .B(in1[12]), .Y(n313) );
INVX2TS U88 ( .A(in2[26]), .Y(n184) );
NOR2X2TS U89 ( .A(n134), .B(in2[16]), .Y(n135) );
NOR2X2TS U90 ( .A(in2[25]), .B(in2[24]), .Y(n185) );
INVX2TS U91 ( .A(n157), .Y(n134) );
BUFX16TS U92 ( .A(n128), .Y(n157) );
OR2X6TS U93 ( .A(in1[9]), .B(n100), .Y(n49) );
NAND2X2TS U94 ( .A(n65), .B(n114), .Y(n111) );
OR2X4TS U95 ( .A(n98), .B(in1[8]), .Y(n68) );
OR2X2TS U96 ( .A(in2[21]), .B(in2[20]), .Y(n160) );
NAND2X6TS U97 ( .A(n100), .B(in1[9]), .Y(n326) );
NOR2X1TS U98 ( .A(in2[19]), .B(in2[18]), .Y(n145) );
NOR2X2TS U99 ( .A(in2[17]), .B(in2[16]), .Y(n146) );
NOR2X4TS U100 ( .A(n110), .B(n10), .Y(n106) );
NOR2X2TS U101 ( .A(in2[13]), .B(in2[12]), .Y(n122) );
AND2X6TS U102 ( .A(n45), .B(n44), .Y(n344) );
CLKINVX2TS U103 ( .A(n348), .Y(n79) );
INVX2TS U104 ( .A(in2[8]), .Y(n102) );
OR2X2TS U105 ( .A(in2[10]), .B(n9), .Y(n10) );
AND2X6TS U106 ( .A(n41), .B(n19), .Y(n11) );
INVX3TS U107 ( .A(n45), .Y(n43) );
CLKINVX6TS U108 ( .A(n9), .Y(n19) );
INVX2TS U109 ( .A(add_sub), .Y(n75) );
INVX12TS U110 ( .A(in2[4]), .Y(n23) );
NOR2X4TS U111 ( .A(in2[2]), .B(in2[1]), .Y(n87) );
AOI21X2TS U112 ( .A0(n88), .A1(n87), .B0(n75), .Y(n89) );
CLKINVX6TS U113 ( .A(in2[10]), .Y(n40) );
OAI21X2TS U114 ( .A0(n284), .A1(n278), .B0(n279), .Y(n151) );
INVX12TS U115 ( .A(in2[1]), .Y(n33) );
NAND2X6TS U116 ( .A(n69), .B(n29), .Y(n28) );
MXI2X2TS U117 ( .A(n130), .B(n129), .S0(n182), .Y(n131) );
NOR2X4TS U118 ( .A(n150), .B(in1[20]), .Y(n278) );
NOR2X4TS U119 ( .A(n171), .B(in1[23]), .Y(n261) );
NOR2X2TS U120 ( .A(n307), .B(n312), .Y(n118) );
INVX6TS U121 ( .A(n166), .Y(n85) );
OAI21XLTS U122 ( .A0(n327), .A1(n325), .B0(n326), .Y(n322) );
NAND2X1TS U123 ( .A(n70), .B(n289), .Y(n290) );
AND2X4TS U124 ( .A(n37), .B(n73), .Y(n7) );
NAND2X2TS U125 ( .A(n98), .B(in1[8]), .Y(n329) );
NAND2X2TS U126 ( .A(n104), .B(in1[10]), .Y(n323) );
NAND2X8TS U127 ( .A(n301), .B(n303), .Y(n38) );
NAND2X4TS U128 ( .A(n194), .B(in1[28]), .Y(n227) );
OR2X4TS U129 ( .A(n131), .B(in1[16]), .Y(n71) );
INVX4TS U130 ( .A(n11), .Y(n105) );
INVX2TS U131 ( .A(in1[5]), .Y(n44) );
BUFX12TS U132 ( .A(add_sub), .Y(n182) );
INVX2TS U133 ( .A(in2[7]), .Y(n82) );
INVX2TS U134 ( .A(in2[18]), .Y(n133) );
NAND2X4TS U135 ( .A(n39), .B(n233), .Y(n237) );
INVX2TS U136 ( .A(n268), .Y(n270) );
INVX2TS U137 ( .A(n261), .Y(n263) );
NAND2X4TS U138 ( .A(n191), .B(in1[25]), .Y(n244) );
NAND2X4TS U139 ( .A(n149), .B(in1[19]), .Y(n284) );
NOR2X4TS U140 ( .A(n191), .B(in1[25]), .Y(n243) );
NOR2X4TS U141 ( .A(n149), .B(in1[19]), .Y(n283) );
INVX4TS U142 ( .A(n289), .Y(n139) );
NAND2X4TS U143 ( .A(n116), .B(in1[13]), .Y(n308) );
NAND2X4TS U144 ( .A(n43), .B(in1[5]), .Y(n345) );
NOR4X2TS U145 ( .A(n155), .B(n160), .C(in2[23]), .D(in2[22]), .Y(n156) );
NAND2X2TS U146 ( .A(n146), .B(n145), .Y(n155) );
NOR2X4TS U147 ( .A(n57), .B(n54), .Y(n218) );
INVX6TS U148 ( .A(n249), .Y(n276) );
XOR2X1TS U149 ( .A(n291), .B(n290), .Y(res[18]) );
NAND2X4TS U150 ( .A(n56), .B(n196), .Y(n55) );
INVX4TS U151 ( .A(n196), .Y(n8) );
NAND2X2TS U152 ( .A(n210), .B(in1[31]), .Y(n216) );
OAI21X1TS U153 ( .A0(n316), .A1(n312), .B0(n313), .Y(n311) );
XOR2X1TS U154 ( .A(n321), .B(n320), .Y(res[11]) );
XOR2X1TS U155 ( .A(n316), .B(n315), .Y(res[12]) );
INVX4TS U156 ( .A(n292), .Y(n288) );
XOR2X1TS U157 ( .A(n328), .B(n327), .Y(res[9]) );
NAND2X4TS U158 ( .A(n169), .B(in1[21]), .Y(n273) );
MX2X4TS U159 ( .A(in2[19]), .B(n144), .S0(n182), .Y(n149) );
XOR2X2TS U160 ( .A(n165), .B(in2[21]), .Y(n168) );
XNOR2X2TS U161 ( .A(n135), .B(in2[17]), .Y(n136) );
OR2X6TS U162 ( .A(n125), .B(in1[15]), .Y(n73) );
NAND2X4TS U163 ( .A(n125), .B(in1[15]), .Y(n299) );
INVX4TS U164 ( .A(n317), .Y(n319) );
NAND2X6TS U165 ( .A(n120), .B(in1[14]), .Y(n303) );
INVX6TS U166 ( .A(n326), .Y(n29) );
XOR2XLTS U167 ( .A(n343), .B(n342), .Y(res[6]) );
XOR2X1TS U168 ( .A(n339), .B(n338), .Y(res[7]) );
NOR2X6TS U169 ( .A(n108), .B(in1[11]), .Y(n317) );
OAI21XLTS U170 ( .A0(n354), .A1(n75), .B0(n353), .Y(res[3]) );
OAI21XLTS U171 ( .A0(n357), .A1(n85), .B0(n356), .Y(res[4]) );
OAI21XLTS U172 ( .A0(n350), .A1(n75), .B0(n349), .Y(res[2]) );
OAI21XLTS U173 ( .A0(n360), .A1(n85), .B0(n359), .Y(res[1]) );
OR2X1TS U174 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
AND2X2TS U175 ( .A(in2[4]), .B(add_sub), .Y(n17) );
OA21X2TS U176 ( .A0(add_sub), .A1(in2[4]), .B0(in1[4]), .Y(n77) );
INVX2TS U177 ( .A(n232), .Y(n233) );
NOR2X8TS U178 ( .A(n116), .B(in1[13]), .Y(n307) );
NAND3X6TS U179 ( .A(n77), .B(n76), .C(n46), .Y(n45) );
INVX4TS U180 ( .A(n212), .Y(n220) );
AND2X6TS U181 ( .A(n358), .B(n33), .Y(n12) );
OAI21X2TS U182 ( .A0(n262), .A1(n254), .B0(n255), .Y(n173) );
NOR2X4TS U183 ( .A(n172), .B(in1[24]), .Y(n254) );
XNOR2X2TS U184 ( .A(n215), .B(n214), .Y(res[30]) );
NAND3X8TS U185 ( .A(n30), .B(n27), .C(n318), .Y(n306) );
NAND2X8TS U186 ( .A(n52), .B(n31), .Y(n30) );
MXI2X8TS U187 ( .A(n184), .B(n183), .S0(n182), .Y(n18) );
XNOR2X1TS U188 ( .A(n142), .B(in2[18]), .Y(n132) );
NAND2X4TS U189 ( .A(n157), .B(n146), .Y(n142) );
XOR2X2TS U190 ( .A(n65), .B(in2[12]), .Y(n113) );
NOR2X4TS U191 ( .A(n115), .B(in1[12]), .Y(n312) );
NOR2X4TS U192 ( .A(n202), .B(in1[29]), .Y(n212) );
XNOR2X2TS U193 ( .A(n200), .B(in2[29]), .Y(n201) );
NOR3X6TS U194 ( .A(n198), .B(in2[28]), .C(n197), .Y(n200) );
XNOR2X1TS U195 ( .A(n222), .B(n221), .Y(res[29]) );
NAND2X4TS U196 ( .A(n137), .B(in1[17]), .Y(n292) );
XOR2X4TS U197 ( .A(n207), .B(in2[30]), .Y(n199) );
NAND2X6TS U198 ( .A(n24), .B(n23), .Y(n95) );
NOR2X4TS U199 ( .A(n32), .B(n317), .Y(n31) );
NAND2X6TS U200 ( .A(n61), .B(n59), .Y(n217) );
AO21X2TS U201 ( .A0(n72), .A1(n205), .B0(n204), .Y(n14) );
AND3X8TS U202 ( .A(n36), .B(n295), .C(n35), .Y(n13) );
NAND2X8TS U203 ( .A(n53), .B(n319), .Y(n27) );
MXI2X4TS U204 ( .A(n40), .B(n103), .S0(n182), .Y(n104) );
NAND2X8TS U205 ( .A(n223), .B(n62), .Y(n61) );
OR2X4TS U206 ( .A(n210), .B(in1[31]), .Y(n64) );
NAND2BX4TS U207 ( .AN(in2[29]), .B(n200), .Y(n207) );
XNOR2X2TS U208 ( .A(n217), .B(n211), .Y(res[31]) );
OAI21X4TS U209 ( .A0(n307), .A1(n313), .B0(n308), .Y(n117) );
MXI2X4TS U210 ( .A(n114), .B(n113), .S0(n166), .Y(n115) );
NOR2X4TS U211 ( .A(n206), .B(n8), .Y(n62) );
AOI21X4TS U212 ( .A0(n306), .A1(n118), .B0(n117), .Y(n301) );
NAND2X6TS U213 ( .A(n49), .B(n69), .Y(n32) );
NAND2X2TS U214 ( .A(n71), .B(n126), .Y(n35) );
NAND2X4TS U215 ( .A(n70), .B(n67), .Y(n141) );
NAND2X4TS U216 ( .A(n174), .B(n260), .Y(n176) );
NAND2X2TS U217 ( .A(n85), .B(in2[7]), .Y(n84) );
MXI2X4TS U218 ( .A(n101), .B(n99), .S0(n166), .Y(n100) );
INVX2TS U219 ( .A(in2[9]), .Y(n101) );
MX2X4TS U220 ( .A(in2[13]), .B(n112), .S0(n182), .Y(n116) );
INVX2TS U221 ( .A(in2[16]), .Y(n130) );
MX2X4TS U222 ( .A(in2[17]), .B(n136), .S0(n182), .Y(n137) );
INVX2TS U223 ( .A(n332), .Y(n341) );
INVX2TS U224 ( .A(n333), .Y(n334) );
NAND2X4TS U225 ( .A(n92), .B(in1[7]), .Y(n336) );
INVX2TS U226 ( .A(n69), .Y(n48) );
CLKBUFX2TS U227 ( .A(n52), .Y(n21) );
INVX2TS U228 ( .A(n306), .Y(n316) );
NOR2X4TS U229 ( .A(n170), .B(in1[22]), .Y(n268) );
NAND2X6TS U230 ( .A(n202), .B(in1[29]), .Y(n219) );
INVX2TS U231 ( .A(n12), .Y(n47) );
CLKINVX6TS U232 ( .A(in2[5]), .Y(n24) );
NOR2X4TS U233 ( .A(in2[5]), .B(in2[6]), .Y(n80) );
INVX2TS U234 ( .A(in2[12]), .Y(n114) );
NAND2BX2TS U235 ( .AN(n109), .B(n19), .Y(n26) );
NOR2X4TS U236 ( .A(n261), .B(n254), .Y(n174) );
NOR2X4TS U237 ( .A(in2[3]), .B(in2[4]), .Y(n81) );
XNOR2X1TS U238 ( .A(n198), .B(in2[24]), .Y(n158) );
INVX2TS U239 ( .A(n176), .Y(n56) );
NOR2X4TS U240 ( .A(n225), .B(n226), .Y(n196) );
INVX2TS U241 ( .A(n195), .Y(n58) );
INVX2TS U242 ( .A(n219), .Y(n205) );
INVX2TS U243 ( .A(n213), .Y(n204) );
INVX2TS U244 ( .A(n266), .Y(n274) );
INVX2TS U245 ( .A(n273), .Y(n267) );
NOR2X4TS U246 ( .A(n268), .B(n266), .Y(n260) );
OAI21X1TS U247 ( .A0(n251), .A1(n261), .B0(n262), .Y(n252) );
NOR2X1TS U248 ( .A(n250), .B(n261), .Y(n253) );
INVX2TS U249 ( .A(n260), .Y(n250) );
NAND2X2TS U250 ( .A(n172), .B(in1[24]), .Y(n255) );
CLKBUFX2TS U251 ( .A(n248), .Y(n249) );
NAND2X2TS U252 ( .A(n192), .B(in1[27]), .Y(n235) );
INVX2TS U253 ( .A(n231), .Y(n234) );
AOI21X1TS U254 ( .A0(n195), .A1(n60), .B0(n14), .Y(n59) );
INVX2TS U255 ( .A(n206), .Y(n60) );
NAND2X1TS U256 ( .A(n346), .B(n345), .Y(n347) );
NAND2X1TS U257 ( .A(n341), .B(n333), .Y(n342) );
INVX2TS U258 ( .A(n340), .Y(n343) );
NAND2X1TS U259 ( .A(n337), .B(n336), .Y(n338) );
INVX2TS U260 ( .A(n335), .Y(n337) );
NAND2X1TS U261 ( .A(n68), .B(n329), .Y(n330) );
NAND2X1TS U262 ( .A(n49), .B(n326), .Y(n328) );
NAND2X1TS U263 ( .A(n69), .B(n323), .Y(n324) );
NAND2X1TS U264 ( .A(n319), .B(n318), .Y(n321) );
NOR3X1TS U265 ( .A(n327), .B(n325), .C(n48), .Y(n51) );
NAND2X1TS U266 ( .A(n314), .B(n313), .Y(n315) );
INVX2TS U267 ( .A(n312), .Y(n314) );
NAND2X1TS U268 ( .A(n309), .B(n308), .Y(n310) );
INVX2TS U269 ( .A(n307), .Y(n309) );
NAND2X1TS U270 ( .A(n304), .B(n303), .Y(n305) );
INVX2TS U271 ( .A(n302), .Y(n304) );
NAND2X1TS U272 ( .A(n34), .B(n299), .Y(n297) );
NAND2X1TS U273 ( .A(n71), .B(n295), .Y(n296) );
NAND2X1TS U274 ( .A(n38), .B(n7), .Y(n34) );
XOR2X1TS U275 ( .A(n287), .B(n286), .Y(res[19]) );
INVX2TS U276 ( .A(n283), .Y(n285) );
XNOR2X1TS U277 ( .A(n282), .B(n281), .Y(res[20]) );
OAI21X2TS U278 ( .A0(n286), .A1(n283), .B0(n284), .Y(n282) );
XNOR2X1TS U279 ( .A(n276), .B(n275), .Y(res[21]) );
XOR2X1TS U280 ( .A(n247), .B(n246), .Y(res[25]) );
NAND2X1TS U281 ( .A(n245), .B(n244), .Y(n246) );
INVX2TS U282 ( .A(n243), .Y(n245) );
INVX2TS U283 ( .A(n238), .Y(n240) );
INVX2TS U284 ( .A(n226), .Y(n228) );
NAND2X1TS U285 ( .A(n72), .B(n213), .Y(n214) );
NAND2X2TS U286 ( .A(n63), .B(n216), .Y(res[32]) );
NAND2X4TS U287 ( .A(n217), .B(n64), .Y(n63) );
NAND2BX2TS U288 ( .AN(in2[11]), .B(n40), .Y(n109) );
CLKINVX6TS U289 ( .A(n198), .Y(n180) );
NAND2X8TS U290 ( .A(n157), .B(n156), .Y(n198) );
CLKINVX1TS U291 ( .A(n13), .Y(n294) );
CLKINVX1TS U292 ( .A(n277), .Y(n286) );
XNOR2X1TS U293 ( .A(n294), .B(n293), .Y(res[17]) );
AOI21X1TS U294 ( .A0(n294), .A1(n67), .B0(n288), .Y(n291) );
NAND2X2TS U295 ( .A(n108), .B(in1[11]), .Y(n318) );
XOR2X2TS U296 ( .A(n110), .B(n102), .Y(n97) );
NOR2X4TS U297 ( .A(n110), .B(in2[8]), .Y(n22) );
AND2X8TS U298 ( .A(n358), .B(n33), .Y(n20) );
OR2X4TS U299 ( .A(in2[8]), .B(in2[9]), .Y(n9) );
CLKINVX12TS U300 ( .A(n95), .Y(n42) );
NOR2X8TS U301 ( .A(n92), .B(in1[7]), .Y(n335) );
OA21X4TS U302 ( .A0(n335), .A1(n333), .B0(n336), .Y(n16) );
INVX16TS U303 ( .A(in2[0]), .Y(n358) );
NAND2X4TS U304 ( .A(n91), .B(in1[6]), .Y(n333) );
BUFX12TS U305 ( .A(add_sub), .Y(n166) );
NOR2X4TS U306 ( .A(n335), .B(n332), .Y(n90) );
INVX8TS U307 ( .A(n15), .Y(n223) );
OR2X4TS U308 ( .A(n234), .B(n15), .Y(n39) );
OA21X4TS U309 ( .A0(n248), .A1(n176), .B0(n175), .Y(n15) );
OAI21XLTS U310 ( .A0(n301), .A1(n302), .B0(n303), .Y(n298) );
INVX2TS U311 ( .A(n299), .Y(n126) );
INVX2TS U312 ( .A(n49), .Y(n325) );
OAI21X4TS U313 ( .A0(n238), .A1(n244), .B0(n239), .Y(n232) );
XOR2X4TS U314 ( .A(n22), .B(in2[9]), .Y(n99) );
NOR2X8TS U315 ( .A(n25), .B(n355), .Y(n41) );
NAND2X8TS U316 ( .A(n42), .B(n96), .Y(n25) );
NOR2X8TS U317 ( .A(n110), .B(n26), .Y(n65) );
OAI21X4TS U318 ( .A0(n268), .A1(n273), .B0(n269), .Y(n259) );
NAND2X8TS U319 ( .A(n323), .B(n28), .Y(n53) );
NAND3X8TS U320 ( .A(n71), .B(n38), .C(n7), .Y(n36) );
INVX12TS U321 ( .A(n223), .Y(n247) );
INVX12TS U322 ( .A(n41), .Y(n110) );
XOR2X4TS U323 ( .A(n105), .B(n40), .Y(n103) );
NAND2X8TS U324 ( .A(n20), .B(n94), .Y(n355) );
XOR2X4TS U325 ( .A(n111), .B(in2[13]), .Y(n112) );
MXI2X4TS U326 ( .A(n121), .B(n119), .S0(n166), .Y(n120) );
XNOR2X4TS U327 ( .A(n181), .B(in2[26]), .Y(n183) );
OAI21X4TS U328 ( .A0(n218), .A1(n212), .B0(n219), .Y(n215) );
NAND2BX4TS U329 ( .AN(n155), .B(n157), .Y(n164) );
MXI2X4TS U330 ( .A(n148), .B(n147), .S0(n166), .Y(n150) );
OAI21X4TS U331 ( .A0(n79), .A1(n344), .B0(n345), .Y(n340) );
OAI21X4TS U332 ( .A0(n78), .A1(n47), .B0(n17), .Y(n46) );
NAND2X8TS U333 ( .A(n50), .B(n329), .Y(n52) );
NAND2X8TS U334 ( .A(n331), .B(n68), .Y(n50) );
NOR2X4TS U335 ( .A(n248), .B(n55), .Y(n54) );
OAI21X4TS U336 ( .A0(n175), .A1(n8), .B0(n58), .Y(n57) );
XOR2X2TS U337 ( .A(n265), .B(n264), .Y(res[23]) );
XOR2X2TS U338 ( .A(n258), .B(n257), .Y(res[24]) );
XOR2X2TS U339 ( .A(n272), .B(n271), .Y(res[22]) );
XNOR2X1TS U340 ( .A(n331), .B(n330), .Y(res[8]) );
XNOR2X1TS U341 ( .A(n297), .B(n296), .Y(res[16]) );
NOR2X8TS U342 ( .A(in2[3]), .B(in2[2]), .Y(n94) );
XOR2X4TS U343 ( .A(n74), .B(in2[5]), .Y(n348) );
NAND2X6TS U344 ( .A(n340), .B(n90), .Y(n93) );
AOI21X1TS U345 ( .A0(n341), .A1(n340), .B0(n334), .Y(n339) );
OR2X8TS U346 ( .A(n104), .B(in1[10]), .Y(n69) );
NOR2X4TS U347 ( .A(in2[7]), .B(in2[6]), .Y(n96) );
NOR2X2TS U348 ( .A(n164), .B(n160), .Y(n161) );
NOR2X4TS U349 ( .A(n91), .B(in1[6]), .Y(n332) );
MX2X4TS U350 ( .A(in2[11]), .B(n107), .S0(n182), .Y(n108) );
INVX2TS U351 ( .A(n259), .Y(n251) );
INVX2TS U352 ( .A(n344), .Y(n346) );
INVX2TS U353 ( .A(in2[2]), .Y(n351) );
AOI31X2TS U354 ( .A0(n12), .A1(n81), .A2(n351), .B0(n75), .Y(n74) );
INVX2TS U355 ( .A(n94), .Y(n78) );
NAND3X2TS U356 ( .A(n94), .B(n12), .C(n23), .Y(n76) );
NAND4X2TS U357 ( .A(n81), .B(n87), .C(n358), .D(n80), .Y(n83) );
XOR2X4TS U358 ( .A(n83), .B(n82), .Y(n86) );
OAI21X4TS U359 ( .A0(n86), .A1(n85), .B0(n84), .Y(n92) );
NOR3X4TS U360 ( .A(n95), .B(in2[3]), .C(in2[0]), .Y(n88) );
XOR2X4TS U361 ( .A(n89), .B(in2[6]), .Y(n91) );
NAND2X8TS U362 ( .A(n93), .B(n16), .Y(n331) );
MXI2X4TS U363 ( .A(n102), .B(n97), .S0(n166), .Y(n98) );
XNOR2X4TS U364 ( .A(n106), .B(in2[11]), .Y(n107) );
INVX2TS U365 ( .A(in2[14]), .Y(n121) );
NAND2X8TS U366 ( .A(n65), .B(n122), .Y(n127) );
XNOR2X1TS U367 ( .A(in2[14]), .B(n127), .Y(n119) );
NAND3X1TS U368 ( .A(n65), .B(n122), .C(n121), .Y(n123) );
XOR2X1TS U369 ( .A(n123), .B(in2[15]), .Y(n124) );
NOR3X8TS U370 ( .A(n127), .B(in2[15]), .C(in2[14]), .Y(n128) );
XOR2X4TS U371 ( .A(n157), .B(in2[16]), .Y(n129) );
MXI2X4TS U372 ( .A(n133), .B(n132), .S0(n182), .Y(n138) );
AOI21X4TS U373 ( .A0(n288), .A1(n70), .B0(n139), .Y(n140) );
OAI21X4TS U374 ( .A0(n13), .A1(n141), .B0(n140), .Y(n277) );
INVX2TS U375 ( .A(in2[20]), .Y(n148) );
XNOR2X1TS U376 ( .A(n164), .B(in2[20]), .Y(n147) );
AOI21X4TS U377 ( .A0(n277), .A1(n152), .B0(n151), .Y(n248) );
NOR3X4TS U378 ( .A(n164), .B(in2[22]), .C(n160), .Y(n153) );
XNOR2X2TS U379 ( .A(n153), .B(in2[23]), .Y(n154) );
INVX2TS U380 ( .A(in2[24]), .Y(n159) );
MXI2X2TS U381 ( .A(n159), .B(n158), .S0(n166), .Y(n172) );
INVX2TS U382 ( .A(in2[22]), .Y(n163) );
MXI2X4TS U383 ( .A(n163), .B(n162), .S0(n182), .Y(n170) );
INVX2TS U384 ( .A(in2[21]), .Y(n167) );
MXI2X4TS U385 ( .A(n168), .B(n167), .S0(n85), .Y(n169) );
AOI21X4TS U386 ( .A0(n259), .A1(n174), .B0(n173), .Y(n175) );
XOR2X4TS U387 ( .A(n177), .B(in2[25]), .Y(n179) );
INVX2TS U388 ( .A(in2[25]), .Y(n178) );
MXI2X4TS U389 ( .A(n179), .B(n178), .S0(n85), .Y(n191) );
NAND2X4TS U390 ( .A(n180), .B(n185), .Y(n181) );
NOR2X8TS U391 ( .A(n18), .B(in1[26]), .Y(n238) );
NOR2X4TS U392 ( .A(n198), .B(n188), .Y(n186) );
XNOR2X4TS U393 ( .A(n186), .B(in2[27]), .Y(n187) );
MX2X4TS U394 ( .A(in2[27]), .B(n187), .S0(add_sub), .Y(n192) );
NOR2X1TS U395 ( .A(n198), .B(n197), .Y(n189) );
XNOR2X1TS U396 ( .A(n189), .B(in2[28]), .Y(n190) );
NOR2X8TS U397 ( .A(n194), .B(in1[28]), .Y(n226) );
AOI21X4TS U398 ( .A0(n66), .A1(n232), .B0(n193), .Y(n224) );
OAI21X4TS U399 ( .A0(n224), .A1(n226), .B0(n227), .Y(n195) );
MX2X4TS U400 ( .A(in2[30]), .B(n199), .S0(add_sub), .Y(n203) );
NAND2X4TS U401 ( .A(n203), .B(in1[30]), .Y(n213) );
XNOR2X1TS U402 ( .A(n208), .B(in2[31]), .Y(n209) );
INVX2TS U403 ( .A(n218), .Y(n222) );
OAI21X4TS U404 ( .A0(n247), .A1(n225), .B0(n224), .Y(n230) );
XNOR2X4TS U405 ( .A(n230), .B(n229), .Y(res[28]) );
XNOR2X2TS U406 ( .A(n237), .B(n236), .Y(res[27]) );
OAI21X4TS U407 ( .A0(n247), .A1(n243), .B0(n244), .Y(n242) );
XNOR2X4TS U408 ( .A(n242), .B(n241), .Y(res[26]) );
AOI21X4TS U409 ( .A0(n276), .A1(n253), .B0(n252), .Y(n258) );
INVX2TS U410 ( .A(n254), .Y(n256) );
AOI21X4TS U411 ( .A0(n276), .A1(n260), .B0(n259), .Y(n265) );
AOI21X4TS U412 ( .A0(n276), .A1(n274), .B0(n267), .Y(n272) );
INVX2TS U413 ( .A(n278), .Y(n280) );
XNOR2X1TS U414 ( .A(n298), .B(n300), .Y(res[15]) );
XOR2XLTS U415 ( .A(n301), .B(n305), .Y(res[14]) );
XNOR2X1TS U416 ( .A(n311), .B(n310), .Y(res[13]) );
XNOR2X1TS U417 ( .A(n322), .B(n324), .Y(res[10]) );
XNOR2X1TS U418 ( .A(n348), .B(n347), .Y(res[5]) );
XNOR2X1TS U419 ( .A(n12), .B(n351), .Y(n350) );
AOI21X1TS U420 ( .A0(n85), .A1(in2[2]), .B0(in1[2]), .Y(n349) );
NAND2X1TS U421 ( .A(n12), .B(n351), .Y(n352) );
XNOR2X1TS U422 ( .A(n352), .B(in2[3]), .Y(n354) );
AOI21X1TS U423 ( .A0(n85), .A1(in2[3]), .B0(in1[3]), .Y(n353) );
XNOR2X1TS U424 ( .A(in2[4]), .B(n355), .Y(n357) );
AOI21X1TS U425 ( .A0(n85), .A1(in2[4]), .B0(in1[4]), .Y(n356) );
XOR2X1TS U426 ( .A(n358), .B(in2[1]), .Y(n360) );
AOI21X1TS U427 ( .A0(n85), .A1(in2[1]), .B0(in1[1]), .Y(n359) );
initial $sdf_annotate("Approx_adder_LOALPL5_syn.sdf");
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
hdmi_ref_clk,
hdmi_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_empty,
vdma_almost_empty,
vdma_valid,
vdma_data,
vdma_be,
vdma_last,
vdma_ready,
up_status,
debug_trigger,
debug_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
input hdmi_ref_clk;
output hdmi_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [35:0] hdmi_data;
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_empty;
input vdma_almost_empty;
input vdma_valid;
input [63:0] vdma_data;
input [ 7:0] vdma_be;
input vdma_last;
output vdma_ready;
output [ 7:0] up_status;
output [ 7:0] debug_trigger;
output [63:0] debug_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_hdmi_tx_36b i_hdmi_tx_36b (
.hdmi_clk (hdmi_ref_clk),
.hdmi_vsync (hdmi_vsync),
.hdmi_hsync (hdmi_hsync),
.hdmi_data_e (hdmi_data_e),
.hdmi_data (hdmi_data),
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_be (vdma_be),
.vdma_data (vdma_data),
.vdma_last (vdma_last),
.vdma_ready (vdma_ready),
.debug_trigger (debug_trigger),
.debug_data (debug_data),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status));
ODDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
i_ddr_hdmi_clk (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_ref_clk),
.Q (hdmi_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:10.0
// IP Revision: 128000
`timescale 1ns/1ps
module golden_ticket_fifo (
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
fifo_generator_v10_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(2),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1021),
.C_PROG_FULL_THRESH_NEGATE_VAL(1020),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(8),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'B0),
.backup_marker(1'B0),
.clk(1'B0),
.rst(1'B0),
.srst(1'B0),
.wr_clk(wr_clk),
.wr_rst(1'B0),
.rd_clk(rd_clk),
.rd_rst(1'B0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'B0),
.injectdbiterr(1'B0),
.injectsbiterr(1'B0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'B0),
.s_aclk(1'B0),
.s_aresetn(1'B0),
.m_aclk_en(1'B0),
.s_aclk_en(1'B0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(2'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'B0),
.s_axi_awready(),
.s_axi_wid(4'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'B0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'B0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'B0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'B0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'B0),
.m_axi_bid(4'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'B0),
.m_axi_bready(),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(2'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'B0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'B0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'B0),
.m_axi_rid(4'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'B0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'B0),
.m_axi_rready(),
.s_axis_tvalid(1'B0),
.s_axis_tready(),
.s_axis_tdata(64'B0),
.s_axis_tstrb(8'B0),
.s_axis_tkeep(8'B0),
.s_axis_tlast(1'B0),
.s_axis_tid(8'B0),
.s_axis_tdest(4'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'B0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'B0),
.axi_aw_injectdbiterr(1'B0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'B0),
.axi_w_injectdbiterr(1'B0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'B0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'B0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'B0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'B0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'B0),
.axi_r_injectdbiterr(1'B0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'B0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'B0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
module tb_gmii2fifo9();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [8:0] din;
reg full;
wire wr_en;
wire wr_clk;
gmii2fifo9 # (
.Gap(4'h2)
) gmii2fifo9_tb (
.sys_rst(sys_rst),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge wr_clk) begin
if (wr_en == 1'b1)
$display("din: %x", din);
end
reg [8:0] rom [0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv,phy_rxd} <= rom[ counter ];
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo9);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
full = 1'b0;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof. intros. rewrite H. rewrite H0. reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros. rewrite H. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof. intros. destruct n. reflexivity. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof. intros. rewrite H. rewrite H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros.
destruct b.
destruct c.
reflexivity.
inversion H.
simpl in H. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
int cnt_ar2d;
// sizes
int siz_bit ;
int siz_byte;
int siz_int ;
int siz_ar1d;
int siz_ar2d;
// add all counters
assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
// finish report
always @ (posedge clk)
if (cnt == 5) begin
if (siz_bit != 1) $stop();
if (siz_byte != 8) $stop();
if (siz_int != 32) $stop();
if (siz_ar1d != 24) $stop();
if (siz_ar2d != 16) $stop();
end else if (cnt > 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
// instances with various types
mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit );
mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int );
mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
endmodule : t
module mod_typ #(
parameter type TYP = byte
)(
input logic clk,
output TYP cnt = 0,
output int siz
);
always @ (posedge clk)
cnt <= cnt + 1;
assign siz = $bits (cnt);
endmodule
|
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module fjmem #(
parameter adr_width = 24
) (
input sys_clk,
input sys_rst,
/* flash */
output [adr_width-1:0] flash_adr,
inout [15:0] flash_d,
output flash_oe_n,
output flash_we_n,
/* debug output */
output fjmem_update
);
wire jtag_tck;
wire jtag_rst;
wire jtag_update;
wire jtag_shift;
wire jtag_tdi;
wire jtag_tdo;
fjmem_core #(
.adr_width(adr_width)
) core (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* jtag */
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
/* flash */
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
/* debug */
.fjmem_update(fjmem_update)
);
fjmem_jtag jtag (
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s6s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_BLACKBOX_V
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test checks that the upwards search for a name stops at a
* module boundary. In this example, the q variable in the instance
* "inst" of the test module should be an implicit wire, even though
* it is placed into the containing main scope that has a wire q in it.
*/
module test(p);
output p;
wire q = 1;
assign p = q;
endmodule // test
module main;
wire q = 0;
wire sig;
test inst(sig);
initial begin
#1 if (q !== 1'b0) begin
$display("FAILED -- main.q == %b", q);
$finish;
end
if (sig !== 1'b1) begin
$display("FAILED -- main.test.q == %b", sig);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// CONFIG:
// NUM_COEFF = 50
// PIPLINED = 1
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 25)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 50;
parameter N_UNIQ = 25; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 57;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 50;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
reg [dw-1:0] COEFFICIENT_11;
reg [dw-1:0] COEFFICIENT_12;
reg [dw-1:0] COEFFICIENT_13;
reg [dw-1:0] COEFFICIENT_14;
reg [dw-1:0] COEFFICIENT_15;
reg [dw-1:0] COEFFICIENT_16;
reg [dw-1:0] COEFFICIENT_17;
reg [dw-1:0] COEFFICIENT_18;
reg [dw-1:0] COEFFICIENT_19;
reg [dw-1:0] COEFFICIENT_20;
reg [dw-1:0] COEFFICIENT_21;
reg [dw-1:0] COEFFICIENT_22;
reg [dw-1:0] COEFFICIENT_23;
reg [dw-1:0] COEFFICIENT_24;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
COEFFICIENT_11 <= -18'd319;
COEFFICIENT_12 <= -18'd178;
COEFFICIENT_13 <= 18'd0;
COEFFICIENT_14 <= 18'd212;
COEFFICIENT_15 <= 18'd451;
COEFFICIENT_16 <= 18'd710;
COEFFICIENT_17 <= 18'd980;
COEFFICIENT_18 <= 18'd1252;
COEFFICIENT_19 <= 18'd1514;
COEFFICIENT_20 <= 18'd1756;
COEFFICIENT_21 <= 18'd1971;
COEFFICIENT_22 <= 18'd2147;
COEFFICIENT_23 <= 18'd2278;
COEFFICIENT_24 <= 18'd2360;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
wire [dw-1:0] INPUT_PIPELINE_REG_22;
wire [dw-1:0] INPUT_PIPELINE_REG_23;
wire [dw-1:0] INPUT_PIPELINE_REG_24;
wire [dw-1:0] INPUT_PIPELINE_REG_25;
wire [dw-1:0] INPUT_PIPELINE_REG_26;
wire [dw-1:0] INPUT_PIPELINE_REG_27;
wire [dw-1:0] INPUT_PIPELINE_REG_28;
wire [dw-1:0] INPUT_PIPELINE_REG_29;
wire [dw-1:0] INPUT_PIPELINE_REG_30;
wire [dw-1:0] INPUT_PIPELINE_REG_31;
wire [dw-1:0] INPUT_PIPELINE_REG_32;
wire [dw-1:0] INPUT_PIPELINE_REG_33;
wire [dw-1:0] INPUT_PIPELINE_REG_34;
wire [dw-1:0] INPUT_PIPELINE_REG_35;
wire [dw-1:0] INPUT_PIPELINE_REG_36;
wire [dw-1:0] INPUT_PIPELINE_REG_37;
wire [dw-1:0] INPUT_PIPELINE_REG_38;
wire [dw-1:0] INPUT_PIPELINE_REG_39;
wire [dw-1:0] INPUT_PIPELINE_REG_40;
wire [dw-1:0] INPUT_PIPELINE_REG_41;
wire [dw-1:0] INPUT_PIPELINE_REG_42;
wire [dw-1:0] INPUT_PIPELINE_REG_43;
wire [dw-1:0] INPUT_PIPELINE_REG_44;
wire [dw-1:0] INPUT_PIPELINE_REG_45;
wire [dw-1:0] INPUT_PIPELINE_REG_46;
wire [dw-1:0] INPUT_PIPELINE_REG_47;
wire [dw-1:0] INPUT_PIPELINE_REG_48;
wire [dw-1:0] INPUT_PIPELINE_REG_49;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.pipeline_reg_22(INPUT_PIPELINE_REG_22),
.pipeline_reg_23(INPUT_PIPELINE_REG_23),
.pipeline_reg_24(INPUT_PIPELINE_REG_24),
.pipeline_reg_25(INPUT_PIPELINE_REG_25),
.pipeline_reg_26(INPUT_PIPELINE_REG_26),
.pipeline_reg_27(INPUT_PIPELINE_REG_27),
.pipeline_reg_28(INPUT_PIPELINE_REG_28),
.pipeline_reg_29(INPUT_PIPELINE_REG_29),
.pipeline_reg_30(INPUT_PIPELINE_REG_30),
.pipeline_reg_31(INPUT_PIPELINE_REG_31),
.pipeline_reg_32(INPUT_PIPELINE_REG_32),
.pipeline_reg_33(INPUT_PIPELINE_REG_33),
.pipeline_reg_34(INPUT_PIPELINE_REG_34),
.pipeline_reg_35(INPUT_PIPELINE_REG_35),
.pipeline_reg_36(INPUT_PIPELINE_REG_36),
.pipeline_reg_37(INPUT_PIPELINE_REG_37),
.pipeline_reg_38(INPUT_PIPELINE_REG_38),
.pipeline_reg_39(INPUT_PIPELINE_REG_39),
.pipeline_reg_40(INPUT_PIPELINE_REG_40),
.pipeline_reg_41(INPUT_PIPELINE_REG_41),
.pipeline_reg_42(INPUT_PIPELINE_REG_42),
.pipeline_reg_43(INPUT_PIPELINE_REG_43),
.pipeline_reg_44(INPUT_PIPELINE_REG_44),
.pipeline_reg_45(INPUT_PIPELINE_REG_45),
.pipeline_reg_46(INPUT_PIPELINE_REG_46),
.pipeline_reg_47(INPUT_PIPELINE_REG_47),
.pipeline_reg_48(INPUT_PIPELINE_REG_48),
.pipeline_reg_49(INPUT_PIPELINE_REG_49),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
wire [dw-1:0] L0_output_wires_11;
wire [dw-1:0] L0_output_wires_12;
wire [dw-1:0] L0_output_wires_13;
wire [dw-1:0] L0_output_wires_14;
wire [dw-1:0] L0_output_wires_15;
wire [dw-1:0] L0_output_wires_16;
wire [dw-1:0] L0_output_wires_17;
wire [dw-1:0] L0_output_wires_18;
wire [dw-1:0] L0_output_wires_19;
wire [dw-1:0] L0_output_wires_20;
wire [dw-1:0] L0_output_wires_21;
wire [dw-1:0] L0_output_wires_22;
wire [dw-1:0] L0_output_wires_23;
wire [dw-1:0] L0_output_wires_24;
adder_with_1_reg L0_adder_0and49(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_49),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and48(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_48),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and47(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_47),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and46(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_46),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and45(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_45),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and44(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_44),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and43(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_43),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and42(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_42),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and41(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_41),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and40(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_40),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and39(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_39),
.result(L0_output_wires_10)
);
adder_with_1_reg L0_adder_11and38(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_11),
.datab (INPUT_PIPELINE_REG_38),
.result(L0_output_wires_11)
);
adder_with_1_reg L0_adder_12and37(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_12),
.datab (INPUT_PIPELINE_REG_37),
.result(L0_output_wires_12)
);
adder_with_1_reg L0_adder_13and36(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_13),
.datab (INPUT_PIPELINE_REG_36),
.result(L0_output_wires_13)
);
adder_with_1_reg L0_adder_14and35(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_14),
.datab (INPUT_PIPELINE_REG_35),
.result(L0_output_wires_14)
);
adder_with_1_reg L0_adder_15and34(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_15),
.datab (INPUT_PIPELINE_REG_34),
.result(L0_output_wires_15)
);
adder_with_1_reg L0_adder_16and33(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_16),
.datab (INPUT_PIPELINE_REG_33),
.result(L0_output_wires_16)
);
adder_with_1_reg L0_adder_17and32(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_17),
.datab (INPUT_PIPELINE_REG_32),
.result(L0_output_wires_17)
);
adder_with_1_reg L0_adder_18and31(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_18),
.datab (INPUT_PIPELINE_REG_31),
.result(L0_output_wires_18)
);
adder_with_1_reg L0_adder_19and30(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_19),
.datab (INPUT_PIPELINE_REG_30),
.result(L0_output_wires_19)
);
adder_with_1_reg L0_adder_20and29(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_20),
.datab (INPUT_PIPELINE_REG_29),
.result(L0_output_wires_20)
);
adder_with_1_reg L0_adder_21and28(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_21),
.datab (INPUT_PIPELINE_REG_28),
.result(L0_output_wires_21)
);
adder_with_1_reg L0_adder_22and27(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_22),
.datab (INPUT_PIPELINE_REG_27),
.result(L0_output_wires_22)
);
adder_with_1_reg L0_adder_23and26(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_23),
.datab (INPUT_PIPELINE_REG_26),
.result(L0_output_wires_23)
);
adder_with_1_reg L0_adder_24and25(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_24),
.datab (INPUT_PIPELINE_REG_25),
.result(L0_output_wires_24)
);
// (25 main tree Adders)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
wire [dw-1:0] L1_mult_wires_11;
wire [dw-1:0] L1_mult_wires_12;
wire [dw-1:0] L1_mult_wires_13;
wire [dw-1:0] L1_mult_wires_14;
wire [dw-1:0] L1_mult_wires_15;
wire [dw-1:0] L1_mult_wires_16;
wire [dw-1:0] L1_mult_wires_17;
wire [dw-1:0] L1_mult_wires_18;
wire [dw-1:0] L1_mult_wires_19;
wire [dw-1:0] L1_mult_wires_20;
wire [dw-1:0] L1_mult_wires_21;
wire [dw-1:0] L1_mult_wires_22;
wire [dw-1:0] L1_mult_wires_23;
wire [dw-1:0] L1_mult_wires_24;
multiplier_with_reg L1_mul_0(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
multiplier_with_reg L1_mul_11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_11),
.datab (COEFFICIENT_11),
.result(L1_mult_wires_11)
);
multiplier_with_reg L1_mul_12(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_12),
.datab (COEFFICIENT_12),
.result(L1_mult_wires_12)
);
multiplier_with_reg L1_mul_13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_13),
.datab (COEFFICIENT_13),
.result(L1_mult_wires_13)
);
multiplier_with_reg L1_mul_14(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_14),
.datab (COEFFICIENT_14),
.result(L1_mult_wires_14)
);
multiplier_with_reg L1_mul_15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_15),
.datab (COEFFICIENT_15),
.result(L1_mult_wires_15)
);
multiplier_with_reg L1_mul_16(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_16),
.datab (COEFFICIENT_16),
.result(L1_mult_wires_16)
);
multiplier_with_reg L1_mul_17(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_17),
.datab (COEFFICIENT_17),
.result(L1_mult_wires_17)
);
multiplier_with_reg L1_mul_18(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_18),
.datab (COEFFICIENT_18),
.result(L1_mult_wires_18)
);
multiplier_with_reg L1_mul_19(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_19),
.datab (COEFFICIENT_19),
.result(L1_mult_wires_19)
);
multiplier_with_reg L1_mul_20(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_20),
.datab (COEFFICIENT_20),
.result(L1_mult_wires_20)
);
multiplier_with_reg L1_mul_21(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_21),
.datab (COEFFICIENT_21),
.result(L1_mult_wires_21)
);
multiplier_with_reg L1_mul_22(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_22),
.datab (COEFFICIENT_22),
.result(L1_mult_wires_22)
);
multiplier_with_reg L1_mul_23(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_23),
.datab (COEFFICIENT_23),
.result(L1_mult_wires_23)
);
multiplier_with_reg L1_mul_24(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_24),
.datab (COEFFICIENT_24),
.result(L1_mult_wires_24)
);
// (25 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
wire [dw-1:0] L1_output_wires_6;
wire [dw-1:0] L1_output_wires_7;
wire [dw-1:0] L1_output_wires_8;
wire [dw-1:0] L1_output_wires_9;
wire [dw-1:0] L1_output_wires_10;
wire [dw-1:0] L1_output_wires_11;
wire [dw-1:0] L1_output_wires_12;
adder_with_1_reg L1_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
adder_with_1_reg L1_adder_10and11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_10),
.datab (L1_mult_wires_11),
.result(L1_output_wires_5)
);
adder_with_1_reg L1_adder_12and13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_12),
.datab (L1_mult_wires_13),
.result(L1_output_wires_6)
);
adder_with_1_reg L1_adder_14and15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_14),
.datab (L1_mult_wires_15),
.result(L1_output_wires_7)
);
adder_with_1_reg L1_adder_16and17(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_16),
.datab (L1_mult_wires_17),
.result(L1_output_wires_8)
);
adder_with_1_reg L1_adder_18and19(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_18),
.datab (L1_mult_wires_19),
.result(L1_output_wires_9)
);
adder_with_1_reg L1_adder_20and21(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_20),
.datab (L1_mult_wires_21),
.result(L1_output_wires_10)
);
adder_with_1_reg L1_adder_22and23(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_22),
.datab (L1_mult_wires_23),
.result(L1_output_wires_11)
);
// (12 main tree Adders)
// ********* Byes ******** \\
one_register L1_byereg_for_24(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_24),
.result(L1_output_wires_12)
);
// (1 byes)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
wire [dw-1:0] L2_output_wires_3;
wire [dw-1:0] L2_output_wires_4;
wire [dw-1:0] L2_output_wires_5;
wire [dw-1:0] L2_output_wires_6;
adder_with_1_reg L2_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
adder_with_1_reg L2_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_6),
.datab (L1_output_wires_7),
.result(L2_output_wires_3)
);
adder_with_1_reg L2_adder_8and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_8),
.datab (L1_output_wires_9),
.result(L2_output_wires_4)
);
adder_with_1_reg L2_adder_10and11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_10),
.datab (L1_output_wires_11),
.result(L2_output_wires_5)
);
// (6 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_12(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_12),
.result(L2_output_wires_6)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
wire [dw-1:0] L3_output_wires_2;
wire [dw-1:0] L3_output_wires_3;
adder_with_1_reg L3_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
adder_with_1_reg L3_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_2),
.datab (L2_output_wires_3),
.result(L3_output_wires_1)
);
adder_with_1_reg L3_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_4),
.datab (L2_output_wires_5),
.result(L3_output_wires_2)
);
// (3 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_6(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_6),
.result(L3_output_wires_3)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
wire [dw-1:0] L4_output_wires_1;
adder_with_1_reg L4_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
adder_with_1_reg L4_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_2),
.datab (L3_output_wires_3),
.result(L4_output_wires_1)
);
// (2 main tree Adders)
// ************************* LEVEL 5 ************************* \\
wire [dw-1:0] L5_output_wires_0;
adder_with_1_reg L5_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L4_output_wires_0),
.datab (L4_output_wires_1),
.result(L5_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
assign o_out = L5_output_wires_0;
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
pipeline_reg_22,
pipeline_reg_23,
pipeline_reg_24,
pipeline_reg_25,
pipeline_reg_26,
pipeline_reg_27,
pipeline_reg_28,
pipeline_reg_29,
pipeline_reg_30,
pipeline_reg_31,
pipeline_reg_32,
pipeline_reg_33,
pipeline_reg_34,
pipeline_reg_35,
pipeline_reg_36,
pipeline_reg_37,
pipeline_reg_38,
pipeline_reg_39,
pipeline_reg_40,
pipeline_reg_41,
pipeline_reg_42,
pipeline_reg_43,
pipeline_reg_44,
pipeline_reg_45,
pipeline_reg_46,
pipeline_reg_47,
pipeline_reg_48,
pipeline_reg_49,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
output [WIDTH-1:0] pipeline_reg_22;
output [WIDTH-1:0] pipeline_reg_23;
output [WIDTH-1:0] pipeline_reg_24;
output [WIDTH-1:0] pipeline_reg_25;
output [WIDTH-1:0] pipeline_reg_26;
output [WIDTH-1:0] pipeline_reg_27;
output [WIDTH-1:0] pipeline_reg_28;
output [WIDTH-1:0] pipeline_reg_29;
output [WIDTH-1:0] pipeline_reg_30;
output [WIDTH-1:0] pipeline_reg_31;
output [WIDTH-1:0] pipeline_reg_32;
output [WIDTH-1:0] pipeline_reg_33;
output [WIDTH-1:0] pipeline_reg_34;
output [WIDTH-1:0] pipeline_reg_35;
output [WIDTH-1:0] pipeline_reg_36;
output [WIDTH-1:0] pipeline_reg_37;
output [WIDTH-1:0] pipeline_reg_38;
output [WIDTH-1:0] pipeline_reg_39;
output [WIDTH-1:0] pipeline_reg_40;
output [WIDTH-1:0] pipeline_reg_41;
output [WIDTH-1:0] pipeline_reg_42;
output [WIDTH-1:0] pipeline_reg_43;
output [WIDTH-1:0] pipeline_reg_44;
output [WIDTH-1:0] pipeline_reg_45;
output [WIDTH-1:0] pipeline_reg_46;
output [WIDTH-1:0] pipeline_reg_47;
output [WIDTH-1:0] pipeline_reg_48;
output [WIDTH-1:0] pipeline_reg_49;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_22;
reg [WIDTH-1:0] pipeline_reg_23;
reg [WIDTH-1:0] pipeline_reg_24;
reg [WIDTH-1:0] pipeline_reg_25;
reg [WIDTH-1:0] pipeline_reg_26;
reg [WIDTH-1:0] pipeline_reg_27;
reg [WIDTH-1:0] pipeline_reg_28;
reg [WIDTH-1:0] pipeline_reg_29;
reg [WIDTH-1:0] pipeline_reg_30;
reg [WIDTH-1:0] pipeline_reg_31;
reg [WIDTH-1:0] pipeline_reg_32;
reg [WIDTH-1:0] pipeline_reg_33;
reg [WIDTH-1:0] pipeline_reg_34;
reg [WIDTH-1:0] pipeline_reg_35;
reg [WIDTH-1:0] pipeline_reg_36;
reg [WIDTH-1:0] pipeline_reg_37;
reg [WIDTH-1:0] pipeline_reg_38;
reg [WIDTH-1:0] pipeline_reg_39;
reg [WIDTH-1:0] pipeline_reg_40;
reg [WIDTH-1:0] pipeline_reg_41;
reg [WIDTH-1:0] pipeline_reg_42;
reg [WIDTH-1:0] pipeline_reg_43;
reg [WIDTH-1:0] pipeline_reg_44;
reg [WIDTH-1:0] pipeline_reg_45;
reg [WIDTH-1:0] pipeline_reg_46;
reg [WIDTH-1:0] pipeline_reg_47;
reg [WIDTH-1:0] pipeline_reg_48;
reg [WIDTH-1:0] pipeline_reg_49;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
pipeline_reg_22 <= 0;
pipeline_reg_23 <= 0;
pipeline_reg_24 <= 0;
pipeline_reg_25 <= 0;
pipeline_reg_26 <= 0;
pipeline_reg_27 <= 0;
pipeline_reg_28 <= 0;
pipeline_reg_29 <= 0;
pipeline_reg_30 <= 0;
pipeline_reg_31 <= 0;
pipeline_reg_32 <= 0;
pipeline_reg_33 <= 0;
pipeline_reg_34 <= 0;
pipeline_reg_35 <= 0;
pipeline_reg_36 <= 0;
pipeline_reg_37 <= 0;
pipeline_reg_38 <= 0;
pipeline_reg_39 <= 0;
pipeline_reg_40 <= 0;
pipeline_reg_41 <= 0;
pipeline_reg_42 <= 0;
pipeline_reg_43 <= 0;
pipeline_reg_44 <= 0;
pipeline_reg_45 <= 0;
pipeline_reg_46 <= 0;
pipeline_reg_47 <= 0;
pipeline_reg_48 <= 0;
pipeline_reg_49 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
pipeline_reg_22 <= pipeline_reg_21;
pipeline_reg_23 <= pipeline_reg_22;
pipeline_reg_24 <= pipeline_reg_23;
pipeline_reg_25 <= pipeline_reg_24;
pipeline_reg_26 <= pipeline_reg_25;
pipeline_reg_27 <= pipeline_reg_26;
pipeline_reg_28 <= pipeline_reg_27;
pipeline_reg_29 <= pipeline_reg_28;
pipeline_reg_30 <= pipeline_reg_29;
pipeline_reg_31 <= pipeline_reg_30;
pipeline_reg_32 <= pipeline_reg_31;
pipeline_reg_33 <= pipeline_reg_32;
pipeline_reg_34 <= pipeline_reg_33;
pipeline_reg_35 <= pipeline_reg_34;
pipeline_reg_36 <= pipeline_reg_35;
pipeline_reg_37 <= pipeline_reg_36;
pipeline_reg_38 <= pipeline_reg_37;
pipeline_reg_39 <= pipeline_reg_38;
pipeline_reg_40 <= pipeline_reg_39;
pipeline_reg_41 <= pipeline_reg_40;
pipeline_reg_42 <= pipeline_reg_41;
pipeline_reg_43 <= pipeline_reg_42;
pipeline_reg_44 <= pipeline_reg_43;
pipeline_reg_45 <= pipeline_reg_44;
pipeline_reg_46 <= pipeline_reg_45;
pipeline_reg_47 <= pipeline_reg_46;
pipeline_reg_48 <= pipeline_reg_47;
pipeline_reg_49 <= pipeline_reg_48;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//pipeline_reg_22 <= pipeline_reg_22;
//pipeline_reg_23 <= pipeline_reg_23;
//pipeline_reg_24 <= pipeline_reg_24;
//pipeline_reg_25 <= pipeline_reg_25;
//pipeline_reg_26 <= pipeline_reg_26;
//pipeline_reg_27 <= pipeline_reg_27;
//pipeline_reg_28 <= pipeline_reg_28;
//pipeline_reg_29 <= pipeline_reg_29;
//pipeline_reg_30 <= pipeline_reg_30;
//pipeline_reg_31 <= pipeline_reg_31;
//pipeline_reg_32 <= pipeline_reg_32;
//pipeline_reg_33 <= pipeline_reg_33;
//pipeline_reg_34 <= pipeline_reg_34;
//pipeline_reg_35 <= pipeline_reg_35;
//pipeline_reg_36 <= pipeline_reg_36;
//pipeline_reg_37 <= pipeline_reg_37;
//pipeline_reg_38 <= pipeline_reg_38;
//pipeline_reg_39 <= pipeline_reg_39;
//pipeline_reg_40 <= pipeline_reg_40;
//pipeline_reg_41 <= pipeline_reg_41;
//pipeline_reg_42 <= pipeline_reg_42;
//pipeline_reg_43 <= pipeline_reg_43;
//pipeline_reg_44 <= pipeline_reg_44;
//pipeline_reg_45 <= pipeline_reg_45;
//pipeline_reg_46 <= pipeline_reg_46;
//pipeline_reg_47 <= pipeline_reg_47;
//pipeline_reg_48 <= pipeline_reg_48;
//pipeline_reg_49 <= pipeline_reg_49;
//end
end
end
endmodule
module adder_with_1_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa + datab;
end
end
endmodule
module multiplier_with_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa * datab;
end
end
endmodule
module one_register (
clk,
clk_ena,
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa;
end
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : uart_regs.v
// Description : UART Registers
// Author : Philip Tracton
// Created On : Wed May 27 17:22:20 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed May 27 17:22:20 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module pb_uart_regs (/*AUTOARG*/
// Outputs
data_out, interrupt, buffer_write, uart_data_write, buffer_read,
enable, uart_clock_divide,
// Inputs
clk, reset, port_id, data_in, read_strobe, write_strobe,
uart_data_read, rx_data_present, rx_half_full, rx_full,
tx_data_present, tx_half_full, tx_full
) ;
input clk;
input reset;
input [7:0] port_id;
input [7:0] data_in;
output [7:0] data_out;
input read_strobe;
input write_strobe;
output interrupt;
output buffer_write;
output [7:0] uart_data_write;
output buffer_read;
input [7:0] uart_data_read;
input rx_data_present;
input rx_half_full;
input rx_full;
input tx_data_present;
input tx_half_full;
input tx_full;
output enable;
output [15:0] uart_clock_divide;
parameter BASE_ADDRESS = 8'h00;
//
// Address Decode
//
wire uart_data_in_enable = (port_id == (BASE_ADDRESS + 0)); //Read Only
wire uart_data_out_enable = (port_id == (BASE_ADDRESS + 0)); //Write Only
wire uart_control_enable = (port_id == (BASE_ADDRESS + 1));
wire uart_status_enable = (port_id == (BASE_ADDRESS + 2));
wire uart_irq_mask_enable = (port_id == (BASE_ADDRESS + 3));
wire uart_irq_enable = (port_id == (BASE_ADDRESS + 4));
wire uart_clock_divide_lower_enable = (port_id == (BASE_ADDRESS + 5));
wire uart_clock_divide_upper_enable = (port_id == (BASE_ADDRESS + 6));
//
// Registers
//
reg [7:0] uart_control = 8'h00;
reg [2:0] uart_irq_mask = 3'h0;
reg [2:0] uart_irq = 3'h0;
reg [15:0] uart_clock_divide = 16'h0000;
reg buffer_read = 1'b0;
reg buffer_write = 1'b0;
reg [7:0] uart_data_write = 8'h00;
reg [7:0] uart_data_read_reg = 8'h00;
reg [7:0] data_out = 8'h00;
reg interrupt = 1'b0;
//
// Interrupt Logic
//
always @(posedge clk)
if (reset) begin
interrupt <= 0;
end else begin
interrupt <= rx_data_present;
end
//
// Register Writing
//
always @(posedge clk)
if (reset) begin
buffer_write <= 0;
uart_data_write <= 0;
uart_control <= 0;
uart_irq_mask <= 0;
uart_clock_divide <= 0;
end else if (write_strobe == 1'b1) begin
if (uart_data_in_enable) begin
uart_data_write <= data_in;
buffer_write <= 1'b1;
end
if (uart_control_enable) begin
uart_control <= data_in;
end
if (uart_irq_mask_enable) begin
uart_irq_mask <= data_in[2:0];
end
if (uart_clock_divide_lower_enable) begin
uart_clock_divide[7:0] <= data_in;
end
if (uart_clock_divide_upper_enable) begin
uart_clock_divide[15:8] <= data_in;
end
end else begin
buffer_write <= 1'b0;
end // else: !if(write_strobe == 1'b1)
//
// Register Reading
//
always @(posedge clk)
if (reset) begin
data_out <= 0;
buffer_read <= 0;
end else begin
if (uart_data_out_enable) begin
data_out <= uart_data_read;
buffer_read <= 1'b1;
end
else if (uart_control_enable) begin
data_out <= uart_control;
end
else if (uart_status_enable) begin
data_out <= {2'b00, tx_full, tx_half_full, tx_data_present, rx_full, rx_half_full, rx_data_present};
end
else if (uart_irq_mask_enable) begin
data_out <= {5'b0, uart_irq_mask};
end
else if (uart_irq_enable) begin
data_out <= {5'b0, uart_irq};
end
else if (uart_clock_divide_lower_enable) begin
data_out <= uart_clock_divide[7:0];
end
else if (uart_clock_divide_upper_enable) begin
data_out <= uart_clock_divide[15:8];
end
else begin
data_out <= 8'h00;
buffer_read <= 1'b0;
end
end // always @ (posedge clk)
endmodule // uart_regs
|
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_encoder_top.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Encoder
// Module Name: d_BCH_encoder_top
// File Name: d_BCH_encoder_top.v
//
// Version: v1.0.1-256B_T14
//
// Description:
// - BCH encoder TOP module
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_BCH_encoder_parameters.vh"
`timescale 1ns / 1ps
module d_BCH_encoder_top
(
input wire i_clk,
input wire i_nRESET,
input wire i_exe_encoding, // execute encoding, encoding start command signal
input wire i_message_valid, // message BUS strobe signal
input wire [`D_BCH_ENC_P_LVL-1:0] i_message, // message block data BUS
output reg o_message_ready,
output wire o_encoding_start, // [indicate] encoding start
output wire o_last_m_block_rcvd, // [indicate] last message block received
output wire o_encoding_cmplt, // [indicate] encoding complete
input wire i_parity_ready,
output wire o_parity_valid, // [indicate] parity BUS strobe signal
output wire o_parity_out_start, // [indicate] parity block out start
output wire o_parity_out_cmplt, // [indicate] last parity block transmitted
output wire [`D_BCH_ENC_P_LVL-1:0] o_parity_out // parity block data BUS
);
parameter D_BCH_ENC_FSM_BIT = 7;
parameter RESET = 7'b0000001; // RESET: encoder sequence reset
parameter ENCD_ST = 7'b0000010; // encoder: start mode, compute parity
parameter ENCD_FB = 7'b0000100;
parameter P_O_STR = 7'b0001000; // encoder: feedback mode, compute parity
parameter P_O_STBY = 7'b0010000; // parity out: first block
parameter P_O_SHF = 7'b0100000; // parity out: shifted block
parameter MSG_T_P = 7'b1000000; // encoder: message transmit paused (message BUS invalid)
// registered input
reg [`D_BCH_ENC_P_LVL-1:0] r_message_b;
// encoder FSM state
reg [D_BCH_ENC_FSM_BIT-1:0] r_cur_state;
reg [D_BCH_ENC_FSM_BIT-1:0] r_nxt_state;
// internal counter
reg [`D_BCH_ENC_I_CNT_BIT-1:0] r_counter;
// registers for parity code
reg [`D_BCH_ENC_PRT_LENGTH-1:0] r_parity_code;
wire [`D_BCH_ENC_PRT_LENGTH-1:0] w_nxt_parity_code;
wire w_valid_execution;
////////////////////////////////////////////////////////////////////////////////
// modified(improved) linear feedback shift XOR matrix
// LFSR = LFSXOR + register
d_parallel_m_lfs_XOR d_mLFSXOR_matrix (
.i_message (r_message_b),
.i_cur_parity(r_parity_code),
.o_nxt_parity(w_nxt_parity_code));
////////////////////////////////////////////////////////////////////////////////
// generate control/indicate signal
assign w_valid_execution = i_exe_encoding & i_message_valid;
assign o_encoding_start = (r_cur_state == ENCD_ST);
assign o_last_m_block_rcvd = (i_message_valid == 1) & (r_counter == `D_BCH_ENC_I_CNT-1);
assign o_encoding_cmplt = (r_counter == `D_BCH_ENC_I_CNT);
assign o_parity_valid = (r_cur_state == P_O_STR) | (r_cur_state == P_O_SHF) | (r_cur_state == P_O_STBY);
assign o_parity_out_start = (r_cur_state == P_O_STR);
assign o_parity_out_cmplt = ((r_cur_state == P_O_SHF) | (r_cur_state == P_O_STBY)) & (r_counter == `D_BCH_ENC_O_CNT-1) & (i_parity_ready & o_parity_valid);
// parity output
assign o_parity_out = (o_parity_valid)? r_parity_code[`D_BCH_ENC_PRT_LENGTH-1 : `D_BCH_ENC_PRT_LENGTH-`D_BCH_ENC_P_LVL]:0;
// update current state to next state
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET) begin
r_cur_state <= RESET;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
RESET: begin
r_nxt_state <= (w_valid_execution)? (ENCD_ST):(RESET);
end
ENCD_ST: begin
r_nxt_state <= (i_message_valid)? (ENCD_FB):(MSG_T_P);
end
ENCD_FB: begin
r_nxt_state <= (o_encoding_cmplt)? (P_O_STR):
((i_message_valid)? (ENCD_FB):(MSG_T_P));
end
P_O_STR: begin
r_nxt_state <= (!i_parity_ready) ? (P_O_STBY) : (P_O_SHF);
end
P_O_SHF: begin
r_nxt_state <= (!i_parity_ready) ? (P_O_STBY):((o_parity_out_cmplt) ? (RESET) : (P_O_SHF));//((w_valid_execution)? (ENCD_ST):(RESET)):(P_O_SHF));
end
MSG_T_P: begin
r_nxt_state <= (i_message_valid)? (ENCD_FB):(MSG_T_P);
end
P_O_STBY: begin
r_nxt_state <= (i_parity_ready)?((o_parity_out_cmplt) ? /*((w_valid_execution)? (ENCD_ST):(RESET))*/(RESET) : (P_O_SHF)) : (P_O_STBY);
end
default: begin
r_nxt_state <= RESET;
end
endcase
end
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET)
o_message_ready <= 1;
else
case (r_nxt_state)
RESET:
o_message_ready <= 1;
ENCD_FB:
o_message_ready <= (o_last_m_block_rcvd) ? 0 : 1;
endcase
end
// state behaviour
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET) begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
else begin
case (r_nxt_state)
RESET: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
ENCD_ST: begin
r_counter <= 1;
r_message_b <= i_message;
r_parity_code <= 0;
end
ENCD_FB: begin
r_counter <= r_counter + 1'b1;
r_message_b <= i_message;
r_parity_code <= w_nxt_parity_code;
end
P_O_STR: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= w_nxt_parity_code;
end
P_O_SHF: begin
r_counter <= r_counter + 1'b1;
r_message_b <= 0;
r_parity_code <= r_parity_code << `D_BCH_ENC_P_LVL;
end
MSG_T_P: begin
r_counter <= r_counter;
r_message_b <= r_message_b;
r_parity_code <= r_parity_code;
end
P_O_STBY: begin
r_counter <= r_counter;
r_message_b <= 0;
r_parity_code <= r_parity_code;
end
default: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
endcase
end
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test triggers constant propagation through AND gates.
*/
module main;
wire a = 1'b0;
wire b = 1'b1;
wire c = 1'b1;
wire d = 1'bx;
wire out0, out1, out2, out3;
and (out0, a, b); // Should be 0
and (out1, b, c); // Should be 1
and (out2, a, d); // Should be 0 because of a
and (out3, b, d); // Should be x
initial begin
#0 if (out0 !== 1'b0) begin
$display("FAILED -- out0 = %b", out0);
$finish;
end
if (out1 !== 1'b1) begin
$display("FAILED -- out1 = %b", out1);
$finish;
end
if (out2 !== 1'b0) begin
$display("FAILED -- out2 = %b", out2);
$finish;
end
if (out3 !== 1'bx) begin
$display("FAILED -- outx = %b", out3);
$finish;
end
$display("PASSED");
end
endmodule // main
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_64w_32r_512d.v when simulating
// the core, fifo_64w_32r_512d. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_64w_32r_512d(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
output [9 : 0] rd_data_count;
output [8 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(509),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(508),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// EMPTY !
// Need to specify directions and connections statically
module xmos_cpld_slice
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
AB10,
AA11,
AB11,
AA12,
AB12,
AA13,
CLK,
AB13,
AA15,
AB15,
AA16,
AB17,
nRST,
B18,
AA18,
BA18,
BB17,
BA16,
BB15,
BA15,
BB13,
BA13,
BB12,
BA12,
BB11,
BA11,
BB10,
BA9,
BB9,
BA8,
BB7,
BA7,
BB6,
BA6,
BB4,
BA4,
BB2,
BA3,
BB1,
BA1,
AA1,
AB1,
AA3,
AB2,
AA4,
AB4,
P55,
AA6,
AB6,
AA7,
AB7,
AA8,
AB9,
AA9
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
);
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
inout AB10;
inout AA11;
inout AB11;
inout AA12;
inout AB12;
inout AA13;
input CLK;
inout AB13;
inout AA15;
inout AB15;
inout AA16;
inout AB17;
input nRST;
input B18;
inout AA18;
inout BA18;
inout BB17;
inout BA16;
inout BB15;
inout BA15;
inout BB13;
inout BA13;
inout BB12;
inout BA12;
inout BB11;
inout BA11;
input BB10;
input BA9;
input BB9;
input BA8;
input BB7;
input BA7;
input BB6;
input BA6;
input BB4;
input BA4;
input BB2;
input BA3;
input BB1;
input BA1;
input AA1;
input AB1;
input AA3;
input AB2;
input AA4;
input AB4;
input P55;
input AA6;
input AB6;
input AA7;
input AB7;
inout AA8;
input AB9;
input AA9;
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
endmodule
|
`timescale 1 ns / 1 ps
module fsm_io_switch_v1_1_S_AXI #
(
// Users to add parameters here
parameter C_FSM_SWITCH_WIDTH = 20,
parameter C_INTERFACE = 0,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
input [C_FSM_SWITCH_WIDTH-1:0] fsm_data_i,
input [3:0] fsm_ns_out_8_5,
output [C_FSM_SWITCH_WIDTH-1:0] fsm_data_o,
output [7:0]fsm_input,
input [C_FSM_SWITCH_WIDTH-1:0] fsm_output,
output [C_FSM_SWITCH_WIDTH-1:0] fsm_tri_o,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// FSM related wires and connections
wire [C_FSM_SWITCH_WIDTH-1:0] fsm_data_o0, fsm_data_o1, fsm_data_o2, fsm_data_o3, fsm_data_o4, fsm_data_o5, fsm_data_o6, fsm_data_o7, fsm_data_o8, fsm_data_o9, fsm_data_o10;
wire [C_FSM_SWITCH_WIDTH-1:0] fsm_data_o11, fsm_data_o12, fsm_data_o13, fsm_data_o14, fsm_data_o15, fsm_data_o16, fsm_data_o17, fsm_data_o18, fsm_data_o19;
wire fsm_input_0, fsm_input_1, fsm_input_2, fsm_input_3;
assign fsm_data_o = fsm_data_o0 | fsm_data_o1 | fsm_data_o2 | fsm_data_o3 | fsm_data_o4 | fsm_data_o5 | fsm_data_o6 | fsm_data_o7 | fsm_data_o8 | fsm_data_o9 |
fsm_data_o10 | fsm_data_o11 | fsm_data_o12 | fsm_data_o13 | fsm_data_o14 | fsm_data_o15 | fsm_data_o16 | fsm_data_o17 | fsm_data_o18 | fsm_data_o19;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 2;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 8
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h4:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h5:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h6:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h7:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0 : reg_data_out <= slv_reg0;
3'h1 : reg_data_out <= slv_reg1;
3'h2 : reg_data_out <= slv_reg2;
3'h3 : reg_data_out <= slv_reg3;
3'h4 : reg_data_out <= slv_reg4;
3'h5 : reg_data_out <= slv_reg5;
3'h6 : reg_data_out <= slv_reg6;
3'h7 : reg_data_out <= slv_reg7;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
mux_2_to_1 mux_input0(
.sel(slv_reg0[7]),
.smb_ns_i(fsm_ns_out_8_5[0]),
.in_pin(fsm_input_0),
.out_int(fsm_input[0])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux0(
.sel(slv_reg0[4:0]),
.in_pin(fsm_data_i),
.out_int(fsm_input_0)
);
mux_2_to_1 mux_input1(
.sel(slv_reg0[15]),
.smb_ns_i(fsm_ns_out_8_5[1]),
.in_pin(fsm_input_1),
.out_int(fsm_input[1])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux1(
.sel(slv_reg0[12:8]),
.in_pin(fsm_data_i),
.out_int(fsm_input_1)
);
mux_2_to_1 mux_input2(
.sel(slv_reg0[23]),
.smb_ns_i(fsm_ns_out_8_5[2]),
.in_pin(fsm_input_2),
.out_int(fsm_input[2])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux2(
.sel(slv_reg0[20:16]),
.in_pin(fsm_data_i),
.out_int(fsm_input_2)
);
mux_2_to_1 mux_input3(
.sel(slv_reg0[31]),
.smb_ns_i(fsm_ns_out_8_5[3]),
.in_pin(fsm_input_3),
.out_int(fsm_input[3])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux3(
.sel(slv_reg0[28:24]),
.in_pin(fsm_data_i),
.out_int(fsm_input_3)
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux4(
.sel(slv_reg1[4:0]),
.in_pin(fsm_data_i),
.out_int(fsm_input[4])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux5(
.sel(slv_reg1[12:8]),
.in_pin(fsm_data_i),
.out_int(fsm_input[5])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux6(
.sel(slv_reg1[20:16]),
.in_pin(fsm_data_i),
.out_int(fsm_input[6])
);
input_mux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) mux7(
.sel(slv_reg1[28:24]),
.in_pin(fsm_data_i),
.out_int(fsm_input[7])
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux0(
.sel(slv_reg2[4:0]),
.in_pin(fsm_output[0]),
.out_pin(fsm_data_o0)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux1(
.sel(slv_reg2[12:8]),
.in_pin(fsm_output[1]),
.out_pin(fsm_data_o1)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux2(
.sel(slv_reg2[20:16]),
.in_pin(fsm_output[2]),
.out_pin(fsm_data_o2)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux3(
.sel(slv_reg2[28:24]),
.in_pin(fsm_output[3]),
.out_pin(fsm_data_o3)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux4(
.sel(slv_reg3[4:0]),
.in_pin(fsm_output[4]),
.out_pin(fsm_data_o4)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux5(
.sel(slv_reg3[12:8]),
.in_pin(fsm_output[5]),
.out_pin(fsm_data_o5)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux6(
.sel(slv_reg3[20:16]),
.in_pin(fsm_output[6]),
.out_pin(fsm_data_o6)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux7(
.sel(slv_reg3[28:24]),
.in_pin(fsm_output[7]),
.out_pin(fsm_data_o7)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux8(
.sel(slv_reg4[4:0]),
.in_pin(fsm_output[8]),
.out_pin(fsm_data_o8)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux9(
.sel(slv_reg4[12:8]),
.in_pin(fsm_output[9]),
.out_pin(fsm_data_o9)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux10(
.sel(slv_reg4[20:16]),
.in_pin(fsm_output[10]),
.out_pin(fsm_data_o10)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux11(
.sel(slv_reg4[28:24]),
.in_pin(fsm_output[11]),
.out_pin(fsm_data_o11)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux12(
.sel(slv_reg5[4:0]),
.in_pin(fsm_output[12]),
.out_pin(fsm_data_o12)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux13(
.sel(slv_reg5[12:8]),
.in_pin(fsm_output[13]),
.out_pin(fsm_data_o13)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux14(
.sel(slv_reg5[20:16]),
.in_pin(fsm_output[14]),
.out_pin(fsm_data_o14)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux15(
.sel(slv_reg5[28:24]),
.in_pin(fsm_output[15]),
.out_pin(fsm_data_o15)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux16(
.sel(slv_reg6[4:0]),
.in_pin(fsm_output[16]),
.out_pin(fsm_data_o16)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux17(
.sel(slv_reg6[12:8]),
.in_pin(fsm_output[17]),
.out_pin(fsm_data_o17)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux18(
.sel(slv_reg6[20:16]),
.in_pin(fsm_output[18]),
.out_pin(fsm_data_o18)
);
output_demux # (
.C_FSM_SWITCH_WIDTH(C_FSM_SWITCH_WIDTH),
.C_INTERFACE(C_INTERFACE)
) demux19 (
.sel(slv_reg6[28:24]),
.in_pin(fsm_output[19]),
.out_pin(fsm_data_o19)
);
assign fsm_tri_o = slv_reg7[C_FSM_SWITCH_WIDTH-1:0];
// User logic ends
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module video_sys_Chroma_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_rd.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 read requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
if(prt_dv) begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
if(prt_dv) begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_hp2_3.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_hp2_3(
sw_clk,
rstn,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_dv_ddr_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_hp3;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp2;
input [max_burst_bits-1:0] wr_data_hp2;
input [addr_width-1:0] wr_addr_hp2;
input [max_burst_bytes_width:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [addr_width-1:0] rd_addr_hp2;
input [max_burst_bytes_width:0] rd_bytes_hp2;
output [max_burst_bits-1:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [max_burst_bits-1:0] wr_data_hp3;
input [addr_width-1:0] wr_addr_hp3;
input [max_burst_bytes_width:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [addr_width-1:0] rd_addr_hp3;
input [max_burst_bytes_width:0] rd_bytes_hp3;
output [max_burst_bits-1:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp2),
.qos2(w_qos_hp3),
.prt_dv1(wr_dv_ddr_hp2),
.prt_dv2(wr_dv_ddr_hp3),
.prt_data1(wr_data_hp2),
.prt_data2(wr_data_hp3),
.prt_addr1(wr_addr_hp2),
.prt_addr2(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp2),
.prt_bytes2(wr_bytes_hp3),
.prt_ack1(wr_ack_ddr_hp2),
.prt_ack2(wr_ack_ddr_hp3),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp2),
.qos2(r_qos_hp3),
.prt_req1(rd_req_ddr_hp2),
.prt_req2(rd_req_ddr_hp3),
.prt_data1(rd_data_ddr_hp2),
.prt_data2(rd_data_ddr_hp3),
.prt_addr1(rd_addr_hp2),
.prt_addr2(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp2),
.prt_bytes2(rd_bytes_hp3),
.prt_dv1(rd_dv_ddr_hp2),
.prt_dv2(rd_dv_ddr_hp3),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ssw_hp.v
*
* Date : 2012-11
*
* Description : SSW switch Model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ssw_hp(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
rd_data_ocm_hp0,
wr_ack_ocm_hp0,
wr_dv_ocm_hp0,
rd_req_ocm_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
wr_ack_ocm_hp1,
wr_dv_ocm_hp1,
rd_req_ocm_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
wr_ack_ocm_hp2,
wr_dv_ocm_hp2,
rd_req_ocm_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ocm_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
wr_ack_ocm_hp3,
wr_dv_ocm_hp3,
rd_req_ocm_hp3,
rd_dv_ocm_hp3,
ddr_wr_ack0,
ddr_wr_dv0,
ddr_rd_req0,
ddr_rd_dv0,
ddr_rd_qos0,
ddr_wr_qos0,
ddr_wr_addr0,
ddr_wr_data0,
ddr_wr_bytes0,
ddr_rd_addr0,
ddr_rd_data0,
ddr_rd_bytes0,
ddr_wr_ack1,
ddr_wr_dv1,
ddr_rd_req1,
ddr_rd_dv1,
ddr_rd_qos1,
ddr_wr_qos1,
ddr_wr_addr1,
ddr_wr_data1,
ddr_wr_bytes1,
ddr_rd_addr1,
ddr_rd_data1,
ddr_rd_bytes1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ocm_wr_qos,
ocm_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes
);
input sw_clk;
input rstn;
input [3:0] w_qos_hp0;
input [3:0] r_qos_hp0;
input [3:0] w_qos_hp1;
input [3:0] r_qos_hp1;
input [3:0] w_qos_hp2;
input [3:0] r_qos_hp2;
input [3:0] w_qos_hp3;
input [3:0] r_qos_hp3;
output [3:0] ddr_rd_qos0;
output [3:0] ddr_wr_qos0;
output [3:0] ddr_rd_qos1;
output [3:0] ddr_wr_qos1;
output [3:0] ocm_wr_qos;
output [3:0] ocm_rd_qos;
output wr_ack_ddr_hp0;
input [1023:0] wr_data_hp0;
input [31:0] wr_addr_hp0;
input [7:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [31:0] rd_addr_hp0;
input [7:0] rd_bytes_hp0;
output [1023:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [1023:0] wr_data_hp1;
input [31:0] wr_addr_hp1;
input [7:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [31:0] rd_addr_hp1;
input [7:0] rd_bytes_hp1;
output [1023:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
output wr_ack_ddr_hp2;
input [1023:0] wr_data_hp2;
input [31:0] wr_addr_hp2;
input [7:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [31:0] rd_addr_hp2;
input [7:0] rd_bytes_hp2;
output [1023:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [1023:0] wr_data_hp3;
input [31:0] wr_addr_hp3;
input [7:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [31:0] rd_addr_hp3;
input [7:0] rd_bytes_hp3;
output [1023:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack0;
output ddr_wr_dv0;
output [31:0]ddr_wr_addr0;
output [1023:0]ddr_wr_data0;
output [7:0]ddr_wr_bytes0;
input ddr_rd_dv0;
input [1023:0] ddr_rd_data0;
output ddr_rd_req0;
output [31:0] ddr_rd_addr0;
output [7:0] ddr_rd_bytes0;
input ddr_wr_ack1;
output ddr_wr_dv1;
output [31:0]ddr_wr_addr1;
output [1023:0]ddr_wr_data1;
output [7:0]ddr_wr_bytes1;
input ddr_rd_dv1;
input [1023:0] ddr_rd_data1;
output ddr_rd_req1;
output [31:0] ddr_rd_addr1;
output [7:0] ddr_rd_bytes1;
output wr_ack_ocm_hp0;
input wr_dv_ocm_hp0;
input rd_req_ocm_hp0;
output rd_dv_ocm_hp0;
output [1023:0] rd_data_ocm_hp0;
output wr_ack_ocm_hp1;
input wr_dv_ocm_hp1;
input rd_req_ocm_hp1;
output rd_dv_ocm_hp1;
output [1023:0] rd_data_ocm_hp1;
output wr_ack_ocm_hp2;
input wr_dv_ocm_hp2;
input rd_req_ocm_hp2;
output rd_dv_ocm_hp2;
output [1023:0] rd_data_ocm_hp2;
output wr_ack_ocm_hp3;
input wr_dv_ocm_hp3;
input rd_req_ocm_hp3;
output rd_dv_ocm_hp3;
output [1023:0] rd_data_ocm_hp3;
input ocm_wr_ack;
output ocm_wr_dv;
output [31:0]ocm_wr_addr;
output [1023:0]ocm_wr_data;
output [7:0]ocm_wr_bytes;
input ocm_rd_dv;
input [1023:0] ocm_rd_data;
output ocm_rd_req;
output [31:0] ocm_rd_addr;
output [7:0] ocm_rd_bytes;
/* FOR DDR */
processing_system7_bfm_v2_0_5_arb_hp0_1 ddr_hp01 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.ddr_wr_ack(ddr_wr_ack0),
.ddr_wr_dv(ddr_wr_dv0),
.ddr_rd_req(ddr_rd_req0),
.ddr_rd_dv(ddr_rd_dv0),
.ddr_rd_qos(ddr_rd_qos0),
.ddr_wr_qos(ddr_wr_qos0),
.ddr_wr_addr(ddr_wr_addr0),
.ddr_wr_data(ddr_wr_data0),
.ddr_wr_bytes(ddr_wr_bytes0),
.ddr_rd_addr(ddr_rd_addr0),
.ddr_rd_data(ddr_rd_data0),
.ddr_rd_bytes(ddr_rd_bytes0)
);
/* FOR DDR */
processing_system7_bfm_v2_0_5_arb_hp2_3 ddr_hp23 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.ddr_wr_ack(ddr_wr_ack1),
.ddr_wr_dv(ddr_wr_dv1),
.ddr_rd_req(ddr_rd_req1),
.ddr_rd_dv(ddr_rd_dv1),
.ddr_rd_qos(ddr_rd_qos1),
.ddr_wr_qos(ddr_wr_qos1),
.ddr_wr_addr(ddr_wr_addr1),
.ddr_wr_data(ddr_wr_data1),
.ddr_wr_bytes(ddr_wr_bytes1),
.ddr_rd_addr(ddr_rd_addr1),
.ddr_rd_data(ddr_rd_data1),
.ddr_rd_bytes(ddr_rd_bytes1)
);
/* FOR OCM_WR */
processing_system7_bfm_v2_0_5_arb_wr_4 ocm_wr_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.qos3(w_qos_hp2),
.qos4(w_qos_hp3),
.prt_dv1(wr_dv_ocm_hp0),
.prt_dv2(wr_dv_ocm_hp1),
.prt_dv3(wr_dv_ocm_hp2),
.prt_dv4(wr_dv_ocm_hp3),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_data3(wr_data_hp2),
.prt_data4(wr_data_hp3),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_addr3(wr_addr_hp2),
.prt_addr4(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_bytes3(wr_bytes_hp2),
.prt_bytes4(wr_bytes_hp3),
.prt_ack1(wr_ack_ocm_hp0),
.prt_ack2(wr_ack_ocm_hp1),
.prt_ack3(wr_ack_ocm_hp2),
.prt_ack4(wr_ack_ocm_hp3),
.prt_qos(ocm_wr_qos),
.prt_req(ocm_wr_dv),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
/* FOR OCM_RD */
processing_system7_bfm_v2_0_5_arb_rd_4 ocm_rd_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.qos3(r_qos_hp2),
.qos4(r_qos_hp3),
.prt_req1(rd_req_ocm_hp0),
.prt_req2(rd_req_ocm_hp1),
.prt_req3(rd_req_ocm_hp2),
.prt_req4(rd_req_ocm_hp3),
.prt_data1(rd_data_ocm_hp0),
.prt_data2(rd_data_ocm_hp1),
.prt_data3(rd_data_ocm_hp2),
.prt_data4(rd_data_ocm_hp3),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_addr3(rd_addr_hp2),
.prt_addr4(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_bytes3(rd_bytes_hp2),
.prt_bytes4(rd_bytes_hp3),
.prt_dv1(rd_dv_ocm_hp0),
.prt_dv2(rd_dv_ocm_hp1),
.prt_dv3(rd_dv_ocm_hp2),
.prt_dv4(rd_dv_ocm_hp3),
.prt_qos(ocm_rd_qos),
.prt_req(ocm_rd_req),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_sparse_mem.v
*
* Date : 2012-11
*
* Description : Sparse Memory Model
*
*****************************************************************************/
/*** WA for CR # 695818 ***/
`ifdef XILINX_SIMULATOR
`define XSIM_ISIM
`endif
`ifdef XILINX_ISIM
`define XSIM_ISIM
`endif
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_sparse_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4000_0000; /// 1GB mem size
parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
`ifdef XSIM_ISIM
reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
`else
reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
`endif
event mem_updated;
reg check_we;
reg [addr_width-1:0] check_up_add;
reg [data_width-1:0] updated_data;
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
`ifdef XSIM_ISIM
case(start_addr[31:28])
4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
endcase
`else
$readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
`endif
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : set_data(addr , $random);
ALL_ZEROS : set_data(addr , 32'h0000_0000);
ALL_ONES : set_data(addr , 32'hFFFF_FFFF);
default : set_data(addr , $random);
endcase
addr = addr+1;
end
end
endtask
/* wait for memory update at certain location */
task automatic wait_mem_update;
input[addr_width-1:0] address;
output[data_width-1:0] dataout;
begin
check_up_add = address >> shft_addr_bits;
check_we = 1;
@(mem_updated);
dataout = updated_data;
check_we = 0;
end
endtask
/* internal task to write data in memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
if(check_we && (addr === check_up_add)) begin
updated_data = data;
-> mem_updated;
end
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : ddr_mem0[addr[25:0]] = data;
6'd1 : ddr_mem1[addr[25:0]] = data;
6'd2 : ddr_mem2[addr[25:0]] = data;
6'd3 : ddr_mem3[addr[25:0]] = data;
endcase
`else
ddr_mem[addr] = data;
`endif
end
endtask
/* internal task to read data from memory */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : data = ddr_mem0[addr[25:0]];
6'd1 : data = ddr_mem1[addr[25:0]];
6'd2 : data = ddr_mem2[addr[25:0]];
6'd3 : data = ddr_mem3[addr[25:0]];
endcase
`else
data = ddr_mem[addr];
`endif
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
//ddr_mem[addr] = wr_temp_data[data_width-1:0];
set_data(addr,wr_temp_data[data_width-1:0]);
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
//temp_rd_data = ddr_mem[addr];
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
get_data(addr,rd_data);
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_reg_map.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
/*** WA for CR # 695818 ***/
`ifdef XILINX_SIMULATOR
`define XSIM_ISIM
`endif
`ifdef XILINX_ISIM
`define XSIM_ISIM
`endif
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_reg_map();
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Register definitions */
`include "processing_system7_bfm_v2_0_5_reg_params.v"
parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB
`ifdef XSIM_ISIM
reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
parameter addr_offset_bits = 26;
`else
reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space
parameter addr_offset_bits = 27;
`endif
/* preload reset_values from file */
task automatic pre_load_rst_values;
input dummy;
begin
`include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
end
endtask
/* writes the reset data into the reg memory */
task automatic set_reset_data;
input [addr_width-1:0] address;
input [data_width-1:0] data;
reg [addr_width-1:0] addr;
begin
addr = address >> 2;
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* writes the data into the reg memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* get the read data from reg mem */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
endcase
`else
data = reg_mem[addr[addr_offset_bits-1:0]];
`endif
end
endtask
/* read chunk of registers */
task read_reg_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
if(no_of_bytes < mem_width ) begin
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - mem_width;
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
initial
begin
pre_load_rst_values(1);
end
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ocm_mem.v
*
* Date : 2012-11
*
* Description : Mimics OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ocm_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
rd_data = ocm_memory[addr];
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_wr_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Writes between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_wr_mem(
sw_clk,
rstn,
full,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_QOS,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* local parameters for interconnect wr fifo model */
input sw_clk, rstn;
output full;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg [axi_qos_width-1:0] WR_QOS;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
wire empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
task automatic write_mem;
input [wr_fifo_data_bits-1:0] data;
begin
wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
end
endtask
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
WR_QOS = 0;
state = SEND_DATA;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
if(!empty) begin
WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin
rd_ptr[intr_cnt_width-2:0] = 0;
end else begin
rd_ptr = rd_ptr+1;
end
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_interconnect_model.v
*
* Date : 2012-11
*
* Description : Mimics Top_interconnect Switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_interconnect_model (
rstn,
sw_clk,
w_qos_gp0,
w_qos_gp1,
w_qos_hp0,
w_qos_hp1,
w_qos_hp2,
w_qos_hp3,
r_qos_gp0,
r_qos_gp1,
r_qos_hp0,
r_qos_hp1,
r_qos_hp2,
r_qos_hp3,
wr_ack_ddr_gp0,
wr_ack_ocm_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ddr_gp0,
wr_dv_ocm_gp0,
rd_req_ddr_gp0,
rd_req_ocm_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ddr_gp0,
rd_data_ocm_gp0,
rd_data_reg_gp0,
rd_dv_ddr_gp0,
rd_dv_ocm_gp0,
rd_dv_reg_gp0,
wr_ack_ddr_gp1,
wr_ack_ocm_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ddr_gp1,
wr_dv_ocm_gp1,
rd_req_ddr_gp1,
rd_req_ocm_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ddr_gp1,
rd_data_ocm_gp1,
rd_data_reg_gp1,
rd_dv_ddr_gp1,
rd_dv_ocm_gp1,
rd_dv_reg_gp1,
wr_ack_ddr_hp0,
wr_ack_ocm_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
wr_dv_ocm_hp0,
rd_req_ddr_hp0,
rd_req_ocm_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_data_ocm_hp0,
rd_dv_ddr_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_ack_ocm_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
wr_dv_ocm_hp1,
rd_req_ddr_hp1,
rd_req_ocm_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_ack_ocm_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
wr_dv_ocm_hp2,
rd_req_ddr_hp2,
rd_req_ocm_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_ack_ocm_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
wr_dv_ocm_hp3,
rd_req_ddr_hp3,
rd_req_ocm_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_data_ocm_hp3,
rd_dv_ddr_hp3,
rd_dv_ocm_hp3,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3,
/* Goes to port1 of OCM */
ocm_wr_qos_port1,
ocm_rd_qos_port1,
ocm_wr_dv_port1,
ocm_wr_data_port1,
ocm_wr_addr_port1,
ocm_wr_bytes_port1,
ocm_wr_ack_port1,
ocm_rd_req_port1,
ocm_rd_data_port1,
ocm_rd_addr_port1,
ocm_rd_bytes_port1,
ocm_rd_dv_port1,
/* Goes to port1 for RegMap */
reg_rd_qos_port1,
reg_rd_req_port1,
reg_rd_data_port1,
reg_rd_addr_port1,
reg_rd_bytes_port1,
reg_rd_dv_port1
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
input [axi_qos_width-1:0] w_qos_gp0;
input [axi_qos_width-1:0] w_qos_gp1;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_gp0;
input [axi_qos_width-1:0] r_qos_gp1;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp3;
output [axi_qos_width-1:0] ocm_wr_qos_port1;
output [axi_qos_width-1:0] ocm_rd_qos_port1;
output wr_ack_ddr_gp0;
output wr_ack_ocm_gp0;
input[max_burst_bits-1:0] wr_data_gp0;
input[addr_width-1:0] wr_addr_gp0;
input[max_burst_bytes_width:0] wr_bytes_gp0;
input wr_dv_ddr_gp0;
input wr_dv_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_reg_gp0;
input[addr_width-1:0] rd_addr_gp0;
input[max_burst_bytes_width:0] rd_bytes_gp0;
output[max_burst_bits-1:0] rd_data_ddr_gp0;
output[max_burst_bits-1:0] rd_data_ocm_gp0;
output[max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ddr_gp0;
output rd_dv_ocm_gp0;
output rd_dv_reg_gp0;
output wr_ack_ddr_gp1;
output wr_ack_ocm_gp1;
input[max_burst_bits-1:0] wr_data_gp1;
input[addr_width-1:0] wr_addr_gp1;
input[max_burst_bytes_width:0] wr_bytes_gp1;
input wr_dv_ddr_gp1;
input wr_dv_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_reg_gp1;
input[addr_width-1:0] rd_addr_gp1;
input[max_burst_bytes_width:0] rd_bytes_gp1;
output[max_burst_bits-1:0] rd_data_ddr_gp1;
output[max_burst_bits-1:0] rd_data_ocm_gp1;
output[max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ddr_gp1;
output rd_dv_ocm_gp1;
output rd_dv_reg_gp1;
output wr_ack_ddr_hp0;
output wr_ack_ocm_hp0;
input[max_burst_bits-1:0] wr_data_hp0;
input[addr_width-1:0] wr_addr_hp0;
input[max_burst_bytes_width:0] wr_bytes_hp0;
input wr_dv_ddr_hp0;
input wr_dv_ocm_hp0;
input rd_req_ddr_hp0;
input rd_req_ocm_hp0;
input[addr_width-1:0] rd_addr_hp0;
input[max_burst_bytes_width:0] rd_bytes_hp0;
output[max_burst_bits-1:0] rd_data_ddr_hp0;
output[max_burst_bits-1:0] rd_data_ocm_hp0;
output rd_dv_ddr_hp0;
output rd_dv_ocm_hp0;
output wr_ack_ddr_hp1;
output wr_ack_ocm_hp1;
input[max_burst_bits-1:0] wr_data_hp1;
input[addr_width-1:0] wr_addr_hp1;
input[max_burst_bytes_width:0] wr_bytes_hp1;
input wr_dv_ddr_hp1;
input wr_dv_ocm_hp1;
input rd_req_ddr_hp1;
input rd_req_ocm_hp1;
input[addr_width-1:0] rd_addr_hp1;
input[max_burst_bytes_width:0] rd_bytes_hp1;
output[max_burst_bits-1:0] rd_data_ddr_hp1;
output[max_burst_bits-1:0] rd_data_ocm_hp1;
output rd_dv_ddr_hp1;
output rd_dv_ocm_hp1;
output wr_ack_ddr_hp2;
output wr_ack_ocm_hp2;
input[max_burst_bits-1:0] wr_data_hp2;
input[addr_width-1:0] wr_addr_hp2;
input[max_burst_bytes_width:0] wr_bytes_hp2;
input wr_dv_ddr_hp2;
input wr_dv_ocm_hp2;
input rd_req_ddr_hp2;
input rd_req_ocm_hp2;
input[addr_width-1:0] rd_addr_hp2;
input[max_burst_bytes_width:0] rd_bytes_hp2;
output[max_burst_bits-1:0] rd_data_ddr_hp2;
output[max_burst_bits-1:0] rd_data_ocm_hp2;
output rd_dv_ddr_hp2;
output rd_dv_ocm_hp2;
output wr_ack_ddr_hp3;
output wr_ack_ocm_hp3;
input[max_burst_bits-1:0] wr_data_hp3;
input[addr_width-1:0] wr_addr_hp3;
input[max_burst_bytes_width:0] wr_bytes_hp3;
input wr_dv_ddr_hp3;
input wr_dv_ocm_hp3;
input rd_req_ddr_hp3;
input rd_req_ocm_hp3;
input[addr_width-1:0] rd_addr_hp3;
input[max_burst_bytes_width:0] rd_bytes_hp3;
output[max_burst_bits-1:0] rd_data_ddr_hp3;
output[max_burst_bits-1:0] rd_data_ocm_hp3;
output rd_dv_ddr_hp3;
output rd_dv_ocm_hp3;
/* Goes to port 1 of DDR */
input ddr_wr_ack_port1;
output ddr_wr_dv_port1;
output ddr_rd_req_port1;
input ddr_rd_dv_port1;
output[addr_width-1:0] ddr_wr_addr_port1;
output[max_burst_bits-1:0] ddr_wr_data_port1;
output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
output[addr_width-1:0] ddr_rd_addr_port1;
input[max_burst_bits-1:0] ddr_rd_data_port1;
output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
output [axi_qos_width-1:0] ddr_wr_qos_port1;
output [axi_qos_width-1:0] ddr_rd_qos_port1;
/* Goes to port2 of DDR */
input ddr_wr_ack_port2;
output ddr_wr_dv_port2;
output ddr_rd_req_port2;
input ddr_rd_dv_port2;
output[addr_width-1:0] ddr_wr_addr_port2;
output[max_burst_bits-1:0] ddr_wr_data_port2;
output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
output[addr_width-1:0] ddr_rd_addr_port2;
input[max_burst_bits-1:0] ddr_rd_data_port2;
output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
output [axi_qos_width-1:0] ddr_wr_qos_port2;
output [axi_qos_width-1:0] ddr_rd_qos_port2;
/* Goes to port3 of DDR */
input ddr_wr_ack_port3;
output ddr_wr_dv_port3;
output ddr_rd_req_port3;
input ddr_rd_dv_port3;
output[addr_width-1:0] ddr_wr_addr_port3;
output[max_burst_bits-1:0] ddr_wr_data_port3;
output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
output[addr_width-1:0] ddr_rd_addr_port3;
input[max_burst_bits-1:0] ddr_rd_data_port3;
output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
output [axi_qos_width-1:0] ddr_wr_qos_port3;
output [axi_qos_width-1:0] ddr_rd_qos_port3;
/* Goes to port1 of OCM */
input ocm_wr_ack_port1;
output ocm_wr_dv_port1;
output ocm_rd_req_port1;
input ocm_rd_dv_port1;
output[max_burst_bits-1:0] ocm_wr_data_port1;
output[addr_width-1:0] ocm_wr_addr_port1;
output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[max_burst_bits-1:0] ocm_rd_data_port1;
output[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
/* Goes to port1 of REG */
output [axi_qos_width-1:0] reg_rd_qos_port1;
output reg_rd_req_port1;
input reg_rd_dv_port1;
input[max_burst_bits-1:0] reg_rd_data_port1;
output[addr_width-1:0] reg_rd_addr_port1;
output[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire ocm_wr_dv_osw0;
wire ocm_wr_dv_osw1;
wire[max_burst_bits-1:0] ocm_wr_data_osw0;
wire[max_burst_bits-1:0] ocm_wr_data_osw1;
wire[addr_width-1:0] ocm_wr_addr_osw0;
wire[addr_width-1:0] ocm_wr_addr_osw1;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
wire ocm_wr_ack_osw0;
wire ocm_wr_ack_osw1;
wire ocm_rd_req_osw0;
wire ocm_rd_req_osw1;
wire[max_burst_bits-1:0] ocm_rd_data_osw0;
wire[max_burst_bits-1:0] ocm_rd_data_osw1;
wire[addr_width-1:0] ocm_rd_addr_osw0;
wire[addr_width-1:0] ocm_rd_addr_osw1;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
wire ocm_rd_dv_osw0;
wire ocm_rd_dv_osw1;
wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
processing_system7_bfm_v2_0_5_fmsw_gp fmsw (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_gp0(w_qos_gp0),
.r_qos_gp0(r_qos_gp0),
.wr_ack_ocm_gp0(wr_ack_ocm_gp0),
.wr_ack_ddr_gp0(wr_ack_ddr_gp0),
.wr_data_gp0(wr_data_gp0),
.wr_addr_gp0(wr_addr_gp0),
.wr_bytes_gp0(wr_bytes_gp0),
.wr_dv_ocm_gp0(wr_dv_ocm_gp0),
.wr_dv_ddr_gp0(wr_dv_ddr_gp0),
.rd_req_ocm_gp0(rd_req_ocm_gp0),
.rd_req_ddr_gp0(rd_req_ddr_gp0),
.rd_req_reg_gp0(rd_req_reg_gp0),
.rd_addr_gp0(rd_addr_gp0),
.rd_bytes_gp0(rd_bytes_gp0),
.rd_data_ddr_gp0(rd_data_ddr_gp0),
.rd_data_ocm_gp0(rd_data_ocm_gp0),
.rd_data_reg_gp0(rd_data_reg_gp0),
.rd_dv_ocm_gp0(rd_dv_ocm_gp0),
.rd_dv_ddr_gp0(rd_dv_ddr_gp0),
.rd_dv_reg_gp0(rd_dv_reg_gp0),
.w_qos_gp1(w_qos_gp1),
.r_qos_gp1(r_qos_gp1),
.wr_ack_ocm_gp1(wr_ack_ocm_gp1),
.wr_ack_ddr_gp1(wr_ack_ddr_gp1),
.wr_data_gp1(wr_data_gp1),
.wr_addr_gp1(wr_addr_gp1),
.wr_bytes_gp1(wr_bytes_gp1),
.wr_dv_ocm_gp1(wr_dv_ocm_gp1),
.wr_dv_ddr_gp1(wr_dv_ddr_gp1),
.rd_req_ocm_gp1(rd_req_ocm_gp1),
.rd_req_ddr_gp1(rd_req_ddr_gp1),
.rd_req_reg_gp1(rd_req_reg_gp1),
.rd_addr_gp1(rd_addr_gp1),
.rd_bytes_gp1(rd_bytes_gp1),
.rd_data_ddr_gp1(rd_data_ddr_gp1),
.rd_data_ocm_gp1(rd_data_ocm_gp1),
.rd_data_reg_gp1(rd_data_reg_gp1),
.rd_dv_ocm_gp1(rd_dv_ocm_gp1),
.rd_dv_ddr_gp1(rd_dv_ddr_gp1),
.rd_dv_reg_gp1(rd_dv_reg_gp1),
.ocm_wr_ack (ocm_wr_ack_osw0),
.ocm_wr_dv (ocm_wr_dv_osw0),
.ocm_rd_req (ocm_rd_req_osw0),
.ocm_rd_dv (ocm_rd_dv_osw0),
.ocm_wr_addr(ocm_wr_addr_osw0),
.ocm_wr_data(ocm_wr_data_osw0),
.ocm_wr_bytes(ocm_wr_bytes_osw0),
.ocm_rd_addr(ocm_rd_addr_osw0),
.ocm_rd_data(ocm_rd_data_osw0),
.ocm_rd_bytes(ocm_rd_bytes_osw0),
.ocm_wr_qos(ocm_wr_qos_osw0),
.ocm_rd_qos(ocm_rd_qos_osw0),
.ddr_wr_qos(ddr_wr_qos_port1),
.ddr_rd_qos(ddr_rd_qos_port1),
.reg_rd_qos(reg_rd_qos_port1),
.ddr_wr_ack(ddr_wr_ack_port1),
.ddr_wr_dv(ddr_wr_dv_port1),
.ddr_rd_req(ddr_rd_req_port1),
.ddr_rd_dv(ddr_rd_dv_port1),
.ddr_wr_addr(ddr_wr_addr_port1),
.ddr_wr_data(ddr_wr_data_port1),
.ddr_wr_bytes(ddr_wr_bytes_port1),
.ddr_rd_addr(ddr_rd_addr_port1),
.ddr_rd_data(ddr_rd_data_port1),
.ddr_rd_bytes(ddr_rd_bytes_port1),
.reg_rd_req(reg_rd_req_port1),
.reg_rd_dv(reg_rd_dv_port1),
.reg_rd_addr(reg_rd_addr_port1),
.reg_rd_data(reg_rd_data_port1),
.reg_rd_bytes(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_5_ssw_hp ssw(
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_data_ocm_hp0(rd_data_ocm_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ocm_hp0(wr_ack_ocm_hp0),
.wr_dv_ocm_hp0(wr_dv_ocm_hp0),
.rd_req_ocm_hp0(rd_req_ocm_hp0),
.rd_dv_ocm_hp0(rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_data_ocm_hp1(rd_data_ocm_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.wr_ack_ocm_hp1(wr_ack_ocm_hp1),
.wr_dv_ocm_hp1(wr_dv_ocm_hp1),
.rd_req_ocm_hp1(rd_req_ocm_hp1),
.rd_dv_ocm_hp1(rd_dv_ocm_hp1),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_data_ocm_hp2(rd_data_ocm_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ocm_hp2(wr_ack_ocm_hp2),
.wr_dv_ocm_hp2(wr_dv_ocm_hp2),
.rd_req_ocm_hp2(rd_req_ocm_hp2),
.rd_dv_ocm_hp2(rd_dv_ocm_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_data_ocm_hp3(rd_data_ocm_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.wr_ack_ocm_hp3(wr_ack_ocm_hp3),
.wr_dv_ocm_hp3(wr_dv_ocm_hp3),
.rd_req_ocm_hp3(rd_req_ocm_hp3),
.rd_dv_ocm_hp3(rd_dv_ocm_hp3),
.ddr_wr_ack0(ddr_wr_ack_port2),
.ddr_wr_dv0(ddr_wr_dv_port2),
.ddr_rd_req0(ddr_rd_req_port2),
.ddr_rd_dv0(ddr_rd_dv_port2),
.ddr_wr_addr0(ddr_wr_addr_port2),
.ddr_wr_data0(ddr_wr_data_port2),
.ddr_wr_bytes0(ddr_wr_bytes_port2),
.ddr_rd_addr0(ddr_rd_addr_port2),
.ddr_rd_data0(ddr_rd_data_port2),
.ddr_rd_bytes0(ddr_rd_bytes_port2),
.ddr_wr_qos0(ddr_wr_qos_port2),
.ddr_rd_qos0(ddr_rd_qos_port2),
.ddr_wr_ack1(ddr_wr_ack_port3),
.ddr_wr_dv1(ddr_wr_dv_port3),
.ddr_rd_req1(ddr_rd_req_port3),
.ddr_rd_dv1(ddr_rd_dv_port3),
.ddr_wr_addr1(ddr_wr_addr_port3),
.ddr_wr_data1(ddr_wr_data_port3),
.ddr_wr_bytes1(ddr_wr_bytes_port3),
.ddr_rd_addr1(ddr_rd_addr_port3),
.ddr_rd_data1(ddr_rd_data_port3),
.ddr_rd_bytes1(ddr_rd_bytes_port3),
.ddr_wr_qos1(ddr_wr_qos_port3),
.ddr_rd_qos1(ddr_rd_qos_port3),
.ocm_wr_qos(ocm_wr_qos_osw1),
.ocm_rd_qos(ocm_rd_qos_osw1),
.ocm_wr_ack (ocm_wr_ack_osw1),
.ocm_wr_dv (ocm_wr_dv_osw1),
.ocm_rd_req (ocm_rd_req_osw1),
.ocm_rd_dv (ocm_rd_dv_osw1),
.ocm_wr_addr(ocm_wr_addr_osw1),
.ocm_wr_data(ocm_wr_data_osw1),
.ocm_wr_bytes(ocm_wr_bytes_osw1),
.ocm_rd_addr(ocm_rd_addr_osw1),
.ocm_rd_data(ocm_rd_data_osw1),
.ocm_rd_bytes(ocm_rd_bytes_osw1)
);
processing_system7_bfm_v2_0_5_arb_wr osw_wr (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_osw0), /// chk
.qos2(ocm_wr_qos_osw1), /// chk
.prt_dv1(ocm_wr_dv_osw0),
.prt_dv2(ocm_wr_dv_osw1),
.prt_data1(ocm_wr_data_osw0),
.prt_data2(ocm_wr_data_osw1),
.prt_addr1(ocm_wr_addr_osw0),
.prt_addr2(ocm_wr_addr_osw1),
.prt_bytes1(ocm_wr_bytes_osw0),
.prt_bytes2(ocm_wr_bytes_osw1),
.prt_ack1(ocm_wr_ack_osw0),
.prt_ack2(ocm_wr_ack_osw1),
.prt_req(ocm_wr_dv_port1),
.prt_qos(ocm_wr_qos_port1),
.prt_data(ocm_wr_data_port1),
.prt_addr(ocm_wr_addr_port1),
.prt_bytes(ocm_wr_bytes_port1),
.prt_ack(ocm_wr_ack_port1)
);
processing_system7_bfm_v2_0_5_arb_rd osw_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_osw0), // chk
.qos2(ocm_rd_qos_osw1), // chk
.prt_req1(ocm_rd_req_osw0),
.prt_req2(ocm_rd_req_osw1),
.prt_data1(ocm_rd_data_osw0),
.prt_data2(ocm_rd_data_osw1),
.prt_addr1(ocm_rd_addr_osw0),
.prt_addr2(ocm_rd_addr_osw1),
.prt_bytes1(ocm_rd_bytes_osw0),
.prt_bytes2(ocm_rd_bytes_osw1),
.prt_dv1(ocm_rd_dv_osw0),
.prt_dv2(ocm_rd_dv_osw1),
.prt_req(ocm_rd_req_port1),
.prt_qos(ocm_rd_qos_port1),
.prt_data(ocm_rd_data_port1),
.prt_addr(ocm_rd_addr_port1),
.prt_bytes(ocm_rd_bytes_port1),
.prt_dv(ocm_rd_dv_port1)
);
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_reset.v
*
* Date : 2012-11
*
* Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
* respective clocks.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_reset(
por_rst_n,
sys_rst_n,
rst_out_n,
m_axi_gp0_clk,
m_axi_gp1_clk,
s_axi_gp0_clk,
s_axi_gp1_clk,
s_axi_hp0_clk,
s_axi_hp1_clk,
s_axi_hp2_clk,
s_axi_hp3_clk,
s_axi_acp_clk,
m_axi_gp0_rstn,
m_axi_gp1_rstn,
s_axi_gp0_rstn,
s_axi_gp1_rstn,
s_axi_hp0_rstn,
s_axi_hp1_rstn,
s_axi_hp2_rstn,
s_axi_hp3_rstn,
s_axi_acp_rstn,
fclk_reset3_n,
fclk_reset2_n,
fclk_reset1_n,
fclk_reset0_n,
fpga_acp_reset_n,
fpga_gp_m0_reset_n,
fpga_gp_m1_reset_n,
fpga_gp_s0_reset_n,
fpga_gp_s1_reset_n,
fpga_hp_s0_reset_n,
fpga_hp_s1_reset_n,
fpga_hp_s2_reset_n,
fpga_hp_s3_reset_n
);
input por_rst_n;
input sys_rst_n;
input m_axi_gp0_clk;
input m_axi_gp1_clk;
input s_axi_gp0_clk;
input s_axi_gp1_clk;
input s_axi_hp0_clk;
input s_axi_hp1_clk;
input s_axi_hp2_clk;
input s_axi_hp3_clk;
input s_axi_acp_clk;
output reg m_axi_gp0_rstn;
output reg m_axi_gp1_rstn;
output reg s_axi_gp0_rstn;
output reg s_axi_gp1_rstn;
output reg s_axi_hp0_rstn;
output reg s_axi_hp1_rstn;
output reg s_axi_hp2_rstn;
output reg s_axi_hp3_rstn;
output reg s_axi_acp_rstn;
output rst_out_n;
output fclk_reset3_n;
output fclk_reset2_n;
output fclk_reset1_n;
output fclk_reset0_n;
output fpga_acp_reset_n;
output fpga_gp_m0_reset_n;
output fpga_gp_m1_reset_n;
output fpga_gp_s0_reset_n;
output fpga_gp_s1_reset_n;
output fpga_hp_s0_reset_n;
output fpga_hp_s1_reset_n;
output fpga_hp_s2_reset_n;
output fpga_hp_s3_reset_n;
reg [31:0] fabric_rst_n;
reg r_m_axi_gp0_rstn;
reg r_m_axi_gp1_rstn;
reg r_s_axi_gp0_rstn;
reg r_s_axi_gp1_rstn;
reg r_s_axi_hp0_rstn;
reg r_s_axi_hp1_rstn;
reg r_s_axi_hp2_rstn;
reg r_s_axi_hp3_rstn;
reg r_s_axi_acp_rstn;
assign rst_out_n = por_rst_n & sys_rst_n;
assign fclk_reset0_n = !fabric_rst_n[0];
assign fclk_reset1_n = !fabric_rst_n[1];
assign fclk_reset2_n = !fabric_rst_n[2];
assign fclk_reset3_n = !fabric_rst_n[3];
assign fpga_acp_reset_n = !fabric_rst_n[24];
assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
task fpga_soft_reset;
input[31:0] reset_ctrl;
begin
fabric_rst_n[0] = reset_ctrl[0];
fabric_rst_n[1] = reset_ctrl[1];
fabric_rst_n[2] = reset_ctrl[2];
fabric_rst_n[3] = reset_ctrl[3];
fabric_rst_n[12] = reset_ctrl[12];
fabric_rst_n[13] = reset_ctrl[13];
fabric_rst_n[16] = reset_ctrl[16];
fabric_rst_n[17] = reset_ctrl[17];
fabric_rst_n[20] = reset_ctrl[20];
fabric_rst_n[21] = reset_ctrl[21];
fabric_rst_n[22] = reset_ctrl[22];
fabric_rst_n[23] = reset_ctrl[23];
fabric_rst_n[24] = reset_ctrl[24];
end
endtask
always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp0_rstn = 1'b0;
else
m_axi_gp0_rstn = 1'b1;
end
always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp1_rstn = 1'b0;
else
m_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp0_rstn = 1'b0;
else
s_axi_gp0_rstn = 1'b1;
end
always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp1_rstn = 1'b0;
else
s_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp0_rstn = 1'b0;
else
s_axi_hp0_rstn = 1'b1;
end
always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp1_rstn = 1'b0;
else
s_axi_hp1_rstn = 1'b1;
end
always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp2_rstn = 1'b0;
else
s_axi_hp2_rstn = 1'b1;
end
always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp3_rstn = 1'b0;
else
s_axi_hp3_rstn = 1'b1;
end
always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_acp_rstn = 1'b0;
else
s_axi_acp_rstn = 1'b1;
end
always@(*) begin
if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin
$display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state");
$finish();
end
end
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_axi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Slave port interface.
* It uses AXI3 Slave BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_axi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_REQ_REG,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_REG,
RD_BYTES,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
RD_DATA_VALID_REG
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter max_wr_outstanding_transactions = 8;
parameter max_rd_outstanding_transactions = 8;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(net_AWVALID && S_AWREADY) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
aw_cnt = aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] = 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] = 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt = 0;
wr_fifo_wr_ptr = 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt = 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(net_ARVALID && S_ARREADY) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] = 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
REG_MEM : RD_REQ_REG = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
rd_fifo_state = WAIT_RD_VALID;
wr_rresp_cnt = wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_cnt = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt = rd_cnt + 1;
rresp_time_cnt = rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] = 0;
end
rd_latency_count = get_rd_lat_number(1);
end
end /// else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_axi_master.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Master port interface.
* It uses AXI3 Master BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_axi_master (
M_RESETN,
M_ARVALID,
M_AWVALID,
M_BREADY,
M_RREADY,
M_WLAST,
M_WVALID,
M_ARID,
M_AWID,
M_WID,
M_ARBURST,
M_ARLOCK,
M_ARSIZE,
M_AWBURST,
M_AWLOCK,
M_AWSIZE,
M_ARPROT,
M_AWPROT,
M_ARADDR,
M_AWADDR,
M_WDATA,
M_ARCACHE,
M_ARLEN,
M_AWCACHE,
M_AWLEN,
M_ARQOS, // not connected to AXI BFM
M_AWQOS, // not connected to AXI BFM
M_WSTRB,
M_ACLK,
M_ARREADY,
M_AWREADY,
M_BVALID,
M_RLAST,
M_RVALID,
M_WREADY,
M_BID,
M_RID,
M_BRESP,
M_RRESP,
M_RDATA
);
parameter enable_this_port = 0;
parameter master_name = "Master";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter ID = 12'hC00;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* IDs for Masters
// l2m1 (CPU000)
12'b11_000_000_00_00
12'b11_010_000_00_00
12'b11_011_000_00_00
12'b11_100_000_00_00
12'b11_101_000_00_00
12'b11_110_000_00_00
12'b11_111_000_00_00
// l2m1 (CPU001)
12'b11_000_001_00_00
12'b11_010_001_00_00
12'b11_011_001_00_00
12'b11_100_001_00_00
12'b11_101_001_00_00
12'b11_110_001_00_00
12'b11_111_001_00_00
*/
input M_RESETN;
output M_ARVALID;
output M_AWVALID;
output M_BREADY;
output M_RREADY;
output M_WLAST;
output M_WVALID;
output [id_bus_width-1:0] M_ARID;
output [id_bus_width-1:0] M_AWID;
output [id_bus_width-1:0] M_WID;
output [axi_brst_type_width-1:0] M_ARBURST;
output [axi_lock_width-1:0] M_ARLOCK;
output [axi_size_width-1:0] M_ARSIZE;
output [axi_brst_type_width-1:0] M_AWBURST;
output [axi_lock_width-1:0] M_AWLOCK;
output [axi_size_width-1:0] M_AWSIZE;
output [axi_prot_width-1:0] M_ARPROT;
output [axi_prot_width-1:0] M_AWPROT;
output [address_bus_width-1:0] M_ARADDR;
output [address_bus_width-1:0] M_AWADDR;
output [data_bus_width-1:0] M_WDATA;
output [axi_cache_width-1:0] M_ARCACHE;
output [axi_len_width-1:0] M_ARLEN;
output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM
output [axi_cache_width-1:0] M_AWCACHE;
output [axi_len_width-1:0] M_AWLEN;
output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM
output [(data_bus_width/8)-1:0] M_WSTRB;
input M_ACLK;
input M_ARREADY;
input M_AWREADY;
input M_BVALID;
input M_RLAST;
input M_RVALID;
input M_WREADY;
input [id_bus_width-1:0] M_BID;
input [id_bus_width-1:0] M_RID;
input [axi_rsp_width-1:0] M_BRESP;
input [axi_rsp_width-1:0] M_RRESP;
input [data_bus_width-1:0] M_RDATA;
wire net_RESETN;
wire net_RVALID;
wire net_BVALID;
reg DEBUG_INFO = 1'b1;
reg STOP_ON_ERROR = 1'b1;
integer use_id_no = 0;
assign M_ARQOS = 'b0;
assign M_AWQOS = 'b0;
assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0;
assign net_RVALID = enable_this_port ? M_RVALID : 1'b0;
assign net_BVALID = enable_this_port ? M_BVALID : 1'b0;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name);
end
end
initial master.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge M_ACLK);
if(!enable_this_port) begin
master.set_channel_level_info(0);
master.set_function_level_info(0);
end
master.RESPONSE_TIMEOUT = 0;
end
cdn_axi3_master_bfm #(master_name,
data_bus_width,
address_bus_width,
id_bus_width,
max_outstanding_transactions,
exclusive_access_supported)
master (.ACLK (M_ACLK),
.ARESETn (net_RESETN), /// confirm this
// Write Address Channel
.AWID (M_AWID),
.AWADDR (M_AWADDR),
.AWLEN (M_AWLEN),
.AWSIZE (M_AWSIZE),
.AWBURST (M_AWBURST),
.AWLOCK (M_AWLOCK),
.AWCACHE (M_AWCACHE),
.AWPROT (M_AWPROT),
.AWVALID (M_AWVALID),
.AWREADY (M_AWREADY),
// Write Data Channel Signals.
.WID (M_WID),
.WDATA (M_WDATA),
.WSTRB (M_WSTRB),
.WLAST (M_WLAST),
.WVALID (M_WVALID),
.WREADY (M_WREADY),
// Write Response Channel Signals.
.BID (M_BID),
.BRESP (M_BRESP),
.BVALID (net_BVALID),
.BREADY (M_BREADY),
// Read Address Channel Signals.
.ARID (M_ARID),
.ARADDR (M_ARADDR),
.ARLEN (M_ARLEN),
.ARSIZE (M_ARSIZE),
.ARBURST (M_ARBURST),
.ARLOCK (M_ARLOCK),
.ARCACHE (M_ARCACHE),
.ARPROT (M_ARPROT),
.ARVALID (M_ARVALID),
.ARREADY (M_ARREADY),
// Read Data Channel Signals.
.RID (M_RID),
.RDATA (M_RDATA),
.RRESP (M_RRESP),
.RLAST (M_RLAST),
.RVALID (net_RVALID),
.RREADY (M_RREADY));
/* Call to BFM APIs */
task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
else
master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
/* local */
function automatic[id_bus_width-1:0] get_id;
input dummy;
begin
case(use_id_no)
// l2m1 (CPU000)
0 : get_id = 12'b11_000_000_00_00;
1 : get_id = 12'b11_010_000_00_00;
2 : get_id = 12'b11_011_000_00_00;
3 : get_id = 12'b11_100_000_00_00;
4 : get_id = 12'b11_101_000_00_00;
5 : get_id = 12'b11_110_000_00_00;
6 : get_id = 12'b11_111_000_00_00;
// l2m1 (CPU001)
7 : get_id = 12'b11_000_001_00_00;
8 : get_id = 12'b11_010_001_00_00;
9 : get_id = 12'b11_011_001_00_00;
10 : get_id = 12'b11_100_001_00_00;
11 : get_id = 12'b11_101_001_00_00;
12 : get_id = 12'b11_110_001_00_00;
13 : get_id = 12'b11_111_001_00_00;
endcase
if(use_id_no == 13)
use_id_no = 0;
else
use_id_no = use_id_no+1;
end
endfunction
/* Write data from file */
task automatic write_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] wr_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
integer bytes;
integer trnsfr_bytes;
integer wr_fd;
integer succ;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
bytes = wr_size;
wresp = 0;
concurrent = 1;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_bytes = (axi_burst_len * data_bus_width/8);
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wr_id = ID;
wr_fd = $fopen(file_name,"r");
while (bytes > 0) begin
repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
wr_data = wr_data >> data_bus_width;
succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
end
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes >= (axi_burst_len * data_bus_width/8) )
trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data to file */
task automatic read_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] rd_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp, rrrsp;
reg [addr_width-1:0] addr;
integer bytes;
integer trnsfr_lngth;
reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
integer rd_fd;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
rresp = 0;
bytes = rd_size;
rd_id = ID;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rd_fd = $fopen(file_name,"w");
while (bytes > 0) begin
master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
repeat(trnsfr_lngth+1) begin
$fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
rd_data = rd_data >> data_bus_width;
end
addr = addr + (trnsfr_lngth+1)*4;
if(bytes >= (axi_burst_len * data_bus_width/8) )
bytes = bytes - (axi_burst_len * data_bus_width/8); //
else
bytes = 0;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rresp = rresp | rrrsp;
end /// while
response = rresp;
end
end
endtask
/* Write data (used for transfer size <= 128 Bytes */
task automatic write_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] wr_size;
input [(max_transfer_bytes*8)-1:0] w_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [7:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1:0] wr_data;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = wr_size;
wresp = 0;
wr_data = w_data;
concurrent = 1;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
wr_id = ID;
if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
wr_data = wr_data >> (trnsfr_bytes*8);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data (used for transfer size <= 128 Bytes */
task automatic read_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] rd_size;
output [(max_transfer_bytes*8)-1:0] r_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp,rdrsp;
reg [addr_width-1:0] addr;
reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1 : 0] rd_data;
reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
integer total_rcvd_bytes;
integer trnsfr_lngth;
integer i;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = rd_size;
rresp = 0;
total_rcvd_bytes = 0;
rd_data = 0;
rd_id = ID;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
for(i = 0; i < trnsfr_bytes; i = i+1) begin
rd_data = rd_data >> 8;
rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
rcv_rd_data = rcv_rd_data >> 8;
total_rcvd_bytes = total_rcvd_bytes+1;
end
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = 15;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
rresp = rresp | rdrsp;
end /// while
rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
r_data = rd_data;
response = rresp;
end
end
endtask
/* Wait Register Update in PL */
/* Issue a series of 1 burst length reads until the expected data pattern is received */
task automatic wait_reg_update;
input [addr_width-1:0] addri;
input [data_width-1:0] datai;
input [data_width-1:0] maski;
input [int_width-1:0] time_interval;
input [int_width-1:0] time_out;
output [data_width-1:0] data_o;
output upd_done;
reg [addr_width-1:0] addr;
reg [data_width-1:0] data_i;
reg [data_width-1:0] mask_i;
integer time_int;
integer timeout;
reg [axi_rsp_width-1:0] rdrsp;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
reg [data_width-1:0] rcv_data;
integer trnsfr_lngth;
reg rd_loop;
reg timed_out;
integer i;
integer cycle_cnt;
begin
addr = addri;
data_i = datai;
mask_i = maski;
time_int = time_interval;
timeout = time_out;
timed_out = 0;
cycle_cnt = 0;
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name);
upd_done = 0;
if(STOP_ON_ERROR) $stop;
end else begin
rd_id = ID;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
trnsfr_lngth = 0;
rd_loop = 1;
fork
begin
while(!timed_out & rd_loop) begin
cycle_cnt = cycle_cnt + 1;
if(cycle_cnt >= timeout) timed_out = 1;
@(posedge M_ACLK);
end
end
begin
while (rd_loop) begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr);
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data);
if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
rd_loop = 0;
else
repeat(time_int) @(posedge M_ACLK);
end /// while
end
join
data_o = rcv_data & ~mask_i;
if(timed_out) begin
$display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else
upd_done = 1;
end
end
endtask
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v
*
* Date : 2012-11
*
* Description : Processing_system7_bfm Top (zynq_bfm top)
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_processing_system7_bfm
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
/* parameters for gen_clk */
parameter C_FCLK_CLK0_FREQ = 50;
parameter C_FCLK_CLK1_FREQ = 50;
parameter C_FCLK_CLK3_FREQ = 50;
parameter C_FCLK_CLK2_FREQ = 50;
parameter C_HIGH_OCM_EN = 0;
/* parameters for HP ports */
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_S_AXI_HP0_DATA_WIDTH = 32;
parameter C_S_AXI_HP1_DATA_WIDTH = 32;
parameter C_S_AXI_HP2_DATA_WIDTH = 32;
parameter C_S_AXI_HP3_DATA_WIDTH = 32;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
/* Do we need these
parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF;
/* parameters for GP and ACP ports */
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 1;
parameter C_USE_S_AXI_GP1 = 1;
/* Do we need this?
parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_USE_S_AXI_ACP = 1;
parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF;
`include "processing_system7_bfm_v2_0_5_local_params.v"
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [5:0] S_AXI_HP0_BID;
output [5:0] S_AXI_HP0_RID;
output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [5:0] S_AXI_HP0_ARID;
input [5:0] S_AXI_HP0_AWID;
input [5:0] S_AXI_HP0_WID;
input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [irq_width-1:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
/* Reset Input & Clock Input */
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
/* Internal wires/nets used for connectivity */
wire net_rstn;
wire net_sw_clk;
wire net_ocm_clk;
wire net_arbiter_clk;
wire net_axi_mgp0_rstn;
wire net_axi_mgp1_rstn;
wire net_axi_gp0_rstn;
wire net_axi_gp1_rstn;
wire net_axi_hp0_rstn;
wire net_axi_hp1_rstn;
wire net_axi_hp2_rstn;
wire net_axi_hp3_rstn;
wire net_axi_acp_rstn;
wire [4:0] net_axi_acp_awuser;
wire [4:0] net_axi_acp_aruser;
/* Dummy */
assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
/* Global variables */
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1;
/* local variable acting as semaphore for wait_mem_update and wait_reg_update task */
reg mem_update_key = 1;
reg reg_update_key_0 = 1;
reg reg_update_key_1 = 1;
/* assignments and semantic checks for unused ports */
`include "processing_system7_bfm_v2_0_5_unused_ports.v"
/* include api definition */
`include "processing_system7_bfm_v2_0_5_apis.v"
/* Reset Generator */
processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB),
.sys_rst_n(PS_SRSTB),
.rst_out_n(net_rstn),
.m_axi_gp0_clk(M_AXI_GP0_ACLK),
.m_axi_gp1_clk(M_AXI_GP1_ACLK),
.s_axi_gp0_clk(S_AXI_GP0_ACLK),
.s_axi_gp1_clk(S_AXI_GP1_ACLK),
.s_axi_hp0_clk(S_AXI_HP0_ACLK),
.s_axi_hp1_clk(S_AXI_HP1_ACLK),
.s_axi_hp2_clk(S_AXI_HP2_ACLK),
.s_axi_hp3_clk(S_AXI_HP3_ACLK),
.s_axi_acp_clk(S_AXI_ACP_ACLK),
.m_axi_gp0_rstn(net_axi_mgp0_rstn),
.m_axi_gp1_rstn(net_axi_mgp1_rstn),
.s_axi_gp0_rstn(net_axi_gp0_rstn),
.s_axi_gp1_rstn(net_axi_gp1_rstn),
.s_axi_hp0_rstn(net_axi_hp0_rstn),
.s_axi_hp1_rstn(net_axi_hp1_rstn),
.s_axi_hp2_rstn(net_axi_hp2_rstn),
.s_axi_hp3_rstn(net_axi_hp3_rstn),
.s_axi_acp_rstn(net_axi_acp_rstn),
.fclk_reset3_n(FCLK_RESET3_N),
.fclk_reset2_n(FCLK_RESET2_N),
.fclk_reset1_n(FCLK_RESET1_N),
.fclk_reset0_n(FCLK_RESET0_N),
.fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
.fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
.fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
.fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
.fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
.fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
.fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
.fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
.fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN)
);
/* Clock Generator */
processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
gen_clk(.ps_clk(PS_CLK),
.sw_clk(net_sw_clk),
.fclk_clk3(FCLK_CLK3),
.fclk_clk2(FCLK_CLK2),
.fclk_clk1(FCLK_CLK1),
.fclk_clk0(FCLK_CLK0)
);
wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
wire [max_burst_bits-1:0] net_wr_data_acp;
wire [addr_width-1:0] net_wr_addr_acp;
wire [max_burst_bytes_width:0] net_wr_bytes_acp;
wire [axi_qos_width-1:0] net_wr_qos_acp;
wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
wire [addr_width-1:0] net_rd_addr_acp;
wire [max_burst_bytes_width:0] net_rd_bytes_acp;
wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
wire [axi_qos_width-1:0] net_rd_qos_acp;
wire ocm_wr_ack_port0;
wire ocm_wr_dv_port0;
wire ocm_rd_req_port0;
wire ocm_rd_dv_port0;
wire [addr_width-1:0] ocm_wr_addr_port0;
wire [max_burst_bits-1:0] ocm_wr_data_port0;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
wire [addr_width-1:0] ocm_rd_addr_port0;
wire [max_burst_bits-1:0] ocm_rd_data_port0;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
wire [axi_qos_width-1:0] ocm_wr_qos_port0;
wire [axi_qos_width-1:0] ocm_rd_qos_port0;
wire ocm_wr_ack_port1;
wire ocm_wr_dv_port1;
wire ocm_rd_req_port1;
wire ocm_rd_dv_port1;
wire [addr_width-1:0] ocm_wr_addr_port1;
wire [max_burst_bits-1:0] ocm_wr_data_port1;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
wire [addr_width-1:0] ocm_rd_addr_port1;
wire [max_burst_bits-1:0] ocm_rd_data_port1;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
wire [axi_qos_width-1:0] ocm_wr_qos_port1;
wire [axi_qos_width-1:0] ocm_rd_qos_port1;
wire ddr_wr_ack_port0;
wire ddr_wr_dv_port0;
wire ddr_rd_req_port0;
wire ddr_rd_dv_port0;
wire[addr_width-1:0] ddr_wr_addr_port0;
wire[max_burst_bits-1:0] ddr_wr_data_port0;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
wire[addr_width-1:0] ddr_rd_addr_port0;
wire[max_burst_bits-1:0] ddr_rd_data_port0;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
wire [axi_qos_width-1:0] ddr_wr_qos_port0;
wire [axi_qos_width-1:0] ddr_rd_qos_port0;
wire ddr_wr_ack_port1;
wire ddr_wr_dv_port1;
wire ddr_rd_req_port1;
wire ddr_rd_dv_port1;
wire[addr_width-1:0] ddr_wr_addr_port1;
wire[max_burst_bits-1:0] ddr_wr_data_port1;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
wire[addr_width-1:0] ddr_rd_addr_port1;
wire[max_burst_bits-1:0] ddr_rd_data_port1;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
wire[axi_qos_width-1:0] ddr_wr_qos_port1;
wire[axi_qos_width-1:0] ddr_rd_qos_port1;
wire ddr_wr_ack_port2;
wire ddr_wr_dv_port2;
wire ddr_rd_req_port2;
wire ddr_rd_dv_port2;
wire[addr_width-1:0] ddr_wr_addr_port2;
wire[max_burst_bits-1:0] ddr_wr_data_port2;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
wire[addr_width-1:0] ddr_rd_addr_port2;
wire[max_burst_bits-1:0] ddr_rd_data_port2;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
wire[axi_qos_width-1:0] ddr_wr_qos_port2;
wire[axi_qos_width-1:0] ddr_rd_qos_port2;
wire ddr_wr_ack_port3;
wire ddr_wr_dv_port3;
wire ddr_rd_req_port3;
wire ddr_rd_dv_port3;
wire[addr_width-1:0] ddr_wr_addr_port3;
wire[max_burst_bits-1:0] ddr_wr_data_port3;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
wire[addr_width-1:0] ddr_rd_addr_port3;
wire[max_burst_bits-1:0] ddr_rd_data_port3;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
wire[axi_qos_width-1:0] ddr_wr_qos_port3;
wire[axi_qos_width-1:0] ddr_rd_qos_port3;
wire reg_rd_req_port0;
wire reg_rd_dv_port0;
wire[addr_width-1:0] reg_rd_addr_port0;
wire[max_burst_bits-1:0] reg_rd_data_port0;
wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
wire [axi_qos_width-1:0] reg_rd_qos_port0;
wire reg_rd_req_port1;
wire reg_rd_dv_port1;
wire[addr_width-1:0] reg_rd_addr_port1;
wire[max_burst_bits-1:0] reg_rd_data_port1;
wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire [axi_qos_width-1:0] reg_rd_qos_port1;
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
function [5:0] compress_id;
input [11:0] id;
begin
compress_id = id[5:0];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
uncompress_id = {6'b110000, id[5:0]};
end
endfunction
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
processing_system7_bfm_v2_0_5_interconnect_model icm (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
.w_qos_gp0(net_wr_qos_gp0),
.w_qos_gp1(net_wr_qos_gp1),
.w_qos_hp0(net_wr_qos_hp0),
.w_qos_hp1(net_wr_qos_hp1),
.w_qos_hp2(net_wr_qos_hp2),
.w_qos_hp3(net_wr_qos_hp3),
.r_qos_gp0(net_rd_qos_gp0),
.r_qos_gp1(net_rd_qos_gp1),
.r_qos_hp0(net_rd_qos_hp0),
.r_qos_hp1(net_rd_qos_hp1),
.r_qos_hp2(net_rd_qos_hp2),
.r_qos_hp3(net_rd_qos_hp3),
/* GP Slave ports access */
.wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
.wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
.wr_data_gp0(net_wr_data_gp0),
.wr_addr_gp0(net_wr_addr_gp0),
.wr_bytes_gp0(net_wr_bytes_gp0),
.wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
.wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
.rd_req_ddr_gp0(net_rd_req_ddr_gp0),
.rd_req_ocm_gp0(net_rd_req_ocm_gp0),
.rd_req_reg_gp0(net_rd_req_reg_gp0),
.rd_addr_gp0(net_rd_addr_gp0),
.rd_bytes_gp0(net_rd_bytes_gp0),
.rd_data_ddr_gp0(net_rd_data_ddr_gp0),
.rd_data_ocm_gp0(net_rd_data_ocm_gp0),
.rd_data_reg_gp0(net_rd_data_reg_gp0),
.rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
.rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
.rd_dv_reg_gp0(net_rd_dv_reg_gp0),
.wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
.wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
.wr_data_gp1(net_wr_data_gp1),
.wr_addr_gp1(net_wr_addr_gp1),
.wr_bytes_gp1(net_wr_bytes_gp1),
.wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
.wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
.rd_req_ddr_gp1(net_rd_req_ddr_gp1),
.rd_req_ocm_gp1(net_rd_req_ocm_gp1),
.rd_req_reg_gp1(net_rd_req_reg_gp1),
.rd_addr_gp1(net_rd_addr_gp1),
.rd_bytes_gp1(net_rd_bytes_gp1),
.rd_data_ddr_gp1(net_rd_data_ddr_gp1),
.rd_data_ocm_gp1(net_rd_data_ocm_gp1),
.rd_data_reg_gp1(net_rd_data_reg_gp1),
.rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
.rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
.rd_dv_reg_gp1(net_rd_dv_reg_gp1),
/* HP Slave ports access */
.wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
.wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
.wr_data_hp0(net_wr_data_hp0),
.wr_addr_hp0(net_wr_addr_hp0),
.wr_bytes_hp0(net_wr_bytes_hp0),
.wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
.wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
.rd_req_ddr_hp0(net_rd_req_ddr_hp0),
.rd_req_ocm_hp0(net_rd_req_ocm_hp0),
.rd_addr_hp0(net_rd_addr_hp0),
.rd_bytes_hp0(net_rd_bytes_hp0),
.rd_data_ddr_hp0(net_rd_data_ddr_hp0),
.rd_data_ocm_hp0(net_rd_data_ocm_hp0),
.rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
.rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
.wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
.wr_data_hp1(net_wr_data_hp1),
.wr_addr_hp1(net_wr_addr_hp1),
.wr_bytes_hp1(net_wr_bytes_hp1),
.wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
.wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
.rd_req_ddr_hp1(net_rd_req_ddr_hp1),
.rd_req_ocm_hp1(net_rd_req_ocm_hp1),
.rd_addr_hp1(net_rd_addr_hp1),
.rd_bytes_hp1(net_rd_bytes_hp1),
.rd_data_ddr_hp1(net_rd_data_ddr_hp1),
.rd_data_ocm_hp1(net_rd_data_ocm_hp1),
.rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
.rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
.wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
.wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
.wr_data_hp2(net_wr_data_hp2),
.wr_addr_hp2(net_wr_addr_hp2),
.wr_bytes_hp2(net_wr_bytes_hp2),
.wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
.wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
.rd_req_ddr_hp2(net_rd_req_ddr_hp2),
.rd_req_ocm_hp2(net_rd_req_ocm_hp2),
.rd_addr_hp2(net_rd_addr_hp2),
.rd_bytes_hp2(net_rd_bytes_hp2),
.rd_data_ddr_hp2(net_rd_data_ddr_hp2),
.rd_data_ocm_hp2(net_rd_data_ocm_hp2),
.rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
.rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
.wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
.wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
.wr_data_hp3(net_wr_data_hp3),
.wr_addr_hp3(net_wr_addr_hp3),
.wr_bytes_hp3(net_wr_bytes_hp3),
.wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
.wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
.rd_req_ddr_hp3(net_rd_req_ddr_hp3),
.rd_req_ocm_hp3(net_rd_req_ocm_hp3),
.rd_addr_hp3(net_rd_addr_hp3),
.rd_bytes_hp3(net_rd_bytes_hp3),
.rd_data_ddr_hp3(net_rd_data_ddr_hp3),
.rd_data_ocm_hp3(net_rd_data_ocm_hp3),
.rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
.rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1(ddr_wr_ack_port1),
.ddr_wr_dv_port1(ddr_wr_dv_port1),
.ddr_rd_req_port1(ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1(ddr_wr_qos_port1),
.ddr_rd_qos_port1(ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1),
/* Goes to port 0 of REG */
.reg_rd_qos_port1 (reg_rd_qos_port1) ,
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_5_ddrc ddrc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of DDR */
.ddr_wr_ack_port0 (ddr_wr_ack_port0),
.ddr_wr_dv_port0 (ddr_wr_dv_port0),
.ddr_rd_req_port0 (ddr_rd_req_port0),
.ddr_rd_dv_port0 (ddr_rd_dv_port0),
.ddr_wr_addr_port0(net_wr_addr_acp),
.ddr_wr_data_port0(net_wr_data_acp),
.ddr_wr_bytes_port0(net_wr_bytes_acp),
.ddr_rd_addr_port0(net_rd_addr_acp),
.ddr_rd_bytes_port0(net_rd_bytes_acp),
.ddr_rd_data_port0(ddr_rd_data_port0),
.ddr_wr_qos_port0 (net_wr_qos_acp),
.ddr_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1 (ddr_wr_ack_port1),
.ddr_wr_dv_port1 (ddr_wr_dv_port1),
.ddr_rd_req_port1 (ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1 (ddr_wr_qos_port1),
.ddr_rd_qos_port1 (ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3)
);
processing_system7_bfm_v2_0_5_ocmc ocmc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port0 (ocm_wr_ack_port0),
.ocm_wr_dv_port0 (ocm_wr_dv_port0),
.ocm_rd_req_port0 (ocm_rd_req_port0),
.ocm_rd_dv_port0 (ocm_rd_dv_port0),
.ocm_wr_addr_port0(net_wr_addr_acp),
.ocm_wr_data_port0(net_wr_data_acp),
.ocm_wr_bytes_port0(net_wr_bytes_acp),
.ocm_rd_addr_port0(net_rd_addr_acp),
.ocm_rd_bytes_port0(net_rd_bytes_acp),
.ocm_rd_data_port0(ocm_rd_data_port0),
.ocm_wr_qos_port0 (net_wr_qos_acp),
.ocm_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1)
);
processing_system7_bfm_v2_0_5_regc regc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of REG */
.reg_rd_req_port0 (reg_rd_req_port0),
.reg_rd_dv_port0 (reg_rd_dv_port0),
.reg_rd_addr_port0(net_rd_addr_acp),
.reg_rd_bytes_port0(net_rd_bytes_acp),
.reg_rd_data_port0(reg_rd_data_port0),
.reg_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of REG */
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1),
.reg_rd_qos_port1(reg_rd_qos_port1)
);
/* include axi_gp port instantiations */
`include "processing_system7_bfm_v2_0_5_axi_gp.v"
/* include axi_hp port instantiations */
`include "processing_system7_bfm_v2_0_5_axi_hp.v"
/* include axi_acp port instantiations */
`include "processing_system7_bfm_v2_0_5_axi_acp.v"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_2_V
`define SKY130_FD_SC_MS__A2BB2OI_2_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_2_V
|
// part of NeoGS project
//
// (c) NedoPC 2007-2019
module chan_ctrl
(
input wire clk, // 24.0 MHz
input wire rst_n,
// memory interface
output reg [ 6:0] rd_addr,
input wire [31:0] rd_data,
//
output reg [ 6:0] wr_addr,
output wire [31:0] wr_data,
output reg wr_stb,
// 37500 Hz period strobe (1-cycle strobe)
input wire sync_stb,
// channel enables
input wire [31:0] ch_enas,
// output data
output reg [ 7:0] out_data,
output reg out_stb_addr, // strobes address sequence (addrhi/mid/lo)
output reg out_stb_mix // strobes mix sequence (frac/vl/vr)
// sequence: addrhi, addrmid, addrlo; frac, vl, vr (6 bytes)
);
reg [ 5:0] curr_ch; // current channel number
wire stop = curr_ch[5];
// channel fetch state machine
reg [3:0] st;
reg [3:0] next_st;
// channel enable
wire ch_ena = ch_enas[curr_ch[4:0]];
// offset storage
reg [31:0] offset;
reg off_cy; // extra carry [32th bit]
// offset>=size flag
reg oversize;
// volumes storage
reg [5:0] vol_left;
reg [5:0] vol_right;
// miscellaneous
reg loopena;
reg surround;
// base address
reg [21:0] base;
// emit control
reg [1:0] addr_emit;
///////////////////////
// states definition //
///////////////////////
localparam ST_BEGIN = 4'd0;
localparam ST_GETOFFS = 4'd1; // when offset value arrives
localparam ST_GETADDVOL = 4'd2; // whed add and volumes arrive
localparam ST_GETSIZE = 4'd3; // size and part of base address arrive
localparam ST_GETLOOP = 4'd4; // when loop and last part of base address arrive
localparam ST_SAVEOFFS = 4'd5;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
//localparam ST_ = 4'd;
localparam ST_NEXT = 4'd14;
localparam ST_WAIT = 4'd15;
always @(posedge clk)
if( st==ST_WAIT )
curr_ch[5:0] <= 6'd0;
else if( st==ST_NEXT )
curr_ch[5:0] <= curr_ch[5:0] + 6'd1;
always @(posedge clk, negedge rst_n)
if( !rst_n )
st <= ST_WAIT;
else
st <= next_st;
//
always @*
case( st )
//////////////////////////////////////////////////////////////////////
ST_BEGIN:
if( stop )
next_st = ST_WAIT;
else if( !ch_ena )
next_st = ST_NEXT;
else
next_st = ST_GETOFFS;
///////////////////////////////////////////////////////////////////////
ST_GETOFFS:
next_st = ST_GETADDVOL;
///////////////////////////////////////////////////////////////////////
ST_GETADDVOL:
next_st = ST_GETSIZE;
///////////////////////////////////////////////////////////////////////
ST_GETSIZE:
next_st = ST_GETLOOP;
///////////////////////////////////////////////////////////////////////
ST_GETLOOP:
next_st = ST_SAVEOFFS;
///////////////////////////////////////////////////////////////////////
ST_SAVEOFFS:
next_st = ST_NEXT;
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ST_NEXT:
next_st = ST_BEGIN;
///////////////////////////////////////////////////////////////////////
ST_WAIT:
if( sync_stb )
next_st = ST_BEGIN;
else
next_st = ST_WAIT;
////////////////////////////////////////////////
///////////////////////
default: next_st = ST_WAIT;
///////////////////////////////////////////////////////////////////////
endcase
// state memory address control
always @*
rd_addr[6:2] <= curr_ch[4:0];
always @*
wr_addr[6:2] <= curr_ch[4:0];
always @(posedge clk)
wr_addr[1:0] <= 2'd0;
//
always @(posedge clk)
if( st==ST_NEXT || st==ST_WAIT )
begin
rd_addr[1:0] <= 2'd0;
end
else if( st==ST_BEGIN || st==ST_GETOFFS || st==ST_GETADDVOL )
begin
rd_addr[1:0] <= rd_addr[1:0] + 2'd1;
end
// offset register control
always @(posedge clk)
if( st==ST_GETOFFS )
offset <= rd_data;
else if( st==ST_GETADDVOL )
{off_cy, offset} <= {1'b0, offset} + {1'b0, 14'd0, rd_data[31:14]};
else if( st==ST_GETLOOP )
offset[31:12] <= oversize ? (offset[31:12]+rd_data[27:8]) : offset[31:12]; // TODO: or maybe rd_data & {20{oversize}} ?
// offset overflow control
always @(posedge clk)
if( st==ST_GETSIZE )
oversize <= ( {off_cy,offset[31:12]} >= {1'b0, rd_data[27:8]} );
// offset writeback
always @(posedge clk)
wr_stb <= st==ST_SAVEOFFS;
//
assign wr_data = offset;
// volumes and miscellaneous
always @(posedge clk)
if( st==ST_GETADDVOL )
begin
vol_left <= rd_data[11:6];
vol_right <= rd_data[ 5:0];
loopena <= rd_data[13];
surround <= rd_data[12];
end
// base address calc
always @(posedge clk)
if( st==ST_GETSIZE )
base[15:8] <= rd_data[7:0];
else if( st==ST_GETLOOP )
base[21:16] <= rd_data[5:0];
else if( st==ST_SAVEOFFS )
begin
base[7:0] <= offset[19:12];
base[21:8] <= base[21:8] + {2'd0,offset[31:20]};
end
// emitting data to fifos
always @(posedge clk, negedge rst_n)
if( !rst_n )
addr_emit <= 2'd0;
else
addr_emit[1:0] <= {addr_emit[0], st==ST_NEXT};
//
always @(posedge clk)
if( st==ST_GETSIZE )
out_data <= offset[11:4];
else if( st==ST_GETLOOP )
out_data <= {2'd0, vol_left[5:0]};
else if( st==ST_SAVEOFFS )
out_data <= {2'd0, vol_right[5:0] ^ {6{surround}}};
else if( st==ST_NEXT )
out_data <= {2'd0, base[21:16]};
else if( addr_emit[0] )
out_data <= base[15:8];
else
out_data <= base[7:0];
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_mix <= 1'b0;
else
out_stb_mix <= (st==ST_GETSIZE) ||
(st==ST_GETLOOP) ||
(st==ST_SAVEOFFS) ;
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
out_stb_addr <= 1'b0;
else
out_stb_addr <= (st==ST_NEXT) || addr_emit;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:54:07 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112,
n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134,
n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145;
NAND2XLTS U50 ( .A(n86), .B(n127), .Y(n129) );
NOR2X2TS U51 ( .A(n112), .B(in1[14]), .Y(n122) );
OR2X2TS U52 ( .A(n115), .B(in1[13]), .Y(n86) );
NAND2X1TS U53 ( .A(n110), .B(add_sub), .Y(n111) );
NAND2X1TS U54 ( .A(n58), .B(n61), .Y(n57) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n113), .Y(n110) );
NOR2X1TS U56 ( .A(n113), .B(n78), .Y(n114) );
INVX2TS U57 ( .A(in1[11]), .Y(n61) );
CLKXOR2X2TS U58 ( .A(n103), .B(in2[11]), .Y(n131) );
NAND2XLTS U59 ( .A(n100), .B(add_sub), .Y(n99) );
NOR2X2TS U60 ( .A(n106), .B(in2[12]), .Y(n113) );
OR2X2TS U61 ( .A(n136), .B(in1[7]), .Y(n51) );
INVX2TS U62 ( .A(in2[9]), .Y(n38) );
XNOR2X2TS U63 ( .A(n88), .B(in2[6]), .Y(n94) );
NAND2X1TS U64 ( .A(n95), .B(in2[7]), .Y(n53) );
NAND2X1TS U65 ( .A(n78), .B(in2[7]), .Y(n52) );
CLKINVX6TS U66 ( .A(add_sub), .Y(n78) );
INVX2TS U67 ( .A(in2[7]), .Y(n63) );
NOR2X1TS U68 ( .A(n102), .B(n78), .Y(n103) );
XNOR2X2TS U69 ( .A(n101), .B(in2[12]), .Y(n117) );
XNOR2X4TS U70 ( .A(n111), .B(in2[14]), .Y(n112) );
INVX2TS U71 ( .A(in2[5]), .Y(n75) );
NOR2X2TS U72 ( .A(n127), .B(n48), .Y(n47) );
NAND3X4TS U73 ( .A(n54), .B(n53), .C(n52), .Y(n136) );
NAND2X2TS U74 ( .A(n91), .B(add_sub), .Y(n88) );
NAND2X6TS U75 ( .A(n41), .B(n75), .Y(n91) );
NOR2X2TS U76 ( .A(n41), .B(n78), .Y(n90) );
NAND2X4TS U77 ( .A(n72), .B(n73), .Y(n64) );
INVX2TS U78 ( .A(n117), .Y(n72) );
NOR2X4TS U79 ( .A(n100), .B(in2[10]), .Y(n102) );
OR2X4TS U80 ( .A(n95), .B(n55), .Y(n54) );
NOR2X4TS U81 ( .A(n96), .B(in2[8]), .Y(n98) );
NAND2X6TS U82 ( .A(n63), .B(n95), .Y(n96) );
NAND2X2TS U83 ( .A(n119), .B(n118), .Y(n121) );
INVX2TS U84 ( .A(n122), .Y(n124) );
NAND2X4TS U85 ( .A(n37), .B(n69), .Y(n68) );
XNOR2X2TS U86 ( .A(n107), .B(in2[15]), .Y(n108) );
INVX2TS U87 ( .A(n131), .Y(n58) );
NAND2X6TS U88 ( .A(n137), .B(n51), .Y(n50) );
XNOR2X2TS U89 ( .A(n99), .B(in2[10]), .Y(n104) );
NAND2X4TS U90 ( .A(n98), .B(n38), .Y(n100) );
XOR2X1TS U91 ( .A(n126), .B(n125), .Y(res[14]) );
AND2X4TS U92 ( .A(n47), .B(n43), .Y(n42) );
AND2X4TS U93 ( .A(n46), .B(n71), .Y(n45) );
NAND2X2TS U94 ( .A(n108), .B(in1[15]), .Y(n118) );
NAND2X6TS U95 ( .A(n68), .B(n67), .Y(n132) );
NAND2X2TS U96 ( .A(n112), .B(in1[14]), .Y(n123) );
NOR2X2TS U97 ( .A(n108), .B(in1[15]), .Y(n109) );
NAND2X2TS U98 ( .A(n117), .B(in1[12]), .Y(n71) );
OAI21X2TS U99 ( .A0(n110), .A1(in2[14]), .B0(add_sub), .Y(n107) );
NAND2X6TS U100 ( .A(n135), .B(in1[8]), .Y(n69) );
NAND2BX2TS U101 ( .AN(n61), .B(n131), .Y(n60) );
NAND2BXLTS U102 ( .AN(in1[4]), .B(n145), .Y(res[4]) );
OAI21XLTS U103 ( .A0(in2[1]), .A1(n140), .B0(n139), .Y(res[1]) );
OAI21XLTS U104 ( .A0(in2[2]), .A1(n142), .B0(n141), .Y(res[2]) );
INVX4TS U105 ( .A(n39), .Y(n76) );
OAI21XLTS U106 ( .A0(in2[3]), .A1(n144), .B0(n143), .Y(res[3]) );
OR2X1TS U107 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
AND2X2TS U108 ( .A(in2[4]), .B(add_sub), .Y(n33) );
NAND2X2TS U109 ( .A(n124), .B(n123), .Y(n126) );
NAND2X4TS U110 ( .A(n76), .B(n79), .Y(n81) );
NAND2X2TS U111 ( .A(n79), .B(n78), .Y(n77) );
XOR2X2TS U112 ( .A(n90), .B(in2[5]), .Y(n138) );
OR2X8TS U113 ( .A(n135), .B(in1[8]), .Y(n67) );
NOR2X2TS U114 ( .A(n98), .B(n78), .Y(n92) );
NAND3X6TS U115 ( .A(n81), .B(n80), .C(n77), .Y(n145) );
NOR2X6TS U116 ( .A(n145), .B(n82), .Y(n36) );
BUFX8TS U117 ( .A(n89), .Y(n39) );
NAND2X8TS U118 ( .A(n84), .B(n85), .Y(n89) );
NAND2X4TS U119 ( .A(n33), .B(n39), .Y(n80) );
NAND2BX4TS U120 ( .AN(in2[11]), .B(n102), .Y(n106) );
NAND2BX2TS U121 ( .AN(n60), .B(n64), .Y(n43) );
NAND2BX2TS U122 ( .AN(n60), .B(n64), .Y(n46) );
NAND2X2TS U123 ( .A(n136), .B(in1[7]), .Y(n49) );
NAND2X2TS U124 ( .A(n96), .B(add_sub), .Y(n97) );
NAND2X1TS U125 ( .A(n56), .B(n63), .Y(n55) );
INVX2TS U126 ( .A(in1[12]), .Y(n73) );
INVX2TS U127 ( .A(n71), .Y(n48) );
OAI21X2TS U128 ( .A0(in1[5]), .A1(n36), .B0(n138), .Y(n34) );
INVX2TS U129 ( .A(in1[4]), .Y(n82) );
NAND2X1TS U130 ( .A(in2[0]), .B(n56), .Y(n140) );
OAI21X1TS U131 ( .A0(in2[1]), .A1(in2[0]), .B0(n56), .Y(n142) );
OAI31X1TS U132 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(add_sub), .Y(
n144) );
XNOR2X1TS U133 ( .A(n35), .B(n138), .Y(res[5]) );
XNOR2X1TS U134 ( .A(n36), .B(in1[5]), .Y(n35) );
XNOR2X1TS U135 ( .A(n65), .B(n136), .Y(res[7]) );
XNOR2X1TS U136 ( .A(n137), .B(in1[7]), .Y(n65) );
XNOR2X1TS U137 ( .A(n135), .B(in1[8]), .Y(n70) );
XOR2XLTS U138 ( .A(n66), .B(n105), .Y(res[10]) );
XOR2X1TS U139 ( .A(n116), .B(n74), .Y(res[12]) );
XOR2X1TS U140 ( .A(n117), .B(in1[12]), .Y(n74) );
NAND2X1TS U141 ( .A(n62), .B(n60), .Y(n116) );
XNOR2X1TS U142 ( .A(n129), .B(n128), .Y(res[13]) );
OA21X4TS U143 ( .A0(n62), .A1(n44), .B0(n42), .Y(n32) );
NAND2X2TS U144 ( .A(n115), .B(in1[13]), .Y(n127) );
INVX2TS U145 ( .A(in2[4]), .Y(n79) );
INVX2TS U146 ( .A(n109), .Y(n119) );
INVX2TS U147 ( .A(n78), .Y(n56) );
OAI21X2TS U148 ( .A0(n105), .A1(in1[10]), .B0(n104), .Y(n40) );
OAI2BB1X4TS U149 ( .A0N(n36), .A1N(in1[5]), .B0(n34), .Y(n93) );
INVX2TS U150 ( .A(n134), .Y(n37) );
OAI2BB1X4TS U151 ( .A0N(n105), .A1N(in1[10]), .B0(n40), .Y(n130) );
NOR2X8TS U152 ( .A(n89), .B(in2[4]), .Y(n41) );
INVX2TS U153 ( .A(n64), .Y(n44) );
OAI21X4TS U154 ( .A0(n62), .A1(n44), .B0(n45), .Y(n128) );
NAND2X8TS U155 ( .A(n50), .B(n49), .Y(n135) );
NAND2X8TS U156 ( .A(n130), .B(n57), .Y(n62) );
AND2X8TS U157 ( .A(n128), .B(n86), .Y(n83) );
NOR2X8TS U158 ( .A(n83), .B(n32), .Y(n125) );
XNOR2X1TS U159 ( .A(n130), .B(n59), .Y(res[11]) );
XOR2X1TS U160 ( .A(n131), .B(n61), .Y(n59) );
MXI2X4TS U161 ( .A(n122), .B(n123), .S0(n125), .Y(n120) );
MXI2X2TS U162 ( .A(n118), .B(n109), .S0(n120), .Y(res[16]) );
XOR2X1TS U163 ( .A(n104), .B(in1[10]), .Y(n66) );
XNOR2X1TS U164 ( .A(n70), .B(n134), .Y(res[8]) );
XNOR2X1TS U165 ( .A(n120), .B(n121), .Y(res[15]) );
NOR2X8TS U166 ( .A(in2[3]), .B(in2[2]), .Y(n84) );
NOR2X8TS U167 ( .A(in2[1]), .B(in2[0]), .Y(n85) );
AFHCINX4TS U168 ( .CIN(n132), .B(n133), .A(in1[9]), .S(res[9]), .CO(n105) );
NOR2X8TS U169 ( .A(n91), .B(in2[6]), .Y(n95) );
XOR2X4TS U170 ( .A(n114), .B(in2[13]), .Y(n115) );
NAND2X2TS U171 ( .A(n106), .B(add_sub), .Y(n101) );
XOR2X1TS U172 ( .A(n92), .B(in2[9]), .Y(n133) );
ADDFHX4TS U173 ( .A(n94), .B(in1[6]), .CI(n93), .CO(n137), .S(res[6]) );
XNOR2X1TS U174 ( .A(n97), .B(in2[8]), .Y(n134) );
AOI21X1TS U175 ( .A0(in2[1]), .A1(n140), .B0(in1[1]), .Y(n139) );
AOI21X1TS U176 ( .A0(in2[2]), .A1(n142), .B0(in1[2]), .Y(n141) );
AOI21X1TS U177 ( .A0(in2[3]), .A1(n144), .B0(in1[3]), .Y(n143) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL5_syn.sdf");
endmodule
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: WB_Serial.v
// Description: Wishbone Compatible RS232 core.
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module WB_Serial(
input wb_clk_i, // Clock Input
input wb_rst_i, // Reset Input
input [15:0] wb_dat_i, // Command to send to mouse
output [15:0] wb_dat_o, // Received data
input wb_cyc_i, // Cycle
input wb_stb_i, // Strobe
input [ 1:0] wb_adr_i, // Wishbone address lines
input [ 1:0] wb_sel_i, // Wishbone Select lines
input wb_we_i, // Write enable
output reg wb_ack_o, // Normal bus termination
output wb_tgc_o, // Interrupt request
output rs232_tx, // RS232 output
input rs232_rx // RS232 input
);
// --------------------------------------------------------------------
// This section is a simple WB interface
// --------------------------------------------------------------------
reg [7:0] dat_o;
wire [7:0] dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 8 to 16 bit WB
assign wb_dat_o = wb_sel_i[0] ? {8'h00, dat_o} : {dat_o, 8'h00}; // 8 to 16 bit WB
wire [2:0] UART_Addr = {wb_adr_i, wb_sel_i[1]}; // Computer UART Address
wire wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
wire wr_command = wb_ack_i & wb_we_i; // WISHBONE write access, Singal to send
wire rd_command = wb_ack_i & ~wb_we_i; // WISHBONE write access, Singal to send
assign wb_tgc_o = ~IPEN; // If ==0 - new data has been received
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// This section is a simple 8250 Emulator that front ends the UART
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define UART_RG_TR 3'h0 // RW - Transmit / Receive register
`define UART_RG_IE 3'h1 // RW - Interrupt enable
`define UART_RG_II 3'h2 // R - Interrupt identification (no fifo on 8250)
`define UART_RG_LC 3'h3 // RW - Line Control
`define UART_RG_MC 3'h4 // W - Modem control
`define UART_RG_LS 3'h5 // R - Line status
`define UART_RG_MS 3'h6 // R - Modem status
`define UART_RG_SR 3'h7 // RW - Scratch register
`define UART_DL_LSB 8'h60 // Divisor latch least significant byte, hard coded to 9600 baud
`define UART_DL_MSB 8'h00 // Divisor latch most significant byte
`define UART_IE_DEF 8'h00 // Interupt Enable default
`define UART_LC_DEF 8'h03 // Line Control default
`define UART_MC_DEF 8'h00 // Line Control default
// --------------------------------------------------------------------
// Wires for Interrupt Enable Register (IER)
// --------------------------------------------------------------------
wire EDAI = ier[0]; // Enable Data Available Interrupt
wire ETXH = ier[1]; // Enable Tx Holding Register Empty Interrupt
wire ERLS = ier[2]; // Enable Receive Line Status Interrupt
wire EMSI = ier[3]; // Enable Modem Status Interrupt
wire [7:0] INTE = {4'b0000, ier};
// --------------------------------------------------------------------
// Wires for Interrupt Identification Register (IIR)
// --------------------------------------------------------------------
reg IPEN; // 0 if intereupt pending
reg IPEND; // Interupt pending
reg [1:0] INTID; // Interrupt ID Bits
wire [7:0] ISTAT = { 5'b0000_0,INTID,IPEN};
// --------------------------------------------------------------------
// UART Interrupt Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
IPEN <= 1'b1; // Interupt Enable default
IPEND <= 1'b0; // Interupt pending
INTID <= 2'b00; // Interupt ID
end
else begin
if(DR & EDAI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b10; // Set Interupt ID
end
if(THRE & ETXH) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b01; // Set Interupt ID
end
if((CTS | DSR | RI |RLSD) && EMSI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b00; // Interupt ID
end
if(rd_command) // If a read was requested
case(UART_Addr) // Determine which register was read
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_II: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_MS: IPEN <= 1'b1; // Resets interupt flag
default: ; // Do nothing if anything else
endcase // End of case
if(wr_command) // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag;
default: ; // Do nothing if anything else
endcase // End of case
if(IPEN & IPEND) begin
INTID <= 2'b00; // user has cleared the Interupt
IPEND <= 1'b0; // Interupt pending
end
end
end // Synchrounous always
// --------------------------------------------------------------------
// Wires for Line Status Register (LSR)
// --------------------------------------------------------------------
wire TSRE = tx_done; // Tx Shift Register Empty
wire PE = 1'b0; // Parity Error
wire BI = 1'b0; // Break Interrupt, hard coded off
wire FE = to_error; // Framing Error, hard coded off
wire OR = rx_over; // Overrun Error, hard coded off
reg rx_rden; // Receive data enable
reg DR; // Data Ready
reg THRE; // Transmitter Holding Register Empty
wire [7:0] LSTAT = {1'b0,TSRE,THRE,BI,FE,PE,OR,DR};
// --------------------------------------------------------------------
// UART Line Status Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
rx_read <= 1'b0; // Singal to get the data out of the buffer
rx_rden <= 1'b1; // Singal to get the data out of the buffer
DR <= 1'b0; // Indicates data is waiting to be read
THRE <= 1'b0; // Transmitter holding register is empty
end
else begin
if(rx_drdy) begin // If enabled
DR <= 1'b1; // Indicates data is waiting to be read
if(rx_rden) rx_read <= 1'b1; // If reading enabled, request another byte
else begin // of data out of the buffer, else..
rx_read <= 1'b0; // on next clock, do not request anymore
rx_rden <= 1'b0; // block your fifo from reading
end // until ready
end
if(tx_done) begin // If enabled
THRE <= 1'b1; // Transmitter holding register is empty
end
if(IPEN && IPEND) begin // If the user has cleared the and there is not one pending
rx_rden <= 1'b1; // User has digested that byte, now enable reading some more
DR <= 1'b0; // interrupt, then clear
THRE <= 1'b0; // the flags in the Line status register
end
end
end
// --------------------------------------------------------------------
// Wires for Modem Control Register (MCR)
// --------------------------------------------------------------------
wire DTR = mcr[0];
wire RTS = mcr[1];
wire OUT1 = mcr[2];
wire OUT2 = mcr[3];
wire LOOP = mcr[4];
wire [7:0] MCON = {3'b000, mcr[4:0]};
// --------------------------------------------------------------------
// Wires for Modem Status Register (MSR)
// --------------------------------------------------------------------
wire RLSD = LOOP ? OUT2 : 1'b0; // Received Line Signal Detect
wire RI = LOOP ? OUT1 : 1'b1; // Ring Indicator
wire DSR = LOOP ? DTR : 1'b0; // Data Set Ready
wire CTS = LOOP ? RTS : 1'b0; // Clear To Send
wire DRLSD = 1'b0; // Delta Rx Line Signal Detect
wire TERI = 1'b0; // Trailing Edge Ring Indicator
wire DDSR = 1'b0; // Delta Data Set Ready
wire DCTS = 1'b0; // Delta Clear to Send
wire [7:0] MSTAT = {RLSD,RI,DSR,CTS,DCTS,DDSR,TERI,DRLSD};
// --------------------------------------------------------------------
// Wires for Line Control Register (LCRR)
// --------------------------------------------------------------------
wire [7:0] LCON = lcr; // Data Latch Address Bit
wire dlab = lcr[7]; // Data Latch Address Bit
// --------------------------------------------------------------------
// 8250A Registers
// --------------------------------------------------------------------
wire [7:0] output_data; // Wired to receiver
reg [7:0] input_data; // Transmit register
reg [3:0] ier; // Interrupt enable register
reg [7:0] lcr; // Line Control register
reg [7:0] mcr; // Modem Control register
reg [7:0] dll; // Data latch register low
reg [7:0] dlh; // Data latch register high
// --------------------------------------------------------------------
// UART Register behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dat_o <= 8'h00; // Default value
end
else
if(rd_command) begin
case(UART_Addr) // Determine which register was read
`UART_RG_TR: dat_o <= dlab ? dll : output_data;
`UART_RG_IE: dat_o <= dlab ? dlh : INTE;
`UART_RG_II: dat_o <= ISTAT; // Interupt ID
`UART_RG_LC: dat_o <= LCON; // Line control
`UART_RG_MC: dat_o <= MCON ; // Modem Control Register
`UART_RG_LS: dat_o <= LSTAT; // Line status
`UART_RG_MS: dat_o <= MSTAT; // Modem Status
`UART_RG_SR: dat_o <= 8'h00; // No Scratch register
default: dat_o <= 8'h00; // Default
endcase // End of case
end
end // Synchrounous always
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dll <= `UART_DL_LSB; // Set default to 9600 baud
dlh <= `UART_DL_MSB; // Set default to 9600 baud
ier <= 4'h01; // Interupt Enable default
lcr <= 8'h03; // Default value
mcr <= 8'h00; // Default value
end
else if(wr_command) begin // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: if(dlab) dll <= dat_i; else input_data <= dat_i;
`UART_RG_IE: if(dlab) dlh <= dat_i; else ier <= dat_i[3:0];
`UART_RG_II: ; // Read only register
`UART_RG_LC: lcr <= dat_i; // Line Control
`UART_RG_MC: mcr <= dat_i; // Modem Control Register
`UART_RG_LS: ; // Read only register
`UART_RG_MS: ; // Read only register
`UART_RG_SR: ; // No scratch register
default: ; // Default
endcase // End of case
end
end // Synchrounous always
// --------------------------------------------------------------------
// Transmit behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) tx_send <= 1'b0; // Default value
else tx_send <= (wr_command && (UART_Addr == `UART_RG_TR) && !dlab);
end // Synchrounous always
// --------------------------------------------------------------------
// Instantiate the UART
// --------------------------------------------------------------------
reg rx_read; // Signal to read next byte in the buffer
wire rx_drdy; // Indicates new data has come in
wire rx_idle; // Indicates Receiver is idle
wire rx_over; // Indicates buffer over run error
reg tx_send; // Signal to send data
wire to_error; // Indicates a transmit error occured
wire tx_done = ~tx_busy; // Signal command finished sending
wire tx_busy; // Signal transmitter is busy
async_receiver RX(.clk(wb_clk_i), .Baud8Tick(Baud8Tick), .RxD(rs232_rx), .RxD_data_ready(rx_drdy), .RxD_data(output_data), .RxD_idle(rx_idle) );
async_transmitter TX(.clk(wb_clk_i), .Baud1Tick(Baud1Tick), .TxD(rs232_tx), .TxD_start(tx_send), .TxD_data(input_data), .TxD_busy(tx_busy));
// --------------------------------------------------------------------
// Baud Clock Generator
// --------------------------------------------------------------------
wire [18:0] Baudiv = {3'b000,dlh,dll};
wire Baud1Tick = BaudAcc1[18];
wire Baud8Tick = BaudAcc8[15];
reg [18:0] BaudAcc1;
reg [15:0] BaudAcc8;
wire [18:0] BaudInc = 19'd2416/Baudiv;
always @(posedge wb_clk_i) BaudAcc1 <= BaudAcc1[17:0] + BaudInc;
always @(posedge wb_clk_i) BaudAcc8 <= BaudAcc8[14:0] + BaudInc;
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// 1.8432Mhz Baud Clock Generator:
// This module generates the standard 1.8432Mhz Baud Clock. Using this clock
// The Baud Rate Generator below can then derive all the standard
// Bauds. Make the accumulator 1 more bit for carry out than what is
// Needed. Example: Main Clock = 12.5Mhz = 12,500,000 Hence
// 1024/151 = 6.78, => 12,500,000 / 6.78 = 1,843,261.72 , .003% error, Good !
// so the accumulator should be 11 bits (log2(1024) +1
//
// --------------------------------------------------------------------
// Baud Rate Generator:
// Once we have our little 1.8432Mhz Baud Clock, deriving the bauds is
// simple simon. Just divide by 16 to get the 1x baud for transmitting
// and divide by 2 to get the 8x oversampling clock for receiving.
//
// Baud Clock = 1.8432Mhz
// Divisor = 16
//
// Baud Divsr %Error
// ------ ----- -----
// 50 2304 0.000%
// 75 1536 0.000%
// 110 1047 0.026%
// 150 768 0.000%
// 300 384 0.000%
// 600 192 0.000%
// 1200 96 0.000%
// 2400 48 0.000%
// 4800 24 0.000%
// 7200 16 0.000%
// 9600 12 0.000%
// 14400 8 0.000%
// 19200 6 0.000%
// 28800 4 0.000%
// 38400 3 0.000%
// 57600 2 0.000%
// 115200 1 0.000%
//
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// RS-232 RX module
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module async_receiver(clk, Baud8Tick, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk;
input RxD;
input Baud8Tick; // Desired baud rate
output [7:0] RxD_data;
output RxD_data_ready; // on clock pulse when RxD_data is valid
// We also detect if a gap occurs in the received stream of characters whuich can be useful if
// multiple characters are sent in burst so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
reg [1:0] RxD_sync_inv; // we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick) begin
if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg [3:0] state;
reg [3:0] bit_spacing;
// "next_bit" controls when the data sampling occurs depending on how noisy the RxD is, different
// values might work better with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always @(posedge clk)
if(state==0)bit_spacing <= 4'b0000;
else
if(Baud8Tick) bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv)state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// RS-232 TX module
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module async_transmitter(clk, Baud1Tick, TxD_start, TxD_data, TxD, TxD_busy);
input clk;
input TxD_start;
input Baud1Tick; // Desired baud rate
input [7:0] TxD_data;
output TxD;
output TxD_busy;
// Transmitter state machine
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
reg [3:0] state;
wire TxD_ready = (state==0);
wire TxD_busy = ~TxD_ready;
wire BaudTick = TxD_busy ? Baud1Tick : 1'b0;
reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
reg muxbit; // Output mux
always @( * )
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
reg TxD; // Put together the start, data and stop bits
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// End of WB Serial Modules
// --------------------------------------------------------------------
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_vc709.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the VC709 Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_vc709
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
//Interface: CQ Ultrascale (RXR)
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
//Interface: RC Ultrascale (RXC)
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
//Interface: CC Ultrascale (TXC)
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
//Interface: RQ Ultrascale (TXR)
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
input USER_CLK,
input USER_RESET,
output [3:0] CFG_INTERRUPT_INT,
output [1:0] CFG_INTERRUPT_PENDING,
input [1:0] CFG_INTERRUPT_MSI_ENABLE,
input CFG_INTERRUPT_MSI_MASK_UPDATE,
input [31:0] CFG_INTERRUPT_MSI_DATA,
output [3:0] CFG_INTERRUPT_MSI_SELECT,
output [31:0] CFG_INTERRUPT_MSI_INT,
output [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS,
input CFG_INTERRUPT_MSI_SENT,
input CFG_INTERRUPT_MSI_FAIL,
output [2:0] CFG_INTERRUPT_MSI_ATTR,
output CFG_INTERRUPT_MSI_TPH_PRESENT,
output [1:0] CFG_INTERRUPT_MSI_TPH_TYPE,
output [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG,
output [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
input [7:0] CFG_FC_CPLH,
input [11:0] CFG_FC_CPLD,
output [2:0] CFG_FC_SEL,
input [3:0] CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH
input [2:0] CFG_CURRENT_SPEED, // CONFIG_LINK_RATE
input [2:0] CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD
input [2:0] CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST
input [7:0] CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE
input [1:0] CFG_RCB_STATUS,
output PCIE_CQ_NP_REQ,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN // Channel write data has been recieved
);
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "ULTRASCALE";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
wire clk;
wire rst_in;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Unconnected Wires (Used in classic interface)
wire wRxTlpReady_nc;
wire [C_PCI_DATA_WIDTH-1:0] wRxTlp_nc = 0;
wire wRxTlpEndFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset_nc = 0;
wire wRxTlpStartFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset_nc = 0;
wire wRxTlpValid_nc = 0;
wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode_nc = 0;
wire wTxTlpReady_nc = 0;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp_nc;
wire wTxTlpEndFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset_nc;
wire wTxTlpStartFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset_nc;
wire wTxTlpValid_nc;
//--------------------------------------------------------------------------
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
assign config_completer_id = 0; // Not used in ULTRASCALE implementation
assign config_bus_master_enable = CFG_FUNCTION_STATUS[2];
assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH
assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;
assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD
assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST
assign config_cpl_boundary_sel = CFG_RCB_STATUS[0];
assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0];
assign config_max_cpl_data = CFG_FC_CPLD;
assign config_max_cpl_hdr = CFG_FC_CPLH;
assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below
assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_INT = 0;
assign CFG_INTERRUPT_PENDING = 0;
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_ATTR = 0;
assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0;
assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0;
assign CFG_INTERRUPT_MSI_TPH_TYPE = 0;
assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0;
assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL;
assign PCIE_CQ_NP_REQ = 1;
engine_layer
#(// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
// Unconnected Outputs
.TX_TLP (wTxTlp_nc),
.TX_TLP_VALID (wTxTlpValid_nc),
.TX_TLP_START_FLAG (wTxTlpStartFlag_nc),
.TX_TLP_START_OFFSET (wTxTlpStartOffset_nc),
.TX_TLP_END_FLAG (wTxTlpEndFlag_nc),
.TX_TLP_END_OFFSET (wTxTlpEndOffset_nc),
.RX_TLP_READY (wRxTlpReady_nc),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (wRxTlp_nc),
.RX_TLP_VALID (wRxTlpValid_nc),
.RX_TLP_START_FLAG (wRxTlpStartFlag_nc),
.RX_TLP_START_OFFSET (wRxTlpStartOffset_nc),
.RX_TLP_END_FLAG (wRxTlpEndFlag_nc),
.RX_TLP_END_OFFSET (wRxTlpEndOffset_nc),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode_nc),
.TX_TLP_READY (wTxTlpReady_nc),
/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY));
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../engine/" "../../riffa/")
// End:
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx.v
// Version : 1.3
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_3_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_7x_v1_3_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/*
* Verification test for increment/decrement operators
*
* Author: Prasad Joshi <[email protected]>
*/
module main;
logic la;
logic lb;
int ia;
int ib;
bit ba;
bit bb;
real ra;
real rb;
real rc;
initial begin
/* logic tests */
la = 0;
#1
lb = ++la;
#1
if (la != lb) begin
$display("FAILED");
$finish;
end
ib = 15;
#1
ia = ++ib;
#1
if (ia != ib) begin
$display("FAILED");
$finish;
end
ia = 15;
#1
ib = ia++;
#1
if (ia != 16 || ib != 15) begin
$display("FAILED");
$finish;
end
ib = --ia;
if (ib != ia) begin
$display("FAILED");
$finish;
end
/* bit test */
ba = 0;
#1
for (ia = 0; ia < 10; ia = ia + 1) begin
bb = --ba;
#1
if (bb != ba && !(bb == 1 || bb == 0)) begin
$display("FAILED");
$finish;
end
end
/* real decrement test */
ia = 15;
ra = --ia;
if (ra != ia) begin
$display("FAILED");
$finish;
end
rb = 19.99;
rc = rb - 2;
ra = --rb;
if (ra != rb) begin
$display("FAILED");
$finish;
end
ra = rb--;
if (ra == rb || rc != rb) begin
$display("FAILED");
$finish;
end
/* real increment test */
ia = 15;
ra = ++ia;
if (ra != ia) begin
$display("FAILED");
$finish;
end
rb = 19.99;
rc = rb + 2;
ra = ++rb;
if (ra != rb) begin
$display("FAILED");
$finish;
end
ra = rb++;
if (ra == rb || rc != rb) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
//rsf `include "timescale.v"
// synopsys translate_on
//rsf `include "i2c_master_defines.v"
// I2C registers wishbone addresses
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module i2c_master_byte_ctrl (
clk, rst, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk)
if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk)
if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk)
if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_16_32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_16_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output [15:0] q;
wire sub_wire0;
wire [15:0] sub_wire1;
wire empty = sub_wire0;
wire [15:0] q = sub_wire1[15:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_16_32_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`include "../src/include/asym_ram.v"
`include "../src/include/line_reader.v"
`include "../src/include/scale_1d.v"
`include "../src/mm2s_adv.v"
`timescale 1ns / 1ps
module test();
localparam integer C_PIXEL_WIDTH = 8;
localparam integer C_PIXEL_STORE_WIDTH = 8;
localparam integer C_IMG_STRIDE_SIZE = 1024;
localparam integer C_IMG_WBITS = 12;
localparam integer C_IMG_HBITS = 12;
localparam integer C_M_AXI_BURST_LEN = 4;
localparam integer C_M_AXI_ADDR_WIDTH = 32;
localparam integer C_M_AXI_DATA_WIDTH = 32;
reg clk;
reg resetn;
reg soft_resetn;
/// mm to fifo
reg [C_IMG_WBITS-1:0] img_width;
reg [C_IMG_HBITS-1:0] img_height;
reg [C_IMG_WBITS-1:0] win_left;
reg [C_IMG_WBITS-1:0] win_width;
reg [C_IMG_HBITS-1:0] win_top;
reg [C_IMG_HBITS-1:0] win_height;
reg [C_IMG_WBITS-1:0] dst_width;
reg [C_IMG_HBITS-1:0] dst_height;
reg fsync;
wire sof;
wire [C_M_AXI_ADDR_WIDTH-1:0] frame_addr;
// Ports of Axi Master Bus Interface M_AXI
wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr;
wire [7 : 0] m_axi_arlen;
wire [2 : 0] m_axi_arsize;
wire [1 : 0] m_axi_arburst;
wire m_axi_arlock;
wire [3 : 0] m_axi_arcache;
wire [2 : 0] m_axi_arprot;
wire [3 : 0] m_axi_arqos;
wire m_axi_arvalid;
wire m_axi_arready;
reg [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata;
reg [1 : 0] m_axi_rresp;
wire m_axi_rlast;
reg m_axi_rvalid;
wire m_axi_rready;
wire m_axis_tvalid;
wire [C_PIXEL_WIDTH-1:0] m_axis_tdata;
wire m_axis_tuser;
wire m_axis_tlast;
reg m_axis_tready;
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
mm2s_adv #(
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_PIXEL_STORE_WIDTH(C_PIXEL_STORE_WIDTH),
.C_IMG_STRIDE_SIZE(C_IMG_STRIDE_SIZE),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) uut (
.clk(clk),
.resetn(resetn),
.soft_resetn(soft_resetn),
.img_width(img_width),
.img_height(img_height),
.win_left(win_left),
.win_width(win_width),
.win_top(win_top),
.win_height(win_height),
.dst_width(dst_width),
.dst_height(dst_height),
.fsync(fsync),
.sof(sof),
.frame_addr(frame_addr),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tdata(m_axis_tdata),
.m_axis_tuser(m_axis_tuser),
.m_axis_tlast(m_axis_tlast),
.m_axis_tready(m_axis_tready)
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg running;
initial begin
running <= 0;
repeat (20) #2 running <= 0;
repeat (1) #2 running <= 1;
forever #2 running <= 0;
end
assign frame_addr = 32'h3FF80000;
assign m_axi_arready = 1;
////////////////////////////////// file ////////////////////////////////////////
integer fileR, picType, dataPosition, grayDepth;
reg[80*8:0] outputFileName;
reg[11:0] outputFileIdx = 0;
integer fileW = 0;
initial begin
fileR=$fopen("a.pgm", "r");
$fscanf(fileR, "P%d\n%d %d\n%d\n", picType, img_width, img_height, grayDepth);
dataPosition=$ftell(fileR);
$display("header: %dx%d, %d", img_width, img_height, grayDepth);
win_left <= img_width/4 + 1;
win_width <= img_width/2;
win_top <= img_height/4 + 1;
win_height <= img_height/2;
dst_width <= img_width /4;
dst_height <= img_height /4;
end
////////////////////////////////////////////////////////////////////////////////
reg [C_M_AXI_ADDR_WIDTH-1:0] img_offset;
reg[7 : 0] burstIdx;
reg[C_M_AXI_ADDR_WIDTH-1:0] burstAddr;
always @(posedge clk) begin: readfile
integer i;
if (resetn == 0) begin
burstIdx = 0;
burstAddr = 0;
m_axi_rdata = 0;
end
else if (m_axi_arvalid && m_axi_arready) begin
burstIdx = m_axi_arlen;
burstAddr = m_axi_araddr;
img_offset = (burstAddr - frame_addr) / C_IMG_STRIDE_SIZE * img_width + (burstAddr - frame_addr) % C_IMG_STRIDE_SIZE;
$fseek(fileR, dataPosition + img_offset, 0);
for (i = 0; i < C_M_AXI_DATA_WIDTH; i = i+8) begin
m_axi_rdata[i+7 -: 8] = $fgetc(fileR);
end
end
else if (m_axi_rready && m_axi_rvalid && ~m_axi_rlast) begin
burstIdx = burstIdx - 1;
burstAddr = burstAddr + (C_M_AXI_DATA_WIDTH / 8);
img_offset = (burstAddr - frame_addr) / C_IMG_STRIDE_SIZE * img_width + (burstAddr - frame_addr) % C_IMG_STRIDE_SIZE;
$fseek(fileR, dataPosition + img_offset, 0);
for (i = 0; i < C_M_AXI_DATA_WIDTH; i = i+8) begin
m_axi_rdata[i+7 -: 8] = $fgetc(fileR);
end
end
end
assign m_axi_rlast = (burstIdx == 0);
reg readingmm;
always @(posedge clk) begin
if (resetn == 0) begin
readingmm <= 0;
end
else if (m_axi_arvalid && m_axi_arready) begin
readingmm <= 1;
end
else if (m_axi_rready && m_axi_rvalid && m_axi_rlast) begin
readingmm <= 0;
end
end
always @(posedge clk) begin
if (resetn == 0) begin
m_axi_rvalid <= 0;
end
else if (m_axi_rready && m_axi_rvalid && m_axi_rlast) begin
m_axi_rvalid <= 0;
end
else if (readingmm) begin
if (~m_axi_rvalid || m_axi_rready) begin
m_axi_rvalid <= (RANDOMINPUT ? {$random}%2 : 1);
end
end
end
//////////////////////////////////////////// output ////////////////////////////
always @(posedge clk) begin
if (resetn == 0) begin
m_axis_tready <= 0;
end
else if (~m_axis_tready || m_axis_tvalid)
m_axis_tready <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
reg [C_IMG_WBITS-1:0] m_axis_width;
reg [C_IMG_HBITS-1:0] m_axis_height;
reg [C_IMG_WBITS-1:0] m_axis_col;
reg [C_IMG_HBITS-1:0] m_axis_row;
reg [C_M_AXI_ADDR_WIDTH-1:0] outputFileIdx;
reg[80*8:0] outputFileName;
integer fileW = 0;
always @ (posedge clk) begin
if (resetn == 0) begin
m_axis_width <= 0;
m_axis_height <= 0;
outputFileIdx <= 0;
end
else if (fsync) begin
m_axis_width <= dst_width;
m_axis_height <= dst_height;
m_axis_col <= 1;
m_axis_row <= 1;
outputFileIdx <= outputFileIdx + 1;
$sformat(outputFileName, "output%0d.pgm", outputFileIdx);
fileW=$fopen(outputFileName, "w");
$display("outputFileName: %s - %0d", outputFileName, fileW);
$fwrite(fileW, "P%0d\n%0d %0d\n%0d\n", picType, dst_width, dst_height, grayDepth);
end
else if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_col > m_axis_width || m_axis_row > m_axis_height) begin
$error("too big frame!\n");
end
if (m_axis_tuser) begin
if (m_axis_col != 1 || m_axis_row != 1) begin
$error("start frame col/row index error!\n");
end
else begin
$write("start frame\n");
end
end
$write("%0d ", m_axis_tdata);
if (m_axis_tlast) begin
if (m_axis_col != m_axis_width) begin
$error("\nline end error!\n");
end
else begin
$write("\n");
end
end
$fwrite(fileW, "%c", m_axis_tdata);
if (m_axis_col == m_axis_width && m_axis_row == m_axis_height) begin
$fclose(fileW);
end
if (m_axis_tlast) begin
m_axis_row <= m_axis_row + 1;
m_axis_col <= 1;
end
else begin
m_axis_col <= m_axis_col + 1;
end
end
end
reg end_of_frame;
always @(posedge clk) begin
if (resetn == 0)
end_of_frame <= 0;
else if (end_of_frame)
end_of_frame <= 0;
else if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_col == m_axis_width && m_axis_row == m_axis_height)
end_of_frame <= 1;
end
end
reg framing;
always @(posedge clk) begin
if (resetn == 0)
framing <= 0;
else if (fsync)
framing <= 1;
else if (end_of_frame)
framing <= 0;
end
always @(posedge clk) begin
if (resetn == 0) begin
fsync <= 0;
soft_resetn <= 0;
end
else if (fsync) begin
fsync <= 0;
soft_resetn <= 0;
end
else if (~framing) begin
fsync <= 1;
soft_resetn <= 1;
win_left <= win_left + 1;
win_width <= win_width - 1;
win_top <= win_top + 1;
win_height <= win_height - 1;
dst_width <= dst_width + 1;
dst_height <= dst_height + 1;
end
end
endmodule
|
module jjkflipfloptb;
wire q, qbar;
reg clk,rst;
reg [1:0] jk;
jjkflipflop jjkff(q,qbar,clk,rst,jk);
always #5 clk = ~clk;
initial
begin
clk = 1'b0;
rst = 1; # 10; rst = 0; #10;
$display("RSLT\tj\tk\tq\tqbar");
jk = 0; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
jk = 1; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
jk = 2; # 10; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
jk = 3; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
jk = 3; # 11; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
jk = 3; # 16; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",jk[1],jk[0],q,qbar);
#100;
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter nRD_EN2CNFG_WR = 6,
parameter nWR_EN2CNFG_RD = 4,
parameter nWR_EN2CNFG_WR = 4,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, dfi_wrdata_en, wr_data_en,
wr_data_addr, dfi_rddata_en, inhbt_wr_config, inhbt_rd_config,
rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en,
// Inputs
clk, rst, sent_col, col_size, io_config, col_wr_data_buf_addr,
dfi_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if (DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(/*AS*/col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(/*AS*/col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
generate
if ((nPHY_WRLAT == 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
input [RANK_WIDTH:0] io_config;
reg sent_col_r1;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
wire wrdata_en = (nPHY_WRLAT == 0)
? ((sent_col || |offset_r) && io_config[RANK_WIDTH])
: ((sent_col_r1 || |offset_r1) && io_config[RANK_WIDTH]);
output wire [DQS_WIDTH-1:0] dfi_wrdata_en;
assign dfi_wrdata_en = {DQS_WIDTH{wrdata_en}};
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && io_config[RANK_WIDTH])
: ((sent_col || |offset_r) && io_config[RANK_WIDTH]);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to dfi_rddata_en
wire read_data_valid = (sent_col || |offset_r) && ~io_config[RANK_WIDTH];
output wire [DQS_WIDTH-1:0] dfi_rddata_en;
assign dfi_rddata_en = {DQS_WIDTH{read_data_valid}};
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam nRD_EN2CNFG_WR_LOCAL = nRD_EN2CNFG_WR - 2;
localparam nWR_EN2CNFG_WR_LOCAL = nWR_EN2CNFG_WR - 2;
localparam WR_WAIT_CNT_WIDTH = clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_r;
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_ns;
always @(/*AS*/cnfg_wr_wait_r or read_data_valid or rst or wrdata_en) begin
if (rst) cnfg_wr_wait_ns = {WR_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_wr_wait_ns = cnfg_wr_wait_r;
if (wrdata_en)
cnfg_wr_wait_ns = nWR_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (read_data_valid)
cnfg_wr_wait_ns = nRD_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_wr_wait_r)
cnfg_wr_wait_ns = cnfg_wr_wait_r - ONE[WR_WAIT_CNT_WIDTH-1:0];
end // else: !if(rst)
end
always @(posedge clk) cnfg_wr_wait_r <= #TCQ cnfg_wr_wait_ns;
localparam nWR_EN2CNFG_RD_LOCAL = nWR_EN2CNFG_RD - 2;
localparam RD_WAIT_CNT_WIDTH = clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_r;
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_ns;
always @(/*AS*/cnfg_rd_wait_r or rst or wrdata_en) begin
if (rst) cnfg_rd_wait_ns = {RD_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_rd_wait_ns = cnfg_rd_wait_r;
if (wrdata_en)
cnfg_rd_wait_ns = nWR_EN2CNFG_RD_LOCAL[RD_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_rd_wait_r)
cnfg_rd_wait_ns = cnfg_rd_wait_r - ONE[RD_WAIT_CNT_WIDTH-1:0];
end
end
always @(posedge clk) cnfg_rd_wait_r <= #TCQ cnfg_rd_wait_ns;
// Finally, generate the inhbit signals. Do it in a way to help timing.
wire inhbt_wr_config_ns = (cnfg_wr_wait_ns != {WR_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_wr_config_r;
always @(posedge clk) inhbt_wr_config_r <= #TCQ inhbt_wr_config_ns;
output wire inhbt_wr_config;
assign inhbt_wr_config = sent_col || wrdata_en || inhbt_wr_config_r;
wire inhbt_rd_config_ns = (cnfg_rd_wait_ns != {RD_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_rd_config_r;
always @(posedge clk) inhbt_rd_config_r <= #TCQ inhbt_rd_config_ns;
output wire inhbt_rd_config;
assign inhbt_rd_config = sent_col || wrdata_en || inhbt_rd_config_r;
// Implement FIFO that records reads as they are sent to the DRAM.
// When dfi_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input dfi_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
wire [11:0] col_a_full = {col_a[13], col_a[11], col_a[9:0]};
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
reg [RAM_WIDTH-1:0] fifo_in_data_r;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
always @(posedge clk) fifo_in_data_r <= #TCQ fifo_in_data;
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
reg [4:0] head_r1;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
always @(posedge clk) head_r1 <= #TCQ head_r;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : dfi_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data_r[((i*6)+4)+:2]),
.DIB(fifo_in_data_r[((i*6)+2)+:2]),
.DIC(fifo_in_data_r[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r1),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/dfi_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = dfi_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = dfi_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = dfi_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = dfi_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:17 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module crc_gen (
input Reset,
input Clk,
input Init,
input [7:0] Frame_data,
input Data_en,
input CRC_rd,
output [31:0] CRC_out,
output reg CRC_end
);
reg [31:0] CRC_reg;
reg [3:0] Counter;
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
always @ ( negedge Clk )
if (Reset)
CRC_reg <= 32'hffffffff;
else
CRC_reg <= Init ? 32'hffffffff : Data_en ? NextCRC(Frame_data, CRC_reg ) : CRC_reg;
assign CRC_out = ~{ CRC_reg[24],CRC_reg[25],CRC_reg[26],CRC_reg[27],CRC_reg[28],CRC_reg[29],CRC_reg[30],CRC_reg[31], CRC_reg[16],CRC_reg[17],CRC_reg[18],CRC_reg[19],CRC_reg[20],CRC_reg[21],CRC_reg[22],CRC_reg[23], CRC_reg[ 8],CRC_reg[ 9],CRC_reg[10],CRC_reg[11],CRC_reg[12],CRC_reg[13],CRC_reg[14],CRC_reg[15], CRC_reg[ 0],CRC_reg[ 1],CRC_reg[ 2],CRC_reg[ 3],CRC_reg[ 4],CRC_reg[ 5],CRC_reg[ 6],CRC_reg[ 7] };
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (int i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Check we can declare the same signal twice
loops = 0;
for (int i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (loops !== 17) $stop;
// Check type is correct
loops = 0;
for (byte unsigned i=5; i>4; i=i+1) begin
loops = loops + 1;
end
if (loops !== 251) $stop;
// Check large loops
loops = 0;
for (int i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_1_0_sim_netlist.v
// Design : system_buffer_register_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_buffer_register_1_0_buffer_register
(val_out,
val_in,
clk);
output [31:0]val_out;
input [31:0]val_in;
input clk;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
FDRE \val_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(val_in[0]),
.Q(val_out[0]),
.R(1'b0));
FDRE \val_out_reg[10]
(.C(clk),
.CE(1'b1),
.D(val_in[10]),
.Q(val_out[10]),
.R(1'b0));
FDRE \val_out_reg[11]
(.C(clk),
.CE(1'b1),
.D(val_in[11]),
.Q(val_out[11]),
.R(1'b0));
FDRE \val_out_reg[12]
(.C(clk),
.CE(1'b1),
.D(val_in[12]),
.Q(val_out[12]),
.R(1'b0));
FDRE \val_out_reg[13]
(.C(clk),
.CE(1'b1),
.D(val_in[13]),
.Q(val_out[13]),
.R(1'b0));
FDRE \val_out_reg[14]
(.C(clk),
.CE(1'b1),
.D(val_in[14]),
.Q(val_out[14]),
.R(1'b0));
FDRE \val_out_reg[15]
(.C(clk),
.CE(1'b1),
.D(val_in[15]),
.Q(val_out[15]),
.R(1'b0));
FDRE \val_out_reg[16]
(.C(clk),
.CE(1'b1),
.D(val_in[16]),
.Q(val_out[16]),
.R(1'b0));
FDRE \val_out_reg[17]
(.C(clk),
.CE(1'b1),
.D(val_in[17]),
.Q(val_out[17]),
.R(1'b0));
FDRE \val_out_reg[18]
(.C(clk),
.CE(1'b1),
.D(val_in[18]),
.Q(val_out[18]),
.R(1'b0));
FDRE \val_out_reg[19]
(.C(clk),
.CE(1'b1),
.D(val_in[19]),
.Q(val_out[19]),
.R(1'b0));
FDRE \val_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(val_in[1]),
.Q(val_out[1]),
.R(1'b0));
FDRE \val_out_reg[20]
(.C(clk),
.CE(1'b1),
.D(val_in[20]),
.Q(val_out[20]),
.R(1'b0));
FDRE \val_out_reg[21]
(.C(clk),
.CE(1'b1),
.D(val_in[21]),
.Q(val_out[21]),
.R(1'b0));
FDRE \val_out_reg[22]
(.C(clk),
.CE(1'b1),
.D(val_in[22]),
.Q(val_out[22]),
.R(1'b0));
FDRE \val_out_reg[23]
(.C(clk),
.CE(1'b1),
.D(val_in[23]),
.Q(val_out[23]),
.R(1'b0));
FDRE \val_out_reg[24]
(.C(clk),
.CE(1'b1),
.D(val_in[24]),
.Q(val_out[24]),
.R(1'b0));
FDRE \val_out_reg[25]
(.C(clk),
.CE(1'b1),
.D(val_in[25]),
.Q(val_out[25]),
.R(1'b0));
FDRE \val_out_reg[26]
(.C(clk),
.CE(1'b1),
.D(val_in[26]),
.Q(val_out[26]),
.R(1'b0));
FDRE \val_out_reg[27]
(.C(clk),
.CE(1'b1),
.D(val_in[27]),
.Q(val_out[27]),
.R(1'b0));
FDRE \val_out_reg[28]
(.C(clk),
.CE(1'b1),
.D(val_in[28]),
.Q(val_out[28]),
.R(1'b0));
FDRE \val_out_reg[29]
(.C(clk),
.CE(1'b1),
.D(val_in[29]),
.Q(val_out[29]),
.R(1'b0));
FDRE \val_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(val_in[2]),
.Q(val_out[2]),
.R(1'b0));
FDRE \val_out_reg[30]
(.C(clk),
.CE(1'b1),
.D(val_in[30]),
.Q(val_out[30]),
.R(1'b0));
FDRE \val_out_reg[31]
(.C(clk),
.CE(1'b1),
.D(val_in[31]),
.Q(val_out[31]),
.R(1'b0));
FDRE \val_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(val_in[3]),
.Q(val_out[3]),
.R(1'b0));
FDRE \val_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(val_in[4]),
.Q(val_out[4]),
.R(1'b0));
FDRE \val_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(val_in[5]),
.Q(val_out[5]),
.R(1'b0));
FDRE \val_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(val_in[6]),
.Q(val_out[6]),
.R(1'b0));
FDRE \val_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(val_in[7]),
.Q(val_out[7]),
.R(1'b0));
FDRE \val_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(val_in[8]),
.Q(val_out[8]),
.R(1'b0));
FDRE \val_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(val_in[9]),
.Q(val_out[9]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_buffer_register_1_0,buffer_register,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "buffer_register,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_buffer_register_1_0
(clk,
val_in,
val_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [31:0]val_in;
output [31:0]val_out;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
system_buffer_register_1_0_buffer_register U0
(.clk(clk),
.val_in(val_in),
.val_out(val_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`include "memory.v"
`include "register_file.v"
`include "sim.v"
`include "decoder.v"
`define ADDRESS_WIDTH 32
`define DATA_WIDTH 32
module decoder_test();
wire reset;
wire clk;
reg [`ADDRESS_WIDTH-1:0] mem_address = 0;
wire [`DATA_WIDTH-1:0] mem_data_out;
reg[31:0] decoder_inp;
reg[1:0] instr_size;
reg mem_cmd = `MEM_CMD_READ;
reg mem_valid;
wire mem_ready;
wire mem_res_valid;
integer tests;
initial begin
//$dumpfile("dump.vcd");
// $dumpvars;
tests = 0;
end
always @(posedge clk) begin
if (!reset && mem_ready) begin
mem_valid <= 1;
decoder_inp = mem_data_out;
end
if (!reset && mem_res_valid) begin
mem_valid <= 0;
// $display("Address = %h, data = %h, data 2 = %h", mem_address, mem_data_out, decoder_inp);
mem_address += (`DATA_WIDTH / 8);
//tests += 1;
//if (tests > 20)
// #20 $finish;
end
end
decoder my_decoder(
.i_clk(clk),
.i_reset(reset),
.i_ready(mem_valid),
.i_data(decoder_inp),
.o_instr_size(instr_size));
// Memory module
memory #(`ADDRESS_WIDTH, `DATA_WIDTH) my_mem(
.clk(clk),
.reset(reset),
.i_address(mem_address),
.i_res_ready(1'b1), //we are always ready to receive data
.i_cmd(mem_cmd), //R/W
.i_data(`DATA_WIDTH'bx),//no write data
.i_valid(mem_valid),
.o_data(mem_data_out),
.o_res_valid(mem_res_valid),
.o_ready(mem_ready)
);
// Simulator (clock + reset)
sim my_sim(
.clk(clk),
.reset(reset)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_buffered_fifo(clock, resetn,
data_in, valid_in, stall_out,
data_out, valid_out, stall_in);
parameter DATA_WIDTH = 32;
parameter DEPTH = 64;
parameter EXTRA_FIFO_SPACE = 32; //256;
parameter IMPLEMENTATION_MODE = "MLAB";
localparam REAL_DEPTH=DEPTH-EXTRA_FIFO_SPACE;
input clock, resetn;
input [DATA_WIDTH-1:0] data_in;
input valid_in;
output stall_out;
output [DATA_WIDTH-1:0] data_out;
output valid_out;
input stall_in;
wire fifo_almost_full;
generate
if (IMPLEMENTATION_MODE == "RAM")
begin
acl_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
else
begin
acl_mlab_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
endgenerate
assign stall_out = fifo_almost_full;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/);
parameter int sliceddn[7:0] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
parameter int slicedup[0:7] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
int alldn[7:0];
int allup[0:7];
int twodn[1:0];
int twoup[0:1];
initial begin
`checkh(sliceddn[7], 'h100);
alldn[7:0] = sliceddn[7:0];
`checkh(alldn[7], 'h100);
alldn[7:0] = sliceddn[0 +: 8]; // down: lsb/lo +: width
`checkh(alldn[7], 'h100);
alldn[7:0] = sliceddn[7 -: 8]; // down: msb/hi -: width
`checkh(alldn[7], 'h100);
twodn[1:0] = sliceddn[6:5];
`checkh(twodn[1], 'h101);
`checkh(twodn[0], 'h102);
twodn[1:0] = sliceddn[4 +: 2];
`checkh(twodn[1], 'h102);
`checkh(twodn[0], 'h103);
twodn[1:0] = sliceddn[4 -: 2];
`checkh(twodn[1], 'h103);
`checkh(twodn[0], 'h104);
`checkh(slicedup[7], 'h107);
allup[0:7] = slicedup[0:7];
`checkh(alldn[7], 'h100);
allup[0:7] = slicedup[0 +: 8]; // up: msb/lo +: width
`checkh(alldn[7], 'h100);
allup[0:7] = slicedup[7 -: 8]; // up: lsb/hi -: width
`checkh(alldn[7], 'h100);
twoup[0:1] = slicedup[5:6];
`checkh(twoup[1], 'h106);
`checkh(twoup[0], 'h105);
twoup[0:1] = slicedup[4 +: 2];
`checkh(twoup[1], 'h105);
`checkh(twoup[0], 'h104);
twoup[0:1] = slicedup[4 -: 2];
`checkh(twoup[1], 'h104);
`checkh(twoup[0], 'h103);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_input_if
#(parameter
CFG_LOCAL_DATA_WIDTH = 64,
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_MEM_IF_CHIP = 1,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL"
)
(
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early,
itf_rd_data_id_early_valid,
// command generator
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
cmd_id,
// write data path
wr_data_mem_full,
write_data_id,
write_data,
byte_en,
write_data_valid,
// read data path
read_data,
read_data_valid,
read_data_error,
read_data_localid,
read_data_begin,
read_data_last,
//side band
local_refresh_req,
local_refresh_chip,
local_zqcal_req,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
bg_do_read,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_localid,
rfsh_req,
rfsh_chip,
zqcal_req,
deep_powerdn_req,
deep_powerdn_chip,
self_rfsh_req,
self_rfsh_chip,
rfsh_ack,
deep_powerdn_ack,
power_down_ack,
self_rfsh_ack,
init_done
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
// command channel
output itf_cmd_ready;
input [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
// read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// command generator
input cmd_gen_full;
output cmd_valid;
output [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
output cmd_write;
output cmd_read;
output cmd_multicast;
output [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
output cmd_priority;
output cmd_autoprecharge;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
// write data path
output [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
output [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
output write_data_valid;
input wr_data_mem_full;
output [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
// read data path
input [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
input read_data_valid;
input read_data_error;
input [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
input read_data_begin;
input read_data_last;
//side band
input local_refresh_req;
input [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
input local_zqcal_req;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
//side band
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output zqcal_req;
output deep_powerdn_req;
output [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output self_rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
input rfsh_ack;
input deep_powerdn_ack;
input power_down_ack;
input self_rfsh_ack;
input init_done;
// command generator
wire cmd_priority;
wire [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
wire cmd_read;
wire cmd_write;
wire cmd_multicast;
wire cmd_gen_full;
wire cmd_valid;
wire itf_cmd_ready;
wire cmd_autoprecharge;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
//side band
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
wire zqcal_req;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
wire self_rfsh_req;
//wire rfsh_ack;
//wire deep_powerdn_ack;
wire power_down_ack;
//wire self_rfsh_ack;
// wire init_done;
//write data path
wire itf_wr_data_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire write_data_valid;
wire [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
wire [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
//read data path
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
// commmand generator
assign cmd_priority = itf_cmd_priority;
assign cmd_address = itf_cmd_address;
assign cmd_multicast = itf_cmd_multicast;
assign cmd_size = itf_cmd_burstlen;
assign cmd_autoprecharge = itf_cmd_autopercharge;
assign cmd_id = itf_cmd_id;
// side band
assign rfsh_req = local_refresh_req;
assign rfsh_chip = local_refresh_chip;
assign zqcal_req = local_zqcal_req;
assign deep_powerdn_req = local_deep_powerdn_req;
assign deep_powerdn_chip = local_deep_powerdn_chip;
assign self_rfsh_req = local_self_rfsh_req;
assign self_rfsh_chip = local_self_rfsh_chip;
assign local_refresh_ack = rfsh_ack;
assign local_deep_powerdn_ack = deep_powerdn_ack;
assign local_power_down_ack = power_down_ack;
assign local_self_rfsh_ack = self_rfsh_ack;
assign local_init_done = init_done;
//write data path
assign write_data = itf_wr_data;
assign byte_en = itf_wr_data_byte_en;
assign write_data_valid = itf_wr_data_valid;
assign write_data_id = itf_wr_data_id;
// read data path
assign itf_rd_data_id = read_data_localid;
assign itf_rd_data_error = read_data_error;
assign itf_rd_data_valid = read_data_valid;
assign itf_rd_data_begin = read_data_begin;
assign itf_rd_data_last = read_data_last;
assign itf_rd_data = read_data;
assign itf_rd_data_id_early = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
//==============================================================================
// Logic below is to tie low itf_cmd_ready, itf_cmd_valid and itf_wr_data_ready when local_init_done is low
assign itf_cmd_ready = ~cmd_gen_full & local_init_done;
assign itf_wr_data_ready = ~wr_data_mem_full & local_init_done;
assign cmd_read = ~itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_write = itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_valid = itf_cmd_valid & local_init_done;
generate
begin : gen_rd_data_id_early_valid
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
end
else
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
end
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// onchip_ram_top.v ////
//// ////
//// ////
//// ////
//// Author(s): ////
//// De Nayer Instituut (emsys.denayer.wenk.be) ////
//// Nathan Yawn ([email protected]) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2003-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// //
// This file is a simple wrapper for on-chip (FPGA) RAM blocks, //
// coupled with a simple WISHBONE bus interface. It supports 2- //
// cycle writes, and 1-cycle reads. Bursts using bus tags (for //
// registered-feedback busses) are not supported at present. //
// Altera ALTSYNCRAM blocks are instantiated directly. Xilinx //
// BRAM blocks are not as easy to declare for a wide range of //
// devices, they are implied instead of declared directly. //
// //
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: onchip_ram_top.v,v $
// Revision 1.1 2010-03-29 19:34:52 Nathan
// The onchip_ram memory unit is not distributed on the OpenCores website as of this checkin; this version of the core may be used with the advanced debug system testbench until it is.
//
// Revision 1.1 2008/07/18 20:13:48 Nathan
// Changed directory structure to match existing projects.
//
// Revision 1.2 2008/05/22 19:56:36 Nathan
// Added implied BRAM for Xilinx FPGAs. Also added copyright, CVS log, and brief description.
//
`define ALTERA
module onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
// Function to calculate width of address signal.
function integer log2;
input [31:0] value;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
endfunction
//
// Parameters
//
parameter dwidth = 32;
parameter size_bytes = 4096;
parameter initfile = "NONE";
parameter words = (size_bytes / (dwidth/8)); // Don't override this. Really.
parameter awidth = log2(size_bytes)-1; // Don't override this either.
parameter bewidth = (dwidth/8); // Or this.
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [dwidth-1:0] wb_dat_i;
output [dwidth-1:0] wb_dat_o;
input [awidth-1:0] wb_adr_i;
input [bewidth-1:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [bewidth-1:0] be_i;
wire [dwidth-1:0] wb_dat_o;
wire ack_we;
reg ack_we1;
reg ack_we2;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = 1'b0; //wb_cyc_i & wb_stb_i & ???;
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[bewidth-1:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
// Little trick to keep the writes single-cycle:
// set the write ack signal on the falling clk edge, so it will be set halfway through the
// cycle and be registered at the end of the first clock cycle. To prevent contention for
// the next half-cycle, latch the ack_we1 signal on the next rising edge, and force the
// bus output low when that latched signal is high.
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we1 <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we1 <= #1 1'b1;
else
ack_we1 <= #1 1'b0;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we2 <= 1'b0;
else
ack_we2 <= ack_we1;
end
assign ack_we = ack_we1 & ~ack_we2;
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= 1'b1;
else
ack_re <= 1'b0;
end
`ifdef ALTERA
//
// change intended_device_family according to the FPGA device (Stratix or Cyclone)
//
altsyncram altsyncram_component (
.wren_a (we),
.clock0 (wb_clk_i),
.byteena_a (be_i),
.address_a (wb_adr_i[awidth-1:2]),
.data_a (wb_dat_i),
.q_a (wb_dat_o));
defparam
altsyncram_component.intended_device_family = "CycloneII",
altsyncram_component.width_a = dwidth,
altsyncram_component.widthad_a = (awidth-2),
altsyncram_component.numwords_a = (words),
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.width_byteena_a = bewidth,
altsyncram_component.byte_size = 8,
altsyncram_component.byteena_aclr_a = "NONE",
altsyncram_component.ram_block_type = "AUTO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.init_file = initfile;
`else
// Xilinx does not have anything so neat as a resizable memory array.
// We use generic code, which will imply a BRAM array.
// This will also work for non-Xilinx architectures, but be warned that
// it will not be recognized as an implied RAM block by the current Altera
// tools.
// The actual memory array...4 banks, for 4 separate byte lanes
reg [7:0] mem_bank0 [0:(words-1)];
reg [7:0] mem_bank1 [0:(words-1)];
reg [7:0] mem_bank2 [0:(words-1)];
reg [7:0] mem_bank3 [0:(words-1)];
// Write enables, qualified with byte lane enables
wire we_0, we_1, we_2, we_3;
// Enable, indicates any read or write operation
wire en;
// Yes, separate address registers, which will hold identical data. This
// is necessary to correctly imply a Xilinx BRAM. Because that's just
// how they roll.
reg [(awidth-3):0] addr_reg0;
reg [(awidth-3):0] addr_reg1;
reg [(awidth-3):0] addr_reg2;
reg [(awidth-3):0] addr_reg3;
assign we_0 = be_i[0] & wb_we_i;
assign we_1 = be_i[1] & wb_we_i;
assign we_2 = be_i[2] & wb_we_i;
assign we_3 = be_i[3] & wb_we_i;
assign en = (|be_i);
// Sequential bits. Setting of the address registers, and memory array writes.
always @ (posedge wb_clk_i)
begin
if (en)
begin
addr_reg0 <= wb_adr_i[(awidth-1):2];
if (we_0)
begin
mem_bank0[wb_adr_i[(awidth-1):2]] <= wb_dat_i[7:0];
end
end
if (en)
begin
addr_reg1 <= wb_adr_i[(awidth-1):2];
if (we_1)
begin
mem_bank1[wb_adr_i[(awidth-1):2]] <= wb_dat_i[15:8];
end
end
if (en)
begin
addr_reg2 <= wb_adr_i[(awidth-1):2];
if (we_2)
begin
mem_bank2[wb_adr_i[(awidth-1):2]] <= wb_dat_i[23:16];
end
end
if (en)
begin
addr_reg3 <= wb_adr_i[(awidth-1):2];
if (we_3)
begin
mem_bank3[wb_adr_i[(awidth-1):2]] <= wb_dat_i[31:24];
end
end
end
// Data output. Combinatorial, no output register.
assign wb_dat_o = {mem_bank3[addr_reg2], mem_bank2[addr_reg2], mem_bank1[addr_reg1], mem_bank0[addr_reg0]};
`endif
endmodule
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