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// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main (
input [1:0] vc83501,
input [1:0] v78d66e,
output [1:0] vbb8263,
output [1:0] v6f5c59
);
wire [0:1] w0;
wire [0:1] w1;
wire [0:1] w2;
assign w0 = vc83501;
assign vbb8263 = w0;
assign w1 = v78d66e;
assign v6f5c59 = w2;
v76f7ce v165459 (
.va8fcbc(w1),
.v8fd8fb(w2)
);
endmodule
//---- Top entity
module v76f7ce (
input [1:0] va8fcbc,
output [1:0] v8fd8fb
);
wire [0:1] w0;
wire [0:1] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign w0 = va8fcbc;
assign v8fd8fb = w1;
v0dbcb9 v7d1cb8 (
.v8b19dd(w0),
.v3f8943(w2),
.v64d863(w4)
);
v80ac84 v1cc6f4 (
.v67a3fc(w1),
.vee8a83(w3),
.v03aaf0(w5)
);
v3676a0 v214cf3 (
.v0e28cb(w2),
.vcbab45(w3)
);
v3676a0 v8b12b1 (
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- not-x2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- not-x2: 2-bits not gate
//---------------------------------------------------
//---- Top entity
module v0dbcb9 (
input [1:0] v8b19dd,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:1] w2;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = v8b19dd;
v0dbcb9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Split-all: Split the 2-bits bus into two wires
//---------------------------------------------------
module v0dbcb9_v9a2a06 (
input [1:0] i,
output o1,
output o0
);
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v80ac84 (
input vee8a83,
input v03aaf0,
output [1:0] v67a3fc
);
wire w0;
wire w1;
wire [0:1] w2;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v67a3fc = w2;
v80ac84_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Join-all: Joint two wires into a 2-bits Bus
//---------------------------------------------------
module v80ac84_v9a2a06 (
input i1,
input i0,
output [1:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
|
`include "reg_define.v"
`include "version.v"
module AXI2SREG
(
clk,
rst,
en,
wen,
din,
dout,
addr,
ien,
oen,
async,
tddmode,
ibase,
isize,
obase,
osize,
frame_len,
frame_adj,
tstart,
tend,
rstart,
rend,
iacnt,
ibcnt,
oacnt,
obcnt,
test,
axiwresp,
axirresp,
axistatus,
axiraddr,
axiwaddr,
adj_pending
);
parameter BASE = `AXI2SREG_BASE;
input clk,rst,en,wen;
input [31:0]din;
input [17:0]addr;
output reg ien,oen,async,tddmode;
output reg [31:0]dout;
output reg [31:0]ibase;
output reg [31:0]obase;
output reg [23:6]isize;
output reg [23:6]osize;
output reg [23:0]frame_len;
output reg [23:0]tstart;
output reg [23:0]tend;
output reg [23:0]rstart;
output reg [23:0]rend;
output reg [23:0]frame_adj;
output reg test;
input [23:6]iacnt;
input [23:6]oacnt;
input [31:0]ibcnt;
input [31:0]obcnt;
input [31:0]axiwresp;
input [31:0]axirresp;
input [31:0]axistatus;
input [31:0]axiraddr;
input [31:0]axiwaddr;
input adj_pending;
wire [159:0]version_git;
reg [31:0]ibcnt_reg;
reg [31:0]obcnt_reg;
always @(posedge clk or posedge rst)
begin
if(rst) begin
ien <= 1'b0;
oen <= 1'b0;
tddmode <= 1'b0;
ibase <= 32'hfffc0000;
isize <= 18'h400;
obase <= 32'hfffd0000;
osize <= 18'h400;
frame_len <= 24'd1920;
frame_len <= 24'd1920;
tstart <= 24'h0;
tend <= 24'd1919;
rstart <= 24'h0;
rend <= 24'd1919;
test <= 1'b0;
end
else if(clk) begin
if( en==1'b1 ) begin
// write
if( wen==1'b1 ) begin
case( addr )
// define AXI2S_EN 18'h00
`AXI2S_EN: begin
ien <= din[0];
oen <= din[1];
async <= din[2];
tddmode <= din[3];
end
// define AXI2S_TEST 18'h04
`AXI2S_TEST: begin
test <= din[0];
end
// define AXI2S_IBASE 18'h10
`AXI2S_IBASE: begin
ibase <= din;
end
// define AXI2S_ISIZE 18'h14
`AXI2S_ISIZE: begin
isize <= din[23:6];
end
// define AXI2S_OBASE 18'h18
`AXI2S_OBASE: begin
obase <= din;
end
// define AXI2S_OSIZE 18'h1C
`AXI2S_OSIZE: begin
osize <= din[23:6];
end
// define FRAME_LEN 18'h20
`FRAME_LEN: begin
frame_len <= din[23:0];
end
// define FRAME_ADJ 18'h24
`FRAME_ADJ: begin
frame_adj <= din[23:0];
end
// define TSTART 18'h30
`TSTART: begin
tstart <= din[23:0];
end
// define TEND 18'h34
`TEND: begin
tend <= din[23:0];
end
// define RSTART 18'h38
`RSTART: begin
rstart <= din[23:0];
end
// define REND 18'h3C
`REND: begin
rend <= din[23:0];
end
endcase
end
end
end
end
always @(posedge clk) begin
if(addr[17:8]==BASE[17:8] && en==1'b1 ) begin
case( addr )
// define AXI2S_IACNT 18'h10
`AXI2S_IACNT: begin
ibcnt_reg <= ibcnt;
end
// define AXI2S_OACNT 18'h18
`AXI2S_OACNT: begin
obcnt_reg <= obcnt;
end
endcase
end
end
always @(*) begin
if(addr[17:8]==BASE[17:8] && en==1'b1 ) begin
case( addr )
// define AXI2S_STATE 18'h00
`AXI2S_STATE: begin
dout[0] <= ien;
dout[1] <= oen;
dout[2] <= tddmode;
dout[3] <= adj_pending;
dout[31:4] <= 28'd0;
end
// define AXI2S_IACNT 18'h10
`AXI2S_IACNT: begin
dout[23:6] <= iacnt;
dout[31:24] <= 8'd0;
dout[5:0] <= 6'd0;
end
// define AXI2S_IBCNT 18'h14
`AXI2S_IBCNT: begin
dout <= ibcnt_reg;
end
// define AXI2S_OACNT 18'h18
`AXI2S_OACNT: begin
dout[23:6] <= oacnt;
dout[31:24] <= 8'd0;
dout[5:0] <= 6'd0;
end
// define AXI2S_OBCNT 18'h1c
`AXI2S_OBCNT: begin
dout <= obcnt_reg;
end
`ifdef DEBUG
// define AXI_RRESP 18'h20
`AXI_RRESP: begin
dout <= axirresp;
end
// define AXI_WRESP 18'h24
`AXI_WRESP: begin
dout <= axiwresp;
end
// define AXI_STATUS 18'h28
`AXI_STATUS: begin
dout <= axistatus;
end
// define AXI_RADDR 18'h30
`AXI_RADDR: begin
dout <= axiraddr;
end
// define AXI_WADDR 18'h34
`AXI_WADDR: begin
dout <= axiwaddr;
end
`endif
// define VER_MAJOR 18'h40
`VER_MAJOR: begin
dout <= `VERSION_MAJOR;
end
// define VER_MINOR0 18'h50
`VER_MINOR0: begin
dout <= version_git[31:0];
end
// define VER_MINOR1 18'h54
`VER_MINOR1: begin
dout <= version_git[63:32];
end
// define VER_MINOR2 18'h58
`VER_MINOR2: begin
dout <= version_git[95:64];
end
// define VER_MINOR3 18'h5c
`VER_MINOR3: begin
dout <= version_git[127:96];
end
// define VER_MINOR4 18'h60
`VER_MINOR4: begin
dout <= version_git[159:128];
end
endcase
end
else dout <= 32'h0;
end
assign version_git = `VERSION;
endmodule
|
//
// Paul Gao 02/2021
//
// This is the sender part of bsg_link_sdr, an SDR communication endpoint
// over single source-synchronous channel.
//
// Typical usage: Communication between different hierarchical blocks in
// different clock domains on ASIC. In this way the clock trees can be
// fully independent in different hierarchical blocks.
//
//
// General reset procedures:
//
// Step 1: Assert io_link_reset and core_link_reset.
// Step 2: async_token_reset must be posedge/negedge toggled (0->1->0)
// at least once. token_clk_i cannot toggle during this step.
// Step 3: io_clk_i posedge toggled at least four times after that.
// Step 4: De-assert upstream_io_link_reset to generate io_clk_o.
// Step 5: De-assert downstream_io_link_reset.
// Step 6: De-assert downstream_core_link_reset.
//
// *************************************************************************
// async upstream downstream downstream
// token_reset io_link_reset io_link_reset core_link_reset
// Step 1 0 1 1 1
// Step 2 1 1 1 1
// Step 3 0 1 1 1
// Step 4 0 0 1 1
// Step 5 0 0 0 1
// Step 6 0 0 0 0
// *************************************************************************
//
module bsg_link_sdr_upstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
,parameter strength_p = 0
)
(// Core side
input io_clk_i
,input io_link_reset_i
,input async_token_reset_i
,input io_v_i
,input [width_p-1:0] io_data_i
,output io_ready_and_o
// IO side
,output io_clk_o
,output io_v_o
,output [width_p-1:0] io_data_o
,input token_clk_i
);
logic osdr_v_li;
logic [width_p-1:0] osdr_data_li;
bsg_link_source_sync_upstream_sync
#(.width_p (width_p)
,.lg_fifo_depth_p (lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p (bypass_twofer_fifo_p)
) sso
(.io_clk_i (io_clk_i)
,.io_link_reset_i (io_link_reset_i)
,.async_token_reset_i(async_token_reset_i)
,.io_v_i (io_v_i)
,.io_data_i (io_data_i)
,.io_ready_and_o (io_ready_and_o)
,.io_v_o (osdr_v_li)
,.io_data_o (osdr_data_li)
,.token_clk_i (token_clk_i)
);
// valid and data signals are sent together
bsg_link_osdr_phy
#(.width_p(width_p+1)
,.strength_p(strength_p)
) osdr_phy
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.data_i ({osdr_v_li, osdr_data_li})
,.clk_o (io_clk_o)
,.data_o ({io_v_o, io_data_o})
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_sdr_upstream)
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate task calling a function
module main;
reg var1,var2;
reg in1;
reg error;
function foo ;
input in1 ;
foo = in1 ;
endfunction
task my_task ;
input in1,in2;
output out1,out2;
begin
out1 = foo(~foo(in1)) ;
out2 = foo(in2) ;
end
endtask
initial
begin
error = 0;
my_task(1'b1,1'b0,var1,var2);
if(~(~var1 & ~var2))
begin
$display("FAILED - task 3.14E task calling a function (1)");
error = 1;
end
in1 = 0;
my_task(~in1,~in1,var1,var2);
if(~(~var1 & var2))
begin
$display("FAILED - task 3.14E task calling a function(2)");
error = 1;
end
in1 = 0;
my_task(in1,in1,var1,var2);
if(~(var1 & ~var2))
begin
$display("FAILED - task 3.14E task calling a function(3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// Code your design here
//////////////////////////////////////////////////////////////////////////////////////////////////7
// Module: control_DAT
// Projecto: SD Host
//
// Descripcion: Modulo de control para el bloque DAT del SD Host , este modulo controla las señales para solicitud de un nuevo servicio , escritura y lectura
// hacia la capa fisica que se encarga de leer y escribir desde y hacia el fifo y la tarjeda SD
// Autor: Mario Zamora Rivera
//
//
//
/////////////////////////////////////////////////////////////////////////////////////////////////////
module control_DAT(input logic writeRead,
input logic multiblock,
input logic timeoutenable,
input logic [15:0] timeout ,
input logic newService,
input logic clock,
input logic reset,
input logic[3:0] blockSize,
input logic IDLE_in,
input logic fifo_full,
input logic recibido,
input logic transferComplete,
output logic newService_fisica,
output logic [15:0] timeout_fisica,
output logic writeRead_fisica,
output logic reset_fisica,
output logic complete,
output logic IDLE_out
);
////////////////////////////////////////7
//Las variables que pasan desde la capa de control a la capa fisica con nombres similares tendran un identificador despues del _ para la capa fisica
////////////////////////////////////7
parameter RESET=6'b000001, IDLE = 6'b000010, checkfifo = 6'b000100 ,solicitud=6'b001000 , waitResponse= 6'b010000 , waitIdle= 6'b100000 ;
reg [5:0] state;
reg [5:0] next_state;
reg [4:0] blockCount;
reg [4:0] blockCountFlip;
//----------Seq Logic-----------------------------------------------------seqlogic------------------------------------------------\\\\
always @ ( posedge clock ) begin
if (reset == 1'b1) begin
state <= RESET;
// blockCount<=5'b00000 ;
// next_state<=6'b000000 ;
end else begin
state <= next_state;
end
end
//----------Output Logic------------------------------------------------Output logic----------------------------------------------------\\\
always @ (posedge clock)begin
if (reset == 1'b1) begin
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b1;
complete<=1'b0;
IDLE_out<=1'b0;
//blockCount<=5'b00000 ;
blockCountFlip<=5'b00000 ;
end
else begin
case(state)
RESET : begin///////////////////////////////////////RESET
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=5'b00000 ;
// blockCount<=5'b00000 ;
// blockCount<=blockCount ;
end////////////////////////////////////////////Final RESET
IDLE : begin////////////////////////////////////IDLE
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b1;
blockCountFlip<=5'b00000 ;
// blockCount<=5'b00000 ;
// blockCount<=blockCount ;
end///////////////////////////////////////////Final IDLE
checkfifo : begin////////////////////////////////checkfifo
newService_fisica<=1'b0;
if (timeoutenable==1'b1) begin
timeout_fisica<=timeout;
end
else begin
timeout_fisica<=16'b0000000000000000;
end
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=5'b00000 ;
// blockCount= blockCount+5'b00001;
// blockCount<=blockCount+5'b11111 ;
end
solicitud : begin ///////////////////////////////////////solicitud
newService_fisica<=1'b1;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
//blockCount<=blockCount ;
end
waitResponse : begin
newService_fisica<=1'b0;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
//blockCount<=blockCount ;
end
waitIdle : begin
newService_fisica<=1'b0;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b1;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=blockCount ;
end
default : begin
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=blockCount ;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
//----------------------------logic block-------------------------------------------------------------logic block---------------------------------------------̣\\\
always @ ( * ) begin//Logica proximo estado
next_state = 6'b000000;
blockCount=blockCountFlip;
case(state)
RESET : if (IDLE_in== 1'b1)begin/////////////////////////RESET
next_state=IDLE;
blockCount=5'b00000 ;
end
else begin
next_state=RESET;
blockCount=5'b00000 ;
end
IDLE :if (newService== 1'b1) begin//////////////////////IDLE
next_state=checkfifo;
blockCount=5'b00000 ;
end
else begin
next_state=IDLE;
blockCount=5'b00000 ;
end
checkfifo :if (fifo_full== 1'b1) begin/////////////////////checkfifo
next_state=solicitud;
// blockCount=5'b00000 ;
end
else begin
//blockCount=5'b00000 ;
next_state=checkfifo;
end
solicitud :if (recibido== 1'b1) begin/////////////////////////////solicitud
next_state=waitResponse;
//blockCount=5'b00000 ;
end
else begin
next_state=solicitud;
//blockCount=5'b00000 ;
end
waitResponse :if (transferComplete== 1'b1) begin//////////////////////waitResponse
next_state=waitIdle;
// blockCount=5'b00000 ;
end
else begin
next_state=waitResponse;
//blockCount=5'b00000 ;
end
waitIdle:////////////////////////////////////////////////waitIdle
if (IDLE_in== 1'b1) begin
if ((multiblock==0)||(blockCountFlip==blockSize)) begin
next_state=IDLE;
blockCount=5'b00000 ;
end
else begin
blockCount=blockCountFlip+5'b00001;
next_state=checkfifo;
end
end
else begin
//blockCount=5'b00000 ;
next_state=waitIdle;
end
/* if (multiblock==1) begin
if (blockCount==blockSize) begin
next_state=IDLE;
end
else begin
// blockCount=blockCount+1;
next_state=checkfifo;
end
end
else begin
next_state=IDLE;
end*/
default : begin
next_state=IDLE;
end
endcase
//blockCount=5'b00000 ;
end//////////////////////////////////end combinational block
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V |
//----------------------------------------------------------------------
// Copyright 2007-2010 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
//This is dummy DUT.
module dut_dummy(
input wire ubus_req_master_0,
output reg ubus_gnt_master_0,
input wire ubus_req_master_1,
output reg ubus_gnt_master_1,
input wire ubus_clock,
input wire ubus_reset,
input wire [15:0] ubus_addr,
input wire [1:0] ubus_size,
output reg ubus_read,
output reg ubus_write,
output reg ubus_start,
input wire ubus_bip,
inout wire [7:0] ubus_data,
input wire ubus_wait,
input wire ubus_error);
bit[2:0] st;
// Basic arbiter, supports two masters, 0 has priority over 1
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_start <= 1'b0;
st<=3'h0;
end
else
case(st)
0: begin //Begin out of Reset
ubus_start <= 1'b1;
st<=3'h3;
end
3: begin //Start state
ubus_start <= 1'b0;
if((ubus_gnt_master_0==0) && (ubus_gnt_master_1==0)) begin
st<=3'h4;
end
else
st<=3'h1;
end
4: begin // No-op state
ubus_start <= 1'b1;
st<=3'h3;
end
1: begin // Addr state
st<=3'h2;
ubus_start <= 1'b0;
end
2: begin // Data state
if((ubus_error==1) || ((ubus_bip==0) && (ubus_wait==0))) begin
st<=3'h3;
ubus_start <= 1'b1;
end
else begin
st<=3'h2;
ubus_start <= 1'b0;
end
end
endcase
end
always @(negedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset == 1'b1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
else begin
if(ubus_start && ubus_req_master_0) begin
ubus_gnt_master_0 <= 1;
ubus_gnt_master_1 <= 0;
end
else if(ubus_start && !ubus_req_master_0 && ubus_req_master_1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 1;
end
else begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
end
end
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
else if(ubus_start && !ubus_gnt_master_0 && !ubus_gnt_master_1) begin
ubus_read <= 1'b0;
ubus_write <= 1'b0;
end
else begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`timescale 1ns/1ns
module riffa
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA",
parameter C_FPGA_NAME = "FPGA", // TODO: Give each channel a unique name
parameter C_FPGA_ID = 0,// A value from 0 to 255 uniquely identifying this RIFFA design
parameter C_DEPTH_PACKETS = 10)
(input CLK,
input RST_BUS,
output RST_OUT,
input DONE_TXC_RST,
input DONE_TXR_RST,
// Interface: RXC Engine
input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
input RXC_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
input RXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
input RXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
input [`SIG_LBE_W-1:0] RXC_META_LDWBE,
input [`SIG_FBE_W-1:0] RXC_META_FDWBE,
input [`SIG_TAG_W-1:0] RXC_META_TAG,
input [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
input [`SIG_TYPE_W-1:0] RXC_META_TYPE,
input [`SIG_LEN_W-1:0] RXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
input [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
input RXC_META_EP,
// Interface: RXR Engine
input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
input RXR_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
input RXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
input RXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
input [`SIG_TC_W-1:0] RXR_META_TC,
input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
input [`SIG_TAG_W-1:0] RXR_META_TAG,
input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
input RXR_META_EP,
// Interface: TXC Engine
output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
output TXC_DATA_VALID,
output TXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
output TXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
input TXC_DATA_READY,
output TXC_META_VALID,
output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
output [`SIG_TAG_W-1:0] TXC_META_TAG,
output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
output [`SIG_TC_W-1:0] TXC_META_TC,
output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
output TXC_META_EP,
input TXC_META_READY,
input TXC_SENT,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
input CONFIG_BUS_MASTER_ENABLE,
input [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
input [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
input [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
input [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
input [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_INTERRUPT_MSIENABLE,
input CONFIG_CPL_BOUNDARY_SEL,
// Interrupt Request
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7; // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
localparam C_NUM_VECTORS = 2;
localparam C_VECTOR_WIDTH = 32;
// Interface: Reorder Buffer Output
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
wire [C_NUM_CHNL-1:0] wRxEngMainDone;
wire [C_NUM_CHNL-1:0] wRxEngMainErr;
// Interface: Reorder Buffer to SG RX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
// Interface: Reorder Buffer to SG TX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
// Interface: Channel TX Write
wire [C_NUM_CHNL-1:0] wTxEngWrReq;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngWrAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngWrLen;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
wire [C_NUM_CHNL-1:0] wTxEngWrAck;
wire [C_NUM_CHNL-1:0] wTxEngWrSent;
// Interface: Channel TX Read
wire [C_NUM_CHNL-1:0] wTxEngRdReq;
wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngRdAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngRdLen;
wire [C_NUM_CHNL-1:0] wTxEngRdAck;
// Interface: Channel Interrupts
wire [C_NUM_CHNL-1:0] wChnlSgRxBufRecvd;
wire [C_NUM_CHNL-1:0] wChnlRxDone;
wire [C_NUM_CHNL-1:0] wChnlTxRequest;
wire [C_NUM_CHNL-1:0] wChnlTxDone;
wire [C_NUM_CHNL-1:0] wChnlSgTxBufRecvd;
wire wInternalTagValid;
wire [5:0] wInternalTag;
wire wExternalTagValid;
wire [C_TAG_WIDTH-1:0] wExternalTag;
// Interface: Channel - PIO Read
wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] wChnlTxReqLen;
wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] wChnlTxOfflast;
wire wCoreSettingsReady;
wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
wire [C_NUM_VECTORS-1:0] wIntrVectorReady;
wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] wIntrVector;
wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] wChnlTxDoneLen;
wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] wChnlRxDoneLen;
wire wChnlNameReady;
// Interface: Channel - PIO Write
wire [31:0] wChnlReqData;
wire [C_NUM_CHNL-1:0] wChnlSgRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
// Interface: TXC Engine
wire [C_PCI_DATA_WIDTH-1:0] _wTxcData, wTxcData;
wire _wTxcDataValid, wTxcDataValid;
wire _wTxcDataStartFlag, wTxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataStartOffset, wTxcDataStartOffset;
wire _wTxcDataEndFlag, wTxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataEndOffset, wTxcDataEndOffset;
wire _wTxcDataReady, wTxcDataReady;
wire _wTxcMetaValid, wTxcMetaValid;
wire [`SIG_FBE_W-1:0] _wTxcMetaFdwbe, wTxcMetaFdwbe;
wire [`SIG_LBE_W-1:0] _wTxcMetaLdwbe, wTxcMetaLdwbe;
wire [`SIG_LOWADDR_W-1:0] _wTxcMetaAddr, wTxcMetaAddr;
wire [`SIG_TYPE_W-1:0] _wTxcMetaType, wTxcMetaType;
wire [`SIG_LEN_W-1:0] _wTxcMetaLength, wTxcMetaLength;
wire [`SIG_BYTECNT_W-1:0] _wTxcMetaByteCount, wTxcMetaByteCount;
wire [`SIG_TAG_W-1:0] _wTxcMetaTag, wTxcMetaTag;
wire [`SIG_REQID_W-1:0] _wTxcMetaRequesterId, wTxcMetaRequesterId;
wire [`SIG_TC_W-1:0] _wTxcMetaTc, wTxcMetaTc;
wire [`SIG_ATTR_W-1:0] _wTxcMetaAttr, wTxcMetaAttr;
wire _wTxcMetaEp, wTxcMetaEp;
wire _wTxcMetaReady, wTxcMetaReady;
wire wRxBufSpaceAvail;
wire wTxEngRdReqSent;
wire wRxEngRdComplete;
wire [31:0] wCPciDataWidth;
reg [31:0] wCFpgaId;
reg [4:0] rWideRst;
reg rRst;
genvar i;
assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
assign wCoreSettings = {1'd0, wCFpgaId, wCPciDataWidth[8:5],
CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE,
CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE,
C_NUM_CHNL[3:0]};
// Interface: TXC Engine
assign TXC_DATA = wTxcData;
assign TXC_DATA_START_FLAG = wTxcDataStartFlag;
assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
assign TXC_DATA_VALID = wTxcDataValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcDataReady = TXC_DATA_READY & ~wPendingRst & DONE_TXC_RST;
assign TXC_META_FDWBE = wTxcMetaFdwbe;
assign TXC_META_LDWBE = wTxcMetaLdwbe;
assign TXC_META_ADDR = wTxcMetaAddr;
assign TXC_META_TYPE = wTxcMetaType;
assign TXC_META_LENGTH = wTxcMetaLength;
assign TXC_META_BYTE_COUNT = wTxcMetaByteCount;
assign TXC_META_TAG = wTxcMetaTag;
assign TXC_META_REQUESTER_ID = wTxcMetaRequesterId;
assign TXC_META_TC = wTxcMetaTc;
assign TXC_META_ATTR = wTxcMetaAttr;
assign TXC_META_EP = wTxcMetaEp;
assign TXC_META_VALID = wTxcMetaValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcMetaReady = TXC_META_READY & ~wPendingRst & DONE_TXC_RST;
/* Workaround for a bug reported by the NetFPGA group, where the parameter
C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wCPciDataWidth = 32;
end else if (C_PCI_DATA_WIDTH == 64) begin
assign wCPciDataWidth = 64;
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wCPciDataWidth = 128;
end else if (C_PCI_DATA_WIDTH == 256) begin
assign wCPciDataWidth = 256;
end
always @(*) begin
wCFpgaId = 0;
if((C_FPGA_ID & 128) != 0) begin
wCFpgaId[7] = 1;
end else if ((C_FPGA_ID & 64) != 1) begin
wCFpgaId[6] = 1;
end else if ((C_FPGA_ID & 32) != 1) begin
wCFpgaId[5] = 1;
end else if ((C_FPGA_ID & 16) != 1) begin
wCFpgaId[4] = 1;
end else if ((C_FPGA_ID & 8) != 1) begin
wCFpgaId[3] = 1;
end else if ((C_FPGA_ID & 4) != 1) begin
wCFpgaId[2] = 1;
end else if ((C_FPGA_ID & 2) != 1) begin
wCFpgaId[1] = 1;
end else if ((C_FPGA_ID & 1) != 1) begin
wCFpgaId[0] = 1;
end
end
endgenerate
/* The purpose of these two hold modules is to safely reset the TX path and
still respond to the core status request (which causes a RIFFA reset). We
could wait until after the completion has been transmitted, but we have no
guarantee that the TX path is operating correctly until after we reset */
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (2 * `SIG_FBE_W + `SIG_LOWADDR_W +
`SIG_TYPE_W + `SIG_LEN_W +
`SIG_BYTECNT_W + `SIG_TAG_W +
`SIG_REQID_W + `SIG_TC_W +
`SIG_ATTR_W + 1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_meta_hold
(// Outputs
.WR_DATA_READY (_wTxcMetaReady), // NC
.RD_DATA ({wTxcMetaFdwbe, wTxcMetaLdwbe,
wTxcMetaAddr, wTxcMetaType,
wTxcMetaLength,
wTxcMetaByteCount, wTxcMetaTag,
wTxcMetaRequesterId, wTxcMetaTc,
wTxcMetaAttr, wTxcMetaEp}),
.RD_DATA_VALID (wTxcMetaValid),
// Inputs
.WR_DATA ({_wTxcMetaFdwbe, _wTxcMetaLdwbe,
_wTxcMetaAddr, _wTxcMetaType,
_wTxcMetaLength,
_wTxcMetaByteCount, _wTxcMetaTag,
_wTxcMetaRequesterId, _wTxcMetaTc,
_wTxcMetaAttr, _wTxcMetaEp}),
.WR_DATA_VALID (_wTxcMetaValid),
.RD_DATA_READY (wTxcMetaReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (C_PCI_DATA_WIDTH +
2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_data_hold
(// Outputs
.WR_DATA_READY (_wTxcDataReady), // NC
.RD_DATA ({wTxcData, wTxcDataStartFlag,
wTxcDataStartOffset, wTxcDataEndFlag,
wTxcDataEndOffset}),
.RD_DATA_VALID (wTxcDataValid),
// Inputs
.WR_DATA ({_wTxcData, _wTxcDataStartFlag,
_wTxcDataStartOffset, _wTxcDataEndFlag,
_wTxcDataEndOffset}),
.WR_DATA_VALID (_wTxcDataValid),
.RD_DATA_READY (wTxcDataReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
reset_extender
#(.C_RST_COUNT (8)
/*AUTOINSTPARAM*/)
reset_extender_inst
(// Outputs
.PENDING_RST (wPendingRst),
// Inputs
.RST_LOGIC (wCoreSettingsReady),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS));
reorder_queue
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH))
reorderQueue
(.RST (RST_OUT),
.VALID (RXC_DATA_VALID),
.DATA_START_FLAG (RXC_DATA_START_FLAG),
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (RXC_DATA_END_FLAG),
.DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (RXC_DATA),
.DATA_EN (RXC_DATA_WORD_ENABLE),
.DONE (wRxEngRdComplete),
.ERR (RXC_META_EP),
.TAG (RXC_META_TAG[C_TAG_WIDTH-1:0]),
.INT_TAG (wInternalTag),
.INT_TAG_VALID (wInternalTagValid),
.EXT_TAG (wExternalTag),
.EXT_TAG_VALID (wExternalTagValid),
.ENG_DATA (wRxEngData),
.MAIN_DATA_EN (wRxEngMainDataEn),
.MAIN_DONE (wRxEngMainDone),
.MAIN_ERR (wRxEngMainErr),
.SG_RX_DATA_EN (wRxEngSgRxDataEn),
.SG_RX_DONE (wRxEngSgRxDone),
.SG_RX_ERR (wRxEngSgRxErr),
.SG_TX_DATA_EN (wRxEngSgTxDataEn),
.SG_TX_DONE (wRxEngSgTxDone),
.SG_TX_ERR (wRxEngSgTxErr),
/*AUTOINST*/
// Inputs
.CLK (CLK));
registers
#(// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_NUM_VECTORS (C_NUM_VECTORS),
.C_VECTOR_WIDTH (C_VECTOR_WIDTH),
.C_FPGA_NAME (C_FPGA_NAME))
reg_inst
(// Outputs
// Write Interfaces
.CHNL_REQ_DATA (wChnlReqData[31:0]),
.CHNL_SGRX_LEN_VALID (wChnlSgRxLenValid),
.CHNL_SGRX_ADDRLO_VALID (wChnlSgRxAddrLoValid),
.CHNL_SGRX_ADDRHI_VALID (wChnlSgRxAddrHiValid),
.CHNL_SGTX_LEN_VALID (wChnlSgTxLenValid),
.CHNL_SGTX_ADDRLO_VALID (wChnlSgTxAddrLoValid),
.CHNL_SGTX_ADDRHI_VALID (wChnlSgTxAddrHiValid),
.CHNL_RX_LEN_VALID (wChnlRxLenValid),
.CHNL_RX_OFFLAST_VALID (wChnlRxOfflastValid),
// Read Interfaces
.CHNL_TX_LEN_READY (wChnlTxLenReady),
.CHNL_TX_OFFLAST_READY (wChnlTxOfflastReady),
.CORE_SETTINGS_READY (wCoreSettingsReady),
.INTR_VECTOR_READY (wIntrVectorReady),
.CHNL_TX_DONE_READY (wChnlTxDoneReady),
.CHNL_RX_DONE_READY (wChnlRxDoneReady),
.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
// TXC Engine Interface
.TXC_DATA_VALID (_wTxcDataValid),
.TXC_DATA (_wTxcData[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (_wTxcDataStartFlag),
.TXC_DATA_START_OFFSET (_wTxcDataStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (_wTxcDataEndFlag),
.TXC_DATA_END_OFFSET (_wTxcDataEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (_wTxcMetaValid),
.TXC_META_FDWBE (_wTxcMetaFdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (_wTxcMetaLdwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (_wTxcMetaAddr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (_wTxcMetaType[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (_wTxcMetaLength[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (_wTxcMetaByteCount[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (_wTxcMetaTag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (_wTxcMetaRequesterId[`SIG_REQID_W-1:0]),
.TXC_META_TC (_wTxcMetaTc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (_wTxcMetaAttr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (_wTxcMetaEp),
// Inputs
// Read Data
.CORE_SETTINGS (wCoreSettings),
.CHNL_TX_REQLEN (wChnlTxReqLen),
.CHNL_TX_OFFLAST (wChnlTxOfflast),
.CHNL_TX_DONELEN (wChnlTxDoneLen),
.CHNL_RX_DONELEN (wChnlRxDoneLen),
.INTR_VECTOR (wIntrVector),
.RST_IN (RST_OUT),
.TXC_DATA_READY (_wTxcDataReady),
.TXC_META_READY (_wTxcMetaReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]));
// Track receive buffer flow control credits (header & Data)
recv_credit_flow_ctrl rc_fc
(// Outputs
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
// Inputs
.RX_ENG_RD_DONE (wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
.RST (RST_OUT),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
// Connect the interrupt vector and controller.
interrupt
#(.C_NUM_CHNL (C_NUM_CHNL))
intr
(// Inputs
.RST (RST_OUT),
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
.RX_TXN_DONE (wChnlRxDone),
.TX_TXN (wChnlTxRequest),
.TX_SG_BUF_RECVD (wChnlSgTxBufRecvd),
.TX_TXN_DONE (wChnlTxDone),
.VECT_0_RST (wIntrVectorReady[0]),
.VECT_1_RST (wIntrVectorReady[1]),
.VECT_RST (_wTxcData[31:0]),
.VECT_0 (wIntrVector[31:0]),
.VECT_1 (wIntrVector[63:32]),
.INTR_LEGACY_CLR (1'd0),
/*AUTOINST*/
// Outputs
.INTR_MSI_REQUEST (INTR_MSI_REQUEST),
// Inputs
.CLK (CLK),
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY (INTR_MSI_RDY));
tx_multiplexer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
tx_mux_inst
(
// Outputs
.WR_DATA_REN (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
.WR_ACK (wTxEngWrAck[C_NUM_CHNL-1:0]),
.RD_ACK (wTxEngRdAck[C_NUM_CHNL-1:0]),
.INT_TAG (wInternalTag[5:0]),
.INT_TAG_VALID (wInternalTagValid),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
// Inputs
.RST_IN (RST_OUT),
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.WR_SENT (wTxEngWrSent[C_NUM_CHNL-1:0]),
.RD_REQ (wTxEngRdReq[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (wExternalTag[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (wExternalTagValid),
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
/*AUTOINST*/
// Outputs
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT));
// Generate and link up the channels.
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
channel
#(
.C_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(
.RST(RST_OUT),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.PIO_DATA(wChnlReqData),
.ENG_DATA(wRxEngData),
.SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
.SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
.TXN_TX(wChnlTxRequest[i]),
.TXN_TX_DONE(wChnlTxDone[i]),
.TXN_RX_DONE(wChnlRxDone[i]),
.SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
.SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
.SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
.SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
.SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
.SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
.TXN_RX_LEN_VALID(wChnlRxLenValid[i]),
.TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]),
.TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
.TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
.TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
.TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
.TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
.TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
.TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
.RX_REQ(wTxEngRdReq[i]),
.RX_REQ_ACK(wTxEngRdAck[i]),
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
.RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
.RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
.TX_REQ(wTxEngWrReq[i]),
.TX_REQ_ACK(wTxEngWrAck[i]),
.TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]),
.TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]),
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.TX_DATA_REN(wTxEngWrDataRen[i]),
.TX_SENT(wTxEngWrSent[i]),
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.MAIN_DONE(wRxEngMainDone[i]),
.MAIN_ERR(wRxEngMainErr[i]),
.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_RX_DONE(wRxEngSgRxDone[i]),
.SG_RX_ERR(wRxEngSgRxErr[i]),
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_TX_DONE(wRxEngSgTxDone[i]),
.SG_TX_ERR(wRxEngSgTxErr[i]),
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
.CHNL_RX(CHNL_RX[i]),
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
.CHNL_TX(CHNL_TX[i]),
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "import")
// End:
|
//====================================================================
// bsg_imul_iterative.v
// 11/15/2016, [email protected]
//====================================================================
//
// An 32bit integer iterative multiplier, capable of signed & unsigned division
// a3 a2 a1 a0
// b3 b2 b1 b0
// ------------------------------------------------------------------
// | a3b0 a2b0 a1b0 a0b0
// a3b1 | a2b1 a1b1 a0b1
// a3b2 a2b2 | a1b2 a0b2
// a3b3 a2b3 a1b3 | a0b3
// ------------------------------------------------------------------
// High Part | Low Part
//
// 1. for LOW part output:
// def imul( a, b ):
// result = 0
// for i in range(32):
// if b & 0x1 == 1:
// result += a
// a = a << 1
// b = b >> 1
// return result
//
// 2. for HIGH part output
// def imul( a, b ):
// result = 0
// for i in range(31):
// if b & 0x1 == 1:
// result = ( {1'b0,result} + {1'b0,a}) >> 1
// else:
// result = result >> 1
//
// b = b >> 1
// return result
// 3. for negtive high part output, we have to check if the low part of the
// abs(result) are all zeros. If it is all zero, we have to add 1 to the
// neg high part, otherwise we onely have to neg the high part
// -(4'b10_00) = ~(4'b10 00) + 1 = 4'b01_11 + 1= 4'b10_00
// -(4'b10_10) = ~(4'b10_10) + 1 = 4'b01_01 + 1= 4'b01_10
//
// We add a one bit register to track whether the shifted out LSB of the result
// are all zeros
//
`include "bsg_defines.v"
module bsg_imul_iterative #( width_p = 32)
(input clk_i
,input reset_i
,input v_i //there is a request
,output ready_o //idiv is idle
,input [width_p-1: 0] opA_i
,input signed_opA_i
,input [width_p-1: 0] opB_i
,input signed_opB_i
//needs the high part result or low part result
,input gets_high_part_i
,output v_o //result is valid
,output [width_p-1: 0] result_o
,input yumi_i
);
localparam lg_width_lp = `BSG_SAFE_CLOG2( width_p + 1);
///////////////////////////////////////////////////////////////////////////////
// counter for the shift operation
logic[lg_width_lp-1:0] shift_counter_r;
logic gets_high_part_r;
wire shift_counter_full = gets_high_part_r
? ( shift_counter_r == (width_p-1) )
: ( shift_counter_r == width_p );
///////////////////////////////////////////////////////////////////////////////
// The state machine
typedef enum logic[2:0] {IDLE, NEG_A, NEG_B, CALC, NEG_R, DONE } imul_ctrl_stat;
imul_ctrl_stat curr_state_r, next_state;
// state machine register
always_ff@( posedge clk_i ) begin
if( reset_i ) curr_state_r <= IDLE;
else curr_state_r <= next_state;
end
//determing next state
always_comb begin
unique case(curr_state_r )
IDLE: begin
if( v_i ) next_state = NEG_A;
else next_state = IDLE;
end
NEG_A: next_state = NEG_B;
NEG_B: next_state = CALC ;
CALC: begin
if( !shift_counter_full ) next_state = CALC;
else next_state = NEG_R;
end
NEG_R: next_state = DONE;
DONE: begin
if( yumi_i ) next_state = IDLE;
else next_state = DONE;
end
default: next_state = IDLE;
endcase
end
///////////////////////////////////////////////////////////////////////////////
// update the shift_counter_r
always_ff@( posedge clk_i ) begin
if ( reset_i ) shift_counter_r <= 'b0; //reset
else if( curr_state_r != CALC && next_state == CALC )
shift_counter_r <= 'b0; //new request
else if( curr_state_r == CALC)
shift_counter_r <= shift_counter_r + 1;
end
///////////////////////////////////////////////////////////////////////////////
// the computation logic
logic [width_p-1:0] opA_r, opB_r, result_r;
logic [width_p-1:0] adder_a, adder_b;
logic [width_p :0] adder_result,shifted_adder_result;
// -opA_r = ~opA_r + 1, reunsing the adder here
assign adder_a = (curr_state_r == NEG_A) ? ~opA_r :
(curr_state_r == NEG_B) ? ~opB_r :
(curr_state_r == NEG_R) ? ~result_r : result_r;
wire adder_neg_op = (curr_state_r == NEG_A
|| curr_state_r == NEG_B
|| curr_state_r == NEG_R);
assign adder_b = adder_neg_op ? { {(width_p-1){1'b0}}, 1'b1}
: opA_r ;
assign adder_result = {1'b0, adder_a} + {1'b0, adder_b};
assign shifted_adder_result = adder_result >> 1;
///////////////////////////////////////////////////////////////////////////////
// control register update logic
wire latch_input = v_i & ready_o;
logic signed_opA_r, signed_opB_r, need_neg_result_r;
wire signed_opA = signed_opA_i & opA_i[width_p-1];
wire signed_opB = signed_opB_i & opB_i[width_p-1];
always_ff@(posedge clk_i ) begin
if( reset_i ) signed_opA_r <= 1'b0;
else if( latch_input ) signed_opA_r <= signed_opA;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) signed_opB_r <= 1'b0;
else if( latch_input ) signed_opB_r <= signed_opB;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) need_neg_result_r <= 1'b0;
else if( latch_input ) need_neg_result_r <= signed_opA ^ signed_opB ;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) gets_high_part_r <= 1'b0;
else if( latch_input ) gets_high_part_r <= gets_high_part_i;
end
///////////////////////////////////////////////////////////////////////////////
// operands update logic
always_ff@(posedge clk_i) begin
if( reset_i ) opA_r <= 'b0;
else if( latch_input ) opA_r <= opA_i;
//opA only shifts when we want low part result
else if(curr_state_r == CALC && (!gets_high_part_r ) )
opA_r <= opA_r << 1 ;
else if(curr_state_r == NEG_A && signed_opA_r) //get the abs(opA)
opA_r <= adder_result[width_p-1:0];
end
always_ff@(posedge clk_i) begin
if( reset_i ) opB_r <= 'b0;
else if( latch_input ) opB_r <= opB_i;
else if(curr_state_r == CALC) opB_r <= opB_r >> 1 ;
else if(curr_state_r == NEG_B && signed_opB_r) //get the abs(opB)
opB_r <= adder_result[width_p-1:0];
end
///////////////////////////////////////////////////////////////////////////////
// track the LSB of the result which is shifted out for high part computation
wire shifted_lsb = opB_r[0] ? adder_result[0] : result_r[0];
logic all_sh_lsb_zero_r;
always_ff@(posedge clk_i ) begin
if( reset_i ) all_sh_lsb_zero_r <= 1'b0;
else if( latch_input ) all_sh_lsb_zero_r <= 1'b1;
else if( curr_state_r == CALC ) all_sh_lsb_zero_r <= all_sh_lsb_zero_r
& (~shifted_lsb);
end
///////////////////////////////////////////////////////////////////////////////
// update the result register
// synopsys sync_set_reset "reset_i, latch_input"
always_ff@(posedge clk_i) begin
if( reset_i ) result_r <= 'b0;
else if( latch_input ) result_r <= 'b0;
else if(curr_state_r == NEG_R && need_neg_result_r) //get the signed result
//1. High part Neg in case Low part are not all zeros
if( gets_high_part_r && !all_sh_lsb_zero_r ) //No cin, just reverse
result_r <= ~result_r;
//1. Low part Neg
//2. High part Neg in case Low part are all zeros, ~(result_r) +1
else
result_r <= adder_result[width_p-1:0];
else if(curr_state_r == CALC && opB_r[0]) begin //get the accumulated result
if( gets_high_part_r ) result_r <= shifted_adder_result[width_p-1:0];
else result_r <= adder_result [width_p-1:0];
end
else if(curr_state_r == CALC && !opB_r[0])begin //No addition
if( gets_high_part_r ) result_r <= result_r >>1 ;
end
end
///////////////////////////////////////////////////////////////////////////////
// the output logic
assign ready_o = ( curr_state_r == IDLE );
assign result_o = result_r;
assign v_o = ( curr_state_r == DONE );
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
// bug291
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer out18;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire out1; // From test of Test.v
wire out19; // From test of Test.v
wire out1b; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out1 (out1),
.out18 (out18),
.out1b (out1b),
.out19 (out19));
// Test loop
always @ (posedge clk) begin
if (out1 !== 1'b1) $stop;
if (out18 !== 32'h18) $stop;
if (out1b !== 1'b1) $stop;
if (out19 !== 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test (
output wire out1 = 1'b1,
output integer out18 = 32'h18,
output var out1b = 1'b1,
output var logic out19 = 1'b1
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A221OI_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
int_ap_ready <= ap_ready;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* $Date: 2011-11-23 16:09:04 -0500 (Wed, 23 Nov 2011) $ *)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** Up to this point, we've been working with lists of numbers.
Of course, interesting programs also need to be able to manipulate
lists whose elements are drawn from other types -- lists of
strings, lists of booleans, lists of lists, etc. We _could_ just
define a new inductive datatype for each of these, for
example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a polymorphic
list datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** So what, exactly, is [list]? One good way to think about it
is that [list] is a _function_ from [Type]s to [Inductive]
definitions; or, to put it another way, [list] is a function from
[Type]s to [Type]s. For any particular type [X], the type [list
X] is an [Inductive]ly defined set of lists whose elements are
things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to specify what type of lists we
are building -- that is, [nil] and [cons] are now _polymorphic
constructors_. Observe the types of these constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types should be read as an
additional argument to the constructors that determines the
expected types of the arguments that follow. When [nil] and
[cons] are used, these arguments are supplied in the same way as
the others. For example, the list containing [2] and [1] is
written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We are writing [nil] and [cons] explicitly here because we
haven't yet defined the [ [] ] and [::] notations. We'll do that
in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: we already know that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. More formally, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors.
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** *** Type Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
Check app.
(** It has exactly the same type type as [app]. Coq was able to
use a procedure called _type inference_ to deduce what the types
of [X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to strike a balance in your own code
between too many type annotations (which serve only to clutter and
distract) and too few (which force the reader to perform type
inference in their head in order to understand your code).
*)
(* ###################################################### *)
(** *** Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type inference -- in fact, the two
procedures rely on the same underlying mechanisms. Instead of
simply omitting the types of some arguments to a function, like
[[
app' X l1 l2 : list X :=
]]
we can also replace the types with [_], like
[[
app' (X : _) (l1 l2 : _) : list X :=
]]
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. *)
Implicit Arguments nil [[X]].
Implicit Arguments cons [[X]].
Implicit Arguments length [[X]].
Implicit Arguments app [[X]].
Implicit Arguments rev [[X]].
Implicit Arguments snoc [[X]].
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** We can also declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length''].) We will use this style
whenever possible, although we will continue to use use explicit
[Implicit Argument] declarations for [Inductive] constructors. *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, if we
write: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x , .. , y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1, 2, 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in [Lists.v], for
practice with polymorphism. Fill in the definitions and complete
the proofs below. *)
Fixpoint repeat (X : Type) (n : X) (count : nat) : list X :=
(* FILL IN HERE *) admit.
Example test_repeat1:
repeat bool true 2 = cons true (cons true nil).
(* FILL IN HERE *) Admitted.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
(* FILL IN HERE *) Admitted.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Implicit Arguments pair [[X] [Y]].
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ consisting of a
pair of values; [X*Y] is a _type_ consisting of a pair of types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type [X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** Indeed, when no ambiguity results, we can even drop the enclosing
parens: *)
Fixpoint combine' {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx,ly with
| [],_ => []
| _,[] => []
| x::tx, y::ty => (x,y) :: (combine' tx ty)
end.
(** **** Exercise: 1 star (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
[[
Eval simpl in (combine [1,2] [false,false,true,true]).
]]
print? []
*)
(** **** Exercise: 2 stars, recommended (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
(*
Fixpoint split
(* FILL IN HERE *)
(* SOON: Argh: this displays totally wrong in the HTML version!!
(The square brackets get dropped.) *)
Example test_split:
split [(1,false),(2,false)] = ([1,2],[false,false]).
Proof. reflexivity. Qed.
*)
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Implicit Arguments Some [[X]].
Implicit Arguments None [[X]].
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4,5,6,7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1],[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
(* FILL IN HERE *) admit.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1,2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_opt2 : hd_opt [[1],[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including,
of course, all _functional languages_ -- Coq treats functions as
first-class citizens, allowing functions to be passed as arguments
to other functions, returned as results, stored in data
structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall that the type of [plus], for instance, is [nat -> nat ->
nat]. *)
Check plus.
(** The [->] is actually a _binary_ operator on types; that is,
Coq primitively supports only one-argument functions. Moreover,
this operator is _right-associative_, so the type of [plus] is
really a shorthand for [nat -> (nat -> nat)] -- i.e., it can be
read as saying that "[plus] is a one-argument function that takes
a [nat] and returns a one-argument function that takes another
[nat] and returns a [nat]." In the examples above, we have always
applied [plus] to both of its arguments at once, but if we like we
can supply just the first. This is called _partial
application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, optional (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
(* FILL IN HERE *) admit.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1,2,3,4] = [2,4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from [Lists.v]. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1,0,3,1,4,5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0,2,4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
This is not an isolated example. When using higher-order
functions, we often want to pass as arguments "one-off" functions
that we will never use again; having to give each of these
functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (filter_even_gt7) *)
(** Use [filter] to write a Coq function [filter_even_gt7] which takes
a list of natural numbers as input and keeps only those numbers
which are even and greater than 7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
(* FILL IN HERE *) admit.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1,2,6,9,10,3,12,8] = [10,12,8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5,2,6,19,129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (partition) *)
(** Use [filter] to write a Coq function [partition]:
[[
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
]]
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(* FILL IN HERE *) admit.
Example test_partition1: partition oddb [1,2,3,4,5] = ([1,3,5], [2,4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5,9,0] = ([], [5,9,0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2,0,2] = [5,3,5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2,1,2,5] = [false,true,false,true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n,oddb n]) [2,1,2,5]
= [[true,false],[false,true],[true,false],[false,true]].
Proof. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, recommended (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
[[
flat_map (fun n => [n,n+1,n+2]) [1,5,10]
= [1, 2, 3, 5, 6, 7, 10, 11, 12].
]]
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
(* FILL IN HERE *) admit.
Example test_flat_map1:
flat_map (fun n => [n,n,n]) [1,5,4]
= [1, 1, 1, 5, 5, 5, 4, 4, 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards. [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called [fold]. It
is the inspiration for the "[reduce]" operation that lies at the
heart of Google's map/reduce distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1,2,3,4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
[[
fold plus [1,2,3,4] 0
]]
yields
[[
1 + (2 + (3 + (4 + 0))).
]]
Here are some more examples:
*)
Check (fold plus).
Eval simpl in (fold plus [1,2,3,4] 0).
Example fold_example1 : fold mult [1,2,3,4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true,true,false,true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1],[],[2,3],[4]] [] = [1,2,3,4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the rest of the chapter. *)
(* ###################################################### *)
(** * More About Coq *)
(* ###################################################### *)
(** ** The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n,o] = [n,p] ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with "[rewrite -> eq2. reflexivity.]"
as we have done several times above. But we can achieve the
same effect in a single step by using the [apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q,o] = [r,p]) ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Admitted.
(** In this case we can use the [symmetry] tactic, which
switches the left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will do a [simpl] step first. *)
apply H. Qed.
(** **** Exercise: 3 stars, recommended (apply_exercise1) *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(** ###################################################### *)
(** ** The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since [plus3 n] is
definitionally equal to [3 + n]. However, Coq doesn't
automatically expand [plus3 n] to its definition. *)
Admitted.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ###################################################### *)
(** ** Inversion *)
(** Recall the definition of natural numbers:
[[
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
]]
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic, called [inversion], that allows us to
exploit these principles in making proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
[[
c a1 a2 ... an = d b1 b2 ... bm
]]
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm].
Then [inversion H] instructs Coq to "invert" this equality to
extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n,m] = [o,o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication, provable by standard equational reasoning, is a
useful fact to record for cases we will see several times. *)
Lemma eq_remove_S : forall n m,
n = m -> S n = S m.
Proof. intros n m eq. rewrite -> eq. reflexivity. Qed.
(** Here is a more realistic use of inversion to prove a
property that is useful in many places later on... *)
Theorem beq_nat_eq : forall n m,
true = beq_nat n m -> n = m.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
intros m. destruct m as [| m'].
SCase "m = 0". reflexivity.
SCase "m = S m'". simpl. intros contra. inversion contra.
Case "n = S n'".
intros m. destruct m as [| m'].
SCase "m = 0". simpl. intros contra. inversion contra.
SCase "m = S m'". simpl. intros H.
apply eq_remove_S. apply IHn'. apply H. Qed.
(** **** Exercise: 2 stars (beq_nat_eq_informal) *)
(** Give an informal proof of [beq_nat_eq]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (beq_nat_eq') *)
(** We can also prove beq_nat_eq by induction on [m], though we have
to be a little careful about which order we introduce the
variables, so that we get a general enough induction hypothesis --
this is done for you below. Finish the following proof. To get
maximum benefit from the exercise, try first to do it without
looking back at the one above. *)
Theorem beq_nat_eq' : forall m n,
beq_nat n m = true -> n = m.
Proof.
intros m. induction m as [| m'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Here's another illustration of [inversion]. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []". intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'". intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply eq_remove_S. apply IHl'. inversion eq. reflexivity. Qed.
(* ###################################################### *)
(** *** Practice Session *)
(** **** Exercise: 2 stars, optional (practice) *)
(** Some nontrivial but not-too-complicated proofs to work together in
class, and some for you to work as exercises. Some of the
exercises may involve applying lemmas from earlier lectures or
homeworks. *)
Theorem beq_nat_0_l : forall n,
true = beq_nat 0 n -> 0 = n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_0_r : forall n,
true = beq_nat n 0 -> 0 = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* WORKED IN CLASS *)
Case "n = 0". simpl. intros m eq. destruct m as [| m'].
SCase "m = 0". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros m eq. destruct m as [| m'].
SCase "m = 0". inversion eq.
SCase "m = S m'".
apply eq_remove_S. apply IHn'. inversion eq. reflexivity. Qed.
(* ###################################################### *)
(** ** Varying the Induction Hypothesis *)
(** One subtlety in the inductive proofs above is worth noticing here.
For example, look back at the proof of the [app_ass] theorem. The
induction hypothesis (in the second subgoal generated by the
[induction] tactic) is
[ (l1' ++ l2) ++ l3 = l1' ++ l2 ++ l3 ].
(Note that, because we've defined [++] to be right associative,
the expression on the right of the [=] is the same as writing [l1'
++ (l2 ++ l3)].)
This hypothesis makes a statement about [l1'] together with the
_particular_ lists [l2] and [l3]. The lists [l2] and [l3], which
were introduced into the context by the [intros] at the top of the
proof, are "held constant" in the induction hypothesis. If we set
up the proof slightly differently by introducing just [n] into the
context at the top, then we get an induction hypothesis that makes
a stronger claim:
[ forall l2 l3, (l1' ++ l2) ++ l3 = l1' ++ l2 ++ l3 ]
Use Coq to see the difference for yourself.
In the present case, the difference between the two proofs is
minor, since the definition of the [++] function just examines its
first argument and doesn't do anything interesting with its second
argument. But we'll soon come to situations where setting up the
induction hypothesis one way or the other can make the difference
between a proof working and failing. *)
(** **** Exercise: 2 stars, optional (app_ass') *)
(** Give an alternate proof of the associativity of [++] with a more
general induction hypothesis. Complete the following (leaving the
first line unchanged). *)
Theorem app_ass' : forall l1 l2 l3 : list nat,
(l1 ++ l2) ++ l3 = l1 ++ (l2 ++ l3).
Proof.
intros l1. induction l1 as [ | n l1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (apply_exercise2) *)
(** In the following proof opening, notice that we don't introduce [m]
before performing induction. This leaves it general, so that the
IH doesn't specify a particular [m], but lets us pick. Finish the
proof. *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n. induction n as [| n'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (beq_nat_sym_informal) *)
(** Provide an informal proof of this lemma that corresponds
to your formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(* ###################################################### *)
(** ** Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars, recommended (plus_n_n_injective) *)
(** You can practice using the "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases. *)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (combine_split) *)
(*
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l. induction l as [| [x y] l'].
(* FILL IN HERE *) Admitted.
*)
(** [] *)
(** **** Exercise: 3 stars, optional (split_combine) *)
(** Thought exercise: We have just proven that for all lists of pairs,
[combine] is the inverse of [split]. How would you state the
theorem showing that [split] is the inverse of [combine]?
Hint: what property do you need of [l1] and [l2] for [split]
[combine l1 l2 = (l1,l2)] to be true?
State this theorem in Coq, and prove it. (Be sure to leave your
induction hypothesis general by not doing [intros] on more things
than necessary.) *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################### *)
(** ** The [remember] Tactic *)
(** (Note: the [remember] tactic is not strictly needed until a
bit later, so if necessary this section can be skipped and
returned to when needed.) *)
(** We have seen how the [destruct] tactic can be used to
perform case analysis of the results of arbitrary computations.
If [e] is an expression whose type is some inductively defined
type [T], then, for each constructor [c] of [T], [destruct e]
generates a subgoal in which all occurrences of [e] (in the goal
and in the context) are replaced by [c].
Sometimes, however, this substitution process loses information
that we need in order to complete the proof. For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Admitted.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep at
least one of these because we need to be able to reason that
since, in this branch of the case analysis, [beq_nat n 3 = true],
it must be that [n = 3], from which it follows that [n] is odd.
What we would really like is not to use [destruct] directly on
[beq_nat n 3] and substitute away all occurrences of this
expression, but rather to use [destruct] on something else that is
_equal_ to [beq_nat n 3]. For example, if we had a variable that
we knew was equal to [beq_nat n 3], we could [destruct] this
variable instead.
The [remember] tactic allows us to introduce such a variable. *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
remember (beq_nat n 3) as e3.
(* At this point, the context has been enriched with a new
variable [e3] and an assumption that [e3 = beq_nat n 3].
Now if we do [destruct e3]... *)
destruct e3.
(* ... the variable [e3] gets substituted away (it
disappears completely) and we are left with the same
state as at the point where we got stuck above, except
that the context still contains the extra equality
assumption -- now with [true] substituted for [e3] --
which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_eq in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the
body of the function we are reasoning about, we can
use [remember] again in the same way, allowing us
to finish the proof. *)
remember (beq_nat n 5) as e5. destruct e5.
SCase "e5 = true".
apply beq_nat_eq in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall {X:Type} x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (filter_exercise) *)
(** This one is a bit challenging. Be sure your initial [intros] go
only up through the parameter on which you want to do
induction! *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall {X:Type} (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c,d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: apply trans_eq with [c,d]. *)
(** **** Exercise: 3 stars, recommended (apply_exercises) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_trans : forall n m p,
true = beq_nat n m ->
true = beq_nat m p ->
true = beq_nat n p.
Proof.
(* FILL IN HERE *) Admitted.
Theorem override_permute : forall {X:Type} x1 x2 k1 k2 k3 (f : nat->X),
false = beq_nat k2 k1 ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics -- enough to
do pretty much everything we'll want for a while. We'll introduce
one or two more as we go along through the next few lectures, and
later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [remember (e) as x]:
give a name ([x]) to an expression ([e]) so that we can
destruct [x] without "losing" [e]
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternate definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4,7,0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
(* FILL IN HERE *) admit.
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
(* FILL IN HERE *)
(** [] *)
Module MumbleBaz.
(** **** Exercise: 2 stars, optional (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
[] *)
(** **** Exercise: 2 stars, optional (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
[] *)
End MumbleBaz.
(** **** Exercise: 4 stars, recommended (forall_exists_challenge) *)
(** Challenge problem: Define two recursive [Fixpoints],
[forallb] and [existsb]. The first checks whether every
element in a list satisfies a given predicate:
[[
forallb oddb [1,3,5,7,9] = true
forallb negb [false,false] = true
forallb evenb [0,2,4,5] = false
forallb (beq_nat 5) [] = true
]]
The function [existsb] checks whether there exists an element in
the list that satisfies a given predicate:
[[
existsb (beq_nat 5) [0,2,3,6] = false
existsb (andb true) [true,true,false] = true
existsb oddb [1,0,0,0,0,3] = true
existsb evenb [] = false
]]
Next, create a _nonrecursive_ [Definition], [existsb'], using
[forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (index_informal) *)
(** Recall the definition of the [index] function:
[[
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
]]
Write an informal proof of the following theorem:
[[
forall X n l, length l = n -> @index X (S n) l = None.
]]
(* FILL IN HERE *)
*)
(** [] *)
|
// -*- Mode: Verilog -*-
// Filename : cpu_wrapper.v
// Description : Wrapper around WishBone based CPUs
// Author : Philip Tracton
// Created On : Sun Jul 24 20:57:15 2016
// Last Modified By: Philip Tracton
// Last Modified On: Sun Jul 24 20:57:15 2016
// Update Count : 0
// Status : Unknown, Use with caution!
//`include "wb_soc_includes.vh"
module wishbone_cpu (/*AUTOARG*/
// Outputs
iwbm_adr_o, iwbm_stb_o, iwbm_cyc_o, iwbm_sel_o, iwbm_we_o,
iwbm_cti_o, iwbm_bte_o, iwbm_dat_o, dwbm_adr_o, dwbm_stb_o,
dwbm_cyc_o, dwbm_sel_o, dwbm_we_o, dwbm_cti_o, dwbm_bte_o,
dwbm_dat_o, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
dbg_ack_o,
// Inputs
clk_i, rst_i, interrupts, iwbm_err_i, iwbm_ack_i, iwbm_dat_i,
iwbm_rty_i, dwbm_err_i, dwbm_ack_i, dwbm_dat_i, dwbm_rty_i,
dbg_stall_i, dbg_ewt_i, dbg_stb_i, dbg_we_i, dbg_sel_i, dbg_cti_i,
dbg_bte_i, dbg_lock_i, dbg_cyc_i, dbg_adr_i, dbg_dat_i
) ;
parameter NUMBER_OF_INTERRUPTS = 32;
parameter ADDRESS_WIDTH = 32;
parameter DATA_WIDTH = 32;
//
// System Interface
//
input wire clk_i;
input wire rst_i;
input wire [NUMBER_OF_INTERRUPTS-1:0] interrupts;
//
// Instruction Bus
//
output wire [ADDRESS_WIDTH-1:0] iwbm_adr_o;
output wire iwbm_stb_o;
output wire iwbm_cyc_o;
output wire [3:0] iwbm_sel_o;
output wire iwbm_we_o;
output wire [2:0] iwbm_cti_o;
output wire [1:0] iwbm_bte_o;
output wire [DATA_WIDTH-1:0] iwbm_dat_o;
input wire iwbm_err_i;
input wire iwbm_ack_i;
input wire [DATA_WIDTH-1:0] iwbm_dat_i;
input wire iwbm_rty_i;
//
// Data Bus
//
output wire [ADDRESS_WIDTH-1:0] dwbm_adr_o;
output wire dwbm_stb_o;
output wire dwbm_cyc_o;
output wire [3:0] dwbm_sel_o;
output wire dwbm_we_o;
output wire [2:0] dwbm_cti_o;
output wire [1:0] dwbm_bte_o;
output wire [DATA_WIDTH-1:0] dwbm_dat_o;
input wire dwbm_err_i;
input wire dwbm_ack_i;
input wire [DATA_WIDTH-1:0] dwbm_dat_i;
input wire dwbm_rty_i;
//
// Debug interface
//
input wire dbg_stall_i; // External Stall Input
input wire dbg_ewt_i; // External Watchpoint Trigger Input
output wire [3:0] dbg_lss_o; // External Load/Store Unit Status
output wire [1:0] dbg_is_o; // External Insn Fetch Status
output wire [10:0] dbg_wp_o; // Watchpoints Outputs
output wire dbg_bp_o; // Breakpoint Output
input wire dbg_stb_i; // External Address/Data Strobe
input wire dbg_we_i; // External Write Enable
input wire dbg_sel_i; //Debug select
input wire [2:0] dbg_cti_i;//
input wire dbg_bte_i;//
input wire dbg_lock_i;
input wire dbg_cyc_i;
input wire [ADDRESS_WIDTH-1:0] dbg_adr_i; // External Address Input
input wire [DATA_WIDTH-1:0] dbg_dat_i; // External Data Input
output wire [DATA_WIDTH-1:0] dbg_dat_o; // External Data Output
output wire dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef WISHBONE_CPU_LM32
`include "lm32_config.v"
assign dbg_cti_i = 3'b000;
initial begin
$display("INSTANTIATE LM32 CPU");
end
lm32_top cpu(
// ----- Inputs -------
.clk_i(clk_i),
.rst_i(rst_i),
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
.at_debug(),
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
.interrupt(interrupts),
`endif
// From user logic
`ifdef CFG_USER_ENABLED
.user_result(),
.user_complete(),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_I(iwbm_dat_i),
.I_ACK_I(iwbm_ack_i),
.I_ERR_I(iwbm_err_i),
.I_RTY_I(iwbm_rty_i),
`endif
// Data Wishbone master
.D_DAT_I(dwbm_dat_i),
.D_ACK_I(dwbm_ack_i),
.D_ERR_I(dwbm_err_i),
.D_RTY_I(dwbm_rty_i),
// ----- Outputs -------
`ifdef CFG_USER_ENABLED
.user_valid(),
.user_opcode(),
.user_operand_0(),
.user_operand_1(),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_O(iwbm_dat_o),
.I_ADR_O(iwbm_adr_o),
.I_CYC_O(iwbm_cyc_o),
.I_SEL_O(iwbm_sel_o),
.I_STB_O(iwbm_stb_o),
.I_WE_O(iwbm_we_o),
.I_CTI_O(iwbm_cti_o),
.I_LOCK_O(),
.I_BTE_O(iwbm_bte_o),
`endif
// Data Wishbone master
.D_DAT_O(dwbm_dat_o),
.D_ADR_O(dwbm_adr_o),
.D_CYC_O(dwbm_cyc_o),
.D_SEL_O(dwbm_sel_o),
.D_STB_O(dwbm_stb_o),
.D_WE_O(dwbm_we_o),
.D_CTI_O(dwbm_cti_o),
.D_LOCK_O(),
.D_BTE_O(dwbm_bte_o)
);
`elsif WISHBONE_CPU_MOR1KX
initial begin
$display("INSTANTIATE MOR1K CPU");
end
mor1kx cpu(
.clk(clk_i),
.rst(rst_i),
// Wishbone interface
.iwbm_adr_o(iwbm_adr_o),
.iwbm_stb_o(iwbm_stb_o),
.iwbm_cyc_o(iwbm_cyc_o),
.iwbm_sel_o(iwbm_sel_o),
.iwbm_we_o(iwbm_we_o),
.iwbm_cti_o(iwbm_cti_o),
.iwbm_bte_o(iwbm_bte_o),
.iwbm_dat_o(iwbm_dat_o),
.iwbm_err_i(iwbm_err_i),
.iwbm_ack_i(iwbm_ack_i),
.iwbm_dat_i(iwbm_dat_i),
.iwbm_rty_i(iwbm_rty_i),
.dwbm_adr_o(dwbm_adr_o),
.dwbm_stb_o(dwbm_stb_o),
.dwbm_cyc_o(dwbm_cyc_o),
.dwbm_sel_o(dwbm_sel_o),
.dwbm_we_o(dwbm_we_o),
.dwbm_cti_o(dwbm_cti_o),
.dwbm_bte_o(dwbm_bte_o),
.dwbm_dat_o(dwbm_dat_o),
.dwbm_err_i(dwbm_err_i),
.dwbm_ack_i(dwbm_ack_i),
.dwbm_dat_i(dwbm_dat_i),
.dwbm_rty_i(dwbm_rty_i),
.irq_i(interrupts),
// Debug interface
.du_addr_i('b0),
.du_stb_i('b0),
.du_dat_i('b0),
.du_we_i('b0),
.du_dat_o(),
.du_ack_o(),
// Stall control from debug interface
.du_stall_i('b0),
.du_stall_o(),
.traceport_exec_valid_o(),
.traceport_exec_pc_o(),
.traceport_exec_insn_o(),
.traceport_exec_wbdata_o(),
.traceport_exec_wbreg_o(),
.traceport_exec_wben_o(),
// The multicore core identifier
.multicore_coreid_i('b0),
// The number of cores
.multicore_numcores_i('b0),
.snoop_adr_i('b0),
.snoop_en_i('b0)
);
`elsif WISHBONE_CPU_OR1200
`include "or1200_defines.v"
initial begin
$display("INSTANTIATE OR1200 CPU");
end
or1200_top cpu(
// System
.clk_i(clk_i),
.rst_i(rst_i),
.pic_ints_i(interrupts),
.clmode_i(2'b00), //WB=RISC
// Instruction WISHBONE INTERFACE
.iwb_clk_i(clk_i),
.iwb_rst_i(rst_i),
.iwb_ack_i(iwbm_ack_i),
.iwb_err_i(iwbm_err_i),
.iwb_rty_i(iwbm_rty_i),
.iwb_dat_i(iwbm_dat_i),
.iwb_cyc_o(iwbm_cyc_o),
.iwb_adr_o(iwbm_adr_o),
.iwb_stb_o(iwbm_stb_o),
.iwb_we_o(iwbm_we_o),
.iwb_sel_o(iwbm_sel_o),
.iwb_dat_o(iwbm_dat_o),
`ifdef OR1200_WB_CAB
.iwb_cab_o(),
`endif
`ifdef OR1200_WB_B3
.iwb_cti_o(iwbm_cti_o),
.iwb_bte_o(iwbm_bte_o),
`endif
// Data WISHBONE INTERFACE
.dwb_clk_i(clk_i),
.dwb_rst_i(rst_i),
.dwb_ack_i(dwbm_ack_i),
.dwb_err_i(dwbm_err_i),
.dwb_rty_i(dwbm_rty_i),
.dwb_dat_i(dwbm_dat_i),
.dwb_cyc_o(dwbm_cyc_o),
.dwb_adr_o(dwbm_adr_o),
.dwb_stb_o(dwbm_stb_o),
.dwb_we_o(dwbm_we_o),
.dwb_sel_o(dwbm_sel_o),
.dwb_dat_o(dwbm_dat_o),
`ifdef OR1200_WB_CAB
.dwb_cab_o(),
`endif
`ifdef OR1200_WB_B3
.dwb_cti_o(dwbm_cti_o),
.dwb_bte_o(dwbm_bte_o),
`endif
// External Debug Interface
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_adr_o),
.dbg_ack_o(dbg_ack_o),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i('b0),
.mbist_so_o(),
.mbist_ctrl_i('b0),
`endif
// Power Management
.pm_cpustall_i('b0),
.pm_clksd_o(),
.pm_dc_gate_o(),
.pm_ic_gate_o(),
.pm_dmmu_gate_o(),
.pm_immu_gate_o(),
.pm_tt_gate_o(),
.pm_cpu_gate_o(),
.pm_wakeup_o(),
.pm_lvolt_o()
,.sig_tick()
);
`elsif WISHBONE_CPU_RISCV
initial begin
$display("INSTANTIATE RISCV CPU");
end
wire [ADDRESS_WIDTH-1:0] rv_wbm_adr_o;
wire rv_wbm_stb_o;
wire rv_wbm_cyc_o;
wire [3:0] rv_wbm_sel_o;
wire rv_wbm_we_o;
wire [2:0] rv_wbm_cti_o;
wire [1:0] rv_wbm_bte_o;
wire [DATA_WIDTH-1:0] rv_wbm_dat_o;
wire rv_wbm_err_i;
wire rv_wbm_ack_i;
wire [DATA_WIDTH-1:0] rv_wbm_dat_i;
wire rv_wbm_rty_i;
wire [31:0] end_of_interrupt;
wire mem_instr;
//
// picorv32 has a single WB interface. Our design has 2. The mem_instr signal indicates if we are fetching
// an instruction (iwbm) or data (dwbm).
//
assign iwbm_adr_o = ( mem_instr) ? rv_wbm_adr_o : 32'b0;
assign dwbm_adr_o = (!mem_instr) ? rv_wbm_adr_o : 32'b0;
assign iwbm_dat_o = ( mem_instr) ? rv_wbm_dat_o : 32'b0;
assign dwbm_dat_o = (!mem_instr) ? rv_wbm_dat_o : 32'b0;
assign iwbm_stb_o = ( mem_instr) ? rv_wbm_stb_o : 1'b0;
assign dwbm_stb_o = (!mem_instr) ? rv_wbm_stb_o : 1'b0;
assign iwbm_cyc_o = ( mem_instr) ? rv_wbm_cyc_o : 1'b0;
assign dwbm_cyc_o = (!mem_instr) ? rv_wbm_cyc_o : 1'b0;
assign iwbm_sel_o = ( mem_instr) ? rv_wbm_sel_o : 1'b0;
assign dwbm_sel_o = (!mem_instr) ? rv_wbm_sel_o : 4'b0;
assign iwbm_cti_o = 3'b0;
assign dwbm_cti_o = 3'b0;
assign iwbm_bte_o = 2'b0;
assign dwbm_bte_o = 2'b0;
assign rv_wbm_dat_i = ( mem_instr) ? iwbm_dat_i : dwbm_dat_i;
assign rv_wbm_err_i = ( mem_instr) ? iwbm_err_i : dwbm_err_i;
assign rv_wbm_ack_i = ( mem_instr) ? iwbm_ack_i : dwbm_ack_i;
assign rv_wbm_rty_i = ( mem_instr) ? iwbm_rty_i : dwbm_rty_i;
picorv32_wb cpu(
.trap(),
// Wishbone interfaces
.wb_rst_i(rst_i),
.wb_clk_i(clk_i),
.wbm_adr_o(rv_wbm_adr_o),
.wbm_dat_o(rv_wbm_dat_o),
.wbm_dat_i(rv_wbm_dat_i),
.wbm_we_o (rv_wbm_we_o ),
.wbm_sel_o(rv_wbm_sel_o),
.wbm_stb_o(rv_wbm_stb_o),
.wbm_ack_i(rv_wbm_ack_i),
.wbm_cyc_o(rv_wbm_cyc_o),
// Pico Co-Processor Interface (PCPI)
.pcpi_valid(),
.pcpi_insn(),
.pcpi_rs1(),
.pcpi_rs2(),
.pcpi_wr(1'b0),
.pcpi_rd(32'b0),
.pcpi_wait(1'b0),
.pcpi_ready(1'b0),
// IRQ interface
.irq(interrupts),
.eoi(end_of_interrupt),
// Trace Interface
.trace_valid(),
.trace_data(),
.mem_instr(mem_instr)
);
`elsif WISHBONE_CPU_ZIP
//
// ZIP has a single WB interface, this design assumes 2
//
wire z_inst_or_data;
wire [29:0] zwbm_adr_o;
wire [DATA_WIDTH-1:0] zwbm_dat_o;
wire zwbm_cyc_o;
wire [3:0] zwbm_sel_o;
wire zwbm_we_o;
wire zwbm_stb_o;
wire zwbm_err_i;
wire zwbm_ack_i;
wire [DATA_WIDTH-1:0] zwbm_dat_i;
wire zwbm_rty_i;
`define ZWBM_INSTR_ADDR_START 32'h00000000
`define ZWBM_INSTR_ADDR_END 32'h00001000
//Determine if this is a instruction or data access
/* -----\/----- EXCLUDED -----\/-----
assign z_inst_or_data = ((zwbm_adr_o >= `ZWBM_INSTR_ADDR_START) && (zwbm_adr_o <`ZWBM_INSTR_ADDR_END));
assign iwbm_adr_o = (z_inst_or_data) ? {2'b00, zwbm_adr_o} : 32'h0;
assign iwbm_dat_o = (z_inst_or_data) ? zwbm_dat_o : 32'h0;
assign iwbm_stb_o = (z_inst_or_data) ? zwbm_stb_o : 0;
assign iwbm_cyc_o = (z_inst_or_data) ? zwbm_cyc_o : 0;
assign iwbm_sel_o = (z_inst_or_data) ? zwbm_sel_o : 0;
assign iwbm_we_o = (z_inst_or_data) ? zwbm_we_o : 0;
assign zwbm_err_i = (z_inst_or_data) ? iwbm_err_i : dwbm_err_i;
assign zwbm_ack_i = (z_inst_or_data) ? iwbm_ack_i : dwbm_ack_i;
assign zwbm_rty_i = (z_inst_or_data) ? iwbm_rty_i : dwbm_rty_i;
assign zwbm_dat_i = (z_inst_or_data) ? iwbm_dat_i : dwbm_dat_i;
assign dwbm_adr_o = (!z_inst_or_data) ? {2'b00,zwbm_adr_o} : 32'h0;
assign dwbm_dat_o = (!z_inst_or_data) ? zwbm_dat_o : 32'h0;
assign dwbm_stb_o = (!z_inst_or_data) ? zwbm_stb_o : 0;
assign dwbm_cyc_o = (!z_inst_or_data) ? zwbm_cyc_o : 0;
assign dwbm_sel_o = (!z_inst_or_data) ? zwbm_sel_o : 0;
assign dwbm_we_o = (!z_inst_or_data) ? zwbm_we_o : 0;
assign dwbm_bte_o = 2'b0;
assign dwbm_cti_o = 3'b0;
-----/\----- EXCLUDED -----/\----- */
assign iwbm_adr_o[31:30] = 2'b00;
assign iwbm_bte_o = 2'b0;
assign iwbm_cti_o = 3'b0;
assign dwbm_adr_o = 32'h0;
assign dwbm_dat_o = 32'h0;
assign dwbm_stb_o = 0;
assign dwbm_cyc_o = 0;
assign dwbm_sel_o = 0;
assign dwbm_we_o = 0;
assign dwbm_bte_o = 2'b0;
assign dwbm_cti_o = 3'b0;
wire lcl_cyc;
wire lcl_stb;
zipcpu #(.RESET_ADDRESS(`ZWBM_INSTR_ADDR_START))
cpu(
.i_clk(clk_i),
.i_rst(rst_i),
.i_interrupt(),
// Debug interface
.i_halt(1'b0),
.i_clear_pf_cache(1'b0),
.i_dbg_reg(5'b0),
.i_dbg_we(1'b0),
.i_dbg_data(32'b0),
.o_dbg_stall(),
.o_dbg_reg(),
.o_dbg_cc(),
.o_break(),
// CPU interface to the wishbone bus
.o_wb_gbl_cyc(iwbm_cyc_o),
.o_wb_gbl_stb(iwbm_stb_o),
.o_wb_lcl_cyc(lcl_cyc),
.o_wb_lcl_stb(lcl_stb),
.o_wb_we(iwbm_we_o),
.o_wb_addr(iwbm_adr_o[29:0]),
.o_wb_data(iwbm_dat_o),
.o_wb_sel(iwbm_sel_o),
.i_wb_ack(iwbm_ack_i),
.i_wb_stall(iwbm_rty_i),
.i_wb_data(iwbm_dat_i),
.i_wb_err(iwbm_err_i),
// Accounting/CPU usage interface
.o_op_stall(),
.o_pf_stall(),
.o_i_count()
`ifdef DEBUG_SCOPE
, o_debug()
`endif
);
`endif // !`elsif WISHBONE_CPU_RISCV
endmodule // wishbone_cpu
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(clk, rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_565[15:0],rgb_888[23:0]" */;
input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// This example describes a 16x1 RAM that can be synthesized into
// a CLB ram in a Xilinx FPGA.
module ram16x1 (q, d, a, we, wclk);
output q;
input d;
input [3:0] a;
input we;
input wclk;
reg mem[15:0];
assign q = mem[a];
always @(posedge wclk) if (we) mem[a] = d;
endmodule /* ram16x1 */
module main;
wire q;
reg d;
reg [3:0] a;
reg we, wclk;
ram16x1 r1 (q, d, a, we, wclk);
initial begin
wclk = 0;
we = 1;
for (a = 0 ; a < 4'hf ; a = a + 1) begin
d = a[0];
#1 wclk = 1;
#1 wclk = 0;
$display("r1[%h] == %b", a, q);
end
for (a = 0 ; a < 4'hf ; a = a + 1)
#1 if (q !== a[0]) begin
$display("FAILED -- mem[%h] !== %b", a, a[0]);
$finish;
end
$display("PASSED");
end
endmodule /* main */
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter2.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter2();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter2 pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#19
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:23:12 08/15/2011
// Design Name:
// Module Name: RCB_FRL_RX_Data_FIFO_8bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RX_Data_FIFO_8bit(
input RDCLK,
input RDEN,
input WRCLK,
input WREN,
input RST,
input [7:0] DI,
output ALMOSTEMPTY,
output ALMOSTFULL,
output EMPTY,
output FULL,
output [7:0] DO
);
wire [7:0] temp1;
FIFO18 FIFO18_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
.DO({temp1, DO[7:0]}), // 16-bit data output
.DOP(), // 2-bit parity data output
.EMPTY(EMPTY), // 1-bit empty output flag
.FULL(FULL), // 1-bit full output flag
.RDCOUNT(), // 12-bit read count output
.RDERR(), // 1-bit read error output
.WRCOUNT(), // 12-bit write count output
.WRERR(), // 1-bit write error
.DI({8'h0,DI[7:0]}), // 16-bit data input
.DIP(), // 2-bit parity input
.RDCLK(RDCLK), // 1-bit read clock input
.RDEN(RDEN), // 1-bit read enable input
.RST(RST), // 1-bit reset input
.WRCLK(WRCLK), // 1-bit write clock input
.WREN(WREN) // 1-bit write enable input
);
defparam FIFO18_inst.DATA_WIDTH = 9;
defparam FIFO18_inst.ALMOST_EMPTY_OFFSET = 6;
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 13.1 cbx_altiobuf_out 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratixiii 2013:10:24:09:15:20:SJ cbx_stratixv 2013:10:24:09:15:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable Setoid DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecide_fun (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts_fun E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Export Decidable.
Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isn't decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
Ltac abstract_term t :=
tryif (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
#[global]
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
tryif (change T with E.t in H) then fail
else tryif (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
tryif prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Global Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Global Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
#[global]
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substFSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_FSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
tryif prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide_fun.
Require Import FSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WS) := !WDecide_fun M.E M.
Module Decide := WDecide.
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
/* */
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
end else
if(WIDTH == 3) begin
LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
end else
if(WIDTH == 4) begin
LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
// $Id: c_tree_arbiter.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic tree arbiter
module c_tree_arbiter
(clk, reset, update, req, gnt);
`include "c_constants.v"
// number of input ports
parameter num_ports = 16;
// number of blocks in first stage of arbitration
parameter num_blocks = 4;
// number of inputs to each first-stage arbiter
localparam ports_per_block = num_ports / num_blocks;
// select arbiter variant to use
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// update port priorities
input update;
// request vector
input [0:num_ports-1] req;
// grant vector
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
// effective second-stage request vector
wire [0:num_blocks-1] stg2_req;
// second-stage grant vector
wire [0:num_blocks-1] stg2_gnt;
generate
// first stage of arbitration: one arbiter per group
genvar i;
for(i = 0; i < num_blocks; i = i + 1)
begin:blocks
wire [0:ports_per_block-1] stg1_req;
assign stg1_req = req[i*ports_per_block:(i+1)*ports_per_block-1];
assign stg2_req[i] = |stg1_req;
wire [0:ports_per_block-1] stg1_gnt;
c_arbiter
#(.num_ports(ports_per_block),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
stg1_arb
(.clk(clk),
.reset(reset),
.update(update),
.req(stg1_req),
.gnt(stg1_gnt));
assign gnt[i*ports_per_block:(i+1)*ports_per_block-1]
= {ports_per_block{stg2_gnt[i]}} & stg1_gnt;
end
endgenerate
// second stage of arbitration: arbitrate between all groups
c_arbiter
#(.num_ports(num_blocks),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
stg2_arb
(.clk(clk),
.reset(reset),
.update(update),
.req(stg2_req),
.gnt(stg2_gnt));
endmodule
|
/* $Id: aeMB_edk32.v,v 1.14 2008-01-19 16:01:22 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[email protected]>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
*/
module aeMB_edk32 (/*AUTOARG*/
// Outputs
iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
// Inputs
sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
dwb_ack_i, sys_clk_i, sys_rst_i
);
// Bus widths
parameter IW = 32; /// Instruction bus address width
parameter DW = 32; /// Data bus address width
// Optional functions
parameter MUL = 0; // Multiplier
parameter BSF = 1; // Barrel Shifter
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v
output dwb_stb_o; // From ctrl of aeMB_ctrl.v
output dwb_wre_o; // From ctrl of aeMB_ctrl.v
output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v
output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
output fsl_stb_o; // From ctrl of aeMB_ctrl.v
output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v
output fsl_wre_o; // From ctrl of aeMB_ctrl.v
output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
output iwb_stb_o; // From ibuf of aeMB_ibuf.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dwb_ack_i; // To ctrl of aeMB_ctrl.v
input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
input fsl_ack_i; // To ctrl of aeMB_ctrl.v
input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...
input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
input sys_int_i; // To ibuf of aeMB_ibuf.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
wire rBRA; // From bpcu of aeMB_bpcu.v
wire rDLY; // From bpcu of aeMB_bpcu.v
wire [31:0] rDWBDI; // From regf of aeMB_regf.v
wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
wire rMSR_BIP; // From xecu of aeMB_xecu.v
wire rMSR_IE; // From xecu of aeMB_xecu.v
wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v
wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v
wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v
wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v
wire [31:2] rPC; // From bpcu of aeMB_bpcu.v
wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v
wire [4:0] rRA; // From ibuf of aeMB_ibuf.v
wire [4:0] rRB; // From ibuf of aeMB_ibuf.v
wire [4:0] rRD; // From ibuf of aeMB_ibuf.v
wire [31:0] rREGA; // From regf of aeMB_regf.v
wire [31:0] rREGB; // From regf of aeMB_regf.v
wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
wire rSTALL; // From ibuf of aeMB_ibuf.v
wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
// End of automatics
input sys_clk_i;
input sys_rst_i;
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
// --- INSTANTIATIONS -------------------------------------
aeMB_ibuf
ibuf (/*AUTOINST*/
// Outputs
.rIMM (rIMM[15:0]),
.rRA (rRA[4:0]),
.rRD (rRD[4:0]),
.rRB (rRB[4:0]),
.rALT (rALT[10:0]),
.rOPC (rOPC[5:0]),
.rSIMM (rSIMM[31:0]),
.xIREG (xIREG[31:0]),
.rSTALL (rSTALL),
.iwb_stb_o (iwb_stb_o),
// Inputs
.rBRA (rBRA),
.rMSR_IE (rMSR_IE),
.rMSR_BIP (rMSR_BIP),
.iwb_dat_i (iwb_dat_i[31:0]),
.iwb_ack_i (iwb_ack_i),
.sys_int_i (sys_int_i),
.gclk (gclk),
.grst (grst),
.gena (gena),
.oena (oena));
aeMB_ctrl
ctrl (/*AUTOINST*/
// Outputs
.rMXDST (rMXDST[1:0]),
.rMXSRC (rMXSRC[1:0]),
.rMXTGT (rMXTGT[1:0]),
.rMXALT (rMXALT[1:0]),
.rMXALU (rMXALU[2:0]),
.rRW (rRW[4:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_wre_o (dwb_wre_o),
.fsl_stb_o (fsl_stb_o),
.fsl_wre_o (fsl_wre_o),
// Inputs
.rDLY (rDLY),
.rIMM (rIMM[15:0]),
.rALT (rALT[10:0]),
.rOPC (rOPC[5:0]),
.rRD (rRD[4:0]),
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rPC (rPC[31:2]),
.rBRA (rBRA),
.rMSR_IE (rMSR_IE),
.xIREG (xIREG[31:0]),
.dwb_ack_i (dwb_ack_i),
.iwb_ack_i (iwb_ack_i),
.fsl_ack_i (fsl_ack_i),
.gclk (gclk),
.grst (grst),
.gena (gena));
aeMB_bpcu #(IW)
bpcu (/*AUTOINST*/
// Outputs
.iwb_adr_o (iwb_adr_o[IW-1:2]),
.rPC (rPC[31:2]),
.rPCLNK (rPCLNK[31:2]),
.rBRA (rBRA),
.rDLY (rDLY),
// Inputs
.rMXALT (rMXALT[1:0]),
.rOPC (rOPC[5:0]),
.rRD (rRD[4:0]),
.rRA (rRA[4:0]),
.rRESULT (rRESULT[31:0]),
.rDWBDI (rDWBDI[31:0]),
.rREGA (rREGA[31:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
aeMB_regf
regf (/*AUTOINST*/
// Outputs
.rREGA (rREGA[31:0]),
.rREGB (rREGB[31:0]),
.rDWBDI (rDWBDI[31:0]),
.dwb_dat_o (dwb_dat_o[31:0]),
.fsl_dat_o (fsl_dat_o[31:0]),
// Inputs
.rOPC (rOPC[5:0]),
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rRW (rRW[4:0]),
.rRD (rRD[4:0]),
.rMXDST (rMXDST[1:0]),
.rPCLNK (rPCLNK[31:2]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rBRA (rBRA),
.rDLY (rDLY),
.dwb_dat_i (dwb_dat_i[31:0]),
.fsl_dat_i (fsl_dat_i[31:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
aeMB_xecu #(DW, MUL, BSF)
xecu (/*AUTOINST*/
// Outputs
.dwb_adr_o (dwb_adr_o[DW-1:2]),
.dwb_sel_o (dwb_sel_o[3:0]),
.fsl_adr_o (fsl_adr_o[6:2]),
.fsl_tag_o (fsl_tag_o[1:0]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rMSR_IE (rMSR_IE),
.rMSR_BIP (rMSR_BIP),
// Inputs
.rREGA (rREGA[31:0]),
.rREGB (rREGB[31:0]),
.rMXSRC (rMXSRC[1:0]),
.rMXTGT (rMXTGT[1:0]),
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rMXALU (rMXALU[2:0]),
.rBRA (rBRA),
.rDLY (rDLY),
.rALT (rALT[10:0]),
.rSTALL (rSTALL),
.rSIMM (rSIMM[31:0]),
.rIMM (rIMM[15:0]),
.rOPC (rOPC[5:0]),
.rRD (rRD[4:0]),
.rDWBDI (rDWBDI[31:0]),
.rPC (rPC[31:2]),
.gclk (gclk),
.grst (grst),
.gena (gena));
endmodule // aeMB_edk32
/*
$Log: not supported by cvs2svn $
Revision 1.13 2007/12/25 22:15:09 sybreon
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
Revision 1.12 2007/12/23 20:40:44 sybreon
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
Revision 1.11 2007/11/30 17:08:29 sybreon
Moved simulation kernel into code.
Revision 1.10 2007/11/16 21:52:03 sybreon
Added fsl_tag_o to FSL bus (tag either address or data).
Revision 1.9 2007/11/14 23:19:24 sybreon
Fixed minor typo.
Revision 1.8 2007/11/14 22:14:34 sybreon
Changed interrupt handling system (reported by M. Ettus).
Revision 1.7 2007/11/10 16:39:38 sybreon
Upgraded license to LGPLv3.
Significant performance optimisations.
Revision 1.6 2007/11/09 20:51:52 sybreon
Added GET/PUT support through a FSL bus.
Revision 1.5 2007/11/08 17:48:14 sybreon
Fixed data WISHBONE arbitration problem (reported by J Lee).
Revision 1.4 2007/11/08 14:17:47 sybreon
Parameterised optional components.
Revision 1.3 2007/11/03 08:34:55 sybreon
Minor code cleanup.
Revision 1.2 2007/11/02 19:20:58 sybreon
Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.
Revision 1.1 2007/11/02 03:25:40 sybreon
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
*/ |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac_txfifo(
input sys_clk,
input tx_rst,
input stb,
input [7:0] data,
output full,
input can_tx,
output reg empty,
input phy_tx_clk,
output reg phy_tx_en,
output reg [3:0] phy_tx_data
);
wire [7:0] fifo_out;
wire fifo_empty;
reg fifo_read;
reg empty2;
always @(posedge sys_clk) begin
empty2 <= fifo_empty;
empty <= empty2;
end
minimac_asfifo #(
.DATA_WIDTH(8),
.ADDRESS_WIDTH(7)
) fifo (
.Data_out(fifo_out),
.Empty_out(fifo_empty),
.ReadEn_in(fifo_read),
.RClk(phy_tx_clk),
.Data_in(data),
.Full_out(full),
.WriteEn_in(stb),
.WClk(sys_clk),
.Clear_in(tx_rst)
);
reg can_tx1;
reg can_tx2;
always @(posedge phy_tx_clk) begin
can_tx1 <= can_tx;
can_tx2 <= can_tx1;
end
reg tx_rst1;
reg tx_rst2;
always @(posedge phy_tx_clk) begin
tx_rst1 <= tx_rst;
tx_rst2 <= tx_rst1;
end
wire interframe_gap;
wire transmitting = can_tx2 & ~fifo_empty & ~interframe_gap;
reg transmitting_r;
always @(posedge phy_tx_clk)
transmitting_r <= transmitting;
reg [4:0] interframe_counter;
always @(posedge phy_tx_clk) begin
if(tx_rst2)
interframe_counter <= 5'd0;
else begin
if(transmitting_r & ~transmitting)
interframe_counter <= 5'd24;
else if(interframe_counter != 5'd0)
interframe_counter <= interframe_counter - 5'd1;
end
end
assign interframe_gap = |interframe_counter;
reg hi_nibble;
always @(posedge phy_tx_clk) begin
if(tx_rst2) begin
hi_nibble <= 1'b0;
phy_tx_en <= 1'b0;
end else begin
hi_nibble <= 1'b0;
phy_tx_en <= 1'b0;
fifo_read <= 1'b0;
if(transmitting) begin
phy_tx_en <= 1'b1;
if(~hi_nibble) begin
phy_tx_data <= fifo_out[3:0];
fifo_read <= 1'b1;
hi_nibble <= 1'b1;
end else begin
phy_tx_data <= fifo_out[7:4];
hi_nibble <= 1'b0;
end
end
end
end
endmodule
|
`include "DEF.v"
module excute(clock,
in_op, in_src1, in_src2, in_dst, in_imm,
out_dst, out_dst_data, write_dst,
dmem_address, dmem_data, dmem_write, dmem_read,
cnt_ex, cnt_read, in_databus, in_databus2
);
input clock;
input [31:0] in_op;
input signed [31:0] in_src1, in_src2;
input [4:0] in_dst;
input [31:0] in_imm;
inout [31:0] dmem_data;
input [63:0] in_databus, in_databus2;
output [31:0] dmem_address;
output [4:0] out_dst;
output [31:0] out_dst_data;
output write_dst;
output dmem_write;
output dmem_read;
output cnt_read;
output cnt_ex;
reg [31:0] opcode;
reg signed [31:0] source1, source2;
reg [4:0] destination;
reg signed [31:0] immediate;
reg signed [31:0] result;
reg r_write_dst;
reg r_dmem_write, r_dmem_read;
reg r_cnt_read;
reg r_cnt_ex;
assign out_dst = destination;
assign out_dst_data = result;
assign write_dst = r_write_dst;
assign dmem_write = r_dmem_write;
assign dmem_read = r_dmem_read;
assign dmem_address = immediate;
assign dmem_data = r_dmem_read ? 32'hz : source2;
assign cnt_read = r_cnt_read;
assign cnt_ex = r_cnt_ex;
always @(posedge clock)
begin
r_cnt_read <= 0;
r_cnt_ex <= 0;
if(in_databus[63:48] !== 16'b100000_00000_00000 &&
in_databus2[63:48] !== 16'b100000_00000_00000)
begin
//$display("cycle=%d\ninstruction=%d\n", count_cycle, count_instr);
//$stop;
/*#0.001
$display("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\n", opcode, result, source1, source2, immediate, destination);
*/
//$monitor("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\n", opcode, result, source1, source2, immediate, destination);
//$display("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
#0.001
if(!(opcode === 1 && source2 === 0 && immediate === 0))
begin
r_cnt_ex <= 1;
end
casex(opcode)
1: /* sll */
begin
result <= source2 << immediate;
#0.010 r_write_dst <= 1;
end
2: /* addi */
begin
result <= immediate[15:15]===1 ? source1 - (~{16'b1111111111111111,immediate[15:0]}+1) : source1 + immediate;
#0.010 r_write_dst <= 1;
end
3: /* mul */
begin
result <= source1 * source2;
/*
#0.001 $display("MUL !!!! %d %d %d\n", result, source1, source2);
$stop;
*/
#0.010 r_write_dst <= 1;
end
4: /* move */
begin
result <= source1;
#0.010 r_write_dst <= 1;
end
5: /* movei */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
end
6: /* add */
begin
result <= source1 + source2;
#0.010 r_write_dst <= 1;
end
9: /* lw */
begin
r_dmem_read <= 1;
//#0.010 $display("dmem_data:%d dmem_read:%d dmem_address:%d\n", dmem_data, dmem_read, dmem_address);
#0.010 result <= dmem_data;
/*
$display("dmem_data:%d dmem_read:%d dmem_address:%d\n", dmem_data, dmem_read, dmem_address);
$stop;
*/
#0.010 r_write_dst <= 1;
end
10: /* sw */
begin
#0.010 r_dmem_write <= 1;
//$display("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
end
12: /* halt */
begin
#0.001
r_cnt_read <= 1;
#0.498
$display("halt\n");
$stop;
end
13: /* muli */
begin
result <= source1 * (immediate[15:15]==1 ? -(~{16'b1111111111111111,immediate[15:0]}+1) : immediate);
#0.010 r_write_dst <= 1;
end
14: /* jal */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
//$display("jal31: %d %d\n", destination, result);
//$stop;
end
15: /* ori */
begin
result <= source1 | immediate;
//$display("ori miao!!!!!!! %d %d %d\n", source1, immediate, source1 | immediate);
#0.010 r_write_dst <= 1;
end
16: /* lui */
begin
result <= immediate << 16;
//$display("lui miao!!!!!!! %d %d\n", immediate, immediate << 16);
#0.010 r_write_dst <= 1;
end
endcase
end
end
always @(negedge clock)
begin
#0.010
if(in_databus[63:48] !== 16'b100000_00000_00000)
begin
opcode <= in_op;
source1 <= in_src1;
source2 <= in_src2;
immediate <= in_imm;
destination <= in_dst;
r_write_dst <= 0;
r_dmem_write <= 0;
r_dmem_read <= 0;
end
end
endmodule
|
//==================================================================================================
// Filename : DECO_CORDIC_OP.v
// Created On : 2016-10-03 13:00:49
// Last Modified : 2016-10-03 14:44:53
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : DECODER TO TO SELECT THE THIRD MUX AND INVERT SIGN
//
//
//==================================================================================================
`timescale 1ns / 1ps
module DECO_CORDIC_EXT #(parameter W = 32)(
input wire [W-1:0] data_i,
input wire operation,
input wire [1:0] shift_region_flag,
output reg sel_mux_3,
output reg [W-1:0] data_out
);
always @(*) begin
if(operation == 1'b0)
begin //COSENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b1;
data_out = {~data_i[W-1],data_i[W-2:0]};
end
2'b10 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
2'b11 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
default: begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
endcase
end
else begin ///SENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
2'b10 : begin
sel_mux_3 = 1'b0;
data_out = {~data_i[W-1],data_i[W-2:0]};;
end
2'b11 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
default: begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
endcase
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic single-channel AXI FIFO
// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
// Transfers received on the AXI slave port are pushed onto the FIFO.
// FIFO output, when available, is presented on the AXI master port and
// popped when the master port responds (M_READY).
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_fifo
// fifo_gen
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON64_NEXT 6'b00_0001
`define S_TXPORTMON64_EVT_2 6'b00_0010
`define S_TXPORTMON64_TXN 6'b00_0100
`define S_TXPORTMON64_READ 6'b00_1000
`define S_TXPORTMON64_END_0 6'b01_0000
`define S_TXPORTMON64_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE2Lo=0, _rLenLE2Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON64_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON64_READ
assign TXN = rState[2]; // S_TXPORTMON64_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON64_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_EVT_2;
end
`S_TXPORTMON64_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_TXN;
end
`S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ);
end
`S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON64_END_0;
end
`S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
end
`S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_NEXT;
end
default: begin
_rState = `S_TXPORTMON64_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE2Lo <= #1 _rLenLE2Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[C_DATA_WIDTH-1:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 2, we want to trigger the almost all received flag
_rLenLE2Lo = (LEN[15:0] <= 16'd2);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
input clk;
sub sub (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
module sub (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
integer cyc=0;
reg [127:0] save128;
reg [47:0] save48;
reg [1:0] save2;
reg [255:0] cycdone; // Make sure each cycle executes exactly once
reg [31:0] vec[2:1][2:1];
reg [2:1][2:1][31:0] pvec;
real r;
string s,s2;
string sarr[2:1];
string si;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d\n",$time, cyc);
`endif
si = "siimmed";
cyc <= cyc + 1;
if (cycdone[cyc[7:0]]) $stop;
cycdone[cyc[7:0]] <= '1;
if (cyc==0) begin
// Setup
save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e;
save48 <= 48'h4afe43fb79d7;
save2 <= 2'b10;
vec[1][1] <= 32'h0101;
vec[1][2] <= 32'h0102;
vec[2][1] <= 32'h0201;
vec[2][2] <= 32'h0202;
pvec[1][1] <= 32'h10101;
pvec[1][2] <= 32'h10102;
pvec[2][1] <= 32'h10201;
pvec[2][2] <= 32'h10202;
r <= 1.234;
s <= "hello";
sarr[1] <= "sarr[1]";
sarr[2] <= "sarr[2]";
end
if (cyc==1) begin
if ($test$plusargs("save_restore")!=0) begin
// Don't allow the restored model to run from time 0, it must run from a restore
$write("%%Error: didn't really restore\n");
$stop;
end
end
else if (cyc==99) begin
if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop;
if (save48 !== 48'h4afe43fb79d7) $stop;
if (save2 !== 2'b10) $stop;
if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop;
if (vec[1][1] !== 32'h0101) $stop;
if (vec[1][2] !== 32'h0102) $stop;
if (vec[2][1] !== 32'h0201) $stop;
if (vec[2][2] !== 32'h0202) $stop;
if (pvec[1][1] !== 32'h10101) $stop;
if (pvec[1][2] !== 32'h10102) $stop;
if (pvec[2][1] !== 32'h10201) $stop;
if (pvec[2][2] !== 32'h10202) $stop;
if (r != 1.234) $stop;
$display("%s",s);
$display("%s",sarr[1]);
$display("%s",sarr[2]);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_BEHAVIORAL_PP_V |
`timescale 1ns/1ps
`include "../global.v"
module ExpRegisterFile_tb();
parameter HCP = 10; //half clock period
reg clk, reset;
reg writeEnableA, writeEnableB;
reg [8:0] writeValueA, writeValueB;
reg [2:0] readSelectA, readSelectB;
wire [8:0] readResultA, readResultB;
defparam DUT.REGISTER_WIDTH = 9;
RegisterFile DUT(clk, reset, writeEnableA, writeEnableB, writeValueA, writeValueB, readSelectA, readSelectB, readResultA, readResultB);
initial forever begin
#HCP clk = ~clk;
end
initial begin
clk = 0;
reset = 1;
writeEnableA = 1'b1;
writeEnableB = 1'b0;
writeValueA = 9'h0AA;
writeValueB = 9'h0EE;
readSelectA = 3'b000;
readSelectB = 3'b001;
#(2*HCP) reset = 0;
#(2*HCP) writeEnableA = 1'b0;
writeEnableB = 1'b1;
writeValueA = 9'h0EE;
writeValueB = 9'h0BB;
#(2*HCP) readSelectA = 3'b001;
readSelectB = 3'b000;
#(2*HCP) readSelectA = 3'b010;
readSelectB = 3'b011;
#(2*HCP) readSelectA = 3'b100;
readSelectB = 3'b101;
#(2*HCP) readSelectA = 3'b110;
readSelectB = 3'b111;
end
endmodule
|
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
$write("P0%d(%d)|P1%d(%d)|P2%d(%d)|P3%d(%d)",
c.phase_a[2:0], c.pchange_a, c.phase_b[2:0], c.pchange_b,
c.phase_c[2:0], c.pchange_c, c.phase_d[2:0], c.pchange_d);
$write("|");
if (c.stree0.F04_emp) $write("---------- "); else $write("%d ", c.stree0.F04_dot);
if (c.stree0.F05_emp) $write("---------- "); else $write("%d ", c.stree0.F05_dot);
if (c.stree0.F06_emp) $write("---------- "); else $write("%d ", c.stree0.F06_dot);
if (c.stree0.F07_emp) $write("---------- "); else $write("%d ", c.stree0.F07_dot);
$write("|");
if (c.stree1.F04_emp) $write("---------- "); else $write("%d ", c.stree1.F04_dot);
if (c.stree1.F05_emp) $write("---------- "); else $write("%d ", c.stree1.F05_dot);
if (c.stree1.F06_emp) $write("---------- "); else $write("%d ", c.stree1.F06_dot);
if (c.stree1.F07_emp) $write("---------- "); else $write("%d ", c.stree1.F07_dot);
$write("|");
if (c.stree2.F04_emp) $write("---------- "); else $write("%d ", c.stree2.F04_dot);
if (c.stree2.F05_emp) $write("---------- "); else $write("%d ", c.stree2.F05_dot);
if (c.stree2.F06_emp) $write("---------- "); else $write("%d ", c.stree2.F06_dot);
if (c.stree2.F07_emp) $write("---------- "); else $write("%d ", c.stree2.F07_dot);
$write("|");
if (c.stree3.F04_emp) $write("---------- "); else $write("%d ", c.stree3.F04_dot);
if (c.stree3.F05_emp) $write("---------- "); else $write("%d ", c.stree3.F05_dot);
if (c.stree3.F06_emp) $write("---------- "); else $write("%d ", c.stree3.F06_dot);
if (c.stree3.F07_emp) $write("---------- "); else $write("%d ", c.stree3.F07_dot);
$write("|");
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
if (c.F01_deq2) $write("%d", c.F01_dot2); else $write(" ");
if (c.F01_deq3) $write("%d", c.F01_dot3); else $write(" ");
if (d_w) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(d.app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:28:10 02/03/2015
// Design Name: sha256_core
// Project Name: crypto_sha256
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sha256_core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sha256_core_tb;
// Inputs
reg clk;
reg rst_i;
reg load_i;
reg [511:0] data_i;
reg [255:0] state_i;
reg [255:0] test_val;
// Outputs
wire [255:0] state_o;
wire busy_o;
// Instantiate the Unit Under Test (UUT)
sha256_core uut (
.clk(clk),
//.rst_i(rst_i),
.load_i(load_i),
.data_i(data_i),
.state_i(state_i),
.state_o(state_o),
.busy_o(busy_o)
);
initial begin
// Initialize Inputs
clk = 0;
rst_i = 1;
load_i = 0;
data_i = 0;
state_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst_i = 0;
state_i = {
32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a,
32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19
};
data_i = {
32'h61626380, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000018
};
test_val = {
32'hba7816bf, 32'h8f01cfea, 32'h414140de, 32'h5dae2223,
32'hb00361a3, 32'h96177a9c, 32'hb410ff61, 32'hf20015ad
};
load_i = 1;
while(!busy_o) #1;
load_i = 0;
while(busy_o) #1;
if(test_val != state_o)
begin
$display("test #1 fail");
$stop;
end
$display("sha256_core passed");
$finish;
end
always #10 clk <= ~clk;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_timer_ms (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h3E7;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_bypass_reg(clock, resetn,
i_settings,
i_register_settings,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, o_dataout_valid, i_dataout_stall);
parameter DATA_WIDTH = 32;
input clock;
input resetn;
input i_settings;
input [DATA_WIDTH-1:0] i_register_settings;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
assign o_dataout = i_settings ? i_register_settings : i_datain;
assign o_dataout_valid = i_datain_valid;
assign o_datain_stall = i_dataout_stall;
endmodule
|
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module t
(
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule
|
//----------------------------------------------------
// A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL.
//----------------------------------------------------
module arbiter (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
//--------------Internal Registers----------------------
wire [1:0] gnt ;
wire comreq ;
wire beg ;
wire [1:0] lgnt ;
wire lcomreq ;
reg lgnt0 ;
reg lgnt1 ;
reg lgnt2 ;
reg lgnt3 ;
reg lasmask ;
reg lmask0 ;
reg lmask1 ;
reg ledge ;
//--------------Code Starts Here-----------------------
always @ (posedge clk)
if (rst) begin
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
| (~lcomreq & lmask1 & lmask0 & req0 )
| ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req2)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
| (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
end
//----------------------------------------------------
// lasmask state machine.
//----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk)
begin
lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask);
end
//----------------------------------------------------
// comreq logic.
//----------------------------------------------------
assign lcomreq = ( req3 & lgnt3 )
| ( req2 & lgnt2 )
| ( req1 & lgnt1 )
| ( req0 & lgnt0 );
//----------------------------------------------------
// Encoder logic.
//----------------------------------------------------
assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
//----------------------------------------------------
// lmask register.
//----------------------------------------------------
always @ (posedge clk )
if( rst ) begin
lmask1 <= 0;
lmask0 <= 0;
end else if(lasmask) begin
lmask1 <= lgnt[1];
lmask0 <= lgnt[0];
end else begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
assign comreq = lcomreq;
assign gnt = lgnt;
//----------------------------------------------------
// Drive the outputs
//----------------------------------------------------
assign gnt3 = lgnt3;
assign gnt2 = lgnt2;
assign gnt1 = lgnt1;
assign gnt0 = lgnt0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
//bug456
typedef logic signed [34:0] rc_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [34:0] rc = crc[34:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic o; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.rc (rc),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, o};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7211d24a17b25ec9
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test( output logic o,
input rc_t rc,
input logic clk);
localparam RATIO = 2;
rc_t rc_d[RATIO:1];
always_ff @(posedge clk) begin
integer k;
rc_d[1] <= rc;
for( k=2; k<RATIO+1; k++ ) begin
rc_d[k] <= rc_d[k-1];
end
end // always_ff @
assign o = rc_d[RATIO] < 0;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE
// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// ALTTEMP_SENSE
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix V" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 12.0SP2 cbx_alttemp_sense 2012:08:02:15:11:11:SJ cbx_cycloneii 2012:08:02:15:11:11:SJ cbx_lpm_add_sub 2012:08:02:15:11:11:SJ cbx_lpm_compare 2012:08:02:15:11:11:SJ cbx_lpm_counter 2012:08:02:15:11:11:SJ cbx_lpm_decode 2012:08:02:15:11:11:SJ cbx_mgl 2012:08:02:15:40:54:SJ cbx_stratix 2012:08:02:15:11:11:SJ cbx_stratixii 2012:08:02:15:11:11:SJ cbx_stratixiii 2012:08:02:15:11:11:SJ cbx_stratixv 2012:08:02:15:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixv_tsdblock 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_v8t
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp FALSE TRUE
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_1_V
`define SKY130_FD_SC_HVL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_1_V
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Module Description : This module generates CE signal
// in 3 different patterns,
// (1) Always asserted
// (2) Random assertion
// (3) Periodic assertion based on input period
//--------------------------------------------------
//-- Clock Enable Generator
//--------------------------------------------------
`timescale 1ns/10ps
module ce_gen
(
input clk_in,
input sclr_in,
output reg ce_out
);
integer rseed = 0;
integer ce_period = 10;
integer ce_period_cnt = 0;
reg enable = 0;
reg [1:0] ce_pattern = 2'b00;
//----------------------------------------------------
// CE PATTERN :
// 2'b00 : CE is always asserted
// 2'b01 : CE is asserted periodically every ce_period
// 2'b10 : CE is asserted randomly
// 2'b11 : FORBIDDEN
//----------------------------------------------------
task start_random;
input [31:0] seed;
begin
rseed <= seed;
ce_pattern <= 2'b10;
enable <= 1;
$display("@%10t : CE Generator : Enabled (Random)", $time);
end
endtask
task start_periodic;
input [31:0] input_period;
begin
ce_period <= input_period;
ce_period_cnt <= 0;
ce_pattern <= 2'b01;
enable <= 1;
$display("@%10t : CE Generator : Enabled (Periodic) [%dns]", $time, input_period);
end
endtask
task start;
begin
ce_pattern <= 2'b00;
enable <= 1;
$display("@%10t : CE Generator : Enabled (always asserted)", $time);
end
endtask
task stop;
begin
enable <= 0;
$display("@%10t : CE Generator : Disabled.", $time);
end
endtask
// RESET DETECTION
always @ (posedge sclr_in)
begin
ce_out = 0;
ce_period_cnt = 0;
enable = 0;
end
// CE GENERATION
always @ (posedge clk_in)
begin
if (enable)
begin
case (ce_pattern)
2'b00 : begin
ce_out = 1;
end
2'b01 : begin
if (ce_period_cnt % (ce_period/2) == 0)
begin
ce_out = ~ce_out;
ce_period_cnt = 0;
end
ce_period_cnt = ce_period_cnt + 1;
end
2'b10 : begin
ce_out = {$random(rseed)}%2;
end
default : begin
$display("CE Generator : ERROR! ce_pattern[1:0] = 2'b11 IS NOT A VALID SETTING.");
$finish;
end
endcase
end
else
begin
ce_period_cnt <= 0;
ce_out <= 0;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
|
module ram_wb_b3(
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
wb_clk_i, wb_rst_i);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [dw-1:0] wb_dat_o;
input wb_clk_i;
input wb_rst_i;
// Memory parameters
parameter mem_size_bytes = 32'h0002_0000; // 128KBytes
parameter mem_adr_width = 17; //(log2(mem_size_bytes));
parameter bytes_per_dw = (dw/8);
parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
parameter mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [0:mem_words-1] /* synthesis ram_style = block */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
wire [31:0] wr_data;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
// Wire to indicate addressing error
wire addr_err;
// Logic to detect if there's a burst access going on
assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans;
assign wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Burst address generation logic
always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
if (wb_b3_trans_start)
// Kick off burst_adr_counter, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
if (wb_bte_i_r == 2'b00) // Linear burst
burst_adr_counter = adr + 1;
if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
burst_adr_counter[1:0] = adr[1:0] + 1;
if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
burst_adr_counter[2:0] = adr[2:0] + 1;
if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
burst_adr_counter[3:0] = adr[3:0] + 1;
end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
always @(posedge wb_clk_i)
wb_bte_i_r <= wb_bte_i;
// Register it locally
always @(posedge wb_clk_i)
wb_cti_i_r <= wb_cti_i;
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr &
(adr != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic
always@(posedge wb_clk_i)
if(wb_rst_i)
adr <= 0;
else if (using_burst_adr)
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[mem_adr_width-1:2];
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr_comb;
// Address registering logic, combinational version, to enable block ram infer
always@(*)
if(wb_rst_i)
adr_comb = 0;
else if (using_burst_adr)
adr_comb = burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr_comb = wb_adr_i[mem_adr_width-1:2];
// Memory initialisation.
parameter memory_file = "sram.vmem";
// Must add -use_new_parser yes to XST command line for this to work
//otherwise XST requires an odd format
integer k;
initial begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we;
assign ram_we = wb_we_i & wb_ack_o;
reg [dw-1:0] data_from_mem;
always @(posedge wb_clk_i)begin
if(wb_cyc_i)
data_from_mem <= mem[adr_comb];
end
assign wb_dat_o = data_from_mem;
// Write logic
always @ (posedge wb_clk_i)
begin
if (ram_we)
mem[adr] <= wr_data;
end
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i &
!(burst_access_wrong_wb_adr | addr_err);
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) // We have bus
begin
if (addr_err & wb_stb_i)
begin
wb_ack_o_r <= 1;
end
else if (wb_cti_i == 3'b000)
begin
// Classic cycle acks
if (wb_stb_i)
begin
if (!wb_ack_o_r)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
end // if (wb_cti_i == 3'b000)
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
begin
// Increment/constant address bursts
if (wb_stb_i)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
else if (wb_cti_i == 3'b111)
begin
// End of cycle
if (!wb_ack_o_r)
wb_ack_o_r <= wb_stb_i;
else
wb_ack_o_r <= 0;
end
end // if (wb_cyc_i)
else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// Error when out of bounds of memory - skip top byte of address in case
// this is mapped somewhere other than 0x00.
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1:mem_adr_width]);
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr | addr_err);
`ifdef verilator
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr] = data;
endfunction // set_mem32
`endif
endmodule // ram_wb_b3
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_1_V
`define SKY130_FD_SC_HS__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_1_V
|
/**
* This file is part of pyBAR.
*
* pyBAR is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pyBAR is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with pyBAR. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
`default_nettype none
module clk_gen (
U1_CLKIN_IN,
U1_USER_RST_IN,
U1_CLKIN_IBUFG_OUT,
U1_CLK0_OUT,
U1_STATUS_OUT,
U2_CLKFX_OUT,
U2_CLKDV_OUT,
U2_CLK0_OUT,
U2_CLK2X_OUT,
U2_LOCKED_OUT,
U2_STATUS_OUT
);
input wire U1_CLKIN_IN;
input wire U1_USER_RST_IN;
output wire U2_CLKFX_OUT;
output wire U1_CLKIN_IBUFG_OUT;
output wire U1_CLK0_OUT;
output wire [7:0] U1_STATUS_OUT;
output wire U2_CLKDV_OUT;
output wire U2_CLK0_OUT;
output wire U2_CLK2X_OUT;
output wire U2_LOCKED_OUT;
output wire [7:0] U2_STATUS_OUT;
wire GND_BIT;
wire U1_CLKIN_IBUFG;
wire U1_CLK0_BUF;
wire U1_LOCKED_INV_IN;
wire U1_RST_IN;
wire U2_CLKDV_BUF;
wire U2_CLKFB_IN;
wire U2_CLKFX_BUF;
wire U2_CLK0_BUF;
wire U2_CLK2X_BUF;
wire U2_LOCKED_INV_RST;
wire U2_RST_IN;
wire CLKFX_OUT;
wire CLKFX_OUT_IBUFG;
assign GND_BIT = 0;
assign U1_CLKIN_IBUFG_OUT = U1_CLKIN_IBUFG;
assign U2_CLK0_OUT = U2_CLKFB_IN;
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(10), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_INST1 (
.CLKFB(U1_CLK0_OUT),
.CLKIN(U1_CLKIN_IBUFG), // 48MHz
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(U1_RST_IN),
.CLKDV(),
.CLKFX(CLKFX_OUT),
.CLKFX180(),
.CLK0(U1_CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(U1_LOCKED_INV_IN),
.PSDONE(),
.STATUS(U1_STATUS_OUT[7:0]));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(2), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(6.250), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_INST2 (
.CLKFB(U2_CLKFB_IN),
.CLKIN(CLKFX_OUT_IBUFG), // 160MHz
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(U2_RST_IN),
.CLKDV(U2_CLKDV_BUF),
.CLKFX(U2_CLKFX_BUF),
.CLKFX180(),
.CLK0(U2_CLK0_BUF),
.CLK2X(U2_CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(U2_LOCKED_OUT),
.PSDONE(),
.STATUS(U2_STATUS_OUT[7:0]));
IBUFG U1_CLKIN_IBUFG_INST (.I(U1_CLKIN_IN),
.O(U1_CLKIN_IBUFG));
BUFG U1_CLK0_BUFG_INST (.I(U1_CLK0_BUF),
.O(U1_CLK0_OUT));
BUFG U2_CLKDV_BUFG_INST (.I(U2_CLKDV_BUF),
.O(U2_CLKDV_OUT));
BUFG U2_CLKFX_BUFG_INST (.I(U2_CLKFX_BUF),
.O(U2_CLKFX_OUT));
BUFG U2_CLK0_BUFG_INST (.I(U2_CLK0_BUF),
.O(U2_CLKFB_IN));
BUFG U2_CLK2X_BUFG_INST (.I(U2_CLK2X_BUF),
.O(U2_CLK2X_OUT));
BUFG U1_CLK_OUT_BUFG_INST (.I(CLKFX_OUT),
.O(CLKFX_OUT_IBUFG));
wire U1_FDS_Q_OUT;
wire U1_FD1_Q_OUT;
wire U1_FD2_Q_OUT;
wire U1_FD3_Q_OUT;
wire U1_OR3_O_OUT;
FDS U1_FDS_INST (.C(U1_CLKIN_IBUFG),
.D(GND_BIT),
.S(GND_BIT),
.Q(U1_FDS_Q_OUT));
FD U1_FD1_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FDS_Q_OUT),
.Q(U1_FD1_Q_OUT));
FD U1_FD2_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FD1_Q_OUT),
.Q(U1_FD2_Q_OUT));
FD U1_FD3_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FD2_Q_OUT),
.Q(U1_FD3_Q_OUT));
INV U1_INV_INST (.I(U1_LOCKED_INV_IN),
.O(U2_LOCKED_INV_RST));
OR2 U1_OR2_INST (.I0(U1_USER_RST_IN),
.I1(U1_OR3_O_OUT),
.O(U1_RST_IN));
OR3 U1_OR3_INST (.I0(U1_FD3_Q_OUT),
.I1(U1_FD2_Q_OUT),
.I2(U1_FD1_Q_OUT),
.O(U1_OR3_O_OUT));
wire U2_FDS_Q_OUT;
wire U2_FD1_Q_OUT;
wire U2_FD2_Q_OUT;
wire U2_FD3_Q_OUT;
wire U2_OR3_O_OUT;
FDS U2_FDS_INST (.C(CLKFX_OUT_IBUFG),
.D(GND_BIT),
.S(GND_BIT),
.Q(U2_FDS_Q_OUT));
FD U2_FD1_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FDS_Q_OUT),
.Q(U2_FD1_Q_OUT));
FD U2_FD2_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FD1_Q_OUT),
.Q(U2_FD2_Q_OUT));
FD U2_FD3_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FD2_Q_OUT),
.Q(U2_FD3_Q_OUT));
OR2 U2_OR2_INST (.I0(U2_LOCKED_INV_RST),
.I1(U2_OR3_O_OUT),
.O(U2_RST_IN));
OR3 U2_OR3_INST (.I0(U2_FD3_Q_OUT),
.I1(U2_FD2_Q_OUT),
.I2(U2_FD1_Q_OUT),
.O(U2_OR3_O_OUT));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V |
`timescale 1ns / 1ps
/*
* Module: InstructionMemory
*
* Implements read-only instruction memory
* Memory contents are initialized from the file "ImemInit.v"
*/
module InstructionMemory(Data, Address);
parameter T_rd = 20;
parameter MemSize = 40;
output [31:0] Data;
input [31:0] Address;
reg [31:0] Data;
/*
* ECEN 350 Processor Test Functions
* Texas A&M University
*/
always @ (Address) begin
case(Address)
/*
* Test Program 1:
* Sums $a0 words starting at $a1. Stores the sum at the end of the array
* Tests add, addi, lw, sw, beq
*/
/*
main:
li $t0, 50 # Initialize the array to (50, 40, 30)
sw $t0, 0($0) # Store first value
li $t0, 40
sw $t0, 4($0) # Store Second Value
li $t0, 30
sw $t0, 8($0) # Store Third Value
li $a0, 0 # address of array
li $a1, 3 # 3 values to sum
TestProg1:
add $t0, $0, $0 # This is the sum
add $t1, $0, $a0 # This is our array pointer
add $t2, $0, $0 # This is our index counter
P1Loop: beq $t2, $a1, P1Done # Our loop
lw $t3, 0($t1) # Load Array[i]
add $t0, $t0, $t3 # Add it into the sum
add $t1, $t1, 4 # Next address
add $t2, $t2, 1 # Next index
j P1Loop # Jump to loop
P1Done: sw $t0, 0($t1) # Store the sum at end of array
lw $t0, 12($0) # Load Final Value
nop # Complete
*/
32'h00: Data = 32'h34080032;
32'h04: Data = 32'hac080000;
32'h08: Data = 32'h34080028;
32'h0C: Data = 32'hac080004;
32'h10: Data = 32'h3408001e;
32'h14: Data = 32'hac080008;
32'h18: Data = 32'h34040000;
32'h1C: Data = 32'h34050003;
32'h20: Data = 32'h00004020;
32'h24: Data = 32'h00044820;
32'h28: Data = 32'h00005020;
32'h2C: Data = 32'h11450005;
32'h30: Data = 32'h8d2b0000;
32'h34: Data = 32'h010b4020;
32'h38: Data = 32'h21290004;
32'h3C: Data = 32'h214a0001;
32'h40: Data = 32'h0800000b;
32'h44: Data = 32'had280000;
32'h48: Data = 32'h8c08000c;
32'h4C: Data = 32'h00000000;
/*
* Test Program 2:
* Does some arithmetic computations and stores result in memory
*/
/*
main2:
li $a0, 32 # Address of memory to store result
TestProg2:
add $2, $0, 1 # $2 = 1
sub $3, $0, $2 # $3 = -1
slt $5, $3, $0 # $5 = 1
add $6, $2, $5 # $6 = 2
or $7, $5, $6 # $7 = 3
sub $8, $5, $7 # $8 = -2
and $9, $8, $7 # $9 = 2
sw $9, 0($a0) # Store $9 in DMem[8]
lw $9, 32($0) # Load Final Value
nop # Complete
*/
32'h60: Data = 32'h34040020;
32'h64: Data = 32'h20020001;
32'h68: Data = 32'h00021822;
32'h6C: Data = 32'h0060282a;
32'h70: Data = 32'h00453020;
32'h74: Data = 32'h00a63825;
32'h78: Data = 32'h00a74022;
32'h7C: Data = 32'h01074824;
32'h80: Data = 32'hac890000;
32'h84: Data = 32'h8c090020;
32'h88: Data = 32'h00000000;
/*
* Test Program 3
* Test Immediate Function
*/
/*
TestProg3:
li $a0, 0xfeedbeef # $a0 = 0xfeedbeef
sw $a0, 36($0) # Store $a0 in DMem[9]
addi $a1, $a0, -2656 # $a1 = 0xfeedb48f
sw $a1, 40($0) # Store $a1 in DMem[10]
addiu $a1, $a0, -2656 # $a1 = 0xfeedb48f
sw $a1, 44($0) # Store $a1 in DMem[11]
andi $a1, $a0, 0xf5a0 # $a1 = 0xb4a0
sw $a1, 48($0) # Store $a1 in DMem[12]
sll $a1, $a0, 5 # $a1 = 0xddb7dde0
sw $a1, 52($0) # Store $a1 in DMem[13]
srl $a1, $a0, 5 # $a1 = 0x07f76df7
sw $a1, 56($0) # Store $a1 in DMem[14]
sra $a1, $a0, 5 # $a1 = 0xfff76df7
sw $a1, 60($0) # Store $a1 in DMem[15]
slti $a1, $a0, 1 # $a1 = 1
sw $a1, 64($0) # Store $a1 in DMem[16]
slti $a1, $a1, -1 # $a1 = 0
sw $a1, 68($0) # Store $a1 in DMem[17]
sltiu $a1, $a0, 1 # $a1 = 0
sw $a1, 72($0) # Store $a1 in DMem[18]
sltiu $a1, $a1, -1 # $a1 = 1
sw $a1, 76($0) # Store $a1 in DMem[19]
xori $a1, $a0, 0xf5a0 # $a1 = 0xfeed4b4f
sw $a1, 80($0) # Store $a1 in DMem[20]
lw $a0, 36($0) # Load Value to test
lw $a1, 40($0) # Load Value to test
lw $a1, 44($0) # Load Value to test
lw $a1, 48($0) # Load Value to test
lw $a1, 52($0) # Load Value to test
lw $a1, 56($0) # Load Value to test
lw $a1, 60($0) # Load Value to test
lw $a1, 64($0) # Load Value to test
lw $a1, 68($0) # Load Value to test
lw $a1, 72($0) # Load Value to test
lw $a1, 76($0) # Load Value to test
lw $a1, 80($0) # Load Value to test
nop # Complete
*/
32'hA0: Data = 32'h3c01feed;
32'hA4: Data = 32'h3424beef;
32'hA8: Data = 32'hac040024;
32'hAC: Data = 32'h2085f5a0;
32'hB0: Data = 32'hac050028;
32'hB4: Data = 32'h2485f5a0;
32'hB8: Data = 32'hac05002c;
32'hBC: Data = 32'h3085f5a0;
32'hC0: Data = 32'hac050030;
32'hC4: Data = 32'h00042940;
32'hC8: Data = 32'hac050034;
32'hCC: Data = 32'h00042942;
32'hD0: Data = 32'hac050038;
32'hD4: Data = 32'h00042943;
32'hD8: Data = 32'hac05003c;
32'hDC: Data = 32'h28850001;
32'hE0: Data = 32'hac050040;
32'hE4: Data = 32'h28a5ffff;
32'hE8: Data = 32'hac050044;
32'hEC: Data = 32'h2c850001;
32'hF0: Data = 32'hac050048;
32'hF4: Data = 32'h2ca5ffff;
32'hF8: Data = 32'hac05004c;
32'hFC: Data = 32'h3885f5a0;
32'h100: Data = 32'hac050050;
32'h104: Data = 32'h8c040024;
32'h108: Data = 32'h8c050028;
32'h10C: Data = 32'h8c05002c;
32'h110: Data = 32'h8c050030;
32'h114: Data = 32'h8c050034;
32'h118: Data = 32'h8c050038;
32'h11C: Data = 32'h8c05003c;
32'h120: Data = 32'h8c050040;
32'h124: Data = 32'h8c050044;
32'h128: Data = 32'h8c050048;
32'h12C: Data = 32'h8c05004c;
32'h130: Data = 32'h8c050050;
32'h134: Data = 32'h00000000;
/*
* Test Program 4
* Test jal and jr
*/
/*
TestProg4:
li $t1, 0xfeed # $t1 = 0xfeed
li $t0, 0x190 # Load address of P4jr
jr $t0 # Jump to P4jr
li $t1, 0 # Check for failure to jump
P4jr: sw $t1, 84($0) # $t1 should be 0xfeed if successful
li $t0, 0xcafe # $t1 = 0xcafe
jal P4Jal # Jump to P4Jal
li $t0, 0xbabe # Check for failure to jump
P4Jal: sw $t0, 88($0) # $t0 should be 0xcafe if successful
li $t2, 0xface # $t2 = 0xface
j P4Skip # Jump to P4Skip
li $t2, 0
P4Skip: sw $t2, 92($0) # $t2 should be 0xface if successful
sw $ra, 96($0) # Store $ra
lw $t0, 84($0) # Load value for check
lw $t1, 88($0) # Load value for check
lw $t2, 92($0) # Load value for check
lw $ra, 96($0) # Load value for check
*/
32'h180: Data = 32'h3409feed;
32'h184: Data = 32'h34080190;
32'h188: Data = 32'h01000008;
32'h18C: Data = 32'h34090000;
32'h190: Data = 32'hac090054;
32'h194: Data = 32'h3408cafe;
32'h198: Data = 32'h0c000068;
32'h19C: Data = 32'h3408babe;
32'h1A0: Data = 32'hac080058;
32'h1A4: Data = 32'h340aface;
32'h1A8: Data = 32'h0800006c;
32'h1AC: Data = 32'h340a0000;
32'h1B0: Data = 32'hac0a005c;
32'h1B4: Data = 32'hac1f0060;
32'h1B8: Data = 32'h8c080054;
32'h1BC: Data = 32'h8c090058;
32'h1C0: Data = 32'h8c0a005c;
32'h1C4: Data = 32'h8c1f0060;
32'h1C8: Data = 32'h00000000;
/*
* Test Program 5
* Tests mula using wavelet transform
*/
/*
TestProg5:
li $2, 1 # $1 = 1
li $3, 0 # $2 = -1
li $20, 0 # $20 = 0 (result)
li $4, 5 # Load wavelet part 1
li $5, 7 # Load wavelet part 2
li $6, 2 # Load wavelet part 3
li $7, 9 # Load wavelet part 4
mula $20, $4, $2 # Perform convolution
mula $20, $5, $2
mula $20, $6, $0
mula $20, $7, $0
sw $20, 104($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $0 # Perform convolution
mula $20, $5, $0
mula $20, $6, $2
mula $20, $7, $2
sw $20, 108($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $2 # Perform convolution
mula $20, $5, $0
mula $20, $6, $2
mula $20, $7, $0
sw $20, 112($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $0 # Perform convolution
mula $20, $5, $2
mula $20, $6, $0
mula $20, $7, $2
sw $20, 116($0) # Save result
lw $t0, 104($0) # Load value for check
lw $t0, 108($0) # Load value for check
lw $t0, 112($0) # Load value for check
lw $t0, 116($0) # Load value for check
*/
32'h200: Data = 32'h34020001;
32'h204: Data = 32'h34030000;
32'h208: Data = 32'h34140000;
32'h20C: Data = 32'h34040005;
32'h210: Data = 32'h34050007;
32'h214: Data = 32'h34060002;
32'h218: Data = 32'h34070009;
32'h21C: Data = 32'h0082a038;
32'h220: Data = 32'h00a2a038;
32'h224: Data = 32'h00c0a038;
32'h228: Data = 32'h00e0a038;
32'h22C: Data = 32'hac140068;
32'h230: Data = 32'h34140000;
32'h234: Data = 32'h0080a038;
32'h238: Data = 32'h00a0a038;
32'h23C: Data = 32'h00c2a038;
32'h240: Data = 32'h00e2a038;
32'h244: Data = 32'hac14006c;
32'h248: Data = 32'h34140000;
32'h24C: Data = 32'h0082a038;
32'h250: Data = 32'h00a0a038;
32'h254: Data = 32'h00c2a038;
32'h258: Data = 32'h00e0a038;
32'h25C: Data = 32'hac140070;
32'h260: Data = 32'h34140000;
32'h264: Data = 32'h0080a038;
32'h268: Data = 32'h00a2a038;
32'h26C: Data = 32'h00c0a038;
32'h270: Data = 32'h00e2a038;
32'h274: Data = 32'hac140074;
32'h278: Data = 32'h8c080068;
32'h27C: Data = 32'h8c08006c;
32'h280: Data = 32'h8c080070;
32'h284: Data = 32'h8c080074;
/*
* Test Program 6
* Tests Overflow Exceptions
*/
/*
Test4-1:
li $t0, -2147450880
add $t0, $t0, $t0
lw $t0, 4($0)
Test4-2:
li $t0, 2147450879
add $t0, $t0, $t0
lw $t0, 4($0)
Test 4-3:
lw $t0, 4($0)
li $t0, -2147483648
li $t1, 1
sub $t0, $t0, $t1
lw $t0, 4($0)
Test 4-4:
li $t0, 2147483647
mula $t0, $t0, $t0
lw $t0, 4($0)
*/
32'h300: Data = 32'h3c018000;
32'h304: Data = 32'h34288000;
32'h308: Data = 32'h01084020;
32'h30C: Data = 32'h8c080004;
32'h310: Data = 32'h3c017fff;
32'h314: Data = 32'h34287fff;
32'h318: Data = 32'h01084020;
32'h31C: Data = 32'h8c080004;
32'h320: Data = 32'h8c080004;
32'h324: Data = 32'h3c088000;
32'h328: Data = 32'h34090001;
32'h32C: Data = 32'h01094022;
32'h330: Data = 32'h8c080004;
32'h334: Data = 32'h3c017FFF;
32'h338: Data = 32'h3428FFFF;
32'h33C: Data = 32'h01084038;
32'h340: Data = 32'h8c080004;
/*
* Overflow Exception
*/
/*
lw $t0, 0($0)
*/
32'hF0000000: Data = 32'h8c080000;
default: Data = 32'hXXXXXXXX;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_protocol_converter_v2_1_9_b2s
// WRITE_BUNDLE
// aw_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// w_channel_0
// b_channel_0
// READ_BUNDLE
// ar_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// r_channel_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_9_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_9_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_9_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_9_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_9_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_9_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- Divisor de reloj
//-- Señal de periodo igual al indicado
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == 0) ? 1 : 0;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_streaming #(
parameter PURPOSE = 0,
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// JTAG Signals
input wire tck,
input wire tdi,
output reg tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire reset_n,
// Source Signals
output wire [7:0] source_data,
output wire source_valid,
// Sink Signals
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
// Clock Debug Signals
input wire clock_to_sample,
input wire reset_to_sample,
// Resetrequest signal
output reg resetrequest,
// Debug reset and management channel
output wire debug_reset,
output reg mgmt_valid,
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output reg mgmt_data
);
// function to calculate log2, floored.
function integer flog2;
input [31:0] Depth;
integer i;
begin
i = Depth;
if ( i <= 0 ) flog2 = 0;
else begin
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// IR values determine the operating modes
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
// Operating Modes:
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
// Loopback - To become a JTAG loopback with a bypass register
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
// Control - To set the offset of bit-padding and to do a reset request
// Mgmt - Send management commands (resets mostly) to agents
localparam IRWIDTH = 3;
// State machine encoding for write_state
localparam ST_BYPASS = 'h0;
localparam ST_HEADER_1 = 'h1;
localparam ST_HEADER_2 = 'h2;
localparam ST_WRITE_DATA = 'h3;
// State machine encoding for read_state
localparam ST_HEADER = 'h0;
localparam ST_PADDED = 'h1;
localparam ST_READ_DATA = 'h2;
reg [1:0] write_state = ST_BYPASS;
reg [1:0] read_state = ST_HEADER;
reg [ 7:0] dr_data_in = 'b0;
reg [ 7:0] dr_data_out = 'b0;
reg dr_loopback = 'b0;
reg [ 2:0] dr_debug = 'b0;
reg [10:0] dr_info = 'b0;
reg [ 8:0] dr_control = 'b0;
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
reg [ 8:0] padded_bit_counter = 'b0;
reg [ 7:0] bypass_bit_counter = 'b0;
reg [ 2:0] write_data_bit_counter = 'b0;
reg [ 2:0] read_data_bit_counter = 'b0;
reg [ 3:0] header_in_bit_counter = 'b0;
reg [ 3:0] header_out_bit_counter = 'b0;
reg [18:0] scan_length_byte_counter = 'b0;
reg [18:0] valid_write_data_length_byte_counter = 'b0;
reg write_data_valid = 'b0;
reg read_data_valid = 'b0;
reg read_data_all_valid = 'b0;
reg decode_header_1 = 'b0;
reg decode_header_2 = 'b0;
wire write_data_byte_aligned;
wire read_data_byte_aligned;
wire padded_bit_byte_aligned;
wire bytestream_end;
assign write_data_byte_aligned = (write_data_bit_counter == 1);
assign read_data_byte_aligned = (read_data_bit_counter == 1);
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
assign bytestream_end = (scan_length_byte_counter == 'b0);
reg [ 7:0] offset = 'b0;
reg [15:0] header_in = 'b0;
reg [9:0] scan_length = 'b0;
reg [2:0] read_data_length = 'b0;
reg [2:0] write_data_length = 'b0;
wire [7:0] idle_inserter_sink_data;
wire idle_inserter_sink_valid;
wire idle_inserter_sink_ready;
wire [7:0] idle_inserter_source_data;
reg idle_inserter_source_ready = 'b0;
reg [7:0] idle_remover_sink_data = 'b0;
reg idle_remover_sink_valid = 'b0;
wire [7:0] idle_remover_source_data;
wire idle_remover_source_valid;
assign source_data = idle_remover_source_data;
assign source_valid = idle_remover_source_valid;
assign sink_ready = idle_inserter_sink_ready;
assign idle_inserter_sink_data = sink_data;
assign idle_inserter_sink_valid = sink_valid;
reg clock_sensor = 'b0;
reg clock_to_sample_div2 = 'b0;
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
wire data_available;
assign data_available = sink_valid;
wire [18:0] decoded_scan_length;
wire [18:0] decoded_write_data_length;
wire [18:0] decoded_read_data_length;
assign decoded_scan_length = { scan_length, {8{1'b1}} };
// +-------------------+----------------+---------------------+
// | scan_length | Length (bytes) | decoded_scan_length |
// +-------------------+----------------+---------------------+
// | 0x0 | 256 | 0x0ff (255) |
// | 0x1 | 512 | 0x1ff (511) |
// | 0x2 | 768 | 0x2ff (767) |
// | . | . | . |
// | 0x3ff | 256k | 0x3ff (256k-1) |
// +-------------------+----------------+---------------------+
// TODO: use look up table to save LEs?
// Decoded value is correct except for 0x7
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
// +-------------------+---------------+---------------------------+
// | read_data_length | Length | decoded_read_data_length |
// | write_data_length | (bytes) | decoded_write_data_length |
// +-------------------+---------------+---------------------------+
// | 0x0 | 0 | 0x0000 (0) |
// | 0x1 | 256 | 0x0100 (256) |
// | 0x2 | 512 | 0x0200 (512) |
// | 0x3 | 1k | 0x0400 (1024) |
// | 0x4 | 2k | 0x0800 (2048) |
// | 0x5 | 4k | 0x1000 (4096) |
// | 0x6 | 8k | 0x2000 (8192) |
// | 0x7 | scan_length | invalid |
// +-------------------+---------------+---------------------------+
wire clock_sensor_sync;
wire reset_to_sample_sync;
wire clock_to_sample_div2_sync;
wire clock_sense_reset_n_sync;
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_sensor),
.dout(clock_sensor_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(reset_to_sample),
.dout(reset_to_sample_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_to_sample_div2),
.dout(clock_to_sample_div2_sync));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
.clk(clock_to_sample),
.reset_n(clock_sense_reset_n),
.din(1'b1),
.dout(clock_sense_reset_n_sync));
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
if (~clock_sense_reset_n_sync) begin
clock_sensor <= 1'b0;
end else begin
clock_sensor <= 1'b1;
end
end
always @ (posedge clock_to_sample) begin
clock_to_sample_div2 <= ~clock_to_sample_div2;
end
always @ (posedge tck) begin
idle_remover_sink_valid <= 1'b0;
idle_inserter_source_ready <= 1'b0;
// Data mode sourcing (write)
// offset(rounded 8) m-i i 16 offset
// +------------+-----------+------------------+--------+------------+
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
// +------------+-----------+------------------+--------+------------+
// Data mode DR data stream write format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
if (offset == 'b0) begin
write_state <= ST_HEADER_1;
end else begin
write_state <= ST_BYPASS;
end
// 8-bit bypass_bit_counter
bypass_bit_counter <= offset;
// 4-bit header_in_bit_counter
header_in_bit_counter <= 15;
// 3-bit write_data_bit_counter
write_data_bit_counter <= 0;
// Reset the registers
// TODO: not necessarily all, reduce LE
decode_header_1 <= 1'b0;
decode_header_2 <= 1'b0;
read_data_all_valid <= 1'b0;
valid_write_data_length_byte_counter <= 0;
end
if (virtual_state_sdr) begin
// Discard bypass bits, then decode the 16-bit header
// 3 3 10
// +-------------------+------------------+-------------+
// | write_data_length | read_data_length | scan_length |
// +-------------------+------------------+-------------+
// Header format
case (write_state)
ST_BYPASS: begin
// Discard the bypass bit
bypass_bit_counter <= bypass_bit_counter - 1'b1;
if (bypass_bit_counter == 1) begin
write_state <= ST_HEADER_1;
end
end
// Shift the scan_length and read_data_length
ST_HEADER_1: begin
// TODO: header_in can be shorter
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
if (header_in_bit_counter == 3) begin
read_data_length <= {tdi, header_in[15:14]};
scan_length <= header_in[13:4];
write_state <= ST_HEADER_2;
decode_header_1 <= 1'b1;
end
end
// Shift the write_data_length
ST_HEADER_2: begin
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
// Decode read_data_length and scan_length
if (decode_header_1) begin
decode_header_1 <= 1'b0;
// Set read_data_all_valid
if (read_data_length == 3'b111) begin
read_data_all_valid <= 1'b1;
end
// Load scan_length_byte_counter
scan_length_byte_counter <= decoded_scan_length;
end
if (header_in_bit_counter == 0) begin
write_data_length <= {tdi, header_in[15:14]};
write_state <= ST_WRITE_DATA;
decode_header_2 <= 1'b1;
end
end
// Shift the valid_write_data
ST_WRITE_DATA: begin
// Shift into dr_data_in
dr_data_in <= {tdi, dr_data_in[7:1]};
// Decode write_data_length
if (decode_header_2) begin
decode_header_2 <= 1'b0;
// Load valid_write_data_length_byte_counter
case (write_data_length)
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
3'b000: valid_write_data_length_byte_counter <= 'b0;
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
endcase
end
write_data_bit_counter <= write_data_bit_counter - 1'b1;
write_data_valid <= (valid_write_data_length_byte_counter != 0);
// Feed the data to the idle remover
if (write_data_byte_aligned && write_data_valid) begin
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
idle_remover_sink_valid <= 1'b1;
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
end
end
endcase
end
end
// Data mode sinking (read)
// i m-i offset(rounded 8) 16
// +-----------------+-----------+------------+--------+
// | valid_read_data | undefined | padded_bit | header | -> tdo
// +-----------------+-----------+------------+--------+
// Data mode DR data stream read format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
read_state <= ST_HEADER;
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
// 9-bit padded_bit_counter
if (|offset[2:0]) begin
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
padded_bit_counter[2:0] <= 3'b0;
end else begin
padded_bit_counter <= {1'b0, offset};
end
// 4-bit header_out_bit_counter
header_out_bit_counter <= 0;
// 3-bit read_data_bit_counter
read_data_bit_counter <= 0;
// Load the data_available bit into header
dr_data_out <= {{7{1'b0}}, data_available};
read_data_valid <= 0;
end
if (virtual_state_sdr) begin
// 10 1
// +-----------------------------------+----------------+
// | reserved | data_available |
// +-----------------------------------+----------------+
// Header format
dr_data_out <= {1'b0, dr_data_out[7:1]};
case (read_state)
// Shift the scan_length and read_data_length
ST_HEADER: begin
header_out_bit_counter <= header_out_bit_counter - 1'b1;
// Retrieve data from idle inserter for the next shift if no paddded bits
if (header_out_bit_counter == 2) begin
if (padded_bit_counter == 0) begin
idle_inserter_source_ready <= read_data_all_valid;
end
end
if (header_out_bit_counter == 1) begin
if (padded_bit_counter == 0) begin
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end else begin
read_state <= ST_PADDED;
padded_bit_counter <= padded_bit_counter - 1'b1;
idle_inserter_source_ready <= 1'b0;
dr_data_out <= 8'h4a;
end
end
end
ST_PADDED: begin
padded_bit_counter <= padded_bit_counter - 1'b1;
if (padded_bit_byte_aligned) begin
// Load idle character into data register
dr_data_out <= 8'h4a;
end
// Retrieve data from idle inserter for the next shift when padded bits finish
if (padded_bit_counter == 1) begin
idle_inserter_source_ready <= read_data_all_valid;
end
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end
end
ST_READ_DATA: begin
read_data_bit_counter <= read_data_bit_counter - 1'b1;
// Retrieve data from idle inserter just before read_data_byte_aligned
if (read_data_bit_counter == 2) begin
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
end
if (read_data_byte_aligned) begin
// Note that bytestream_end is driven by scan_length_byte_counter
if (~bytestream_end) begin
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
end
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
// Load idle character if bytestream has ended, else get data from the idle inserter
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
end
end
endcase
end
end
// Loopback mode
if (ir_in == LOOPBACK) begin
if (virtual_state_cdr) begin
dr_loopback <= 1'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_loopback
dr_loopback <= tdi;
end
end
// Debug mode
if (ir_in == DEBUG) begin
if (virtual_state_cdr) begin
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
end
if (virtual_state_udr) begin
clock_sense_reset_n <= 1'b0;
end else begin
clock_sense_reset_n <= 1'b1;
end
end
// Info mode
if (ir_in == INFO) begin
if (virtual_state_cdr) begin
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
end
if (virtual_state_sdr) begin
// Shift dr_info
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
end
end
// Control mode
if (ir_in == CONTROL) begin
if (virtual_state_cdr) begin
dr_control <= 'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_control
dr_control <= {tdi, dr_control[8:1]};
end
if (virtual_state_udr) begin
// Update resetrequest and offset
{resetrequest, offset} <= dr_control;
end
end
end
always @ * begin
if (virtual_state_sdr) begin
case (ir_in)
DATA: tdo <= dr_data_out[0];
LOOPBACK: tdo <= dr_loopback;
DEBUG: tdo <= dr_debug[0];
INFO: tdo <= dr_info[0];
CONTROL: tdo <= dr_control[0];
MGMT: tdo <= dr_mgmt[0];
default: tdo <= 1'b0;
endcase
end else begin
tdo <= 1'b0;
end
end
// Idle Remover
altera_avalon_st_idle_remover idle_remover (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (), // left disconnected
.in_valid (idle_remover_sink_valid),
.in_data (idle_remover_sink_data),
// Interface: ST out
.out_ready (1'b1), // downstream is expected to be always ready
.out_valid (idle_remover_source_valid),
.out_data (idle_remover_source_data)
);
// Idle Inserter
altera_avalon_st_idle_inserter idle_inserter (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (idle_inserter_sink_ready),
.in_valid (idle_inserter_sink_valid),
.in_data (idle_inserter_sink_data),
// Interface: ST out
.out_ready (idle_inserter_source_ready),
.out_valid (),
.out_data (idle_inserter_source_data)
);
generate
if (MGMT_CHANNEL_WIDTH > 0)
begin : has_mgmt
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
reg mgmt_toggle = 1'b0;
wire mgmt_toggle_sync;
reg mgmt_toggle_prev;
always @ (posedge tck) begin
// Debug mode
if (ir_in == MGMT) begin
if (virtual_state_cdr) begin
dr_mgmt <= 'b0;
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
end
if (virtual_state_udr) begin
mgmt_out <= dr_mgmt;
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
end
end
end
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
.dout(debug_reset));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_toggle),
.dout(mgmt_toggle_sync));
always @ (posedge clock_to_sample or posedge debug_reset) begin
if (debug_reset) begin
mgmt_valid <= 1'b0;
mgmt_toggle_prev <= 1'b0;
end else begin
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
mgmt_valid <= 1'b1;
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
mgmt_data <= mgmt_out[0];
end else begin
mgmt_valid <= 1'b0;
end
mgmt_toggle_prev <= mgmt_toggle_sync;
end
end
end
else
begin : no_mgmt
always @ (posedge tck) begin
dr_mgmt[0] <= 1'b0;
end
assign debug_reset = 1'b0;
always @ (posedge clock_to_sample) begin
mgmt_valid <= 1'b0;
mgmt_data <= 'b0;
mgmt_channel <= 'b0;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s (
Q ,
D ,
CLK_N ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK_N ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
|
// limbus_sram.v
// This file was auto-generated from altera_generic_tristate_controller_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_sram #(
parameter TCM_ADDRESS_W = 19,
parameter TCM_DATA_W = 16,
parameter TCM_BYTEENABLE_W = 2,
parameter TCM_READ_WAIT = 10,
parameter TCM_WRITE_WAIT = 10,
parameter TCM_SETUP_WAIT = 10,
parameter TCM_DATA_HOLD = 10,
parameter TCM_TURNAROUND_TIME = 2,
parameter TCM_TIMING_UNITS = 0,
parameter TCM_READLATENCY = 2,
parameter TCM_SYMBOLS_PER_WORD = 2,
parameter USE_READDATA = 1,
parameter USE_WRITEDATA = 1,
parameter USE_READ = 0,
parameter USE_WRITE = 1,
parameter USE_BYTEENABLE = 1,
parameter USE_CHIPSELECT = 1,
parameter USE_LOCK = 0,
parameter USE_ADDRESS = 1,
parameter USE_WAITREQUEST = 0,
parameter USE_WRITEBYTEENABLE = 0,
parameter USE_OUTPUTENABLE = 1,
parameter USE_RESETREQUEST = 0,
parameter USE_IRQ = 0,
parameter USE_RESET_OUTPUT = 0,
parameter ACTIVE_LOW_READ = 0,
parameter ACTIVE_LOW_LOCK = 0,
parameter ACTIVE_LOW_WRITE = 1,
parameter ACTIVE_LOW_CHIPSELECT = 1,
parameter ACTIVE_LOW_BYTEENABLE = 1,
parameter ACTIVE_LOW_OUTPUTENABLE = 1,
parameter ACTIVE_LOW_WRITEBYTEENABLE = 0,
parameter ACTIVE_LOW_WAITREQUEST = 0,
parameter ACTIVE_LOW_BEGINTRANSFER = 0,
parameter CHIPSELECT_THROUGH_READLATENCY = 0
) (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
input wire [18:0] uas_address, // uas.address
input wire [1:0] uas_burstcount, // .burstcount
input wire uas_read, // .read
input wire uas_write, // .write
output wire uas_waitrequest, // .waitrequest
output wire uas_readdatavalid, // .readdatavalid
input wire [1:0] uas_byteenable, // .byteenable
output wire [15:0] uas_readdata, // .readdata
input wire [15:0] uas_writedata, // .writedata
input wire uas_lock, // .lock
input wire uas_debugaccess, // .debugaccess
output wire tcm_write_n_out, // tcm.write_n_out
output wire tcm_chipselect_n_out, // .chipselect_n_out
output wire tcm_outputenable_n_out, // .outputenable_n_out
output wire tcm_request, // .request
input wire tcm_grant, // .grant
output wire [18:0] tcm_address_out, // .address_out
output wire [1:0] tcm_byteenable_n_out, // .byteenable_n_out
output wire [15:0] tcm_data_out, // .data_out
output wire tcm_data_outen, // .data_outen
input wire [15:0] tcm_data_in // .data_in
);
wire tdt_conduit_start_request; // tdt:c0_request -> tda:c0_request
wire tda_conduit_end_grant; // tda:c0_grant -> tdt:c0_grant
wire tdt_conduit_start_uav_write; // tdt:c0_uav_write -> tda:c0_uav_write
wire tdt_avalon_universal_master_0_waitrequest; // slave_translator:uav_waitrequest -> tdt:m0_uav_waitrequest
wire [15:0] tdt_avalon_universal_master_0_readdata; // slave_translator:uav_readdata -> tdt:m0_uav_readdata
wire tdt_avalon_universal_master_0_debugaccess; // tdt:m0_uav_debugaccess -> slave_translator:uav_debugaccess
wire [18:0] tdt_avalon_universal_master_0_address; // tdt:m0_uav_address -> slave_translator:uav_address
wire tdt_avalon_universal_master_0_read; // tdt:m0_uav_read -> slave_translator:uav_read
wire [1:0] tdt_avalon_universal_master_0_byteenable; // tdt:m0_uav_byteenable -> slave_translator:uav_byteenable
wire tdt_avalon_universal_master_0_readdatavalid; // slave_translator:uav_readdatavalid -> tdt:m0_uav_readdatavalid
wire tdt_avalon_universal_master_0_lock; // tdt:m0_uav_lock -> slave_translator:uav_lock
wire tdt_avalon_universal_master_0_write; // tdt:m0_uav_write -> slave_translator:uav_write
wire [15:0] tdt_avalon_universal_master_0_writedata; // tdt:m0_uav_writedata -> slave_translator:uav_writedata
wire [1:0] tdt_avalon_universal_master_0_burstcount; // tdt:m0_uav_burstcount -> slave_translator:uav_burstcount
wire slave_translator_avalon_anti_slave_0_chipselect; // slave_translator:av_chipselect -> tda:av_chipselect
wire [15:0] slave_translator_avalon_anti_slave_0_readdata; // tda:av_readdata -> slave_translator:av_readdata
wire slave_translator_avalon_anti_slave_0_outputenable; // slave_translator:av_outputenable -> tda:av_outputenable
wire [18:0] slave_translator_avalon_anti_slave_0_address; // slave_translator:av_address -> tda:av_address
wire [1:0] slave_translator_avalon_anti_slave_0_byteenable; // slave_translator:av_byteenable -> tda:av_byteenable
wire slave_translator_avalon_anti_slave_0_write; // slave_translator:av_write -> tda:av_write
wire [15:0] slave_translator_avalon_anti_slave_0_writedata; // slave_translator:av_writedata -> tda:av_writedata
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (TCM_ADDRESS_W != 19)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_address_w_check ( .error(1'b1) );
end
if (TCM_DATA_W != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_data_w_check ( .error(1'b1) );
end
if (TCM_BYTEENABLE_W != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_byteenable_w_check ( .error(1'b1) );
end
if (TCM_READ_WAIT != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_read_wait_check ( .error(1'b1) );
end
if (TCM_WRITE_WAIT != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_write_wait_check ( .error(1'b1) );
end
if (TCM_SETUP_WAIT != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_setup_wait_check ( .error(1'b1) );
end
if (TCM_DATA_HOLD != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_data_hold_check ( .error(1'b1) );
end
if (TCM_TURNAROUND_TIME != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_turnaround_time_check ( .error(1'b1) );
end
if (TCM_TIMING_UNITS != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_timing_units_check ( .error(1'b1) );
end
if (TCM_READLATENCY != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_readlatency_check ( .error(1'b1) );
end
if (TCM_SYMBOLS_PER_WORD != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tcm_symbols_per_word_check ( .error(1'b1) );
end
if (USE_READDATA != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_readdata_check ( .error(1'b1) );
end
if (USE_WRITEDATA != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_writedata_check ( .error(1'b1) );
end
if (USE_READ != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_read_check ( .error(1'b1) );
end
if (USE_WRITE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_write_check ( .error(1'b1) );
end
if (USE_BYTEENABLE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_byteenable_check ( .error(1'b1) );
end
if (USE_CHIPSELECT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_chipselect_check ( .error(1'b1) );
end
if (USE_LOCK != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_lock_check ( .error(1'b1) );
end
if (USE_ADDRESS != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_address_check ( .error(1'b1) );
end
if (USE_WAITREQUEST != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_waitrequest_check ( .error(1'b1) );
end
if (USE_WRITEBYTEENABLE != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_writebyteenable_check ( .error(1'b1) );
end
if (USE_OUTPUTENABLE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_outputenable_check ( .error(1'b1) );
end
if (USE_RESETREQUEST != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_resetrequest_check ( .error(1'b1) );
end
if (USE_IRQ != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_irq_check ( .error(1'b1) );
end
if (USE_RESET_OUTPUT != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_reset_output_check ( .error(1'b1) );
end
if (ACTIVE_LOW_READ != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_read_check ( .error(1'b1) );
end
if (ACTIVE_LOW_LOCK != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_lock_check ( .error(1'b1) );
end
if (ACTIVE_LOW_WRITE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_write_check ( .error(1'b1) );
end
if (ACTIVE_LOW_CHIPSELECT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_chipselect_check ( .error(1'b1) );
end
if (ACTIVE_LOW_BYTEENABLE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_byteenable_check ( .error(1'b1) );
end
if (ACTIVE_LOW_OUTPUTENABLE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_outputenable_check ( .error(1'b1) );
end
if (ACTIVE_LOW_WRITEBYTEENABLE != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_writebyteenable_check ( .error(1'b1) );
end
if (ACTIVE_LOW_WAITREQUEST != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_waitrequest_check ( .error(1'b1) );
end
if (ACTIVE_LOW_BEGINTRANSFER != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
active_low_begintransfer_check ( .error(1'b1) );
end
if (CHIPSELECT_THROUGH_READLATENCY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
chipselect_through_readlatency_check ( .error(1'b1) );
end
endgenerate
altera_tristate_controller_translator #(
.UAV_DATA_W (16),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (2),
.ZERO_WRITE_DELAY (0),
.ZERO_READ_DELAY (0),
.TURNAROUND_TIME_CYCLES (1),
.READLATENCY_CYCLES (2)
) tdt (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.s0_uav_address (uas_address), // avalon_universal_slave_0.address
.s0_uav_burstcount (uas_burstcount), // .burstcount
.s0_uav_read (uas_read), // .read
.s0_uav_write (uas_write), // .write
.s0_uav_waitrequest (uas_waitrequest), // .waitrequest
.s0_uav_readdatavalid (uas_readdatavalid), // .readdatavalid
.s0_uav_byteenable (uas_byteenable), // .byteenable
.s0_uav_readdata (uas_readdata), // .readdata
.s0_uav_writedata (uas_writedata), // .writedata
.s0_uav_lock (uas_lock), // .lock
.s0_uav_debugaccess (uas_debugaccess), // .debugaccess
.m0_uav_address (tdt_avalon_universal_master_0_address), // avalon_universal_master_0.address
.m0_uav_burstcount (tdt_avalon_universal_master_0_burstcount), // .burstcount
.m0_uav_read (tdt_avalon_universal_master_0_read), // .read
.m0_uav_write (tdt_avalon_universal_master_0_write), // .write
.m0_uav_waitrequest (tdt_avalon_universal_master_0_waitrequest), // .waitrequest
.m0_uav_readdatavalid (tdt_avalon_universal_master_0_readdatavalid), // .readdatavalid
.m0_uav_byteenable (tdt_avalon_universal_master_0_byteenable), // .byteenable
.m0_uav_readdata (tdt_avalon_universal_master_0_readdata), // .readdata
.m0_uav_writedata (tdt_avalon_universal_master_0_writedata), // .writedata
.m0_uav_lock (tdt_avalon_universal_master_0_lock), // .lock
.m0_uav_debugaccess (tdt_avalon_universal_master_0_debugaccess), // .debugaccess
.c0_request (tdt_conduit_start_request), // conduit_start.request
.c0_grant (tda_conduit_end_grant), // .grant
.c0_uav_write (tdt_conduit_start_uav_write) // .uav_write
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (2),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (1),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (1),
.AV_DATA_HOLD_CYCLES (1)
) slave_translator (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.uav_address (tdt_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (tdt_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (tdt_avalon_universal_master_0_read), // .read
.uav_write (tdt_avalon_universal_master_0_write), // .write
.uav_waitrequest (tdt_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (tdt_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (tdt_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (tdt_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (tdt_avalon_universal_master_0_writedata), // .writedata
.uav_lock (tdt_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (tdt_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (slave_translator_avalon_anti_slave_0_write), // .write
.av_readdata (slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_outputenable (slave_translator_avalon_anti_slave_0_outputenable), // .outputenable
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_tristate_controller_aggregator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (16),
.AV_BYTEENABLE_W (2)
) tda (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.tcm0_write_n (tcm_write_n_out), // tristate_conduit_master_0.write_n_out
.tcm0_chipselect_n (tcm_chipselect_n_out), // .chipselect_n_out
.tcm0_outputenable_n (tcm_outputenable_n_out), // .outputenable_n_out
.tcm0_request (tcm_request), // .request
.tcm0_grant (tcm_grant), // .grant
.tcm0_address (tcm_address_out), // .address_out
.tcm0_byteenable_n (tcm_byteenable_n_out), // .byteenable_n_out
.tcm0_writedata (tcm_data_out), // .data_out
.tcm0_data_outen (tcm_data_outen), // .data_outen
.tcm0_readdata (tcm_data_in), // .data_in
.av_write (slave_translator_avalon_anti_slave_0_write), // avalon_slave_0.write
.av_chipselect (slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_outputenable (slave_translator_avalon_anti_slave_0_outputenable), // .outputenable
.av_address (slave_translator_avalon_anti_slave_0_address), // .address
.av_byteenable (slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_writedata (slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_readdata (slave_translator_avalon_anti_slave_0_readdata), // .readdata
.c0_request (tdt_conduit_start_request), // conduit_end.request
.c0_grant (tda_conduit_end_grant), // .grant
.c0_uav_write (tdt_conduit_start_uav_write), // .uav_write
.tcm0_write (), // (terminated)
.av_lock (1'b0), // (terminated)
.tcm0_lock (), // (terminated)
.tcm0_lock_n (), // (terminated)
.av_read (1'b0), // (terminated)
.tcm0_read (), // (terminated)
.tcm0_read_n (), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.tcm0_begintransfer (), // (terminated)
.tcm0_begintransfer_n (), // (terminated)
.tcm0_chipselect (), // (terminated)
.tcm0_outputenable (), // (terminated)
.av_waitrequest (), // (terminated)
.tcm0_waitrequest (1'b0), // (terminated)
.tcm0_waitrequest_n (1'b0), // (terminated)
.reset_out (), // (terminated)
.tcm0_resetrequest (1'b0), // (terminated)
.tcm0_resetrequest_n (1'b1), // (terminated)
.tcm0_irq_in (1'b0), // (terminated)
.tcm0_irq_in_n (1'b1), // (terminated)
.irq_out (), // (terminated)
.tcm0_reset_output (), // (terminated)
.tcm0_reset_output_n (), // (terminated)
.tcm0_byteenable (), // (terminated)
.av_writebyteenable (2'b00), // (terminated)
.tcm0_writebyteenable (), // (terminated)
.tcm0_writebyteenable_n () // (terminated)
);
endmodule
|
// Select between clk1 and clk2
// clk1 is expected to have higher priority compared to clk2
// (if clk1 and clk2 are requested we output clk1)
module clock_selector (/*AUTOARG*/
// Outputs
ack_clk1, ack_clk2, clkout,
// Inputs
clk1, clk2, req_clk1, req_clk2, select, rst_n
);
input clk1;
input clk2;
input req_clk1;
output ack_clk1;
input req_clk2;
output ack_clk2;
output clkout;
input select; // To be removed
input rst_n; // Fixme - synchronized reset for clk1/clk2 is needed (or a POR like reset)
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg ack_clk1;
reg ack_clk2;
// End of automatics
/*AUTOWIRE*/
// for now a very simple implementation without the arbitration done correctly
wire select; // 0 : clk1, 1 : clk2
wire select1_a;
reg select1_m;
reg select1_r;
wire select2_a;
reg select2_m;
reg select2_r;
wire clkout;
assign select1_a = !select &!select2_r;
assign select2_a = select &!select1_r;
// We use posedge DFFs
always @(posedge clk1 or negedge rst_n) begin
if(rst_n == 1'b0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
select1_m <= 1'h0;
select1_r <= 1'h0;
// End of automatics
end
else begin
select1_m <= select1_a;
select1_r <= select1_m;
end
end
always @(posedge clk2 or negedge rst_n) begin
if(rst_n == 1'b0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
select2_m <= 1'h0;
select2_r <= 1'h0;
// End of automatics
end
else begin
select2_m <= select2_a;
select2_r <= select2_m;
end
end
// we use posedge FF above, so we have to be carefull
assign clkout = ((!clk1 & select1_r) | (!clk2 & select2_r));
endmodule // clock_selector
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
/* wb_mux_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
`default_nettype none
module wb_mux_tb
#(parameter AUTORUN = 1);
localparam NUM_SLAVES = 4;
localparam aw = 32;
localparam dw = 32;
localparam SEGMENT_SIZE = 32'h100;
localparam MEMORY_SIZE_BITS = 8;
/*TODO: Find a way to generate MATCH_ADDR and MATCH_MASK based on memory
size and number of slaves. Missing support for constant
user functions in Icarus Verilog is the blocker for this*/
localparam [dw*NUM_SLAVES-1:0] MATCH_ADDR = {32'h00000300,
32'h00000200,
32'h00000100,
32'h00000000};
localparam [dw*NUM_SLAVES-1:0] MATCH_MASK = {NUM_SLAVES{32'hffffff00}};
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
wire [NUM_SLAVES*aw-1:0] wbs_m2s_adr;
wire [NUM_SLAVES*dw-1:0] wbs_m2s_dat;
wire [NUM_SLAVES*4-1:0] wbs_m2s_sel;
wire [NUM_SLAVES-1:0] wbs_m2s_we ;
wire [NUM_SLAVES-1:0] wbs_m2s_cyc;
wire [NUM_SLAVES-1:0] wbs_m2s_stb;
wire [NUM_SLAVES*3-1:0] wbs_m2s_cti;
wire [NUM_SLAVES*2-1:0] wbs_m2s_bte;
wire [NUM_SLAVES*dw-1:0] wbs_s2m_dat;
wire [NUM_SLAVES-1:0] wbs_s2m_ack;
wire [NUM_SLAVES-1:0] wbs_s2m_err;
wire [NUM_SLAVES-1:0] wbs_s2m_rty;
wire [aw-1:0] wb_m2s_adr;
wire [dw-1:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we ;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [2:0] wb_m2s_cti;
wire [1:0] wb_m2s_bte;
wire [dw-1:0] wb_s2m_dat;
wire wb_s2m_ack;
wire wb_s2m_err;
wire wb_s2m_rty;
wire [31:0] slave_writes [0:NUM_SLAVES-1];
wire [31:0] slave_reads [0:NUM_SLAVES-1];
genvar i;
integer TRANSACTIONS;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_mux.tap", 1) vtg();
initial begin
#100 run;
vtg.ok("wb_mux: All tests passed!");
$finish;
end
end
endgenerate
task run;
integer idx;
begin
wb_rst = 1'b0;
if($value$plusargs("transactions=%d", TRANSACTIONS))
transactor.set_transactions(TRANSACTIONS);
transactor.display_settings;
transactor.run();
transactor.display_stats;
for(idx=0;idx<NUM_SLAVES;idx=idx+1) begin
$display("%0d writes to slave %0d", slave_writes[idx], idx);
end
end
endtask
always #5 wb_clk <= ~wb_clk;
wb_bfm_transactor
#(.NUM_SEGMENTS (NUM_SLAVES),
.AUTORUN (0),
.VERBOSE (0),
.SEGMENT_SIZE (SEGMENT_SIZE))
transactor
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_o (wb_m2s_adr),
.wb_dat_o (wb_m2s_dat),
.wb_sel_o (wb_m2s_sel),
.wb_we_o (wb_m2s_we ),
.wb_cyc_o (wb_m2s_cyc),
.wb_stb_o (wb_m2s_stb),
.wb_cti_o (wb_m2s_cti),
.wb_bte_o (wb_m2s_bte),
.wb_dat_i (wb_s2m_dat),
.wb_ack_i (wb_s2m_ack),
.wb_err_i (wb_s2m_err),
.wb_rty_i (wb_s2m_rty),
//Test Control
.done());
wb_mux
#(.num_slaves(NUM_SLAVES),
.MATCH_ADDR (MATCH_ADDR),
.MATCH_MASK (MATCH_MASK))
wb_mux0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
// Master Interface
.wbm_adr_i (wb_m2s_adr),
.wbm_dat_i (wb_m2s_dat),
.wbm_sel_i (wb_m2s_sel),
.wbm_we_i (wb_m2s_we ),
.wbm_cyc_i (wb_m2s_cyc),
.wbm_stb_i (wb_m2s_stb),
.wbm_cti_i (wb_m2s_cti),
.wbm_bte_i (wb_m2s_bte),
.wbm_dat_o (wb_s2m_dat),
.wbm_ack_o (wb_s2m_ack),
.wbm_err_o (wb_s2m_err),
.wbm_rty_o (wb_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
generate
for(i=0;i<NUM_SLAVES;i=i+1) begin : slaves
assign slave_writes[i] = wb_mem_model0.writes;
assign slave_reads[i] = wb_mem_model0.reads;
wb_bfm_memory #(.DEBUG (0),
.mem_size_bytes(SEGMENT_SIZE))
wb_mem_model0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wbs_m2s_adr[i*aw+:aw] & (2**MEMORY_SIZE_BITS-1)),
.wb_dat_i (wbs_m2s_dat[i*dw+:dw]),
.wb_sel_i (wbs_m2s_sel[i*4+:4]),
.wb_we_i (wbs_m2s_we[i]),
.wb_cyc_i (wbs_m2s_cyc[i]),
.wb_stb_i (wbs_m2s_stb[i]),
.wb_cti_i (wbs_m2s_cti[i*3+:3]),
.wb_bte_i (wbs_m2s_bte[i*2+:2]),
.wb_dat_o (wbs_s2m_dat[i*dw+:dw]),
.wb_ack_o (wbs_s2m_ack[i]),
.wb_err_o (wbs_s2m_err[i]),
.wb_rty_o (wbs_s2m_rty[i]));
end // block: slaves
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 24 13:58:19 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_3/part_1/ip/clk_193MHz/clk_193MHz_stub.v
// Design : clk_193MHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_193MHz(clk_100MHz, clk_193MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_100MHz,clk_193MHz,locked" */;
input clk_100MHz;
output clk_193MHz;
output locked;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Driss Hafdi
// SPDX-License-Identifier: CC0-1.0
interface validData
(
input wire clk,
input wire rst
);
logic data;
logic valid;
modport sink
(
input data, valid, clk, rst
);
modport source
(
input clk, rst,
output data, valid
);
endinterface
module sinkMod
(
validData.sink ctrl,
output logic valid_data
);
always_ff @(posedge ctrl.clk) begin
if (ctrl.valid) valid_data <= ctrl.data;
end
endmodule
module sourceMod
(
validData.source ctrl
);
always_ff @(posedge ctrl.clk) begin
ctrl.data <= ~ctrl.data;
ctrl.valid <= ~ctrl.valid;
end
endmodule
module parentSourceMod
(
validData.sink ctrl
);
sourceMod source_i (.ctrl);
endmodule
module t (/*AUTOARG*/
// Outputs
data,
// Inputs
clk, rst
);
input clk;
input rst;
output logic data;
validData ctrl(.clk, .rst);
sinkMod sink_i (.ctrl, .valid_data(data));
parentSourceMod source_i (.ctrl);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_rows_V_2_loc_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_rows_V_2_loc_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_rows_V_2_loc_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_rows_V_2_loc_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [60:0] p;
reg [60:0] a;
reg [20:0] b;
reg [60:0] shifted;
always @* begin
p = a[60:0] ** b[20:0];
shifted = 2 ** b[20:0];
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%0x %x %x\n", cyc, p, shifted);
`endif
// Constant versions
if (61'h1 ** 21'h31 != 61'h1) $stop;
if (61'h2 ** 21'h10 != 61'h10000) $stop;
if (61'd10 ** 21'h3 != 61'h3e8) $stop;
if (61'h3 ** 21'h7 != 61'h88b) $stop;
if (61'h7ab3811219 ** 21'ha6e30 != 61'h01ea58c703687e81) $stop;
if (cyc==1) begin
a <= 61'h0;
b <= 21'h0;
end
if (cyc==2) begin
a <= 61'h0;
b <= 21'h3;
end
if (cyc==3) begin
a <= 61'h1;
b <= 21'h31;
end
if (cyc==4) begin
a <= 61'h2;
b <= 21'h10;
end
if (cyc==5) begin
a <= 61'd10;
b <= 21'd3;
end
if (cyc==6) begin
a <= 61'd3;
b <= 21'd7;
end
if (cyc==7) begin
a <= 61'h7ab3811219;
b <= 21'ha6e30;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
case (cyc)
32'd00: ;
32'd01: ;
32'd02: ; // 0^x is indeterminate
32'd03: ; // 0^x is indeterminate
32'd04: if (p!=61'h1) $stop;
32'd05: if (p!=61'h10000) $stop;
32'd06: if (p!=61'h3e8) $stop;
32'd07: if (p!=61'h88b) $stop;
32'd08: if (p!=61'h01ea58c703687e81) $stop;
32'd09: if (p!=61'h01ea58c703687e81) $stop;
default: $stop;
endcase
case (cyc)
32'd00: ;
32'd01: ;
32'd02: if (shifted!=61'h0000000000000001) $stop;
32'd03: if (shifted!=61'h0000000000000008) $stop;
32'd04: if (shifted!=61'h0002000000000000) $stop;
32'd05: if (shifted!=61'h0000000000010000) $stop;
32'd06: if (shifted!=61'h0000000000000008) $stop;
32'd07: if (shifted!=61'h0000000000000080) $stop;
32'd08: if (shifted!=61'h0000000000000000) $stop;
32'd09: if (shifted!=61'h0000000000000000) $stop;
default: $stop;
endcase
end
endmodule
|
//-------------------------------------------------------------------
//-- scicad2_tb
//-- Banco de pruebas para el ejemplo de transmision temporizada
//-------------------------------------------------------------------
//-- BQ September 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module scicad2_tb();
//-- Baudios con los que realizar la simulacion
localparam BAUD = `B115200;
localparam DELAY = 10000;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Instanciar el componente
scicad2 #(.BAUD(BAUD), .DELAY(DELAY))
dut(
.clk(clk),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("scicad2_tb.vcd");
$dumpvars(0, scicad2_tb);
#(FRAME * 20) $display("FIN de la simulacion");
$finish;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg1_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg1_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg1-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg1-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Manually created global mem, to avoid qsys hex generation bug
// qsys will always generate a .hex file to initialize the
// altsyncram - EVEN if you specify not to init the ram,
// for big ram's, this causes qsys to hang
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module bram_256x67M (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter DEPTH = 67108864;
parameter NWORDS_A = 67108864;
parameter ADDR_WIDTH = 26; // this should be $clog( DEPTH ), but qsys dies;
output [255: 0] readdata;
// ADDR_WIDTH
input [ 25: 0] address;
input [ 31: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [255: 0] writedata;
reg [255: 0] readdata;
wire [255: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = DEPTH,
the_altsyncram.numwords_a = NWORDS_A,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 256,
the_altsyncram.width_byteena_a = 32,
the_altsyncram.widthad_a = ADDR_WIDTH;
//////////////// END SIMULATION-ONLY CONTENTS
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: apB.v
// /___/ /\ Timestamp: Thu Mar 26 19:43:13 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/apB.ngc /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/apB.v
// Device : 3s500efg320-4
// Input file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/apB.ngc
// Output file : /home/vka/Programming/VHDL/workspace/sysrek/arithm/ipcore_dir/tmp/_cg/apB.v
// # of Modules : 1
// Design Name : apB
// Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module apB (
clk, ce, s, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
output [18 : 0] s;
input [17 : 0] a;
input [17 : 0] b;
// synthesis translate_off
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \NLW_blk00000001/blk0000001d_O_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006b ),
.Q(s[0])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000007e (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000003b ),
.Q(\blk00000001/sig0000006b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006c ),
.Q(s[1])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000007c (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000003c ),
.Q(\blk00000001/sig0000006c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006d ),
.Q(s[2])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000007a (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000003d ),
.Q(\blk00000001/sig0000006d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000079 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006e ),
.Q(s[3])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000078 (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000003e ),
.Q(\blk00000001/sig0000006e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000077 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006f ),
.Q(s[4])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000076 (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000006f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000075 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000070 ),
.Q(s[5])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000074 (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000040 ),
.Q(\blk00000001/sig00000070 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000073 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000072 ),
.Q(s[7])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000072 (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000042 ),
.Q(\blk00000001/sig00000072 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000071 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000073 ),
.Q(s[8])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000070 (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000043 ),
.Q(\blk00000001/sig00000073 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000006f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000071 ),
.Q(s[6])
);
SRL16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000006e (
.A0(\blk00000001/sig00000027 ),
.A1(\blk00000001/sig00000027 ),
.A2(\blk00000001/sig00000027 ),
.A3(\blk00000001/sig00000027 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000041 ),
.Q(\blk00000001/sig00000071 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000006d (
.I0(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000099 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig00000058 ),
.O(\blk00000001/sig00000098 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000006b (
.I0(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000090 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000006a (
.I0(\blk00000001/sig0000005a ),
.O(\blk00000001/sig00000091 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig0000005b ),
.O(\blk00000001/sig00000092 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000068 (
.I0(\blk00000001/sig0000005c ),
.O(\blk00000001/sig00000093 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000067 (
.I0(\blk00000001/sig0000005d ),
.O(\blk00000001/sig00000094 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000066 (
.I0(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000095 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000065 (
.I0(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000096 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000064 (
.I0(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000097 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000063 (
.I0(b[9]),
.I1(a[9]),
.O(\blk00000001/sig0000004d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000062 (
.I0(b[0]),
.I1(a[0]),
.O(\blk00000001/sig00000031 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000061 (
.I0(b[10]),
.I1(a[10]),
.O(\blk00000001/sig0000004e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000060 (
.I0(b[1]),
.I1(a[1]),
.O(\blk00000001/sig00000032 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005f (
.I0(b[11]),
.I1(a[11]),
.O(\blk00000001/sig0000004f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005e (
.I0(b[2]),
.I1(a[2]),
.O(\blk00000001/sig00000033 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005d (
.I0(b[12]),
.I1(a[12]),
.O(\blk00000001/sig00000050 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005c (
.I0(b[3]),
.I1(a[3]),
.O(\blk00000001/sig00000034 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005b (
.I0(b[13]),
.I1(a[13]),
.O(\blk00000001/sig00000051 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005a (
.I0(b[4]),
.I1(a[4]),
.O(\blk00000001/sig00000035 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000059 (
.I0(b[14]),
.I1(a[14]),
.O(\blk00000001/sig00000052 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000058 (
.I0(b[5]),
.I1(a[5]),
.O(\blk00000001/sig00000036 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000057 (
.I0(b[15]),
.I1(a[15]),
.O(\blk00000001/sig00000053 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000056 (
.I0(b[6]),
.I1(a[6]),
.O(\blk00000001/sig00000037 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000055 (
.I0(b[16]),
.I1(a[16]),
.O(\blk00000001/sig00000054 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000054 (
.I0(b[7]),
.I1(a[7]),
.O(\blk00000001/sig00000038 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000053 (
.I0(b[17]),
.I1(a[17]),
.O(\blk00000001/sig00000055 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000052 (
.I0(b[8]),
.I1(a[8]),
.O(\blk00000001/sig00000039 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000051 (
.I0(b[17]),
.I1(a[17]),
.O(\blk00000001/sig00000056 )
);
MUXCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig00000027 ),
.DI(a[0]),
.S(\blk00000001/sig00000031 ),
.O(\blk00000001/sig00000028 )
);
XORCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig00000027 ),
.LI(\blk00000001/sig00000031 ),
.O(\blk00000001/sig0000003b )
);
XORCY \blk00000001/blk0000004e (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig00000039 ),
.O(\blk00000001/sig00000043 )
);
MUXCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig0000002f ),
.DI(a[8]),
.S(\blk00000001/sig00000039 ),
.O(\blk00000001/sig00000030 )
);
MUXCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig00000028 ),
.DI(a[1]),
.S(\blk00000001/sig00000032 ),
.O(\blk00000001/sig00000029 )
);
XORCY \blk00000001/blk0000004b (
.CI(\blk00000001/sig00000028 ),
.LI(\blk00000001/sig00000032 ),
.O(\blk00000001/sig0000003c )
);
MUXCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig00000029 ),
.DI(a[2]),
.S(\blk00000001/sig00000033 ),
.O(\blk00000001/sig0000002a )
);
XORCY \blk00000001/blk00000049 (
.CI(\blk00000001/sig00000029 ),
.LI(\blk00000001/sig00000033 ),
.O(\blk00000001/sig0000003d )
);
MUXCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig0000002a ),
.DI(a[3]),
.S(\blk00000001/sig00000034 ),
.O(\blk00000001/sig0000002b )
);
XORCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig0000002a ),
.LI(\blk00000001/sig00000034 ),
.O(\blk00000001/sig0000003e )
);
MUXCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig0000002b ),
.DI(a[4]),
.S(\blk00000001/sig00000035 ),
.O(\blk00000001/sig0000002c )
);
XORCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig0000002b ),
.LI(\blk00000001/sig00000035 ),
.O(\blk00000001/sig0000003f )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig0000002c ),
.DI(a[5]),
.S(\blk00000001/sig00000036 ),
.O(\blk00000001/sig0000002d )
);
XORCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig0000002c ),
.LI(\blk00000001/sig00000036 ),
.O(\blk00000001/sig00000040 )
);
MUXCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig0000002d ),
.DI(a[6]),
.S(\blk00000001/sig00000037 ),
.O(\blk00000001/sig0000002e )
);
XORCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig0000002d ),
.LI(\blk00000001/sig00000037 ),
.O(\blk00000001/sig00000041 )
);
MUXCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig0000002e ),
.DI(a[7]),
.S(\blk00000001/sig00000038 ),
.O(\blk00000001/sig0000002f )
);
XORCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig0000002e ),
.LI(\blk00000001/sig00000038 ),
.O(\blk00000001/sig00000042 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000030 ),
.Q(\blk00000001/sig0000003a )
);
MUXCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig00000027 ),
.DI(a[9]),
.S(\blk00000001/sig0000004d ),
.O(\blk00000001/sig00000044 )
);
XORCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig00000027 ),
.LI(\blk00000001/sig0000004d ),
.O(\blk00000001/sig00000061 )
);
XORCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig0000004c ),
.LI(\blk00000001/sig00000056 ),
.O(\blk00000001/sig0000006a )
);
MUXCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig00000044 ),
.DI(a[10]),
.S(\blk00000001/sig0000004e ),
.O(\blk00000001/sig00000045 )
);
XORCY \blk00000001/blk00000039 (
.CI(\blk00000001/sig00000044 ),
.LI(\blk00000001/sig0000004e ),
.O(\blk00000001/sig00000062 )
);
MUXCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig00000045 ),
.DI(a[11]),
.S(\blk00000001/sig0000004f ),
.O(\blk00000001/sig00000046 )
);
XORCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig00000045 ),
.LI(\blk00000001/sig0000004f ),
.O(\blk00000001/sig00000063 )
);
MUXCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig00000046 ),
.DI(a[12]),
.S(\blk00000001/sig00000050 ),
.O(\blk00000001/sig00000047 )
);
XORCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig00000046 ),
.LI(\blk00000001/sig00000050 ),
.O(\blk00000001/sig00000064 )
);
MUXCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig00000047 ),
.DI(a[13]),
.S(\blk00000001/sig00000051 ),
.O(\blk00000001/sig00000048 )
);
XORCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig00000047 ),
.LI(\blk00000001/sig00000051 ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig00000048 ),
.DI(a[14]),
.S(\blk00000001/sig00000052 ),
.O(\blk00000001/sig00000049 )
);
XORCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig00000048 ),
.LI(\blk00000001/sig00000052 ),
.O(\blk00000001/sig00000066 )
);
MUXCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig00000049 ),
.DI(a[15]),
.S(\blk00000001/sig00000053 ),
.O(\blk00000001/sig0000004a )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig00000049 ),
.LI(\blk00000001/sig00000053 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig0000004a ),
.DI(a[16]),
.S(\blk00000001/sig00000054 ),
.O(\blk00000001/sig0000004b )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig0000004a ),
.LI(\blk00000001/sig00000054 ),
.O(\blk00000001/sig00000068 )
);
MUXCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig0000004b ),
.DI(a[17]),
.S(\blk00000001/sig00000055 ),
.O(\blk00000001/sig0000004c )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000055 ),
.O(\blk00000001/sig00000069 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000061 ),
.Q(\blk00000001/sig00000057 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000062 ),
.Q(\blk00000001/sig00000059 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000063 ),
.Q(\blk00000001/sig0000005a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000064 ),
.Q(\blk00000001/sig0000005b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000065 ),
.Q(\blk00000001/sig0000005c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000066 ),
.Q(\blk00000001/sig0000005d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000067 ),
.Q(\blk00000001/sig0000005e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000068 ),
.Q(\blk00000001/sig0000005f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000069 ),
.Q(\blk00000001/sig00000060 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006a ),
.Q(\blk00000001/sig00000058 )
);
MUXCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig0000003a ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000099 ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig0000003a ),
.LI(\blk00000001/sig00000099 ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000098 ),
.O(\blk00000001/sig000000a3 )
);
MUXCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig00000085 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000098 ),
.O(\NLW_blk00000001/blk0000001d_O_UNCONNECTED )
);
MUXCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000090 ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig00000090 ),
.O(\blk00000001/sig0000009b )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000009c )
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig0000007f ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000009d )
);
MUXCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig00000093 ),
.O(\blk00000001/sig0000009e )
);
MUXCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig00000081 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig00000094 ),
.O(\blk00000001/sig0000009f )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig00000082 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig00000082 ),
.LI(\blk00000001/sig00000095 ),
.O(\blk00000001/sig000000a0 )
);
MUXCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig00000083 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000084 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig000000a1 )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000084 ),
.DI(\blk00000001/sig00000027 ),
.S(\blk00000001/sig00000097 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig00000084 ),
.LI(\blk00000001/sig00000097 ),
.O(\blk00000001/sig000000a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009a ),
.Q(s[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009b ),
.Q(s[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009c ),
.Q(s[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009d ),
.Q(s[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009e ),
.Q(s[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009f ),
.Q(s[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a0 ),
.Q(s[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a1 ),
.Q(s[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a2 ),
.Q(s[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000003 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a3 ),
.Q(s[18])
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000027 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire pick1 = crc[0];
wire [13:0][1:0] data1 = crc[27+1:1];
wire [3:0][2:0][1:0] data2 = crc[23+29:29];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [15:0] [1:0] datao; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.datao (datao/*[15:0][1:0]*/),
// Inputs
.pick1 (pick1),
.data1 (data1/*[13:0][1:0]*/),
.data2 (data2/*[2:0][3:0][1:0]*/));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, datao};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3ff4bf0e6407b281
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input logic pick1,
input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits
input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits
output logic [15:0] [1:0] datao // 16 x 2 = 32 bits
);
// verilator lint_off WIDTH
always_comb datao[13: 0] // 28 bits
= (pick1)
? {data1} // 28 bits
: {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized
// verilator lint_on WIDTH
always_comb datao[15:14] = '0;
endmodule
|
// usb_rx_fifo.v
`timescale 1 ns / 1 ps
module usb_rx_fifo
(
input reset,
input wrclk,
input write,
input [15:0]din,
input min,
output full,
input rdclk,
input read,
output [15:0]dout,
output mout,
output empty
);
wire [16:0]data = { min, din };
wire [16:0]q;
assign { mout, dout } = q;
dcfifo dcfifo_component
(
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (write),
.aclr (reset),
.data (data),
.rdreq (read),
.wrfull (full),
.q (q),
.rdempty (empty),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 17,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// PLB INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: plb_if.v
//
// Description:
//
//
// Design Notes:
//
//-----------------------------------------------------------------------------
// Structure:
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps
module plb_if(
// PLB GLOBAL SIGNALS
clk, // I 100MHz
rst, // I
// REQUEST QUALIFIERS INPUTS
PLB_MnAddrAck, // I
Mn_request, // O
Mn_priority, // O [0:1]
Mn_RNW, // O
Mn_BE, // O [0:7]
Mn_size, // O [0:3]
Mn_type, // O [0:2]
Mn_MSize, // O [0:1]
Mn_ABus, // O [0:31]
// PLB READ DATA BUS
PLB_MnRdDAck, // I
PLB_MnRdWdAddr, // I
PLB_MnRdDBus, // I [0:63]
// PLB_BRAM CONTROL AND DATA
PLB_BRAM_data, // O [0:63]
PLB_BRAM_addr_lsb, // O [0:1]
PLB_BRAM_addr_en, // O
PLB_BRAM_we, // O
// GET_LINE PULSE
get_line, // I
// BASE ADDRESS
tft_base_addr, // I [0:10]
tft_on_reg // I
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// PLB GLOBAL SIGNALS
input clk;
input rst;
// REQUEST QUALIFIERS INPUTS
input PLB_MnAddrAck;
output Mn_request;
output [0:1] Mn_priority;
output Mn_RNW;
output [0:7] Mn_BE;
output [0:3] Mn_size;
output [0:2] Mn_type;
output [0:1] Mn_MSize;
output [0:31] Mn_ABus;
// PLB READ DATA BUS
input PLB_MnRdDAck;
input [0:3] PLB_MnRdWdAddr;
input [0:63] PLB_MnRdDBus;
// PLB_BRAM CONTROL AND DATA
output [0:63] PLB_BRAM_data;
output [0:1] PLB_BRAM_addr_lsb;
output PLB_BRAM_addr_en;
output PLB_BRAM_we;
// GET LINE PULSE
input get_line;
input [0:10] tft_base_addr;
input tft_on_reg;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg [0:6] trans_cnt;
reg [0:6] trans_cnt_i;
wire trans_cnt_ce;
wire trans_cnt_tc;
reg [0:8] line_cnt;
reg [0:8] line_cnt_i;
wire line_cnt_ce;
wire end_xfer;
wire end_xfer_p1;
reg [0:63] PLB_BRAM_data;
reg [0:1] PLB_BRAM_addr_lsb;
reg PLB_BRAM_we;
reg [0:10] tft_base_addr_i;
wire skip_line;
reg skip_line_d1;
reg skip_plb_xfer;
reg skip_plb_xfer_d1;
reg skip_plb_xfer_d2;
reg skip_plb_xfer_d3;
reg skip_plb_xfer_d4;
reg dummy_rd_ack;
wire mn_request_set;
reg [0:3] data_xfer_shreg;
reg data_xfer_shreg1_d1;
////////////////////////////////////////////////////////////////////////////
// Tie off Constants
////////////////////////////////////////////////////////////////////////////
assign Mn_MSize = 2'b01; // 64 Bit PLB Xfers
assign Mn_priority = 2'b11; // Set priority to 3
assign Mn_size = 4'b0010; // Transfer 8-word line
assign Mn_type = 3'b000; // Memory type transfer
assign Mn_RNW = 1'b1; // Always read
assign Mn_BE = 8'b00000000; // Ignored on Line xfers
assign Mn_ABus[0:10] = tft_base_addr_i; // 11-bits
assign Mn_ABus[11:19] = line_cnt_i;
assign Mn_ABus[20:26] = trans_cnt_i;
assign Mn_ABus[27:31] = 5'b00000;
assign mn_request_set = tft_on_reg & ( (get_line & (trans_cnt == 0))
| (end_xfer & (trans_cnt != 0)));
FDRSE FDRS_MN_REQUEST_DLY (.Q(Mn_request),.CE(1'b0),.C(clk),.D(1'b0),
.R(PLB_MnAddrAck | rst), .S(mn_request_set));
always @(posedge clk)
begin
skip_plb_xfer <= ~tft_on_reg & ( (get_line & (trans_cnt == 0))
| (end_xfer & (trans_cnt != 0)));
skip_plb_xfer_d1 <= skip_plb_xfer;
skip_plb_xfer_d2 <= skip_plb_xfer_d1;
skip_plb_xfer_d3 <= skip_plb_xfer_d2;
skip_plb_xfer_d4 <= skip_plb_xfer_d3;
dummy_rd_ack <= skip_plb_xfer_d4 | skip_plb_xfer_d3 | skip_plb_xfer_d2 | skip_plb_xfer_d1;
end
always @(posedge clk)
if (mn_request_set) begin
tft_base_addr_i <= tft_base_addr;
line_cnt_i <= line_cnt;
trans_cnt_i <= trans_cnt;
end
always @(posedge clk)
begin
PLB_BRAM_data <= PLB_MnRdDBus;
PLB_BRAM_addr_lsb <= PLB_MnRdWdAddr[1:2];
PLB_BRAM_we <= PLB_MnRdDAck | dummy_rd_ack;
end
assign PLB_BRAM_addr_en = end_xfer;
always @(posedge clk)
if (rst | end_xfer)
data_xfer_shreg <= (end_xfer & (PLB_MnRdDAck | dummy_rd_ack))? 4'b0001 : 4'b0000;
else if (PLB_MnRdDAck | dummy_rd_ack)
data_xfer_shreg <= {data_xfer_shreg[1:3], 1'b1};
assign end_xfer = data_xfer_shreg[0];
always @(posedge clk)
data_xfer_shreg1_d1 <= data_xfer_shreg[1];
assign end_xfer_p1 = data_xfer_shreg[1] & ~data_xfer_shreg1_d1;
///////////////////////////////////////////////////////////////////////////////
// Transaction Counter - Counts 0-79 (d)
///////////////////////////////////////////////////////////////////////////////
assign trans_cnt_ce = end_xfer_p1;
assign trans_cnt_tc = (trans_cnt == 7'd79);
always @(posedge clk)
if(rst)
trans_cnt = 7'b0;
else if (trans_cnt_ce) begin
if (trans_cnt_tc)
trans_cnt = 7'b0;
else
trans_cnt = trans_cnt + 1;
end
///////////////////////////////////////////////////////////////////////////////
// Line Counter - Counts 0-479 (d)
///////////////////////////////////////////////////////////////////////////////
// increment line cnt if getline missed because prev plb xfers not complete
assign skip_line = get_line & (trans_cnt != 0);
always @(posedge clk)
skip_line_d1 <= skip_line & line_cnt_ce;
assign line_cnt_ce = end_xfer_p1 & trans_cnt_tc;
always @(posedge clk)
if (rst)
line_cnt = 9'b0;
else if (line_cnt_ce | skip_line | skip_line_d1) begin
if (line_cnt == 9'd479)
line_cnt = 9'b0;
else
line_cnt = line_cnt + 1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// BCHDecoderX for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder array
// Module Name: BCHDecoderX
// File Name: BCHDecoderX.v
//
// Version: v1.0.0
//
// Description: BCH decoder array
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module BCHDecoderX
#
(
parameter DataWidth = 32,
parameter Multi = 2,
parameter MaxErrorCountBits = 9,
parameter GaloisFieldDegree = 12,
parameter Syndromes = 27,
parameter ELPCoefficients = 15
)
(
iClock ,
iReset ,
iData ,
iDataValid ,
oDataReady ,
oDataLast ,
oDecoderReady ,
oDecodeFinished ,
oDecodeSuccess ,
oErrorSum ,
oErrorCountOut ,
oCorrectedData ,
oCorrectedDataValid ,
oCorrectedDataLast ,
iCorrectedDataReady ,
iSharedKESReady ,
oErrorDetectionEnd ,
oDecodeNeeded ,
oSyndromes ,
iIntraSharedKESEnd ,
iErroredChunk ,
iCorrectionFail ,
iErrorCount ,
iELPCoefficients ,
oCSAvailable ,
iCSReset
);
input iClock ;
input iReset ;
input [DataWidth - 1:0] iData ;
input iDataValid ;
output oDataReady ;
output oDecoderReady ;
output oDecodeFinished ;
output oDecodeSuccess ;
output [MaxErrorCountBits - 1:0] oErrorSum ;
output [4*Multi - 1:0] oErrorCountOut ;
output oDataLast ;
output [DataWidth - 1:0] oCorrectedData ;
output oCorrectedDataValid ;
output oCorrectedDataLast ;
input iCorrectedDataReady ;
input iSharedKESReady ;
output [Multi - 1:0] oErrorDetectionEnd ;
output [Multi - 1:0] oDecodeNeeded ;
output [Multi*GaloisFieldDegree*Syndromes - 1:0] oSyndromes ;
input iIntraSharedKESEnd ;
input [Multi - 1:0] iErroredChunk ;
input [Multi - 1:0] iCorrectionFail ;
input [Multi*MaxErrorCountBits - 1:0] iErrorCount ;
input [Multi*GaloisFieldDegree*ELPCoefficients - 1:0] iELPCoefficients ;
output oCSAvailable ;
input iCSReset ;
wire [Multi - 1:0] wDecoderReady ;
wire [Multi - 1:0] wDataValid ;
wire [Multi - 1:0] wInDataLast ;
wire [DataWidth - 1:0] wDecOutData ;
wire wDecOutDataStrobe ;
wire wDecOutDataLast ;
wire wDecodeEnd ;
wire [Multi - 1:0] wErroredData ;
wire [Multi - 1:0] wDecodeFailed ;
wire [Multi - 1:0] wDecoderFinished ;
reg [DataWidth - 1:0] rDecOutData ;
reg rDecOutDataValid ;
reg rDecOutDataLast ;
wire [Multi - 1:0] wMuxDataReady ;
reg [Multi - 1:0] rDecoderStatus ;
reg [Multi - 1:0] rSuccessStatus ;
wire wAllDecoderFinished ;
wire wAllDecoderSucceeded;
wire [MaxErrorCountBits*Multi - 1:0] wErrorCountOut ;
reg [MaxErrorCountBits*Multi - 1:0] rErrorCountOut ;
reg [MaxErrorCountBits - 1:0] rSumOfErrorCount ;
wire wReset ;
localparam ChunkSize = 256;
localparam ChunkSizeBits = 8;
genvar c;
generate
for (c = 0; c < Multi; c = c + 1)
begin
always @ (posedge iClock)
if (iReset)
rDecoderStatus[c] <= 1'b0;
else
if (wDecodeEnd)
rDecoderStatus[c] <= 1'b1;
else if (wAllDecoderFinished)
rDecoderStatus[c] <= 1'b0;
always @ (posedge iClock)
if (iReset)
rSuccessStatus[c] <= 1'b0;
else
if (wDecodeEnd)
rSuccessStatus[c] <= (wDecodeFailed) ? 1'b0 : 1'b1;
else if (wAllDecoderFinished)
rSuccessStatus[c] <= 1'b0;
/*always @ (*)
begin
rDecOutData[(c + 1) * 8 - 1:c * 8] <= wDecOutData[(c + 1) * 8 - 1:c * 8];
rDecOutDataValid[c] <= wDecOutDataStrobe[c];
rDecOutDataLast[c] <= wDecOutDataLast[c];
end
*/
assign wMuxDataReady[c] = iCorrectedDataReady && oCorrectedDataValid;
assign wDataValid[c] = iDataValid;
end
endgenerate
PageDecoderTop
#
(
.Multi (Multi ),
.GaloisFieldDegree (GaloisFieldDegree ),
.MaxErrorCountBits (MaxErrorCountBits ),
.DataWidth (32 ),
.Syndromes (Syndromes ),
.ELPCoefficients (ELPCoefficients )
)
Inst_BCHPDecoder
(
.iClock (iClock ),
.iReset (wReset ),
.iExecuteDecoding (1'b1 ),
.iDataValid (wDataValid ),
.iData (iData ),
.oDataReady (oDataReady ),
.oDecoderReady (wDecoderReady ),
.oInDataLast (wInDataLast ),
.oDecoderFinished (wDecoderFinished ),
.oErrorCountOut (wErrorCountOut ),
.oDecodeEnd (wDecodeEnd ),
.oErroredChunk (wErroredData ),
.oDecodeFailed (wDecodeFailed ),
.iMuxDataReady (wMuxDataReady ),
.oDecOutDataStrobe (wDecOutDataStrobe ),
.oDecOutDataLast (wDecOutDataLast ),
.oDecOutData (wDecOutData ),
.iSharedKESReady (iSharedKESReady ),
.oErrorDetectionEnd (oErrorDetectionEnd ),
.oDecodeNeeded (oDecodeNeeded ),
.oSyndromes (oSyndromes ),
.iIntraSharedKESEnd (iIntraSharedKESEnd ),
.iErroredChunk (iErroredChunk ),
.iCorrectionFail (iCorrectionFail ),
.iErrorCount (iErrorCount ),
.iELPCoefficients (iELPCoefficients ),
.oCSAvailable (oCSAvailable )
);
assign oDecoderReady = &(wDecoderReady);
assign wReset = iReset | iCSReset;
initial begin
if (Multi != 2 || MaxErrorCountBits != 9)
begin
$display ("Modify <rSumOfErrorCount> in BCHDecoderX to continue.");
$finish;
end
end
always @ (posedge iClock)
if (iReset) begin
rSumOfErrorCount <= {(MaxErrorCountBits){1'b0}};
rErrorCountOut <= {(MaxErrorCountBits*Multi){1'b0}};
end
else
if (wAllDecoderFinished) begin
rSumOfErrorCount <= {(MaxErrorCountBits){1'b0}};
rErrorCountOut <= {(MaxErrorCountBits*Multi){1'b0}};
end
else if (wDecodeEnd) begin
rSumOfErrorCount <= (wErrorCountOut[17:9] + wErrorCountOut[8:0]);
rErrorCountOut <= wErrorCountOut;
end
always @ (*)
begin
rDecOutData <= wDecOutData ;
rDecOutDataLast <= wDecOutDataLast ;
rDecOutDataValid <= wDecOutDataStrobe ;
end
assign wAllDecoderFinished = &(rDecoderStatus);
assign wAllDecoderSucceeded = &(rSuccessStatus);
assign oDecodeFinished = wAllDecoderFinished ;
assign oDecodeSuccess = wAllDecoderSucceeded ;
assign oErrorSum = rSumOfErrorCount ;
assign oErrorCountOut = { rErrorCountOut[12:9 ],
rErrorCountOut[3 :0 ] };
assign oCorrectedData = rDecOutData ;
assign oCorrectedDataLast = &rDecOutDataLast ;
assign oCorrectedDataValid = &rDecOutDataValid ;
assign oDataLast = wInDataLast[0];
endmodule |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:09 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_sim_netlist.v
// Design : ip_design_led_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_led_controller_0_0,led_controller_v1_0,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(LEDs_out,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready,
s00_axi_aclk,
s00_axi_aresetn);
output [7:0]LEDs_out;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [3:0]s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [3:0]s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s00_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW" *) input s00_axi_aresetn;
wire \<const0> ;
wire [7:0]LEDs_out;
wire s00_axi_aclk;
wire [3:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arready;
wire s00_axi_arvalid;
wire [3:0]s00_axi_awaddr;
wire s00_axi_awready;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
assign s00_axi_bresp[1] = \<const0> ;
assign s00_axi_bresp[0] = \<const0> ;
assign s00_axi_rresp[1] = \<const0> ;
assign s00_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 inst
(.LEDs_out(LEDs_out),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WREADY(s00_axi_wready),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr[3:2]),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awaddr(s00_axi_awaddr[3:2]),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0
(S_AXI_ARREADY,
S_AXI_AWREADY,
S_AXI_WREADY,
LEDs_out,
s00_axi_rdata,
s00_axi_rvalid,
s00_axi_bvalid,
s00_axi_arvalid,
s00_axi_aclk,
s00_axi_awaddr,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wdata,
s00_axi_araddr,
s00_axi_wstrb,
s00_axi_aresetn,
s00_axi_bready,
s00_axi_rready);
output S_AXI_ARREADY;
output S_AXI_AWREADY;
output S_AXI_WREADY;
output [7:0]LEDs_out;
output [31:0]s00_axi_rdata;
output s00_axi_rvalid;
output s00_axi_bvalid;
input s00_axi_arvalid;
input s00_axi_aclk;
input [1:0]s00_axi_awaddr;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [31:0]s00_axi_wdata;
input [1:0]s00_axi_araddr;
input [3:0]s00_axi_wstrb;
input s00_axi_aresetn;
input s00_axi_bready;
input s00_axi_rready;
wire [7:0]LEDs_out;
wire S_AXI_ARREADY;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire s00_axi_aclk;
wire [1:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire [1:0]s00_axi_awaddr;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI led_controller_v1_0_S00_AXI_inst
(.LEDs_out(LEDs_out),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WREADY(S_AXI_WREADY),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI
(S_AXI_ARREADY,
S_AXI_AWREADY,
S_AXI_WREADY,
LEDs_out,
s00_axi_rdata,
s00_axi_rvalid,
s00_axi_bvalid,
s00_axi_arvalid,
s00_axi_aclk,
s00_axi_awaddr,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wdata,
s00_axi_araddr,
s00_axi_wstrb,
s00_axi_aresetn,
s00_axi_bready,
s00_axi_rready);
output S_AXI_ARREADY;
output S_AXI_AWREADY;
output S_AXI_WREADY;
output [7:0]LEDs_out;
output [31:0]s00_axi_rdata;
output s00_axi_rvalid;
output s00_axi_bvalid;
input s00_axi_arvalid;
input s00_axi_aclk;
input [1:0]s00_axi_awaddr;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [31:0]s00_axi_wdata;
input [1:0]s00_axi_araddr;
input [3:0]s00_axi_wstrb;
input s00_axi_aresetn;
input s00_axi_bready;
input s00_axi_rready;
wire [7:0]LEDs_out;
wire S_AXI_ARREADY;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire aw_en_i_1_n_0;
wire aw_en_reg_n_0;
wire [3:2]axi_araddr;
wire \axi_araddr[2]_i_1_n_0 ;
wire \axi_araddr[3]_i_1_n_0 ;
wire axi_arready_i_1_n_0;
wire \axi_awaddr[2]_i_1_n_0 ;
wire \axi_awaddr[3]_i_1_n_0 ;
wire axi_awready0;
wire axi_bvalid_i_1_n_0;
wire axi_rvalid_i_1_n_0;
wire axi_wready0;
wire [1:0]p_0_in;
wire [31:7]p_1_in;
wire [31:0]reg_data_out;
wire s00_axi_aclk;
wire [1:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire [1:0]s00_axi_awaddr;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
wire [31:8]slv_reg0;
wire \slv_reg0[7]_i_1_n_0 ;
wire [31:0]slv_reg1;
wire \slv_reg1[15]_i_1_n_0 ;
wire \slv_reg1[23]_i_1_n_0 ;
wire \slv_reg1[31]_i_1_n_0 ;
wire \slv_reg1[7]_i_1_n_0 ;
wire [31:0]slv_reg2;
wire \slv_reg2[15]_i_1_n_0 ;
wire \slv_reg2[23]_i_1_n_0 ;
wire \slv_reg2[31]_i_1_n_0 ;
wire \slv_reg2[7]_i_1_n_0 ;
wire [31:0]slv_reg3;
wire \slv_reg3[15]_i_1_n_0 ;
wire \slv_reg3[23]_i_1_n_0 ;
wire \slv_reg3[31]_i_1_n_0 ;
wire \slv_reg3[7]_i_1_n_0 ;
wire slv_reg_rden__0;
wire slv_reg_wren__0;
LUT6 #(
.INIT(64'hF7FFC4CCC4CCC4CC))
aw_en_i_1
(.I0(s00_axi_wvalid),
.I1(aw_en_reg_n_0),
.I2(S_AXI_AWREADY),
.I3(s00_axi_awvalid),
.I4(s00_axi_bready),
.I5(s00_axi_bvalid),
.O(aw_en_i_1_n_0));
FDSE aw_en_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(aw_en_i_1_n_0),
.Q(aw_en_reg_n_0),
.S(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\axi_araddr[2]_i_1
(.I0(s00_axi_araddr[0]),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.I3(axi_araddr[2]),
.O(\axi_araddr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
\axi_araddr[3]_i_1
(.I0(s00_axi_araddr[1]),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.I3(axi_araddr[3]),
.O(\axi_araddr[3]_i_1_n_0 ));
FDRE \axi_araddr_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_araddr[2]_i_1_n_0 ),
.Q(axi_araddr[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_araddr_reg[3]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_araddr[3]_i_1_n_0 ),
.Q(axi_araddr[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
axi_arready_i_1
(.I0(s00_axi_arvalid),
.I1(S_AXI_ARREADY),
.O(axi_arready_i_1_n_0));
FDRE axi_arready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_arready_i_1_n_0),
.Q(S_AXI_ARREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFBFFFFFF08000000))
\axi_awaddr[2]_i_1
(.I0(s00_axi_awaddr[0]),
.I1(s00_axi_awvalid),
.I2(S_AXI_AWREADY),
.I3(aw_en_reg_n_0),
.I4(s00_axi_wvalid),
.I5(p_0_in[0]),
.O(\axi_awaddr[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFBFFFFFF08000000))
\axi_awaddr[3]_i_1
(.I0(s00_axi_awaddr[1]),
.I1(s00_axi_awvalid),
.I2(S_AXI_AWREADY),
.I3(aw_en_reg_n_0),
.I4(s00_axi_wvalid),
.I5(p_0_in[1]),
.O(\axi_awaddr[3]_i_1_n_0 ));
FDRE \axi_awaddr_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_awaddr[2]_i_1_n_0 ),
.Q(p_0_in[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_awaddr_reg[3]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_awaddr[3]_i_1_n_0 ),
.Q(p_0_in[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
axi_awready_i_1
(.I0(s00_axi_awvalid),
.I1(S_AXI_AWREADY),
.I2(aw_en_reg_n_0),
.I3(s00_axi_wvalid),
.O(axi_awready0));
FDRE axi_awready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_awready0),
.Q(S_AXI_AWREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF80008000))
axi_bvalid_i_1
(.I0(S_AXI_WREADY),
.I1(S_AXI_AWREADY),
.I2(s00_axi_awvalid),
.I3(s00_axi_wvalid),
.I4(s00_axi_bready),
.I5(s00_axi_bvalid),
.O(axi_bvalid_i_1_n_0));
FDRE axi_bvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_i_1_n_0),
.Q(s00_axi_bvalid),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[0]_i_1
(.I0(slv_reg1[0]),
.I1(LEDs_out[0]),
.I2(slv_reg3[0]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[0]),
.O(reg_data_out[0]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[10]_i_1
(.I0(slv_reg1[10]),
.I1(slv_reg0[10]),
.I2(slv_reg3[10]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[10]),
.O(reg_data_out[10]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[11]_i_1
(.I0(slv_reg1[11]),
.I1(slv_reg0[11]),
.I2(slv_reg3[11]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[11]),
.O(reg_data_out[11]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[12]_i_1
(.I0(slv_reg1[12]),
.I1(slv_reg0[12]),
.I2(slv_reg3[12]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[12]),
.O(reg_data_out[12]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[13]_i_1
(.I0(slv_reg1[13]),
.I1(slv_reg0[13]),
.I2(slv_reg3[13]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[13]),
.O(reg_data_out[13]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[14]_i_1
(.I0(slv_reg1[14]),
.I1(slv_reg0[14]),
.I2(slv_reg3[14]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[14]),
.O(reg_data_out[14]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[15]_i_1
(.I0(slv_reg1[15]),
.I1(slv_reg0[15]),
.I2(slv_reg3[15]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[15]),
.O(reg_data_out[15]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[16]_i_1
(.I0(slv_reg1[16]),
.I1(slv_reg0[16]),
.I2(slv_reg3[16]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[16]),
.O(reg_data_out[16]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[17]_i_1
(.I0(slv_reg1[17]),
.I1(slv_reg0[17]),
.I2(slv_reg3[17]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[17]),
.O(reg_data_out[17]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[18]_i_1
(.I0(slv_reg1[18]),
.I1(slv_reg0[18]),
.I2(slv_reg3[18]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[18]),
.O(reg_data_out[18]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[19]_i_1
(.I0(slv_reg1[19]),
.I1(slv_reg0[19]),
.I2(slv_reg3[19]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[19]),
.O(reg_data_out[19]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[1]_i_1
(.I0(slv_reg1[1]),
.I1(LEDs_out[1]),
.I2(slv_reg3[1]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[1]),
.O(reg_data_out[1]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[20]_i_1
(.I0(slv_reg1[20]),
.I1(slv_reg0[20]),
.I2(slv_reg3[20]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[20]),
.O(reg_data_out[20]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[21]_i_1
(.I0(slv_reg1[21]),
.I1(slv_reg0[21]),
.I2(slv_reg3[21]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[21]),
.O(reg_data_out[21]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[22]_i_1
(.I0(slv_reg1[22]),
.I1(slv_reg0[22]),
.I2(slv_reg3[22]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[22]),
.O(reg_data_out[22]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[23]_i_1
(.I0(slv_reg1[23]),
.I1(slv_reg0[23]),
.I2(slv_reg3[23]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[23]),
.O(reg_data_out[23]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[24]_i_1
(.I0(slv_reg1[24]),
.I1(slv_reg0[24]),
.I2(slv_reg3[24]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[24]),
.O(reg_data_out[24]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[25]_i_1
(.I0(slv_reg1[25]),
.I1(slv_reg0[25]),
.I2(slv_reg3[25]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[25]),
.O(reg_data_out[25]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[26]_i_1
(.I0(slv_reg1[26]),
.I1(slv_reg0[26]),
.I2(slv_reg3[26]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[26]),
.O(reg_data_out[26]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[27]_i_1
(.I0(slv_reg1[27]),
.I1(slv_reg0[27]),
.I2(slv_reg3[27]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[27]),
.O(reg_data_out[27]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[28]_i_1
(.I0(slv_reg1[28]),
.I1(slv_reg0[28]),
.I2(slv_reg3[28]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[28]),
.O(reg_data_out[28]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[29]_i_1
(.I0(slv_reg1[29]),
.I1(slv_reg0[29]),
.I2(slv_reg3[29]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[29]),
.O(reg_data_out[29]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[2]_i_1
(.I0(slv_reg1[2]),
.I1(LEDs_out[2]),
.I2(slv_reg3[2]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[2]),
.O(reg_data_out[2]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[30]_i_1
(.I0(slv_reg1[30]),
.I1(slv_reg0[30]),
.I2(slv_reg3[30]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[30]),
.O(reg_data_out[30]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[31]_i_1
(.I0(slv_reg1[31]),
.I1(slv_reg0[31]),
.I2(slv_reg3[31]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[31]),
.O(reg_data_out[31]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[3]_i_1
(.I0(slv_reg1[3]),
.I1(LEDs_out[3]),
.I2(slv_reg3[3]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[3]),
.O(reg_data_out[3]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[4]_i_1
(.I0(slv_reg1[4]),
.I1(LEDs_out[4]),
.I2(slv_reg3[4]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[4]),
.O(reg_data_out[4]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[5]_i_1
(.I0(slv_reg1[5]),
.I1(LEDs_out[5]),
.I2(slv_reg3[5]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[5]),
.O(reg_data_out[5]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[6]_i_1
(.I0(slv_reg1[6]),
.I1(LEDs_out[6]),
.I2(slv_reg3[6]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[6]),
.O(reg_data_out[6]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[7]_i_1
(.I0(slv_reg1[7]),
.I1(LEDs_out[7]),
.I2(slv_reg3[7]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[7]),
.O(reg_data_out[7]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[8]_i_1
(.I0(slv_reg1[8]),
.I1(slv_reg0[8]),
.I2(slv_reg3[8]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[8]),
.O(reg_data_out[8]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[9]_i_1
(.I0(slv_reg1[9]),
.I1(slv_reg0[9]),
.I2(slv_reg3[9]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[9]),
.O(reg_data_out[9]));
FDRE \axi_rdata_reg[0]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[0]),
.Q(s00_axi_rdata[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[10]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[10]),
.Q(s00_axi_rdata[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[11]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[11]),
.Q(s00_axi_rdata[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[12]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[12]),
.Q(s00_axi_rdata[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[13]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[13]),
.Q(s00_axi_rdata[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[14]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[14]),
.Q(s00_axi_rdata[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[15]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[15]),
.Q(s00_axi_rdata[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[16]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[16]),
.Q(s00_axi_rdata[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[17]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[17]),
.Q(s00_axi_rdata[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[18]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[18]),
.Q(s00_axi_rdata[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[19]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[19]),
.Q(s00_axi_rdata[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[1]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[1]),
.Q(s00_axi_rdata[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[20]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[20]),
.Q(s00_axi_rdata[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[21]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[21]),
.Q(s00_axi_rdata[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[22]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[22]),
.Q(s00_axi_rdata[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[23]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[23]),
.Q(s00_axi_rdata[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[24]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[24]),
.Q(s00_axi_rdata[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[25]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[25]),
.Q(s00_axi_rdata[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[26]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[26]),
.Q(s00_axi_rdata[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[27]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[27]),
.Q(s00_axi_rdata[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[28]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[28]),
.Q(s00_axi_rdata[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[29]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[29]),
.Q(s00_axi_rdata[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[2]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[2]),
.Q(s00_axi_rdata[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[30]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[30]),
.Q(s00_axi_rdata[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[31]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[31]),
.Q(s00_axi_rdata[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[3]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[3]),
.Q(s00_axi_rdata[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[4]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[4]),
.Q(s00_axi_rdata[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[5]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[5]),
.Q(s00_axi_rdata[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[6]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[6]),
.Q(s00_axi_rdata[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[7]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[7]),
.Q(s00_axi_rdata[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[8]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[8]),
.Q(s00_axi_rdata[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[9]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[9]),
.Q(s00_axi_rdata[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h08F8))
axi_rvalid_i_1
(.I0(S_AXI_ARREADY),
.I1(s00_axi_arvalid),
.I2(s00_axi_rvalid),
.I3(s00_axi_rready),
.O(axi_rvalid_i_1_n_0));
FDRE axi_rvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_i_1_n_0),
.Q(s00_axi_rvalid),
.R(\slv_reg0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h4000))
axi_wready_i_1
(.I0(S_AXI_WREADY),
.I1(s00_axi_wvalid),
.I2(s00_axi_awvalid),
.I3(aw_en_reg_n_0),
.O(axi_wready0));
FDRE axi_wready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_wready0),
.Q(S_AXI_WREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[1]),
.O(p_1_in[15]));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[2]),
.O(p_1_in[23]));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[3]),
.O(p_1_in[31]));
LUT1 #(
.INIT(2'h1))
\slv_reg0[7]_i_1
(.I0(s00_axi_aresetn),
.O(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[7]_i_2
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[0]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\slv_reg0[7]_i_3
(.I0(S_AXI_WREADY),
.I1(S_AXI_AWREADY),
.I2(s00_axi_awvalid),
.I3(s00_axi_wvalid),
.O(slv_reg_wren__0));
FDRE \slv_reg0_reg[0]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[0]),
.Q(LEDs_out[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[10]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[10]),
.Q(slv_reg0[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[11]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[11]),
.Q(slv_reg0[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[12]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[12]),
.Q(slv_reg0[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[13]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[13]),
.Q(slv_reg0[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[14]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[14]),
.Q(slv_reg0[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[15]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[15]),
.Q(slv_reg0[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[16]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[16]),
.Q(slv_reg0[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[17]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[17]),
.Q(slv_reg0[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[18]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[18]),
.Q(slv_reg0[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[19]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[19]),
.Q(slv_reg0[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[1]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[1]),
.Q(LEDs_out[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[20]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[20]),
.Q(slv_reg0[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[21]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[21]),
.Q(slv_reg0[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[22]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[22]),
.Q(slv_reg0[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[23]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[23]),
.Q(slv_reg0[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[24]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[24]),
.Q(slv_reg0[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[25]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[25]),
.Q(slv_reg0[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[26]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[26]),
.Q(slv_reg0[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[27]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[27]),
.Q(slv_reg0[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[28]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[28]),
.Q(slv_reg0[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[29]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[29]),
.Q(slv_reg0[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[2]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[2]),
.Q(LEDs_out[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[30]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[30]),
.Q(slv_reg0[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[31]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[31]),
.Q(slv_reg0[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[3]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[3]),
.Q(LEDs_out[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[4]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[4]),
.Q(LEDs_out[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[5]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[5]),
.Q(LEDs_out[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[6]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[6]),
.Q(LEDs_out[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[7]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[7]),
.Q(LEDs_out[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[8]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[8]),
.Q(slv_reg0[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[9]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[9]),
.Q(slv_reg0[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[1]),
.I3(p_0_in[0]),
.O(\slv_reg1[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[2]),
.I3(p_0_in[0]),
.O(\slv_reg1[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[3]),
.I3(p_0_in[0]),
.O(\slv_reg1[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[7]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[0]),
.I3(p_0_in[0]),
.O(\slv_reg1[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg1[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg1[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg1[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg1[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg1[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg1[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg1[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg1[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg1[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg1[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg1[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg1[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg1[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg1[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg1[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg1[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg1[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg1[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg1[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg1[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg1[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg1[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg1[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg1[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg1[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg1[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg1[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg1[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg1[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg1[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg1[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg1[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[1]),
.I3(p_0_in[0]),
.O(\slv_reg2[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[2]),
.I3(p_0_in[0]),
.O(\slv_reg2[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[3]),
.I3(p_0_in[0]),
.O(\slv_reg2[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[7]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[0]),
.I3(p_0_in[0]),
.O(\slv_reg2[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg2[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg2[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg2[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg2[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg2[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg2[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg2[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg2[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg2[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg2[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg2[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg2[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg2[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg2[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg2[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg2[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg2[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg2[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg2[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg2[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg2[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg2[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg2[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg2[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg2[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg2[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg2[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg2[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg2[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg2[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg2[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg2[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[15]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[1]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[23]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[2]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[31]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[3]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[7]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[0]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg3[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg3[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg3[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg3[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg3[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg3[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg3[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg3[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg3[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg3[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg3[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg3[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg3[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg3[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg3[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg3[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg3[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg3[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg3[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg3[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg3[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg3[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg3[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg3[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg3[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg3[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg3[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg3[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg3[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg3[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg3[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg3[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'h40))
slv_reg_rden
(.I0(s00_axi_rvalid),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.O(slv_reg_rden__0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// This is the main design unit.
// Pins description:
// clk in master clock input, assign to dedicated input
// when possible. Clock should be 25.178MHz
// for proper 60Hz VGA display
// LED1 out LED1 used to display game status
// LED2 out LED2 used to display player 2 mode
// VSYNC, HSYNC, RED, GREEN, BLUE outputs are VGA signals
// MISO in SPI master input
// MOSI out SPI master output
// SCK out SPI clock
// SCS out SPI slave chip select for ADC
// SOUND out 1-bit sound output
// BATON1 input active low, START button
// BATON2 input active low, ROBO-HAND button
module vga(clk, LED1, LED2, VSYNC, HSYNC, RED, GREEN, BLUE, MISO, MOSI, SCK, SCS, SOUND, BATON1, BATON2);
input clk;
output LED1;
output LED2;
output VSYNC;
output HSYNC;
output RED, GREEN, BLUE;
input MISO;
output MOSI;
output SCK;
output SCS;
output SOUND;
input BATON1;
input BATON2;
wand RED;
wand GREEN;
wand BLUE;
parameter SCREENWIDTH = 10'd640;
parameter SCREENHEIGHT = 10'd480;
parameter PADDLESIZE = 10'd64;
parameter BALLSIZE = 8;
// instantiate paddles
wire paddle_scan;
wire ball_scan;
wire[9:0] paddleA_y; // paddle A y-coordinate
wire[9:0] paddleB_y_manual; // paddle B y-coordinate as per ADC input
wire[9:0] paddleB_y_robot; // paddle B y-coordinate as per Robo-Hand
reg [9:0] paddleB_y; // paddle B y-coordinate result
reg playerBswitch; // 1 == paddle B is played by hunam
//
// clkdiv8 is an additional, slower clock
//
reg clkdiv8;
reg [6:0] clkdiv8_cnt;
always @(posedge clk) begin
if (clkdiv8_cnt == 0)
clkdiv8 <= !clkdiv8;
clkdiv8_cnt <= clkdiv8_cnt - 1'b1;
end
//
// paddle clock for robo-hand and ball clocks
//
reg [7:0] paddle_cnt;
reg [6:0] ball_cnt;
reg paddleAdvance;
reg ballAdvance;
always @(posedge clkdiv8) begin
paddle_cnt <= paddle_cnt - 1'b1;
ball_cnt <= ball_cnt - 1'b1;
if (ball_cnt == 0) ball_cnt <= 7'b1100000;
end
always @(posedge clk) paddleAdvance = paddle_cnt == 0;
always @(posedge clk) ballAdvance = ball_cnt == 0;
//
// Reset Generator and button debouncers
//
wire resetpulse; // initial set pulse
wire gamereset; // start game
resetgen resetgen(clk, resetpulse, 1);
button2 #(8192) gameresetter(clkdiv8, gamereset, BATON1);
button2 #(8192) button2(clkdiv8, playerBbutton, BATON2);
// Handle player B Hunam/Robo-Hand switch
always @(posedge playerBbutton or posedge resetpulse) begin
if (resetpulse)
playerBswitch <= 1;
else
playerBswitch <= !playerBswitch;
end
// LED2 simply shows if human player is active.
// For LED1 driver see tehgame.v
assign LED2 = playerBswitch;
// VGA scan instantiated here
wire[9:0] realx; // user area X coordinate
wire[9:0] realy; // user area Y coordinate
wire videoActive; // 1 == beam in user area
wire xscanstart, xscanend; // helper signals used for border scan
vgascan vgascan(clk, HSYNC, VSYNC, realx, realy, videoActive, xscanstart, xscanend);
// Analog input for player paddles
analinput #(PADDLESIZE, SCREENHEIGHT) analinput(clkdiv8, paddleA_y, paddleB_y_manual, MISO, MOSI, SCS, SCK);
wire[9:0] ball_y;
robohand #(PADDLESIZE,SCREENHEIGHT) paddleB(resetpulse, paddleAdvance, ball_y, paddleB_y_robot);
always @(posedge clkdiv8) begin
paddleB_y <= playerBswitch ? paddleB_y_manual : paddleB_y_robot;
end
tehgame teh(clk, clkdiv8, resetpulse, gamereset, HSYNC, realx, realy, paddleA_y, paddleB_y, ballAdvance, {ball_scan, paddle_scan, score_scan}, ball_y, SOUND, LED1);
wire border_scan;
borderscan #(640,480) borderscan(clk, xscanstart, xscanend, realy, border_scan);
reg [3:0] netcnt;
always @(posedge clk) begin
if (realx == SCREENWIDTH/2 && realy[1])
netcnt = 4;
if (netcnt != 0) netcnt = netcnt - 1'b1;
end
wire net_scan = netcnt != 0;
//scores scoreA(clk, HSYNC, realx, realy, outB, outA, 1'b0, score_scan);
wire bgr, bgg, bgb;
bgfill bgfill(clk, HSYNC, VSYNC, bgr, bgg, bgb);
reg red, green, blue;
always @(negedge clk) begin
red <= videoActive & (bgr | paddle_scan | border_scan | ball_scan | score_scan);
green <= videoActive & (bgg | paddle_scan | border_scan | ball_scan | net_scan | score_scan);
blue <= videoActive & (bgb | paddle_scan | border_scan | ball_scan);
end
assign RED = red;
assign GREEN = green;
assign BLUE = blue;
endmodule
module borderscan(clk, xstart, xend, realy, q);
parameter SCREENWIDTH = 0;
parameter SCREENHEIGHT = 0;
input clk, xstart, xend;
input [9:0] realy;
output q;
assign q = xstart | xend | realy == 0 | realy == SCREENHEIGHT - 1;
endmodule
module bgfill(clk, hsync, vsync, r, g, b);
input clk, hsync, vsync;
output r, g, b;
reg ff1, ff2;
always @(negedge clk) begin
if (vsync)
ff1 <= ~ff1;
else ff1 <= 0;
end
always @(negedge hsync) begin
if (vsync)
ff2 <= ~ff2;
else ff2 <= 0;
end
assign r = (1'b0 & ~(ff1^ff2));
assign g = (1'b0 & (ff1^ff2));
assign b = (1'b1 & (ff1^ff2));
endmodule
module collider(cclk, bx, by, ptop, pbot, reset, collide);
parameter px = 0;
parameter pw = 16;
input cclk;
input [9:0]bx;
input [9:0]by;
input [9:0]ptop;
input [9:0]pbot;
input reset;
output reg collide;
always @(posedge cclk or posedge reset) begin
if (cclk) begin
collide <= (bx >= px && bx <= (px + pw)) && (by+4 >= ptop && by-4 <= pbot);
end
else begin
collide <= 0;
end
end
endmodule
// $Id: vga.v,v 1.27 2007/08/27 22:12:30 svo Exp $ |
typedef struct packed {
logic [7:0] data;
logic wr_ena;
} mystruct_s;
module submod
(input logic a_port,
input logic [4:0] b_bus,
input mystruct_s single_struct_is_fine,
input mystruct_s [2:0] array_of_struct_is_not,
output logic status);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire status = 1'h0;
// End of automatics
endmodule // submod
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic status; // From submod0 of submod.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic a_port; // To submod0 of submod.v
mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
logic [4:0] b_bus; // To submod0 of submod.v
mystruct_s single_struct_is_fine; // To submod0 of submod.v
// End of automatics
submod submod0
(/*AUTOINST*/
// Outputs
.status (status),
// Inputs
.a_port (a_port),
.b_bus (b_bus[4:0]),
.single_struct_is_fine (single_struct_is_fine),
.array_of_struct_is_not (array_of_struct_is_not[2:0]));
endmodule // top
// Local Variables:
// verilog-typedef-regexp: "_s$"
// End:
|
module FswArbiter (/*AUTOARG*/
// Outputs
xb_ecc_error_dbit, xb_ecc_error_1bit, insert_idle_ack, bp_performance_count, obx_xb0_GntPst_s3a,
obx_xb0_GntByp_s3a, obx_xb1_GntPst_s3a, obx_xb1_GntByp_s3a, obx_xb2_GntPst_s3a,
obx_xb2_GntByp_s3a, obx_xb3_GntPst_s3a, obx_xb3_GntByp_s3a, xbx_grant_cycle, bp1_grant_cycle,
set_arbitration_enable_d1, reset_ackbuf, wait_for_ack, ice9_databus,
// Inputs
sclk, lreset_l, csr_insert_idle, csr_arb_enable, csr_bypass3_enable, csr_bypass2_enable,
csr_bypass1_enable, csr_xb_ecc_enable, xb0_obx_ReqPst_s2a, xb0_obx_NextVc_s2a,
xb0_obx_NextPort_s2a, xb0_obx_NextXbe_s2a, xb0_obx_NextXbe_s3a, xb0_obx_OutDat_s4a,
xb0_obx_ReqBypS3_s2a, xb0_obx_ReqBypS2_s2a, xb1_obx_ReqPst_s2a, xb1_obx_NextVc_s2a,
xb1_obx_NextPort_s2a, xb1_obx_NextXbe_s2a, xb1_obx_NextXbe_s3a, xb1_obx_OutDat_s4a,
xb1_obx_ReqBypS3_s2a, xb1_obx_ReqBypS2_s2a, xb2_obx_ReqPst_s2a, xb2_obx_NextVc_s2a,
xb2_obx_NextPort_s2a, xb2_obx_NextXbe_s2a, xb2_obx_NextXbe_s3a, xb2_obx_OutDat_s4a,
xb2_obx_ReqBypS3_s2a, xb2_obx_ReqBypS2_s2a, xb3_obx_ReqPst_s2a, xb3_obx_NextVc_s2a,
xb3_obx_NextPort_s2a, xb3_obx_NextXbe_s2a, xb3_obx_NextXbe_s3a, xb3_obx_OutDat_s4a,
xb3_obx_ReqBypS3_s2a, xb3_obx_ReqBypS2_s2a, ib0_obx_PortSel_s1a, ib0_obx_InDat_s1a,
ib0_obx_NextPort_s1a, ib0_obx_NextVc_s1a, ib1_obx_PortSel_s1a, ib1_obx_InDat_s1a,
ib1_obx_NextPort_s1a, ib1_obx_NextVc_s1a, ib2_obx_PortSel_s1a, ib2_obx_InDat_s1a,
ib2_obx_NextPort_s1a, ib2_obx_NextVc_s1a, ib3_obx_PortSel_s1a, ib3_obx_InDat_s1a,
ib3_obx_NextPort_s1a, ib3_obx_NextVc_s1a, rp_is_full, rp_in_progress, rp_arb_poolmask,
rp_arb_bufbusy_mask
) ;
// ========================
// Include parameter File
// ========================
parameter DMAO = 0;
`include "chip_fsw_spec_param.v"
// ===============
// Physical Pins
// ===============
input sclk; // Fabric switch clock
input lreset_l;
input csr_insert_idle;
input csr_arb_enable;
input [3:0] csr_bypass3_enable;
input [3:0] csr_bypass2_enable;
input [3:0] csr_bypass1_enable;
input csr_xb_ecc_enable;
output [3:0] xb_ecc_error_dbit;
output [3:0] xb_ecc_error_1bit;
output insert_idle_ack;
output [2:0] bp_performance_count;
input xb0_obx_ReqPst_s2a;
input [3:0] xb0_obx_NextVc_s2a;
input [1:0] xb0_obx_NextPort_s2a;
input [3:0] xb0_obx_NextXbe_s2a;
input [3:0] xb0_obx_NextXbe_s3a;
input [71:0] xb0_obx_OutDat_s4a;
output obx_xb0_GntPst_s3a;
output obx_xb0_GntByp_s3a;
input xb0_obx_ReqBypS3_s2a;
input xb0_obx_ReqBypS2_s2a;
input xb1_obx_ReqPst_s2a;
input [3:0] xb1_obx_NextVc_s2a;
input [1:0] xb1_obx_NextPort_s2a;
input [3:0] xb1_obx_NextXbe_s2a;
input [3:0] xb1_obx_NextXbe_s3a;
input [71:0] xb1_obx_OutDat_s4a;
output obx_xb1_GntPst_s3a;
output obx_xb1_GntByp_s3a;
input xb1_obx_ReqBypS3_s2a;
input xb1_obx_ReqBypS2_s2a;
input xb2_obx_ReqPst_s2a;
input [3:0] xb2_obx_NextVc_s2a;
input [1:0] xb2_obx_NextPort_s2a;
input [3:0] xb2_obx_NextXbe_s2a;
input [3:0] xb2_obx_NextXbe_s3a;
input [71:0] xb2_obx_OutDat_s4a;
output obx_xb2_GntPst_s3a;
output obx_xb2_GntByp_s3a;
input xb2_obx_ReqBypS3_s2a;
input xb2_obx_ReqBypS2_s2a;
input xb3_obx_ReqPst_s2a;
input [3:0] xb3_obx_NextVc_s2a;
input [1:0] xb3_obx_NextPort_s2a;
input [3:0] xb3_obx_NextXbe_s2a;
input [3:0] xb3_obx_NextXbe_s3a;
input [71:0] xb3_obx_OutDat_s4a;
output obx_xb3_GntPst_s3a;
output obx_xb3_GntByp_s3a;
input xb3_obx_ReqBypS3_s2a;
input xb3_obx_ReqBypS2_s2a;
input ib0_obx_PortSel_s1a;
input [63:0] ib0_obx_InDat_s1a;
input [1:0] ib0_obx_NextPort_s1a;
input [3:0] ib0_obx_NextVc_s1a;
input ib1_obx_PortSel_s1a;
input [63:0] ib1_obx_InDat_s1a;
input [1:0] ib1_obx_NextPort_s1a;
input [3:0] ib1_obx_NextVc_s1a;
input ib2_obx_PortSel_s1a;
input [63:0] ib2_obx_InDat_s1a;
input [1:0] ib2_obx_NextPort_s1a;
input [3:0] ib2_obx_NextVc_s1a;
input ib3_obx_PortSel_s1a;
input [63:0] ib3_obx_InDat_s1a;
input [1:0] ib3_obx_NextPort_s1a;
input [3:0] ib3_obx_NextVc_s1a;
input rp_is_full;
input rp_in_progress;
input [15:0] rp_arb_poolmask;
input [63:0] rp_arb_bufbusy_mask;
output xbx_grant_cycle;
output bp1_grant_cycle;
output set_arbitration_enable_d1;
output [63:0] reset_ackbuf;
output [63:0] wait_for_ack;
output [63:0] ice9_databus;
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bp1_grant0; // From bp1 of FswBypassArbiter.v
wire bp1_grant1; // From bp1 of FswBypassArbiter.v
wire bp1_grant2; // From bp1 of FswBypassArbiter.v
wire bp1_grant3; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d1; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d2; // From bp1 of FswBypassArbiter.v
wire bp1_header; // From bp1 of FswBypassArbiter.v
wire bp1_header_d1; // From bp1 of FswBypassArbiter.v
wire bp1_header_d2; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector_d1;// From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d1; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d2; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d1; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d2; // From bp1 of FswBypassArbiter.v
wire bp1_select; // From bp1 of FswBypassArbiter.v
wire bp1_select_d1; // From bp1 of FswBypassArbiter.v
wire bp1_select_d2; // From bp1 of FswBypassArbiter.v
wire bp2_grant0; // From bp2 of FswBypassArbiter.v
wire bp2_grant1; // From bp2 of FswBypassArbiter.v
wire bp2_grant2; // From bp2 of FswBypassArbiter.v
wire bp2_grant3; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d1; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d2; // From bp2 of FswBypassArbiter.v
wire bp2_header; // From bp2 of FswBypassArbiter.v
wire bp2_header_d1; // From bp2 of FswBypassArbiter.v
wire bp2_header_d2; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector_d1;// From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d1; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d2; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d1; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d2; // From bp2 of FswBypassArbiter.v
wire bp2_select; // From bp2 of FswBypassArbiter.v
wire bp2_select_d1; // From bp2 of FswBypassArbiter.v
wire bp2_select_d2; // From bp2 of FswBypassArbiter.v
wire bp3_grant0; // From bp3 of FswBypassArbiter.v
wire bp3_grant1; // From bp3 of FswBypassArbiter.v
wire bp3_grant2; // From bp3 of FswBypassArbiter.v
wire bp3_grant3; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d1; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d2; // From bp3 of FswBypassArbiter.v
wire bp3_header; // From bp3 of FswBypassArbiter.v
wire bp3_header_d1; // From bp3 of FswBypassArbiter.v
wire bp3_header_d2; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector_d1;// From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d1; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d2; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d1; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d2; // From bp3 of FswBypassArbiter.v
wire bp3_select; // From bp3 of FswBypassArbiter.v
wire bp3_select_d1; // From bp3 of FswBypassArbiter.v
wire bp3_select_d2; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] bp_performance_count;
reg [63:0] ice9_databus;
reg insert_idle_ack;
reg obx_xb0_GntByp_s3a;
reg obx_xb0_GntPst_s3a;
reg obx_xb1_GntByp_s3a;
reg obx_xb1_GntPst_s3a;
reg obx_xb2_GntByp_s3a;
reg obx_xb2_GntPst_s3a;
reg obx_xb3_GntByp_s3a;
reg obx_xb3_GntPst_s3a;
reg [63:0] reset_ackbuf;
reg set_arbitration_enable_d1;
reg [63:0] wait_for_ack;
reg [3:0] xb_ecc_error_1bit;
reg [3:0] xb_ecc_error_dbit;
reg xbx_grant_cycle;
// End of automatics
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp3_enable_3),
.sop2 (sop2 & xbx_bp3_enable_2),
.sop1 (sop1 & xbx_bp3_enable_1),
.sop0 (sop0 & xbx_bp3_enable_0),
); */
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp3_grant3), // Templated
.bp_grant2 (bp3_grant2), // Templated
.bp_grant1 (bp3_grant1), // Templated
.bp_grant0 (bp3_grant0), // Templated
.bp_grant_cycle (bp3_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp3_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp3_grant_cycle_d2), // Templated
.bp_next_winner (bp3_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp3_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp3_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp3_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp3_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp3_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp3_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp3_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp3_header), // Templated
.bp_header_d1 (bp3_header_d1), // Templated
.bp_header_d2 (bp3_header_d2), // Templated
.bp_select (bp3_select), // Templated
.bp_select_d1 (bp3_select_d1), // Templated
.bp_select_d2 (bp3_select_d2), // Templated
// Inputs
.lreset_l (bp3_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp3_arb_enable), // Templated
.sop3 (sop3 & xbx_bp3_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp3_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp3_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp3_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp2_enable_3),
.sop2 (sop2 & xbx_bp2_enable_2),
.sop1 (sop1 & xbx_bp2_enable_1),
.sop0 (sop0 & xbx_bp2_enable_0),
); */
FswBypassArbiter bp2 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp2_grant3), // Templated
.bp_grant2 (bp2_grant2), // Templated
.bp_grant1 (bp2_grant1), // Templated
.bp_grant0 (bp2_grant0), // Templated
.bp_grant_cycle (bp2_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp2_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp2_grant_cycle_d2), // Templated
.bp_next_winner (bp2_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp2_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp2_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp2_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp2_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp2_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp2_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp2_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp2_header), // Templated
.bp_header_d1 (bp2_header_d1), // Templated
.bp_header_d2 (bp2_header_d2), // Templated
.bp_select (bp2_select), // Templated
.bp_select_d1 (bp2_select_d1), // Templated
.bp_select_d2 (bp2_select_d2), // Templated
// Inputs
.lreset_l (bp2_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp2_arb_enable), // Templated
.sop3 (sop3 & xbx_bp2_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp2_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp2_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp2_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & csr_bp1_enable_3),
.sop2 (sop2 & csr_bp1_enable_2),
.sop1 (sop1 & csr_bp1_enable_1),
.sop0 (sop0 & csr_bp1_enable_0),
); */
FswBypassArbiter bp1 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp1_grant3), // Templated
.bp_grant2 (bp1_grant2), // Templated
.bp_grant1 (bp1_grant1), // Templated
.bp_grant0 (bp1_grant0), // Templated
.bp_grant_cycle (bp1_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp1_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp1_grant_cycle_d2), // Templated
.bp_next_winner (bp1_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp1_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp1_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp1_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp1_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp1_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp1_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp1_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp1_header), // Templated
.bp_header_d1 (bp1_header_d1), // Templated
.bp_header_d2 (bp1_header_d2), // Templated
.bp_select (bp1_select), // Templated
.bp_select_d1 (bp1_select_d1), // Templated
.bp_select_d2 (bp1_select_d2), // Templated
// Inputs
.lreset_l (bp1_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp1_arb_enable), // Templated
.sop3 (sop3 & csr_bp1_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & csr_bp1_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & csr_bp1_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & csr_bp1_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
// =======================================
// Coverage
// =======================================
// psl default clock = negedge sclk;
generate if (DMAO == 0)
begin
// psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
// psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
// psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
end
endgenerate
// ================
// Unused signals
// ================
// lint_checking SCX_UNUSED off
wire _unused_ok = &{1'b0,
bp_select,
bp3_hold_wait_vector,
bp2_hold_wait_vector_d1,
bp1_hold_wait_vector_d1,
bp3_header,
bp3_header_d1,
bp3_select,
bp3_select_d1,
bp3_next_winner[1:0],
bp3_next_winner_d1[1:0],
bp3_nextxbe[3:0],
bp3_nextxbe_d1[3:0],
bp2_grant_cycle_d2,
bp2_header,
bp2_header_d2,
bp2_select,
bp2_select_d2,
bp2_next_winner[1:0],
bp2_next_winner_d2[1:0],
bp2_nextxbe[3:0],
bp2_nextxbe_d2[3:0],
bp1_header_d1,
bp1_header_d2,
bp1_select_d1,
bp1_select_d2,
bp1_next_winner_d1[1:0],
bp1_next_winner_d2[1:0],
bp1_nextxbe_d1[3:0],
bp1_nextxbe_d2[3:0],
xb0_obx_NextXbe_s3a, // This is unused signal now.
xb1_obx_NextXbe_s3a,
xb2_obx_NextXbe_s3a,
xb3_obx_NextXbe_s3a,
syn64,
dataout64,
1'b0
};
// lint_checking SCX_UNUSED on
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
bp_grant3, bp_grant2, bp_grant1, bp_grant0, bp_grant_cycle, bp_grant_cycle_d1, bp_grant_cycle_d2,
bp_next_winner, bp_next_winner_d1, bp_next_winner_d2, bp_nextxbe, bp_nextxbe_d1, bp_nextxbe_d2,
bp_hold_wait_vector, bp_hold_wait_vector_d1, bp_header, bp_header_d1, bp_header_d2, bp_select,
bp_select_d1, bp_select_d2,
// Inputs
lreset_l, sclk, bp_arb_enable, sop3, sop3_data, sop3_bpcontext, sop2, sop2_data, sop2_bpcontext,
sop1, sop1_data, sop1_bpcontext, sop0, sop0_data, sop0_bpcontext, poolmask, bufbusy_mask
) ;
input lreset_l;
input sclk;
input bp_arb_enable;
output bp_grant3;
output bp_grant2;
output bp_grant1;
output bp_grant0;
output bp_grant_cycle;
output bp_grant_cycle_d1;
output bp_grant_cycle_d2;
output [1:0] bp_next_winner;
output [1:0] bp_next_winner_d1;
output [1:0] bp_next_winner_d2;
output [3:0] bp_nextxbe;
output [3:0] bp_nextxbe_d1;
output [3:0] bp_nextxbe_d2;
output [5:0] bp_hold_wait_vector;
output [5:0] bp_hold_wait_vector_d1;
output bp_header;
output bp_header_d1;
output bp_header_d2;
output bp_select;
output bp_select_d1;
output bp_select_d2;
input sop3;
input [63:0] sop3_data;
input [5:0] sop3_bpcontext;
input sop2;
input [63:0] sop2_data;
input [5:0] sop2_bpcontext;
input sop1;
input [63:0] sop1_data;
input [5:0] sop1_bpcontext;
input sop0;
input [63:0] sop0_data;
input [5:0] sop0_bpcontext;
input [15:0] poolmask;
input [63:0] bufbusy_mask;
endmodule
|
// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
// ANY MANUAL CHANGES WILL BE LOST
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:0] wb_iwmb_bte_i,
output [31:0] wb_iwmb_dat_o,
output wb_iwmb_ack_o,
output wb_iwmb_err_o,
output wb_iwmb_rty_o,
input [31:0] wb_dwmb_adr_i,
input [31:0] wb_dwmb_dat_i,
input [3:0] wb_dwmb_sel_i,
input wb_dwmb_we_i,
input wb_dwmb_cyc_i,
input wb_dwmb_stb_i,
input [2:0] wb_dwmb_cti_i,
input [1:0] wb_dwmb_bte_i,
output [31:0] wb_dwmb_dat_o,
output wb_dwmb_ack_o,
output wb_dwmb_err_o,
output wb_dwmb_rty_o,
output [31:0] wb_uart_adr_o,
output [31:0] wb_uart_dat_o,
output [3:0] wb_uart_sel_o,
output wb_uart_we_o,
output wb_uart_cyc_o,
output wb_uart_stb_o,
output [2:0] wb_uart_cti_o,
output [1:0] wb_uart_bte_o,
input [31:0] wb_uart_dat_i,
input wb_uart_ack_i,
input wb_uart_err_i,
input wb_uart_rty_i,
output [31:0] wb_ram_adr_o,
output [31:0] wb_ram_dat_o,
output [3:0] wb_ram_sel_o,
output wb_ram_we_o,
output wb_ram_cyc_o,
output wb_ram_stb_o,
output [2:0] wb_ram_cti_o,
output [1:0] wb_ram_bte_o,
input [31:0] wb_ram_dat_i,
input wb_ram_ack_i,
input wb_ram_err_i,
input wb_ram_rty_i,
output [31:0] wb_rom_adr_o,
output [31:0] wb_rom_dat_o,
output [3:0] wb_rom_sel_o,
output wb_rom_we_o,
output wb_rom_cyc_o,
output wb_rom_stb_o,
output [2:0] wb_rom_cti_o,
output [1:0] wb_rom_bte_o,
input [31:0] wb_rom_dat_i,
input wb_rom_ack_i,
input wb_rom_err_i,
input wb_rom_rty_i,
output [31:0] wb_fw_interface_adr_o,
output [31:0] wb_fw_interface_dat_o,
output [3:0] wb_fw_interface_sel_o,
output wb_fw_interface_we_o,
output wb_fw_interface_cyc_o,
output wb_fw_interface_stb_o,
output [2:0] wb_fw_interface_cti_o,
output [1:0] wb_fw_interface_bte_o,
input [31:0] wb_fw_interface_dat_i,
input wb_fw_interface_ack_i,
input wb_fw_interface_err_i,
input wb_fw_interface_rty_i);
wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire [3:0] wb_m2s_iwmb_ram_sel;
wire wb_m2s_iwmb_ram_we;
wire wb_m2s_iwmb_ram_cyc;
wire wb_m2s_iwmb_ram_stb;
wire [2:0] wb_m2s_iwmb_ram_cti;
wire [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire wb_s2m_iwmb_ram_ack;
wire wb_s2m_iwmb_ram_err;
wire wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire [3:0] wb_m2s_iwmb_rom_sel;
wire wb_m2s_iwmb_rom_we;
wire wb_m2s_iwmb_rom_cyc;
wire wb_m2s_iwmb_rom_stb;
wire [2:0] wb_m2s_iwmb_rom_cti;
wire [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire wb_s2m_iwmb_rom_ack;
wire wb_s2m_iwmb_rom_err;
wire wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire [3:0] wb_m2s_iwmb_uart_sel;
wire wb_m2s_iwmb_uart_we;
wire wb_m2s_iwmb_uart_cyc;
wire wb_m2s_iwmb_uart_stb;
wire [2:0] wb_m2s_iwmb_uart_cti;
wire [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire wb_s2m_iwmb_uart_ack;
wire wb_s2m_iwmb_uart_err;
wire wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_fw_interface_adr;
wire [31:0] wb_m2s_iwmb_fw_interface_dat;
wire [3:0] wb_m2s_iwmb_fw_interface_sel;
wire wb_m2s_iwmb_fw_interface_we;
wire wb_m2s_iwmb_fw_interface_cyc;
wire wb_m2s_iwmb_fw_interface_stb;
wire [2:0] wb_m2s_iwmb_fw_interface_cti;
wire [1:0] wb_m2s_iwmb_fw_interface_bte;
wire [31:0] wb_s2m_iwmb_fw_interface_dat;
wire wb_s2m_iwmb_fw_interface_ack;
wire wb_s2m_iwmb_fw_interface_err;
wire wb_s2m_iwmb_fw_interface_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire [3:0] wb_m2s_dwmb_uart_sel;
wire wb_m2s_dwmb_uart_we;
wire wb_m2s_dwmb_uart_cyc;
wire wb_m2s_dwmb_uart_stb;
wire [2:0] wb_m2s_dwmb_uart_cti;
wire [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire wb_s2m_dwmb_uart_ack;
wire wb_s2m_dwmb_uart_err;
wire wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire [3:0] wb_m2s_dwmb_ram_sel;
wire wb_m2s_dwmb_ram_we;
wire wb_m2s_dwmb_ram_cyc;
wire wb_m2s_dwmb_ram_stb;
wire [2:0] wb_m2s_dwmb_ram_cti;
wire [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire wb_s2m_dwmb_ram_ack;
wire wb_s2m_dwmb_ram_err;
wire wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire [3:0] wb_m2s_dwmb_rom_sel;
wire wb_m2s_dwmb_rom_we;
wire wb_m2s_dwmb_rom_cyc;
wire wb_m2s_dwmb_rom_stb;
wire [2:0] wb_m2s_dwmb_rom_cti;
wire [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire wb_s2m_dwmb_rom_ack;
wire wb_s2m_dwmb_rom_err;
wire wb_s2m_dwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_fw_interface_adr;
wire [31:0] wb_m2s_dwmb_fw_interface_dat;
wire [3:0] wb_m2s_dwmb_fw_interface_sel;
wire wb_m2s_dwmb_fw_interface_we;
wire wb_m2s_dwmb_fw_interface_cyc;
wire wb_m2s_dwmb_fw_interface_stb;
wire [2:0] wb_m2s_dwmb_fw_interface_cti;
wire [1:0] wb_m2s_dwmb_fw_interface_bte;
wire [31:0] wb_s2m_dwmb_fw_interface_dat;
wire wb_s2m_dwmb_fw_interface_ack;
wire wb_s2m_dwmb_fw_interface_err;
wire wb_s2m_dwmb_fw_interface_rty;
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h20000000, 32'h00000000, 32'h40000000, 32'he0000000}),
.MATCH_MASK ({32'hffff8000, 32'hffff8000, 32'hffffffe0, 32'hffffff80}))
wb_mux_iwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_iwmb_adr_i),
.wbm_dat_i (wb_iwmb_dat_i),
.wbm_sel_i (wb_iwmb_sel_i),
.wbm_we_i (wb_iwmb_we_i),
.wbm_cyc_i (wb_iwmb_cyc_i),
.wbm_stb_i (wb_iwmb_stb_i),
.wbm_cti_i (wb_iwmb_cti_i),
.wbm_bte_i (wb_iwmb_bte_i),
.wbm_dat_o (wb_iwmb_dat_o),
.wbm_ack_o (wb_iwmb_ack_o),
.wbm_err_o (wb_iwmb_err_o),
.wbm_rty_o (wb_iwmb_rty_o),
.wbs_adr_o ({wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr, wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat, wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel, wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we, wb_m2s_iwmb_uart_we, wb_m2s_iwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc, wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb, wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti, wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte, wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat, wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack, wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err, wb_s2m_iwmb_uart_err, wb_s2m_iwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty, wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_fw_interface_rty}));
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000, 32'he0000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000, 32'hffffff80}))
wb_mux_dwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dwmb_adr_i),
.wbm_dat_i (wb_dwmb_dat_i),
.wbm_sel_i (wb_dwmb_sel_i),
.wbm_we_i (wb_dwmb_we_i),
.wbm_cyc_i (wb_dwmb_cyc_i),
.wbm_stb_i (wb_dwmb_stb_i),
.wbm_cti_i (wb_dwmb_cti_i),
.wbm_bte_i (wb_dwmb_bte_i),
.wbm_dat_o (wb_dwmb_dat_o),
.wbm_ack_o (wb_dwmb_ack_o),
.wbm_err_o (wb_dwmb_err_o),
.wbm_rty_o (wb_dwmb_rty_o),
.wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we, wb_m2s_dwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err, wb_s2m_dwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty, wb_s2m_dwmb_fw_interface_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
.wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
.wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
.wbm_we_i ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
.wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
.wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
.wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
.wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
.wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
.wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
.wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
.wbs_adr_o (wb_uart_adr_o),
.wbs_dat_o (wb_uart_dat_o),
.wbs_sel_o (wb_uart_sel_o),
.wbs_we_o (wb_uart_we_o),
.wbs_cyc_o (wb_uart_cyc_o),
.wbs_stb_o (wb_uart_stb_o),
.wbs_cti_o (wb_uart_cti_o),
.wbs_bte_o (wb_uart_bte_o),
.wbs_dat_i (wb_uart_dat_i),
.wbs_ack_i (wb_uart_ack_i),
.wbs_err_i (wb_uart_err_i),
.wbs_rty_i (wb_uart_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_ram
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
.wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
.wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
.wbm_we_i ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
.wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
.wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
.wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
.wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
.wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
.wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
.wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
.wbs_adr_o (wb_ram_adr_o),
.wbs_dat_o (wb_ram_dat_o),
.wbs_sel_o (wb_ram_sel_o),
.wbs_we_o (wb_ram_we_o),
.wbs_cyc_o (wb_ram_cyc_o),
.wbs_stb_o (wb_ram_stb_o),
.wbs_cti_o (wb_ram_cti_o),
.wbs_bte_o (wb_ram_bte_o),
.wbs_dat_i (wb_ram_dat_i),
.wbs_ack_i (wb_ram_ack_i),
.wbs_err_i (wb_ram_err_i),
.wbs_rty_i (wb_ram_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_rom
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
.wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
.wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
.wbm_we_i ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
.wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
.wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
.wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
.wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
.wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
.wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
.wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
.wbs_adr_o (wb_rom_adr_o),
.wbs_dat_o (wb_rom_dat_o),
.wbs_sel_o (wb_rom_sel_o),
.wbs_we_o (wb_rom_we_o),
.wbs_cyc_o (wb_rom_cyc_o),
.wbs_stb_o (wb_rom_stb_o),
.wbs_cti_o (wb_rom_cti_o),
.wbs_bte_o (wb_rom_bte_o),
.wbs_dat_i (wb_rom_dat_i),
.wbs_ack_i (wb_rom_ack_i),
.wbs_err_i (wb_rom_err_i),
.wbs_rty_i (wb_rom_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_fw_interface
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_fw_interface_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbm_dat_i ({wb_m2s_iwmb_fw_interface_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbm_sel_i ({wb_m2s_iwmb_fw_interface_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbm_we_i ({wb_m2s_iwmb_fw_interface_we, wb_m2s_dwmb_fw_interface_we}),
.wbm_cyc_i ({wb_m2s_iwmb_fw_interface_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_fw_interface_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbm_cti_i ({wb_m2s_iwmb_fw_interface_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbm_bte_i ({wb_m2s_iwmb_fw_interface_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbm_dat_o ({wb_s2m_iwmb_fw_interface_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbm_ack_o ({wb_s2m_iwmb_fw_interface_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbm_err_o ({wb_s2m_iwmb_fw_interface_err, wb_s2m_dwmb_fw_interface_err}),
.wbm_rty_o ({wb_s2m_iwmb_fw_interface_rty, wb_s2m_dwmb_fw_interface_rty}),
.wbs_adr_o (wb_fw_interface_adr_o),
.wbs_dat_o (wb_fw_interface_dat_o),
.wbs_sel_o (wb_fw_interface_sel_o),
.wbs_we_o (wb_fw_interface_we_o),
.wbs_cyc_o (wb_fw_interface_cyc_o),
.wbs_stb_o (wb_fw_interface_stb_o),
.wbs_cti_o (wb_fw_interface_cti_o),
.wbs_bte_o (wb_fw_interface_bte_o),
.wbs_dat_i (wb_fw_interface_dat_i),
.wbs_ack_i (wb_fw_interface_ack_i),
.wbs_err_i (wb_fw_interface_err_i),
.wbs_rty_i (wb_fw_interface_rty_i));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_ll(clock, enable, resetn, dataa, datab, result);
// This is a version of the adder with reduced latency.
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 8.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 0;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
/* salsa-B.v for use with hashvariant-B.v
Based on salsa3.v ... registered at the column-row interface (and final row output)
Latency 2 clock cycle hence 4 salsa iterations in 8 cycles.
NB Columns feed forward two levels into rows, so this is likely to be NON-OPTIMAL.
HMMM, not sure if I can sensibly implement this, but I'll give it a go [MAYBE errors, possibly
explaining higher clock speed!]
THE FOLLOWING is for the OBSOLETE salsa-B1.v
TODO redo it in ../SALSA for this version
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Clocks 59/25 = 2.4 times faster, so the 4 cycle latency gives a slightly highe throughput overall!!
But wwhat about overclocking? TODO try for real.
AHA ... its because I've registered the salsa_core output, which is NOT what I actually want
as it breaks the FSM timing. Rename this salsa-B1.v and adjust the registers in salsa-B.v
200MHz clock gives (ltcminer.sta.rpt) ... HMM should have used 60MHz, but good result anyway
+------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+-----------+-----------------+-----------------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+-----------------------------------------------------+------+
; 59.08 MHz ; 59.08 MHz ; pll_blk|altpll_component|auto_generated|pll1|clk[0] ; ;
+-----------+-----------------+-----------------------------------------------------+------+
-----------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+--------------------------------------------+--------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -11.925 ; mixfeedback ; salsa:salsa_blk|salsa_core:salsa1|c10d[15] ; pll_blk|altpll_component|auto_generated|pll1|clk[0] ; pll_blk|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; 0.272 ; 17.192 ;
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, feedback, B, Bx, Bo);
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
wire [511:0]xx; // Initial xor
wire [511:0]xr;
reg [511:0]xrd;
//salsa_core salsa1 (clk, feedback ? xr : xx, xr); // unregistered xr
salsa_core salsa1 (clk, feedback ? xrd : xx, xr); // registered xrd
reg [511:0]xxd;
always @ (posedge clk)
begin
xxd <= xx;
xrd <= xr;
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
// assign Bo[`IDX(i)] = xx[`IDX(i)] + xr[`IDX(i)]; // Original
assign Bo[`IDX(i)] = xxd[`IDX(i)] + xr[`IDX(i)]; // Salsa-B
end
endgenerate
endmodule
module salsa_core (clk, xx, out);
input clk;
input [511:0]xx;
output [511:0]out; // NB out remains UNREGISTERED even though I have added c00d etc registers
// output reg [511:0]out;
// Some debugging assignments so we can check the word format
/*
wire [31:0]x00;
wire [31:0]x04;
wire [31:0]x12;
assign x00 = xx[`IDX(0)];
assign x04 = xx[`IDX(4)];
assign x12 = xx[`IDX(12)];
*/
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00; // Row results
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
reg [31:0]c00d; // Column results registered
reg [31:0]c01d;
reg [31:0]c02d;
reg [31:0]c03d;
reg [31:0]c04d;
reg [31:0]c05d;
reg [31:0]c06d;
reg [31:0]c07d;
reg [31:0]c08d;
reg [31:0]c09d;
reg [31:0]c10d;
reg [31:0]c11d;
reg [31:0]c12d;
reg [31:0]c13d;
reg [31:0]c14d;
reg [31:0]c15d;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
// rows
assign r01s = c00d + c03d;
assign r01 = c01d ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05d + c04d;
assign r06 = c06d ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10d + c09d;
assign r11 = c11d ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15d + c14d;
assign r12 = c12d ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00d;
assign r02 = c02d ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05d;
assign r07 = c07d ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10d;
assign r08 = c08d ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15d;
assign r13 = c13d ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03d ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04d ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09d ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14d ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00d ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05d ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10d ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15d ^ { r15s[13:0], r15s[31:14] };
wire [511:0]xo; // Rename row results
assign xo = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
always @ (posedge clk)
begin
c00d <= c00;
c01d <= c01;
c02d <= c02;
c03d <= c03;
c04d <= c04;
c05d <= c05;
c06d <= c06;
c07d <= c07;
c08d <= c08;
c09d <= c09;
c10d <= c10;
c11d <= c11;
c12d <= c12;
c13d <= c13;
c14d <= c14;
c15d <= c15;
// out <= xo; // registered version
end
assign out = xo; // unregistered version
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I.T.C.R
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:02:57 02/28/2016
// Design Name:
// Module Name: Conversor_BCD_7seg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Conversor_BCD_7seg
(
input wire [3:0] Valor_Decimal,
output reg [7:0] Code_7seg
);
//Descripción combinacional del valor decimal a código para el 7 segmentos
always @*
begin
case(Valor_Decimal)
4'h0: Code_7seg = 8'b00000011; //0
4'h1: Code_7seg = 8'b10011111; //1
4'h2: Code_7seg = 8'b00100101; //2
4'h3: Code_7seg = 8'b00001101; //3
4'h4: Code_7seg = 8'b10011001; //4
4'h5: Code_7seg = 8'b01001001; //5
4'h6: Code_7seg = 8'b01000001; //6
4'h7: Code_7seg = 8'b00011111; //8
4'h8: Code_7seg = 8'b00000001; //9
4'h9: Code_7seg = 8'b00001001; //Caso default no enciende el 7 seg
default: Code_7seg = 8'b11111111;
endcase
end
endmodule
|
module uart ( input[15:0] din, output[15:0] dout, input a0, input rnw, input clk, input reset_b, input cs_b, input rxd, output txd);
// CLKSPEED is the main clock speed
parameter CLKSPEED = 32000000;
// BAUD is the desired serial baud rate
parameter BAUD = 115200;
// DIVISOR is the number of clk cycles per bit time
parameter DIVISOR = CLKSPEED / BAUD;
// Registers
reg [15:0] rx_bit_cnt = 0;
reg [15:0] tx_bit_cnt;
reg [10:0] tx_shift_reg;
reg [9:0] rx_shift_reg;
reg rxd1;
reg rxd2;
reg rx_full = 1'b0;
reg [7:0] rx_data;
wire rx_busy;
wire tx_busy;
// Assignments
assign rx_busy = rx_shift_reg != 10'b1111111111;
assign tx_busy = tx_shift_reg != 11'b1;
assign txd = tx_shift_reg[0];
assign dout = a0 ? {8'h00, rx_data} : { tx_busy, rx_full, 14'b0};
// UART Receiver
always @ (posedge clk) begin
rxd1 <= rxd;
rxd2 <= rxd1;
if (!cs_b && rnw && a0) begin
rx_full <= 1'b0;
end
if (!reset_b) begin
rx_shift_reg <= 10'b1111111111;
end else if (!rx_shift_reg[0]) begin
rx_shift_reg <= 10'b1111111111;
rx_data <= rx_shift_reg[9:2];
rx_full <= 1;
end else if (rx_busy) begin
if (rx_bit_cnt == 0) begin
rx_bit_cnt <= DIVISOR;
rx_shift_reg <= {rxd1 , rx_shift_reg[9:1]};
end else begin
rx_bit_cnt <= rx_bit_cnt - 1;
end
end else if (!rxd1 && rxd2) begin
rx_shift_reg <= 10'b0111111111;
rx_bit_cnt <= DIVISOR >> 1;
end
end
// UART Transmitter
always @ (posedge clk)
if (!reset_b) begin
tx_shift_reg <= 11'b1;
end else if (tx_busy) begin
if (tx_bit_cnt == 0) begin
tx_shift_reg <= {1'b0 , tx_shift_reg[10:1]};
tx_bit_cnt <= DIVISOR - 1;
end else begin
tx_bit_cnt <= tx_bit_cnt - 1;
end
end else if (!cs_b && !rnw && a0) begin
tx_shift_reg <= {2'b11, din[7:0], 1'b0};
tx_bit_cnt <= DIVISOR - 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_SYMBOL_V
`define SKY130_FD_SC_HDLL__EINVN_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_SYMBOL_V
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ([email protected])
//Last Modified: Feb 25 2014
//Description: MBUS Analog Block Example
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module ablk
(
//**************************************
//Power Domain
//Input - Own Power Domain
//Output - N/A
//**************************************
//Signals
//Input
ABLK_PG, //Active High
ABLK_RESETn, //Active Low
ABLK_EN, //Active High
ABLK_CONFIG_0,//Config Bits
ABLK_CONFIG_1 //Config Bits
//Output
);
input ABLK_PG;
input ABLK_RESETn;
input ABLK_EN;
input [3:0] ABLK_CONFIG_0;
input [3:0] ABLK_CONFIG_1;
always @(ABLK_PG) begin
$write("%c[1;34m",27);
$display("ablk Input ABLK_PG Has been changed to:%x", ABLK_PG);
$write("%c[0m",27);
end
always @(ABLK_RESETn) begin
$write("%c[1;34m",27);
$display("ablk Input ABLK_RESETn Has been changed to:%x", ABLK_RESETn);
$write("%c[0m",27);
end
always @(ABLK_EN) begin
$write("%c[1;34m",27);
$display("ablk Input ABLK_EN Has been changed to:%x", ABLK_EN);
$write("%c[0m",27);
end
always @(ABLK_CONFIG_0) begin
$write("%c[1;34m",27);
$display("ablk Input ABLK_CONFIG_0 Has been changed to:%x", ABLK_CONFIG_0);
$write("%c[0m",27);
end
always @(ABLK_CONFIG_1) begin
$write("%c[1;34m",27);
$display("ablk Input ABLK_CONFIG_1 Has been changed to:%x", ABLK_CONFIG_1);
$write("%c[0m",27);
end
endmodule // ablk
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.633800,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=14,HLS_SYN_FF=5893,HLS_SYN_LUT=3947}" *)
module convolve_kernel (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
bufw_Addr_A,
bufw_EN_A,
bufw_WEN_A,
bufw_Din_A,
bufw_Dout_A,
bufw_Clk_A,
bufw_Rst_A,
bufi_Addr_A,
bufi_EN_A,
bufi_WEN_A,
bufi_Din_A,
bufi_Dout_A,
bufi_Clk_A,
bufi_Rst_A,
bufo_0_Addr_A,
bufo_0_EN_A,
bufo_0_WEN_A,
bufo_0_Din_A,
bufo_0_Dout_A,
bufo_0_Clk_A,
bufo_0_Rst_A,
bufo_1_Addr_A,
bufo_1_EN_A,
bufo_1_WEN_A,
bufo_1_Din_A,
bufo_1_Dout_A,
bufo_1_Clk_A,
bufo_1_Rst_A,
bufo_2_Addr_A,
bufo_2_EN_A,
bufo_2_WEN_A,
bufo_2_Din_A,
bufo_2_Dout_A,
bufo_2_Clk_A,
bufo_2_Rst_A,
bufo_3_Addr_A,
bufo_3_EN_A,
bufo_3_WEN_A,
bufo_3_Din_A,
bufo_3_Dout_A,
bufo_3_Clk_A,
bufo_3_Rst_A,
bufo_4_Addr_A,
bufo_4_EN_A,
bufo_4_WEN_A,
bufo_4_Din_A,
bufo_4_Dout_A,
bufo_4_Clk_A,
bufo_4_Rst_A,
bufo_5_Addr_A,
bufo_5_EN_A,
bufo_5_WEN_A,
bufo_5_Din_A,
bufo_5_Dout_A,
bufo_5_Clk_A,
bufo_5_Rst_A,
bufo_6_Addr_A,
bufo_6_EN_A,
bufo_6_WEN_A,
bufo_6_Din_A,
bufo_6_Dout_A,
bufo_6_Clk_A,
bufo_6_Rst_A,
bufo_7_Addr_A,
bufo_7_EN_A,
bufo_7_WEN_A,
bufo_7_Din_A,
bufo_7_Dout_A,
bufo_7_Clk_A,
bufo_7_Rst_A,
bufo_8_Addr_A,
bufo_8_EN_A,
bufo_8_WEN_A,
bufo_8_Din_A,
bufo_8_Dout_A,
bufo_8_Clk_A,
bufo_8_Rst_A,
bufo_9_Addr_A,
bufo_9_EN_A,
bufo_9_WEN_A,
bufo_9_Din_A,
bufo_9_Dout_A,
bufo_9_Clk_A,
bufo_9_Rst_A,
bufo_10_Addr_A,
bufo_10_EN_A,
bufo_10_WEN_A,
bufo_10_Din_A,
bufo_10_Dout_A,
bufo_10_Clk_A,
bufo_10_Rst_A,
bufo_11_Addr_A,
bufo_11_EN_A,
bufo_11_WEN_A,
bufo_11_Din_A,
bufo_11_Dout_A,
bufo_11_Clk_A,
bufo_11_Rst_A,
bufo_12_Addr_A,
bufo_12_EN_A,
bufo_12_WEN_A,
bufo_12_Din_A,
bufo_12_Dout_A,
bufo_12_Clk_A,
bufo_12_Rst_A,
bufo_13_Addr_A,
bufo_13_EN_A,
bufo_13_WEN_A,
bufo_13_Din_A,
bufo_13_Dout_A,
bufo_13_Clk_A,
bufo_13_Rst_A,
bufo_14_Addr_A,
bufo_14_EN_A,
bufo_14_WEN_A,
bufo_14_Din_A,
bufo_14_Dout_A,
bufo_14_Clk_A,
bufo_14_Rst_A,
bufo_15_Addr_A,
bufo_15_EN_A,
bufo_15_WEN_A,
bufo_15_Din_A,
bufo_15_Dout_A,
bufo_15_Clk_A,
bufo_15_Rst_A,
bufo_16_Addr_A,
bufo_16_EN_A,
bufo_16_WEN_A,
bufo_16_Din_A,
bufo_16_Dout_A,
bufo_16_Clk_A,
bufo_16_Rst_A,
bufo_17_Addr_A,
bufo_17_EN_A,
bufo_17_WEN_A,
bufo_17_Din_A,
bufo_17_Dout_A,
bufo_17_Clk_A,
bufo_17_Rst_A,
bufo_18_Addr_A,
bufo_18_EN_A,
bufo_18_WEN_A,
bufo_18_Din_A,
bufo_18_Dout_A,
bufo_18_Clk_A,
bufo_18_Rst_A,
bufo_19_Addr_A,
bufo_19_EN_A,
bufo_19_WEN_A,
bufo_19_Din_A,
bufo_19_Dout_A,
bufo_19_Clk_A,
bufo_19_Rst_A,
bufo_20_Addr_A,
bufo_20_EN_A,
bufo_20_WEN_A,
bufo_20_Din_A,
bufo_20_Dout_A,
bufo_20_Clk_A,
bufo_20_Rst_A,
bufo_21_Addr_A,
bufo_21_EN_A,
bufo_21_WEN_A,
bufo_21_Din_A,
bufo_21_Dout_A,
bufo_21_Clk_A,
bufo_21_Rst_A,
bufo_22_Addr_A,
bufo_22_EN_A,
bufo_22_WEN_A,
bufo_22_Din_A,
bufo_22_Dout_A,
bufo_22_Clk_A,
bufo_22_Rst_A,
bufo_23_Addr_A,
bufo_23_EN_A,
bufo_23_WEN_A,
bufo_23_Din_A,
bufo_23_Dout_A,
bufo_23_Clk_A,
bufo_23_Rst_A,
bufo_24_Addr_A,
bufo_24_EN_A,
bufo_24_WEN_A,
bufo_24_Din_A,
bufo_24_Dout_A,
bufo_24_Clk_A,
bufo_24_Rst_A,
bufo_25_Addr_A,
bufo_25_EN_A,
bufo_25_WEN_A,
bufo_25_Din_A,
bufo_25_Dout_A,
bufo_25_Clk_A,
bufo_25_Rst_A,
bufo_26_Addr_A,
bufo_26_EN_A,
bufo_26_WEN_A,
bufo_26_Din_A,
bufo_26_Dout_A,
bufo_26_Clk_A,
bufo_26_Rst_A,
bufo_27_Addr_A,
bufo_27_EN_A,
bufo_27_WEN_A,
bufo_27_Din_A,
bufo_27_Dout_A,
bufo_27_Clk_A,
bufo_27_Rst_A,
bufo_28_Addr_A,
bufo_28_EN_A,
bufo_28_WEN_A,
bufo_28_Din_A,
bufo_28_Dout_A,
bufo_28_Clk_A,
bufo_28_Rst_A,
bufo_29_Addr_A,
bufo_29_EN_A,
bufo_29_WEN_A,
bufo_29_Din_A,
bufo_29_Dout_A,
bufo_29_Clk_A,
bufo_29_Rst_A,
bufo_30_Addr_A,
bufo_30_EN_A,
bufo_30_WEN_A,
bufo_30_Din_A,
bufo_30_Dout_A,
bufo_30_Clk_A,
bufo_30_Rst_A,
bufo_31_Addr_A,
bufo_31_EN_A,
bufo_31_WEN_A,
bufo_31_Din_A,
bufo_31_Dout_A,
bufo_31_Clk_A,
bufo_31_Rst_A,
bufo_32_Addr_A,
bufo_32_EN_A,
bufo_32_WEN_A,
bufo_32_Din_A,
bufo_32_Dout_A,
bufo_32_Clk_A,
bufo_32_Rst_A,
bufo_33_Addr_A,
bufo_33_EN_A,
bufo_33_WEN_A,
bufo_33_Din_A,
bufo_33_Dout_A,
bufo_33_Clk_A,
bufo_33_Rst_A,
bufo_34_Addr_A,
bufo_34_EN_A,
bufo_34_WEN_A,
bufo_34_Din_A,
bufo_34_Dout_A,
bufo_34_Clk_A,
bufo_34_Rst_A,
bufo_35_Addr_A,
bufo_35_EN_A,
bufo_35_WEN_A,
bufo_35_Din_A,
bufo_35_Dout_A,
bufo_35_Clk_A,
bufo_35_Rst_A,
bufo_36_Addr_A,
bufo_36_EN_A,
bufo_36_WEN_A,
bufo_36_Din_A,
bufo_36_Dout_A,
bufo_36_Clk_A,
bufo_36_Rst_A,
bufo_37_Addr_A,
bufo_37_EN_A,
bufo_37_WEN_A,
bufo_37_Din_A,
bufo_37_Dout_A,
bufo_37_Clk_A,
bufo_37_Rst_A,
bufo_38_Addr_A,
bufo_38_EN_A,
bufo_38_WEN_A,
bufo_38_Din_A,
bufo_38_Dout_A,
bufo_38_Clk_A,
bufo_38_Rst_A,
bufo_39_Addr_A,
bufo_39_EN_A,
bufo_39_WEN_A,
bufo_39_Din_A,
bufo_39_Dout_A,
bufo_39_Clk_A,
bufo_39_Rst_A,
bufo_40_Addr_A,
bufo_40_EN_A,
bufo_40_WEN_A,
bufo_40_Din_A,
bufo_40_Dout_A,
bufo_40_Clk_A,
bufo_40_Rst_A,
bufo_41_Addr_A,
bufo_41_EN_A,
bufo_41_WEN_A,
bufo_41_Din_A,
bufo_41_Dout_A,
bufo_41_Clk_A,
bufo_41_Rst_A,
bufo_42_Addr_A,
bufo_42_EN_A,
bufo_42_WEN_A,
bufo_42_Din_A,
bufo_42_Dout_A,
bufo_42_Clk_A,
bufo_42_Rst_A,
bufo_43_Addr_A,
bufo_43_EN_A,
bufo_43_WEN_A,
bufo_43_Din_A,
bufo_43_Dout_A,
bufo_43_Clk_A,
bufo_43_Rst_A,
bufo_44_Addr_A,
bufo_44_EN_A,
bufo_44_WEN_A,
bufo_44_Din_A,
bufo_44_Dout_A,
bufo_44_Clk_A,
bufo_44_Rst_A,
bufo_45_Addr_A,
bufo_45_EN_A,
bufo_45_WEN_A,
bufo_45_Din_A,
bufo_45_Dout_A,
bufo_45_Clk_A,
bufo_45_Rst_A,
bufo_46_Addr_A,
bufo_46_EN_A,
bufo_46_WEN_A,
bufo_46_Din_A,
bufo_46_Dout_A,
bufo_46_Clk_A,
bufo_46_Rst_A,
bufo_47_Addr_A,
bufo_47_EN_A,
bufo_47_WEN_A,
bufo_47_Din_A,
bufo_47_Dout_A,
bufo_47_Clk_A,
bufo_47_Rst_A,
bufo_48_Addr_A,
bufo_48_EN_A,
bufo_48_WEN_A,
bufo_48_Din_A,
bufo_48_Dout_A,
bufo_48_Clk_A,
bufo_48_Rst_A,
bufo_49_Addr_A,
bufo_49_EN_A,
bufo_49_WEN_A,
bufo_49_Din_A,
bufo_49_Dout_A,
bufo_49_Clk_A,
bufo_49_Rst_A,
bufo_50_Addr_A,
bufo_50_EN_A,
bufo_50_WEN_A,
bufo_50_Din_A,
bufo_50_Dout_A,
bufo_50_Clk_A,
bufo_50_Rst_A,
bufo_51_Addr_A,
bufo_51_EN_A,
bufo_51_WEN_A,
bufo_51_Din_A,
bufo_51_Dout_A,
bufo_51_Clk_A,
bufo_51_Rst_A,
bufo_52_Addr_A,
bufo_52_EN_A,
bufo_52_WEN_A,
bufo_52_Din_A,
bufo_52_Dout_A,
bufo_52_Clk_A,
bufo_52_Rst_A,
bufo_53_Addr_A,
bufo_53_EN_A,
bufo_53_WEN_A,
bufo_53_Din_A,
bufo_53_Dout_A,
bufo_53_Clk_A,
bufo_53_Rst_A,
bufo_54_Addr_A,
bufo_54_EN_A,
bufo_54_WEN_A,
bufo_54_Din_A,
bufo_54_Dout_A,
bufo_54_Clk_A,
bufo_54_Rst_A,
bufo_55_Addr_A,
bufo_55_EN_A,
bufo_55_WEN_A,
bufo_55_Din_A,
bufo_55_Dout_A,
bufo_55_Clk_A,
bufo_55_Rst_A,
bufo_56_Addr_A,
bufo_56_EN_A,
bufo_56_WEN_A,
bufo_56_Din_A,
bufo_56_Dout_A,
bufo_56_Clk_A,
bufo_56_Rst_A,
bufo_57_Addr_A,
bufo_57_EN_A,
bufo_57_WEN_A,
bufo_57_Din_A,
bufo_57_Dout_A,
bufo_57_Clk_A,
bufo_57_Rst_A,
bufo_58_Addr_A,
bufo_58_EN_A,
bufo_58_WEN_A,
bufo_58_Din_A,
bufo_58_Dout_A,
bufo_58_Clk_A,
bufo_58_Rst_A,
bufo_59_Addr_A,
bufo_59_EN_A,
bufo_59_WEN_A,
bufo_59_Din_A,
bufo_59_Dout_A,
bufo_59_Clk_A,
bufo_59_Rst_A,
bufo_60_Addr_A,
bufo_60_EN_A,
bufo_60_WEN_A,
bufo_60_Din_A,
bufo_60_Dout_A,
bufo_60_Clk_A,
bufo_60_Rst_A,
bufo_61_Addr_A,
bufo_61_EN_A,
bufo_61_WEN_A,
bufo_61_Din_A,
bufo_61_Dout_A,
bufo_61_Clk_A,
bufo_61_Rst_A,
bufo_62_Addr_A,
bufo_62_EN_A,
bufo_62_WEN_A,
bufo_62_Din_A,
bufo_62_Dout_A,
bufo_62_Clk_A,
bufo_62_Rst_A,
bufo_63_Addr_A,
bufo_63_EN_A,
bufo_63_WEN_A,
bufo_63_Din_A,
bufo_63_Dout_A,
bufo_63_Clk_A,
bufo_63_Rst_A,
bufo_64_Addr_A,
bufo_64_EN_A,
bufo_64_WEN_A,
bufo_64_Din_A,
bufo_64_Dout_A,
bufo_64_Clk_A,
bufo_64_Rst_A,
bufo_65_Addr_A,
bufo_65_EN_A,
bufo_65_WEN_A,
bufo_65_Din_A,
bufo_65_Dout_A,
bufo_65_Clk_A,
bufo_65_Rst_A,
bufo_66_Addr_A,
bufo_66_EN_A,
bufo_66_WEN_A,
bufo_66_Din_A,
bufo_66_Dout_A,
bufo_66_Clk_A,
bufo_66_Rst_A,
bufo_67_Addr_A,
bufo_67_EN_A,
bufo_67_WEN_A,
bufo_67_Din_A,
bufo_67_Dout_A,
bufo_67_Clk_A,
bufo_67_Rst_A,
bufo_68_Addr_A,
bufo_68_EN_A,
bufo_68_WEN_A,
bufo_68_Din_A,
bufo_68_Dout_A,
bufo_68_Clk_A,
bufo_68_Rst_A,
bufo_69_Addr_A,
bufo_69_EN_A,
bufo_69_WEN_A,
bufo_69_Din_A,
bufo_69_Dout_A,
bufo_69_Clk_A,
bufo_69_Rst_A,
bufo_70_Addr_A,
bufo_70_EN_A,
bufo_70_WEN_A,
bufo_70_Din_A,
bufo_70_Dout_A,
bufo_70_Clk_A,
bufo_70_Rst_A,
bufo_71_Addr_A,
bufo_71_EN_A,
bufo_71_WEN_A,
bufo_71_Din_A,
bufo_71_Dout_A,
bufo_71_Clk_A,
bufo_71_Rst_A,
bufo_72_Addr_A,
bufo_72_EN_A,
bufo_72_WEN_A,
bufo_72_Din_A,
bufo_72_Dout_A,
bufo_72_Clk_A,
bufo_72_Rst_A,
bufo_73_Addr_A,
bufo_73_EN_A,
bufo_73_WEN_A,
bufo_73_Din_A,
bufo_73_Dout_A,
bufo_73_Clk_A,
bufo_73_Rst_A,
bufo_74_Addr_A,
bufo_74_EN_A,
bufo_74_WEN_A,
bufo_74_Din_A,
bufo_74_Dout_A,
bufo_74_Clk_A,
bufo_74_Rst_A,
bufo_75_Addr_A,
bufo_75_EN_A,
bufo_75_WEN_A,
bufo_75_Din_A,
bufo_75_Dout_A,
bufo_75_Clk_A,
bufo_75_Rst_A,
bufo_76_Addr_A,
bufo_76_EN_A,
bufo_76_WEN_A,
bufo_76_Din_A,
bufo_76_Dout_A,
bufo_76_Clk_A,
bufo_76_Rst_A,
bufo_77_Addr_A,
bufo_77_EN_A,
bufo_77_WEN_A,
bufo_77_Din_A,
bufo_77_Dout_A,
bufo_77_Clk_A,
bufo_77_Rst_A,
bufo_78_Addr_A,
bufo_78_EN_A,
bufo_78_WEN_A,
bufo_78_Din_A,
bufo_78_Dout_A,
bufo_78_Clk_A,
bufo_78_Rst_A,
bufo_79_Addr_A,
bufo_79_EN_A,
bufo_79_WEN_A,
bufo_79_Din_A,
bufo_79_Dout_A,
bufo_79_Clk_A,
bufo_79_Rst_A,
bufo_80_Addr_A,
bufo_80_EN_A,
bufo_80_WEN_A,
bufo_80_Din_A,
bufo_80_Dout_A,
bufo_80_Clk_A,
bufo_80_Rst_A,
bufo_81_Addr_A,
bufo_81_EN_A,
bufo_81_WEN_A,
bufo_81_Din_A,
bufo_81_Dout_A,
bufo_81_Clk_A,
bufo_81_Rst_A,
bufo_82_Addr_A,
bufo_82_EN_A,
bufo_82_WEN_A,
bufo_82_Din_A,
bufo_82_Dout_A,
bufo_82_Clk_A,
bufo_82_Rst_A,
bufo_83_Addr_A,
bufo_83_EN_A,
bufo_83_WEN_A,
bufo_83_Din_A,
bufo_83_Dout_A,
bufo_83_Clk_A,
bufo_83_Rst_A,
bufo_84_Addr_A,
bufo_84_EN_A,
bufo_84_WEN_A,
bufo_84_Din_A,
bufo_84_Dout_A,
bufo_84_Clk_A,
bufo_84_Rst_A,
bufo_85_Addr_A,
bufo_85_EN_A,
bufo_85_WEN_A,
bufo_85_Din_A,
bufo_85_Dout_A,
bufo_85_Clk_A,
bufo_85_Rst_A,
bufo_86_Addr_A,
bufo_86_EN_A,
bufo_86_WEN_A,
bufo_86_Din_A,
bufo_86_Dout_A,
bufo_86_Clk_A,
bufo_86_Rst_A,
bufo_87_Addr_A,
bufo_87_EN_A,
bufo_87_WEN_A,
bufo_87_Din_A,
bufo_87_Dout_A,
bufo_87_Clk_A,
bufo_87_Rst_A,
bufo_88_Addr_A,
bufo_88_EN_A,
bufo_88_WEN_A,
bufo_88_Din_A,
bufo_88_Dout_A,
bufo_88_Clk_A,
bufo_88_Rst_A,
bufo_89_Addr_A,
bufo_89_EN_A,
bufo_89_WEN_A,
bufo_89_Din_A,
bufo_89_Dout_A,
bufo_89_Clk_A,
bufo_89_Rst_A,
bufo_90_Addr_A,
bufo_90_EN_A,
bufo_90_WEN_A,
bufo_90_Din_A,
bufo_90_Dout_A,
bufo_90_Clk_A,
bufo_90_Rst_A,
bufo_91_Addr_A,
bufo_91_EN_A,
bufo_91_WEN_A,
bufo_91_Din_A,
bufo_91_Dout_A,
bufo_91_Clk_A,
bufo_91_Rst_A,
bufo_92_Addr_A,
bufo_92_EN_A,
bufo_92_WEN_A,
bufo_92_Din_A,
bufo_92_Dout_A,
bufo_92_Clk_A,
bufo_92_Rst_A,
bufo_93_Addr_A,
bufo_93_EN_A,
bufo_93_WEN_A,
bufo_93_Din_A,
bufo_93_Dout_A,
bufo_93_Clk_A,
bufo_93_Rst_A,
bufo_94_Addr_A,
bufo_94_EN_A,
bufo_94_WEN_A,
bufo_94_Din_A,
bufo_94_Dout_A,
bufo_94_Clk_A,
bufo_94_Rst_A,
bufo_95_Addr_A,
bufo_95_EN_A,
bufo_95_WEN_A,
bufo_95_Din_A,
bufo_95_Dout_A,
bufo_95_Clk_A,
bufo_95_Rst_A,
bufo_96_Addr_A,
bufo_96_EN_A,
bufo_96_WEN_A,
bufo_96_Din_A,
bufo_96_Dout_A,
bufo_96_Clk_A,
bufo_96_Rst_A,
bufo_97_Addr_A,
bufo_97_EN_A,
bufo_97_WEN_A,
bufo_97_Din_A,
bufo_97_Dout_A,
bufo_97_Clk_A,
bufo_97_Rst_A,
bufo_98_Addr_A,
bufo_98_EN_A,
bufo_98_WEN_A,
bufo_98_Din_A,
bufo_98_Dout_A,
bufo_98_Clk_A,
bufo_98_Rst_A,
bufo_99_Addr_A,
bufo_99_EN_A,
bufo_99_WEN_A,
bufo_99_Din_A,
bufo_99_Dout_A,
bufo_99_Clk_A,
bufo_99_Rst_A,
bufo_100_Addr_A,
bufo_100_EN_A,
bufo_100_WEN_A,
bufo_100_Din_A,
bufo_100_Dout_A,
bufo_100_Clk_A,
bufo_100_Rst_A,
bufo_101_Addr_A,
bufo_101_EN_A,
bufo_101_WEN_A,
bufo_101_Din_A,
bufo_101_Dout_A,
bufo_101_Clk_A,
bufo_101_Rst_A,
bufo_102_Addr_A,
bufo_102_EN_A,
bufo_102_WEN_A,
bufo_102_Din_A,
bufo_102_Dout_A,
bufo_102_Clk_A,
bufo_102_Rst_A,
bufo_103_Addr_A,
bufo_103_EN_A,
bufo_103_WEN_A,
bufo_103_Din_A,
bufo_103_Dout_A,
bufo_103_Clk_A,
bufo_103_Rst_A,
bufo_104_Addr_A,
bufo_104_EN_A,
bufo_104_WEN_A,
bufo_104_Din_A,
bufo_104_Dout_A,
bufo_104_Clk_A,
bufo_104_Rst_A,
bufo_105_Addr_A,
bufo_105_EN_A,
bufo_105_WEN_A,
bufo_105_Din_A,
bufo_105_Dout_A,
bufo_105_Clk_A,
bufo_105_Rst_A,
bufo_106_Addr_A,
bufo_106_EN_A,
bufo_106_WEN_A,
bufo_106_Din_A,
bufo_106_Dout_A,
bufo_106_Clk_A,
bufo_106_Rst_A,
bufo_107_Addr_A,
bufo_107_EN_A,
bufo_107_WEN_A,
bufo_107_Din_A,
bufo_107_Dout_A,
bufo_107_Clk_A,
bufo_107_Rst_A,
bufo_108_Addr_A,
bufo_108_EN_A,
bufo_108_WEN_A,
bufo_108_Din_A,
bufo_108_Dout_A,
bufo_108_Clk_A,
bufo_108_Rst_A,
bufo_109_Addr_A,
bufo_109_EN_A,
bufo_109_WEN_A,
bufo_109_Din_A,
bufo_109_Dout_A,
bufo_109_Clk_A,
bufo_109_Rst_A,
bufo_110_Addr_A,
bufo_110_EN_A,
bufo_110_WEN_A,
bufo_110_Din_A,
bufo_110_Dout_A,
bufo_110_Clk_A,
bufo_110_Rst_A,
bufo_111_Addr_A,
bufo_111_EN_A,
bufo_111_WEN_A,
bufo_111_Din_A,
bufo_111_Dout_A,
bufo_111_Clk_A,
bufo_111_Rst_A,
bufo_112_Addr_A,
bufo_112_EN_A,
bufo_112_WEN_A,
bufo_112_Din_A,
bufo_112_Dout_A,
bufo_112_Clk_A,
bufo_112_Rst_A,
bufo_113_Addr_A,
bufo_113_EN_A,
bufo_113_WEN_A,
bufo_113_Din_A,
bufo_113_Dout_A,
bufo_113_Clk_A,
bufo_113_Rst_A,
bufo_114_Addr_A,
bufo_114_EN_A,
bufo_114_WEN_A,
bufo_114_Din_A,
bufo_114_Dout_A,
bufo_114_Clk_A,
bufo_114_Rst_A,
bufo_115_Addr_A,
bufo_115_EN_A,
bufo_115_WEN_A,
bufo_115_Din_A,
bufo_115_Dout_A,
bufo_115_Clk_A,
bufo_115_Rst_A,
bufo_116_Addr_A,
bufo_116_EN_A,
bufo_116_WEN_A,
bufo_116_Din_A,
bufo_116_Dout_A,
bufo_116_Clk_A,
bufo_116_Rst_A,
bufo_117_Addr_A,
bufo_117_EN_A,
bufo_117_WEN_A,
bufo_117_Din_A,
bufo_117_Dout_A,
bufo_117_Clk_A,
bufo_117_Rst_A,
bufo_118_Addr_A,
bufo_118_EN_A,
bufo_118_WEN_A,
bufo_118_Din_A,
bufo_118_Dout_A,
bufo_118_Clk_A,
bufo_118_Rst_A,
bufo_119_Addr_A,
bufo_119_EN_A,
bufo_119_WEN_A,
bufo_119_Din_A,
bufo_119_Dout_A,
bufo_119_Clk_A,
bufo_119_Rst_A,
bufo_120_Addr_A,
bufo_120_EN_A,
bufo_120_WEN_A,
bufo_120_Din_A,
bufo_120_Dout_A,
bufo_120_Clk_A,
bufo_120_Rst_A,
bufo_121_Addr_A,
bufo_121_EN_A,
bufo_121_WEN_A,
bufo_121_Din_A,
bufo_121_Dout_A,
bufo_121_Clk_A,
bufo_121_Rst_A,
bufo_122_Addr_A,
bufo_122_EN_A,
bufo_122_WEN_A,
bufo_122_Din_A,
bufo_122_Dout_A,
bufo_122_Clk_A,
bufo_122_Rst_A,
bufo_123_Addr_A,
bufo_123_EN_A,
bufo_123_WEN_A,
bufo_123_Din_A,
bufo_123_Dout_A,
bufo_123_Clk_A,
bufo_123_Rst_A,
bufo_124_Addr_A,
bufo_124_EN_A,
bufo_124_WEN_A,
bufo_124_Din_A,
bufo_124_Dout_A,
bufo_124_Clk_A,
bufo_124_Rst_A,
bufo_125_Addr_A,
bufo_125_EN_A,
bufo_125_WEN_A,
bufo_125_Din_A,
bufo_125_Dout_A,
bufo_125_Clk_A,
bufo_125_Rst_A,
bufo_126_Addr_A,
bufo_126_EN_A,
bufo_126_WEN_A,
bufo_126_Din_A,
bufo_126_Dout_A,
bufo_126_Clk_A,
bufo_126_Rst_A,
bufo_127_Addr_A,
bufo_127_EN_A,
bufo_127_WEN_A,
bufo_127_Din_A,
bufo_127_Dout_A,
bufo_127_Clk_A,
bufo_127_Rst_A,
bufo_128_Addr_A,
bufo_128_EN_A,
bufo_128_WEN_A,
bufo_128_Din_A,
bufo_128_Dout_A,
bufo_128_Clk_A,
bufo_128_Rst_A,
bufo_128_Addr_B,
bufo_128_EN_B,
bufo_128_WEN_B,
bufo_128_Din_B,
bufo_128_Dout_B,
bufo_128_Clk_B,
bufo_128_Rst_B,
bufo_129_Addr_A,
bufo_129_EN_A,
bufo_129_WEN_A,
bufo_129_Din_A,
bufo_129_Dout_A,
bufo_129_Clk_A,
bufo_129_Rst_A,
bufo_129_Addr_B,
bufo_129_EN_B,
bufo_129_WEN_B,
bufo_129_Din_B,
bufo_129_Dout_B,
bufo_129_Clk_B,
bufo_129_Rst_B,
bufo_130_Addr_A,
bufo_130_EN_A,
bufo_130_WEN_A,
bufo_130_Din_A,
bufo_130_Dout_A,
bufo_130_Clk_A,
bufo_130_Rst_A,
bufo_130_Addr_B,
bufo_130_EN_B,
bufo_130_WEN_B,
bufo_130_Din_B,
bufo_130_Dout_B,
bufo_130_Clk_B,
bufo_130_Rst_B,
bufo_131_Addr_A,
bufo_131_EN_A,
bufo_131_WEN_A,
bufo_131_Din_A,
bufo_131_Dout_A,
bufo_131_Clk_A,
bufo_131_Rst_A,
bufo_131_Addr_B,
bufo_131_EN_B,
bufo_131_WEN_B,
bufo_131_Din_B,
bufo_131_Dout_B,
bufo_131_Clk_B,
bufo_131_Rst_B,
bufo_132_Addr_A,
bufo_132_EN_A,
bufo_132_WEN_A,
bufo_132_Din_A,
bufo_132_Dout_A,
bufo_132_Clk_A,
bufo_132_Rst_A,
bufo_132_Addr_B,
bufo_132_EN_B,
bufo_132_WEN_B,
bufo_132_Din_B,
bufo_132_Dout_B,
bufo_132_Clk_B,
bufo_132_Rst_B,
bufo_133_Addr_A,
bufo_133_EN_A,
bufo_133_WEN_A,
bufo_133_Din_A,
bufo_133_Dout_A,
bufo_133_Clk_A,
bufo_133_Rst_A,
bufo_133_Addr_B,
bufo_133_EN_B,
bufo_133_WEN_B,
bufo_133_Din_B,
bufo_133_Dout_B,
bufo_133_Clk_B,
bufo_133_Rst_B,
bufo_134_Addr_A,
bufo_134_EN_A,
bufo_134_WEN_A,
bufo_134_Din_A,
bufo_134_Dout_A,
bufo_134_Clk_A,
bufo_134_Rst_A,
bufo_134_Addr_B,
bufo_134_EN_B,
bufo_134_WEN_B,
bufo_134_Din_B,
bufo_134_Dout_B,
bufo_134_Clk_B,
bufo_134_Rst_B,
bufo_135_Addr_A,
bufo_135_EN_A,
bufo_135_WEN_A,
bufo_135_Din_A,
bufo_135_Dout_A,
bufo_135_Clk_A,
bufo_135_Rst_A,
bufo_135_Addr_B,
bufo_135_EN_B,
bufo_135_WEN_B,
bufo_135_Din_B,
bufo_135_Dout_B,
bufo_135_Clk_B,
bufo_135_Rst_B,
bufo_136_Addr_A,
bufo_136_EN_A,
bufo_136_WEN_A,
bufo_136_Din_A,
bufo_136_Dout_A,
bufo_136_Clk_A,
bufo_136_Rst_A,
bufo_136_Addr_B,
bufo_136_EN_B,
bufo_136_WEN_B,
bufo_136_Din_B,
bufo_136_Dout_B,
bufo_136_Clk_B,
bufo_136_Rst_B,
bufo_137_Addr_A,
bufo_137_EN_A,
bufo_137_WEN_A,
bufo_137_Din_A,
bufo_137_Dout_A,
bufo_137_Clk_A,
bufo_137_Rst_A,
bufo_137_Addr_B,
bufo_137_EN_B,
bufo_137_WEN_B,
bufo_137_Din_B,
bufo_137_Dout_B,
bufo_137_Clk_B,
bufo_137_Rst_B,
bufo_138_Addr_A,
bufo_138_EN_A,
bufo_138_WEN_A,
bufo_138_Din_A,
bufo_138_Dout_A,
bufo_138_Clk_A,
bufo_138_Rst_A,
bufo_138_Addr_B,
bufo_138_EN_B,
bufo_138_WEN_B,
bufo_138_Din_B,
bufo_138_Dout_B,
bufo_138_Clk_B,
bufo_138_Rst_B,
bufo_139_Addr_A,
bufo_139_EN_A,
bufo_139_WEN_A,
bufo_139_Din_A,
bufo_139_Dout_A,
bufo_139_Clk_A,
bufo_139_Rst_A,
bufo_139_Addr_B,
bufo_139_EN_B,
bufo_139_WEN_B,
bufo_139_Din_B,
bufo_139_Dout_B,
bufo_139_Clk_B,
bufo_139_Rst_B,
bufo_140_Addr_A,
bufo_140_EN_A,
bufo_140_WEN_A,
bufo_140_Din_A,
bufo_140_Dout_A,
bufo_140_Clk_A,
bufo_140_Rst_A,
bufo_140_Addr_B,
bufo_140_EN_B,
bufo_140_WEN_B,
bufo_140_Din_B,
bufo_140_Dout_B,
bufo_140_Clk_B,
bufo_140_Rst_B,
bufo_141_Addr_A,
bufo_141_EN_A,
bufo_141_WEN_A,
bufo_141_Din_A,
bufo_141_Dout_A,
bufo_141_Clk_A,
bufo_141_Rst_A,
bufo_141_Addr_B,
bufo_141_EN_B,
bufo_141_WEN_B,
bufo_141_Din_B,
bufo_141_Dout_B,
bufo_141_Clk_B,
bufo_141_Rst_B,
bufo_142_Addr_A,
bufo_142_EN_A,
bufo_142_WEN_A,
bufo_142_Din_A,
bufo_142_Dout_A,
bufo_142_Clk_A,
bufo_142_Rst_A,
bufo_142_Addr_B,
bufo_142_EN_B,
bufo_142_WEN_B,
bufo_142_Din_B,
bufo_142_Dout_B,
bufo_142_Clk_B,
bufo_142_Rst_B,
bufo_143_Addr_A,
bufo_143_EN_A,
bufo_143_WEN_A,
bufo_143_Din_A,
bufo_143_Dout_A,
bufo_143_Clk_A,
bufo_143_Rst_A,
bufo_143_Addr_B,
bufo_143_EN_B,
bufo_143_WEN_B,
bufo_143_Din_B,
bufo_143_Dout_B,
bufo_143_Clk_B,
bufo_143_Rst_B,
bufo_144_Addr_A,
bufo_144_EN_A,
bufo_144_WEN_A,
bufo_144_Din_A,
bufo_144_Dout_A,
bufo_144_Clk_A,
bufo_144_Rst_A,
bufo_144_Addr_B,
bufo_144_EN_B,
bufo_144_WEN_B,
bufo_144_Din_B,
bufo_144_Dout_B,
bufo_144_Clk_B,
bufo_144_Rst_B,
bufo_145_Addr_A,
bufo_145_EN_A,
bufo_145_WEN_A,
bufo_145_Din_A,
bufo_145_Dout_A,
bufo_145_Clk_A,
bufo_145_Rst_A,
bufo_145_Addr_B,
bufo_145_EN_B,
bufo_145_WEN_B,
bufo_145_Din_B,
bufo_145_Dout_B,
bufo_145_Clk_B,
bufo_145_Rst_B,
bufo_146_Addr_A,
bufo_146_EN_A,
bufo_146_WEN_A,
bufo_146_Din_A,
bufo_146_Dout_A,
bufo_146_Clk_A,
bufo_146_Rst_A,
bufo_146_Addr_B,
bufo_146_EN_B,
bufo_146_WEN_B,
bufo_146_Din_B,
bufo_146_Dout_B,
bufo_146_Clk_B,
bufo_146_Rst_B,
bufo_147_Addr_A,
bufo_147_EN_A,
bufo_147_WEN_A,
bufo_147_Din_A,
bufo_147_Dout_A,
bufo_147_Clk_A,
bufo_147_Rst_A,
bufo_147_Addr_B,
bufo_147_EN_B,
bufo_147_WEN_B,
bufo_147_Din_B,
bufo_147_Dout_B,
bufo_147_Clk_B,
bufo_147_Rst_B,
bufo_148_Addr_A,
bufo_148_EN_A,
bufo_148_WEN_A,
bufo_148_Din_A,
bufo_148_Dout_A,
bufo_148_Clk_A,
bufo_148_Rst_A,
bufo_148_Addr_B,
bufo_148_EN_B,
bufo_148_WEN_B,
bufo_148_Din_B,
bufo_148_Dout_B,
bufo_148_Clk_B,
bufo_148_Rst_B,
bufo_149_Addr_A,
bufo_149_EN_A,
bufo_149_WEN_A,
bufo_149_Din_A,
bufo_149_Dout_A,
bufo_149_Clk_A,
bufo_149_Rst_A,
bufo_149_Addr_B,
bufo_149_EN_B,
bufo_149_WEN_B,
bufo_149_Din_B,
bufo_149_Dout_B,
bufo_149_Clk_B,
bufo_149_Rst_B,
bufo_150_Addr_A,
bufo_150_EN_A,
bufo_150_WEN_A,
bufo_150_Din_A,
bufo_150_Dout_A,
bufo_150_Clk_A,
bufo_150_Rst_A,
bufo_150_Addr_B,
bufo_150_EN_B,
bufo_150_WEN_B,
bufo_150_Din_B,
bufo_150_Dout_B,
bufo_150_Clk_B,
bufo_150_Rst_B,
bufo_151_Addr_A,
bufo_151_EN_A,
bufo_151_WEN_A,
bufo_151_Din_A,
bufo_151_Dout_A,
bufo_151_Clk_A,
bufo_151_Rst_A,
bufo_151_Addr_B,
bufo_151_EN_B,
bufo_151_WEN_B,
bufo_151_Din_B,
bufo_151_Dout_B,
bufo_151_Clk_B,
bufo_151_Rst_B,
bufo_152_Addr_A,
bufo_152_EN_A,
bufo_152_WEN_A,
bufo_152_Din_A,
bufo_152_Dout_A,
bufo_152_Clk_A,
bufo_152_Rst_A,
bufo_152_Addr_B,
bufo_152_EN_B,
bufo_152_WEN_B,
bufo_152_Din_B,
bufo_152_Dout_B,
bufo_152_Clk_B,
bufo_152_Rst_B,
bufo_153_Addr_A,
bufo_153_EN_A,
bufo_153_WEN_A,
bufo_153_Din_A,
bufo_153_Dout_A,
bufo_153_Clk_A,
bufo_153_Rst_A,
bufo_153_Addr_B,
bufo_153_EN_B,
bufo_153_WEN_B,
bufo_153_Din_B,
bufo_153_Dout_B,
bufo_153_Clk_B,
bufo_153_Rst_B,
bufo_154_Addr_A,
bufo_154_EN_A,
bufo_154_WEN_A,
bufo_154_Din_A,
bufo_154_Dout_A,
bufo_154_Clk_A,
bufo_154_Rst_A,
bufo_154_Addr_B,
bufo_154_EN_B,
bufo_154_WEN_B,
bufo_154_Din_B,
bufo_154_Dout_B,
bufo_154_Clk_B,
bufo_154_Rst_B,
bufo_155_Addr_A,
bufo_155_EN_A,
bufo_155_WEN_A,
bufo_155_Din_A,
bufo_155_Dout_A,
bufo_155_Clk_A,
bufo_155_Rst_A,
bufo_155_Addr_B,
bufo_155_EN_B,
bufo_155_WEN_B,
bufo_155_Din_B,
bufo_155_Dout_B,
bufo_155_Clk_B,
bufo_155_Rst_B,
bufo_156_Addr_A,
bufo_156_EN_A,
bufo_156_WEN_A,
bufo_156_Din_A,
bufo_156_Dout_A,
bufo_156_Clk_A,
bufo_156_Rst_A,
bufo_156_Addr_B,
bufo_156_EN_B,
bufo_156_WEN_B,
bufo_156_Din_B,
bufo_156_Dout_B,
bufo_156_Clk_B,
bufo_156_Rst_B,
bufo_157_Addr_A,
bufo_157_EN_A,
bufo_157_WEN_A,
bufo_157_Din_A,
bufo_157_Dout_A,
bufo_157_Clk_A,
bufo_157_Rst_A,
bufo_157_Addr_B,
bufo_157_EN_B,
bufo_157_WEN_B,
bufo_157_Din_B,
bufo_157_Dout_B,
bufo_157_Clk_B,
bufo_157_Rst_B,
bufo_158_Addr_A,
bufo_158_EN_A,
bufo_158_WEN_A,
bufo_158_Din_A,
bufo_158_Dout_A,
bufo_158_Clk_A,
bufo_158_Rst_A,
bufo_158_Addr_B,
bufo_158_EN_B,
bufo_158_WEN_B,
bufo_158_Din_B,
bufo_158_Dout_B,
bufo_158_Clk_B,
bufo_158_Rst_B,
bufo_159_Addr_A,
bufo_159_EN_A,
bufo_159_WEN_A,
bufo_159_Din_A,
bufo_159_Dout_A,
bufo_159_Clk_A,
bufo_159_Rst_A,
bufo_159_Addr_B,
bufo_159_EN_B,
bufo_159_WEN_B,
bufo_159_Din_B,
bufo_159_Dout_B,
bufo_159_Clk_B,
bufo_159_Rst_B,
bufo_160_Addr_A,
bufo_160_EN_A,
bufo_160_WEN_A,
bufo_160_Din_A,
bufo_160_Dout_A,
bufo_160_Clk_A,
bufo_160_Rst_A,
bufo_160_Addr_B,
bufo_160_EN_B,
bufo_160_WEN_B,
bufo_160_Din_B,
bufo_160_Dout_B,
bufo_160_Clk_B,
bufo_160_Rst_B,
bufo_161_Addr_A,
bufo_161_EN_A,
bufo_161_WEN_A,
bufo_161_Din_A,
bufo_161_Dout_A,
bufo_161_Clk_A,
bufo_161_Rst_A,
bufo_161_Addr_B,
bufo_161_EN_B,
bufo_161_WEN_B,
bufo_161_Din_B,
bufo_161_Dout_B,
bufo_161_Clk_B,
bufo_161_Rst_B,
bufo_162_Addr_A,
bufo_162_EN_A,
bufo_162_WEN_A,
bufo_162_Din_A,
bufo_162_Dout_A,
bufo_162_Clk_A,
bufo_162_Rst_A,
bufo_162_Addr_B,
bufo_162_EN_B,
bufo_162_WEN_B,
bufo_162_Din_B,
bufo_162_Dout_B,
bufo_162_Clk_B,
bufo_162_Rst_B,
bufo_163_Addr_A,
bufo_163_EN_A,
bufo_163_WEN_A,
bufo_163_Din_A,
bufo_163_Dout_A,
bufo_163_Clk_A,
bufo_163_Rst_A,
bufo_163_Addr_B,
bufo_163_EN_B,
bufo_163_WEN_B,
bufo_163_Din_B,
bufo_163_Dout_B,
bufo_163_Clk_B,
bufo_163_Rst_B,
bufo_164_Addr_A,
bufo_164_EN_A,
bufo_164_WEN_A,
bufo_164_Din_A,
bufo_164_Dout_A,
bufo_164_Clk_A,
bufo_164_Rst_A,
bufo_164_Addr_B,
bufo_164_EN_B,
bufo_164_WEN_B,
bufo_164_Din_B,
bufo_164_Dout_B,
bufo_164_Clk_B,
bufo_164_Rst_B,
bufo_165_Addr_A,
bufo_165_EN_A,
bufo_165_WEN_A,
bufo_165_Din_A,
bufo_165_Dout_A,
bufo_165_Clk_A,
bufo_165_Rst_A,
bufo_165_Addr_B,
bufo_165_EN_B,
bufo_165_WEN_B,
bufo_165_Din_B,
bufo_165_Dout_B,
bufo_165_Clk_B,
bufo_165_Rst_B,
bufo_166_Addr_A,
bufo_166_EN_A,
bufo_166_WEN_A,
bufo_166_Din_A,
bufo_166_Dout_A,
bufo_166_Clk_A,
bufo_166_Rst_A,
bufo_166_Addr_B,
bufo_166_EN_B,
bufo_166_WEN_B,
bufo_166_Din_B,
bufo_166_Dout_B,
bufo_166_Clk_B,
bufo_166_Rst_B,
bufo_167_Addr_A,
bufo_167_EN_A,
bufo_167_WEN_A,
bufo_167_Din_A,
bufo_167_Dout_A,
bufo_167_Clk_A,
bufo_167_Rst_A,
bufo_167_Addr_B,
bufo_167_EN_B,
bufo_167_WEN_B,
bufo_167_Din_B,
bufo_167_Dout_B,
bufo_167_Clk_B,
bufo_167_Rst_B,
bufo_168_Addr_A,
bufo_168_EN_A,
bufo_168_WEN_A,
bufo_168_Din_A,
bufo_168_Dout_A,
bufo_168_Clk_A,
bufo_168_Rst_A,
bufo_168_Addr_B,
bufo_168_EN_B,
bufo_168_WEN_B,
bufo_168_Din_B,
bufo_168_Dout_B,
bufo_168_Clk_B,
bufo_168_Rst_B,
bufo_169_Addr_A,
bufo_169_EN_A,
bufo_169_WEN_A,
bufo_169_Din_A,
bufo_169_Dout_A,
bufo_169_Clk_A,
bufo_169_Rst_A,
bufo_169_Addr_B,
bufo_169_EN_B,
bufo_169_WEN_B,
bufo_169_Din_B,
bufo_169_Dout_B,
bufo_169_Clk_B,
bufo_169_Rst_B,
bufo_170_Addr_A,
bufo_170_EN_A,
bufo_170_WEN_A,
bufo_170_Din_A,
bufo_170_Dout_A,
bufo_170_Clk_A,
bufo_170_Rst_A,
bufo_170_Addr_B,
bufo_170_EN_B,
bufo_170_WEN_B,
bufo_170_Din_B,
bufo_170_Dout_B,
bufo_170_Clk_B,
bufo_170_Rst_B,
bufo_171_Addr_A,
bufo_171_EN_A,
bufo_171_WEN_A,
bufo_171_Din_A,
bufo_171_Dout_A,
bufo_171_Clk_A,
bufo_171_Rst_A,
bufo_171_Addr_B,
bufo_171_EN_B,
bufo_171_WEN_B,
bufo_171_Din_B,
bufo_171_Dout_B,
bufo_171_Clk_B,
bufo_171_Rst_B,
bufo_172_Addr_A,
bufo_172_EN_A,
bufo_172_WEN_A,
bufo_172_Din_A,
bufo_172_Dout_A,
bufo_172_Clk_A,
bufo_172_Rst_A,
bufo_172_Addr_B,
bufo_172_EN_B,
bufo_172_WEN_B,
bufo_172_Din_B,
bufo_172_Dout_B,
bufo_172_Clk_B,
bufo_172_Rst_B,
bufo_173_Addr_A,
bufo_173_EN_A,
bufo_173_WEN_A,
bufo_173_Din_A,
bufo_173_Dout_A,
bufo_173_Clk_A,
bufo_173_Rst_A,
bufo_173_Addr_B,
bufo_173_EN_B,
bufo_173_WEN_B,
bufo_173_Din_B,
bufo_173_Dout_B,
bufo_173_Clk_B,
bufo_173_Rst_B,
bufo_174_Addr_A,
bufo_174_EN_A,
bufo_174_WEN_A,
bufo_174_Din_A,
bufo_174_Dout_A,
bufo_174_Clk_A,
bufo_174_Rst_A,
bufo_174_Addr_B,
bufo_174_EN_B,
bufo_174_WEN_B,
bufo_174_Din_B,
bufo_174_Dout_B,
bufo_174_Clk_B,
bufo_174_Rst_B,
bufo_175_Addr_A,
bufo_175_EN_A,
bufo_175_WEN_A,
bufo_175_Din_A,
bufo_175_Dout_A,
bufo_175_Clk_A,
bufo_175_Rst_A,
bufo_175_Addr_B,
bufo_175_EN_B,
bufo_175_WEN_B,
bufo_175_Din_B,
bufo_175_Dout_B,
bufo_175_Clk_B,
bufo_175_Rst_B,
bufo_176_Addr_A,
bufo_176_EN_A,
bufo_176_WEN_A,
bufo_176_Din_A,
bufo_176_Dout_A,
bufo_176_Clk_A,
bufo_176_Rst_A,
bufo_176_Addr_B,
bufo_176_EN_B,
bufo_176_WEN_B,
bufo_176_Din_B,
bufo_176_Dout_B,
bufo_176_Clk_B,
bufo_176_Rst_B,
bufo_177_Addr_A,
bufo_177_EN_A,
bufo_177_WEN_A,
bufo_177_Din_A,
bufo_177_Dout_A,
bufo_177_Clk_A,
bufo_177_Rst_A,
bufo_177_Addr_B,
bufo_177_EN_B,
bufo_177_WEN_B,
bufo_177_Din_B,
bufo_177_Dout_B,
bufo_177_Clk_B,
bufo_177_Rst_B,
bufo_178_Addr_A,
bufo_178_EN_A,
bufo_178_WEN_A,
bufo_178_Din_A,
bufo_178_Dout_A,
bufo_178_Clk_A,
bufo_178_Rst_A,
bufo_178_Addr_B,
bufo_178_EN_B,
bufo_178_WEN_B,
bufo_178_Din_B,
bufo_178_Dout_B,
bufo_178_Clk_B,
bufo_178_Rst_B,
bufo_179_Addr_A,
bufo_179_EN_A,
bufo_179_WEN_A,
bufo_179_Din_A,
bufo_179_Dout_A,
bufo_179_Clk_A,
bufo_179_Rst_A,
bufo_179_Addr_B,
bufo_179_EN_B,
bufo_179_WEN_B,
bufo_179_Din_B,
bufo_179_Dout_B,
bufo_179_Clk_B,
bufo_179_Rst_B,
bufo_180_Addr_A,
bufo_180_EN_A,
bufo_180_WEN_A,
bufo_180_Din_A,
bufo_180_Dout_A,
bufo_180_Clk_A,
bufo_180_Rst_A,
bufo_180_Addr_B,
bufo_180_EN_B,
bufo_180_WEN_B,
bufo_180_Din_B,
bufo_180_Dout_B,
bufo_180_Clk_B,
bufo_180_Rst_B,
bufo_181_Addr_A,
bufo_181_EN_A,
bufo_181_WEN_A,
bufo_181_Din_A,
bufo_181_Dout_A,
bufo_181_Clk_A,
bufo_181_Rst_A,
bufo_181_Addr_B,
bufo_181_EN_B,
bufo_181_WEN_B,
bufo_181_Din_B,
bufo_181_Dout_B,
bufo_181_Clk_B,
bufo_181_Rst_B,
bufo_182_Addr_A,
bufo_182_EN_A,
bufo_182_WEN_A,
bufo_182_Din_A,
bufo_182_Dout_A,
bufo_182_Clk_A,
bufo_182_Rst_A,
bufo_182_Addr_B,
bufo_182_EN_B,
bufo_182_WEN_B,
bufo_182_Din_B,
bufo_182_Dout_B,
bufo_182_Clk_B,
bufo_182_Rst_B,
bufo_183_Addr_A,
bufo_183_EN_A,
bufo_183_WEN_A,
bufo_183_Din_A,
bufo_183_Dout_A,
bufo_183_Clk_A,
bufo_183_Rst_A,
bufo_183_Addr_B,
bufo_183_EN_B,
bufo_183_WEN_B,
bufo_183_Din_B,
bufo_183_Dout_B,
bufo_183_Clk_B,
bufo_183_Rst_B,
bufo_184_Addr_A,
bufo_184_EN_A,
bufo_184_WEN_A,
bufo_184_Din_A,
bufo_184_Dout_A,
bufo_184_Clk_A,
bufo_184_Rst_A,
bufo_184_Addr_B,
bufo_184_EN_B,
bufo_184_WEN_B,
bufo_184_Din_B,
bufo_184_Dout_B,
bufo_184_Clk_B,
bufo_184_Rst_B,
bufo_185_Addr_A,
bufo_185_EN_A,
bufo_185_WEN_A,
bufo_185_Din_A,
bufo_185_Dout_A,
bufo_185_Clk_A,
bufo_185_Rst_A,
bufo_185_Addr_B,
bufo_185_EN_B,
bufo_185_WEN_B,
bufo_185_Din_B,
bufo_185_Dout_B,
bufo_185_Clk_B,
bufo_185_Rst_B,
bufo_186_Addr_A,
bufo_186_EN_A,
bufo_186_WEN_A,
bufo_186_Din_A,
bufo_186_Dout_A,
bufo_186_Clk_A,
bufo_186_Rst_A,
bufo_186_Addr_B,
bufo_186_EN_B,
bufo_186_WEN_B,
bufo_186_Din_B,
bufo_186_Dout_B,
bufo_186_Clk_B,
bufo_186_Rst_B,
bufo_187_Addr_A,
bufo_187_EN_A,
bufo_187_WEN_A,
bufo_187_Din_A,
bufo_187_Dout_A,
bufo_187_Clk_A,
bufo_187_Rst_A,
bufo_187_Addr_B,
bufo_187_EN_B,
bufo_187_WEN_B,
bufo_187_Din_B,
bufo_187_Dout_B,
bufo_187_Clk_B,
bufo_187_Rst_B,
bufo_188_Addr_A,
bufo_188_EN_A,
bufo_188_WEN_A,
bufo_188_Din_A,
bufo_188_Dout_A,
bufo_188_Clk_A,
bufo_188_Rst_A,
bufo_188_Addr_B,
bufo_188_EN_B,
bufo_188_WEN_B,
bufo_188_Din_B,
bufo_188_Dout_B,
bufo_188_Clk_B,
bufo_188_Rst_B,
bufo_189_Addr_A,
bufo_189_EN_A,
bufo_189_WEN_A,
bufo_189_Din_A,
bufo_189_Dout_A,
bufo_189_Clk_A,
bufo_189_Rst_A,
bufo_189_Addr_B,
bufo_189_EN_B,
bufo_189_WEN_B,
bufo_189_Din_B,
bufo_189_Dout_B,
bufo_189_Clk_B,
bufo_189_Rst_B,
bufo_190_Addr_A,
bufo_190_EN_A,
bufo_190_WEN_A,
bufo_190_Din_A,
bufo_190_Dout_A,
bufo_190_Clk_A,
bufo_190_Rst_A,
bufo_190_Addr_B,
bufo_190_EN_B,
bufo_190_WEN_B,
bufo_190_Din_B,
bufo_190_Dout_B,
bufo_190_Clk_B,
bufo_190_Rst_B,
bufo_191_Addr_A,
bufo_191_EN_A,
bufo_191_WEN_A,
bufo_191_Din_A,
bufo_191_Dout_A,
bufo_191_Clk_A,
bufo_191_Rst_A,
bufo_191_Addr_B,
bufo_191_EN_B,
bufo_191_WEN_B,
bufo_191_Din_B,
bufo_191_Dout_B,
bufo_191_Clk_B,
bufo_191_Rst_B,
bufo_192_Addr_A,
bufo_192_EN_A,
bufo_192_WEN_A,
bufo_192_Din_A,
bufo_192_Dout_A,
bufo_192_Clk_A,
bufo_192_Rst_A,
bufo_192_Addr_B,
bufo_192_EN_B,
bufo_192_WEN_B,
bufo_192_Din_B,
bufo_192_Dout_B,
bufo_192_Clk_B,
bufo_192_Rst_B,
bufo_193_Addr_A,
bufo_193_EN_A,
bufo_193_WEN_A,
bufo_193_Din_A,
bufo_193_Dout_A,
bufo_193_Clk_A,
bufo_193_Rst_A,
bufo_193_Addr_B,
bufo_193_EN_B,
bufo_193_WEN_B,
bufo_193_Din_B,
bufo_193_Dout_B,
bufo_193_Clk_B,
bufo_193_Rst_B,
bufo_194_Addr_A,
bufo_194_EN_A,
bufo_194_WEN_A,
bufo_194_Din_A,
bufo_194_Dout_A,
bufo_194_Clk_A,
bufo_194_Rst_A,
bufo_194_Addr_B,
bufo_194_EN_B,
bufo_194_WEN_B,
bufo_194_Din_B,
bufo_194_Dout_B,
bufo_194_Clk_B,
bufo_194_Rst_B,
bufo_195_Addr_A,
bufo_195_EN_A,
bufo_195_WEN_A,
bufo_195_Din_A,
bufo_195_Dout_A,
bufo_195_Clk_A,
bufo_195_Rst_A,
bufo_195_Addr_B,
bufo_195_EN_B,
bufo_195_WEN_B,
bufo_195_Din_B,
bufo_195_Dout_B,
bufo_195_Clk_B,
bufo_195_Rst_B,
bufo_196_Addr_A,
bufo_196_EN_A,
bufo_196_WEN_A,
bufo_196_Din_A,
bufo_196_Dout_A,
bufo_196_Clk_A,
bufo_196_Rst_A,
bufo_196_Addr_B,
bufo_196_EN_B,
bufo_196_WEN_B,
bufo_196_Din_B,
bufo_196_Dout_B,
bufo_196_Clk_B,
bufo_196_Rst_B,
bufo_197_Addr_A,
bufo_197_EN_A,
bufo_197_WEN_A,
bufo_197_Din_A,
bufo_197_Dout_A,
bufo_197_Clk_A,
bufo_197_Rst_A,
bufo_197_Addr_B,
bufo_197_EN_B,
bufo_197_WEN_B,
bufo_197_Din_B,
bufo_197_Dout_B,
bufo_197_Clk_B,
bufo_197_Rst_B,
bufo_198_Addr_A,
bufo_198_EN_A,
bufo_198_WEN_A,
bufo_198_Din_A,
bufo_198_Dout_A,
bufo_198_Clk_A,
bufo_198_Rst_A,
bufo_198_Addr_B,
bufo_198_EN_B,
bufo_198_WEN_B,
bufo_198_Din_B,
bufo_198_Dout_B,
bufo_198_Clk_B,
bufo_198_Rst_B,
bufo_199_Addr_A,
bufo_199_EN_A,
bufo_199_WEN_A,
bufo_199_Din_A,
bufo_199_Dout_A,
bufo_199_Clk_A,
bufo_199_Rst_A,
bufo_199_Addr_B,
bufo_199_EN_B,
bufo_199_WEN_B,
bufo_199_Din_B,
bufo_199_Dout_B,
bufo_199_Clk_B,
bufo_199_Rst_B
);
parameter ap_ST_fsm_state1 = 56'd1;
parameter ap_ST_fsm_state2 = 56'd2;
parameter ap_ST_fsm_state3 = 56'd4;
parameter ap_ST_fsm_state4 = 56'd8;
parameter ap_ST_fsm_state5 = 56'd16;
parameter ap_ST_fsm_state6 = 56'd32;
parameter ap_ST_fsm_state7 = 56'd64;
parameter ap_ST_fsm_state8 = 56'd128;
parameter ap_ST_fsm_state9 = 56'd256;
parameter ap_ST_fsm_state10 = 56'd512;
parameter ap_ST_fsm_state11 = 56'd1024;
parameter ap_ST_fsm_state12 = 56'd2048;
parameter ap_ST_fsm_state13 = 56'd4096;
parameter ap_ST_fsm_state14 = 56'd8192;
parameter ap_ST_fsm_state15 = 56'd16384;
parameter ap_ST_fsm_state16 = 56'd32768;
parameter ap_ST_fsm_state17 = 56'd65536;
parameter ap_ST_fsm_state18 = 56'd131072;
parameter ap_ST_fsm_state19 = 56'd262144;
parameter ap_ST_fsm_state20 = 56'd524288;
parameter ap_ST_fsm_state21 = 56'd1048576;
parameter ap_ST_fsm_state22 = 56'd2097152;
parameter ap_ST_fsm_state23 = 56'd4194304;
parameter ap_ST_fsm_state24 = 56'd8388608;
parameter ap_ST_fsm_state25 = 56'd16777216;
parameter ap_ST_fsm_state26 = 56'd33554432;
parameter ap_ST_fsm_state27 = 56'd67108864;
parameter ap_ST_fsm_state28 = 56'd134217728;
parameter ap_ST_fsm_state29 = 56'd268435456;
parameter ap_ST_fsm_state30 = 56'd536870912;
parameter ap_ST_fsm_state31 = 56'd1073741824;
parameter ap_ST_fsm_state32 = 56'd2147483648;
parameter ap_ST_fsm_state33 = 56'd4294967296;
parameter ap_ST_fsm_state34 = 56'd8589934592;
parameter ap_ST_fsm_state35 = 56'd17179869184;
parameter ap_ST_fsm_state36 = 56'd34359738368;
parameter ap_ST_fsm_state37 = 56'd68719476736;
parameter ap_ST_fsm_state38 = 56'd137438953472;
parameter ap_ST_fsm_state39 = 56'd274877906944;
parameter ap_ST_fsm_state40 = 56'd549755813888;
parameter ap_ST_fsm_state41 = 56'd1099511627776;
parameter ap_ST_fsm_state42 = 56'd2199023255552;
parameter ap_ST_fsm_state43 = 56'd4398046511104;
parameter ap_ST_fsm_state44 = 56'd8796093022208;
parameter ap_ST_fsm_state45 = 56'd17592186044416;
parameter ap_ST_fsm_state46 = 56'd35184372088832;
parameter ap_ST_fsm_state47 = 56'd70368744177664;
parameter ap_ST_fsm_state48 = 56'd140737488355328;
parameter ap_ST_fsm_state49 = 56'd281474976710656;
parameter ap_ST_fsm_state50 = 56'd562949953421312;
parameter ap_ST_fsm_state51 = 56'd1125899906842624;
parameter ap_ST_fsm_state52 = 56'd2251799813685248;
parameter ap_ST_fsm_state53 = 56'd4503599627370496;
parameter ap_ST_fsm_state54 = 56'd9007199254740992;
parameter ap_ST_fsm_state55 = 56'd18014398509481984;
parameter ap_ST_fsm_state56 = 56'd36028797018963968;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] bufw_Addr_A;
output bufw_EN_A;
output [15:0] bufw_WEN_A;
output [127:0] bufw_Din_A;
input [127:0] bufw_Dout_A;
output bufw_Clk_A;
output bufw_Rst_A;
output [31:0] bufi_Addr_A;
output bufi_EN_A;
output [15:0] bufi_WEN_A;
output [127:0] bufi_Din_A;
input [127:0] bufi_Dout_A;
output bufi_Clk_A;
output bufi_Rst_A;
output [31:0] bufo_0_Addr_A;
output bufo_0_EN_A;
output [3:0] bufo_0_WEN_A;
output [31:0] bufo_0_Din_A;
input [31:0] bufo_0_Dout_A;
output bufo_0_Clk_A;
output bufo_0_Rst_A;
output [31:0] bufo_1_Addr_A;
output bufo_1_EN_A;
output [3:0] bufo_1_WEN_A;
output [31:0] bufo_1_Din_A;
input [31:0] bufo_1_Dout_A;
output bufo_1_Clk_A;
output bufo_1_Rst_A;
output [31:0] bufo_2_Addr_A;
output bufo_2_EN_A;
output [3:0] bufo_2_WEN_A;
output [31:0] bufo_2_Din_A;
input [31:0] bufo_2_Dout_A;
output bufo_2_Clk_A;
output bufo_2_Rst_A;
output [31:0] bufo_3_Addr_A;
output bufo_3_EN_A;
output [3:0] bufo_3_WEN_A;
output [31:0] bufo_3_Din_A;
input [31:0] bufo_3_Dout_A;
output bufo_3_Clk_A;
output bufo_3_Rst_A;
output [31:0] bufo_4_Addr_A;
output bufo_4_EN_A;
output [3:0] bufo_4_WEN_A;
output [31:0] bufo_4_Din_A;
input [31:0] bufo_4_Dout_A;
output bufo_4_Clk_A;
output bufo_4_Rst_A;
output [31:0] bufo_5_Addr_A;
output bufo_5_EN_A;
output [3:0] bufo_5_WEN_A;
output [31:0] bufo_5_Din_A;
input [31:0] bufo_5_Dout_A;
output bufo_5_Clk_A;
output bufo_5_Rst_A;
output [31:0] bufo_6_Addr_A;
output bufo_6_EN_A;
output [3:0] bufo_6_WEN_A;
output [31:0] bufo_6_Din_A;
input [31:0] bufo_6_Dout_A;
output bufo_6_Clk_A;
output bufo_6_Rst_A;
output [31:0] bufo_7_Addr_A;
output bufo_7_EN_A;
output [3:0] bufo_7_WEN_A;
output [31:0] bufo_7_Din_A;
input [31:0] bufo_7_Dout_A;
output bufo_7_Clk_A;
output bufo_7_Rst_A;
output [31:0] bufo_8_Addr_A;
output bufo_8_EN_A;
output [3:0] bufo_8_WEN_A;
output [31:0] bufo_8_Din_A;
input [31:0] bufo_8_Dout_A;
output bufo_8_Clk_A;
output bufo_8_Rst_A;
output [31:0] bufo_9_Addr_A;
output bufo_9_EN_A;
output [3:0] bufo_9_WEN_A;
output [31:0] bufo_9_Din_A;
input [31:0] bufo_9_Dout_A;
output bufo_9_Clk_A;
output bufo_9_Rst_A;
output [31:0] bufo_10_Addr_A;
output bufo_10_EN_A;
output [3:0] bufo_10_WEN_A;
output [31:0] bufo_10_Din_A;
input [31:0] bufo_10_Dout_A;
output bufo_10_Clk_A;
output bufo_10_Rst_A;
output [31:0] bufo_11_Addr_A;
output bufo_11_EN_A;
output [3:0] bufo_11_WEN_A;
output [31:0] bufo_11_Din_A;
input [31:0] bufo_11_Dout_A;
output bufo_11_Clk_A;
output bufo_11_Rst_A;
output [31:0] bufo_12_Addr_A;
output bufo_12_EN_A;
output [3:0] bufo_12_WEN_A;
output [31:0] bufo_12_Din_A;
input [31:0] bufo_12_Dout_A;
output bufo_12_Clk_A;
output bufo_12_Rst_A;
output [31:0] bufo_13_Addr_A;
output bufo_13_EN_A;
output [3:0] bufo_13_WEN_A;
output [31:0] bufo_13_Din_A;
input [31:0] bufo_13_Dout_A;
output bufo_13_Clk_A;
output bufo_13_Rst_A;
output [31:0] bufo_14_Addr_A;
output bufo_14_EN_A;
output [3:0] bufo_14_WEN_A;
output [31:0] bufo_14_Din_A;
input [31:0] bufo_14_Dout_A;
output bufo_14_Clk_A;
output bufo_14_Rst_A;
output [31:0] bufo_15_Addr_A;
output bufo_15_EN_A;
output [3:0] bufo_15_WEN_A;
output [31:0] bufo_15_Din_A;
input [31:0] bufo_15_Dout_A;
output bufo_15_Clk_A;
output bufo_15_Rst_A;
output [31:0] bufo_16_Addr_A;
output bufo_16_EN_A;
output [3:0] bufo_16_WEN_A;
output [31:0] bufo_16_Din_A;
input [31:0] bufo_16_Dout_A;
output bufo_16_Clk_A;
output bufo_16_Rst_A;
output [31:0] bufo_17_Addr_A;
output bufo_17_EN_A;
output [3:0] bufo_17_WEN_A;
output [31:0] bufo_17_Din_A;
input [31:0] bufo_17_Dout_A;
output bufo_17_Clk_A;
output bufo_17_Rst_A;
output [31:0] bufo_18_Addr_A;
output bufo_18_EN_A;
output [3:0] bufo_18_WEN_A;
output [31:0] bufo_18_Din_A;
input [31:0] bufo_18_Dout_A;
output bufo_18_Clk_A;
output bufo_18_Rst_A;
output [31:0] bufo_19_Addr_A;
output bufo_19_EN_A;
output [3:0] bufo_19_WEN_A;
output [31:0] bufo_19_Din_A;
input [31:0] bufo_19_Dout_A;
output bufo_19_Clk_A;
output bufo_19_Rst_A;
output [31:0] bufo_20_Addr_A;
output bufo_20_EN_A;
output [3:0] bufo_20_WEN_A;
output [31:0] bufo_20_Din_A;
input [31:0] bufo_20_Dout_A;
output bufo_20_Clk_A;
output bufo_20_Rst_A;
output [31:0] bufo_21_Addr_A;
output bufo_21_EN_A;
output [3:0] bufo_21_WEN_A;
output [31:0] bufo_21_Din_A;
input [31:0] bufo_21_Dout_A;
output bufo_21_Clk_A;
output bufo_21_Rst_A;
output [31:0] bufo_22_Addr_A;
output bufo_22_EN_A;
output [3:0] bufo_22_WEN_A;
output [31:0] bufo_22_Din_A;
input [31:0] bufo_22_Dout_A;
output bufo_22_Clk_A;
output bufo_22_Rst_A;
output [31:0] bufo_23_Addr_A;
output bufo_23_EN_A;
output [3:0] bufo_23_WEN_A;
output [31:0] bufo_23_Din_A;
input [31:0] bufo_23_Dout_A;
output bufo_23_Clk_A;
output bufo_23_Rst_A;
output [31:0] bufo_24_Addr_A;
output bufo_24_EN_A;
output [3:0] bufo_24_WEN_A;
output [31:0] bufo_24_Din_A;
input [31:0] bufo_24_Dout_A;
output bufo_24_Clk_A;
output bufo_24_Rst_A;
output [31:0] bufo_25_Addr_A;
output bufo_25_EN_A;
output [3:0] bufo_25_WEN_A;
output [31:0] bufo_25_Din_A;
input [31:0] bufo_25_Dout_A;
output bufo_25_Clk_A;
output bufo_25_Rst_A;
output [31:0] bufo_26_Addr_A;
output bufo_26_EN_A;
output [3:0] bufo_26_WEN_A;
output [31:0] bufo_26_Din_A;
input [31:0] bufo_26_Dout_A;
output bufo_26_Clk_A;
output bufo_26_Rst_A;
output [31:0] bufo_27_Addr_A;
output bufo_27_EN_A;
output [3:0] bufo_27_WEN_A;
output [31:0] bufo_27_Din_A;
input [31:0] bufo_27_Dout_A;
output bufo_27_Clk_A;
output bufo_27_Rst_A;
output [31:0] bufo_28_Addr_A;
output bufo_28_EN_A;
output [3:0] bufo_28_WEN_A;
output [31:0] bufo_28_Din_A;
input [31:0] bufo_28_Dout_A;
output bufo_28_Clk_A;
output bufo_28_Rst_A;
output [31:0] bufo_29_Addr_A;
output bufo_29_EN_A;
output [3:0] bufo_29_WEN_A;
output [31:0] bufo_29_Din_A;
input [31:0] bufo_29_Dout_A;
output bufo_29_Clk_A;
output bufo_29_Rst_A;
output [31:0] bufo_30_Addr_A;
output bufo_30_EN_A;
output [3:0] bufo_30_WEN_A;
output [31:0] bufo_30_Din_A;
input [31:0] bufo_30_Dout_A;
output bufo_30_Clk_A;
output bufo_30_Rst_A;
output [31:0] bufo_31_Addr_A;
output bufo_31_EN_A;
output [3:0] bufo_31_WEN_A;
output [31:0] bufo_31_Din_A;
input [31:0] bufo_31_Dout_A;
output bufo_31_Clk_A;
output bufo_31_Rst_A;
output [31:0] bufo_32_Addr_A;
output bufo_32_EN_A;
output [3:0] bufo_32_WEN_A;
output [31:0] bufo_32_Din_A;
input [31:0] bufo_32_Dout_A;
output bufo_32_Clk_A;
output bufo_32_Rst_A;
output [31:0] bufo_33_Addr_A;
output bufo_33_EN_A;
output [3:0] bufo_33_WEN_A;
output [31:0] bufo_33_Din_A;
input [31:0] bufo_33_Dout_A;
output bufo_33_Clk_A;
output bufo_33_Rst_A;
output [31:0] bufo_34_Addr_A;
output bufo_34_EN_A;
output [3:0] bufo_34_WEN_A;
output [31:0] bufo_34_Din_A;
input [31:0] bufo_34_Dout_A;
output bufo_34_Clk_A;
output bufo_34_Rst_A;
output [31:0] bufo_35_Addr_A;
output bufo_35_EN_A;
output [3:0] bufo_35_WEN_A;
output [31:0] bufo_35_Din_A;
input [31:0] bufo_35_Dout_A;
output bufo_35_Clk_A;
output bufo_35_Rst_A;
output [31:0] bufo_36_Addr_A;
output bufo_36_EN_A;
output [3:0] bufo_36_WEN_A;
output [31:0] bufo_36_Din_A;
input [31:0] bufo_36_Dout_A;
output bufo_36_Clk_A;
output bufo_36_Rst_A;
output [31:0] bufo_37_Addr_A;
output bufo_37_EN_A;
output [3:0] bufo_37_WEN_A;
output [31:0] bufo_37_Din_A;
input [31:0] bufo_37_Dout_A;
output bufo_37_Clk_A;
output bufo_37_Rst_A;
output [31:0] bufo_38_Addr_A;
output bufo_38_EN_A;
output [3:0] bufo_38_WEN_A;
output [31:0] bufo_38_Din_A;
input [31:0] bufo_38_Dout_A;
output bufo_38_Clk_A;
output bufo_38_Rst_A;
output [31:0] bufo_39_Addr_A;
output bufo_39_EN_A;
output [3:0] bufo_39_WEN_A;
output [31:0] bufo_39_Din_A;
input [31:0] bufo_39_Dout_A;
output bufo_39_Clk_A;
output bufo_39_Rst_A;
output [31:0] bufo_40_Addr_A;
output bufo_40_EN_A;
output [3:0] bufo_40_WEN_A;
output [31:0] bufo_40_Din_A;
input [31:0] bufo_40_Dout_A;
output bufo_40_Clk_A;
output bufo_40_Rst_A;
output [31:0] bufo_41_Addr_A;
output bufo_41_EN_A;
output [3:0] bufo_41_WEN_A;
output [31:0] bufo_41_Din_A;
input [31:0] bufo_41_Dout_A;
output bufo_41_Clk_A;
output bufo_41_Rst_A;
output [31:0] bufo_42_Addr_A;
output bufo_42_EN_A;
output [3:0] bufo_42_WEN_A;
output [31:0] bufo_42_Din_A;
input [31:0] bufo_42_Dout_A;
output bufo_42_Clk_A;
output bufo_42_Rst_A;
output [31:0] bufo_43_Addr_A;
output bufo_43_EN_A;
output [3:0] bufo_43_WEN_A;
output [31:0] bufo_43_Din_A;
input [31:0] bufo_43_Dout_A;
output bufo_43_Clk_A;
output bufo_43_Rst_A;
output [31:0] bufo_44_Addr_A;
output bufo_44_EN_A;
output [3:0] bufo_44_WEN_A;
output [31:0] bufo_44_Din_A;
input [31:0] bufo_44_Dout_A;
output bufo_44_Clk_A;
output bufo_44_Rst_A;
output [31:0] bufo_45_Addr_A;
output bufo_45_EN_A;
output [3:0] bufo_45_WEN_A;
output [31:0] bufo_45_Din_A;
input [31:0] bufo_45_Dout_A;
output bufo_45_Clk_A;
output bufo_45_Rst_A;
output [31:0] bufo_46_Addr_A;
output bufo_46_EN_A;
output [3:0] bufo_46_WEN_A;
output [31:0] bufo_46_Din_A;
input [31:0] bufo_46_Dout_A;
output bufo_46_Clk_A;
output bufo_46_Rst_A;
output [31:0] bufo_47_Addr_A;
output bufo_47_EN_A;
output [3:0] bufo_47_WEN_A;
output [31:0] bufo_47_Din_A;
input [31:0] bufo_47_Dout_A;
output bufo_47_Clk_A;
output bufo_47_Rst_A;
output [31:0] bufo_48_Addr_A;
output bufo_48_EN_A;
output [3:0] bufo_48_WEN_A;
output [31:0] bufo_48_Din_A;
input [31:0] bufo_48_Dout_A;
output bufo_48_Clk_A;
output bufo_48_Rst_A;
output [31:0] bufo_49_Addr_A;
output bufo_49_EN_A;
output [3:0] bufo_49_WEN_A;
output [31:0] bufo_49_Din_A;
input [31:0] bufo_49_Dout_A;
output bufo_49_Clk_A;
output bufo_49_Rst_A;
output [31:0] bufo_50_Addr_A;
output bufo_50_EN_A;
output [3:0] bufo_50_WEN_A;
output [31:0] bufo_50_Din_A;
input [31:0] bufo_50_Dout_A;
output bufo_50_Clk_A;
output bufo_50_Rst_A;
output [31:0] bufo_51_Addr_A;
output bufo_51_EN_A;
output [3:0] bufo_51_WEN_A;
output [31:0] bufo_51_Din_A;
input [31:0] bufo_51_Dout_A;
output bufo_51_Clk_A;
output bufo_51_Rst_A;
output [31:0] bufo_52_Addr_A;
output bufo_52_EN_A;
output [3:0] bufo_52_WEN_A;
output [31:0] bufo_52_Din_A;
input [31:0] bufo_52_Dout_A;
output bufo_52_Clk_A;
output bufo_52_Rst_A;
output [31:0] bufo_53_Addr_A;
output bufo_53_EN_A;
output [3:0] bufo_53_WEN_A;
output [31:0] bufo_53_Din_A;
input [31:0] bufo_53_Dout_A;
output bufo_53_Clk_A;
output bufo_53_Rst_A;
output [31:0] bufo_54_Addr_A;
output bufo_54_EN_A;
output [3:0] bufo_54_WEN_A;
output [31:0] bufo_54_Din_A;
input [31:0] bufo_54_Dout_A;
output bufo_54_Clk_A;
output bufo_54_Rst_A;
output [31:0] bufo_55_Addr_A;
output bufo_55_EN_A;
output [3:0] bufo_55_WEN_A;
output [31:0] bufo_55_Din_A;
input [31:0] bufo_55_Dout_A;
output bufo_55_Clk_A;
output bufo_55_Rst_A;
output [31:0] bufo_56_Addr_A;
output bufo_56_EN_A;
output [3:0] bufo_56_WEN_A;
output [31:0] bufo_56_Din_A;
input [31:0] bufo_56_Dout_A;
output bufo_56_Clk_A;
output bufo_56_Rst_A;
output [31:0] bufo_57_Addr_A;
output bufo_57_EN_A;
output [3:0] bufo_57_WEN_A;
output [31:0] bufo_57_Din_A;
input [31:0] bufo_57_Dout_A;
output bufo_57_Clk_A;
output bufo_57_Rst_A;
output [31:0] bufo_58_Addr_A;
output bufo_58_EN_A;
output [3:0] bufo_58_WEN_A;
output [31:0] bufo_58_Din_A;
input [31:0] bufo_58_Dout_A;
output bufo_58_Clk_A;
output bufo_58_Rst_A;
output [31:0] bufo_59_Addr_A;
output bufo_59_EN_A;
output [3:0] bufo_59_WEN_A;
output [31:0] bufo_59_Din_A;
input [31:0] bufo_59_Dout_A;
output bufo_59_Clk_A;
output bufo_59_Rst_A;
output [31:0] bufo_60_Addr_A;
output bufo_60_EN_A;
output [3:0] bufo_60_WEN_A;
output [31:0] bufo_60_Din_A;
input [31:0] bufo_60_Dout_A;
output bufo_60_Clk_A;
output bufo_60_Rst_A;
output [31:0] bufo_61_Addr_A;
output bufo_61_EN_A;
output [3:0] bufo_61_WEN_A;
output [31:0] bufo_61_Din_A;
input [31:0] bufo_61_Dout_A;
output bufo_61_Clk_A;
output bufo_61_Rst_A;
output [31:0] bufo_62_Addr_A;
output bufo_62_EN_A;
output [3:0] bufo_62_WEN_A;
output [31:0] bufo_62_Din_A;
input [31:0] bufo_62_Dout_A;
output bufo_62_Clk_A;
output bufo_62_Rst_A;
output [31:0] bufo_63_Addr_A;
output bufo_63_EN_A;
output [3:0] bufo_63_WEN_A;
output [31:0] bufo_63_Din_A;
input [31:0] bufo_63_Dout_A;
output bufo_63_Clk_A;
output bufo_63_Rst_A;
output [31:0] bufo_64_Addr_A;
output bufo_64_EN_A;
output [3:0] bufo_64_WEN_A;
output [31:0] bufo_64_Din_A;
input [31:0] bufo_64_Dout_A;
output bufo_64_Clk_A;
output bufo_64_Rst_A;
output [31:0] bufo_65_Addr_A;
output bufo_65_EN_A;
output [3:0] bufo_65_WEN_A;
output [31:0] bufo_65_Din_A;
input [31:0] bufo_65_Dout_A;
output bufo_65_Clk_A;
output bufo_65_Rst_A;
output [31:0] bufo_66_Addr_A;
output bufo_66_EN_A;
output [3:0] bufo_66_WEN_A;
output [31:0] bufo_66_Din_A;
input [31:0] bufo_66_Dout_A;
output bufo_66_Clk_A;
output bufo_66_Rst_A;
output [31:0] bufo_67_Addr_A;
output bufo_67_EN_A;
output [3:0] bufo_67_WEN_A;
output [31:0] bufo_67_Din_A;
input [31:0] bufo_67_Dout_A;
output bufo_67_Clk_A;
output bufo_67_Rst_A;
output [31:0] bufo_68_Addr_A;
output bufo_68_EN_A;
output [3:0] bufo_68_WEN_A;
output [31:0] bufo_68_Din_A;
input [31:0] bufo_68_Dout_A;
output bufo_68_Clk_A;
output bufo_68_Rst_A;
output [31:0] bufo_69_Addr_A;
output bufo_69_EN_A;
output [3:0] bufo_69_WEN_A;
output [31:0] bufo_69_Din_A;
input [31:0] bufo_69_Dout_A;
output bufo_69_Clk_A;
output bufo_69_Rst_A;
output [31:0] bufo_70_Addr_A;
output bufo_70_EN_A;
output [3:0] bufo_70_WEN_A;
output [31:0] bufo_70_Din_A;
input [31:0] bufo_70_Dout_A;
output bufo_70_Clk_A;
output bufo_70_Rst_A;
output [31:0] bufo_71_Addr_A;
output bufo_71_EN_A;
output [3:0] bufo_71_WEN_A;
output [31:0] bufo_71_Din_A;
input [31:0] bufo_71_Dout_A;
output bufo_71_Clk_A;
output bufo_71_Rst_A;
output [31:0] bufo_72_Addr_A;
output bufo_72_EN_A;
output [3:0] bufo_72_WEN_A;
output [31:0] bufo_72_Din_A;
input [31:0] bufo_72_Dout_A;
output bufo_72_Clk_A;
output bufo_72_Rst_A;
output [31:0] bufo_73_Addr_A;
output bufo_73_EN_A;
output [3:0] bufo_73_WEN_A;
output [31:0] bufo_73_Din_A;
input [31:0] bufo_73_Dout_A;
output bufo_73_Clk_A;
output bufo_73_Rst_A;
output [31:0] bufo_74_Addr_A;
output bufo_74_EN_A;
output [3:0] bufo_74_WEN_A;
output [31:0] bufo_74_Din_A;
input [31:0] bufo_74_Dout_A;
output bufo_74_Clk_A;
output bufo_74_Rst_A;
output [31:0] bufo_75_Addr_A;
output bufo_75_EN_A;
output [3:0] bufo_75_WEN_A;
output [31:0] bufo_75_Din_A;
input [31:0] bufo_75_Dout_A;
output bufo_75_Clk_A;
output bufo_75_Rst_A;
output [31:0] bufo_76_Addr_A;
output bufo_76_EN_A;
output [3:0] bufo_76_WEN_A;
output [31:0] bufo_76_Din_A;
input [31:0] bufo_76_Dout_A;
output bufo_76_Clk_A;
output bufo_76_Rst_A;
output [31:0] bufo_77_Addr_A;
output bufo_77_EN_A;
output [3:0] bufo_77_WEN_A;
output [31:0] bufo_77_Din_A;
input [31:0] bufo_77_Dout_A;
output bufo_77_Clk_A;
output bufo_77_Rst_A;
output [31:0] bufo_78_Addr_A;
output bufo_78_EN_A;
output [3:0] bufo_78_WEN_A;
output [31:0] bufo_78_Din_A;
input [31:0] bufo_78_Dout_A;
output bufo_78_Clk_A;
output bufo_78_Rst_A;
output [31:0] bufo_79_Addr_A;
output bufo_79_EN_A;
output [3:0] bufo_79_WEN_A;
output [31:0] bufo_79_Din_A;
input [31:0] bufo_79_Dout_A;
output bufo_79_Clk_A;
output bufo_79_Rst_A;
output [31:0] bufo_80_Addr_A;
output bufo_80_EN_A;
output [3:0] bufo_80_WEN_A;
output [31:0] bufo_80_Din_A;
input [31:0] bufo_80_Dout_A;
output bufo_80_Clk_A;
output bufo_80_Rst_A;
output [31:0] bufo_81_Addr_A;
output bufo_81_EN_A;
output [3:0] bufo_81_WEN_A;
output [31:0] bufo_81_Din_A;
input [31:0] bufo_81_Dout_A;
output bufo_81_Clk_A;
output bufo_81_Rst_A;
output [31:0] bufo_82_Addr_A;
output bufo_82_EN_A;
output [3:0] bufo_82_WEN_A;
output [31:0] bufo_82_Din_A;
input [31:0] bufo_82_Dout_A;
output bufo_82_Clk_A;
output bufo_82_Rst_A;
output [31:0] bufo_83_Addr_A;
output bufo_83_EN_A;
output [3:0] bufo_83_WEN_A;
output [31:0] bufo_83_Din_A;
input [31:0] bufo_83_Dout_A;
output bufo_83_Clk_A;
output bufo_83_Rst_A;
output [31:0] bufo_84_Addr_A;
output bufo_84_EN_A;
output [3:0] bufo_84_WEN_A;
output [31:0] bufo_84_Din_A;
input [31:0] bufo_84_Dout_A;
output bufo_84_Clk_A;
output bufo_84_Rst_A;
output [31:0] bufo_85_Addr_A;
output bufo_85_EN_A;
output [3:0] bufo_85_WEN_A;
output [31:0] bufo_85_Din_A;
input [31:0] bufo_85_Dout_A;
output bufo_85_Clk_A;
output bufo_85_Rst_A;
output [31:0] bufo_86_Addr_A;
output bufo_86_EN_A;
output [3:0] bufo_86_WEN_A;
output [31:0] bufo_86_Din_A;
input [31:0] bufo_86_Dout_A;
output bufo_86_Clk_A;
output bufo_86_Rst_A;
output [31:0] bufo_87_Addr_A;
output bufo_87_EN_A;
output [3:0] bufo_87_WEN_A;
output [31:0] bufo_87_Din_A;
input [31:0] bufo_87_Dout_A;
output bufo_87_Clk_A;
output bufo_87_Rst_A;
output [31:0] bufo_88_Addr_A;
output bufo_88_EN_A;
output [3:0] bufo_88_WEN_A;
output [31:0] bufo_88_Din_A;
input [31:0] bufo_88_Dout_A;
output bufo_88_Clk_A;
output bufo_88_Rst_A;
output [31:0] bufo_89_Addr_A;
output bufo_89_EN_A;
output [3:0] bufo_89_WEN_A;
output [31:0] bufo_89_Din_A;
input [31:0] bufo_89_Dout_A;
output bufo_89_Clk_A;
output bufo_89_Rst_A;
output [31:0] bufo_90_Addr_A;
output bufo_90_EN_A;
output [3:0] bufo_90_WEN_A;
output [31:0] bufo_90_Din_A;
input [31:0] bufo_90_Dout_A;
output bufo_90_Clk_A;
output bufo_90_Rst_A;
output [31:0] bufo_91_Addr_A;
output bufo_91_EN_A;
output [3:0] bufo_91_WEN_A;
output [31:0] bufo_91_Din_A;
input [31:0] bufo_91_Dout_A;
output bufo_91_Clk_A;
output bufo_91_Rst_A;
output [31:0] bufo_92_Addr_A;
output bufo_92_EN_A;
output [3:0] bufo_92_WEN_A;
output [31:0] bufo_92_Din_A;
input [31:0] bufo_92_Dout_A;
output bufo_92_Clk_A;
output bufo_92_Rst_A;
output [31:0] bufo_93_Addr_A;
output bufo_93_EN_A;
output [3:0] bufo_93_WEN_A;
output [31:0] bufo_93_Din_A;
input [31:0] bufo_93_Dout_A;
output bufo_93_Clk_A;
output bufo_93_Rst_A;
output [31:0] bufo_94_Addr_A;
output bufo_94_EN_A;
output [3:0] bufo_94_WEN_A;
output [31:0] bufo_94_Din_A;
input [31:0] bufo_94_Dout_A;
output bufo_94_Clk_A;
output bufo_94_Rst_A;
output [31:0] bufo_95_Addr_A;
output bufo_95_EN_A;
output [3:0] bufo_95_WEN_A;
output [31:0] bufo_95_Din_A;
input [31:0] bufo_95_Dout_A;
output bufo_95_Clk_A;
output bufo_95_Rst_A;
output [31:0] bufo_96_Addr_A;
output bufo_96_EN_A;
output [3:0] bufo_96_WEN_A;
output [31:0] bufo_96_Din_A;
input [31:0] bufo_96_Dout_A;
output bufo_96_Clk_A;
output bufo_96_Rst_A;
output [31:0] bufo_97_Addr_A;
output bufo_97_EN_A;
output [3:0] bufo_97_WEN_A;
output [31:0] bufo_97_Din_A;
input [31:0] bufo_97_Dout_A;
output bufo_97_Clk_A;
output bufo_97_Rst_A;
output [31:0] bufo_98_Addr_A;
output bufo_98_EN_A;
output [3:0] bufo_98_WEN_A;
output [31:0] bufo_98_Din_A;
input [31:0] bufo_98_Dout_A;
output bufo_98_Clk_A;
output bufo_98_Rst_A;
output [31:0] bufo_99_Addr_A;
output bufo_99_EN_A;
output [3:0] bufo_99_WEN_A;
output [31:0] bufo_99_Din_A;
input [31:0] bufo_99_Dout_A;
output bufo_99_Clk_A;
output bufo_99_Rst_A;
output [31:0] bufo_100_Addr_A;
output bufo_100_EN_A;
output [3:0] bufo_100_WEN_A;
output [31:0] bufo_100_Din_A;
input [31:0] bufo_100_Dout_A;
output bufo_100_Clk_A;
output bufo_100_Rst_A;
output [31:0] bufo_101_Addr_A;
output bufo_101_EN_A;
output [3:0] bufo_101_WEN_A;
output [31:0] bufo_101_Din_A;
input [31:0] bufo_101_Dout_A;
output bufo_101_Clk_A;
output bufo_101_Rst_A;
output [31:0] bufo_102_Addr_A;
output bufo_102_EN_A;
output [3:0] bufo_102_WEN_A;
output [31:0] bufo_102_Din_A;
input [31:0] bufo_102_Dout_A;
output bufo_102_Clk_A;
output bufo_102_Rst_A;
output [31:0] bufo_103_Addr_A;
output bufo_103_EN_A;
output [3:0] bufo_103_WEN_A;
output [31:0] bufo_103_Din_A;
input [31:0] bufo_103_Dout_A;
output bufo_103_Clk_A;
output bufo_103_Rst_A;
output [31:0] bufo_104_Addr_A;
output bufo_104_EN_A;
output [3:0] bufo_104_WEN_A;
output [31:0] bufo_104_Din_A;
input [31:0] bufo_104_Dout_A;
output bufo_104_Clk_A;
output bufo_104_Rst_A;
output [31:0] bufo_105_Addr_A;
output bufo_105_EN_A;
output [3:0] bufo_105_WEN_A;
output [31:0] bufo_105_Din_A;
input [31:0] bufo_105_Dout_A;
output bufo_105_Clk_A;
output bufo_105_Rst_A;
output [31:0] bufo_106_Addr_A;
output bufo_106_EN_A;
output [3:0] bufo_106_WEN_A;
output [31:0] bufo_106_Din_A;
input [31:0] bufo_106_Dout_A;
output bufo_106_Clk_A;
output bufo_106_Rst_A;
output [31:0] bufo_107_Addr_A;
output bufo_107_EN_A;
output [3:0] bufo_107_WEN_A;
output [31:0] bufo_107_Din_A;
input [31:0] bufo_107_Dout_A;
output bufo_107_Clk_A;
output bufo_107_Rst_A;
output [31:0] bufo_108_Addr_A;
output bufo_108_EN_A;
output [3:0] bufo_108_WEN_A;
output [31:0] bufo_108_Din_A;
input [31:0] bufo_108_Dout_A;
output bufo_108_Clk_A;
output bufo_108_Rst_A;
output [31:0] bufo_109_Addr_A;
output bufo_109_EN_A;
output [3:0] bufo_109_WEN_A;
output [31:0] bufo_109_Din_A;
input [31:0] bufo_109_Dout_A;
output bufo_109_Clk_A;
output bufo_109_Rst_A;
output [31:0] bufo_110_Addr_A;
output bufo_110_EN_A;
output [3:0] bufo_110_WEN_A;
output [31:0] bufo_110_Din_A;
input [31:0] bufo_110_Dout_A;
output bufo_110_Clk_A;
output bufo_110_Rst_A;
output [31:0] bufo_111_Addr_A;
output bufo_111_EN_A;
output [3:0] bufo_111_WEN_A;
output [31:0] bufo_111_Din_A;
input [31:0] bufo_111_Dout_A;
output bufo_111_Clk_A;
output bufo_111_Rst_A;
output [31:0] bufo_112_Addr_A;
output bufo_112_EN_A;
output [3:0] bufo_112_WEN_A;
output [31:0] bufo_112_Din_A;
input [31:0] bufo_112_Dout_A;
output bufo_112_Clk_A;
output bufo_112_Rst_A;
output [31:0] bufo_113_Addr_A;
output bufo_113_EN_A;
output [3:0] bufo_113_WEN_A;
output [31:0] bufo_113_Din_A;
input [31:0] bufo_113_Dout_A;
output bufo_113_Clk_A;
output bufo_113_Rst_A;
output [31:0] bufo_114_Addr_A;
output bufo_114_EN_A;
output [3:0] bufo_114_WEN_A;
output [31:0] bufo_114_Din_A;
input [31:0] bufo_114_Dout_A;
output bufo_114_Clk_A;
output bufo_114_Rst_A;
output [31:0] bufo_115_Addr_A;
output bufo_115_EN_A;
output [3:0] bufo_115_WEN_A;
output [31:0] bufo_115_Din_A;
input [31:0] bufo_115_Dout_A;
output bufo_115_Clk_A;
output bufo_115_Rst_A;
output [31:0] bufo_116_Addr_A;
output bufo_116_EN_A;
output [3:0] bufo_116_WEN_A;
output [31:0] bufo_116_Din_A;
input [31:0] bufo_116_Dout_A;
output bufo_116_Clk_A;
output bufo_116_Rst_A;
output [31:0] bufo_117_Addr_A;
output bufo_117_EN_A;
output [3:0] bufo_117_WEN_A;
output [31:0] bufo_117_Din_A;
input [31:0] bufo_117_Dout_A;
output bufo_117_Clk_A;
output bufo_117_Rst_A;
output [31:0] bufo_118_Addr_A;
output bufo_118_EN_A;
output [3:0] bufo_118_WEN_A;
output [31:0] bufo_118_Din_A;
input [31:0] bufo_118_Dout_A;
output bufo_118_Clk_A;
output bufo_118_Rst_A;
output [31:0] bufo_119_Addr_A;
output bufo_119_EN_A;
output [3:0] bufo_119_WEN_A;
output [31:0] bufo_119_Din_A;
input [31:0] bufo_119_Dout_A;
output bufo_119_Clk_A;
output bufo_119_Rst_A;
output [31:0] bufo_120_Addr_A;
output bufo_120_EN_A;
output [3:0] bufo_120_WEN_A;
output [31:0] bufo_120_Din_A;
input [31:0] bufo_120_Dout_A;
output bufo_120_Clk_A;
output bufo_120_Rst_A;
output [31:0] bufo_121_Addr_A;
output bufo_121_EN_A;
output [3:0] bufo_121_WEN_A;
output [31:0] bufo_121_Din_A;
input [31:0] bufo_121_Dout_A;
output bufo_121_Clk_A;
output bufo_121_Rst_A;
output [31:0] bufo_122_Addr_A;
output bufo_122_EN_A;
output [3:0] bufo_122_WEN_A;
output [31:0] bufo_122_Din_A;
input [31:0] bufo_122_Dout_A;
output bufo_122_Clk_A;
output bufo_122_Rst_A;
output [31:0] bufo_123_Addr_A;
output bufo_123_EN_A;
output [3:0] bufo_123_WEN_A;
output [31:0] bufo_123_Din_A;
input [31:0] bufo_123_Dout_A;
output bufo_123_Clk_A;
output bufo_123_Rst_A;
output [31:0] bufo_124_Addr_A;
output bufo_124_EN_A;
output [3:0] bufo_124_WEN_A;
output [31:0] bufo_124_Din_A;
input [31:0] bufo_124_Dout_A;
output bufo_124_Clk_A;
output bufo_124_Rst_A;
output [31:0] bufo_125_Addr_A;
output bufo_125_EN_A;
output [3:0] bufo_125_WEN_A;
output [31:0] bufo_125_Din_A;
input [31:0] bufo_125_Dout_A;
output bufo_125_Clk_A;
output bufo_125_Rst_A;
output [31:0] bufo_126_Addr_A;
output bufo_126_EN_A;
output [3:0] bufo_126_WEN_A;
output [31:0] bufo_126_Din_A;
input [31:0] bufo_126_Dout_A;
output bufo_126_Clk_A;
output bufo_126_Rst_A;
output [31:0] bufo_127_Addr_A;
output bufo_127_EN_A;
output [3:0] bufo_127_WEN_A;
output [31:0] bufo_127_Din_A;
input [31:0] bufo_127_Dout_A;
output bufo_127_Clk_A;
output bufo_127_Rst_A;
output [31:0] bufo_128_Addr_A;
output bufo_128_EN_A;
output [3:0] bufo_128_WEN_A;
output [31:0] bufo_128_Din_A;
input [31:0] bufo_128_Dout_A;
output bufo_128_Clk_A;
output bufo_128_Rst_A;
output [31:0] bufo_128_Addr_B;
output bufo_128_EN_B;
output [3:0] bufo_128_WEN_B;
output [31:0] bufo_128_Din_B;
input [31:0] bufo_128_Dout_B;
output bufo_128_Clk_B;
output bufo_128_Rst_B;
output [31:0] bufo_129_Addr_A;
output bufo_129_EN_A;
output [3:0] bufo_129_WEN_A;
output [31:0] bufo_129_Din_A;
input [31:0] bufo_129_Dout_A;
output bufo_129_Clk_A;
output bufo_129_Rst_A;
output [31:0] bufo_129_Addr_B;
output bufo_129_EN_B;
output [3:0] bufo_129_WEN_B;
output [31:0] bufo_129_Din_B;
input [31:0] bufo_129_Dout_B;
output bufo_129_Clk_B;
output bufo_129_Rst_B;
output [31:0] bufo_130_Addr_A;
output bufo_130_EN_A;
output [3:0] bufo_130_WEN_A;
output [31:0] bufo_130_Din_A;
input [31:0] bufo_130_Dout_A;
output bufo_130_Clk_A;
output bufo_130_Rst_A;
output [31:0] bufo_130_Addr_B;
output bufo_130_EN_B;
output [3:0] bufo_130_WEN_B;
output [31:0] bufo_130_Din_B;
input [31:0] bufo_130_Dout_B;
output bufo_130_Clk_B;
output bufo_130_Rst_B;
output [31:0] bufo_131_Addr_A;
output bufo_131_EN_A;
output [3:0] bufo_131_WEN_A;
output [31:0] bufo_131_Din_A;
input [31:0] bufo_131_Dout_A;
output bufo_131_Clk_A;
output bufo_131_Rst_A;
output [31:0] bufo_131_Addr_B;
output bufo_131_EN_B;
output [3:0] bufo_131_WEN_B;
output [31:0] bufo_131_Din_B;
input [31:0] bufo_131_Dout_B;
output bufo_131_Clk_B;
output bufo_131_Rst_B;
output [31:0] bufo_132_Addr_A;
output bufo_132_EN_A;
output [3:0] bufo_132_WEN_A;
output [31:0] bufo_132_Din_A;
input [31:0] bufo_132_Dout_A;
output bufo_132_Clk_A;
output bufo_132_Rst_A;
output [31:0] bufo_132_Addr_B;
output bufo_132_EN_B;
output [3:0] bufo_132_WEN_B;
output [31:0] bufo_132_Din_B;
input [31:0] bufo_132_Dout_B;
output bufo_132_Clk_B;
output bufo_132_Rst_B;
output [31:0] bufo_133_Addr_A;
output bufo_133_EN_A;
output [3:0] bufo_133_WEN_A;
output [31:0] bufo_133_Din_A;
input [31:0] bufo_133_Dout_A;
output bufo_133_Clk_A;
output bufo_133_Rst_A;
output [31:0] bufo_133_Addr_B;
output bufo_133_EN_B;
output [3:0] bufo_133_WEN_B;
output [31:0] bufo_133_Din_B;
input [31:0] bufo_133_Dout_B;
output bufo_133_Clk_B;
output bufo_133_Rst_B;
output [31:0] bufo_134_Addr_A;
output bufo_134_EN_A;
output [3:0] bufo_134_WEN_A;
output [31:0] bufo_134_Din_A;
input [31:0] bufo_134_Dout_A;
output bufo_134_Clk_A;
output bufo_134_Rst_A;
output [31:0] bufo_134_Addr_B;
output bufo_134_EN_B;
output [3:0] bufo_134_WEN_B;
output [31:0] bufo_134_Din_B;
input [31:0] bufo_134_Dout_B;
output bufo_134_Clk_B;
output bufo_134_Rst_B;
output [31:0] bufo_135_Addr_A;
output bufo_135_EN_A;
output [3:0] bufo_135_WEN_A;
output [31:0] bufo_135_Din_A;
input [31:0] bufo_135_Dout_A;
output bufo_135_Clk_A;
output bufo_135_Rst_A;
output [31:0] bufo_135_Addr_B;
output bufo_135_EN_B;
output [3:0] bufo_135_WEN_B;
output [31:0] bufo_135_Din_B;
input [31:0] bufo_135_Dout_B;
output bufo_135_Clk_B;
output bufo_135_Rst_B;
output [31:0] bufo_136_Addr_A;
output bufo_136_EN_A;
output [3:0] bufo_136_WEN_A;
output [31:0] bufo_136_Din_A;
input [31:0] bufo_136_Dout_A;
output bufo_136_Clk_A;
output bufo_136_Rst_A;
output [31:0] bufo_136_Addr_B;
output bufo_136_EN_B;
output [3:0] bufo_136_WEN_B;
output [31:0] bufo_136_Din_B;
input [31:0] bufo_136_Dout_B;
output bufo_136_Clk_B;
output bufo_136_Rst_B;
output [31:0] bufo_137_Addr_A;
output bufo_137_EN_A;
output [3:0] bufo_137_WEN_A;
output [31:0] bufo_137_Din_A;
input [31:0] bufo_137_Dout_A;
output bufo_137_Clk_A;
output bufo_137_Rst_A;
output [31:0] bufo_137_Addr_B;
output bufo_137_EN_B;
output [3:0] bufo_137_WEN_B;
output [31:0] bufo_137_Din_B;
input [31:0] bufo_137_Dout_B;
output bufo_137_Clk_B;
output bufo_137_Rst_B;
output [31:0] bufo_138_Addr_A;
output bufo_138_EN_A;
output [3:0] bufo_138_WEN_A;
output [31:0] bufo_138_Din_A;
input [31:0] bufo_138_Dout_A;
output bufo_138_Clk_A;
output bufo_138_Rst_A;
output [31:0] bufo_138_Addr_B;
output bufo_138_EN_B;
output [3:0] bufo_138_WEN_B;
output [31:0] bufo_138_Din_B;
input [31:0] bufo_138_Dout_B;
output bufo_138_Clk_B;
output bufo_138_Rst_B;
output [31:0] bufo_139_Addr_A;
output bufo_139_EN_A;
output [3:0] bufo_139_WEN_A;
output [31:0] bufo_139_Din_A;
input [31:0] bufo_139_Dout_A;
output bufo_139_Clk_A;
output bufo_139_Rst_A;
output [31:0] bufo_139_Addr_B;
output bufo_139_EN_B;
output [3:0] bufo_139_WEN_B;
output [31:0] bufo_139_Din_B;
input [31:0] bufo_139_Dout_B;
output bufo_139_Clk_B;
output bufo_139_Rst_B;
output [31:0] bufo_140_Addr_A;
output bufo_140_EN_A;
output [3:0] bufo_140_WEN_A;
output [31:0] bufo_140_Din_A;
input [31:0] bufo_140_Dout_A;
output bufo_140_Clk_A;
output bufo_140_Rst_A;
output [31:0] bufo_140_Addr_B;
output bufo_140_EN_B;
output [3:0] bufo_140_WEN_B;
output [31:0] bufo_140_Din_B;
input [31:0] bufo_140_Dout_B;
output bufo_140_Clk_B;
output bufo_140_Rst_B;
output [31:0] bufo_141_Addr_A;
output bufo_141_EN_A;
output [3:0] bufo_141_WEN_A;
output [31:0] bufo_141_Din_A;
input [31:0] bufo_141_Dout_A;
output bufo_141_Clk_A;
output bufo_141_Rst_A;
output [31:0] bufo_141_Addr_B;
output bufo_141_EN_B;
output [3:0] bufo_141_WEN_B;
output [31:0] bufo_141_Din_B;
input [31:0] bufo_141_Dout_B;
output bufo_141_Clk_B;
output bufo_141_Rst_B;
output [31:0] bufo_142_Addr_A;
output bufo_142_EN_A;
output [3:0] bufo_142_WEN_A;
output [31:0] bufo_142_Din_A;
input [31:0] bufo_142_Dout_A;
output bufo_142_Clk_A;
output bufo_142_Rst_A;
output [31:0] bufo_142_Addr_B;
output bufo_142_EN_B;
output [3:0] bufo_142_WEN_B;
output [31:0] bufo_142_Din_B;
input [31:0] bufo_142_Dout_B;
output bufo_142_Clk_B;
output bufo_142_Rst_B;
output [31:0] bufo_143_Addr_A;
output bufo_143_EN_A;
output [3:0] bufo_143_WEN_A;
output [31:0] bufo_143_Din_A;
input [31:0] bufo_143_Dout_A;
output bufo_143_Clk_A;
output bufo_143_Rst_A;
output [31:0] bufo_143_Addr_B;
output bufo_143_EN_B;
output [3:0] bufo_143_WEN_B;
output [31:0] bufo_143_Din_B;
input [31:0] bufo_143_Dout_B;
output bufo_143_Clk_B;
output bufo_143_Rst_B;
output [31:0] bufo_144_Addr_A;
output bufo_144_EN_A;
output [3:0] bufo_144_WEN_A;
output [31:0] bufo_144_Din_A;
input [31:0] bufo_144_Dout_A;
output bufo_144_Clk_A;
output bufo_144_Rst_A;
output [31:0] bufo_144_Addr_B;
output bufo_144_EN_B;
output [3:0] bufo_144_WEN_B;
output [31:0] bufo_144_Din_B;
input [31:0] bufo_144_Dout_B;
output bufo_144_Clk_B;
output bufo_144_Rst_B;
output [31:0] bufo_145_Addr_A;
output bufo_145_EN_A;
output [3:0] bufo_145_WEN_A;
output [31:0] bufo_145_Din_A;
input [31:0] bufo_145_Dout_A;
output bufo_145_Clk_A;
output bufo_145_Rst_A;
output [31:0] bufo_145_Addr_B;
output bufo_145_EN_B;
output [3:0] bufo_145_WEN_B;
output [31:0] bufo_145_Din_B;
input [31:0] bufo_145_Dout_B;
output bufo_145_Clk_B;
output bufo_145_Rst_B;
output [31:0] bufo_146_Addr_A;
output bufo_146_EN_A;
output [3:0] bufo_146_WEN_A;
output [31:0] bufo_146_Din_A;
input [31:0] bufo_146_Dout_A;
output bufo_146_Clk_A;
output bufo_146_Rst_A;
output [31:0] bufo_146_Addr_B;
output bufo_146_EN_B;
output [3:0] bufo_146_WEN_B;
output [31:0] bufo_146_Din_B;
input [31:0] bufo_146_Dout_B;
output bufo_146_Clk_B;
output bufo_146_Rst_B;
output [31:0] bufo_147_Addr_A;
output bufo_147_EN_A;
output [3:0] bufo_147_WEN_A;
output [31:0] bufo_147_Din_A;
input [31:0] bufo_147_Dout_A;
output bufo_147_Clk_A;
output bufo_147_Rst_A;
output [31:0] bufo_147_Addr_B;
output bufo_147_EN_B;
output [3:0] bufo_147_WEN_B;
output [31:0] bufo_147_Din_B;
input [31:0] bufo_147_Dout_B;
output bufo_147_Clk_B;
output bufo_147_Rst_B;
output [31:0] bufo_148_Addr_A;
output bufo_148_EN_A;
output [3:0] bufo_148_WEN_A;
output [31:0] bufo_148_Din_A;
input [31:0] bufo_148_Dout_A;
output bufo_148_Clk_A;
output bufo_148_Rst_A;
output [31:0] bufo_148_Addr_B;
output bufo_148_EN_B;
output [3:0] bufo_148_WEN_B;
output [31:0] bufo_148_Din_B;
input [31:0] bufo_148_Dout_B;
output bufo_148_Clk_B;
output bufo_148_Rst_B;
output [31:0] bufo_149_Addr_A;
output bufo_149_EN_A;
output [3:0] bufo_149_WEN_A;
output [31:0] bufo_149_Din_A;
input [31:0] bufo_149_Dout_A;
output bufo_149_Clk_A;
output bufo_149_Rst_A;
output [31:0] bufo_149_Addr_B;
output bufo_149_EN_B;
output [3:0] bufo_149_WEN_B;
output [31:0] bufo_149_Din_B;
input [31:0] bufo_149_Dout_B;
output bufo_149_Clk_B;
output bufo_149_Rst_B;
output [31:0] bufo_150_Addr_A;
output bufo_150_EN_A;
output [3:0] bufo_150_WEN_A;
output [31:0] bufo_150_Din_A;
input [31:0] bufo_150_Dout_A;
output bufo_150_Clk_A;
output bufo_150_Rst_A;
output [31:0] bufo_150_Addr_B;
output bufo_150_EN_B;
output [3:0] bufo_150_WEN_B;
output [31:0] bufo_150_Din_B;
input [31:0] bufo_150_Dout_B;
output bufo_150_Clk_B;
output bufo_150_Rst_B;
output [31:0] bufo_151_Addr_A;
output bufo_151_EN_A;
output [3:0] bufo_151_WEN_A;
output [31:0] bufo_151_Din_A;
input [31:0] bufo_151_Dout_A;
output bufo_151_Clk_A;
output bufo_151_Rst_A;
output [31:0] bufo_151_Addr_B;
output bufo_151_EN_B;
output [3:0] bufo_151_WEN_B;
output [31:0] bufo_151_Din_B;
input [31:0] bufo_151_Dout_B;
output bufo_151_Clk_B;
output bufo_151_Rst_B;
output [31:0] bufo_152_Addr_A;
output bufo_152_EN_A;
output [3:0] bufo_152_WEN_A;
output [31:0] bufo_152_Din_A;
input [31:0] bufo_152_Dout_A;
output bufo_152_Clk_A;
output bufo_152_Rst_A;
output [31:0] bufo_152_Addr_B;
output bufo_152_EN_B;
output [3:0] bufo_152_WEN_B;
output [31:0] bufo_152_Din_B;
input [31:0] bufo_152_Dout_B;
output bufo_152_Clk_B;
output bufo_152_Rst_B;
output [31:0] bufo_153_Addr_A;
output bufo_153_EN_A;
output [3:0] bufo_153_WEN_A;
output [31:0] bufo_153_Din_A;
input [31:0] bufo_153_Dout_A;
output bufo_153_Clk_A;
output bufo_153_Rst_A;
output [31:0] bufo_153_Addr_B;
output bufo_153_EN_B;
output [3:0] bufo_153_WEN_B;
output [31:0] bufo_153_Din_B;
input [31:0] bufo_153_Dout_B;
output bufo_153_Clk_B;
output bufo_153_Rst_B;
output [31:0] bufo_154_Addr_A;
output bufo_154_EN_A;
output [3:0] bufo_154_WEN_A;
output [31:0] bufo_154_Din_A;
input [31:0] bufo_154_Dout_A;
output bufo_154_Clk_A;
output bufo_154_Rst_A;
output [31:0] bufo_154_Addr_B;
output bufo_154_EN_B;
output [3:0] bufo_154_WEN_B;
output [31:0] bufo_154_Din_B;
input [31:0] bufo_154_Dout_B;
output bufo_154_Clk_B;
output bufo_154_Rst_B;
output [31:0] bufo_155_Addr_A;
output bufo_155_EN_A;
output [3:0] bufo_155_WEN_A;
output [31:0] bufo_155_Din_A;
input [31:0] bufo_155_Dout_A;
output bufo_155_Clk_A;
output bufo_155_Rst_A;
output [31:0] bufo_155_Addr_B;
output bufo_155_EN_B;
output [3:0] bufo_155_WEN_B;
output [31:0] bufo_155_Din_B;
input [31:0] bufo_155_Dout_B;
output bufo_155_Clk_B;
output bufo_155_Rst_B;
output [31:0] bufo_156_Addr_A;
output bufo_156_EN_A;
output [3:0] bufo_156_WEN_A;
output [31:0] bufo_156_Din_A;
input [31:0] bufo_156_Dout_A;
output bufo_156_Clk_A;
output bufo_156_Rst_A;
output [31:0] bufo_156_Addr_B;
output bufo_156_EN_B;
output [3:0] bufo_156_WEN_B;
output [31:0] bufo_156_Din_B;
input [31:0] bufo_156_Dout_B;
output bufo_156_Clk_B;
output bufo_156_Rst_B;
output [31:0] bufo_157_Addr_A;
output bufo_157_EN_A;
output [3:0] bufo_157_WEN_A;
output [31:0] bufo_157_Din_A;
input [31:0] bufo_157_Dout_A;
output bufo_157_Clk_A;
output bufo_157_Rst_A;
output [31:0] bufo_157_Addr_B;
output bufo_157_EN_B;
output [3:0] bufo_157_WEN_B;
output [31:0] bufo_157_Din_B;
input [31:0] bufo_157_Dout_B;
output bufo_157_Clk_B;
output bufo_157_Rst_B;
output [31:0] bufo_158_Addr_A;
output bufo_158_EN_A;
output [3:0] bufo_158_WEN_A;
output [31:0] bufo_158_Din_A;
input [31:0] bufo_158_Dout_A;
output bufo_158_Clk_A;
output bufo_158_Rst_A;
output [31:0] bufo_158_Addr_B;
output bufo_158_EN_B;
output [3:0] bufo_158_WEN_B;
output [31:0] bufo_158_Din_B;
input [31:0] bufo_158_Dout_B;
output bufo_158_Clk_B;
output bufo_158_Rst_B;
output [31:0] bufo_159_Addr_A;
output bufo_159_EN_A;
output [3:0] bufo_159_WEN_A;
output [31:0] bufo_159_Din_A;
input [31:0] bufo_159_Dout_A;
output bufo_159_Clk_A;
output bufo_159_Rst_A;
output [31:0] bufo_159_Addr_B;
output bufo_159_EN_B;
output [3:0] bufo_159_WEN_B;
output [31:0] bufo_159_Din_B;
input [31:0] bufo_159_Dout_B;
output bufo_159_Clk_B;
output bufo_159_Rst_B;
output [31:0] bufo_160_Addr_A;
output bufo_160_EN_A;
output [3:0] bufo_160_WEN_A;
output [31:0] bufo_160_Din_A;
input [31:0] bufo_160_Dout_A;
output bufo_160_Clk_A;
output bufo_160_Rst_A;
output [31:0] bufo_160_Addr_B;
output bufo_160_EN_B;
output [3:0] bufo_160_WEN_B;
output [31:0] bufo_160_Din_B;
input [31:0] bufo_160_Dout_B;
output bufo_160_Clk_B;
output bufo_160_Rst_B;
output [31:0] bufo_161_Addr_A;
output bufo_161_EN_A;
output [3:0] bufo_161_WEN_A;
output [31:0] bufo_161_Din_A;
input [31:0] bufo_161_Dout_A;
output bufo_161_Clk_A;
output bufo_161_Rst_A;
output [31:0] bufo_161_Addr_B;
output bufo_161_EN_B;
output [3:0] bufo_161_WEN_B;
output [31:0] bufo_161_Din_B;
input [31:0] bufo_161_Dout_B;
output bufo_161_Clk_B;
output bufo_161_Rst_B;
output [31:0] bufo_162_Addr_A;
output bufo_162_EN_A;
output [3:0] bufo_162_WEN_A;
output [31:0] bufo_162_Din_A;
input [31:0] bufo_162_Dout_A;
output bufo_162_Clk_A;
output bufo_162_Rst_A;
output [31:0] bufo_162_Addr_B;
output bufo_162_EN_B;
output [3:0] bufo_162_WEN_B;
output [31:0] bufo_162_Din_B;
input [31:0] bufo_162_Dout_B;
output bufo_162_Clk_B;
output bufo_162_Rst_B;
output [31:0] bufo_163_Addr_A;
output bufo_163_EN_A;
output [3:0] bufo_163_WEN_A;
output [31:0] bufo_163_Din_A;
input [31:0] bufo_163_Dout_A;
output bufo_163_Clk_A;
output bufo_163_Rst_A;
output [31:0] bufo_163_Addr_B;
output bufo_163_EN_B;
output [3:0] bufo_163_WEN_B;
output [31:0] bufo_163_Din_B;
input [31:0] bufo_163_Dout_B;
output bufo_163_Clk_B;
output bufo_163_Rst_B;
output [31:0] bufo_164_Addr_A;
output bufo_164_EN_A;
output [3:0] bufo_164_WEN_A;
output [31:0] bufo_164_Din_A;
input [31:0] bufo_164_Dout_A;
output bufo_164_Clk_A;
output bufo_164_Rst_A;
output [31:0] bufo_164_Addr_B;
output bufo_164_EN_B;
output [3:0] bufo_164_WEN_B;
output [31:0] bufo_164_Din_B;
input [31:0] bufo_164_Dout_B;
output bufo_164_Clk_B;
output bufo_164_Rst_B;
output [31:0] bufo_165_Addr_A;
output bufo_165_EN_A;
output [3:0] bufo_165_WEN_A;
output [31:0] bufo_165_Din_A;
input [31:0] bufo_165_Dout_A;
output bufo_165_Clk_A;
output bufo_165_Rst_A;
output [31:0] bufo_165_Addr_B;
output bufo_165_EN_B;
output [3:0] bufo_165_WEN_B;
output [31:0] bufo_165_Din_B;
input [31:0] bufo_165_Dout_B;
output bufo_165_Clk_B;
output bufo_165_Rst_B;
output [31:0] bufo_166_Addr_A;
output bufo_166_EN_A;
output [3:0] bufo_166_WEN_A;
output [31:0] bufo_166_Din_A;
input [31:0] bufo_166_Dout_A;
output bufo_166_Clk_A;
output bufo_166_Rst_A;
output [31:0] bufo_166_Addr_B;
output bufo_166_EN_B;
output [3:0] bufo_166_WEN_B;
output [31:0] bufo_166_Din_B;
input [31:0] bufo_166_Dout_B;
output bufo_166_Clk_B;
output bufo_166_Rst_B;
output [31:0] bufo_167_Addr_A;
output bufo_167_EN_A;
output [3:0] bufo_167_WEN_A;
output [31:0] bufo_167_Din_A;
input [31:0] bufo_167_Dout_A;
output bufo_167_Clk_A;
output bufo_167_Rst_A;
output [31:0] bufo_167_Addr_B;
output bufo_167_EN_B;
output [3:0] bufo_167_WEN_B;
output [31:0] bufo_167_Din_B;
input [31:0] bufo_167_Dout_B;
output bufo_167_Clk_B;
output bufo_167_Rst_B;
output [31:0] bufo_168_Addr_A;
output bufo_168_EN_A;
output [3:0] bufo_168_WEN_A;
output [31:0] bufo_168_Din_A;
input [31:0] bufo_168_Dout_A;
output bufo_168_Clk_A;
output bufo_168_Rst_A;
output [31:0] bufo_168_Addr_B;
output bufo_168_EN_B;
output [3:0] bufo_168_WEN_B;
output [31:0] bufo_168_Din_B;
input [31:0] bufo_168_Dout_B;
output bufo_168_Clk_B;
output bufo_168_Rst_B;
output [31:0] bufo_169_Addr_A;
output bufo_169_EN_A;
output [3:0] bufo_169_WEN_A;
output [31:0] bufo_169_Din_A;
input [31:0] bufo_169_Dout_A;
output bufo_169_Clk_A;
output bufo_169_Rst_A;
output [31:0] bufo_169_Addr_B;
output bufo_169_EN_B;
output [3:0] bufo_169_WEN_B;
output [31:0] bufo_169_Din_B;
input [31:0] bufo_169_Dout_B;
output bufo_169_Clk_B;
output bufo_169_Rst_B;
output [31:0] bufo_170_Addr_A;
output bufo_170_EN_A;
output [3:0] bufo_170_WEN_A;
output [31:0] bufo_170_Din_A;
input [31:0] bufo_170_Dout_A;
output bufo_170_Clk_A;
output bufo_170_Rst_A;
output [31:0] bufo_170_Addr_B;
output bufo_170_EN_B;
output [3:0] bufo_170_WEN_B;
output [31:0] bufo_170_Din_B;
input [31:0] bufo_170_Dout_B;
output bufo_170_Clk_B;
output bufo_170_Rst_B;
output [31:0] bufo_171_Addr_A;
output bufo_171_EN_A;
output [3:0] bufo_171_WEN_A;
output [31:0] bufo_171_Din_A;
input [31:0] bufo_171_Dout_A;
output bufo_171_Clk_A;
output bufo_171_Rst_A;
output [31:0] bufo_171_Addr_B;
output bufo_171_EN_B;
output [3:0] bufo_171_WEN_B;
output [31:0] bufo_171_Din_B;
input [31:0] bufo_171_Dout_B;
output bufo_171_Clk_B;
output bufo_171_Rst_B;
output [31:0] bufo_172_Addr_A;
output bufo_172_EN_A;
output [3:0] bufo_172_WEN_A;
output [31:0] bufo_172_Din_A;
input [31:0] bufo_172_Dout_A;
output bufo_172_Clk_A;
output bufo_172_Rst_A;
output [31:0] bufo_172_Addr_B;
output bufo_172_EN_B;
output [3:0] bufo_172_WEN_B;
output [31:0] bufo_172_Din_B;
input [31:0] bufo_172_Dout_B;
output bufo_172_Clk_B;
output bufo_172_Rst_B;
output [31:0] bufo_173_Addr_A;
output bufo_173_EN_A;
output [3:0] bufo_173_WEN_A;
output [31:0] bufo_173_Din_A;
input [31:0] bufo_173_Dout_A;
output bufo_173_Clk_A;
output bufo_173_Rst_A;
output [31:0] bufo_173_Addr_B;
output bufo_173_EN_B;
output [3:0] bufo_173_WEN_B;
output [31:0] bufo_173_Din_B;
input [31:0] bufo_173_Dout_B;
output bufo_173_Clk_B;
output bufo_173_Rst_B;
output [31:0] bufo_174_Addr_A;
output bufo_174_EN_A;
output [3:0] bufo_174_WEN_A;
output [31:0] bufo_174_Din_A;
input [31:0] bufo_174_Dout_A;
output bufo_174_Clk_A;
output bufo_174_Rst_A;
output [31:0] bufo_174_Addr_B;
output bufo_174_EN_B;
output [3:0] bufo_174_WEN_B;
output [31:0] bufo_174_Din_B;
input [31:0] bufo_174_Dout_B;
output bufo_174_Clk_B;
output bufo_174_Rst_B;
output [31:0] bufo_175_Addr_A;
output bufo_175_EN_A;
output [3:0] bufo_175_WEN_A;
output [31:0] bufo_175_Din_A;
input [31:0] bufo_175_Dout_A;
output bufo_175_Clk_A;
output bufo_175_Rst_A;
output [31:0] bufo_175_Addr_B;
output bufo_175_EN_B;
output [3:0] bufo_175_WEN_B;
output [31:0] bufo_175_Din_B;
input [31:0] bufo_175_Dout_B;
output bufo_175_Clk_B;
output bufo_175_Rst_B;
output [31:0] bufo_176_Addr_A;
output bufo_176_EN_A;
output [3:0] bufo_176_WEN_A;
output [31:0] bufo_176_Din_A;
input [31:0] bufo_176_Dout_A;
output bufo_176_Clk_A;
output bufo_176_Rst_A;
output [31:0] bufo_176_Addr_B;
output bufo_176_EN_B;
output [3:0] bufo_176_WEN_B;
output [31:0] bufo_176_Din_B;
input [31:0] bufo_176_Dout_B;
output bufo_176_Clk_B;
output bufo_176_Rst_B;
output [31:0] bufo_177_Addr_A;
output bufo_177_EN_A;
output [3:0] bufo_177_WEN_A;
output [31:0] bufo_177_Din_A;
input [31:0] bufo_177_Dout_A;
output bufo_177_Clk_A;
output bufo_177_Rst_A;
output [31:0] bufo_177_Addr_B;
output bufo_177_EN_B;
output [3:0] bufo_177_WEN_B;
output [31:0] bufo_177_Din_B;
input [31:0] bufo_177_Dout_B;
output bufo_177_Clk_B;
output bufo_177_Rst_B;
output [31:0] bufo_178_Addr_A;
output bufo_178_EN_A;
output [3:0] bufo_178_WEN_A;
output [31:0] bufo_178_Din_A;
input [31:0] bufo_178_Dout_A;
output bufo_178_Clk_A;
output bufo_178_Rst_A;
output [31:0] bufo_178_Addr_B;
output bufo_178_EN_B;
output [3:0] bufo_178_WEN_B;
output [31:0] bufo_178_Din_B;
input [31:0] bufo_178_Dout_B;
output bufo_178_Clk_B;
output bufo_178_Rst_B;
output [31:0] bufo_179_Addr_A;
output bufo_179_EN_A;
output [3:0] bufo_179_WEN_A;
output [31:0] bufo_179_Din_A;
input [31:0] bufo_179_Dout_A;
output bufo_179_Clk_A;
output bufo_179_Rst_A;
output [31:0] bufo_179_Addr_B;
output bufo_179_EN_B;
output [3:0] bufo_179_WEN_B;
output [31:0] bufo_179_Din_B;
input [31:0] bufo_179_Dout_B;
output bufo_179_Clk_B;
output bufo_179_Rst_B;
output [31:0] bufo_180_Addr_A;
output bufo_180_EN_A;
output [3:0] bufo_180_WEN_A;
output [31:0] bufo_180_Din_A;
input [31:0] bufo_180_Dout_A;
output bufo_180_Clk_A;
output bufo_180_Rst_A;
output [31:0] bufo_180_Addr_B;
output bufo_180_EN_B;
output [3:0] bufo_180_WEN_B;
output [31:0] bufo_180_Din_B;
input [31:0] bufo_180_Dout_B;
output bufo_180_Clk_B;
output bufo_180_Rst_B;
output [31:0] bufo_181_Addr_A;
output bufo_181_EN_A;
output [3:0] bufo_181_WEN_A;
output [31:0] bufo_181_Din_A;
input [31:0] bufo_181_Dout_A;
output bufo_181_Clk_A;
output bufo_181_Rst_A;
output [31:0] bufo_181_Addr_B;
output bufo_181_EN_B;
output [3:0] bufo_181_WEN_B;
output [31:0] bufo_181_Din_B;
input [31:0] bufo_181_Dout_B;
output bufo_181_Clk_B;
output bufo_181_Rst_B;
output [31:0] bufo_182_Addr_A;
output bufo_182_EN_A;
output [3:0] bufo_182_WEN_A;
output [31:0] bufo_182_Din_A;
input [31:0] bufo_182_Dout_A;
output bufo_182_Clk_A;
output bufo_182_Rst_A;
output [31:0] bufo_182_Addr_B;
output bufo_182_EN_B;
output [3:0] bufo_182_WEN_B;
output [31:0] bufo_182_Din_B;
input [31:0] bufo_182_Dout_B;
output bufo_182_Clk_B;
output bufo_182_Rst_B;
output [31:0] bufo_183_Addr_A;
output bufo_183_EN_A;
output [3:0] bufo_183_WEN_A;
output [31:0] bufo_183_Din_A;
input [31:0] bufo_183_Dout_A;
output bufo_183_Clk_A;
output bufo_183_Rst_A;
output [31:0] bufo_183_Addr_B;
output bufo_183_EN_B;
output [3:0] bufo_183_WEN_B;
output [31:0] bufo_183_Din_B;
input [31:0] bufo_183_Dout_B;
output bufo_183_Clk_B;
output bufo_183_Rst_B;
output [31:0] bufo_184_Addr_A;
output bufo_184_EN_A;
output [3:0] bufo_184_WEN_A;
output [31:0] bufo_184_Din_A;
input [31:0] bufo_184_Dout_A;
output bufo_184_Clk_A;
output bufo_184_Rst_A;
output [31:0] bufo_184_Addr_B;
output bufo_184_EN_B;
output [3:0] bufo_184_WEN_B;
output [31:0] bufo_184_Din_B;
input [31:0] bufo_184_Dout_B;
output bufo_184_Clk_B;
output bufo_184_Rst_B;
output [31:0] bufo_185_Addr_A;
output bufo_185_EN_A;
output [3:0] bufo_185_WEN_A;
output [31:0] bufo_185_Din_A;
input [31:0] bufo_185_Dout_A;
output bufo_185_Clk_A;
output bufo_185_Rst_A;
output [31:0] bufo_185_Addr_B;
output bufo_185_EN_B;
output [3:0] bufo_185_WEN_B;
output [31:0] bufo_185_Din_B;
input [31:0] bufo_185_Dout_B;
output bufo_185_Clk_B;
output bufo_185_Rst_B;
output [31:0] bufo_186_Addr_A;
output bufo_186_EN_A;
output [3:0] bufo_186_WEN_A;
output [31:0] bufo_186_Din_A;
input [31:0] bufo_186_Dout_A;
output bufo_186_Clk_A;
output bufo_186_Rst_A;
output [31:0] bufo_186_Addr_B;
output bufo_186_EN_B;
output [3:0] bufo_186_WEN_B;
output [31:0] bufo_186_Din_B;
input [31:0] bufo_186_Dout_B;
output bufo_186_Clk_B;
output bufo_186_Rst_B;
output [31:0] bufo_187_Addr_A;
output bufo_187_EN_A;
output [3:0] bufo_187_WEN_A;
output [31:0] bufo_187_Din_A;
input [31:0] bufo_187_Dout_A;
output bufo_187_Clk_A;
output bufo_187_Rst_A;
output [31:0] bufo_187_Addr_B;
output bufo_187_EN_B;
output [3:0] bufo_187_WEN_B;
output [31:0] bufo_187_Din_B;
input [31:0] bufo_187_Dout_B;
output bufo_187_Clk_B;
output bufo_187_Rst_B;
output [31:0] bufo_188_Addr_A;
output bufo_188_EN_A;
output [3:0] bufo_188_WEN_A;
output [31:0] bufo_188_Din_A;
input [31:0] bufo_188_Dout_A;
output bufo_188_Clk_A;
output bufo_188_Rst_A;
output [31:0] bufo_188_Addr_B;
output bufo_188_EN_B;
output [3:0] bufo_188_WEN_B;
output [31:0] bufo_188_Din_B;
input [31:0] bufo_188_Dout_B;
output bufo_188_Clk_B;
output bufo_188_Rst_B;
output [31:0] bufo_189_Addr_A;
output bufo_189_EN_A;
output [3:0] bufo_189_WEN_A;
output [31:0] bufo_189_Din_A;
input [31:0] bufo_189_Dout_A;
output bufo_189_Clk_A;
output bufo_189_Rst_A;
output [31:0] bufo_189_Addr_B;
output bufo_189_EN_B;
output [3:0] bufo_189_WEN_B;
output [31:0] bufo_189_Din_B;
input [31:0] bufo_189_Dout_B;
output bufo_189_Clk_B;
output bufo_189_Rst_B;
output [31:0] bufo_190_Addr_A;
output bufo_190_EN_A;
output [3:0] bufo_190_WEN_A;
output [31:0] bufo_190_Din_A;
input [31:0] bufo_190_Dout_A;
output bufo_190_Clk_A;
output bufo_190_Rst_A;
output [31:0] bufo_190_Addr_B;
output bufo_190_EN_B;
output [3:0] bufo_190_WEN_B;
output [31:0] bufo_190_Din_B;
input [31:0] bufo_190_Dout_B;
output bufo_190_Clk_B;
output bufo_190_Rst_B;
output [31:0] bufo_191_Addr_A;
output bufo_191_EN_A;
output [3:0] bufo_191_WEN_A;
output [31:0] bufo_191_Din_A;
input [31:0] bufo_191_Dout_A;
output bufo_191_Clk_A;
output bufo_191_Rst_A;
output [31:0] bufo_191_Addr_B;
output bufo_191_EN_B;
output [3:0] bufo_191_WEN_B;
output [31:0] bufo_191_Din_B;
input [31:0] bufo_191_Dout_B;
output bufo_191_Clk_B;
output bufo_191_Rst_B;
output [31:0] bufo_192_Addr_A;
output bufo_192_EN_A;
output [3:0] bufo_192_WEN_A;
output [31:0] bufo_192_Din_A;
input [31:0] bufo_192_Dout_A;
output bufo_192_Clk_A;
output bufo_192_Rst_A;
output [31:0] bufo_192_Addr_B;
output bufo_192_EN_B;
output [3:0] bufo_192_WEN_B;
output [31:0] bufo_192_Din_B;
input [31:0] bufo_192_Dout_B;
output bufo_192_Clk_B;
output bufo_192_Rst_B;
output [31:0] bufo_193_Addr_A;
output bufo_193_EN_A;
output [3:0] bufo_193_WEN_A;
output [31:0] bufo_193_Din_A;
input [31:0] bufo_193_Dout_A;
output bufo_193_Clk_A;
output bufo_193_Rst_A;
output [31:0] bufo_193_Addr_B;
output bufo_193_EN_B;
output [3:0] bufo_193_WEN_B;
output [31:0] bufo_193_Din_B;
input [31:0] bufo_193_Dout_B;
output bufo_193_Clk_B;
output bufo_193_Rst_B;
output [31:0] bufo_194_Addr_A;
output bufo_194_EN_A;
output [3:0] bufo_194_WEN_A;
output [31:0] bufo_194_Din_A;
input [31:0] bufo_194_Dout_A;
output bufo_194_Clk_A;
output bufo_194_Rst_A;
output [31:0] bufo_194_Addr_B;
output bufo_194_EN_B;
output [3:0] bufo_194_WEN_B;
output [31:0] bufo_194_Din_B;
input [31:0] bufo_194_Dout_B;
output bufo_194_Clk_B;
output bufo_194_Rst_B;
output [31:0] bufo_195_Addr_A;
output bufo_195_EN_A;
output [3:0] bufo_195_WEN_A;
output [31:0] bufo_195_Din_A;
input [31:0] bufo_195_Dout_A;
output bufo_195_Clk_A;
output bufo_195_Rst_A;
output [31:0] bufo_195_Addr_B;
output bufo_195_EN_B;
output [3:0] bufo_195_WEN_B;
output [31:0] bufo_195_Din_B;
input [31:0] bufo_195_Dout_B;
output bufo_195_Clk_B;
output bufo_195_Rst_B;
output [31:0] bufo_196_Addr_A;
output bufo_196_EN_A;
output [3:0] bufo_196_WEN_A;
output [31:0] bufo_196_Din_A;
input [31:0] bufo_196_Dout_A;
output bufo_196_Clk_A;
output bufo_196_Rst_A;
output [31:0] bufo_196_Addr_B;
output bufo_196_EN_B;
output [3:0] bufo_196_WEN_B;
output [31:0] bufo_196_Din_B;
input [31:0] bufo_196_Dout_B;
output bufo_196_Clk_B;
output bufo_196_Rst_B;
output [31:0] bufo_197_Addr_A;
output bufo_197_EN_A;
output [3:0] bufo_197_WEN_A;
output [31:0] bufo_197_Din_A;
input [31:0] bufo_197_Dout_A;
output bufo_197_Clk_A;
output bufo_197_Rst_A;
output [31:0] bufo_197_Addr_B;
output bufo_197_EN_B;
output [3:0] bufo_197_WEN_B;
output [31:0] bufo_197_Din_B;
input [31:0] bufo_197_Dout_B;
output bufo_197_Clk_B;
output bufo_197_Rst_B;
output [31:0] bufo_198_Addr_A;
output bufo_198_EN_A;
output [3:0] bufo_198_WEN_A;
output [31:0] bufo_198_Din_A;
input [31:0] bufo_198_Dout_A;
output bufo_198_Clk_A;
output bufo_198_Rst_A;
output [31:0] bufo_198_Addr_B;
output bufo_198_EN_B;
output [3:0] bufo_198_WEN_B;
output [31:0] bufo_198_Din_B;
input [31:0] bufo_198_Dout_B;
output bufo_198_Clk_B;
output bufo_198_Rst_B;
output [31:0] bufo_199_Addr_A;
output bufo_199_EN_A;
output [3:0] bufo_199_WEN_A;
output [31:0] bufo_199_Din_A;
input [31:0] bufo_199_Dout_A;
output bufo_199_Clk_A;
output bufo_199_Rst_A;
output [31:0] bufo_199_Addr_B;
output bufo_199_EN_B;
output [3:0] bufo_199_WEN_B;
output [31:0] bufo_199_Din_B;
input [31:0] bufo_199_Dout_B;
output bufo_199_Clk_B;
output bufo_199_Rst_B;
reg ap_idle;
reg bufw_EN_A;
reg bufi_EN_A;
reg bufo_0_EN_A;
reg[3:0] bufo_0_WEN_A;
reg bufo_1_EN_A;
reg[3:0] bufo_1_WEN_A;
reg bufo_2_EN_A;
reg[3:0] bufo_2_WEN_A;
reg bufo_3_EN_A;
reg[3:0] bufo_3_WEN_A;
reg bufo_4_EN_A;
reg[3:0] bufo_4_WEN_A;
reg bufo_5_EN_A;
reg[3:0] bufo_5_WEN_A;
reg bufo_6_EN_A;
reg[3:0] bufo_6_WEN_A;
reg bufo_7_EN_A;
reg[3:0] bufo_7_WEN_A;
reg bufo_8_EN_A;
reg[3:0] bufo_8_WEN_A;
reg bufo_9_EN_A;
reg[3:0] bufo_9_WEN_A;
reg bufo_10_EN_A;
reg[3:0] bufo_10_WEN_A;
reg bufo_11_EN_A;
reg[3:0] bufo_11_WEN_A;
reg bufo_12_EN_A;
reg[3:0] bufo_12_WEN_A;
reg bufo_13_EN_A;
reg[3:0] bufo_13_WEN_A;
reg bufo_14_EN_A;
reg[3:0] bufo_14_WEN_A;
reg bufo_15_EN_A;
reg[3:0] bufo_15_WEN_A;
reg bufo_16_EN_A;
reg[3:0] bufo_16_WEN_A;
reg bufo_17_EN_A;
reg[3:0] bufo_17_WEN_A;
reg bufo_18_EN_A;
reg[3:0] bufo_18_WEN_A;
reg bufo_19_EN_A;
reg[3:0] bufo_19_WEN_A;
reg bufo_20_EN_A;
reg[3:0] bufo_20_WEN_A;
reg bufo_21_EN_A;
reg[3:0] bufo_21_WEN_A;
reg bufo_22_EN_A;
reg[3:0] bufo_22_WEN_A;
reg bufo_23_EN_A;
reg[3:0] bufo_23_WEN_A;
reg bufo_24_EN_A;
reg[3:0] bufo_24_WEN_A;
reg bufo_25_EN_A;
reg[3:0] bufo_25_WEN_A;
reg bufo_26_EN_A;
reg[3:0] bufo_26_WEN_A;
reg bufo_27_EN_A;
reg[3:0] bufo_27_WEN_A;
reg bufo_28_EN_A;
reg[3:0] bufo_28_WEN_A;
reg bufo_29_EN_A;
reg[3:0] bufo_29_WEN_A;
reg bufo_30_EN_A;
reg[3:0] bufo_30_WEN_A;
reg bufo_31_EN_A;
reg[3:0] bufo_31_WEN_A;
reg bufo_32_EN_A;
reg[3:0] bufo_32_WEN_A;
reg bufo_33_EN_A;
reg[3:0] bufo_33_WEN_A;
reg bufo_34_EN_A;
reg[3:0] bufo_34_WEN_A;
reg bufo_35_EN_A;
reg[3:0] bufo_35_WEN_A;
reg bufo_36_EN_A;
reg[3:0] bufo_36_WEN_A;
reg bufo_37_EN_A;
reg[3:0] bufo_37_WEN_A;
reg bufo_38_EN_A;
reg[3:0] bufo_38_WEN_A;
reg bufo_39_EN_A;
reg[3:0] bufo_39_WEN_A;
reg bufo_40_EN_A;
reg[3:0] bufo_40_WEN_A;
reg bufo_41_EN_A;
reg[3:0] bufo_41_WEN_A;
reg bufo_42_EN_A;
reg[3:0] bufo_42_WEN_A;
reg bufo_43_EN_A;
reg[3:0] bufo_43_WEN_A;
reg bufo_44_EN_A;
reg[3:0] bufo_44_WEN_A;
reg bufo_45_EN_A;
reg[3:0] bufo_45_WEN_A;
reg bufo_46_EN_A;
reg[3:0] bufo_46_WEN_A;
reg bufo_47_EN_A;
reg[3:0] bufo_47_WEN_A;
reg bufo_48_EN_A;
reg[3:0] bufo_48_WEN_A;
reg bufo_49_EN_A;
reg[3:0] bufo_49_WEN_A;
reg bufo_50_EN_A;
reg[3:0] bufo_50_WEN_A;
reg bufo_51_EN_A;
reg[3:0] bufo_51_WEN_A;
reg bufo_52_EN_A;
reg[3:0] bufo_52_WEN_A;
reg bufo_53_EN_A;
reg[3:0] bufo_53_WEN_A;
reg bufo_54_EN_A;
reg[3:0] bufo_54_WEN_A;
reg bufo_55_EN_A;
reg[3:0] bufo_55_WEN_A;
reg bufo_56_EN_A;
reg[3:0] bufo_56_WEN_A;
reg bufo_57_EN_A;
reg[3:0] bufo_57_WEN_A;
reg bufo_58_EN_A;
reg[3:0] bufo_58_WEN_A;
reg bufo_59_EN_A;
reg[3:0] bufo_59_WEN_A;
reg bufo_60_EN_A;
reg[3:0] bufo_60_WEN_A;
reg bufo_61_EN_A;
reg[3:0] bufo_61_WEN_A;
reg bufo_62_EN_A;
reg[3:0] bufo_62_WEN_A;
reg bufo_63_EN_A;
reg[3:0] bufo_63_WEN_A;
reg bufo_64_EN_A;
reg[3:0] bufo_64_WEN_A;
reg bufo_65_EN_A;
reg[3:0] bufo_65_WEN_A;
reg bufo_66_EN_A;
reg[3:0] bufo_66_WEN_A;
reg bufo_67_EN_A;
reg[3:0] bufo_67_WEN_A;
reg bufo_68_EN_A;
reg[3:0] bufo_68_WEN_A;
reg bufo_69_EN_A;
reg[3:0] bufo_69_WEN_A;
reg bufo_70_EN_A;
reg[3:0] bufo_70_WEN_A;
reg bufo_71_EN_A;
reg[3:0] bufo_71_WEN_A;
reg bufo_72_EN_A;
reg[3:0] bufo_72_WEN_A;
reg bufo_73_EN_A;
reg[3:0] bufo_73_WEN_A;
reg bufo_74_EN_A;
reg[3:0] bufo_74_WEN_A;
reg bufo_75_EN_A;
reg[3:0] bufo_75_WEN_A;
reg bufo_76_EN_A;
reg[3:0] bufo_76_WEN_A;
reg bufo_77_EN_A;
reg[3:0] bufo_77_WEN_A;
reg bufo_78_EN_A;
reg[3:0] bufo_78_WEN_A;
reg bufo_79_EN_A;
reg[3:0] bufo_79_WEN_A;
reg bufo_80_EN_A;
reg[3:0] bufo_80_WEN_A;
reg bufo_81_EN_A;
reg[3:0] bufo_81_WEN_A;
reg bufo_82_EN_A;
reg[3:0] bufo_82_WEN_A;
reg bufo_83_EN_A;
reg[3:0] bufo_83_WEN_A;
reg bufo_84_EN_A;
reg[3:0] bufo_84_WEN_A;
reg bufo_85_EN_A;
reg[3:0] bufo_85_WEN_A;
reg bufo_86_EN_A;
reg[3:0] bufo_86_WEN_A;
reg bufo_87_EN_A;
reg[3:0] bufo_87_WEN_A;
reg bufo_88_EN_A;
reg[3:0] bufo_88_WEN_A;
reg bufo_89_EN_A;
reg[3:0] bufo_89_WEN_A;
reg bufo_90_EN_A;
reg[3:0] bufo_90_WEN_A;
reg bufo_91_EN_A;
reg[3:0] bufo_91_WEN_A;
reg bufo_92_EN_A;
reg[3:0] bufo_92_WEN_A;
reg bufo_93_EN_A;
reg[3:0] bufo_93_WEN_A;
reg bufo_94_EN_A;
reg[3:0] bufo_94_WEN_A;
reg bufo_95_EN_A;
reg[3:0] bufo_95_WEN_A;
reg bufo_96_EN_A;
reg[3:0] bufo_96_WEN_A;
reg bufo_97_EN_A;
reg[3:0] bufo_97_WEN_A;
reg bufo_98_EN_A;
reg[3:0] bufo_98_WEN_A;
reg bufo_99_EN_A;
reg[3:0] bufo_99_WEN_A;
reg bufo_100_EN_A;
reg[3:0] bufo_100_WEN_A;
reg bufo_101_EN_A;
reg[3:0] bufo_101_WEN_A;
reg bufo_102_EN_A;
reg[3:0] bufo_102_WEN_A;
reg bufo_103_EN_A;
reg[3:0] bufo_103_WEN_A;
reg bufo_104_EN_A;
reg[3:0] bufo_104_WEN_A;
reg bufo_105_EN_A;
reg[3:0] bufo_105_WEN_A;
reg bufo_106_EN_A;
reg[3:0] bufo_106_WEN_A;
reg bufo_107_EN_A;
reg[3:0] bufo_107_WEN_A;
reg bufo_108_EN_A;
reg[3:0] bufo_108_WEN_A;
reg bufo_109_EN_A;
reg[3:0] bufo_109_WEN_A;
reg bufo_110_EN_A;
reg[3:0] bufo_110_WEN_A;
reg bufo_111_EN_A;
reg[3:0] bufo_111_WEN_A;
reg bufo_112_EN_A;
reg[3:0] bufo_112_WEN_A;
reg bufo_113_EN_A;
reg[3:0] bufo_113_WEN_A;
reg bufo_114_EN_A;
reg[3:0] bufo_114_WEN_A;
reg bufo_115_EN_A;
reg[3:0] bufo_115_WEN_A;
reg bufo_116_EN_A;
reg[3:0] bufo_116_WEN_A;
reg bufo_117_EN_A;
reg[3:0] bufo_117_WEN_A;
reg bufo_118_EN_A;
reg[3:0] bufo_118_WEN_A;
reg bufo_119_EN_A;
reg[3:0] bufo_119_WEN_A;
reg bufo_120_EN_A;
reg[3:0] bufo_120_WEN_A;
reg bufo_121_EN_A;
reg[3:0] bufo_121_WEN_A;
reg bufo_122_EN_A;
reg[3:0] bufo_122_WEN_A;
reg bufo_123_EN_A;
reg[3:0] bufo_123_WEN_A;
reg bufo_124_EN_A;
reg[3:0] bufo_124_WEN_A;
reg bufo_125_EN_A;
reg[3:0] bufo_125_WEN_A;
reg bufo_126_EN_A;
reg[3:0] bufo_126_WEN_A;
reg bufo_127_EN_A;
reg[3:0] bufo_127_WEN_A;
(* fsm_encoding = "none" *) reg [55:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [31:0] grp_fu_2558_p2;
reg [31:0] reg_2580;
wire ap_CS_fsm_state17;
wire ap_CS_fsm_state26;
wire ap_CS_fsm_state35;
wire ap_CS_fsm_state44;
wire ap_CS_fsm_state55;
wire [63:0] next_mul_fu_2714_p2;
reg [63:0] next_mul_reg_3471;
wire ap_CS_fsm_state2;
wire [31:0] tmp_fu_2720_p1;
reg [31:0] tmp_reg_3481;
wire ap_CS_fsm_state3;
wire [31:0] tmp_1_fu_2724_p1;
reg [31:0] tmp_1_reg_3486;
reg [31:0] tmp_6_reg_3491;
reg [31:0] tmp_8_reg_3496;
reg [31:0] tmp_4_reg_3501;
reg [31:0] tmp_11_reg_3506;
reg [31:0] tmp_13_reg_3511;
reg [31:0] tmp_15_reg_3516;
wire ap_CS_fsm_state4;
wire [31:0] grp_fu_2564_p2;
reg [31:0] tmp_s_reg_3561;
wire ap_CS_fsm_state8;
wire [31:0] grp_fu_2568_p2;
reg [31:0] tmp_5_1_reg_3566;
wire [31:0] grp_fu_2572_p2;
reg [31:0] tmp_5_2_reg_3571;
wire [31:0] grp_fu_2576_p2;
reg [31:0] tmp_5_3_reg_3576;
wire [6:0] to_b_V_fu_2820_p2;
reg [6:0] to_b_V_reg_3581;
reg [31:0] bufo_126_load_reg_3586;
wire ap_CS_fsm_state45;
reg [6:0] p_s_reg_2284;
reg [31:0] bufo_125_load_reg_3591;
reg [31:0] bufo_124_load_reg_3596;
reg [31:0] bufo_123_load_reg_3601;
reg [31:0] bufo_122_load_reg_3606;
reg [31:0] bufo_121_load_reg_3611;
reg [31:0] bufo_120_load_reg_3616;
reg [31:0] bufo_119_load_reg_3621;
reg [31:0] bufo_118_load_reg_3626;
reg [31:0] bufo_117_load_reg_3631;
reg [31:0] bufo_116_load_reg_3636;
reg [31:0] bufo_115_load_reg_3641;
reg [31:0] bufo_114_load_reg_3646;
reg [31:0] bufo_113_load_reg_3651;
reg [31:0] bufo_112_load_reg_3656;
reg [31:0] bufo_111_load_reg_3661;
reg [31:0] bufo_110_load_reg_3666;
reg [31:0] bufo_109_load_reg_3671;
reg [31:0] bufo_108_load_reg_3676;
reg [31:0] bufo_107_load_reg_3681;
reg [31:0] bufo_106_load_reg_3686;
reg [31:0] bufo_105_load_reg_3691;
reg [31:0] bufo_104_load_reg_3696;
reg [31:0] bufo_103_load_reg_3701;
reg [31:0] bufo_102_load_reg_3706;
reg [31:0] bufo_101_load_reg_3711;
reg [31:0] bufo_100_load_reg_3716;
reg [31:0] bufo_99_load_reg_3721;
reg [31:0] bufo_98_load_reg_3726;
reg [31:0] bufo_97_load_reg_3731;
reg [31:0] bufo_96_load_reg_3736;
reg [31:0] bufo_95_load_reg_3741;
reg [31:0] bufo_94_load_reg_3746;
reg [31:0] bufo_93_load_reg_3751;
reg [31:0] bufo_92_load_reg_3756;
reg [31:0] bufo_91_load_reg_3761;
reg [31:0] bufo_90_load_reg_3766;
reg [31:0] bufo_89_load_reg_3771;
reg [31:0] bufo_88_load_reg_3776;
reg [31:0] bufo_87_load_reg_3781;
reg [31:0] bufo_86_load_reg_3786;
reg [31:0] bufo_85_load_reg_3791;
reg [31:0] bufo_84_load_reg_3796;
reg [31:0] bufo_83_load_reg_3801;
reg [31:0] bufo_82_load_reg_3806;
reg [31:0] bufo_81_load_reg_3811;
reg [31:0] bufo_80_load_reg_3816;
reg [31:0] bufo_79_load_reg_3821;
reg [31:0] bufo_78_load_reg_3826;
reg [31:0] bufo_77_load_reg_3831;
reg [31:0] bufo_76_load_reg_3836;
reg [31:0] bufo_75_load_reg_3841;
reg [31:0] bufo_74_load_reg_3846;
reg [31:0] bufo_73_load_reg_3851;
reg [31:0] bufo_72_load_reg_3856;
reg [31:0] bufo_71_load_reg_3861;
reg [31:0] bufo_70_load_reg_3866;
reg [31:0] bufo_69_load_reg_3871;
reg [31:0] bufo_68_load_reg_3876;
reg [31:0] bufo_67_load_reg_3881;
reg [31:0] bufo_66_load_reg_3886;
reg [31:0] bufo_65_load_reg_3891;
reg [31:0] bufo_64_load_reg_3896;
reg [31:0] bufo_63_load_reg_3901;
reg [31:0] bufo_62_load_reg_3906;
reg [31:0] bufo_61_load_reg_3911;
reg [31:0] bufo_60_load_reg_3916;
reg [31:0] bufo_59_load_reg_3921;
reg [31:0] bufo_58_load_reg_3926;
reg [31:0] bufo_57_load_reg_3931;
reg [31:0] bufo_56_load_reg_3936;
reg [31:0] bufo_55_load_reg_3941;
reg [31:0] bufo_54_load_reg_3946;
reg [31:0] bufo_53_load_reg_3951;
reg [31:0] bufo_52_load_reg_3956;
reg [31:0] bufo_51_load_reg_3961;
reg [31:0] bufo_50_load_reg_3966;
reg [31:0] bufo_49_load_reg_3971;
reg [31:0] bufo_48_load_reg_3976;
reg [31:0] bufo_47_load_reg_3981;
reg [31:0] bufo_46_load_reg_3986;
reg [31:0] bufo_45_load_reg_3991;
reg [31:0] bufo_44_load_reg_3996;
reg [31:0] bufo_43_load_reg_4001;
reg [31:0] bufo_42_load_reg_4006;
reg [31:0] bufo_41_load_reg_4011;
reg [31:0] bufo_40_load_reg_4016;
reg [31:0] bufo_39_load_reg_4021;
reg [31:0] bufo_38_load_reg_4026;
reg [31:0] bufo_37_load_reg_4031;
reg [31:0] bufo_36_load_reg_4036;
reg [31:0] bufo_35_load_reg_4041;
reg [31:0] bufo_34_load_reg_4046;
reg [31:0] bufo_33_load_reg_4051;
reg [31:0] bufo_32_load_reg_4056;
reg [31:0] bufo_31_load_reg_4061;
reg [31:0] bufo_30_load_reg_4066;
reg [31:0] bufo_29_load_reg_4071;
reg [31:0] bufo_28_load_reg_4076;
reg [31:0] bufo_27_load_reg_4081;
reg [31:0] bufo_26_load_reg_4086;
reg [31:0] bufo_25_load_reg_4091;
reg [31:0] bufo_24_load_reg_4096;
reg [31:0] bufo_23_load_reg_4101;
reg [31:0] bufo_22_load_reg_4106;
reg [31:0] bufo_21_load_reg_4111;
reg [31:0] bufo_20_load_reg_4116;
reg [31:0] bufo_19_load_reg_4121;
reg [31:0] bufo_18_load_reg_4126;
reg [31:0] bufo_17_load_reg_4131;
reg [31:0] bufo_16_load_reg_4136;
reg [31:0] bufo_15_load_reg_4141;
reg [31:0] bufo_14_load_reg_4146;
reg [31:0] bufo_13_load_reg_4151;
reg [31:0] bufo_12_load_reg_4156;
reg [31:0] bufo_11_load_reg_4161;
reg [31:0] bufo_10_load_reg_4166;
reg [31:0] bufo_9_load_reg_4171;
reg [31:0] bufo_8_load_reg_4176;
reg [31:0] bufo_7_load_reg_4181;
reg [31:0] bufo_6_load_reg_4186;
reg [31:0] bufo_5_load_reg_4191;
reg [31:0] bufo_4_load_reg_4196;
reg [31:0] bufo_3_load_reg_4201;
reg [31:0] bufo_2_load_reg_4206;
reg [31:0] bufo_1_load_reg_4211;
reg [31:0] bufo_0_load_reg_4216;
reg [31:0] bufo_127_load_reg_4221;
reg [63:0] phi_mul_reg_2272;
wire ap_CS_fsm_state56;
reg [31:0] bufo_load_phi_reg_2296;
wire ap_CS_fsm_state46;
wire [31:0] bufw_Addr_A_orig;
wire [31:0] bufi_Addr_A_orig;
wire [31:0] bufo_126_Addr_A_orig;
wire [31:0] bufo_125_Addr_A_orig;
wire [31:0] bufo_124_Addr_A_orig;
wire [31:0] bufo_123_Addr_A_orig;
wire [31:0] bufo_122_Addr_A_orig;
wire [31:0] bufo_121_Addr_A_orig;
wire [31:0] bufo_120_Addr_A_orig;
wire [31:0] bufo_119_Addr_A_orig;
wire [31:0] bufo_118_Addr_A_orig;
wire [31:0] bufo_117_Addr_A_orig;
wire [31:0] bufo_116_Addr_A_orig;
wire [31:0] bufo_115_Addr_A_orig;
wire [31:0] bufo_114_Addr_A_orig;
wire [31:0] bufo_113_Addr_A_orig;
wire [31:0] bufo_112_Addr_A_orig;
wire [31:0] bufo_111_Addr_A_orig;
wire [31:0] bufo_110_Addr_A_orig;
wire [31:0] bufo_109_Addr_A_orig;
wire [31:0] bufo_108_Addr_A_orig;
wire [31:0] bufo_107_Addr_A_orig;
wire [31:0] bufo_106_Addr_A_orig;
wire [31:0] bufo_105_Addr_A_orig;
wire [31:0] bufo_104_Addr_A_orig;
wire [31:0] bufo_103_Addr_A_orig;
wire [31:0] bufo_102_Addr_A_orig;
wire [31:0] bufo_101_Addr_A_orig;
wire [31:0] bufo_100_Addr_A_orig;
wire [31:0] bufo_99_Addr_A_orig;
wire [31:0] bufo_98_Addr_A_orig;
wire [31:0] bufo_97_Addr_A_orig;
wire [31:0] bufo_96_Addr_A_orig;
wire [31:0] bufo_95_Addr_A_orig;
wire [31:0] bufo_94_Addr_A_orig;
wire [31:0] bufo_93_Addr_A_orig;
wire [31:0] bufo_92_Addr_A_orig;
wire [31:0] bufo_91_Addr_A_orig;
wire [31:0] bufo_90_Addr_A_orig;
wire [31:0] bufo_89_Addr_A_orig;
wire [31:0] bufo_88_Addr_A_orig;
wire [31:0] bufo_87_Addr_A_orig;
wire [31:0] bufo_86_Addr_A_orig;
wire [31:0] bufo_85_Addr_A_orig;
wire [31:0] bufo_84_Addr_A_orig;
wire [31:0] bufo_83_Addr_A_orig;
wire [31:0] bufo_82_Addr_A_orig;
wire [31:0] bufo_81_Addr_A_orig;
wire [31:0] bufo_80_Addr_A_orig;
wire [31:0] bufo_79_Addr_A_orig;
wire [31:0] bufo_78_Addr_A_orig;
wire [31:0] bufo_77_Addr_A_orig;
wire [31:0] bufo_76_Addr_A_orig;
wire [31:0] bufo_75_Addr_A_orig;
wire [31:0] bufo_74_Addr_A_orig;
wire [31:0] bufo_73_Addr_A_orig;
wire [31:0] bufo_72_Addr_A_orig;
wire [31:0] bufo_71_Addr_A_orig;
wire [31:0] bufo_70_Addr_A_orig;
wire [31:0] bufo_69_Addr_A_orig;
wire [31:0] bufo_68_Addr_A_orig;
wire [31:0] bufo_67_Addr_A_orig;
wire [31:0] bufo_66_Addr_A_orig;
wire [31:0] bufo_65_Addr_A_orig;
wire [31:0] bufo_64_Addr_A_orig;
wire [31:0] bufo_63_Addr_A_orig;
wire [31:0] bufo_62_Addr_A_orig;
wire [31:0] bufo_61_Addr_A_orig;
wire [31:0] bufo_60_Addr_A_orig;
wire [31:0] bufo_59_Addr_A_orig;
wire [31:0] bufo_58_Addr_A_orig;
wire [31:0] bufo_57_Addr_A_orig;
wire [31:0] bufo_56_Addr_A_orig;
wire [31:0] bufo_55_Addr_A_orig;
wire [31:0] bufo_54_Addr_A_orig;
wire [31:0] bufo_53_Addr_A_orig;
wire [31:0] bufo_52_Addr_A_orig;
wire [31:0] bufo_51_Addr_A_orig;
wire [31:0] bufo_50_Addr_A_orig;
wire [31:0] bufo_49_Addr_A_orig;
wire [31:0] bufo_48_Addr_A_orig;
wire [31:0] bufo_47_Addr_A_orig;
wire [31:0] bufo_46_Addr_A_orig;
wire [31:0] bufo_45_Addr_A_orig;
wire [31:0] bufo_44_Addr_A_orig;
wire [31:0] bufo_43_Addr_A_orig;
wire [31:0] bufo_42_Addr_A_orig;
wire [31:0] bufo_41_Addr_A_orig;
wire [31:0] bufo_40_Addr_A_orig;
wire [31:0] bufo_39_Addr_A_orig;
wire [31:0] bufo_38_Addr_A_orig;
wire [31:0] bufo_37_Addr_A_orig;
wire [31:0] bufo_36_Addr_A_orig;
wire [31:0] bufo_35_Addr_A_orig;
wire [31:0] bufo_34_Addr_A_orig;
wire [31:0] bufo_33_Addr_A_orig;
wire [31:0] bufo_32_Addr_A_orig;
wire [31:0] bufo_31_Addr_A_orig;
wire [31:0] bufo_30_Addr_A_orig;
wire [31:0] bufo_29_Addr_A_orig;
wire [31:0] bufo_28_Addr_A_orig;
wire [31:0] bufo_27_Addr_A_orig;
wire [31:0] bufo_26_Addr_A_orig;
wire [31:0] bufo_25_Addr_A_orig;
wire [31:0] bufo_24_Addr_A_orig;
wire [31:0] bufo_23_Addr_A_orig;
wire [31:0] bufo_22_Addr_A_orig;
wire [31:0] bufo_21_Addr_A_orig;
wire [31:0] bufo_20_Addr_A_orig;
wire [31:0] bufo_19_Addr_A_orig;
wire [31:0] bufo_18_Addr_A_orig;
wire [31:0] bufo_17_Addr_A_orig;
wire [31:0] bufo_16_Addr_A_orig;
wire [31:0] bufo_15_Addr_A_orig;
wire [31:0] bufo_14_Addr_A_orig;
wire [31:0] bufo_13_Addr_A_orig;
wire [31:0] bufo_12_Addr_A_orig;
wire [31:0] bufo_11_Addr_A_orig;
wire [31:0] bufo_10_Addr_A_orig;
wire [31:0] bufo_9_Addr_A_orig;
wire [31:0] bufo_8_Addr_A_orig;
wire [31:0] bufo_7_Addr_A_orig;
wire [31:0] bufo_6_Addr_A_orig;
wire [31:0] bufo_5_Addr_A_orig;
wire [31:0] bufo_4_Addr_A_orig;
wire [31:0] bufo_3_Addr_A_orig;
wire [31:0] bufo_2_Addr_A_orig;
wire [31:0] bufo_1_Addr_A_orig;
wire [31:0] bufo_0_Addr_A_orig;
wire [31:0] bufo_127_Addr_A_orig;
reg [31:0] grp_fu_2558_p0;
reg [31:0] grp_fu_2558_p1;
wire ap_CS_fsm_state9;
wire ap_CS_fsm_state18;
wire ap_CS_fsm_state27;
wire ap_CS_fsm_state36;
wire ap_CS_fsm_state47;
wire [31:0] grp_fu_2564_p0;
wire [31:0] grp_fu_2564_p1;
wire [31:0] grp_fu_2568_p0;
wire [31:0] grp_fu_2568_p1;
wire [31:0] grp_fu_2572_p0;
wire [31:0] grp_fu_2572_p1;
wire [31:0] grp_fu_2576_p0;
wire [31:0] grp_fu_2576_p1;
reg [55:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 56'd1;
end
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U1(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2558_p0),
.din1(grp_fu_2558_p1),
.ce(1'b1),
.dout(grp_fu_2558_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U2(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2564_p0),
.din1(grp_fu_2564_p1),
.ce(1'b1),
.dout(grp_fu_2564_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U3(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2568_p0),
.din1(grp_fu_2568_p1),
.ce(1'b1),
.dout(grp_fu_2568_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U4(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2572_p0),
.din1(grp_fu_2572_p1),
.ce(1'b1),
.dout(grp_fu_2572_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U5(
.clk(ap_clk),
.reset(ap_rst),
.din0(grp_fu_2576_p0),
.din1(grp_fu_2576_p1),
.ce(1'b1),
.dout(grp_fu_2576_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state46)) begin
if ((p_s_reg_2284 == 7'd127)) begin
bufo_load_phi_reg_2296 <= bufo_127_load_reg_4221;
end else if ((p_s_reg_2284 == 7'd126)) begin
bufo_load_phi_reg_2296 <= bufo_126_load_reg_3586;
end else if ((p_s_reg_2284 == 7'd125)) begin
bufo_load_phi_reg_2296 <= bufo_125_load_reg_3591;
end else if ((p_s_reg_2284 == 7'd124)) begin
bufo_load_phi_reg_2296 <= bufo_124_load_reg_3596;
end else if ((p_s_reg_2284 == 7'd123)) begin
bufo_load_phi_reg_2296 <= bufo_123_load_reg_3601;
end else if ((p_s_reg_2284 == 7'd122)) begin
bufo_load_phi_reg_2296 <= bufo_122_load_reg_3606;
end else if ((p_s_reg_2284 == 7'd121)) begin
bufo_load_phi_reg_2296 <= bufo_121_load_reg_3611;
end else if ((p_s_reg_2284 == 7'd120)) begin
bufo_load_phi_reg_2296 <= bufo_120_load_reg_3616;
end else if ((p_s_reg_2284 == 7'd119)) begin
bufo_load_phi_reg_2296 <= bufo_119_load_reg_3621;
end else if ((p_s_reg_2284 == 7'd118)) begin
bufo_load_phi_reg_2296 <= bufo_118_load_reg_3626;
end else if ((p_s_reg_2284 == 7'd117)) begin
bufo_load_phi_reg_2296 <= bufo_117_load_reg_3631;
end else if ((p_s_reg_2284 == 7'd116)) begin
bufo_load_phi_reg_2296 <= bufo_116_load_reg_3636;
end else if ((p_s_reg_2284 == 7'd115)) begin
bufo_load_phi_reg_2296 <= bufo_115_load_reg_3641;
end else if ((p_s_reg_2284 == 7'd114)) begin
bufo_load_phi_reg_2296 <= bufo_114_load_reg_3646;
end else if ((p_s_reg_2284 == 7'd113)) begin
bufo_load_phi_reg_2296 <= bufo_113_load_reg_3651;
end else if ((p_s_reg_2284 == 7'd112)) begin
bufo_load_phi_reg_2296 <= bufo_112_load_reg_3656;
end else if ((p_s_reg_2284 == 7'd111)) begin
bufo_load_phi_reg_2296 <= bufo_111_load_reg_3661;
end else if ((p_s_reg_2284 == 7'd110)) begin
bufo_load_phi_reg_2296 <= bufo_110_load_reg_3666;
end else if ((p_s_reg_2284 == 7'd109)) begin
bufo_load_phi_reg_2296 <= bufo_109_load_reg_3671;
end else if ((p_s_reg_2284 == 7'd108)) begin
bufo_load_phi_reg_2296 <= bufo_108_load_reg_3676;
end else if ((p_s_reg_2284 == 7'd107)) begin
bufo_load_phi_reg_2296 <= bufo_107_load_reg_3681;
end else if ((p_s_reg_2284 == 7'd106)) begin
bufo_load_phi_reg_2296 <= bufo_106_load_reg_3686;
end else if ((p_s_reg_2284 == 7'd105)) begin
bufo_load_phi_reg_2296 <= bufo_105_load_reg_3691;
end else if ((p_s_reg_2284 == 7'd104)) begin
bufo_load_phi_reg_2296 <= bufo_104_load_reg_3696;
end else if ((p_s_reg_2284 == 7'd103)) begin
bufo_load_phi_reg_2296 <= bufo_103_load_reg_3701;
end else if ((p_s_reg_2284 == 7'd102)) begin
bufo_load_phi_reg_2296 <= bufo_102_load_reg_3706;
end else if ((p_s_reg_2284 == 7'd101)) begin
bufo_load_phi_reg_2296 <= bufo_101_load_reg_3711;
end else if ((p_s_reg_2284 == 7'd100)) begin
bufo_load_phi_reg_2296 <= bufo_100_load_reg_3716;
end else if ((p_s_reg_2284 == 7'd99)) begin
bufo_load_phi_reg_2296 <= bufo_99_load_reg_3721;
end else if ((p_s_reg_2284 == 7'd98)) begin
bufo_load_phi_reg_2296 <= bufo_98_load_reg_3726;
end else if ((p_s_reg_2284 == 7'd97)) begin
bufo_load_phi_reg_2296 <= bufo_97_load_reg_3731;
end else if ((p_s_reg_2284 == 7'd96)) begin
bufo_load_phi_reg_2296 <= bufo_96_load_reg_3736;
end else if ((p_s_reg_2284 == 7'd95)) begin
bufo_load_phi_reg_2296 <= bufo_95_load_reg_3741;
end else if ((p_s_reg_2284 == 7'd94)) begin
bufo_load_phi_reg_2296 <= bufo_94_load_reg_3746;
end else if ((p_s_reg_2284 == 7'd93)) begin
bufo_load_phi_reg_2296 <= bufo_93_load_reg_3751;
end else if ((p_s_reg_2284 == 7'd92)) begin
bufo_load_phi_reg_2296 <= bufo_92_load_reg_3756;
end else if ((p_s_reg_2284 == 7'd91)) begin
bufo_load_phi_reg_2296 <= bufo_91_load_reg_3761;
end else if ((p_s_reg_2284 == 7'd90)) begin
bufo_load_phi_reg_2296 <= bufo_90_load_reg_3766;
end else if ((p_s_reg_2284 == 7'd89)) begin
bufo_load_phi_reg_2296 <= bufo_89_load_reg_3771;
end else if ((p_s_reg_2284 == 7'd88)) begin
bufo_load_phi_reg_2296 <= bufo_88_load_reg_3776;
end else if ((p_s_reg_2284 == 7'd87)) begin
bufo_load_phi_reg_2296 <= bufo_87_load_reg_3781;
end else if ((p_s_reg_2284 == 7'd86)) begin
bufo_load_phi_reg_2296 <= bufo_86_load_reg_3786;
end else if ((p_s_reg_2284 == 7'd85)) begin
bufo_load_phi_reg_2296 <= bufo_85_load_reg_3791;
end else if ((p_s_reg_2284 == 7'd84)) begin
bufo_load_phi_reg_2296 <= bufo_84_load_reg_3796;
end else if ((p_s_reg_2284 == 7'd83)) begin
bufo_load_phi_reg_2296 <= bufo_83_load_reg_3801;
end else if ((p_s_reg_2284 == 7'd82)) begin
bufo_load_phi_reg_2296 <= bufo_82_load_reg_3806;
end else if ((p_s_reg_2284 == 7'd81)) begin
bufo_load_phi_reg_2296 <= bufo_81_load_reg_3811;
end else if ((p_s_reg_2284 == 7'd80)) begin
bufo_load_phi_reg_2296 <= bufo_80_load_reg_3816;
end else if ((p_s_reg_2284 == 7'd79)) begin
bufo_load_phi_reg_2296 <= bufo_79_load_reg_3821;
end else if ((p_s_reg_2284 == 7'd78)) begin
bufo_load_phi_reg_2296 <= bufo_78_load_reg_3826;
end else if ((p_s_reg_2284 == 7'd77)) begin
bufo_load_phi_reg_2296 <= bufo_77_load_reg_3831;
end else if ((p_s_reg_2284 == 7'd76)) begin
bufo_load_phi_reg_2296 <= bufo_76_load_reg_3836;
end else if ((p_s_reg_2284 == 7'd75)) begin
bufo_load_phi_reg_2296 <= bufo_75_load_reg_3841;
end else if ((p_s_reg_2284 == 7'd74)) begin
bufo_load_phi_reg_2296 <= bufo_74_load_reg_3846;
end else if ((p_s_reg_2284 == 7'd73)) begin
bufo_load_phi_reg_2296 <= bufo_73_load_reg_3851;
end else if ((p_s_reg_2284 == 7'd72)) begin
bufo_load_phi_reg_2296 <= bufo_72_load_reg_3856;
end else if ((p_s_reg_2284 == 7'd71)) begin
bufo_load_phi_reg_2296 <= bufo_71_load_reg_3861;
end else if ((p_s_reg_2284 == 7'd70)) begin
bufo_load_phi_reg_2296 <= bufo_70_load_reg_3866;
end else if ((p_s_reg_2284 == 7'd69)) begin
bufo_load_phi_reg_2296 <= bufo_69_load_reg_3871;
end else if ((p_s_reg_2284 == 7'd68)) begin
bufo_load_phi_reg_2296 <= bufo_68_load_reg_3876;
end else if ((p_s_reg_2284 == 7'd67)) begin
bufo_load_phi_reg_2296 <= bufo_67_load_reg_3881;
end else if ((p_s_reg_2284 == 7'd66)) begin
bufo_load_phi_reg_2296 <= bufo_66_load_reg_3886;
end else if ((p_s_reg_2284 == 7'd65)) begin
bufo_load_phi_reg_2296 <= bufo_65_load_reg_3891;
end else if ((p_s_reg_2284 == 7'd64)) begin
bufo_load_phi_reg_2296 <= bufo_64_load_reg_3896;
end else if ((p_s_reg_2284 == 7'd63)) begin
bufo_load_phi_reg_2296 <= bufo_63_load_reg_3901;
end else if ((p_s_reg_2284 == 7'd62)) begin
bufo_load_phi_reg_2296 <= bufo_62_load_reg_3906;
end else if ((p_s_reg_2284 == 7'd61)) begin
bufo_load_phi_reg_2296 <= bufo_61_load_reg_3911;
end else if ((p_s_reg_2284 == 7'd60)) begin
bufo_load_phi_reg_2296 <= bufo_60_load_reg_3916;
end else if ((p_s_reg_2284 == 7'd59)) begin
bufo_load_phi_reg_2296 <= bufo_59_load_reg_3921;
end else if ((p_s_reg_2284 == 7'd58)) begin
bufo_load_phi_reg_2296 <= bufo_58_load_reg_3926;
end else if ((p_s_reg_2284 == 7'd57)) begin
bufo_load_phi_reg_2296 <= bufo_57_load_reg_3931;
end else if ((p_s_reg_2284 == 7'd56)) begin
bufo_load_phi_reg_2296 <= bufo_56_load_reg_3936;
end else if ((p_s_reg_2284 == 7'd55)) begin
bufo_load_phi_reg_2296 <= bufo_55_load_reg_3941;
end else if ((p_s_reg_2284 == 7'd54)) begin
bufo_load_phi_reg_2296 <= bufo_54_load_reg_3946;
end else if ((p_s_reg_2284 == 7'd53)) begin
bufo_load_phi_reg_2296 <= bufo_53_load_reg_3951;
end else if ((p_s_reg_2284 == 7'd52)) begin
bufo_load_phi_reg_2296 <= bufo_52_load_reg_3956;
end else if ((p_s_reg_2284 == 7'd51)) begin
bufo_load_phi_reg_2296 <= bufo_51_load_reg_3961;
end else if ((p_s_reg_2284 == 7'd50)) begin
bufo_load_phi_reg_2296 <= bufo_50_load_reg_3966;
end else if ((p_s_reg_2284 == 7'd49)) begin
bufo_load_phi_reg_2296 <= bufo_49_load_reg_3971;
end else if ((p_s_reg_2284 == 7'd48)) begin
bufo_load_phi_reg_2296 <= bufo_48_load_reg_3976;
end else if ((p_s_reg_2284 == 7'd47)) begin
bufo_load_phi_reg_2296 <= bufo_47_load_reg_3981;
end else if ((p_s_reg_2284 == 7'd46)) begin
bufo_load_phi_reg_2296 <= bufo_46_load_reg_3986;
end else if ((p_s_reg_2284 == 7'd45)) begin
bufo_load_phi_reg_2296 <= bufo_45_load_reg_3991;
end else if ((p_s_reg_2284 == 7'd44)) begin
bufo_load_phi_reg_2296 <= bufo_44_load_reg_3996;
end else if ((p_s_reg_2284 == 7'd43)) begin
bufo_load_phi_reg_2296 <= bufo_43_load_reg_4001;
end else if ((p_s_reg_2284 == 7'd42)) begin
bufo_load_phi_reg_2296 <= bufo_42_load_reg_4006;
end else if ((p_s_reg_2284 == 7'd41)) begin
bufo_load_phi_reg_2296 <= bufo_41_load_reg_4011;
end else if ((p_s_reg_2284 == 7'd40)) begin
bufo_load_phi_reg_2296 <= bufo_40_load_reg_4016;
end else if ((p_s_reg_2284 == 7'd39)) begin
bufo_load_phi_reg_2296 <= bufo_39_load_reg_4021;
end else if ((p_s_reg_2284 == 7'd38)) begin
bufo_load_phi_reg_2296 <= bufo_38_load_reg_4026;
end else if ((p_s_reg_2284 == 7'd37)) begin
bufo_load_phi_reg_2296 <= bufo_37_load_reg_4031;
end else if ((p_s_reg_2284 == 7'd36)) begin
bufo_load_phi_reg_2296 <= bufo_36_load_reg_4036;
end else if ((p_s_reg_2284 == 7'd35)) begin
bufo_load_phi_reg_2296 <= bufo_35_load_reg_4041;
end else if ((p_s_reg_2284 == 7'd34)) begin
bufo_load_phi_reg_2296 <= bufo_34_load_reg_4046;
end else if ((p_s_reg_2284 == 7'd33)) begin
bufo_load_phi_reg_2296 <= bufo_33_load_reg_4051;
end else if ((p_s_reg_2284 == 7'd32)) begin
bufo_load_phi_reg_2296 <= bufo_32_load_reg_4056;
end else if ((p_s_reg_2284 == 7'd31)) begin
bufo_load_phi_reg_2296 <= bufo_31_load_reg_4061;
end else if ((p_s_reg_2284 == 7'd30)) begin
bufo_load_phi_reg_2296 <= bufo_30_load_reg_4066;
end else if ((p_s_reg_2284 == 7'd29)) begin
bufo_load_phi_reg_2296 <= bufo_29_load_reg_4071;
end else if ((p_s_reg_2284 == 7'd28)) begin
bufo_load_phi_reg_2296 <= bufo_28_load_reg_4076;
end else if ((p_s_reg_2284 == 7'd27)) begin
bufo_load_phi_reg_2296 <= bufo_27_load_reg_4081;
end else if ((p_s_reg_2284 == 7'd26)) begin
bufo_load_phi_reg_2296 <= bufo_26_load_reg_4086;
end else if ((p_s_reg_2284 == 7'd25)) begin
bufo_load_phi_reg_2296 <= bufo_25_load_reg_4091;
end else if ((p_s_reg_2284 == 7'd24)) begin
bufo_load_phi_reg_2296 <= bufo_24_load_reg_4096;
end else if ((p_s_reg_2284 == 7'd23)) begin
bufo_load_phi_reg_2296 <= bufo_23_load_reg_4101;
end else if ((p_s_reg_2284 == 7'd22)) begin
bufo_load_phi_reg_2296 <= bufo_22_load_reg_4106;
end else if ((p_s_reg_2284 == 7'd21)) begin
bufo_load_phi_reg_2296 <= bufo_21_load_reg_4111;
end else if ((p_s_reg_2284 == 7'd20)) begin
bufo_load_phi_reg_2296 <= bufo_20_load_reg_4116;
end else if ((p_s_reg_2284 == 7'd19)) begin
bufo_load_phi_reg_2296 <= bufo_19_load_reg_4121;
end else if ((p_s_reg_2284 == 7'd18)) begin
bufo_load_phi_reg_2296 <= bufo_18_load_reg_4126;
end else if ((p_s_reg_2284 == 7'd17)) begin
bufo_load_phi_reg_2296 <= bufo_17_load_reg_4131;
end else if ((p_s_reg_2284 == 7'd16)) begin
bufo_load_phi_reg_2296 <= bufo_16_load_reg_4136;
end else if ((p_s_reg_2284 == 7'd15)) begin
bufo_load_phi_reg_2296 <= bufo_15_load_reg_4141;
end else if ((p_s_reg_2284 == 7'd14)) begin
bufo_load_phi_reg_2296 <= bufo_14_load_reg_4146;
end else if ((p_s_reg_2284 == 7'd13)) begin
bufo_load_phi_reg_2296 <= bufo_13_load_reg_4151;
end else if ((p_s_reg_2284 == 7'd12)) begin
bufo_load_phi_reg_2296 <= bufo_12_load_reg_4156;
end else if ((p_s_reg_2284 == 7'd11)) begin
bufo_load_phi_reg_2296 <= bufo_11_load_reg_4161;
end else if ((p_s_reg_2284 == 7'd10)) begin
bufo_load_phi_reg_2296 <= bufo_10_load_reg_4166;
end else if ((p_s_reg_2284 == 7'd9)) begin
bufo_load_phi_reg_2296 <= bufo_9_load_reg_4171;
end else if ((p_s_reg_2284 == 7'd8)) begin
bufo_load_phi_reg_2296 <= bufo_8_load_reg_4176;
end else if ((p_s_reg_2284 == 7'd7)) begin
bufo_load_phi_reg_2296 <= bufo_7_load_reg_4181;
end else if ((p_s_reg_2284 == 7'd6)) begin
bufo_load_phi_reg_2296 <= bufo_6_load_reg_4186;
end else if ((p_s_reg_2284 == 7'd5)) begin
bufo_load_phi_reg_2296 <= bufo_5_load_reg_4191;
end else if ((p_s_reg_2284 == 7'd4)) begin
bufo_load_phi_reg_2296 <= bufo_4_load_reg_4196;
end else if ((p_s_reg_2284 == 7'd3)) begin
bufo_load_phi_reg_2296 <= bufo_3_load_reg_4201;
end else if ((p_s_reg_2284 == 7'd2)) begin
bufo_load_phi_reg_2296 <= bufo_2_load_reg_4206;
end else if ((p_s_reg_2284 == 7'd1)) begin
bufo_load_phi_reg_2296 <= bufo_1_load_reg_4211;
end else if ((p_s_reg_2284 == 7'd0)) begin
bufo_load_phi_reg_2296 <= bufo_0_load_reg_4216;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state56)) begin
p_s_reg_2284 <= to_b_V_reg_3581;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
p_s_reg_2284 <= 7'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state56)) begin
phi_mul_reg_2272 <= next_mul_reg_3471;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
phi_mul_reg_2272 <= 64'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd0))) begin
bufo_0_load_reg_4216 <= bufo_0_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd100))) begin
bufo_100_load_reg_3716 <= bufo_100_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd101))) begin
bufo_101_load_reg_3711 <= bufo_101_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd102))) begin
bufo_102_load_reg_3706 <= bufo_102_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd103))) begin
bufo_103_load_reg_3701 <= bufo_103_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd104))) begin
bufo_104_load_reg_3696 <= bufo_104_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd105))) begin
bufo_105_load_reg_3691 <= bufo_105_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd106))) begin
bufo_106_load_reg_3686 <= bufo_106_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd107))) begin
bufo_107_load_reg_3681 <= bufo_107_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd108))) begin
bufo_108_load_reg_3676 <= bufo_108_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd109))) begin
bufo_109_load_reg_3671 <= bufo_109_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd10))) begin
bufo_10_load_reg_4166 <= bufo_10_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd110))) begin
bufo_110_load_reg_3666 <= bufo_110_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd111))) begin
bufo_111_load_reg_3661 <= bufo_111_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd112))) begin
bufo_112_load_reg_3656 <= bufo_112_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd113))) begin
bufo_113_load_reg_3651 <= bufo_113_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd114))) begin
bufo_114_load_reg_3646 <= bufo_114_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd115))) begin
bufo_115_load_reg_3641 <= bufo_115_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd116))) begin
bufo_116_load_reg_3636 <= bufo_116_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd117))) begin
bufo_117_load_reg_3631 <= bufo_117_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd118))) begin
bufo_118_load_reg_3626 <= bufo_118_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd119))) begin
bufo_119_load_reg_3621 <= bufo_119_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd11))) begin
bufo_11_load_reg_4161 <= bufo_11_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd120))) begin
bufo_120_load_reg_3616 <= bufo_120_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd121))) begin
bufo_121_load_reg_3611 <= bufo_121_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd122))) begin
bufo_122_load_reg_3606 <= bufo_122_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd123))) begin
bufo_123_load_reg_3601 <= bufo_123_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd124))) begin
bufo_124_load_reg_3596 <= bufo_124_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd125))) begin
bufo_125_load_reg_3591 <= bufo_125_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd126))) begin
bufo_126_load_reg_3586 <= bufo_126_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd127))) begin
bufo_127_load_reg_4221 <= bufo_127_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd12))) begin
bufo_12_load_reg_4156 <= bufo_12_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd13))) begin
bufo_13_load_reg_4151 <= bufo_13_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd14))) begin
bufo_14_load_reg_4146 <= bufo_14_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd15))) begin
bufo_15_load_reg_4141 <= bufo_15_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd16))) begin
bufo_16_load_reg_4136 <= bufo_16_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd17))) begin
bufo_17_load_reg_4131 <= bufo_17_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd18))) begin
bufo_18_load_reg_4126 <= bufo_18_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd19))) begin
bufo_19_load_reg_4121 <= bufo_19_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd1))) begin
bufo_1_load_reg_4211 <= bufo_1_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd20))) begin
bufo_20_load_reg_4116 <= bufo_20_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd21))) begin
bufo_21_load_reg_4111 <= bufo_21_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd22))) begin
bufo_22_load_reg_4106 <= bufo_22_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd23))) begin
bufo_23_load_reg_4101 <= bufo_23_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd24))) begin
bufo_24_load_reg_4096 <= bufo_24_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd25))) begin
bufo_25_load_reg_4091 <= bufo_25_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd26))) begin
bufo_26_load_reg_4086 <= bufo_26_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd27))) begin
bufo_27_load_reg_4081 <= bufo_27_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd28))) begin
bufo_28_load_reg_4076 <= bufo_28_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd29))) begin
bufo_29_load_reg_4071 <= bufo_29_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd2))) begin
bufo_2_load_reg_4206 <= bufo_2_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd30))) begin
bufo_30_load_reg_4066 <= bufo_30_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd31))) begin
bufo_31_load_reg_4061 <= bufo_31_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd32))) begin
bufo_32_load_reg_4056 <= bufo_32_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd33))) begin
bufo_33_load_reg_4051 <= bufo_33_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd34))) begin
bufo_34_load_reg_4046 <= bufo_34_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd35))) begin
bufo_35_load_reg_4041 <= bufo_35_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd36))) begin
bufo_36_load_reg_4036 <= bufo_36_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd37))) begin
bufo_37_load_reg_4031 <= bufo_37_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd38))) begin
bufo_38_load_reg_4026 <= bufo_38_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd39))) begin
bufo_39_load_reg_4021 <= bufo_39_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd3))) begin
bufo_3_load_reg_4201 <= bufo_3_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd40))) begin
bufo_40_load_reg_4016 <= bufo_40_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd41))) begin
bufo_41_load_reg_4011 <= bufo_41_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd42))) begin
bufo_42_load_reg_4006 <= bufo_42_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd43))) begin
bufo_43_load_reg_4001 <= bufo_43_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd44))) begin
bufo_44_load_reg_3996 <= bufo_44_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd45))) begin
bufo_45_load_reg_3991 <= bufo_45_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd46))) begin
bufo_46_load_reg_3986 <= bufo_46_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd47))) begin
bufo_47_load_reg_3981 <= bufo_47_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd48))) begin
bufo_48_load_reg_3976 <= bufo_48_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd49))) begin
bufo_49_load_reg_3971 <= bufo_49_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd4))) begin
bufo_4_load_reg_4196 <= bufo_4_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd50))) begin
bufo_50_load_reg_3966 <= bufo_50_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd51))) begin
bufo_51_load_reg_3961 <= bufo_51_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd52))) begin
bufo_52_load_reg_3956 <= bufo_52_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd53))) begin
bufo_53_load_reg_3951 <= bufo_53_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd54))) begin
bufo_54_load_reg_3946 <= bufo_54_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd55))) begin
bufo_55_load_reg_3941 <= bufo_55_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd56))) begin
bufo_56_load_reg_3936 <= bufo_56_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd57))) begin
bufo_57_load_reg_3931 <= bufo_57_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd58))) begin
bufo_58_load_reg_3926 <= bufo_58_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd59))) begin
bufo_59_load_reg_3921 <= bufo_59_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd5))) begin
bufo_5_load_reg_4191 <= bufo_5_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd60))) begin
bufo_60_load_reg_3916 <= bufo_60_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd61))) begin
bufo_61_load_reg_3911 <= bufo_61_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd62))) begin
bufo_62_load_reg_3906 <= bufo_62_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd63))) begin
bufo_63_load_reg_3901 <= bufo_63_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd64))) begin
bufo_64_load_reg_3896 <= bufo_64_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd65))) begin
bufo_65_load_reg_3891 <= bufo_65_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd66))) begin
bufo_66_load_reg_3886 <= bufo_66_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd67))) begin
bufo_67_load_reg_3881 <= bufo_67_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd68))) begin
bufo_68_load_reg_3876 <= bufo_68_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd69))) begin
bufo_69_load_reg_3871 <= bufo_69_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd6))) begin
bufo_6_load_reg_4186 <= bufo_6_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd70))) begin
bufo_70_load_reg_3866 <= bufo_70_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd71))) begin
bufo_71_load_reg_3861 <= bufo_71_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd72))) begin
bufo_72_load_reg_3856 <= bufo_72_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd73))) begin
bufo_73_load_reg_3851 <= bufo_73_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd74))) begin
bufo_74_load_reg_3846 <= bufo_74_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd75))) begin
bufo_75_load_reg_3841 <= bufo_75_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd76))) begin
bufo_76_load_reg_3836 <= bufo_76_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd77))) begin
bufo_77_load_reg_3831 <= bufo_77_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd78))) begin
bufo_78_load_reg_3826 <= bufo_78_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd79))) begin
bufo_79_load_reg_3821 <= bufo_79_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd7))) begin
bufo_7_load_reg_4181 <= bufo_7_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd80))) begin
bufo_80_load_reg_3816 <= bufo_80_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd81))) begin
bufo_81_load_reg_3811 <= bufo_81_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd82))) begin
bufo_82_load_reg_3806 <= bufo_82_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd83))) begin
bufo_83_load_reg_3801 <= bufo_83_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd84))) begin
bufo_84_load_reg_3796 <= bufo_84_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd85))) begin
bufo_85_load_reg_3791 <= bufo_85_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd86))) begin
bufo_86_load_reg_3786 <= bufo_86_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd87))) begin
bufo_87_load_reg_3781 <= bufo_87_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd88))) begin
bufo_88_load_reg_3776 <= bufo_88_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd89))) begin
bufo_89_load_reg_3771 <= bufo_89_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd8))) begin
bufo_8_load_reg_4176 <= bufo_8_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd90))) begin
bufo_90_load_reg_3766 <= bufo_90_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd91))) begin
bufo_91_load_reg_3761 <= bufo_91_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd92))) begin
bufo_92_load_reg_3756 <= bufo_92_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd93))) begin
bufo_93_load_reg_3751 <= bufo_93_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd94))) begin
bufo_94_load_reg_3746 <= bufo_94_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd95))) begin
bufo_95_load_reg_3741 <= bufo_95_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd96))) begin
bufo_96_load_reg_3736 <= bufo_96_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd97))) begin
bufo_97_load_reg_3731 <= bufo_97_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd98))) begin
bufo_98_load_reg_3726 <= bufo_98_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd99))) begin
bufo_99_load_reg_3721 <= bufo_99_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state45) & (p_s_reg_2284 == 7'd9))) begin
bufo_9_load_reg_4171 <= bufo_9_Dout_A;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
next_mul_reg_3471 <= next_mul_fu_2714_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state35) | (1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state55))) begin
reg_2580 <= grp_fu_2558_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
tmp_11_reg_3506 <= {{bufi_Dout_A[95:64]}};
tmp_13_reg_3511 <= {{bufw_Dout_A[127:96]}};
tmp_15_reg_3516 <= {{bufi_Dout_A[127:96]}};
tmp_1_reg_3486 <= tmp_1_fu_2724_p1;
tmp_4_reg_3501 <= {{bufw_Dout_A[95:64]}};
tmp_6_reg_3491 <= {{bufw_Dout_A[63:32]}};
tmp_8_reg_3496 <= {{bufi_Dout_A[63:32]}};
tmp_reg_3481 <= tmp_fu_2720_p1;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state8)) begin
tmp_5_1_reg_3566 <= grp_fu_2568_p2;
tmp_5_2_reg_3571 <= grp_fu_2572_p2;
tmp_5_3_reg_3576 <= grp_fu_2576_p2;
tmp_s_reg_3561 <= grp_fu_2564_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state44)) begin
to_b_V_reg_3581 <= to_b_V_fu_2820_p2;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
bufi_EN_A = 1'b1;
end else begin
bufi_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_0_EN_A = 1'b1;
end else begin
bufo_0_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd0) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_0_WEN_A = 4'd15;
end else begin
bufo_0_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_100_EN_A = 1'b1;
end else begin
bufo_100_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd100) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_100_WEN_A = 4'd15;
end else begin
bufo_100_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_101_EN_A = 1'b1;
end else begin
bufo_101_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd101) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_101_WEN_A = 4'd15;
end else begin
bufo_101_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_102_EN_A = 1'b1;
end else begin
bufo_102_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd102) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_102_WEN_A = 4'd15;
end else begin
bufo_102_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_103_EN_A = 1'b1;
end else begin
bufo_103_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd103) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_103_WEN_A = 4'd15;
end else begin
bufo_103_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_104_EN_A = 1'b1;
end else begin
bufo_104_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd104) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_104_WEN_A = 4'd15;
end else begin
bufo_104_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_105_EN_A = 1'b1;
end else begin
bufo_105_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd105) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_105_WEN_A = 4'd15;
end else begin
bufo_105_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_106_EN_A = 1'b1;
end else begin
bufo_106_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd106) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_106_WEN_A = 4'd15;
end else begin
bufo_106_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_107_EN_A = 1'b1;
end else begin
bufo_107_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd107) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_107_WEN_A = 4'd15;
end else begin
bufo_107_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_108_EN_A = 1'b1;
end else begin
bufo_108_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd108) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_108_WEN_A = 4'd15;
end else begin
bufo_108_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_109_EN_A = 1'b1;
end else begin
bufo_109_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd109) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_109_WEN_A = 4'd15;
end else begin
bufo_109_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_10_EN_A = 1'b1;
end else begin
bufo_10_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd10) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_10_WEN_A = 4'd15;
end else begin
bufo_10_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_110_EN_A = 1'b1;
end else begin
bufo_110_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd110) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_110_WEN_A = 4'd15;
end else begin
bufo_110_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_111_EN_A = 1'b1;
end else begin
bufo_111_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd111) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_111_WEN_A = 4'd15;
end else begin
bufo_111_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_112_EN_A = 1'b1;
end else begin
bufo_112_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd112) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_112_WEN_A = 4'd15;
end else begin
bufo_112_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_113_EN_A = 1'b1;
end else begin
bufo_113_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd113) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_113_WEN_A = 4'd15;
end else begin
bufo_113_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_114_EN_A = 1'b1;
end else begin
bufo_114_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd114) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_114_WEN_A = 4'd15;
end else begin
bufo_114_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_115_EN_A = 1'b1;
end else begin
bufo_115_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd115) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_115_WEN_A = 4'd15;
end else begin
bufo_115_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_116_EN_A = 1'b1;
end else begin
bufo_116_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd116) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_116_WEN_A = 4'd15;
end else begin
bufo_116_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_117_EN_A = 1'b1;
end else begin
bufo_117_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd117) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_117_WEN_A = 4'd15;
end else begin
bufo_117_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_118_EN_A = 1'b1;
end else begin
bufo_118_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd118) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_118_WEN_A = 4'd15;
end else begin
bufo_118_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_119_EN_A = 1'b1;
end else begin
bufo_119_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd119) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_119_WEN_A = 4'd15;
end else begin
bufo_119_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_11_EN_A = 1'b1;
end else begin
bufo_11_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd11) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_11_WEN_A = 4'd15;
end else begin
bufo_11_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_120_EN_A = 1'b1;
end else begin
bufo_120_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd120) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_120_WEN_A = 4'd15;
end else begin
bufo_120_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_121_EN_A = 1'b1;
end else begin
bufo_121_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd121) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_121_WEN_A = 4'd15;
end else begin
bufo_121_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_122_EN_A = 1'b1;
end else begin
bufo_122_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd122) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_122_WEN_A = 4'd15;
end else begin
bufo_122_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_123_EN_A = 1'b1;
end else begin
bufo_123_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd123) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_123_WEN_A = 4'd15;
end else begin
bufo_123_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_124_EN_A = 1'b1;
end else begin
bufo_124_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd124) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_124_WEN_A = 4'd15;
end else begin
bufo_124_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_125_EN_A = 1'b1;
end else begin
bufo_125_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd125) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_125_WEN_A = 4'd15;
end else begin
bufo_125_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_126_EN_A = 1'b1;
end else begin
bufo_126_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd126) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_126_WEN_A = 4'd15;
end else begin
bufo_126_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_127_EN_A = 1'b1;
end else begin
bufo_127_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd127) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_127_WEN_A = 4'd15;
end else begin
bufo_127_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_12_EN_A = 1'b1;
end else begin
bufo_12_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd12) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_12_WEN_A = 4'd15;
end else begin
bufo_12_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_13_EN_A = 1'b1;
end else begin
bufo_13_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd13) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_13_WEN_A = 4'd15;
end else begin
bufo_13_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_14_EN_A = 1'b1;
end else begin
bufo_14_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd14) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_14_WEN_A = 4'd15;
end else begin
bufo_14_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_15_EN_A = 1'b1;
end else begin
bufo_15_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd15) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_15_WEN_A = 4'd15;
end else begin
bufo_15_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_16_EN_A = 1'b1;
end else begin
bufo_16_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd16) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_16_WEN_A = 4'd15;
end else begin
bufo_16_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_17_EN_A = 1'b1;
end else begin
bufo_17_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd17) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_17_WEN_A = 4'd15;
end else begin
bufo_17_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_18_EN_A = 1'b1;
end else begin
bufo_18_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd18) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_18_WEN_A = 4'd15;
end else begin
bufo_18_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_19_EN_A = 1'b1;
end else begin
bufo_19_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd19) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_19_WEN_A = 4'd15;
end else begin
bufo_19_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_1_EN_A = 1'b1;
end else begin
bufo_1_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd1) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_1_WEN_A = 4'd15;
end else begin
bufo_1_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_20_EN_A = 1'b1;
end else begin
bufo_20_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd20) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_20_WEN_A = 4'd15;
end else begin
bufo_20_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_21_EN_A = 1'b1;
end else begin
bufo_21_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd21) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_21_WEN_A = 4'd15;
end else begin
bufo_21_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_22_EN_A = 1'b1;
end else begin
bufo_22_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd22) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_22_WEN_A = 4'd15;
end else begin
bufo_22_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_23_EN_A = 1'b1;
end else begin
bufo_23_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd23) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_23_WEN_A = 4'd15;
end else begin
bufo_23_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_24_EN_A = 1'b1;
end else begin
bufo_24_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd24) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_24_WEN_A = 4'd15;
end else begin
bufo_24_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_25_EN_A = 1'b1;
end else begin
bufo_25_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd25) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_25_WEN_A = 4'd15;
end else begin
bufo_25_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_26_EN_A = 1'b1;
end else begin
bufo_26_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd26) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_26_WEN_A = 4'd15;
end else begin
bufo_26_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_27_EN_A = 1'b1;
end else begin
bufo_27_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd27) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_27_WEN_A = 4'd15;
end else begin
bufo_27_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_28_EN_A = 1'b1;
end else begin
bufo_28_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd28) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_28_WEN_A = 4'd15;
end else begin
bufo_28_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_29_EN_A = 1'b1;
end else begin
bufo_29_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd29) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_29_WEN_A = 4'd15;
end else begin
bufo_29_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_2_EN_A = 1'b1;
end else begin
bufo_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd2) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_2_WEN_A = 4'd15;
end else begin
bufo_2_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_30_EN_A = 1'b1;
end else begin
bufo_30_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd30) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_30_WEN_A = 4'd15;
end else begin
bufo_30_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_31_EN_A = 1'b1;
end else begin
bufo_31_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd31) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_31_WEN_A = 4'd15;
end else begin
bufo_31_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_32_EN_A = 1'b1;
end else begin
bufo_32_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd32) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_32_WEN_A = 4'd15;
end else begin
bufo_32_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_33_EN_A = 1'b1;
end else begin
bufo_33_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd33) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_33_WEN_A = 4'd15;
end else begin
bufo_33_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_34_EN_A = 1'b1;
end else begin
bufo_34_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd34) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_34_WEN_A = 4'd15;
end else begin
bufo_34_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_35_EN_A = 1'b1;
end else begin
bufo_35_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd35) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_35_WEN_A = 4'd15;
end else begin
bufo_35_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_36_EN_A = 1'b1;
end else begin
bufo_36_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd36) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_36_WEN_A = 4'd15;
end else begin
bufo_36_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_37_EN_A = 1'b1;
end else begin
bufo_37_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd37) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_37_WEN_A = 4'd15;
end else begin
bufo_37_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_38_EN_A = 1'b1;
end else begin
bufo_38_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd38) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_38_WEN_A = 4'd15;
end else begin
bufo_38_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_39_EN_A = 1'b1;
end else begin
bufo_39_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd39) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_39_WEN_A = 4'd15;
end else begin
bufo_39_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_3_EN_A = 1'b1;
end else begin
bufo_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd3) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_3_WEN_A = 4'd15;
end else begin
bufo_3_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_40_EN_A = 1'b1;
end else begin
bufo_40_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd40) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_40_WEN_A = 4'd15;
end else begin
bufo_40_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_41_EN_A = 1'b1;
end else begin
bufo_41_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd41) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_41_WEN_A = 4'd15;
end else begin
bufo_41_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_42_EN_A = 1'b1;
end else begin
bufo_42_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd42) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_42_WEN_A = 4'd15;
end else begin
bufo_42_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_43_EN_A = 1'b1;
end else begin
bufo_43_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd43) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_43_WEN_A = 4'd15;
end else begin
bufo_43_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_44_EN_A = 1'b1;
end else begin
bufo_44_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd44) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_44_WEN_A = 4'd15;
end else begin
bufo_44_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_45_EN_A = 1'b1;
end else begin
bufo_45_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd45) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_45_WEN_A = 4'd15;
end else begin
bufo_45_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_46_EN_A = 1'b1;
end else begin
bufo_46_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd46) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_46_WEN_A = 4'd15;
end else begin
bufo_46_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_47_EN_A = 1'b1;
end else begin
bufo_47_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd47) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_47_WEN_A = 4'd15;
end else begin
bufo_47_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_48_EN_A = 1'b1;
end else begin
bufo_48_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd48) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_48_WEN_A = 4'd15;
end else begin
bufo_48_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_49_EN_A = 1'b1;
end else begin
bufo_49_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd49) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_49_WEN_A = 4'd15;
end else begin
bufo_49_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_4_EN_A = 1'b1;
end else begin
bufo_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd4) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_4_WEN_A = 4'd15;
end else begin
bufo_4_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_50_EN_A = 1'b1;
end else begin
bufo_50_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd50) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_50_WEN_A = 4'd15;
end else begin
bufo_50_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_51_EN_A = 1'b1;
end else begin
bufo_51_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd51) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_51_WEN_A = 4'd15;
end else begin
bufo_51_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_52_EN_A = 1'b1;
end else begin
bufo_52_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd52) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_52_WEN_A = 4'd15;
end else begin
bufo_52_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_53_EN_A = 1'b1;
end else begin
bufo_53_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd53) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_53_WEN_A = 4'd15;
end else begin
bufo_53_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_54_EN_A = 1'b1;
end else begin
bufo_54_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd54) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_54_WEN_A = 4'd15;
end else begin
bufo_54_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_55_EN_A = 1'b1;
end else begin
bufo_55_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd55) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_55_WEN_A = 4'd15;
end else begin
bufo_55_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_56_EN_A = 1'b1;
end else begin
bufo_56_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd56) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_56_WEN_A = 4'd15;
end else begin
bufo_56_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_57_EN_A = 1'b1;
end else begin
bufo_57_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd57) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_57_WEN_A = 4'd15;
end else begin
bufo_57_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_58_EN_A = 1'b1;
end else begin
bufo_58_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd58) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_58_WEN_A = 4'd15;
end else begin
bufo_58_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_59_EN_A = 1'b1;
end else begin
bufo_59_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd59) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_59_WEN_A = 4'd15;
end else begin
bufo_59_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_5_EN_A = 1'b1;
end else begin
bufo_5_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd5) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_5_WEN_A = 4'd15;
end else begin
bufo_5_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_60_EN_A = 1'b1;
end else begin
bufo_60_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd60) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_60_WEN_A = 4'd15;
end else begin
bufo_60_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_61_EN_A = 1'b1;
end else begin
bufo_61_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd61) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_61_WEN_A = 4'd15;
end else begin
bufo_61_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_62_EN_A = 1'b1;
end else begin
bufo_62_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd62) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_62_WEN_A = 4'd15;
end else begin
bufo_62_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_63_EN_A = 1'b1;
end else begin
bufo_63_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd63) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_63_WEN_A = 4'd15;
end else begin
bufo_63_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_64_EN_A = 1'b1;
end else begin
bufo_64_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd64) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_64_WEN_A = 4'd15;
end else begin
bufo_64_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_65_EN_A = 1'b1;
end else begin
bufo_65_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd65) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_65_WEN_A = 4'd15;
end else begin
bufo_65_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_66_EN_A = 1'b1;
end else begin
bufo_66_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd66) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_66_WEN_A = 4'd15;
end else begin
bufo_66_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_67_EN_A = 1'b1;
end else begin
bufo_67_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd67) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_67_WEN_A = 4'd15;
end else begin
bufo_67_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_68_EN_A = 1'b1;
end else begin
bufo_68_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd68) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_68_WEN_A = 4'd15;
end else begin
bufo_68_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_69_EN_A = 1'b1;
end else begin
bufo_69_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd69) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_69_WEN_A = 4'd15;
end else begin
bufo_69_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_6_EN_A = 1'b1;
end else begin
bufo_6_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd6) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_6_WEN_A = 4'd15;
end else begin
bufo_6_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_70_EN_A = 1'b1;
end else begin
bufo_70_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd70) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_70_WEN_A = 4'd15;
end else begin
bufo_70_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_71_EN_A = 1'b1;
end else begin
bufo_71_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd71) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_71_WEN_A = 4'd15;
end else begin
bufo_71_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_72_EN_A = 1'b1;
end else begin
bufo_72_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd72) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_72_WEN_A = 4'd15;
end else begin
bufo_72_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_73_EN_A = 1'b1;
end else begin
bufo_73_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd73) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_73_WEN_A = 4'd15;
end else begin
bufo_73_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_74_EN_A = 1'b1;
end else begin
bufo_74_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd74) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_74_WEN_A = 4'd15;
end else begin
bufo_74_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_75_EN_A = 1'b1;
end else begin
bufo_75_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd75) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_75_WEN_A = 4'd15;
end else begin
bufo_75_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_76_EN_A = 1'b1;
end else begin
bufo_76_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd76) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_76_WEN_A = 4'd15;
end else begin
bufo_76_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_77_EN_A = 1'b1;
end else begin
bufo_77_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd77) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_77_WEN_A = 4'd15;
end else begin
bufo_77_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_78_EN_A = 1'b1;
end else begin
bufo_78_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd78) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_78_WEN_A = 4'd15;
end else begin
bufo_78_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_79_EN_A = 1'b1;
end else begin
bufo_79_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd79) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_79_WEN_A = 4'd15;
end else begin
bufo_79_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_7_EN_A = 1'b1;
end else begin
bufo_7_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd7) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_7_WEN_A = 4'd15;
end else begin
bufo_7_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_80_EN_A = 1'b1;
end else begin
bufo_80_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd80) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_80_WEN_A = 4'd15;
end else begin
bufo_80_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_81_EN_A = 1'b1;
end else begin
bufo_81_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd81) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_81_WEN_A = 4'd15;
end else begin
bufo_81_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_82_EN_A = 1'b1;
end else begin
bufo_82_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd82) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_82_WEN_A = 4'd15;
end else begin
bufo_82_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_83_EN_A = 1'b1;
end else begin
bufo_83_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd83) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_83_WEN_A = 4'd15;
end else begin
bufo_83_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_84_EN_A = 1'b1;
end else begin
bufo_84_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd84) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_84_WEN_A = 4'd15;
end else begin
bufo_84_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_85_EN_A = 1'b1;
end else begin
bufo_85_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd85) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_85_WEN_A = 4'd15;
end else begin
bufo_85_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_86_EN_A = 1'b1;
end else begin
bufo_86_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd86) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_86_WEN_A = 4'd15;
end else begin
bufo_86_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_87_EN_A = 1'b1;
end else begin
bufo_87_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd87) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_87_WEN_A = 4'd15;
end else begin
bufo_87_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_88_EN_A = 1'b1;
end else begin
bufo_88_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd88) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_88_WEN_A = 4'd15;
end else begin
bufo_88_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_89_EN_A = 1'b1;
end else begin
bufo_89_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd89) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_89_WEN_A = 4'd15;
end else begin
bufo_89_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_8_EN_A = 1'b1;
end else begin
bufo_8_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd8) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_8_WEN_A = 4'd15;
end else begin
bufo_8_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_90_EN_A = 1'b1;
end else begin
bufo_90_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd90) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_90_WEN_A = 4'd15;
end else begin
bufo_90_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_91_EN_A = 1'b1;
end else begin
bufo_91_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd91) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_91_WEN_A = 4'd15;
end else begin
bufo_91_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_92_EN_A = 1'b1;
end else begin
bufo_92_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd92) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_92_WEN_A = 4'd15;
end else begin
bufo_92_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_93_EN_A = 1'b1;
end else begin
bufo_93_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd93) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_93_WEN_A = 4'd15;
end else begin
bufo_93_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_94_EN_A = 1'b1;
end else begin
bufo_94_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd94) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_94_WEN_A = 4'd15;
end else begin
bufo_94_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_95_EN_A = 1'b1;
end else begin
bufo_95_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd95) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_95_WEN_A = 4'd15;
end else begin
bufo_95_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_96_EN_A = 1'b1;
end else begin
bufo_96_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd96) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_96_WEN_A = 4'd15;
end else begin
bufo_96_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_97_EN_A = 1'b1;
end else begin
bufo_97_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd97) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_97_WEN_A = 4'd15;
end else begin
bufo_97_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_98_EN_A = 1'b1;
end else begin
bufo_98_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd98) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_98_WEN_A = 4'd15;
end else begin
bufo_98_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_99_EN_A = 1'b1;
end else begin
bufo_99_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd99) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_99_WEN_A = 4'd15;
end else begin
bufo_99_WEN_A = 4'd0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state56))) begin
bufo_9_EN_A = 1'b1;
end else begin
bufo_9_EN_A = 1'b0;
end
end
always @ (*) begin
if (((p_s_reg_2284 == 7'd9) & (1'b1 == ap_CS_fsm_state56))) begin
bufo_9_WEN_A = 4'd15;
end else begin
bufo_9_WEN_A = 4'd0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
bufw_EN_A = 1'b1;
end else begin
bufw_EN_A = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state47)) begin
grp_fu_2558_p0 = bufo_load_phi_reg_2296;
end else if (((1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state36))) begin
grp_fu_2558_p0 = reg_2580;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
grp_fu_2558_p0 = tmp_s_reg_3561;
end else begin
grp_fu_2558_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state47)) begin
grp_fu_2558_p1 = reg_2580;
end else if ((1'b1 == ap_CS_fsm_state36)) begin
grp_fu_2558_p1 = tmp_5_3_reg_3576;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
grp_fu_2558_p1 = tmp_5_2_reg_3571;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
grp_fu_2558_p1 = tmp_5_1_reg_3566;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
grp_fu_2558_p1 = 32'd0;
end else begin
grp_fu_2558_p1 = 'bx;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state6;
end
ap_ST_fsm_state6 : begin
ap_NS_fsm = ap_ST_fsm_state7;
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_state8;
end
ap_ST_fsm_state8 : begin
ap_NS_fsm = ap_ST_fsm_state9;
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state10;
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state11;
end
ap_ST_fsm_state11 : begin
ap_NS_fsm = ap_ST_fsm_state12;
end
ap_ST_fsm_state12 : begin
ap_NS_fsm = ap_ST_fsm_state13;
end
ap_ST_fsm_state13 : begin
ap_NS_fsm = ap_ST_fsm_state14;
end
ap_ST_fsm_state14 : begin
ap_NS_fsm = ap_ST_fsm_state15;
end
ap_ST_fsm_state15 : begin
ap_NS_fsm = ap_ST_fsm_state16;
end
ap_ST_fsm_state16 : begin
ap_NS_fsm = ap_ST_fsm_state17;
end
ap_ST_fsm_state17 : begin
ap_NS_fsm = ap_ST_fsm_state18;
end
ap_ST_fsm_state18 : begin
ap_NS_fsm = ap_ST_fsm_state19;
end
ap_ST_fsm_state19 : begin
ap_NS_fsm = ap_ST_fsm_state20;
end
ap_ST_fsm_state20 : begin
ap_NS_fsm = ap_ST_fsm_state21;
end
ap_ST_fsm_state21 : begin
ap_NS_fsm = ap_ST_fsm_state22;
end
ap_ST_fsm_state22 : begin
ap_NS_fsm = ap_ST_fsm_state23;
end
ap_ST_fsm_state23 : begin
ap_NS_fsm = ap_ST_fsm_state24;
end
ap_ST_fsm_state24 : begin
ap_NS_fsm = ap_ST_fsm_state25;
end
ap_ST_fsm_state25 : begin
ap_NS_fsm = ap_ST_fsm_state26;
end
ap_ST_fsm_state26 : begin
ap_NS_fsm = ap_ST_fsm_state27;
end
ap_ST_fsm_state27 : begin
ap_NS_fsm = ap_ST_fsm_state28;
end
ap_ST_fsm_state28 : begin
ap_NS_fsm = ap_ST_fsm_state29;
end
ap_ST_fsm_state29 : begin
ap_NS_fsm = ap_ST_fsm_state30;
end
ap_ST_fsm_state30 : begin
ap_NS_fsm = ap_ST_fsm_state31;
end
ap_ST_fsm_state31 : begin
ap_NS_fsm = ap_ST_fsm_state32;
end
ap_ST_fsm_state32 : begin
ap_NS_fsm = ap_ST_fsm_state33;
end
ap_ST_fsm_state33 : begin
ap_NS_fsm = ap_ST_fsm_state34;
end
ap_ST_fsm_state34 : begin
ap_NS_fsm = ap_ST_fsm_state35;
end
ap_ST_fsm_state35 : begin
ap_NS_fsm = ap_ST_fsm_state36;
end
ap_ST_fsm_state36 : begin
ap_NS_fsm = ap_ST_fsm_state37;
end
ap_ST_fsm_state37 : begin
ap_NS_fsm = ap_ST_fsm_state38;
end
ap_ST_fsm_state38 : begin
ap_NS_fsm = ap_ST_fsm_state39;
end
ap_ST_fsm_state39 : begin
ap_NS_fsm = ap_ST_fsm_state40;
end
ap_ST_fsm_state40 : begin
ap_NS_fsm = ap_ST_fsm_state41;
end
ap_ST_fsm_state41 : begin
ap_NS_fsm = ap_ST_fsm_state42;
end
ap_ST_fsm_state42 : begin
ap_NS_fsm = ap_ST_fsm_state43;
end
ap_ST_fsm_state43 : begin
ap_NS_fsm = ap_ST_fsm_state44;
end
ap_ST_fsm_state44 : begin
ap_NS_fsm = ap_ST_fsm_state45;
end
ap_ST_fsm_state45 : begin
ap_NS_fsm = ap_ST_fsm_state46;
end
ap_ST_fsm_state46 : begin
ap_NS_fsm = ap_ST_fsm_state47;
end
ap_ST_fsm_state47 : begin
ap_NS_fsm = ap_ST_fsm_state48;
end
ap_ST_fsm_state48 : begin
ap_NS_fsm = ap_ST_fsm_state49;
end
ap_ST_fsm_state49 : begin
ap_NS_fsm = ap_ST_fsm_state50;
end
ap_ST_fsm_state50 : begin
ap_NS_fsm = ap_ST_fsm_state51;
end
ap_ST_fsm_state51 : begin
ap_NS_fsm = ap_ST_fsm_state52;
end
ap_ST_fsm_state52 : begin
ap_NS_fsm = ap_ST_fsm_state53;
end
ap_ST_fsm_state53 : begin
ap_NS_fsm = ap_ST_fsm_state54;
end
ap_ST_fsm_state54 : begin
ap_NS_fsm = ap_ST_fsm_state55;
end
ap_ST_fsm_state55 : begin
ap_NS_fsm = ap_ST_fsm_state56;
end
ap_ST_fsm_state56 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16];
assign ap_CS_fsm_state18 = ap_CS_fsm[32'd17];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state26 = ap_CS_fsm[32'd25];
assign ap_CS_fsm_state27 = ap_CS_fsm[32'd26];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state35 = ap_CS_fsm[32'd34];
assign ap_CS_fsm_state36 = ap_CS_fsm[32'd35];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state44 = ap_CS_fsm[32'd43];
assign ap_CS_fsm_state45 = ap_CS_fsm[32'd44];
assign ap_CS_fsm_state46 = ap_CS_fsm[32'd45];
assign ap_CS_fsm_state47 = ap_CS_fsm[32'd46];
assign ap_CS_fsm_state55 = ap_CS_fsm[32'd54];
assign ap_CS_fsm_state56 = ap_CS_fsm[32'd55];
assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8];
assign ap_done = 1'b0;
assign ap_ready = 1'b0;
assign bufi_Addr_A = bufi_Addr_A_orig << 32'd4;
assign bufi_Addr_A_orig = 64'd0;
assign bufi_Clk_A = ap_clk;
assign bufi_Din_A = 128'd0;
assign bufi_Rst_A = ap_rst;
assign bufi_WEN_A = 16'd0;
assign bufo_0_Addr_A = bufo_0_Addr_A_orig << 32'd2;
assign bufo_0_Addr_A_orig = 64'd0;
assign bufo_0_Clk_A = ap_clk;
assign bufo_0_Din_A = reg_2580;
assign bufo_0_Rst_A = ap_rst;
assign bufo_100_Addr_A = bufo_100_Addr_A_orig << 32'd2;
assign bufo_100_Addr_A_orig = 64'd0;
assign bufo_100_Clk_A = ap_clk;
assign bufo_100_Din_A = reg_2580;
assign bufo_100_Rst_A = ap_rst;
assign bufo_101_Addr_A = bufo_101_Addr_A_orig << 32'd2;
assign bufo_101_Addr_A_orig = 64'd0;
assign bufo_101_Clk_A = ap_clk;
assign bufo_101_Din_A = reg_2580;
assign bufo_101_Rst_A = ap_rst;
assign bufo_102_Addr_A = bufo_102_Addr_A_orig << 32'd2;
assign bufo_102_Addr_A_orig = 64'd0;
assign bufo_102_Clk_A = ap_clk;
assign bufo_102_Din_A = reg_2580;
assign bufo_102_Rst_A = ap_rst;
assign bufo_103_Addr_A = bufo_103_Addr_A_orig << 32'd2;
assign bufo_103_Addr_A_orig = 64'd0;
assign bufo_103_Clk_A = ap_clk;
assign bufo_103_Din_A = reg_2580;
assign bufo_103_Rst_A = ap_rst;
assign bufo_104_Addr_A = bufo_104_Addr_A_orig << 32'd2;
assign bufo_104_Addr_A_orig = 64'd0;
assign bufo_104_Clk_A = ap_clk;
assign bufo_104_Din_A = reg_2580;
assign bufo_104_Rst_A = ap_rst;
assign bufo_105_Addr_A = bufo_105_Addr_A_orig << 32'd2;
assign bufo_105_Addr_A_orig = 64'd0;
assign bufo_105_Clk_A = ap_clk;
assign bufo_105_Din_A = reg_2580;
assign bufo_105_Rst_A = ap_rst;
assign bufo_106_Addr_A = bufo_106_Addr_A_orig << 32'd2;
assign bufo_106_Addr_A_orig = 64'd0;
assign bufo_106_Clk_A = ap_clk;
assign bufo_106_Din_A = reg_2580;
assign bufo_106_Rst_A = ap_rst;
assign bufo_107_Addr_A = bufo_107_Addr_A_orig << 32'd2;
assign bufo_107_Addr_A_orig = 64'd0;
assign bufo_107_Clk_A = ap_clk;
assign bufo_107_Din_A = reg_2580;
assign bufo_107_Rst_A = ap_rst;
assign bufo_108_Addr_A = bufo_108_Addr_A_orig << 32'd2;
assign bufo_108_Addr_A_orig = 64'd0;
assign bufo_108_Clk_A = ap_clk;
assign bufo_108_Din_A = reg_2580;
assign bufo_108_Rst_A = ap_rst;
assign bufo_109_Addr_A = bufo_109_Addr_A_orig << 32'd2;
assign bufo_109_Addr_A_orig = 64'd0;
assign bufo_109_Clk_A = ap_clk;
assign bufo_109_Din_A = reg_2580;
assign bufo_109_Rst_A = ap_rst;
assign bufo_10_Addr_A = bufo_10_Addr_A_orig << 32'd2;
assign bufo_10_Addr_A_orig = 64'd0;
assign bufo_10_Clk_A = ap_clk;
assign bufo_10_Din_A = reg_2580;
assign bufo_10_Rst_A = ap_rst;
assign bufo_110_Addr_A = bufo_110_Addr_A_orig << 32'd2;
assign bufo_110_Addr_A_orig = 64'd0;
assign bufo_110_Clk_A = ap_clk;
assign bufo_110_Din_A = reg_2580;
assign bufo_110_Rst_A = ap_rst;
assign bufo_111_Addr_A = bufo_111_Addr_A_orig << 32'd2;
assign bufo_111_Addr_A_orig = 64'd0;
assign bufo_111_Clk_A = ap_clk;
assign bufo_111_Din_A = reg_2580;
assign bufo_111_Rst_A = ap_rst;
assign bufo_112_Addr_A = bufo_112_Addr_A_orig << 32'd2;
assign bufo_112_Addr_A_orig = 64'd0;
assign bufo_112_Clk_A = ap_clk;
assign bufo_112_Din_A = reg_2580;
assign bufo_112_Rst_A = ap_rst;
assign bufo_113_Addr_A = bufo_113_Addr_A_orig << 32'd2;
assign bufo_113_Addr_A_orig = 64'd0;
assign bufo_113_Clk_A = ap_clk;
assign bufo_113_Din_A = reg_2580;
assign bufo_113_Rst_A = ap_rst;
assign bufo_114_Addr_A = bufo_114_Addr_A_orig << 32'd2;
assign bufo_114_Addr_A_orig = 64'd0;
assign bufo_114_Clk_A = ap_clk;
assign bufo_114_Din_A = reg_2580;
assign bufo_114_Rst_A = ap_rst;
assign bufo_115_Addr_A = bufo_115_Addr_A_orig << 32'd2;
assign bufo_115_Addr_A_orig = 64'd0;
assign bufo_115_Clk_A = ap_clk;
assign bufo_115_Din_A = reg_2580;
assign bufo_115_Rst_A = ap_rst;
assign bufo_116_Addr_A = bufo_116_Addr_A_orig << 32'd2;
assign bufo_116_Addr_A_orig = 64'd0;
assign bufo_116_Clk_A = ap_clk;
assign bufo_116_Din_A = reg_2580;
assign bufo_116_Rst_A = ap_rst;
assign bufo_117_Addr_A = bufo_117_Addr_A_orig << 32'd2;
assign bufo_117_Addr_A_orig = 64'd0;
assign bufo_117_Clk_A = ap_clk;
assign bufo_117_Din_A = reg_2580;
assign bufo_117_Rst_A = ap_rst;
assign bufo_118_Addr_A = bufo_118_Addr_A_orig << 32'd2;
assign bufo_118_Addr_A_orig = 64'd0;
assign bufo_118_Clk_A = ap_clk;
assign bufo_118_Din_A = reg_2580;
assign bufo_118_Rst_A = ap_rst;
assign bufo_119_Addr_A = bufo_119_Addr_A_orig << 32'd2;
assign bufo_119_Addr_A_orig = 64'd0;
assign bufo_119_Clk_A = ap_clk;
assign bufo_119_Din_A = reg_2580;
assign bufo_119_Rst_A = ap_rst;
assign bufo_11_Addr_A = bufo_11_Addr_A_orig << 32'd2;
assign bufo_11_Addr_A_orig = 64'd0;
assign bufo_11_Clk_A = ap_clk;
assign bufo_11_Din_A = reg_2580;
assign bufo_11_Rst_A = ap_rst;
assign bufo_120_Addr_A = bufo_120_Addr_A_orig << 32'd2;
assign bufo_120_Addr_A_orig = 64'd0;
assign bufo_120_Clk_A = ap_clk;
assign bufo_120_Din_A = reg_2580;
assign bufo_120_Rst_A = ap_rst;
assign bufo_121_Addr_A = bufo_121_Addr_A_orig << 32'd2;
assign bufo_121_Addr_A_orig = 64'd0;
assign bufo_121_Clk_A = ap_clk;
assign bufo_121_Din_A = reg_2580;
assign bufo_121_Rst_A = ap_rst;
assign bufo_122_Addr_A = bufo_122_Addr_A_orig << 32'd2;
assign bufo_122_Addr_A_orig = 64'd0;
assign bufo_122_Clk_A = ap_clk;
assign bufo_122_Din_A = reg_2580;
assign bufo_122_Rst_A = ap_rst;
assign bufo_123_Addr_A = bufo_123_Addr_A_orig << 32'd2;
assign bufo_123_Addr_A_orig = 64'd0;
assign bufo_123_Clk_A = ap_clk;
assign bufo_123_Din_A = reg_2580;
assign bufo_123_Rst_A = ap_rst;
assign bufo_124_Addr_A = bufo_124_Addr_A_orig << 32'd2;
assign bufo_124_Addr_A_orig = 64'd0;
assign bufo_124_Clk_A = ap_clk;
assign bufo_124_Din_A = reg_2580;
assign bufo_124_Rst_A = ap_rst;
assign bufo_125_Addr_A = bufo_125_Addr_A_orig << 32'd2;
assign bufo_125_Addr_A_orig = 64'd0;
assign bufo_125_Clk_A = ap_clk;
assign bufo_125_Din_A = reg_2580;
assign bufo_125_Rst_A = ap_rst;
assign bufo_126_Addr_A = bufo_126_Addr_A_orig << 32'd2;
assign bufo_126_Addr_A_orig = 64'd0;
assign bufo_126_Clk_A = ap_clk;
assign bufo_126_Din_A = reg_2580;
assign bufo_126_Rst_A = ap_rst;
assign bufo_127_Addr_A = bufo_127_Addr_A_orig << 32'd2;
assign bufo_127_Addr_A_orig = 64'd0;
assign bufo_127_Clk_A = ap_clk;
assign bufo_127_Din_A = reg_2580;
assign bufo_127_Rst_A = ap_rst;
assign bufo_128_Addr_A = 32'd0;
assign bufo_128_Addr_B = 32'd0;
assign bufo_128_Clk_A = ap_clk;
assign bufo_128_Clk_B = ap_clk;
assign bufo_128_Din_A = 32'd0;
assign bufo_128_Din_B = 32'd0;
assign bufo_128_EN_A = 1'b0;
assign bufo_128_EN_B = 1'b0;
assign bufo_128_Rst_A = ap_rst;
assign bufo_128_Rst_B = ap_rst;
assign bufo_128_WEN_A = 4'd0;
assign bufo_128_WEN_B = 4'd0;
assign bufo_129_Addr_A = 32'd0;
assign bufo_129_Addr_B = 32'd0;
assign bufo_129_Clk_A = ap_clk;
assign bufo_129_Clk_B = ap_clk;
assign bufo_129_Din_A = 32'd0;
assign bufo_129_Din_B = 32'd0;
assign bufo_129_EN_A = 1'b0;
assign bufo_129_EN_B = 1'b0;
assign bufo_129_Rst_A = ap_rst;
assign bufo_129_Rst_B = ap_rst;
assign bufo_129_WEN_A = 4'd0;
assign bufo_129_WEN_B = 4'd0;
assign bufo_12_Addr_A = bufo_12_Addr_A_orig << 32'd2;
assign bufo_12_Addr_A_orig = 64'd0;
assign bufo_12_Clk_A = ap_clk;
assign bufo_12_Din_A = reg_2580;
assign bufo_12_Rst_A = ap_rst;
assign bufo_130_Addr_A = 32'd0;
assign bufo_130_Addr_B = 32'd0;
assign bufo_130_Clk_A = ap_clk;
assign bufo_130_Clk_B = ap_clk;
assign bufo_130_Din_A = 32'd0;
assign bufo_130_Din_B = 32'd0;
assign bufo_130_EN_A = 1'b0;
assign bufo_130_EN_B = 1'b0;
assign bufo_130_Rst_A = ap_rst;
assign bufo_130_Rst_B = ap_rst;
assign bufo_130_WEN_A = 4'd0;
assign bufo_130_WEN_B = 4'd0;
assign bufo_131_Addr_A = 32'd0;
assign bufo_131_Addr_B = 32'd0;
assign bufo_131_Clk_A = ap_clk;
assign bufo_131_Clk_B = ap_clk;
assign bufo_131_Din_A = 32'd0;
assign bufo_131_Din_B = 32'd0;
assign bufo_131_EN_A = 1'b0;
assign bufo_131_EN_B = 1'b0;
assign bufo_131_Rst_A = ap_rst;
assign bufo_131_Rst_B = ap_rst;
assign bufo_131_WEN_A = 4'd0;
assign bufo_131_WEN_B = 4'd0;
assign bufo_132_Addr_A = 32'd0;
assign bufo_132_Addr_B = 32'd0;
assign bufo_132_Clk_A = ap_clk;
assign bufo_132_Clk_B = ap_clk;
assign bufo_132_Din_A = 32'd0;
assign bufo_132_Din_B = 32'd0;
assign bufo_132_EN_A = 1'b0;
assign bufo_132_EN_B = 1'b0;
assign bufo_132_Rst_A = ap_rst;
assign bufo_132_Rst_B = ap_rst;
assign bufo_132_WEN_A = 4'd0;
assign bufo_132_WEN_B = 4'd0;
assign bufo_133_Addr_A = 32'd0;
assign bufo_133_Addr_B = 32'd0;
assign bufo_133_Clk_A = ap_clk;
assign bufo_133_Clk_B = ap_clk;
assign bufo_133_Din_A = 32'd0;
assign bufo_133_Din_B = 32'd0;
assign bufo_133_EN_A = 1'b0;
assign bufo_133_EN_B = 1'b0;
assign bufo_133_Rst_A = ap_rst;
assign bufo_133_Rst_B = ap_rst;
assign bufo_133_WEN_A = 4'd0;
assign bufo_133_WEN_B = 4'd0;
assign bufo_134_Addr_A = 32'd0;
assign bufo_134_Addr_B = 32'd0;
assign bufo_134_Clk_A = ap_clk;
assign bufo_134_Clk_B = ap_clk;
assign bufo_134_Din_A = 32'd0;
assign bufo_134_Din_B = 32'd0;
assign bufo_134_EN_A = 1'b0;
assign bufo_134_EN_B = 1'b0;
assign bufo_134_Rst_A = ap_rst;
assign bufo_134_Rst_B = ap_rst;
assign bufo_134_WEN_A = 4'd0;
assign bufo_134_WEN_B = 4'd0;
assign bufo_135_Addr_A = 32'd0;
assign bufo_135_Addr_B = 32'd0;
assign bufo_135_Clk_A = ap_clk;
assign bufo_135_Clk_B = ap_clk;
assign bufo_135_Din_A = 32'd0;
assign bufo_135_Din_B = 32'd0;
assign bufo_135_EN_A = 1'b0;
assign bufo_135_EN_B = 1'b0;
assign bufo_135_Rst_A = ap_rst;
assign bufo_135_Rst_B = ap_rst;
assign bufo_135_WEN_A = 4'd0;
assign bufo_135_WEN_B = 4'd0;
assign bufo_136_Addr_A = 32'd0;
assign bufo_136_Addr_B = 32'd0;
assign bufo_136_Clk_A = ap_clk;
assign bufo_136_Clk_B = ap_clk;
assign bufo_136_Din_A = 32'd0;
assign bufo_136_Din_B = 32'd0;
assign bufo_136_EN_A = 1'b0;
assign bufo_136_EN_B = 1'b0;
assign bufo_136_Rst_A = ap_rst;
assign bufo_136_Rst_B = ap_rst;
assign bufo_136_WEN_A = 4'd0;
assign bufo_136_WEN_B = 4'd0;
assign bufo_137_Addr_A = 32'd0;
assign bufo_137_Addr_B = 32'd0;
assign bufo_137_Clk_A = ap_clk;
assign bufo_137_Clk_B = ap_clk;
assign bufo_137_Din_A = 32'd0;
assign bufo_137_Din_B = 32'd0;
assign bufo_137_EN_A = 1'b0;
assign bufo_137_EN_B = 1'b0;
assign bufo_137_Rst_A = ap_rst;
assign bufo_137_Rst_B = ap_rst;
assign bufo_137_WEN_A = 4'd0;
assign bufo_137_WEN_B = 4'd0;
assign bufo_138_Addr_A = 32'd0;
assign bufo_138_Addr_B = 32'd0;
assign bufo_138_Clk_A = ap_clk;
assign bufo_138_Clk_B = ap_clk;
assign bufo_138_Din_A = 32'd0;
assign bufo_138_Din_B = 32'd0;
assign bufo_138_EN_A = 1'b0;
assign bufo_138_EN_B = 1'b0;
assign bufo_138_Rst_A = ap_rst;
assign bufo_138_Rst_B = ap_rst;
assign bufo_138_WEN_A = 4'd0;
assign bufo_138_WEN_B = 4'd0;
assign bufo_139_Addr_A = 32'd0;
assign bufo_139_Addr_B = 32'd0;
assign bufo_139_Clk_A = ap_clk;
assign bufo_139_Clk_B = ap_clk;
assign bufo_139_Din_A = 32'd0;
assign bufo_139_Din_B = 32'd0;
assign bufo_139_EN_A = 1'b0;
assign bufo_139_EN_B = 1'b0;
assign bufo_139_Rst_A = ap_rst;
assign bufo_139_Rst_B = ap_rst;
assign bufo_139_WEN_A = 4'd0;
assign bufo_139_WEN_B = 4'd0;
assign bufo_13_Addr_A = bufo_13_Addr_A_orig << 32'd2;
assign bufo_13_Addr_A_orig = 64'd0;
assign bufo_13_Clk_A = ap_clk;
assign bufo_13_Din_A = reg_2580;
assign bufo_13_Rst_A = ap_rst;
assign bufo_140_Addr_A = 32'd0;
assign bufo_140_Addr_B = 32'd0;
assign bufo_140_Clk_A = ap_clk;
assign bufo_140_Clk_B = ap_clk;
assign bufo_140_Din_A = 32'd0;
assign bufo_140_Din_B = 32'd0;
assign bufo_140_EN_A = 1'b0;
assign bufo_140_EN_B = 1'b0;
assign bufo_140_Rst_A = ap_rst;
assign bufo_140_Rst_B = ap_rst;
assign bufo_140_WEN_A = 4'd0;
assign bufo_140_WEN_B = 4'd0;
assign bufo_141_Addr_A = 32'd0;
assign bufo_141_Addr_B = 32'd0;
assign bufo_141_Clk_A = ap_clk;
assign bufo_141_Clk_B = ap_clk;
assign bufo_141_Din_A = 32'd0;
assign bufo_141_Din_B = 32'd0;
assign bufo_141_EN_A = 1'b0;
assign bufo_141_EN_B = 1'b0;
assign bufo_141_Rst_A = ap_rst;
assign bufo_141_Rst_B = ap_rst;
assign bufo_141_WEN_A = 4'd0;
assign bufo_141_WEN_B = 4'd0;
assign bufo_142_Addr_A = 32'd0;
assign bufo_142_Addr_B = 32'd0;
assign bufo_142_Clk_A = ap_clk;
assign bufo_142_Clk_B = ap_clk;
assign bufo_142_Din_A = 32'd0;
assign bufo_142_Din_B = 32'd0;
assign bufo_142_EN_A = 1'b0;
assign bufo_142_EN_B = 1'b0;
assign bufo_142_Rst_A = ap_rst;
assign bufo_142_Rst_B = ap_rst;
assign bufo_142_WEN_A = 4'd0;
assign bufo_142_WEN_B = 4'd0;
assign bufo_143_Addr_A = 32'd0;
assign bufo_143_Addr_B = 32'd0;
assign bufo_143_Clk_A = ap_clk;
assign bufo_143_Clk_B = ap_clk;
assign bufo_143_Din_A = 32'd0;
assign bufo_143_Din_B = 32'd0;
assign bufo_143_EN_A = 1'b0;
assign bufo_143_EN_B = 1'b0;
assign bufo_143_Rst_A = ap_rst;
assign bufo_143_Rst_B = ap_rst;
assign bufo_143_WEN_A = 4'd0;
assign bufo_143_WEN_B = 4'd0;
assign bufo_144_Addr_A = 32'd0;
assign bufo_144_Addr_B = 32'd0;
assign bufo_144_Clk_A = ap_clk;
assign bufo_144_Clk_B = ap_clk;
assign bufo_144_Din_A = 32'd0;
assign bufo_144_Din_B = 32'd0;
assign bufo_144_EN_A = 1'b0;
assign bufo_144_EN_B = 1'b0;
assign bufo_144_Rst_A = ap_rst;
assign bufo_144_Rst_B = ap_rst;
assign bufo_144_WEN_A = 4'd0;
assign bufo_144_WEN_B = 4'd0;
assign bufo_145_Addr_A = 32'd0;
assign bufo_145_Addr_B = 32'd0;
assign bufo_145_Clk_A = ap_clk;
assign bufo_145_Clk_B = ap_clk;
assign bufo_145_Din_A = 32'd0;
assign bufo_145_Din_B = 32'd0;
assign bufo_145_EN_A = 1'b0;
assign bufo_145_EN_B = 1'b0;
assign bufo_145_Rst_A = ap_rst;
assign bufo_145_Rst_B = ap_rst;
assign bufo_145_WEN_A = 4'd0;
assign bufo_145_WEN_B = 4'd0;
assign bufo_146_Addr_A = 32'd0;
assign bufo_146_Addr_B = 32'd0;
assign bufo_146_Clk_A = ap_clk;
assign bufo_146_Clk_B = ap_clk;
assign bufo_146_Din_A = 32'd0;
assign bufo_146_Din_B = 32'd0;
assign bufo_146_EN_A = 1'b0;
assign bufo_146_EN_B = 1'b0;
assign bufo_146_Rst_A = ap_rst;
assign bufo_146_Rst_B = ap_rst;
assign bufo_146_WEN_A = 4'd0;
assign bufo_146_WEN_B = 4'd0;
assign bufo_147_Addr_A = 32'd0;
assign bufo_147_Addr_B = 32'd0;
assign bufo_147_Clk_A = ap_clk;
assign bufo_147_Clk_B = ap_clk;
assign bufo_147_Din_A = 32'd0;
assign bufo_147_Din_B = 32'd0;
assign bufo_147_EN_A = 1'b0;
assign bufo_147_EN_B = 1'b0;
assign bufo_147_Rst_A = ap_rst;
assign bufo_147_Rst_B = ap_rst;
assign bufo_147_WEN_A = 4'd0;
assign bufo_147_WEN_B = 4'd0;
assign bufo_148_Addr_A = 32'd0;
assign bufo_148_Addr_B = 32'd0;
assign bufo_148_Clk_A = ap_clk;
assign bufo_148_Clk_B = ap_clk;
assign bufo_148_Din_A = 32'd0;
assign bufo_148_Din_B = 32'd0;
assign bufo_148_EN_A = 1'b0;
assign bufo_148_EN_B = 1'b0;
assign bufo_148_Rst_A = ap_rst;
assign bufo_148_Rst_B = ap_rst;
assign bufo_148_WEN_A = 4'd0;
assign bufo_148_WEN_B = 4'd0;
assign bufo_149_Addr_A = 32'd0;
assign bufo_149_Addr_B = 32'd0;
assign bufo_149_Clk_A = ap_clk;
assign bufo_149_Clk_B = ap_clk;
assign bufo_149_Din_A = 32'd0;
assign bufo_149_Din_B = 32'd0;
assign bufo_149_EN_A = 1'b0;
assign bufo_149_EN_B = 1'b0;
assign bufo_149_Rst_A = ap_rst;
assign bufo_149_Rst_B = ap_rst;
assign bufo_149_WEN_A = 4'd0;
assign bufo_149_WEN_B = 4'd0;
assign bufo_14_Addr_A = bufo_14_Addr_A_orig << 32'd2;
assign bufo_14_Addr_A_orig = 64'd0;
assign bufo_14_Clk_A = ap_clk;
assign bufo_14_Din_A = reg_2580;
assign bufo_14_Rst_A = ap_rst;
assign bufo_150_Addr_A = 32'd0;
assign bufo_150_Addr_B = 32'd0;
assign bufo_150_Clk_A = ap_clk;
assign bufo_150_Clk_B = ap_clk;
assign bufo_150_Din_A = 32'd0;
assign bufo_150_Din_B = 32'd0;
assign bufo_150_EN_A = 1'b0;
assign bufo_150_EN_B = 1'b0;
assign bufo_150_Rst_A = ap_rst;
assign bufo_150_Rst_B = ap_rst;
assign bufo_150_WEN_A = 4'd0;
assign bufo_150_WEN_B = 4'd0;
assign bufo_151_Addr_A = 32'd0;
assign bufo_151_Addr_B = 32'd0;
assign bufo_151_Clk_A = ap_clk;
assign bufo_151_Clk_B = ap_clk;
assign bufo_151_Din_A = 32'd0;
assign bufo_151_Din_B = 32'd0;
assign bufo_151_EN_A = 1'b0;
assign bufo_151_EN_B = 1'b0;
assign bufo_151_Rst_A = ap_rst;
assign bufo_151_Rst_B = ap_rst;
assign bufo_151_WEN_A = 4'd0;
assign bufo_151_WEN_B = 4'd0;
assign bufo_152_Addr_A = 32'd0;
assign bufo_152_Addr_B = 32'd0;
assign bufo_152_Clk_A = ap_clk;
assign bufo_152_Clk_B = ap_clk;
assign bufo_152_Din_A = 32'd0;
assign bufo_152_Din_B = 32'd0;
assign bufo_152_EN_A = 1'b0;
assign bufo_152_EN_B = 1'b0;
assign bufo_152_Rst_A = ap_rst;
assign bufo_152_Rst_B = ap_rst;
assign bufo_152_WEN_A = 4'd0;
assign bufo_152_WEN_B = 4'd0;
assign bufo_153_Addr_A = 32'd0;
assign bufo_153_Addr_B = 32'd0;
assign bufo_153_Clk_A = ap_clk;
assign bufo_153_Clk_B = ap_clk;
assign bufo_153_Din_A = 32'd0;
assign bufo_153_Din_B = 32'd0;
assign bufo_153_EN_A = 1'b0;
assign bufo_153_EN_B = 1'b0;
assign bufo_153_Rst_A = ap_rst;
assign bufo_153_Rst_B = ap_rst;
assign bufo_153_WEN_A = 4'd0;
assign bufo_153_WEN_B = 4'd0;
assign bufo_154_Addr_A = 32'd0;
assign bufo_154_Addr_B = 32'd0;
assign bufo_154_Clk_A = ap_clk;
assign bufo_154_Clk_B = ap_clk;
assign bufo_154_Din_A = 32'd0;
assign bufo_154_Din_B = 32'd0;
assign bufo_154_EN_A = 1'b0;
assign bufo_154_EN_B = 1'b0;
assign bufo_154_Rst_A = ap_rst;
assign bufo_154_Rst_B = ap_rst;
assign bufo_154_WEN_A = 4'd0;
assign bufo_154_WEN_B = 4'd0;
assign bufo_155_Addr_A = 32'd0;
assign bufo_155_Addr_B = 32'd0;
assign bufo_155_Clk_A = ap_clk;
assign bufo_155_Clk_B = ap_clk;
assign bufo_155_Din_A = 32'd0;
assign bufo_155_Din_B = 32'd0;
assign bufo_155_EN_A = 1'b0;
assign bufo_155_EN_B = 1'b0;
assign bufo_155_Rst_A = ap_rst;
assign bufo_155_Rst_B = ap_rst;
assign bufo_155_WEN_A = 4'd0;
assign bufo_155_WEN_B = 4'd0;
assign bufo_156_Addr_A = 32'd0;
assign bufo_156_Addr_B = 32'd0;
assign bufo_156_Clk_A = ap_clk;
assign bufo_156_Clk_B = ap_clk;
assign bufo_156_Din_A = 32'd0;
assign bufo_156_Din_B = 32'd0;
assign bufo_156_EN_A = 1'b0;
assign bufo_156_EN_B = 1'b0;
assign bufo_156_Rst_A = ap_rst;
assign bufo_156_Rst_B = ap_rst;
assign bufo_156_WEN_A = 4'd0;
assign bufo_156_WEN_B = 4'd0;
assign bufo_157_Addr_A = 32'd0;
assign bufo_157_Addr_B = 32'd0;
assign bufo_157_Clk_A = ap_clk;
assign bufo_157_Clk_B = ap_clk;
assign bufo_157_Din_A = 32'd0;
assign bufo_157_Din_B = 32'd0;
assign bufo_157_EN_A = 1'b0;
assign bufo_157_EN_B = 1'b0;
assign bufo_157_Rst_A = ap_rst;
assign bufo_157_Rst_B = ap_rst;
assign bufo_157_WEN_A = 4'd0;
assign bufo_157_WEN_B = 4'd0;
assign bufo_158_Addr_A = 32'd0;
assign bufo_158_Addr_B = 32'd0;
assign bufo_158_Clk_A = ap_clk;
assign bufo_158_Clk_B = ap_clk;
assign bufo_158_Din_A = 32'd0;
assign bufo_158_Din_B = 32'd0;
assign bufo_158_EN_A = 1'b0;
assign bufo_158_EN_B = 1'b0;
assign bufo_158_Rst_A = ap_rst;
assign bufo_158_Rst_B = ap_rst;
assign bufo_158_WEN_A = 4'd0;
assign bufo_158_WEN_B = 4'd0;
assign bufo_159_Addr_A = 32'd0;
assign bufo_159_Addr_B = 32'd0;
assign bufo_159_Clk_A = ap_clk;
assign bufo_159_Clk_B = ap_clk;
assign bufo_159_Din_A = 32'd0;
assign bufo_159_Din_B = 32'd0;
assign bufo_159_EN_A = 1'b0;
assign bufo_159_EN_B = 1'b0;
assign bufo_159_Rst_A = ap_rst;
assign bufo_159_Rst_B = ap_rst;
assign bufo_159_WEN_A = 4'd0;
assign bufo_159_WEN_B = 4'd0;
assign bufo_15_Addr_A = bufo_15_Addr_A_orig << 32'd2;
assign bufo_15_Addr_A_orig = 64'd0;
assign bufo_15_Clk_A = ap_clk;
assign bufo_15_Din_A = reg_2580;
assign bufo_15_Rst_A = ap_rst;
assign bufo_160_Addr_A = 32'd0;
assign bufo_160_Addr_B = 32'd0;
assign bufo_160_Clk_A = ap_clk;
assign bufo_160_Clk_B = ap_clk;
assign bufo_160_Din_A = 32'd0;
assign bufo_160_Din_B = 32'd0;
assign bufo_160_EN_A = 1'b0;
assign bufo_160_EN_B = 1'b0;
assign bufo_160_Rst_A = ap_rst;
assign bufo_160_Rst_B = ap_rst;
assign bufo_160_WEN_A = 4'd0;
assign bufo_160_WEN_B = 4'd0;
assign bufo_161_Addr_A = 32'd0;
assign bufo_161_Addr_B = 32'd0;
assign bufo_161_Clk_A = ap_clk;
assign bufo_161_Clk_B = ap_clk;
assign bufo_161_Din_A = 32'd0;
assign bufo_161_Din_B = 32'd0;
assign bufo_161_EN_A = 1'b0;
assign bufo_161_EN_B = 1'b0;
assign bufo_161_Rst_A = ap_rst;
assign bufo_161_Rst_B = ap_rst;
assign bufo_161_WEN_A = 4'd0;
assign bufo_161_WEN_B = 4'd0;
assign bufo_162_Addr_A = 32'd0;
assign bufo_162_Addr_B = 32'd0;
assign bufo_162_Clk_A = ap_clk;
assign bufo_162_Clk_B = ap_clk;
assign bufo_162_Din_A = 32'd0;
assign bufo_162_Din_B = 32'd0;
assign bufo_162_EN_A = 1'b0;
assign bufo_162_EN_B = 1'b0;
assign bufo_162_Rst_A = ap_rst;
assign bufo_162_Rst_B = ap_rst;
assign bufo_162_WEN_A = 4'd0;
assign bufo_162_WEN_B = 4'd0;
assign bufo_163_Addr_A = 32'd0;
assign bufo_163_Addr_B = 32'd0;
assign bufo_163_Clk_A = ap_clk;
assign bufo_163_Clk_B = ap_clk;
assign bufo_163_Din_A = 32'd0;
assign bufo_163_Din_B = 32'd0;
assign bufo_163_EN_A = 1'b0;
assign bufo_163_EN_B = 1'b0;
assign bufo_163_Rst_A = ap_rst;
assign bufo_163_Rst_B = ap_rst;
assign bufo_163_WEN_A = 4'd0;
assign bufo_163_WEN_B = 4'd0;
assign bufo_164_Addr_A = 32'd0;
assign bufo_164_Addr_B = 32'd0;
assign bufo_164_Clk_A = ap_clk;
assign bufo_164_Clk_B = ap_clk;
assign bufo_164_Din_A = 32'd0;
assign bufo_164_Din_B = 32'd0;
assign bufo_164_EN_A = 1'b0;
assign bufo_164_EN_B = 1'b0;
assign bufo_164_Rst_A = ap_rst;
assign bufo_164_Rst_B = ap_rst;
assign bufo_164_WEN_A = 4'd0;
assign bufo_164_WEN_B = 4'd0;
assign bufo_165_Addr_A = 32'd0;
assign bufo_165_Addr_B = 32'd0;
assign bufo_165_Clk_A = ap_clk;
assign bufo_165_Clk_B = ap_clk;
assign bufo_165_Din_A = 32'd0;
assign bufo_165_Din_B = 32'd0;
assign bufo_165_EN_A = 1'b0;
assign bufo_165_EN_B = 1'b0;
assign bufo_165_Rst_A = ap_rst;
assign bufo_165_Rst_B = ap_rst;
assign bufo_165_WEN_A = 4'd0;
assign bufo_165_WEN_B = 4'd0;
assign bufo_166_Addr_A = 32'd0;
assign bufo_166_Addr_B = 32'd0;
assign bufo_166_Clk_A = ap_clk;
assign bufo_166_Clk_B = ap_clk;
assign bufo_166_Din_A = 32'd0;
assign bufo_166_Din_B = 32'd0;
assign bufo_166_EN_A = 1'b0;
assign bufo_166_EN_B = 1'b0;
assign bufo_166_Rst_A = ap_rst;
assign bufo_166_Rst_B = ap_rst;
assign bufo_166_WEN_A = 4'd0;
assign bufo_166_WEN_B = 4'd0;
assign bufo_167_Addr_A = 32'd0;
assign bufo_167_Addr_B = 32'd0;
assign bufo_167_Clk_A = ap_clk;
assign bufo_167_Clk_B = ap_clk;
assign bufo_167_Din_A = 32'd0;
assign bufo_167_Din_B = 32'd0;
assign bufo_167_EN_A = 1'b0;
assign bufo_167_EN_B = 1'b0;
assign bufo_167_Rst_A = ap_rst;
assign bufo_167_Rst_B = ap_rst;
assign bufo_167_WEN_A = 4'd0;
assign bufo_167_WEN_B = 4'd0;
assign bufo_168_Addr_A = 32'd0;
assign bufo_168_Addr_B = 32'd0;
assign bufo_168_Clk_A = ap_clk;
assign bufo_168_Clk_B = ap_clk;
assign bufo_168_Din_A = 32'd0;
assign bufo_168_Din_B = 32'd0;
assign bufo_168_EN_A = 1'b0;
assign bufo_168_EN_B = 1'b0;
assign bufo_168_Rst_A = ap_rst;
assign bufo_168_Rst_B = ap_rst;
assign bufo_168_WEN_A = 4'd0;
assign bufo_168_WEN_B = 4'd0;
assign bufo_169_Addr_A = 32'd0;
assign bufo_169_Addr_B = 32'd0;
assign bufo_169_Clk_A = ap_clk;
assign bufo_169_Clk_B = ap_clk;
assign bufo_169_Din_A = 32'd0;
assign bufo_169_Din_B = 32'd0;
assign bufo_169_EN_A = 1'b0;
assign bufo_169_EN_B = 1'b0;
assign bufo_169_Rst_A = ap_rst;
assign bufo_169_Rst_B = ap_rst;
assign bufo_169_WEN_A = 4'd0;
assign bufo_169_WEN_B = 4'd0;
assign bufo_16_Addr_A = bufo_16_Addr_A_orig << 32'd2;
assign bufo_16_Addr_A_orig = 64'd0;
assign bufo_16_Clk_A = ap_clk;
assign bufo_16_Din_A = reg_2580;
assign bufo_16_Rst_A = ap_rst;
assign bufo_170_Addr_A = 32'd0;
assign bufo_170_Addr_B = 32'd0;
assign bufo_170_Clk_A = ap_clk;
assign bufo_170_Clk_B = ap_clk;
assign bufo_170_Din_A = 32'd0;
assign bufo_170_Din_B = 32'd0;
assign bufo_170_EN_A = 1'b0;
assign bufo_170_EN_B = 1'b0;
assign bufo_170_Rst_A = ap_rst;
assign bufo_170_Rst_B = ap_rst;
assign bufo_170_WEN_A = 4'd0;
assign bufo_170_WEN_B = 4'd0;
assign bufo_171_Addr_A = 32'd0;
assign bufo_171_Addr_B = 32'd0;
assign bufo_171_Clk_A = ap_clk;
assign bufo_171_Clk_B = ap_clk;
assign bufo_171_Din_A = 32'd0;
assign bufo_171_Din_B = 32'd0;
assign bufo_171_EN_A = 1'b0;
assign bufo_171_EN_B = 1'b0;
assign bufo_171_Rst_A = ap_rst;
assign bufo_171_Rst_B = ap_rst;
assign bufo_171_WEN_A = 4'd0;
assign bufo_171_WEN_B = 4'd0;
assign bufo_172_Addr_A = 32'd0;
assign bufo_172_Addr_B = 32'd0;
assign bufo_172_Clk_A = ap_clk;
assign bufo_172_Clk_B = ap_clk;
assign bufo_172_Din_A = 32'd0;
assign bufo_172_Din_B = 32'd0;
assign bufo_172_EN_A = 1'b0;
assign bufo_172_EN_B = 1'b0;
assign bufo_172_Rst_A = ap_rst;
assign bufo_172_Rst_B = ap_rst;
assign bufo_172_WEN_A = 4'd0;
assign bufo_172_WEN_B = 4'd0;
assign bufo_173_Addr_A = 32'd0;
assign bufo_173_Addr_B = 32'd0;
assign bufo_173_Clk_A = ap_clk;
assign bufo_173_Clk_B = ap_clk;
assign bufo_173_Din_A = 32'd0;
assign bufo_173_Din_B = 32'd0;
assign bufo_173_EN_A = 1'b0;
assign bufo_173_EN_B = 1'b0;
assign bufo_173_Rst_A = ap_rst;
assign bufo_173_Rst_B = ap_rst;
assign bufo_173_WEN_A = 4'd0;
assign bufo_173_WEN_B = 4'd0;
assign bufo_174_Addr_A = 32'd0;
assign bufo_174_Addr_B = 32'd0;
assign bufo_174_Clk_A = ap_clk;
assign bufo_174_Clk_B = ap_clk;
assign bufo_174_Din_A = 32'd0;
assign bufo_174_Din_B = 32'd0;
assign bufo_174_EN_A = 1'b0;
assign bufo_174_EN_B = 1'b0;
assign bufo_174_Rst_A = ap_rst;
assign bufo_174_Rst_B = ap_rst;
assign bufo_174_WEN_A = 4'd0;
assign bufo_174_WEN_B = 4'd0;
assign bufo_175_Addr_A = 32'd0;
assign bufo_175_Addr_B = 32'd0;
assign bufo_175_Clk_A = ap_clk;
assign bufo_175_Clk_B = ap_clk;
assign bufo_175_Din_A = 32'd0;
assign bufo_175_Din_B = 32'd0;
assign bufo_175_EN_A = 1'b0;
assign bufo_175_EN_B = 1'b0;
assign bufo_175_Rst_A = ap_rst;
assign bufo_175_Rst_B = ap_rst;
assign bufo_175_WEN_A = 4'd0;
assign bufo_175_WEN_B = 4'd0;
assign bufo_176_Addr_A = 32'd0;
assign bufo_176_Addr_B = 32'd0;
assign bufo_176_Clk_A = ap_clk;
assign bufo_176_Clk_B = ap_clk;
assign bufo_176_Din_A = 32'd0;
assign bufo_176_Din_B = 32'd0;
assign bufo_176_EN_A = 1'b0;
assign bufo_176_EN_B = 1'b0;
assign bufo_176_Rst_A = ap_rst;
assign bufo_176_Rst_B = ap_rst;
assign bufo_176_WEN_A = 4'd0;
assign bufo_176_WEN_B = 4'd0;
assign bufo_177_Addr_A = 32'd0;
assign bufo_177_Addr_B = 32'd0;
assign bufo_177_Clk_A = ap_clk;
assign bufo_177_Clk_B = ap_clk;
assign bufo_177_Din_A = 32'd0;
assign bufo_177_Din_B = 32'd0;
assign bufo_177_EN_A = 1'b0;
assign bufo_177_EN_B = 1'b0;
assign bufo_177_Rst_A = ap_rst;
assign bufo_177_Rst_B = ap_rst;
assign bufo_177_WEN_A = 4'd0;
assign bufo_177_WEN_B = 4'd0;
assign bufo_178_Addr_A = 32'd0;
assign bufo_178_Addr_B = 32'd0;
assign bufo_178_Clk_A = ap_clk;
assign bufo_178_Clk_B = ap_clk;
assign bufo_178_Din_A = 32'd0;
assign bufo_178_Din_B = 32'd0;
assign bufo_178_EN_A = 1'b0;
assign bufo_178_EN_B = 1'b0;
assign bufo_178_Rst_A = ap_rst;
assign bufo_178_Rst_B = ap_rst;
assign bufo_178_WEN_A = 4'd0;
assign bufo_178_WEN_B = 4'd0;
assign bufo_179_Addr_A = 32'd0;
assign bufo_179_Addr_B = 32'd0;
assign bufo_179_Clk_A = ap_clk;
assign bufo_179_Clk_B = ap_clk;
assign bufo_179_Din_A = 32'd0;
assign bufo_179_Din_B = 32'd0;
assign bufo_179_EN_A = 1'b0;
assign bufo_179_EN_B = 1'b0;
assign bufo_179_Rst_A = ap_rst;
assign bufo_179_Rst_B = ap_rst;
assign bufo_179_WEN_A = 4'd0;
assign bufo_179_WEN_B = 4'd0;
assign bufo_17_Addr_A = bufo_17_Addr_A_orig << 32'd2;
assign bufo_17_Addr_A_orig = 64'd0;
assign bufo_17_Clk_A = ap_clk;
assign bufo_17_Din_A = reg_2580;
assign bufo_17_Rst_A = ap_rst;
assign bufo_180_Addr_A = 32'd0;
assign bufo_180_Addr_B = 32'd0;
assign bufo_180_Clk_A = ap_clk;
assign bufo_180_Clk_B = ap_clk;
assign bufo_180_Din_A = 32'd0;
assign bufo_180_Din_B = 32'd0;
assign bufo_180_EN_A = 1'b0;
assign bufo_180_EN_B = 1'b0;
assign bufo_180_Rst_A = ap_rst;
assign bufo_180_Rst_B = ap_rst;
assign bufo_180_WEN_A = 4'd0;
assign bufo_180_WEN_B = 4'd0;
assign bufo_181_Addr_A = 32'd0;
assign bufo_181_Addr_B = 32'd0;
assign bufo_181_Clk_A = ap_clk;
assign bufo_181_Clk_B = ap_clk;
assign bufo_181_Din_A = 32'd0;
assign bufo_181_Din_B = 32'd0;
assign bufo_181_EN_A = 1'b0;
assign bufo_181_EN_B = 1'b0;
assign bufo_181_Rst_A = ap_rst;
assign bufo_181_Rst_B = ap_rst;
assign bufo_181_WEN_A = 4'd0;
assign bufo_181_WEN_B = 4'd0;
assign bufo_182_Addr_A = 32'd0;
assign bufo_182_Addr_B = 32'd0;
assign bufo_182_Clk_A = ap_clk;
assign bufo_182_Clk_B = ap_clk;
assign bufo_182_Din_A = 32'd0;
assign bufo_182_Din_B = 32'd0;
assign bufo_182_EN_A = 1'b0;
assign bufo_182_EN_B = 1'b0;
assign bufo_182_Rst_A = ap_rst;
assign bufo_182_Rst_B = ap_rst;
assign bufo_182_WEN_A = 4'd0;
assign bufo_182_WEN_B = 4'd0;
assign bufo_183_Addr_A = 32'd0;
assign bufo_183_Addr_B = 32'd0;
assign bufo_183_Clk_A = ap_clk;
assign bufo_183_Clk_B = ap_clk;
assign bufo_183_Din_A = 32'd0;
assign bufo_183_Din_B = 32'd0;
assign bufo_183_EN_A = 1'b0;
assign bufo_183_EN_B = 1'b0;
assign bufo_183_Rst_A = ap_rst;
assign bufo_183_Rst_B = ap_rst;
assign bufo_183_WEN_A = 4'd0;
assign bufo_183_WEN_B = 4'd0;
assign bufo_184_Addr_A = 32'd0;
assign bufo_184_Addr_B = 32'd0;
assign bufo_184_Clk_A = ap_clk;
assign bufo_184_Clk_B = ap_clk;
assign bufo_184_Din_A = 32'd0;
assign bufo_184_Din_B = 32'd0;
assign bufo_184_EN_A = 1'b0;
assign bufo_184_EN_B = 1'b0;
assign bufo_184_Rst_A = ap_rst;
assign bufo_184_Rst_B = ap_rst;
assign bufo_184_WEN_A = 4'd0;
assign bufo_184_WEN_B = 4'd0;
assign bufo_185_Addr_A = 32'd0;
assign bufo_185_Addr_B = 32'd0;
assign bufo_185_Clk_A = ap_clk;
assign bufo_185_Clk_B = ap_clk;
assign bufo_185_Din_A = 32'd0;
assign bufo_185_Din_B = 32'd0;
assign bufo_185_EN_A = 1'b0;
assign bufo_185_EN_B = 1'b0;
assign bufo_185_Rst_A = ap_rst;
assign bufo_185_Rst_B = ap_rst;
assign bufo_185_WEN_A = 4'd0;
assign bufo_185_WEN_B = 4'd0;
assign bufo_186_Addr_A = 32'd0;
assign bufo_186_Addr_B = 32'd0;
assign bufo_186_Clk_A = ap_clk;
assign bufo_186_Clk_B = ap_clk;
assign bufo_186_Din_A = 32'd0;
assign bufo_186_Din_B = 32'd0;
assign bufo_186_EN_A = 1'b0;
assign bufo_186_EN_B = 1'b0;
assign bufo_186_Rst_A = ap_rst;
assign bufo_186_Rst_B = ap_rst;
assign bufo_186_WEN_A = 4'd0;
assign bufo_186_WEN_B = 4'd0;
assign bufo_187_Addr_A = 32'd0;
assign bufo_187_Addr_B = 32'd0;
assign bufo_187_Clk_A = ap_clk;
assign bufo_187_Clk_B = ap_clk;
assign bufo_187_Din_A = 32'd0;
assign bufo_187_Din_B = 32'd0;
assign bufo_187_EN_A = 1'b0;
assign bufo_187_EN_B = 1'b0;
assign bufo_187_Rst_A = ap_rst;
assign bufo_187_Rst_B = ap_rst;
assign bufo_187_WEN_A = 4'd0;
assign bufo_187_WEN_B = 4'd0;
assign bufo_188_Addr_A = 32'd0;
assign bufo_188_Addr_B = 32'd0;
assign bufo_188_Clk_A = ap_clk;
assign bufo_188_Clk_B = ap_clk;
assign bufo_188_Din_A = 32'd0;
assign bufo_188_Din_B = 32'd0;
assign bufo_188_EN_A = 1'b0;
assign bufo_188_EN_B = 1'b0;
assign bufo_188_Rst_A = ap_rst;
assign bufo_188_Rst_B = ap_rst;
assign bufo_188_WEN_A = 4'd0;
assign bufo_188_WEN_B = 4'd0;
assign bufo_189_Addr_A = 32'd0;
assign bufo_189_Addr_B = 32'd0;
assign bufo_189_Clk_A = ap_clk;
assign bufo_189_Clk_B = ap_clk;
assign bufo_189_Din_A = 32'd0;
assign bufo_189_Din_B = 32'd0;
assign bufo_189_EN_A = 1'b0;
assign bufo_189_EN_B = 1'b0;
assign bufo_189_Rst_A = ap_rst;
assign bufo_189_Rst_B = ap_rst;
assign bufo_189_WEN_A = 4'd0;
assign bufo_189_WEN_B = 4'd0;
assign bufo_18_Addr_A = bufo_18_Addr_A_orig << 32'd2;
assign bufo_18_Addr_A_orig = 64'd0;
assign bufo_18_Clk_A = ap_clk;
assign bufo_18_Din_A = reg_2580;
assign bufo_18_Rst_A = ap_rst;
assign bufo_190_Addr_A = 32'd0;
assign bufo_190_Addr_B = 32'd0;
assign bufo_190_Clk_A = ap_clk;
assign bufo_190_Clk_B = ap_clk;
assign bufo_190_Din_A = 32'd0;
assign bufo_190_Din_B = 32'd0;
assign bufo_190_EN_A = 1'b0;
assign bufo_190_EN_B = 1'b0;
assign bufo_190_Rst_A = ap_rst;
assign bufo_190_Rst_B = ap_rst;
assign bufo_190_WEN_A = 4'd0;
assign bufo_190_WEN_B = 4'd0;
assign bufo_191_Addr_A = 32'd0;
assign bufo_191_Addr_B = 32'd0;
assign bufo_191_Clk_A = ap_clk;
assign bufo_191_Clk_B = ap_clk;
assign bufo_191_Din_A = 32'd0;
assign bufo_191_Din_B = 32'd0;
assign bufo_191_EN_A = 1'b0;
assign bufo_191_EN_B = 1'b0;
assign bufo_191_Rst_A = ap_rst;
assign bufo_191_Rst_B = ap_rst;
assign bufo_191_WEN_A = 4'd0;
assign bufo_191_WEN_B = 4'd0;
assign bufo_192_Addr_A = 32'd0;
assign bufo_192_Addr_B = 32'd0;
assign bufo_192_Clk_A = ap_clk;
assign bufo_192_Clk_B = ap_clk;
assign bufo_192_Din_A = 32'd0;
assign bufo_192_Din_B = 32'd0;
assign bufo_192_EN_A = 1'b0;
assign bufo_192_EN_B = 1'b0;
assign bufo_192_Rst_A = ap_rst;
assign bufo_192_Rst_B = ap_rst;
assign bufo_192_WEN_A = 4'd0;
assign bufo_192_WEN_B = 4'd0;
assign bufo_193_Addr_A = 32'd0;
assign bufo_193_Addr_B = 32'd0;
assign bufo_193_Clk_A = ap_clk;
assign bufo_193_Clk_B = ap_clk;
assign bufo_193_Din_A = 32'd0;
assign bufo_193_Din_B = 32'd0;
assign bufo_193_EN_A = 1'b0;
assign bufo_193_EN_B = 1'b0;
assign bufo_193_Rst_A = ap_rst;
assign bufo_193_Rst_B = ap_rst;
assign bufo_193_WEN_A = 4'd0;
assign bufo_193_WEN_B = 4'd0;
assign bufo_194_Addr_A = 32'd0;
assign bufo_194_Addr_B = 32'd0;
assign bufo_194_Clk_A = ap_clk;
assign bufo_194_Clk_B = ap_clk;
assign bufo_194_Din_A = 32'd0;
assign bufo_194_Din_B = 32'd0;
assign bufo_194_EN_A = 1'b0;
assign bufo_194_EN_B = 1'b0;
assign bufo_194_Rst_A = ap_rst;
assign bufo_194_Rst_B = ap_rst;
assign bufo_194_WEN_A = 4'd0;
assign bufo_194_WEN_B = 4'd0;
assign bufo_195_Addr_A = 32'd0;
assign bufo_195_Addr_B = 32'd0;
assign bufo_195_Clk_A = ap_clk;
assign bufo_195_Clk_B = ap_clk;
assign bufo_195_Din_A = 32'd0;
assign bufo_195_Din_B = 32'd0;
assign bufo_195_EN_A = 1'b0;
assign bufo_195_EN_B = 1'b0;
assign bufo_195_Rst_A = ap_rst;
assign bufo_195_Rst_B = ap_rst;
assign bufo_195_WEN_A = 4'd0;
assign bufo_195_WEN_B = 4'd0;
assign bufo_196_Addr_A = 32'd0;
assign bufo_196_Addr_B = 32'd0;
assign bufo_196_Clk_A = ap_clk;
assign bufo_196_Clk_B = ap_clk;
assign bufo_196_Din_A = 32'd0;
assign bufo_196_Din_B = 32'd0;
assign bufo_196_EN_A = 1'b0;
assign bufo_196_EN_B = 1'b0;
assign bufo_196_Rst_A = ap_rst;
assign bufo_196_Rst_B = ap_rst;
assign bufo_196_WEN_A = 4'd0;
assign bufo_196_WEN_B = 4'd0;
assign bufo_197_Addr_A = 32'd0;
assign bufo_197_Addr_B = 32'd0;
assign bufo_197_Clk_A = ap_clk;
assign bufo_197_Clk_B = ap_clk;
assign bufo_197_Din_A = 32'd0;
assign bufo_197_Din_B = 32'd0;
assign bufo_197_EN_A = 1'b0;
assign bufo_197_EN_B = 1'b0;
assign bufo_197_Rst_A = ap_rst;
assign bufo_197_Rst_B = ap_rst;
assign bufo_197_WEN_A = 4'd0;
assign bufo_197_WEN_B = 4'd0;
assign bufo_198_Addr_A = 32'd0;
assign bufo_198_Addr_B = 32'd0;
assign bufo_198_Clk_A = ap_clk;
assign bufo_198_Clk_B = ap_clk;
assign bufo_198_Din_A = 32'd0;
assign bufo_198_Din_B = 32'd0;
assign bufo_198_EN_A = 1'b0;
assign bufo_198_EN_B = 1'b0;
assign bufo_198_Rst_A = ap_rst;
assign bufo_198_Rst_B = ap_rst;
assign bufo_198_WEN_A = 4'd0;
assign bufo_198_WEN_B = 4'd0;
assign bufo_199_Addr_A = 32'd0;
assign bufo_199_Addr_B = 32'd0;
assign bufo_199_Clk_A = ap_clk;
assign bufo_199_Clk_B = ap_clk;
assign bufo_199_Din_A = 32'd0;
assign bufo_199_Din_B = 32'd0;
assign bufo_199_EN_A = 1'b0;
assign bufo_199_EN_B = 1'b0;
assign bufo_199_Rst_A = ap_rst;
assign bufo_199_Rst_B = ap_rst;
assign bufo_199_WEN_A = 4'd0;
assign bufo_199_WEN_B = 4'd0;
assign bufo_19_Addr_A = bufo_19_Addr_A_orig << 32'd2;
assign bufo_19_Addr_A_orig = 64'd0;
assign bufo_19_Clk_A = ap_clk;
assign bufo_19_Din_A = reg_2580;
assign bufo_19_Rst_A = ap_rst;
assign bufo_1_Addr_A = bufo_1_Addr_A_orig << 32'd2;
assign bufo_1_Addr_A_orig = 64'd0;
assign bufo_1_Clk_A = ap_clk;
assign bufo_1_Din_A = reg_2580;
assign bufo_1_Rst_A = ap_rst;
assign bufo_20_Addr_A = bufo_20_Addr_A_orig << 32'd2;
assign bufo_20_Addr_A_orig = 64'd0;
assign bufo_20_Clk_A = ap_clk;
assign bufo_20_Din_A = reg_2580;
assign bufo_20_Rst_A = ap_rst;
assign bufo_21_Addr_A = bufo_21_Addr_A_orig << 32'd2;
assign bufo_21_Addr_A_orig = 64'd0;
assign bufo_21_Clk_A = ap_clk;
assign bufo_21_Din_A = reg_2580;
assign bufo_21_Rst_A = ap_rst;
assign bufo_22_Addr_A = bufo_22_Addr_A_orig << 32'd2;
assign bufo_22_Addr_A_orig = 64'd0;
assign bufo_22_Clk_A = ap_clk;
assign bufo_22_Din_A = reg_2580;
assign bufo_22_Rst_A = ap_rst;
assign bufo_23_Addr_A = bufo_23_Addr_A_orig << 32'd2;
assign bufo_23_Addr_A_orig = 64'd0;
assign bufo_23_Clk_A = ap_clk;
assign bufo_23_Din_A = reg_2580;
assign bufo_23_Rst_A = ap_rst;
assign bufo_24_Addr_A = bufo_24_Addr_A_orig << 32'd2;
assign bufo_24_Addr_A_orig = 64'd0;
assign bufo_24_Clk_A = ap_clk;
assign bufo_24_Din_A = reg_2580;
assign bufo_24_Rst_A = ap_rst;
assign bufo_25_Addr_A = bufo_25_Addr_A_orig << 32'd2;
assign bufo_25_Addr_A_orig = 64'd0;
assign bufo_25_Clk_A = ap_clk;
assign bufo_25_Din_A = reg_2580;
assign bufo_25_Rst_A = ap_rst;
assign bufo_26_Addr_A = bufo_26_Addr_A_orig << 32'd2;
assign bufo_26_Addr_A_orig = 64'd0;
assign bufo_26_Clk_A = ap_clk;
assign bufo_26_Din_A = reg_2580;
assign bufo_26_Rst_A = ap_rst;
assign bufo_27_Addr_A = bufo_27_Addr_A_orig << 32'd2;
assign bufo_27_Addr_A_orig = 64'd0;
assign bufo_27_Clk_A = ap_clk;
assign bufo_27_Din_A = reg_2580;
assign bufo_27_Rst_A = ap_rst;
assign bufo_28_Addr_A = bufo_28_Addr_A_orig << 32'd2;
assign bufo_28_Addr_A_orig = 64'd0;
assign bufo_28_Clk_A = ap_clk;
assign bufo_28_Din_A = reg_2580;
assign bufo_28_Rst_A = ap_rst;
assign bufo_29_Addr_A = bufo_29_Addr_A_orig << 32'd2;
assign bufo_29_Addr_A_orig = 64'd0;
assign bufo_29_Clk_A = ap_clk;
assign bufo_29_Din_A = reg_2580;
assign bufo_29_Rst_A = ap_rst;
assign bufo_2_Addr_A = bufo_2_Addr_A_orig << 32'd2;
assign bufo_2_Addr_A_orig = 64'd0;
assign bufo_2_Clk_A = ap_clk;
assign bufo_2_Din_A = reg_2580;
assign bufo_2_Rst_A = ap_rst;
assign bufo_30_Addr_A = bufo_30_Addr_A_orig << 32'd2;
assign bufo_30_Addr_A_orig = 64'd0;
assign bufo_30_Clk_A = ap_clk;
assign bufo_30_Din_A = reg_2580;
assign bufo_30_Rst_A = ap_rst;
assign bufo_31_Addr_A = bufo_31_Addr_A_orig << 32'd2;
assign bufo_31_Addr_A_orig = 64'd0;
assign bufo_31_Clk_A = ap_clk;
assign bufo_31_Din_A = reg_2580;
assign bufo_31_Rst_A = ap_rst;
assign bufo_32_Addr_A = bufo_32_Addr_A_orig << 32'd2;
assign bufo_32_Addr_A_orig = 64'd0;
assign bufo_32_Clk_A = ap_clk;
assign bufo_32_Din_A = reg_2580;
assign bufo_32_Rst_A = ap_rst;
assign bufo_33_Addr_A = bufo_33_Addr_A_orig << 32'd2;
assign bufo_33_Addr_A_orig = 64'd0;
assign bufo_33_Clk_A = ap_clk;
assign bufo_33_Din_A = reg_2580;
assign bufo_33_Rst_A = ap_rst;
assign bufo_34_Addr_A = bufo_34_Addr_A_orig << 32'd2;
assign bufo_34_Addr_A_orig = 64'd0;
assign bufo_34_Clk_A = ap_clk;
assign bufo_34_Din_A = reg_2580;
assign bufo_34_Rst_A = ap_rst;
assign bufo_35_Addr_A = bufo_35_Addr_A_orig << 32'd2;
assign bufo_35_Addr_A_orig = 64'd0;
assign bufo_35_Clk_A = ap_clk;
assign bufo_35_Din_A = reg_2580;
assign bufo_35_Rst_A = ap_rst;
assign bufo_36_Addr_A = bufo_36_Addr_A_orig << 32'd2;
assign bufo_36_Addr_A_orig = 64'd0;
assign bufo_36_Clk_A = ap_clk;
assign bufo_36_Din_A = reg_2580;
assign bufo_36_Rst_A = ap_rst;
assign bufo_37_Addr_A = bufo_37_Addr_A_orig << 32'd2;
assign bufo_37_Addr_A_orig = 64'd0;
assign bufo_37_Clk_A = ap_clk;
assign bufo_37_Din_A = reg_2580;
assign bufo_37_Rst_A = ap_rst;
assign bufo_38_Addr_A = bufo_38_Addr_A_orig << 32'd2;
assign bufo_38_Addr_A_orig = 64'd0;
assign bufo_38_Clk_A = ap_clk;
assign bufo_38_Din_A = reg_2580;
assign bufo_38_Rst_A = ap_rst;
assign bufo_39_Addr_A = bufo_39_Addr_A_orig << 32'd2;
assign bufo_39_Addr_A_orig = 64'd0;
assign bufo_39_Clk_A = ap_clk;
assign bufo_39_Din_A = reg_2580;
assign bufo_39_Rst_A = ap_rst;
assign bufo_3_Addr_A = bufo_3_Addr_A_orig << 32'd2;
assign bufo_3_Addr_A_orig = 64'd0;
assign bufo_3_Clk_A = ap_clk;
assign bufo_3_Din_A = reg_2580;
assign bufo_3_Rst_A = ap_rst;
assign bufo_40_Addr_A = bufo_40_Addr_A_orig << 32'd2;
assign bufo_40_Addr_A_orig = 64'd0;
assign bufo_40_Clk_A = ap_clk;
assign bufo_40_Din_A = reg_2580;
assign bufo_40_Rst_A = ap_rst;
assign bufo_41_Addr_A = bufo_41_Addr_A_orig << 32'd2;
assign bufo_41_Addr_A_orig = 64'd0;
assign bufo_41_Clk_A = ap_clk;
assign bufo_41_Din_A = reg_2580;
assign bufo_41_Rst_A = ap_rst;
assign bufo_42_Addr_A = bufo_42_Addr_A_orig << 32'd2;
assign bufo_42_Addr_A_orig = 64'd0;
assign bufo_42_Clk_A = ap_clk;
assign bufo_42_Din_A = reg_2580;
assign bufo_42_Rst_A = ap_rst;
assign bufo_43_Addr_A = bufo_43_Addr_A_orig << 32'd2;
assign bufo_43_Addr_A_orig = 64'd0;
assign bufo_43_Clk_A = ap_clk;
assign bufo_43_Din_A = reg_2580;
assign bufo_43_Rst_A = ap_rst;
assign bufo_44_Addr_A = bufo_44_Addr_A_orig << 32'd2;
assign bufo_44_Addr_A_orig = 64'd0;
assign bufo_44_Clk_A = ap_clk;
assign bufo_44_Din_A = reg_2580;
assign bufo_44_Rst_A = ap_rst;
assign bufo_45_Addr_A = bufo_45_Addr_A_orig << 32'd2;
assign bufo_45_Addr_A_orig = 64'd0;
assign bufo_45_Clk_A = ap_clk;
assign bufo_45_Din_A = reg_2580;
assign bufo_45_Rst_A = ap_rst;
assign bufo_46_Addr_A = bufo_46_Addr_A_orig << 32'd2;
assign bufo_46_Addr_A_orig = 64'd0;
assign bufo_46_Clk_A = ap_clk;
assign bufo_46_Din_A = reg_2580;
assign bufo_46_Rst_A = ap_rst;
assign bufo_47_Addr_A = bufo_47_Addr_A_orig << 32'd2;
assign bufo_47_Addr_A_orig = 64'd0;
assign bufo_47_Clk_A = ap_clk;
assign bufo_47_Din_A = reg_2580;
assign bufo_47_Rst_A = ap_rst;
assign bufo_48_Addr_A = bufo_48_Addr_A_orig << 32'd2;
assign bufo_48_Addr_A_orig = 64'd0;
assign bufo_48_Clk_A = ap_clk;
assign bufo_48_Din_A = reg_2580;
assign bufo_48_Rst_A = ap_rst;
assign bufo_49_Addr_A = bufo_49_Addr_A_orig << 32'd2;
assign bufo_49_Addr_A_orig = 64'd0;
assign bufo_49_Clk_A = ap_clk;
assign bufo_49_Din_A = reg_2580;
assign bufo_49_Rst_A = ap_rst;
assign bufo_4_Addr_A = bufo_4_Addr_A_orig << 32'd2;
assign bufo_4_Addr_A_orig = 64'd0;
assign bufo_4_Clk_A = ap_clk;
assign bufo_4_Din_A = reg_2580;
assign bufo_4_Rst_A = ap_rst;
assign bufo_50_Addr_A = bufo_50_Addr_A_orig << 32'd2;
assign bufo_50_Addr_A_orig = 64'd0;
assign bufo_50_Clk_A = ap_clk;
assign bufo_50_Din_A = reg_2580;
assign bufo_50_Rst_A = ap_rst;
assign bufo_51_Addr_A = bufo_51_Addr_A_orig << 32'd2;
assign bufo_51_Addr_A_orig = 64'd0;
assign bufo_51_Clk_A = ap_clk;
assign bufo_51_Din_A = reg_2580;
assign bufo_51_Rst_A = ap_rst;
assign bufo_52_Addr_A = bufo_52_Addr_A_orig << 32'd2;
assign bufo_52_Addr_A_orig = 64'd0;
assign bufo_52_Clk_A = ap_clk;
assign bufo_52_Din_A = reg_2580;
assign bufo_52_Rst_A = ap_rst;
assign bufo_53_Addr_A = bufo_53_Addr_A_orig << 32'd2;
assign bufo_53_Addr_A_orig = 64'd0;
assign bufo_53_Clk_A = ap_clk;
assign bufo_53_Din_A = reg_2580;
assign bufo_53_Rst_A = ap_rst;
assign bufo_54_Addr_A = bufo_54_Addr_A_orig << 32'd2;
assign bufo_54_Addr_A_orig = 64'd0;
assign bufo_54_Clk_A = ap_clk;
assign bufo_54_Din_A = reg_2580;
assign bufo_54_Rst_A = ap_rst;
assign bufo_55_Addr_A = bufo_55_Addr_A_orig << 32'd2;
assign bufo_55_Addr_A_orig = 64'd0;
assign bufo_55_Clk_A = ap_clk;
assign bufo_55_Din_A = reg_2580;
assign bufo_55_Rst_A = ap_rst;
assign bufo_56_Addr_A = bufo_56_Addr_A_orig << 32'd2;
assign bufo_56_Addr_A_orig = 64'd0;
assign bufo_56_Clk_A = ap_clk;
assign bufo_56_Din_A = reg_2580;
assign bufo_56_Rst_A = ap_rst;
assign bufo_57_Addr_A = bufo_57_Addr_A_orig << 32'd2;
assign bufo_57_Addr_A_orig = 64'd0;
assign bufo_57_Clk_A = ap_clk;
assign bufo_57_Din_A = reg_2580;
assign bufo_57_Rst_A = ap_rst;
assign bufo_58_Addr_A = bufo_58_Addr_A_orig << 32'd2;
assign bufo_58_Addr_A_orig = 64'd0;
assign bufo_58_Clk_A = ap_clk;
assign bufo_58_Din_A = reg_2580;
assign bufo_58_Rst_A = ap_rst;
assign bufo_59_Addr_A = bufo_59_Addr_A_orig << 32'd2;
assign bufo_59_Addr_A_orig = 64'd0;
assign bufo_59_Clk_A = ap_clk;
assign bufo_59_Din_A = reg_2580;
assign bufo_59_Rst_A = ap_rst;
assign bufo_5_Addr_A = bufo_5_Addr_A_orig << 32'd2;
assign bufo_5_Addr_A_orig = 64'd0;
assign bufo_5_Clk_A = ap_clk;
assign bufo_5_Din_A = reg_2580;
assign bufo_5_Rst_A = ap_rst;
assign bufo_60_Addr_A = bufo_60_Addr_A_orig << 32'd2;
assign bufo_60_Addr_A_orig = 64'd0;
assign bufo_60_Clk_A = ap_clk;
assign bufo_60_Din_A = reg_2580;
assign bufo_60_Rst_A = ap_rst;
assign bufo_61_Addr_A = bufo_61_Addr_A_orig << 32'd2;
assign bufo_61_Addr_A_orig = 64'd0;
assign bufo_61_Clk_A = ap_clk;
assign bufo_61_Din_A = reg_2580;
assign bufo_61_Rst_A = ap_rst;
assign bufo_62_Addr_A = bufo_62_Addr_A_orig << 32'd2;
assign bufo_62_Addr_A_orig = 64'd0;
assign bufo_62_Clk_A = ap_clk;
assign bufo_62_Din_A = reg_2580;
assign bufo_62_Rst_A = ap_rst;
assign bufo_63_Addr_A = bufo_63_Addr_A_orig << 32'd2;
assign bufo_63_Addr_A_orig = 64'd0;
assign bufo_63_Clk_A = ap_clk;
assign bufo_63_Din_A = reg_2580;
assign bufo_63_Rst_A = ap_rst;
assign bufo_64_Addr_A = bufo_64_Addr_A_orig << 32'd2;
assign bufo_64_Addr_A_orig = 64'd0;
assign bufo_64_Clk_A = ap_clk;
assign bufo_64_Din_A = reg_2580;
assign bufo_64_Rst_A = ap_rst;
assign bufo_65_Addr_A = bufo_65_Addr_A_orig << 32'd2;
assign bufo_65_Addr_A_orig = 64'd0;
assign bufo_65_Clk_A = ap_clk;
assign bufo_65_Din_A = reg_2580;
assign bufo_65_Rst_A = ap_rst;
assign bufo_66_Addr_A = bufo_66_Addr_A_orig << 32'd2;
assign bufo_66_Addr_A_orig = 64'd0;
assign bufo_66_Clk_A = ap_clk;
assign bufo_66_Din_A = reg_2580;
assign bufo_66_Rst_A = ap_rst;
assign bufo_67_Addr_A = bufo_67_Addr_A_orig << 32'd2;
assign bufo_67_Addr_A_orig = 64'd0;
assign bufo_67_Clk_A = ap_clk;
assign bufo_67_Din_A = reg_2580;
assign bufo_67_Rst_A = ap_rst;
assign bufo_68_Addr_A = bufo_68_Addr_A_orig << 32'd2;
assign bufo_68_Addr_A_orig = 64'd0;
assign bufo_68_Clk_A = ap_clk;
assign bufo_68_Din_A = reg_2580;
assign bufo_68_Rst_A = ap_rst;
assign bufo_69_Addr_A = bufo_69_Addr_A_orig << 32'd2;
assign bufo_69_Addr_A_orig = 64'd0;
assign bufo_69_Clk_A = ap_clk;
assign bufo_69_Din_A = reg_2580;
assign bufo_69_Rst_A = ap_rst;
assign bufo_6_Addr_A = bufo_6_Addr_A_orig << 32'd2;
assign bufo_6_Addr_A_orig = 64'd0;
assign bufo_6_Clk_A = ap_clk;
assign bufo_6_Din_A = reg_2580;
assign bufo_6_Rst_A = ap_rst;
assign bufo_70_Addr_A = bufo_70_Addr_A_orig << 32'd2;
assign bufo_70_Addr_A_orig = 64'd0;
assign bufo_70_Clk_A = ap_clk;
assign bufo_70_Din_A = reg_2580;
assign bufo_70_Rst_A = ap_rst;
assign bufo_71_Addr_A = bufo_71_Addr_A_orig << 32'd2;
assign bufo_71_Addr_A_orig = 64'd0;
assign bufo_71_Clk_A = ap_clk;
assign bufo_71_Din_A = reg_2580;
assign bufo_71_Rst_A = ap_rst;
assign bufo_72_Addr_A = bufo_72_Addr_A_orig << 32'd2;
assign bufo_72_Addr_A_orig = 64'd0;
assign bufo_72_Clk_A = ap_clk;
assign bufo_72_Din_A = reg_2580;
assign bufo_72_Rst_A = ap_rst;
assign bufo_73_Addr_A = bufo_73_Addr_A_orig << 32'd2;
assign bufo_73_Addr_A_orig = 64'd0;
assign bufo_73_Clk_A = ap_clk;
assign bufo_73_Din_A = reg_2580;
assign bufo_73_Rst_A = ap_rst;
assign bufo_74_Addr_A = bufo_74_Addr_A_orig << 32'd2;
assign bufo_74_Addr_A_orig = 64'd0;
assign bufo_74_Clk_A = ap_clk;
assign bufo_74_Din_A = reg_2580;
assign bufo_74_Rst_A = ap_rst;
assign bufo_75_Addr_A = bufo_75_Addr_A_orig << 32'd2;
assign bufo_75_Addr_A_orig = 64'd0;
assign bufo_75_Clk_A = ap_clk;
assign bufo_75_Din_A = reg_2580;
assign bufo_75_Rst_A = ap_rst;
assign bufo_76_Addr_A = bufo_76_Addr_A_orig << 32'd2;
assign bufo_76_Addr_A_orig = 64'd0;
assign bufo_76_Clk_A = ap_clk;
assign bufo_76_Din_A = reg_2580;
assign bufo_76_Rst_A = ap_rst;
assign bufo_77_Addr_A = bufo_77_Addr_A_orig << 32'd2;
assign bufo_77_Addr_A_orig = 64'd0;
assign bufo_77_Clk_A = ap_clk;
assign bufo_77_Din_A = reg_2580;
assign bufo_77_Rst_A = ap_rst;
assign bufo_78_Addr_A = bufo_78_Addr_A_orig << 32'd2;
assign bufo_78_Addr_A_orig = 64'd0;
assign bufo_78_Clk_A = ap_clk;
assign bufo_78_Din_A = reg_2580;
assign bufo_78_Rst_A = ap_rst;
assign bufo_79_Addr_A = bufo_79_Addr_A_orig << 32'd2;
assign bufo_79_Addr_A_orig = 64'd0;
assign bufo_79_Clk_A = ap_clk;
assign bufo_79_Din_A = reg_2580;
assign bufo_79_Rst_A = ap_rst;
assign bufo_7_Addr_A = bufo_7_Addr_A_orig << 32'd2;
assign bufo_7_Addr_A_orig = 64'd0;
assign bufo_7_Clk_A = ap_clk;
assign bufo_7_Din_A = reg_2580;
assign bufo_7_Rst_A = ap_rst;
assign bufo_80_Addr_A = bufo_80_Addr_A_orig << 32'd2;
assign bufo_80_Addr_A_orig = 64'd0;
assign bufo_80_Clk_A = ap_clk;
assign bufo_80_Din_A = reg_2580;
assign bufo_80_Rst_A = ap_rst;
assign bufo_81_Addr_A = bufo_81_Addr_A_orig << 32'd2;
assign bufo_81_Addr_A_orig = 64'd0;
assign bufo_81_Clk_A = ap_clk;
assign bufo_81_Din_A = reg_2580;
assign bufo_81_Rst_A = ap_rst;
assign bufo_82_Addr_A = bufo_82_Addr_A_orig << 32'd2;
assign bufo_82_Addr_A_orig = 64'd0;
assign bufo_82_Clk_A = ap_clk;
assign bufo_82_Din_A = reg_2580;
assign bufo_82_Rst_A = ap_rst;
assign bufo_83_Addr_A = bufo_83_Addr_A_orig << 32'd2;
assign bufo_83_Addr_A_orig = 64'd0;
assign bufo_83_Clk_A = ap_clk;
assign bufo_83_Din_A = reg_2580;
assign bufo_83_Rst_A = ap_rst;
assign bufo_84_Addr_A = bufo_84_Addr_A_orig << 32'd2;
assign bufo_84_Addr_A_orig = 64'd0;
assign bufo_84_Clk_A = ap_clk;
assign bufo_84_Din_A = reg_2580;
assign bufo_84_Rst_A = ap_rst;
assign bufo_85_Addr_A = bufo_85_Addr_A_orig << 32'd2;
assign bufo_85_Addr_A_orig = 64'd0;
assign bufo_85_Clk_A = ap_clk;
assign bufo_85_Din_A = reg_2580;
assign bufo_85_Rst_A = ap_rst;
assign bufo_86_Addr_A = bufo_86_Addr_A_orig << 32'd2;
assign bufo_86_Addr_A_orig = 64'd0;
assign bufo_86_Clk_A = ap_clk;
assign bufo_86_Din_A = reg_2580;
assign bufo_86_Rst_A = ap_rst;
assign bufo_87_Addr_A = bufo_87_Addr_A_orig << 32'd2;
assign bufo_87_Addr_A_orig = 64'd0;
assign bufo_87_Clk_A = ap_clk;
assign bufo_87_Din_A = reg_2580;
assign bufo_87_Rst_A = ap_rst;
assign bufo_88_Addr_A = bufo_88_Addr_A_orig << 32'd2;
assign bufo_88_Addr_A_orig = 64'd0;
assign bufo_88_Clk_A = ap_clk;
assign bufo_88_Din_A = reg_2580;
assign bufo_88_Rst_A = ap_rst;
assign bufo_89_Addr_A = bufo_89_Addr_A_orig << 32'd2;
assign bufo_89_Addr_A_orig = 64'd0;
assign bufo_89_Clk_A = ap_clk;
assign bufo_89_Din_A = reg_2580;
assign bufo_89_Rst_A = ap_rst;
assign bufo_8_Addr_A = bufo_8_Addr_A_orig << 32'd2;
assign bufo_8_Addr_A_orig = 64'd0;
assign bufo_8_Clk_A = ap_clk;
assign bufo_8_Din_A = reg_2580;
assign bufo_8_Rst_A = ap_rst;
assign bufo_90_Addr_A = bufo_90_Addr_A_orig << 32'd2;
assign bufo_90_Addr_A_orig = 64'd0;
assign bufo_90_Clk_A = ap_clk;
assign bufo_90_Din_A = reg_2580;
assign bufo_90_Rst_A = ap_rst;
assign bufo_91_Addr_A = bufo_91_Addr_A_orig << 32'd2;
assign bufo_91_Addr_A_orig = 64'd0;
assign bufo_91_Clk_A = ap_clk;
assign bufo_91_Din_A = reg_2580;
assign bufo_91_Rst_A = ap_rst;
assign bufo_92_Addr_A = bufo_92_Addr_A_orig << 32'd2;
assign bufo_92_Addr_A_orig = 64'd0;
assign bufo_92_Clk_A = ap_clk;
assign bufo_92_Din_A = reg_2580;
assign bufo_92_Rst_A = ap_rst;
assign bufo_93_Addr_A = bufo_93_Addr_A_orig << 32'd2;
assign bufo_93_Addr_A_orig = 64'd0;
assign bufo_93_Clk_A = ap_clk;
assign bufo_93_Din_A = reg_2580;
assign bufo_93_Rst_A = ap_rst;
assign bufo_94_Addr_A = bufo_94_Addr_A_orig << 32'd2;
assign bufo_94_Addr_A_orig = 64'd0;
assign bufo_94_Clk_A = ap_clk;
assign bufo_94_Din_A = reg_2580;
assign bufo_94_Rst_A = ap_rst;
assign bufo_95_Addr_A = bufo_95_Addr_A_orig << 32'd2;
assign bufo_95_Addr_A_orig = 64'd0;
assign bufo_95_Clk_A = ap_clk;
assign bufo_95_Din_A = reg_2580;
assign bufo_95_Rst_A = ap_rst;
assign bufo_96_Addr_A = bufo_96_Addr_A_orig << 32'd2;
assign bufo_96_Addr_A_orig = 64'd0;
assign bufo_96_Clk_A = ap_clk;
assign bufo_96_Din_A = reg_2580;
assign bufo_96_Rst_A = ap_rst;
assign bufo_97_Addr_A = bufo_97_Addr_A_orig << 32'd2;
assign bufo_97_Addr_A_orig = 64'd0;
assign bufo_97_Clk_A = ap_clk;
assign bufo_97_Din_A = reg_2580;
assign bufo_97_Rst_A = ap_rst;
assign bufo_98_Addr_A = bufo_98_Addr_A_orig << 32'd2;
assign bufo_98_Addr_A_orig = 64'd0;
assign bufo_98_Clk_A = ap_clk;
assign bufo_98_Din_A = reg_2580;
assign bufo_98_Rst_A = ap_rst;
assign bufo_99_Addr_A = bufo_99_Addr_A_orig << 32'd2;
assign bufo_99_Addr_A_orig = 64'd0;
assign bufo_99_Clk_A = ap_clk;
assign bufo_99_Din_A = reg_2580;
assign bufo_99_Rst_A = ap_rst;
assign bufo_9_Addr_A = bufo_9_Addr_A_orig << 32'd2;
assign bufo_9_Addr_A_orig = 64'd0;
assign bufo_9_Clk_A = ap_clk;
assign bufo_9_Din_A = reg_2580;
assign bufo_9_Rst_A = ap_rst;
assign bufw_Addr_A = bufw_Addr_A_orig << 32'd4;
assign bufw_Addr_A_orig = phi_mul_reg_2272;
assign bufw_Clk_A = ap_clk;
assign bufw_Din_A = 128'd0;
assign bufw_Rst_A = ap_rst;
assign bufw_WEN_A = 16'd0;
assign grp_fu_2564_p0 = tmp_reg_3481;
assign grp_fu_2564_p1 = tmp_1_reg_3486;
assign grp_fu_2568_p0 = tmp_6_reg_3491;
assign grp_fu_2568_p1 = tmp_8_reg_3496;
assign grp_fu_2572_p0 = tmp_4_reg_3501;
assign grp_fu_2572_p1 = tmp_11_reg_3506;
assign grp_fu_2576_p0 = tmp_13_reg_3511;
assign grp_fu_2576_p1 = tmp_15_reg_3516;
assign next_mul_fu_2714_p2 = (64'd25 + phi_mul_reg_2272);
assign tmp_1_fu_2724_p1 = bufi_Dout_A[31:0];
assign tmp_fu_2720_p1 = bufw_Dout_A[31:0];
assign to_b_V_fu_2820_p2 = (7'd1 + p_s_reg_2284);
endmodule //convolve_kernel
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
limbus_cpu_cpu_debug_slave_tck the_limbus_cpu_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
limbus_cpu_cpu_debug_slave_sysclk the_limbus_cpu_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic limbus_cpu_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam limbus_cpu_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// limbus_cpu_cpu_debug_slave_phy.sld_instance_index = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_ir_width = 2,
// limbus_cpu_cpu_debug_slave_phy.sld_mfg_id = 70,
// limbus_cpu_cpu_debug_slave_phy.sld_sim_action = "",
// limbus_cpu_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_sim_total_length = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_type_id = 34,
// limbus_cpu_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY8.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision
// 09/26/12 - Initial functional version.
// 05/24/13 - Add CARRY_TYPE, CI_TOP
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CARRY8 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CARRY_TYPE = "SINGLE_CY8"
)(
output [7:0] CO,
output [7:0] O,
input CI,
input CI_TOP,
input [7:0] DI,
input [7:0] S
);
// define constants
localparam MODULE_NAME = "CARRY8";
// Parameter encodings and registers
localparam CARRY_TYPE_DUAL_CY4 = 1;
localparam CARRY_TYPE_SINGLE_CY8 = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "CARRY8_dr.v"
`else
reg [80:1] CARRY_TYPE_REG = CARRY_TYPE;
`endif
`ifdef XIL_XECLIB
wire CARRY_TYPE_BIN;
`else
reg CARRY_TYPE_BIN;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire CI_TOP_in;
wire CI_in;
wire [7:0] DI_in;
wire [7:0] S_in;
assign CI_TOP_in = ((CI_TOP !== 1'bz) &&
((CARRY_TYPE_BIN == CARRY_TYPE_DUAL_CY4) && CI_TOP)) ||
((CARRY_TYPE_BIN == CARRY_TYPE_SINGLE_CY8) && CO[3]); // rv 0
assign CI_in = (CI !== 1'bz) && CI; // rv 0
assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0
assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0
assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0
assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0
assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0
assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0
assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0
assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0
assign S_in[7] = (S[7] !== 1'bz) && S[7]; // rv 0
assign S_in[6] = (S[6] !== 1'bz) && S[6]; // rv 0
assign S_in[5] = (S[5] !== 1'bz) && S[5]; // rv 0
assign S_in[4] = (S[4] !== 1'bz) && S[4]; // rv 0
assign S_in[3] = (S[3] !== 1'bz) && S[3]; // rv 0
assign S_in[2] = (S[2] !== 1'bz) && S[2]; // rv 0
assign S_in[1] = (S[1] !== 1'bz) && S[1]; // rv 0
assign S_in[0] = (S[0] !== 1'bz) && S[0]; // rv 0
`ifndef XIL_XECLIB
initial begin
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CARRY_TYPE_BIN =
(CARRY_TYPE_REG == "SINGLE_CY8") ? CARRY_TYPE_SINGLE_CY8 :
(CARRY_TYPE_REG == "DUAL_CY4") ? CARRY_TYPE_DUAL_CY4 :
CARRY_TYPE_SINGLE_CY8;
`else
always @(trig_attr) begin
#1;
CARRY_TYPE_BIN =
(CARRY_TYPE_REG == "SINGLE_CY8") ? CARRY_TYPE_SINGLE_CY8 :
(CARRY_TYPE_REG == "DUAL_CY4") ? CARRY_TYPE_DUAL_CY4 :
CARRY_TYPE_SINGLE_CY8;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CARRY_TYPE_REG != "SINGLE_CY8") &&
(CARRY_TYPE_REG != "DUAL_CY4"))) begin
$display("Error: [Unisim %s-101] CARRY_TYPE attribute is set to %s. Legal values for this attribute are SINGLE_CY8 or DUAL_CY4. Instance: %m", MODULE_NAME, CARRY_TYPE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
wire [7:0] CO_fb;
assign CO_fb = {CO[6:4], CI_TOP_in, CO[2:0], CI_in};
assign O = S_in ^ CO_fb;
assign CO = (S_in & CO_fb) | (~S_in & DI_in);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CI => CO[4]) = (0:0:0, 0:0:0);
(CI => CO[5]) = (0:0:0, 0:0:0);
(CI => CO[6]) = (0:0:0, 0:0:0);
(CI => CO[7]) = (0:0:0, 0:0:0);
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CI => O[4]) = (0:0:0, 0:0:0);
(CI => O[5]) = (0:0:0, 0:0:0);
(CI => O[6]) = (0:0:0, 0:0:0);
(CI => O[7]) = (0:0:0, 0:0:0);
(CI_TOP => CO[4]) = (0:0:0, 0:0:0);
(CI_TOP => CO[5]) = (0:0:0, 0:0:0);
(CI_TOP => CO[6]) = (0:0:0, 0:0:0);
(CI_TOP => CO[7]) = (0:0:0, 0:0:0);
(CI_TOP => O[4]) = (0:0:0, 0:0:0);
(CI_TOP => O[5]) = (0:0:0, 0:0:0);
(CI_TOP => O[6]) = (0:0:0, 0:0:0);
(CI_TOP => O[7]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[4]) = (0:0:0, 0:0:0);
(DI[0] => CO[5]) = (0:0:0, 0:0:0);
(DI[0] => CO[6]) = (0:0:0, 0:0:0);
(DI[0] => CO[7]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[0] => O[4]) = (0:0:0, 0:0:0);
(DI[0] => O[5]) = (0:0:0, 0:0:0);
(DI[0] => O[6]) = (0:0:0, 0:0:0);
(DI[0] => O[7]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[4]) = (0:0:0, 0:0:0);
(DI[1] => CO[5]) = (0:0:0, 0:0:0);
(DI[1] => CO[6]) = (0:0:0, 0:0:0);
(DI[1] => CO[7]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => O[4]) = (0:0:0, 0:0:0);
(DI[1] => O[5]) = (0:0:0, 0:0:0);
(DI[1] => O[6]) = (0:0:0, 0:0:0);
(DI[1] => O[7]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[4]) = (0:0:0, 0:0:0);
(DI[2] => CO[5]) = (0:0:0, 0:0:0);
(DI[2] => CO[6]) = (0:0:0, 0:0:0);
(DI[2] => CO[7]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => O[4]) = (0:0:0, 0:0:0);
(DI[2] => O[5]) = (0:0:0, 0:0:0);
(DI[2] => O[6]) = (0:0:0, 0:0:0);
(DI[2] => O[7]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[4]) = (0:0:0, 0:0:0);
(DI[3] => CO[5]) = (0:0:0, 0:0:0);
(DI[3] => CO[6]) = (0:0:0, 0:0:0);
(DI[3] => CO[7]) = (0:0:0, 0:0:0);
(DI[3] => O[4]) = (0:0:0, 0:0:0);
(DI[3] => O[5]) = (0:0:0, 0:0:0);
(DI[3] => O[6]) = (0:0:0, 0:0:0);
(DI[3] => O[7]) = (0:0:0, 0:0:0);
(DI[4] => CO[4]) = (0:0:0, 0:0:0);
(DI[4] => CO[5]) = (0:0:0, 0:0:0);
(DI[4] => CO[6]) = (0:0:0, 0:0:0);
(DI[4] => CO[7]) = (0:0:0, 0:0:0);
(DI[4] => O[5]) = (0:0:0, 0:0:0);
(DI[4] => O[6]) = (0:0:0, 0:0:0);
(DI[4] => O[7]) = (0:0:0, 0:0:0);
(DI[5] => CO[5]) = (0:0:0, 0:0:0);
(DI[5] => CO[6]) = (0:0:0, 0:0:0);
(DI[5] => CO[7]) = (0:0:0, 0:0:0);
(DI[5] => O[6]) = (0:0:0, 0:0:0);
(DI[5] => O[7]) = (0:0:0, 0:0:0);
(DI[6] => CO[6]) = (0:0:0, 0:0:0);
(DI[6] => CO[7]) = (0:0:0, 0:0:0);
(DI[6] => O[7]) = (0:0:0, 0:0:0);
(DI[7] => CO[7]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[0] => CO[4]) = (0:0:0, 0:0:0);
(S[0] => CO[5]) = (0:0:0, 0:0:0);
(S[0] => CO[6]) = (0:0:0, 0:0:0);
(S[0] => CO[7]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[0] => O[4]) = (0:0:0, 0:0:0);
(S[0] => O[5]) = (0:0:0, 0:0:0);
(S[0] => O[6]) = (0:0:0, 0:0:0);
(S[0] => O[7]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => CO[4]) = (0:0:0, 0:0:0);
(S[1] => CO[5]) = (0:0:0, 0:0:0);
(S[1] => CO[6]) = (0:0:0, 0:0:0);
(S[1] => CO[7]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[1] => O[4]) = (0:0:0, 0:0:0);
(S[1] => O[5]) = (0:0:0, 0:0:0);
(S[1] => O[6]) = (0:0:0, 0:0:0);
(S[1] => O[7]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => CO[4]) = (0:0:0, 0:0:0);
(S[2] => CO[5]) = (0:0:0, 0:0:0);
(S[2] => CO[6]) = (0:0:0, 0:0:0);
(S[2] => CO[7]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[2] => O[4]) = (0:0:0, 0:0:0);
(S[2] => O[5]) = (0:0:0, 0:0:0);
(S[2] => O[6]) = (0:0:0, 0:0:0);
(S[2] => O[7]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => CO[4]) = (0:0:0, 0:0:0);
(S[3] => CO[5]) = (0:0:0, 0:0:0);
(S[3] => CO[6]) = (0:0:0, 0:0:0);
(S[3] => CO[7]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
(S[3] => O[4]) = (0:0:0, 0:0:0);
(S[3] => O[5]) = (0:0:0, 0:0:0);
(S[3] => O[6]) = (0:0:0, 0:0:0);
(S[3] => O[7]) = (0:0:0, 0:0:0);
(S[4] => CO[4]) = (0:0:0, 0:0:0);
(S[4] => CO[5]) = (0:0:0, 0:0:0);
(S[4] => CO[6]) = (0:0:0, 0:0:0);
(S[4] => CO[7]) = (0:0:0, 0:0:0);
(S[4] => O[4]) = (0:0:0, 0:0:0);
(S[4] => O[5]) = (0:0:0, 0:0:0);
(S[4] => O[6]) = (0:0:0, 0:0:0);
(S[4] => O[7]) = (0:0:0, 0:0:0);
(S[5] => CO[5]) = (0:0:0, 0:0:0);
(S[5] => CO[6]) = (0:0:0, 0:0:0);
(S[5] => CO[7]) = (0:0:0, 0:0:0);
(S[5] => O[5]) = (0:0:0, 0:0:0);
(S[5] => O[6]) = (0:0:0, 0:0:0);
(S[5] => O[7]) = (0:0:0, 0:0:0);
(S[6] => CO[6]) = (0:0:0, 0:0:0);
(S[6] => CO[7]) = (0:0:0, 0:0:0);
(S[6] => O[6]) = (0:0:0, 0:0:0);
(S[6] => O[7]) = (0:0:0, 0:0:0);
(S[7] => CO[7]) = (0:0:0, 0:0:0);
(S[7] => O[7]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for struct signal bit selection.
//
// This test is to check that bit selection of multi-dimensional signal inside
// of a packed struct works. Currently +: and -: blow up with packed structs.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2013 by Jie Xu.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef struct packed {
logic [15:0] channel;
logic [15:0] others;
} buss_t;
buss_t b;
reg [7:0] a;
reg [7:0] c;
reg [7:0] d;
union packed {
logic [31:0] [7:0] idx;
struct packed {
logic [15:0] z, y, x;
logic [25:0] [7:0] r;
} nam;
} gpr;
reg [14:0] gpr_a;
initial begin
b = {16'h8765,16'h4321};
a = b[19:12]; // This works
c = b[8+:8]; // This fails
d = b[11-:8]; // This fails
`checkh(a, 8'h54);
`checkh(c, 8'h43);
`checkh(d, 8'h32);
gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345;
`checkh (gpr[255:255-14], 15'h091a);
gpr_a = gpr.nam.z[15:1];
`checkh (gpr_a, 15'h091a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_TB_V
`define SKY130_FD_SC_LS__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_ls__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:42:08 03/17/2015
// Design Name: or_gate
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/or_gate/tb_or_gate.v
// Project Name: or_gate
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: or_gate
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_or_gate;
// Inputs
reg [9:0] i = 10'b00000000;
integer file;
reg valid;
// Outputs
wire o;
// Instantiate the Unit Under Test (UUT)
or_gate uut (
.i(i),
.o(o)
);
initial begin
// Initialize Inputs
i = 0;
file = $fopen("or_gate_test.log", "w");
valid = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin: test
#1 i = i + 1;
#1
if((i > 0 & o == 0) | (i == 0 & o == 1))
begin
$fwrite(file, "Output invalid for input %b = %d\n", i, i);
valid = 0;
end
if(i == 10'b1111111111)
begin
if(valid == 1'b1) $fwrite("Test successful.\n");
$fclose(file);
end;
end
endmodule
|
module src_mux (
src_constant,
sgpr_rd_data,
vgpr_source_data,
exec_rd_exec_value,
exec_rd_vcc_value,
exec_rd_m0_value,
exec_rd_scc_value,
literal_constant,
source_mux_select,
source_data
);
input [9:0] src_constant;
input [31:0] sgpr_rd_data;
input [2047:0] vgpr_source_data;
input [63:0] exec_rd_exec_value;
input [63:0] exec_rd_vcc_value;
input [31:0] exec_rd_m0_value;
input exec_rd_scc_value;
input [3:0] source_mux_select;
input [31:0] literal_constant;
output [2047:0] source_data;
reg [2047:0] source_data;
always @ (src_constant or sgpr_rd_data or
vgpr_source_data or exec_rd_exec_value or
exec_rd_vcc_value or source_mux_select or literal_constant) begin
casex(source_mux_select)
4'b0000 : source_data <= {64{literal_constant}};
4'b0001 : source_data <= {64{{22{src_constant[9]}}, src_constant}};
4'b0010 : source_data <= vgpr_source_data;
4'b0011 : source_data <= {64{sgpr_rd_data}};
4'b0100 : source_data <= {64{exec_rd_vcc_value[31:0]}};
4'b0101 : source_data <= {64{exec_rd_vcc_value[63:32]}};
4'b0110 : source_data <= {64{exec_rd_m0_value}};
4'b0111 : source_data <= {64{exec_rd_exec_value[31:0]}};
4'b1000 : source_data <= {64{exec_rd_exec_value[63:32]}};
4'b1001 : source_data <= {64{31'b0, !(&exec_rd_vcc_value)}};
4'b1010 : source_data <= {64{31'b0, !(&exec_rd_exec_value)}};
4'b1011 : source_data <= {64{31'b0, exec_rd_scc_value}};
default: source_data <= {2048{1'bx}};
endcase
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
|
`timescale 1ns / 1ps
// This module verifies correct register file behavior.
module test_alu();
reg clk_o;
reg reset_o;
reg [15:0] story_o;
reg [63:0] inA_o, inB_o;
reg cflag_o;
wire [63:0] out_i;
wire nflag_i, vflag_i, zflag_i, cflag_i;
reg sum_en_o;
reg and_en_o;
reg xor_en_o;
reg invB_en_o;
reg lsh_en_o;
reg rsh_en_o;
reg ltu_en_o; // See issue https://github.com/KestrelComputer/polaris/issues/18
reg lts_en_o; // See issue https://github.com/KestrelComputer/polaris/issues/18
alu a(
.inA_i(inA_o),
.inB_i(inB_o),
.cflag_i(cflag_o),
.out_o(out_i),
.vflag_o(vflag_i),
.cflag_o(cflag_i),
.zflag_o(zflag_i),
.sum_en_i(sum_en_o),
.and_en_i(and_en_o),
.xor_en_i(xor_en_o),
.invB_en_i(invB_en_o),
.lsh_en_i(lsh_en_o),
.rsh_en_i(rsh_en_o),
.ltu_en_i(ltu_en_o),
.lts_en_i(lts_en_o)
);
always begin
#20 clk_o <= ~clk_o;
end
task tick;
input [15:0] story;
begin
story_o <= story;
@(posedge clk_o);
@(negedge clk_o);
end
endtask
task assert_out;
input [63:0] expected;
begin
if(expected !== out_i) begin
$display("@E %04X OUT_O Expected $%016X, got $%016X", story_o, expected, out_i);
$stop;
end
end
endtask
task assert_v;
input expected;
begin
if(expected !== vflag_i) begin
$display("@E %04X VFLAG_O Expected %d, got %d", story_o, expected, vflag_i);
$stop;
end
end
endtask
task assert_c;
input expected;
begin
if(expected !== cflag_i) begin
$display("@E %04X CFLAG_O Expected %d, got %d", story_o, expected, cflag_i);
$stop;
end
end
endtask
task assert_z;
input expected;
begin
if(expected !== zflag_i) begin
$display("@E %04X ZFLAG_O Expected %d, got %d", story_o, expected, zflag_i);
$stop;
end
end
endtask
task check_sum_bit;
input [15:0] story;
input [63:0] base;
input cin;
input carry;
input overflow;
input zero;
begin
inA_o <= base;
inB_o <= base;
cflag_o <= cin;
invB_en_o <= 0;
sum_en_o <= 1;
and_en_o <= 0;
xor_en_o <= 0;
lsh_en_o <= 0;
rsh_en_o <= 0;
ltu_en_o <= 0;
lts_en_o <= 0;
tick(story);
assert_out({base[62:0], cin});
assert_c(carry);
assert_v(overflow);
assert_z(zero);
end
endtask
task check_diff_bit;
input [15:0] story;
input [63:0] base;
input carry;
input overflow;
input zero;
begin
inA_o <= base;
inB_o <= base;
cflag_o <= 1;
invB_en_o <= 1;
sum_en_o <= 1;
and_en_o <= 0;
xor_en_o <= 0;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story);
assert_out(0);
assert_c(carry);
assert_v(overflow);
assert_z(zero);
inA_o <= base;
inB_o <= base;
cflag_o <= 0;
invB_en_o <= 1;
sum_en_o <= 1;
and_en_o <= 0;
xor_en_o <= 0;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story | 16'h8000);
assert_out(-1);
assert_c(~carry);
assert_v(overflow);
assert_z(0);
end
endtask
task check_and;
input [15:0] story;
input [63:0] base;
begin
inA_o <= 64'hFFFF_FFFF_FFFF_FFFF;
inB_o <= base;
invB_en_o <= 0;
sum_en_o <= 0;
and_en_o <= 1;
xor_en_o <= 0;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story);
assert_out(base);
end
endtask
task check_xor;
input [15:0] story;
input [63:0] base;
begin
inA_o <= 64'h0000_0000_0000_0000;
inB_o <= base;
invB_en_o <= 0;
sum_en_o <= 0;
and_en_o <= 0;
xor_en_o <= 1;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story);
assert_out(base);
inA_o <= base;
inB_o <= base;
invB_en_o <= 0;
sum_en_o <= 0;
and_en_o <= 0;
xor_en_o <= 1;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story | 16'h8000);
assert_out(0);
end
endtask
task check_or;
input [15:0] story;
input [63:0] base;
begin
inA_o <= 64'h0000_0000_0000_0000;
inB_o <= base;
invB_en_o <= 0;
sum_en_o <= 0;
and_en_o <= 1;
xor_en_o <= 1;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story);
assert_out(base);
inA_o <= 64'hFFFF_FFFF_FFFF_FFFF;
inB_o <= base;
invB_en_o <= 0;
sum_en_o <= 0;
and_en_o <= 1;
xor_en_o <= 1;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story | 16'h8000);
assert_out(64'hFFFF_FFFF_FFFF_FFFF);
end
endtask
task check_sh;
input [15:0] story;
input [5:0] shamt;
input [63:0] expected;
input [63:0] a;
input cflag;
input lsh;
input rsh;
begin
inA_o <= a;
inB_o <= {58'd0, shamt};
invB_en_o <= 0;
cflag_o <= cflag;
sum_en_o <= 0;
and_en_o <= 0;
xor_en_o <= 0;
lsh_en_o <= lsh;
rsh_en_o <= rsh;
lts_en_o <= 0;
ltu_en_o <= 0;
tick(story);
assert_out(expected);
end
endtask
task check_lt;
input [15:0] story;
input [63:0] a;
input [63:0] b;
input [63:0] expected;
input lts;
input ltu;
begin
inA_o <= a;
inB_o <= b;
cflag_o <= 1'b1;
invB_en_o <= 1'b1;
sum_en_o <= 0;
and_en_o <= 0;
xor_en_o <= 0;
lsh_en_o <= 0;
rsh_en_o <= 0;
lts_en_o <= lts;
ltu_en_o <= ltu;
tick(story);
assert_out(expected);
end
endtask
task check_lsh;
input [15:0] story;
input [5:0] shamt;
input [63:0] expected;
begin
check_sh(story, shamt, expected, 64'h0000_0000_0000_0001, 0, 1, 0);
end
endtask
task check_rsh;
input [15:0] story;
input [5:0] shamt;
input [63:0] expected;
begin
check_sh(story, shamt, expected, 64'h8000_0000_0000_0000, 0, 0, 1);
end
endtask
task check_asr;
input [15:0] story;
input [5:0] shamt;
input [63:0] expected;
begin
check_sh(story, shamt, expected, 64'h8000_0000_0000_0000, 1, 0, 1);
end
endtask
task check_asr_2;
input [15:0] story;
input [5:0] shamt;
input [63:0] expected;
begin
check_sh(story, shamt, expected, 64'h4000_0000_0000_0000, 1, 0, 1);
end
endtask
initial begin
clk_o <= 0;
// We expect the ALU to add two 64-bit numbers, and a carry bit.
check_sum_bit(16'h0000, 64'h0000_0000_0000_0001, 0, 0, 0, 0);
check_sum_bit(16'h0001, 64'h0000_0000_0000_0002, 0, 0, 0, 0);
check_sum_bit(16'h0002, 64'h0000_0000_0000_0004, 0, 0, 0, 0);
check_sum_bit(16'h0003, 64'h0000_0000_0000_0008, 0, 0, 0, 0);
check_sum_bit(16'h0004, 64'h0000_0000_0000_0010, 0, 0, 0, 0);
check_sum_bit(16'h0005, 64'h0000_0000_0000_0020, 0, 0, 0, 0);
check_sum_bit(16'h0006, 64'h0000_0000_0000_0040, 0, 0, 0, 0);
check_sum_bit(16'h0007, 64'h0000_0000_0000_0080, 0, 0, 0, 0);
check_sum_bit(16'h0008, 64'h0000_0000_0000_0100, 0, 0, 0, 0);
check_sum_bit(16'h0009, 64'h0000_0000_0000_0200, 0, 0, 0, 0);
check_sum_bit(16'h000A, 64'h0000_0000_0000_0400, 0, 0, 0, 0);
check_sum_bit(16'h000B, 64'h0000_0000_0000_0800, 0, 0, 0, 0);
check_sum_bit(16'h000C, 64'h0000_0000_0000_1000, 0, 0, 0, 0);
check_sum_bit(16'h000D, 64'h0000_0000_0000_2000, 0, 0, 0, 0);
check_sum_bit(16'h000E, 64'h0000_0000_0000_4000, 0, 0, 0, 0);
check_sum_bit(16'h000F, 64'h0000_0000_0000_8000, 0, 0, 0, 0);
check_sum_bit(16'h0010, 64'h0000_0000_0001_0000, 0, 0, 0, 0);
check_sum_bit(16'h0011, 64'h0000_0000_0002_0000, 0, 0, 0, 0);
check_sum_bit(16'h0012, 64'h0000_0000_0004_0000, 0, 0, 0, 0);
check_sum_bit(16'h0013, 64'h0000_0000_0008_0000, 0, 0, 0, 0);
check_sum_bit(16'h0014, 64'h0000_0000_0010_0000, 0, 0, 0, 0);
check_sum_bit(16'h0015, 64'h0000_0000_0020_0000, 0, 0, 0, 0);
check_sum_bit(16'h0016, 64'h0000_0000_0040_0000, 0, 0, 0, 0);
check_sum_bit(16'h0017, 64'h0000_0000_0080_0000, 0, 0, 0, 0);
check_sum_bit(16'h0018, 64'h0000_0000_0100_0000, 0, 0, 0, 0);
check_sum_bit(16'h0019, 64'h0000_0000_0200_0000, 0, 0, 0, 0);
check_sum_bit(16'h001A, 64'h0000_0000_0400_0000, 0, 0, 0, 0);
check_sum_bit(16'h001B, 64'h0000_0000_0800_0000, 0, 0, 0, 0);
check_sum_bit(16'h001C, 64'h0000_0000_1000_0000, 0, 0, 0, 0);
check_sum_bit(16'h001D, 64'h0000_0000_2000_0000, 0, 0, 0, 0);
check_sum_bit(16'h001E, 64'h0000_0000_4000_0000, 0, 0, 0, 0);
check_sum_bit(16'h001F, 64'h0000_0000_8000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0020, 64'h0000_0001_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0021, 64'h0000_0002_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0022, 64'h0000_0004_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0023, 64'h0000_0008_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0024, 64'h0000_0010_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0025, 64'h0000_0020_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0026, 64'h0000_0040_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0027, 64'h0000_0080_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0028, 64'h0000_0100_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0029, 64'h0000_0200_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002A, 64'h0000_0400_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002B, 64'h0000_0800_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002C, 64'h0000_1000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002D, 64'h0000_2000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002E, 64'h0000_4000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h002F, 64'h0000_8000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0030, 64'h0001_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0031, 64'h0002_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0032, 64'h0004_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0033, 64'h0008_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0034, 64'h0010_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0035, 64'h0020_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0036, 64'h0040_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0037, 64'h0080_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0038, 64'h0100_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h0039, 64'h0200_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h003A, 64'h0400_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h003B, 64'h0800_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h003C, 64'h1000_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h003D, 64'h2000_0000_0000_0000, 0, 0, 0, 0);
check_sum_bit(16'h003E, 64'h4000_0000_0000_0000, 0, 0, 1, 0);
check_sum_bit(16'h003F, 64'h8000_0000_0000_0000, 0, 1, 1, 1);
check_sum_bit(16'h0100, 64'h0000_0000_0000_0001, 1, 0, 0, 0);
check_sum_bit(16'h0101, 64'h0000_0000_0000_0002, 1, 0, 0, 0);
check_sum_bit(16'h0102, 64'h0000_0000_0000_0004, 1, 0, 0, 0);
check_sum_bit(16'h0103, 64'h0000_0000_0000_0008, 1, 0, 0, 0);
check_sum_bit(16'h0104, 64'h0000_0000_0000_0010, 1, 0, 0, 0);
check_sum_bit(16'h0105, 64'h0000_0000_0000_0020, 1, 0, 0, 0);
check_sum_bit(16'h0106, 64'h0000_0000_0000_0040, 1, 0, 0, 0);
check_sum_bit(16'h0107, 64'h0000_0000_0000_0080, 1, 0, 0, 0);
check_sum_bit(16'h0108, 64'h0000_0000_0000_0100, 1, 0, 0, 0);
check_sum_bit(16'h0109, 64'h0000_0000_0000_0200, 1, 0, 0, 0);
check_sum_bit(16'h010A, 64'h0000_0000_0000_0400, 1, 0, 0, 0);
check_sum_bit(16'h010B, 64'h0000_0000_0000_0800, 1, 0, 0, 0);
check_sum_bit(16'h010C, 64'h0000_0000_0000_1000, 1, 0, 0, 0);
check_sum_bit(16'h010D, 64'h0000_0000_0000_2000, 1, 0, 0, 0);
check_sum_bit(16'h010E, 64'h0000_0000_0000_4000, 1, 0, 0, 0);
check_sum_bit(16'h010F, 64'h0000_0000_0000_8000, 1, 0, 0, 0);
check_sum_bit(16'h0110, 64'h0000_0000_0001_0000, 1, 0, 0, 0);
check_sum_bit(16'h0111, 64'h0000_0000_0002_0000, 1, 0, 0, 0);
check_sum_bit(16'h0112, 64'h0000_0000_0004_0000, 1, 0, 0, 0);
check_sum_bit(16'h0113, 64'h0000_0000_0008_0000, 1, 0, 0, 0);
check_sum_bit(16'h0114, 64'h0000_0000_0010_0000, 1, 0, 0, 0);
check_sum_bit(16'h0115, 64'h0000_0000_0020_0000, 1, 0, 0, 0);
check_sum_bit(16'h0116, 64'h0000_0000_0040_0000, 1, 0, 0, 0);
check_sum_bit(16'h0117, 64'h0000_0000_0080_0000, 1, 0, 0, 0);
check_sum_bit(16'h0118, 64'h0000_0000_0100_0000, 1, 0, 0, 0);
check_sum_bit(16'h0119, 64'h0000_0000_0200_0000, 1, 0, 0, 0);
check_sum_bit(16'h011A, 64'h0000_0000_0400_0000, 1, 0, 0, 0);
check_sum_bit(16'h011B, 64'h0000_0000_0800_0000, 1, 0, 0, 0);
check_sum_bit(16'h011C, 64'h0000_0000_1000_0000, 1, 0, 0, 0);
check_sum_bit(16'h011D, 64'h0000_0000_2000_0000, 1, 0, 0, 0);
check_sum_bit(16'h011E, 64'h0000_0000_4000_0000, 1, 0, 0, 0);
check_sum_bit(16'h011F, 64'h0000_0000_8000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0120, 64'h0000_0001_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0121, 64'h0000_0002_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0122, 64'h0000_0004_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0123, 64'h0000_0008_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0124, 64'h0000_0010_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0125, 64'h0000_0020_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0126, 64'h0000_0040_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0127, 64'h0000_0080_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0128, 64'h0000_0100_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0129, 64'h0000_0200_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012A, 64'h0000_0400_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012B, 64'h0000_0800_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012C, 64'h0000_1000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012D, 64'h0000_2000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012E, 64'h0000_4000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h012F, 64'h0000_8000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0130, 64'h0001_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0131, 64'h0002_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0132, 64'h0004_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0133, 64'h0008_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0134, 64'h0010_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0135, 64'h0020_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0136, 64'h0040_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0137, 64'h0080_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0138, 64'h0100_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h0139, 64'h0200_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h013A, 64'h0400_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h013B, 64'h0800_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h013C, 64'h1000_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h013D, 64'h2000_0000_0000_0000, 1, 0, 0, 0);
check_sum_bit(16'h013E, 64'h4000_0000_0000_0000, 1, 0, 1, 0);
check_sum_bit(16'h013F, 64'h8000_0000_0000_0000, 1, 1, 1, 0);
// We also expect our ALU to perform bitwise operations as well.
check_and(16'h0200, 64'h0000_0000_0000_0001);
check_and(16'h0201, 64'h0000_0000_0000_0002);
check_and(16'h0202, 64'h0000_0000_0000_0004);
check_and(16'h0203, 64'h0000_0000_0000_0008);
check_and(16'h0204, 64'h0000_0000_0000_0010);
check_and(16'h0205, 64'h0000_0000_0000_0020);
check_and(16'h0206, 64'h0000_0000_0000_0040);
check_and(16'h0207, 64'h0000_0000_0000_0080);
check_and(16'h0208, 64'h0000_0000_0000_0100);
check_and(16'h0209, 64'h0000_0000_0000_0200);
check_and(16'h020A, 64'h0000_0000_0000_0400);
check_and(16'h020B, 64'h0000_0000_0000_0800);
check_and(16'h020C, 64'h0000_0000_0000_1000);
check_and(16'h020D, 64'h0000_0000_0000_2000);
check_and(16'h020E, 64'h0000_0000_0000_4000);
check_and(16'h020F, 64'h0000_0000_0000_8000);
check_and(16'h0210, 64'h0000_0000_0001_0000);
check_and(16'h0211, 64'h0000_0000_0002_0000);
check_and(16'h0212, 64'h0000_0000_0004_0000);
check_and(16'h0213, 64'h0000_0000_0008_0000);
check_and(16'h0214, 64'h0000_0000_0010_0000);
check_and(16'h0215, 64'h0000_0000_0020_0000);
check_and(16'h0216, 64'h0000_0000_0040_0000);
check_and(16'h0217, 64'h0000_0000_0080_0000);
check_and(16'h0218, 64'h0000_0000_0100_0000);
check_and(16'h0219, 64'h0000_0000_0200_0000);
check_and(16'h021A, 64'h0000_0000_0400_0000);
check_and(16'h021B, 64'h0000_0000_0800_0000);
check_and(16'h021C, 64'h0000_0000_1000_0000);
check_and(16'h021D, 64'h0000_0000_2000_0000);
check_and(16'h021E, 64'h0000_0000_4000_0000);
check_and(16'h021F, 64'h0000_0000_8000_0000);
check_and(16'h0220, 64'h0000_0001_0000_0000);
check_and(16'h0221, 64'h0000_0002_0000_0000);
check_and(16'h0222, 64'h0000_0004_0000_0000);
check_and(16'h0223, 64'h0000_0008_0000_0000);
check_and(16'h0224, 64'h0000_0010_0000_0000);
check_and(16'h0225, 64'h0000_0020_0000_0000);
check_and(16'h0226, 64'h0000_0040_0000_0000);
check_and(16'h0227, 64'h0000_0080_0000_0000);
check_and(16'h0228, 64'h0000_0100_0000_0000);
check_and(16'h0229, 64'h0000_0200_0000_0000);
check_and(16'h022A, 64'h0000_0400_0000_0000);
check_and(16'h022B, 64'h0000_0800_0000_0000);
check_and(16'h022C, 64'h0000_1000_0000_0000);
check_and(16'h022D, 64'h0000_2000_0000_0000);
check_and(16'h022E, 64'h0000_4000_0000_0000);
check_and(16'h022F, 64'h0000_8000_0000_0000);
check_and(16'h0230, 64'h0001_0000_0000_0000);
check_and(16'h0231, 64'h0002_0000_0000_0000);
check_and(16'h0232, 64'h0004_0000_0000_0000);
check_and(16'h0233, 64'h0008_0000_0000_0000);
check_and(16'h0234, 64'h0010_0000_0000_0000);
check_and(16'h0235, 64'h0020_0000_0000_0000);
check_and(16'h0236, 64'h0040_0000_0000_0000);
check_and(16'h0237, 64'h0080_0000_0000_0000);
check_and(16'h0238, 64'h0100_0000_0000_0000);
check_and(16'h0239, 64'h0200_0000_0000_0000);
check_and(16'h023A, 64'h0400_0000_0000_0000);
check_and(16'h023B, 64'h0800_0000_0000_0000);
check_and(16'h023C, 64'h1000_0000_0000_0000);
check_and(16'h023D, 64'h2000_0000_0000_0000);
check_and(16'h023E, 64'h4000_0000_0000_0000);
check_and(16'h023F, 64'h8000_0000_0000_0000);
check_xor(16'h0300, 64'h0000_0000_0000_0001);
check_xor(16'h0301, 64'h0000_0000_0000_0002);
check_xor(16'h0302, 64'h0000_0000_0000_0004);
check_xor(16'h0303, 64'h0000_0000_0000_0008);
check_xor(16'h0304, 64'h0000_0000_0000_0010);
check_xor(16'h0305, 64'h0000_0000_0000_0020);
check_xor(16'h0306, 64'h0000_0000_0000_0040);
check_xor(16'h0307, 64'h0000_0000_0000_0080);
check_xor(16'h0308, 64'h0000_0000_0000_0100);
check_xor(16'h0309, 64'h0000_0000_0000_0200);
check_xor(16'h030A, 64'h0000_0000_0000_0400);
check_xor(16'h030B, 64'h0000_0000_0000_0800);
check_xor(16'h030C, 64'h0000_0000_0000_1000);
check_xor(16'h030D, 64'h0000_0000_0000_2000);
check_xor(16'h030E, 64'h0000_0000_0000_4000);
check_xor(16'h030F, 64'h0000_0000_0000_8000);
check_xor(16'h0310, 64'h0000_0000_0001_0000);
check_xor(16'h0311, 64'h0000_0000_0002_0000);
check_xor(16'h0312, 64'h0000_0000_0004_0000);
check_xor(16'h0313, 64'h0000_0000_0008_0000);
check_xor(16'h0314, 64'h0000_0000_0010_0000);
check_xor(16'h0315, 64'h0000_0000_0020_0000);
check_xor(16'h0316, 64'h0000_0000_0040_0000);
check_xor(16'h0317, 64'h0000_0000_0080_0000);
check_xor(16'h0318, 64'h0000_0000_0100_0000);
check_xor(16'h0319, 64'h0000_0000_0200_0000);
check_xor(16'h031A, 64'h0000_0000_0400_0000);
check_xor(16'h031B, 64'h0000_0000_0800_0000);
check_xor(16'h031C, 64'h0000_0000_1000_0000);
check_xor(16'h031D, 64'h0000_0000_2000_0000);
check_xor(16'h031E, 64'h0000_0000_4000_0000);
check_xor(16'h031F, 64'h0000_0000_8000_0000);
check_xor(16'h0320, 64'h0000_0001_0000_0000);
check_xor(16'h0321, 64'h0000_0002_0000_0000);
check_xor(16'h0322, 64'h0000_0004_0000_0000);
check_xor(16'h0323, 64'h0000_0008_0000_0000);
check_xor(16'h0324, 64'h0000_0010_0000_0000);
check_xor(16'h0325, 64'h0000_0020_0000_0000);
check_xor(16'h0326, 64'h0000_0040_0000_0000);
check_xor(16'h0327, 64'h0000_0080_0000_0000);
check_xor(16'h0328, 64'h0000_0100_0000_0000);
check_xor(16'h0329, 64'h0000_0200_0000_0000);
check_xor(16'h032A, 64'h0000_0400_0000_0000);
check_xor(16'h032B, 64'h0000_0800_0000_0000);
check_xor(16'h032C, 64'h0000_1000_0000_0000);
check_xor(16'h032D, 64'h0000_2000_0000_0000);
check_xor(16'h032E, 64'h0000_4000_0000_0000);
check_xor(16'h032F, 64'h0000_8000_0000_0000);
check_xor(16'h0330, 64'h0001_0000_0000_0000);
check_xor(16'h0331, 64'h0002_0000_0000_0000);
check_xor(16'h0332, 64'h0004_0000_0000_0000);
check_xor(16'h0333, 64'h0008_0000_0000_0000);
check_xor(16'h0334, 64'h0010_0000_0000_0000);
check_xor(16'h0335, 64'h0020_0000_0000_0000);
check_xor(16'h0336, 64'h0040_0000_0000_0000);
check_xor(16'h0337, 64'h0080_0000_0000_0000);
check_xor(16'h0338, 64'h0100_0000_0000_0000);
check_xor(16'h0339, 64'h0300_0000_0000_0000);
check_xor(16'h033A, 64'h0400_0000_0000_0000);
check_xor(16'h033B, 64'h0800_0000_0000_0000);
check_xor(16'h033C, 64'h1000_0000_0000_0000);
check_xor(16'h033D, 64'h2000_0000_0000_0000);
check_xor(16'h033E, 64'h4000_0000_0000_0000);
check_xor(16'h033F, 64'h8000_0000_0000_0000);
check_or(16'h0400, 64'h0000_0000_0000_0001);
check_or(16'h0401, 64'h0000_0000_0000_0002);
check_or(16'h0402, 64'h0000_0000_0000_0004);
check_or(16'h0403, 64'h0000_0000_0000_0008);
check_or(16'h0404, 64'h0000_0000_0000_0010);
check_or(16'h0405, 64'h0000_0000_0000_0020);
check_or(16'h0406, 64'h0000_0000_0000_0040);
check_or(16'h0407, 64'h0000_0000_0000_0080);
check_or(16'h0408, 64'h0000_0000_0000_0100);
check_or(16'h0409, 64'h0000_0000_0000_0200);
check_or(16'h040A, 64'h0000_0000_0000_0400);
check_or(16'h040B, 64'h0000_0000_0000_0800);
check_or(16'h040C, 64'h0000_0000_0000_1000);
check_or(16'h040D, 64'h0000_0000_0000_2000);
check_or(16'h040E, 64'h0000_0000_0000_4000);
check_or(16'h040F, 64'h0000_0000_0000_8000);
check_or(16'h0410, 64'h0000_0000_0001_0000);
check_or(16'h0411, 64'h0000_0000_0002_0000);
check_or(16'h0412, 64'h0000_0000_0004_0000);
check_or(16'h0413, 64'h0000_0000_0008_0000);
check_or(16'h0414, 64'h0000_0000_0010_0000);
check_or(16'h0415, 64'h0000_0000_0020_0000);
check_or(16'h0416, 64'h0000_0000_0040_0000);
check_or(16'h0417, 64'h0000_0000_0080_0000);
check_or(16'h0418, 64'h0000_0000_0100_0000);
check_or(16'h0419, 64'h0000_0000_0200_0000);
check_or(16'h041A, 64'h0000_0000_0400_0000);
check_or(16'h041B, 64'h0000_0000_0800_0000);
check_or(16'h041C, 64'h0000_0000_1000_0000);
check_or(16'h041D, 64'h0000_0000_2000_0000);
check_or(16'h041E, 64'h0000_0000_4000_0000);
check_or(16'h041F, 64'h0000_0000_8000_0000);
check_or(16'h0420, 64'h0000_0001_0000_0000);
check_or(16'h0421, 64'h0000_0002_0000_0000);
check_or(16'h0422, 64'h0000_0004_0000_0000);
check_or(16'h0423, 64'h0000_0008_0000_0000);
check_or(16'h0424, 64'h0000_0010_0000_0000);
check_or(16'h0425, 64'h0000_0020_0000_0000);
check_or(16'h0426, 64'h0000_0040_0000_0000);
check_or(16'h0427, 64'h0000_0080_0000_0000);
check_or(16'h0428, 64'h0000_0100_0000_0000);
check_or(16'h0429, 64'h0000_0200_0000_0000);
check_or(16'h042A, 64'h0000_0400_0000_0000);
check_or(16'h042B, 64'h0000_0800_0000_0000);
check_or(16'h042C, 64'h0000_1000_0000_0000);
check_or(16'h042D, 64'h0000_2000_0000_0000);
check_or(16'h042E, 64'h0000_4000_0000_0000);
check_or(16'h042F, 64'h0000_8000_0000_0000);
check_or(16'h0430, 64'h0001_0000_0000_0000);
check_or(16'h0431, 64'h0002_0000_0000_0000);
check_or(16'h0432, 64'h0004_0000_0000_0000);
check_or(16'h0433, 64'h0008_0000_0000_0000);
check_or(16'h0434, 64'h0010_0000_0000_0000);
check_or(16'h0435, 64'h0020_0000_0000_0000);
check_or(16'h0436, 64'h0040_0000_0000_0000);
check_or(16'h0437, 64'h0080_0000_0000_0000);
check_or(16'h0438, 64'h0100_0000_0000_0000);
check_or(16'h0439, 64'h0400_0000_0000_0000);
check_or(16'h043A, 64'h0400_0000_0000_0000);
check_or(16'h043B, 64'h0800_0000_0000_0000);
check_or(16'h043C, 64'h1000_0000_0000_0000);
check_or(16'h043D, 64'h2000_0000_0000_0000);
check_or(16'h043E, 64'h4000_0000_0000_0000);
check_or(16'h043F, 64'h8000_0000_0000_0000);
check_diff_bit(16'h0500, 64'h0000_0000_0000_0001, 1, 0, 1);
check_diff_bit(16'h0501, 64'h0000_0000_0000_0002, 1, 0, 1);
check_diff_bit(16'h0502, 64'h0000_0000_0000_0004, 1, 0, 1);
check_diff_bit(16'h0503, 64'h0000_0000_0000_0008, 1, 0, 1);
check_diff_bit(16'h0504, 64'h0000_0000_0000_0010, 1, 0, 1);
check_diff_bit(16'h0505, 64'h0000_0000_0000_0020, 1, 0, 1);
check_diff_bit(16'h0506, 64'h0000_0000_0000_0040, 1, 0, 1);
check_diff_bit(16'h0507, 64'h0000_0000_0000_0080, 1, 0, 1);
check_diff_bit(16'h0508, 64'h0000_0000_0000_0100, 1, 0, 1);
check_diff_bit(16'h0509, 64'h0000_0000_0000_0200, 1, 0, 1);
check_diff_bit(16'h050A, 64'h0000_0000_0000_0400, 1, 0, 1);
check_diff_bit(16'h050B, 64'h0000_0000_0000_0800, 1, 0, 1);
check_diff_bit(16'h050C, 64'h0000_0000_0000_1000, 1, 0, 1);
check_diff_bit(16'h050D, 64'h0000_0000_0000_2000, 1, 0, 1);
check_diff_bit(16'h050E, 64'h0000_0000_0000_4000, 1, 0, 1);
check_diff_bit(16'h050F, 64'h0000_0000_0000_8000, 1, 0, 1);
check_diff_bit(16'h0510, 64'h0000_0000_0001_0000, 1, 0, 1);
check_diff_bit(16'h0511, 64'h0000_0000_0002_0000, 1, 0, 1);
check_diff_bit(16'h0512, 64'h0000_0000_0004_0000, 1, 0, 1);
check_diff_bit(16'h0513, 64'h0000_0000_0008_0000, 1, 0, 1);
check_diff_bit(16'h0514, 64'h0000_0000_0010_0000, 1, 0, 1);
check_diff_bit(16'h0515, 64'h0000_0000_0020_0000, 1, 0, 1);
check_diff_bit(16'h0516, 64'h0000_0000_0040_0000, 1, 0, 1);
check_diff_bit(16'h0517, 64'h0000_0000_0080_0000, 1, 0, 1);
check_diff_bit(16'h0518, 64'h0000_0000_0100_0000, 1, 0, 1);
check_diff_bit(16'h0519, 64'h0000_0000_0200_0000, 1, 0, 1);
check_diff_bit(16'h051A, 64'h0000_0000_0400_0000, 1, 0, 1);
check_diff_bit(16'h051B, 64'h0000_0000_0800_0000, 1, 0, 1);
check_diff_bit(16'h051C, 64'h0000_0000_1000_0000, 1, 0, 1);
check_diff_bit(16'h051D, 64'h0000_0000_2000_0000, 1, 0, 1);
check_diff_bit(16'h051E, 64'h0000_0000_4000_0000, 1, 0, 1);
check_diff_bit(16'h051F, 64'h0000_0000_8000_0000, 1, 0, 1);
check_diff_bit(16'h0520, 64'h0000_0001_0000_0000, 1, 0, 1);
check_diff_bit(16'h0521, 64'h0000_0002_0000_0000, 1, 0, 1);
check_diff_bit(16'h0522, 64'h0000_0004_0000_0000, 1, 0, 1);
check_diff_bit(16'h0523, 64'h0000_0008_0000_0000, 1, 0, 1);
check_diff_bit(16'h0524, 64'h0000_0010_0000_0000, 1, 0, 1);
check_diff_bit(16'h0525, 64'h0000_0020_0000_0000, 1, 0, 1);
check_diff_bit(16'h0526, 64'h0000_0040_0000_0000, 1, 0, 1);
check_diff_bit(16'h0527, 64'h0000_0080_0000_0000, 1, 0, 1);
check_diff_bit(16'h0528, 64'h0000_0100_0000_0000, 1, 0, 1);
check_diff_bit(16'h0529, 64'h0000_0200_0000_0000, 1, 0, 1);
check_diff_bit(16'h052A, 64'h0000_0400_0000_0000, 1, 0, 1);
check_diff_bit(16'h052B, 64'h0000_0800_0000_0000, 1, 0, 1);
check_diff_bit(16'h052C, 64'h0000_1000_0000_0000, 1, 0, 1);
check_diff_bit(16'h052D, 64'h0000_2000_0000_0000, 1, 0, 1);
check_diff_bit(16'h052E, 64'h0000_4000_0000_0000, 1, 0, 1);
check_diff_bit(16'h052F, 64'h0000_8000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0530, 64'h0001_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0531, 64'h0002_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0532, 64'h0004_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0533, 64'h0008_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0534, 64'h0010_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0535, 64'h0020_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0536, 64'h0040_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0537, 64'h0080_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0538, 64'h0100_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h0539, 64'h0200_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053A, 64'h0400_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053B, 64'h0800_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053C, 64'h1000_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053D, 64'h2000_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053E, 64'h4000_0000_0000_0000, 1, 0, 1);
check_diff_bit(16'h053F, 64'h8000_0000_0000_0000, 1, 0, 1);
// ALU should be able to perform left and right shifts, both
// logical and arithmetic.
check_lsh(16'h0600, 6'd0, 64'h0000_0000_0000_0001);
check_lsh(16'h0601, 6'd1, 64'h0000_0000_0000_0002);
check_lsh(16'h0602, 6'd2, 64'h0000_0000_0000_0004);
check_lsh(16'h0603, 6'd3, 64'h0000_0000_0000_0008);
check_lsh(16'h0604, 6'd4, 64'h0000_0000_0000_0010);
check_lsh(16'h0605, 6'd5, 64'h0000_0000_0000_0020);
check_lsh(16'h0606, 6'd6, 64'h0000_0000_0000_0040);
check_lsh(16'h0607, 6'd7, 64'h0000_0000_0000_0080);
check_lsh(16'h0608, 6'd8, 64'h0000_0000_0000_0100);
check_lsh(16'h0609, 6'd9, 64'h0000_0000_0000_0200);
check_lsh(16'h060A, 6'd10, 64'h0000_0000_0000_0400);
check_lsh(16'h060B, 6'd11, 64'h0000_0000_0000_0800);
check_lsh(16'h060C, 6'd12, 64'h0000_0000_0000_1000);
check_lsh(16'h060D, 6'd13, 64'h0000_0000_0000_2000);
check_lsh(16'h060E, 6'd14, 64'h0000_0000_0000_4000);
check_lsh(16'h060F, 6'd15, 64'h0000_0000_0000_8000);
check_lsh(16'h0610, 6'd16, 64'h0000_0000_0001_0000);
check_lsh(16'h0611, 6'd17, 64'h0000_0000_0002_0000);
check_lsh(16'h0612, 6'd18, 64'h0000_0000_0004_0000);
check_lsh(16'h0613, 6'd19, 64'h0000_0000_0008_0000);
check_lsh(16'h0614, 6'd20, 64'h0000_0000_0010_0000);
check_lsh(16'h0615, 6'd21, 64'h0000_0000_0020_0000);
check_lsh(16'h0616, 6'd22, 64'h0000_0000_0040_0000);
check_lsh(16'h0617, 6'd23, 64'h0000_0000_0080_0000);
check_lsh(16'h0618, 6'd24, 64'h0000_0000_0100_0000);
check_lsh(16'h0619, 6'd25, 64'h0000_0000_0200_0000);
check_lsh(16'h061A, 6'd26, 64'h0000_0000_0400_0000);
check_lsh(16'h061B, 6'd27, 64'h0000_0000_0800_0000);
check_lsh(16'h061C, 6'd28, 64'h0000_0000_1000_0000);
check_lsh(16'h061D, 6'd29, 64'h0000_0000_2000_0000);
check_lsh(16'h061E, 6'd30, 64'h0000_0000_4000_0000);
check_lsh(16'h061F, 6'd31, 64'h0000_0000_8000_0000);
check_lsh(16'h0620, 6'd32, 64'h0000_0001_0000_0000);
check_lsh(16'h0621, 6'd33, 64'h0000_0002_0000_0000);
check_lsh(16'h0622, 6'd34, 64'h0000_0004_0000_0000);
check_lsh(16'h0623, 6'd35, 64'h0000_0008_0000_0000);
check_lsh(16'h0624, 6'd36, 64'h0000_0010_0000_0000);
check_lsh(16'h0625, 6'd37, 64'h0000_0020_0000_0000);
check_lsh(16'h0626, 6'd38, 64'h0000_0040_0000_0000);
check_lsh(16'h0627, 6'd39, 64'h0000_0080_0000_0000);
check_lsh(16'h0628, 6'd40, 64'h0000_0100_0000_0000);
check_lsh(16'h0629, 6'd41, 64'h0000_0200_0000_0000);
check_lsh(16'h062A, 6'd42, 64'h0000_0400_0000_0000);
check_lsh(16'h062B, 6'd43, 64'h0000_0800_0000_0000);
check_lsh(16'h062C, 6'd44, 64'h0000_1000_0000_0000);
check_lsh(16'h062D, 6'd45, 64'h0000_2000_0000_0000);
check_lsh(16'h062E, 6'd46, 64'h0000_4000_0000_0000);
check_lsh(16'h062F, 6'd47, 64'h0000_8000_0000_0000);
check_lsh(16'h0630, 6'd48, 64'h0001_0000_0000_0000);
check_lsh(16'h0631, 6'd49, 64'h0002_0000_0000_0000);
check_lsh(16'h0632, 6'd50, 64'h0004_0000_0000_0000);
check_lsh(16'h0633, 6'd51, 64'h0008_0000_0000_0000);
check_lsh(16'h0634, 6'd52, 64'h0010_0000_0000_0000);
check_lsh(16'h0635, 6'd53, 64'h0020_0000_0000_0000);
check_lsh(16'h0636, 6'd54, 64'h0040_0000_0000_0000);
check_lsh(16'h0637, 6'd55, 64'h0080_0000_0000_0000);
check_lsh(16'h0638, 6'd56, 64'h0100_0000_0000_0000);
check_lsh(16'h0639, 6'd57, 64'h0200_0000_0000_0000);
check_lsh(16'h063A, 6'd58, 64'h0400_0000_0000_0000);
check_lsh(16'h063B, 6'd59, 64'h0800_0000_0000_0000);
check_lsh(16'h063C, 6'd60, 64'h1000_0000_0000_0000);
check_lsh(16'h063D, 6'd61, 64'h2000_0000_0000_0000);
check_lsh(16'h063E, 6'd62, 64'h4000_0000_0000_0000);
check_lsh(16'h063F, 6'd63, 64'h8000_0000_0000_0000);
check_rsh(16'h0700, 6'd0, 64'h8000_0000_0000_0000);
check_rsh(16'h0701, 6'd1, 64'h4000_0000_0000_0000);
check_rsh(16'h0702, 6'd2, 64'h2000_0000_0000_0000);
check_rsh(16'h0703, 6'd3, 64'h1000_0000_0000_0000);
check_rsh(16'h0704, 6'd4, 64'h0800_0000_0000_0000);
check_rsh(16'h0705, 6'd5, 64'h0400_0000_0000_0000);
check_rsh(16'h0706, 6'd6, 64'h0200_0000_0000_0000);
check_rsh(16'h0707, 6'd7, 64'h0100_0000_0000_0000);
check_rsh(16'h0708, 6'd8, 64'h0080_0000_0000_0000);
check_rsh(16'h0709, 6'd9, 64'h0040_0000_0000_0000);
check_rsh(16'h070A, 6'd10, 64'h0020_0000_0000_0000);
check_rsh(16'h070B, 6'd11, 64'h0010_0000_0000_0000);
check_rsh(16'h070C, 6'd12, 64'h0008_0000_0000_0000);
check_rsh(16'h070D, 6'd13, 64'h0004_0000_0000_0000);
check_rsh(16'h070E, 6'd14, 64'h0002_0000_0000_0000);
check_rsh(16'h070F, 6'd15, 64'h0001_0000_0000_0000);
check_rsh(16'h0710, 6'd16, 64'h0000_8000_0000_0000);
check_rsh(16'h0711, 6'd17, 64'h0000_4000_0000_0000);
check_rsh(16'h0712, 6'd18, 64'h0000_2000_0000_0000);
check_rsh(16'h0713, 6'd19, 64'h0000_1000_0000_0000);
check_rsh(16'h0714, 6'd20, 64'h0000_0800_0000_0000);
check_rsh(16'h0715, 6'd21, 64'h0000_0400_0000_0000);
check_rsh(16'h0716, 6'd22, 64'h0000_0200_0000_0000);
check_rsh(16'h0717, 6'd23, 64'h0000_0100_0000_0000);
check_rsh(16'h0718, 6'd24, 64'h0000_0080_0000_0000);
check_rsh(16'h0719, 6'd25, 64'h0000_0040_0000_0000);
check_rsh(16'h071A, 6'd26, 64'h0000_0020_0000_0000);
check_rsh(16'h071B, 6'd27, 64'h0000_0010_0000_0000);
check_rsh(16'h071C, 6'd28, 64'h0000_0008_0000_0000);
check_rsh(16'h071D, 6'd29, 64'h0000_0004_0000_0000);
check_rsh(16'h071E, 6'd30, 64'h0000_0002_0000_0000);
check_rsh(16'h071F, 6'd31, 64'h0000_0001_0000_0000);
check_rsh(16'h0720, 6'd32, 64'h0000_0000_8000_0000);
check_rsh(16'h0721, 6'd33, 64'h0000_0000_4000_0000);
check_rsh(16'h0722, 6'd34, 64'h0000_0000_2000_0000);
check_rsh(16'h0723, 6'd35, 64'h0000_0000_1000_0000);
check_rsh(16'h0724, 6'd36, 64'h0000_0000_0800_0000);
check_rsh(16'h0725, 6'd37, 64'h0000_0000_0400_0000);
check_rsh(16'h0726, 6'd38, 64'h0000_0000_0200_0000);
check_rsh(16'h0727, 6'd39, 64'h0000_0000_0100_0000);
check_rsh(16'h0728, 6'd40, 64'h0000_0000_0080_0000);
check_rsh(16'h0729, 6'd41, 64'h0000_0000_0040_0000);
check_rsh(16'h072A, 6'd42, 64'h0000_0000_0020_0000);
check_rsh(16'h072B, 6'd43, 64'h0000_0000_0010_0000);
check_rsh(16'h072C, 6'd44, 64'h0000_0000_0008_0000);
check_rsh(16'h072D, 6'd45, 64'h0000_0000_0004_0000);
check_rsh(16'h072E, 6'd46, 64'h0000_0000_0002_0000);
check_rsh(16'h072F, 6'd47, 64'h0000_0000_0001_0000);
check_rsh(16'h0730, 6'd48, 64'h0000_0000_0000_8000);
check_rsh(16'h0731, 6'd49, 64'h0000_0000_0000_4000);
check_rsh(16'h0732, 6'd50, 64'h0000_0000_0000_2000);
check_rsh(16'h0733, 6'd51, 64'h0000_0000_0000_1000);
check_rsh(16'h0734, 6'd52, 64'h0000_0000_0000_0800);
check_rsh(16'h0735, 6'd53, 64'h0000_0000_0000_0400);
check_rsh(16'h0736, 6'd54, 64'h0000_0000_0000_0200);
check_rsh(16'h0737, 6'd55, 64'h0000_0000_0000_0100);
check_rsh(16'h0738, 6'd56, 64'h0000_0000_0000_0080);
check_rsh(16'h0739, 6'd57, 64'h0000_0000_0000_0040);
check_rsh(16'h073A, 6'd58, 64'h0000_0000_0000_0020);
check_rsh(16'h073B, 6'd59, 64'h0000_0000_0000_0010);
check_rsh(16'h073C, 6'd60, 64'h0000_0000_0000_0008);
check_rsh(16'h073D, 6'd61, 64'h0000_0000_0000_0004);
check_rsh(16'h073E, 6'd62, 64'h0000_0000_0000_0002);
check_rsh(16'h073F, 6'd63, 64'h0000_0000_0000_0001);
check_asr(16'h0800, 6'd0, 64'h8000_0000_0000_0000);
check_asr(16'h0801, 6'd1, 64'hC000_0000_0000_0000);
check_asr(16'h0802, 6'd2, 64'hE000_0000_0000_0000);
check_asr(16'h0803, 6'd3, 64'hF000_0000_0000_0000);
check_asr(16'h0804, 6'd4, 64'hF800_0000_0000_0000);
check_asr(16'h0805, 6'd5, 64'hFC00_0000_0000_0000);
check_asr(16'h0806, 6'd6, 64'hFE00_0000_0000_0000);
check_asr(16'h0807, 6'd7, 64'hFF00_0000_0000_0000);
check_asr(16'h0808, 6'd8, 64'hFF80_0000_0000_0000);
check_asr(16'h0809, 6'd9, 64'hFFC0_0000_0000_0000);
check_asr(16'h080A, 6'd10, 64'hFFE0_0000_0000_0000);
check_asr(16'h080B, 6'd11, 64'hFFF0_0000_0000_0000);
check_asr(16'h080C, 6'd12, 64'hFFF8_0000_0000_0000);
check_asr(16'h080D, 6'd13, 64'hFFFC_0000_0000_0000);
check_asr(16'h080E, 6'd14, 64'hFFFE_0000_0000_0000);
check_asr(16'h080F, 6'd15, 64'hFFFF_0000_0000_0000);
check_asr(16'h0810, 6'd16, 64'hFFFF_8000_0000_0000);
check_asr(16'h0811, 6'd17, 64'hFFFF_C000_0000_0000);
check_asr(16'h0812, 6'd18, 64'hFFFF_E000_0000_0000);
check_asr(16'h0813, 6'd19, 64'hFFFF_F000_0000_0000);
check_asr(16'h0814, 6'd20, 64'hFFFF_F800_0000_0000);
check_asr(16'h0815, 6'd21, 64'hFFFF_FC00_0000_0000);
check_asr(16'h0816, 6'd22, 64'hFFFF_FE00_0000_0000);
check_asr(16'h0817, 6'd23, 64'hFFFF_FF00_0000_0000);
check_asr(16'h0818, 6'd24, 64'hFFFF_FF80_0000_0000);
check_asr(16'h0819, 6'd25, 64'hFFFF_FFC0_0000_0000);
check_asr(16'h081A, 6'd26, 64'hFFFF_FFE0_0000_0000);
check_asr(16'h081B, 6'd27, 64'hFFFF_FFF0_0000_0000);
check_asr(16'h081C, 6'd28, 64'hFFFF_FFF8_0000_0000);
check_asr(16'h081D, 6'd29, 64'hFFFF_FFFC_0000_0000);
check_asr(16'h081E, 6'd30, 64'hFFFF_FFFE_0000_0000);
check_asr(16'h081F, 6'd31, 64'hFFFF_FFFF_0000_0000);
check_asr(16'h0820, 6'd32, 64'hFFFF_FFFF_8000_0000);
check_asr(16'h0821, 6'd33, 64'hFFFF_FFFF_C000_0000);
check_asr(16'h0822, 6'd34, 64'hFFFF_FFFF_E000_0000);
check_asr(16'h0823, 6'd35, 64'hFFFF_FFFF_F000_0000);
check_asr(16'h0824, 6'd36, 64'hFFFF_FFFF_F800_0000);
check_asr(16'h0825, 6'd37, 64'hFFFF_FFFF_FC00_0000);
check_asr(16'h0826, 6'd38, 64'hFFFF_FFFF_FE00_0000);
check_asr(16'h0827, 6'd39, 64'hFFFF_FFFF_FF00_0000);
check_asr(16'h0828, 6'd40, 64'hFFFF_FFFF_FF80_0000);
check_asr(16'h0829, 6'd41, 64'hFFFF_FFFF_FFC0_0000);
check_asr(16'h082A, 6'd42, 64'hFFFF_FFFF_FFE0_0000);
check_asr(16'h082B, 6'd43, 64'hFFFF_FFFF_FFF0_0000);
check_asr(16'h082C, 6'd44, 64'hFFFF_FFFF_FFF8_0000);
check_asr(16'h082D, 6'd45, 64'hFFFF_FFFF_FFFC_0000);
check_asr(16'h082E, 6'd46, 64'hFFFF_FFFF_FFFE_0000);
check_asr(16'h082F, 6'd47, 64'hFFFF_FFFF_FFFF_0000);
check_asr(16'h0830, 6'd48, 64'hFFFF_FFFF_FFFF_8000);
check_asr(16'h0831, 6'd49, 64'hFFFF_FFFF_FFFF_C000);
check_asr(16'h0832, 6'd50, 64'hFFFF_FFFF_FFFF_E000);
check_asr(16'h0833, 6'd51, 64'hFFFF_FFFF_FFFF_F000);
check_asr(16'h0834, 6'd52, 64'hFFFF_FFFF_FFFF_F800);
check_asr(16'h0835, 6'd53, 64'hFFFF_FFFF_FFFF_FC00);
check_asr(16'h0836, 6'd54, 64'hFFFF_FFFF_FFFF_FE00);
check_asr(16'h0837, 6'd55, 64'hFFFF_FFFF_FFFF_FF00);
check_asr(16'h0838, 6'd56, 64'hFFFF_FFFF_FFFF_FF80);
check_asr(16'h0839, 6'd57, 64'hFFFF_FFFF_FFFF_FFC0);
check_asr(16'h083A, 6'd58, 64'hFFFF_FFFF_FFFF_FFE0);
check_asr(16'h083B, 6'd59, 64'hFFFF_FFFF_FFFF_FFF0);
check_asr(16'h083C, 6'd60, 64'hFFFF_FFFF_FFFF_FFF8);
check_asr(16'h083D, 6'd61, 64'hFFFF_FFFF_FFFF_FFFC);
check_asr(16'h083E, 6'd62, 64'hFFFF_FFFF_FFFF_FFFE);
check_asr(16'h083F, 6'd63, 64'hFFFF_FFFF_FFFF_FFFF);
check_asr_2(16'h0900, 6'd0, 64'h4000_0000_0000_0000);
check_asr_2(16'h0901, 6'd1, 64'h2000_0000_0000_0000);
check_asr_2(16'h0902, 6'd2, 64'h1000_0000_0000_0000);
check_asr_2(16'h0903, 6'd3, 64'h0800_0000_0000_0000);
check_asr_2(16'h0904, 6'd4, 64'h0400_0000_0000_0000);
check_asr_2(16'h0905, 6'd5, 64'h0200_0000_0000_0000);
check_asr_2(16'h0906, 6'd6, 64'h0100_0000_0000_0000);
check_asr_2(16'h0907, 6'd7, 64'h0080_0000_0000_0000);
check_asr_2(16'h0908, 6'd8, 64'h0040_0000_0000_0000);
check_asr_2(16'h0909, 6'd9, 64'h0020_0000_0000_0000);
check_asr_2(16'h090A, 6'd10, 64'h0010_0000_0000_0000);
check_asr_2(16'h090B, 6'd11, 64'h0008_0000_0000_0000);
check_asr_2(16'h090C, 6'd12, 64'h0004_0000_0000_0000);
check_asr_2(16'h090D, 6'd13, 64'h0002_0000_0000_0000);
check_asr_2(16'h090E, 6'd14, 64'h0001_0000_0000_0000);
check_asr_2(16'h090F, 6'd15, 64'h0000_8000_0000_0000);
check_asr_2(16'h0910, 6'd16, 64'h0000_4000_0000_0000);
check_asr_2(16'h0911, 6'd17, 64'h0000_2000_0000_0000);
check_asr_2(16'h0912, 6'd18, 64'h0000_1000_0000_0000);
check_asr_2(16'h0913, 6'd19, 64'h0000_0800_0000_0000);
check_asr_2(16'h0914, 6'd20, 64'h0000_0400_0000_0000);
check_asr_2(16'h0915, 6'd21, 64'h0000_0200_0000_0000);
check_asr_2(16'h0916, 6'd22, 64'h0000_0100_0000_0000);
check_asr_2(16'h0917, 6'd23, 64'h0000_0080_0000_0000);
check_asr_2(16'h0918, 6'd24, 64'h0000_0040_0000_0000);
check_asr_2(16'h0919, 6'd25, 64'h0000_0020_0000_0000);
check_asr_2(16'h091A, 6'd26, 64'h0000_0010_0000_0000);
check_asr_2(16'h091B, 6'd27, 64'h0000_0008_0000_0000);
check_asr_2(16'h091C, 6'd28, 64'h0000_0004_0000_0000);
check_asr_2(16'h091D, 6'd29, 64'h0000_0002_0000_0000);
check_asr_2(16'h091E, 6'd30, 64'h0000_0001_0000_0000);
check_asr_2(16'h091F, 6'd31, 64'h0000_0000_8000_0000);
check_asr_2(16'h0920, 6'd32, 64'h0000_0000_4000_0000);
check_asr_2(16'h0921, 6'd33, 64'h0000_0000_2000_0000);
check_asr_2(16'h0922, 6'd34, 64'h0000_0000_1000_0000);
check_asr_2(16'h0923, 6'd35, 64'h0000_0000_0800_0000);
check_asr_2(16'h0924, 6'd36, 64'h0000_0000_0400_0000);
check_asr_2(16'h0925, 6'd37, 64'h0000_0000_0200_0000);
check_asr_2(16'h0926, 6'd38, 64'h0000_0000_0100_0000);
check_asr_2(16'h0927, 6'd39, 64'h0000_0000_0080_0000);
check_asr_2(16'h0928, 6'd40, 64'h0000_0000_0040_0000);
check_asr_2(16'h0929, 6'd41, 64'h0000_0000_0020_0000);
check_asr_2(16'h092A, 6'd42, 64'h0000_0000_0010_0000);
check_asr_2(16'h092B, 6'd43, 64'h0000_0000_0008_0000);
check_asr_2(16'h092C, 6'd44, 64'h0000_0000_0004_0000);
check_asr_2(16'h092D, 6'd45, 64'h0000_0000_0002_0000);
check_asr_2(16'h092E, 6'd46, 64'h0000_0000_0001_0000);
check_asr_2(16'h092F, 6'd47, 64'h0000_0000_0000_8000);
check_asr_2(16'h0930, 6'd48, 64'h0000_0000_0000_4000);
check_asr_2(16'h0931, 6'd49, 64'h0000_0000_0000_2000);
check_asr_2(16'h0932, 6'd50, 64'h0000_0000_0000_1000);
check_asr_2(16'h0933, 6'd51, 64'h0000_0000_0000_0800);
check_asr_2(16'h0934, 6'd52, 64'h0000_0000_0000_0400);
check_asr_2(16'h0935, 6'd53, 64'h0000_0000_0000_0200);
check_asr_2(16'h0936, 6'd54, 64'h0000_0000_0000_0100);
check_asr_2(16'h0937, 6'd55, 64'h0000_0000_0000_0080);
check_asr_2(16'h0938, 6'd56, 64'h0000_0000_0000_0040);
check_asr_2(16'h0939, 6'd57, 64'h0000_0000_0000_0020);
check_asr_2(16'h093A, 6'd58, 64'h0000_0000_0000_0010);
check_asr_2(16'h093B, 6'd59, 64'h0000_0000_0000_0008);
check_asr_2(16'h093C, 6'd60, 64'h0000_0000_0000_0004);
check_asr_2(16'h093D, 6'd61, 64'h0000_0000_0000_0002);
check_asr_2(16'h093E, 6'd62, 64'h0000_0000_0000_0001);
check_asr_2(16'h093F, 6'd63, 64'h0000_0000_0000_0000);
// I accidentally left SLT/SLTU instructions unimplemented
// because I forgot to wire things up in the ALU. These
// tests cover my fix to make sure I have things implemented
// correctly.
// See https://github.com/KestrelComputer/polaris/issues/18
check_lt(16'h0A00, 64'hFFFF_FFFF_FFFF_FFFF, 64'h0000_0000_0000_0001, 1, 1, 0);
check_lt(16'h0A01, 64'h0000_0000_0000_0000, 64'h0000_0000_0000_0001, 1, 1, 0);
check_lt(16'h0A02, 64'h0000_0000_0000_0001, 64'h0000_0000_0000_0001, 0, 1, 0);
check_lt(16'h0A10, 64'hFFFF_FFFF_FFFF_FFFF, 64'h0000_0000_0000_0001, 0, 0, 1);
check_lt(16'h0A11, 64'h0000_0000_0000_0000, 64'h0000_0000_0000_0001, 1, 0, 1);
check_lt(16'h0A12, 64'h0000_0000_0000_0001, 64'h0000_0000_0000_0001, 0, 0, 1);
$display("@DONE");
$stop;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 100000000
//ISMASTER: 1
//DATABITS: 8
//TARGETCLOCK: 20000000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0.0001
module soc_design_EPCS64_sub (
// inputs:
MISO,
clk,
data_from_cpu,
epcs_select,
mem_addr,
read_n,
reset_n,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input epcs_select;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
wire [ 10: 0] epcs_control;
reg [ 15: 0] epcs_slave_select_holding_reg;
reg [ 15: 0] epcs_slave_select_reg;
wire [ 10: 0] epcs_status;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 1: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 7: 0] rx_holding_reg;
reg [ 7: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 1: 0] slowcount;
reg [ 4: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//epcs_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & epcs_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & epcs_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign epcs_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign epcs_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
epcs_slave_select_reg <= epcs_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
epcs_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 3 system clock pulses.
assign slowclock = slowcount == 2'h2;
assign p1_slowcount = ({2 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({2 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? epcs_status :
((mem_addr == 3))? epcs_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? epcs_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 17.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 17;
if (state == 17)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[7];
assign SS_n = (enableSS | SSO_reg) ? ~epcs_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 17)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[6 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tornado_soc_design_EPCS64_atom (
// inputs:
dclkin,
oe,
scein,
sdoin,
// outputs:
data0out
)
;
output data0out;
input dclkin;
input oe;
input scein;
input sdoin;
wire data0out;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign data0out = sdoin | scein | dclkin | oe;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// cyclonev_asmiblock the_cyclonev_asmiblock
// (
// .data0oe (~oe),
// .data0out (sdoin),
// .data1in (data0out),
// .data1oe (0),
// .data1out (0),
// .data2oe (0),
// .data2out (0),
// .data3oe (0),
// .data3out (0),
// .dclk (dclkin),
// .oe (oe),
// .sce (scein)
// );
//
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_EPCS64 (
// inputs:
address,
chipselect,
clk,
read_n,
reset_n,
reset_req,
write_n,
writedata,
// outputs:
dataavailable,
endofpacket,
irq,
readdata,
readyfordata
)
;
parameter INIT_FILE = "soc_design_EPCS64_boot_rom.hex";
output dataavailable;
output endofpacket;
output irq;
output [ 31: 0] readdata;
output readyfordata;
input [ 8: 0] address;
input chipselect;
input clk;
input read_n;
input reset_n;
input reset_req;
input write_n;
input [ 31: 0] writedata;
wire MISO;
wire MOSI;
wire SCLK;
wire SS_n;
wire clocken;
wire [ 15: 0] data_from_cpu;
wire [ 15: 0] data_to_cpu;
wire dataavailable;
wire endofpacket;
wire epcs_select;
wire irq;
wire [ 2: 0] mem_addr;
wire [ 31: 0] readdata;
wire readyfordata;
wire [ 31: 0] rom_readdata;
soc_design_EPCS64_sub the_soc_design_EPCS64_sub
(
.MISO (MISO),
.MOSI (MOSI),
.SCLK (SCLK),
.SS_n (SS_n),
.clk (clk),
.data_from_cpu (data_from_cpu),
.data_to_cpu (data_to_cpu),
.dataavailable (dataavailable),
.endofpacket (endofpacket),
.epcs_select (epcs_select),
.irq (irq),
.mem_addr (mem_addr),
.read_n (read_n),
.readyfordata (readyfordata),
.reset_n (reset_n),
.write_n (write_n)
);
//epcs_control_port, which is an e_avalon_slave
tornado_soc_design_EPCS64_atom the_tornado_soc_design_EPCS64_atom
(
.data0out (MISO),
.dclkin (SCLK),
.oe (1'b0),
.scein (SS_n),
.sdoin (MOSI)
);
assign clocken = ~reset_req;
assign epcs_select = chipselect && (address[8] );
assign mem_addr = address;
assign data_from_cpu = writedata;
assign readdata = epcs_select ? data_to_cpu : rom_readdata;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_boot_copier_rom
(
.address_a (address[7 : 0]),
.clock0 (clk),
.clocken0 (clocken),
.q_a (rom_readdata)
);
defparam the_boot_copier_rom.byte_size = 8,
the_boot_copier_rom.init_file = INIT_FILE,
the_boot_copier_rom.lpm_type = "altsyncram",
the_boot_copier_rom.numwords_a = 256,
the_boot_copier_rom.operation_mode = "ROM",
the_boot_copier_rom.outdata_reg_a = "UNREGISTERED",
the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
the_boot_copier_rom.width_a = 32,
the_boot_copier_rom.widthad_a = 8;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_boot_copier_rom
// (
// .address_a (address[7 : 0]),
// .clock0 (clk),
// .clocken0 (clocken),
// .q_a (rom_readdata)
// );
//
// defparam the_boot_copier_rom.byte_size = 8,
// the_boot_copier_rom.init_file = "soc_design_EPCS64_boot_rom.hex",
// the_boot_copier_rom.lpm_type = "altsyncram",
// the_boot_copier_rom.numwords_a = 256,
// the_boot_copier_rom.operation_mode = "ROM",
// the_boot_copier_rom.outdata_reg_a = "UNREGISTERED",
// the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_boot_copier_rom.width_a = 32,
// the_boot_copier_rom.widthad_a = 8;
//
//synthesis read_comments_as_HDL off
endmodule
|
//
// copyright (c) 2014 by [email protected]
// Licensed under CC-BY 3.0 (https://creativecommons.org/licenses/by/3.0/)
//
//______________________________________________________________________________
//
`timescale 1ns / 1ns
module k580vm80a
(
input pin_clk, // global module clock (no in original 8080)
input pin_f1, // clock phase 1 (used as clock enable)
input pin_f2, // clock phase 2 (used as clock enable)
input pin_reset, // module reset
output [15:0] pin_a, // address bus outputs
output [7:0] pin_dout, // data bus output
input [7:0] pin_din, // data bus input
output pin_aena, // address outputs enable
output pin_dena, // data outputs enable
input pin_hold, //
output pin_hlda, //
input pin_ready, //
output pin_wait, //
input pin_int, //
output pin_inte, //
output pin_sync, //
output pin_dbin, //
output pin_wr_n
);
//______________________________________________________________________________
//
wire [7:0] d;
reg [7:0] db, di;
reg [15:0] a;
wire clk, f1, f2;
reg abufena, db_ena, db_stb, dbin_pin, dbinf2;
reg reset;
wire ready;
wire dbin_ext;
reg t851, t404, t382, t383, t712, t735, t773;
reg hold, hlda_pin;
wire hlda, h889;
reg wr_n, t1124, t1011, sync;
wire ready_int;
reg [15:0] r16_pc, r16_hl, r16_de, r16_bc, r16_sp, r16_wz, mxo;
wire [15:0] mxi;
wire mxr0, mxr1, mxr2, mxr3, mxr4, mxr5;
wire mxwh, mxwl, mxrh, mxrl, mxw16, mxwadr;
wire dec16, inc16, iad16;
reg xchg_dh, xchg_tt, t3144;
wire t1460, t1467, t1513, t1514, t1519;
wire sy_inta, sy_wo_n, sy_hlta, sy_out, sy_m1, sy_inp, sy_memr;
reg sy_stack;
wire thalt, twt2;
reg t1, t2, tw, t3, t4, t5;
reg t1f1, t2f1, twf1, t3f1, t4f1, t5f1;
reg m1, m2, m3, m4, m5;
reg m1f1, m2f1, m3f1, m4f1, m5f1;
wire start, ms0, ms1, m836, m839, m871;
reg eom, t789, t887, t953, t976, t980;
reg intr, inta, inte, mstart, minta;
wire irq;
reg [7:0] i;
reg i25, i14, i03;
wire imx, acc_sel;
wire id_op, id_io, id_in, id_popsw, id_pupsw,
id_nop, id_lxi, id_inx, id_inr, id_dcr, id_idr, id_mvi, id_dad,
id_dcx, id_opa, id_idm, id_hlt, id_mov, id_opm, id_pop, id_rst,
id_cxx, id_jxx, id_rxx, id_ret, id_jmp, id_opi, id_out, id_11x,
id_rlc, id_rxc, id_rar, id_sha, id_daa, id_cma, id_stc, id_cmc,
id_add, id_adc, id_sub, id_sbb, id_ana, id_xra, id_ora, id_cmp,
id_lsax, id_mvim, id_shld, id_lhld, id_mvmr, id_mvrm, id_push,
id_xthl, id_sphl, id_pchl, id_xchg, id_call, id_eidi, id_stlda;
wire id80, id81, id82, id83, id84, id85, id86, id00, id01,
id02, id03, id04, id05, id06, id07, id08, id09, id10;
wire goto, jmpflag;
reg jmptake, tree0, tree1, tree2;
reg t2806, t2817, t2819, t3047, t2998, t3363, t3403, t3335, t3361;
reg [7:0] xr, r, acc;
wire [7:0] x, s, c;
wire cl, ch, daa, daa_6x, daa_x6;
wire a398;
reg a327, a357, a358;
wire alu_xout, alu_xwr, alu_xrd, alu_ald, alu_awr, alu_ard,
alu_rld, alu_r00, alu_rwr, alu_srd, alu_zrd, alu_frd;
reg psw_z, psw_s, psw_p, psw_c, psw_ac, tmp_c;
reg t2222, t1375, t1497, t1698, t1668, t1780, t1993, t1994;
reg psw_ld, psw_wr, t2046, t2133, t2175;
//_____________________________________________________________________________
//
assign clk = pin_clk;
assign f1 = pin_f1;
assign f2 = pin_f2;
assign pin_a = a;
assign pin_aena = abufena;
assign pin_dout = db;
assign pin_dena = db_ena;
assign dbin_ext = dbinf2;
assign d[7] = ~reset & ~alu_zrd &
( dbin_ext & di[7]
| mxrl & mxo[7]
| mxrh & mxo[15]
| t1f1 & sy_memr
| alu_xrd & xr[7]
| alu_ard & acc[7]
| alu_frd & psw_s
| alu_srd & s[7] );
assign d[6] = ~reset & ~alu_zrd &
( dbin_ext & di[6]
| mxrl & mxo[6]
| mxrh & mxo[14]
| t1f1 & sy_inp
| alu_xrd & xr[6]
| alu_ard & acc[6]
| alu_frd & psw_z
| alu_srd & s[6] );
assign d[5] = ~reset & ~alu_zrd &
( dbin_ext & di[5]
| mxrl & mxo[5]
| mxrh & mxo[13]
| t1f1 & sy_m1
| alu_xrd & xr[5]
| alu_ard & acc[5]
| alu_frd & 1'b0
| alu_srd & s[5] );
assign d[4] = ~reset & ~alu_zrd &
( dbin_ext & di[4]
| mxrl & mxo[4]
| mxrh & mxo[12]
| t1f1 & sy_out
| alu_xrd & xr[4]
| alu_ard & acc[4]
| alu_frd & psw_ac
| alu_srd & s[4] );
assign d[3] = ~reset & ~alu_zrd &
( dbin_ext & di[3]
| mxrl & mxo[3]
| mxrh & mxo[11]
| t1f1 & sy_hlta
| alu_xrd & xr[3]
| alu_ard & acc[3]
| alu_frd & 1'b0
| alu_srd & s[3] );
assign d[2] = ~reset & ~alu_zrd &
( dbin_ext & di[2]
| mxrl & mxo[2]
| mxrh & mxo[10]
| t1f1 & sy_stack
| alu_xrd & xr[2]
| alu_ard & acc[2]
| alu_frd & psw_p
| alu_srd & s[2] );
assign d[1] = ~reset & ~alu_zrd &
( dbin_ext & di[1]
| mxrl & mxo[1]
| mxrh & mxo[9]
| t1f1 & sy_wo_n
| alu_xrd & xr[1]
| alu_ard & acc[1]
| alu_frd & 1'b1
| alu_srd & s[1] );
assign d[0] = ~reset & ~alu_zrd &
( dbin_ext & di[0]
| mxrl & mxo[0]
| mxrh & mxo[8]
| t1f1 & sy_inta
| alu_xrd & xr[0]
| alu_ard & acc[0]
| alu_frd & psw_c
| alu_srd & s[0] );
always @(posedge clk)
begin
if (f2 & db_stb) db <= d;
if (f2) abufena <= (~twt2 | ~thalt) & ~hlda_pin;
if (f1) db_stb <= t1 | (~sy_wo_n & t2);
if (f1) t851 <= t1 | (~sy_wo_n & (t2 | tw | t3));
if (f2) db_ena <= ~reset & t851;
end
//______________________________________________________________________________
//
// reset input buffer
//
always @(posedge clk)
begin
if (f1) t404 <= pin_reset;
if (f2) reset <= t404;
end
//______________________________________________________________________________
//
// hold input buffer
//
assign pin_hlda = hlda_pin;
assign hlda = hold & (t773 | (t3 & sy_wo_n) | (~m1 & sy_hlta) | t735);
assign h889 = t2f1 | twf1;
always @(posedge clk)
begin
if (f1) t712 <= ~sy_wo_n & t3;
if (f2) t735 <= t712;
if (~f2) t382 <= pin_hold;
if (f2) t383 <= ((~t382 & hold) | t383); // extend the front detector pulse for entire F2 duration
if (~f2) t383 <= 1'b0;
if (f2) t773 <= hlda_pin;
if (f1) hlda_pin <= hlda;
end
always @(posedge clk)
begin
if (reset)
hold <= 1'b0;
else
if (f2)
begin
if (t382)
begin
if (~sy_inta & h889) hold <= 1'b1;
end
else
hold <= 1'b0;
end
end
//______________________________________________________________________________
//
assign pin_dbin = dbin_pin;
assign pin_wr_n = wr_n;
assign pin_sync = sync;
always @(posedge clk)
begin
dbinf2 <= (f2 | dbin_pin) & ((t1124 & (m1f1 | ~sy_hlta)) | dbinf2);
if (dbin_pin) di <= pin_din;
if (f2) dbin_pin <= t1124 & (m1f1 | ~sy_hlta);
if (f2) sync <= ~ready_int & t1011;
if (f1) t1011 <= t1 & ~reset;
if (f1) t1124 <= (t2 | tw) & sy_wo_n;
if (f1) wr_n <= ~(t3 | tw) | ready_int | sy_wo_n;
end
//______________________________________________________________________________
//
// ready pin and internal circuits
//
assign ready_int = (m4 | m5) & id_dad;
assign ready = ready_int | pin_ready;
assign pin_wait = twf1;
//______________________________________________________________________________
//
// register unit - 6 16-bit registers
//
// r0 - pc
// r1 - hl, de
// r2 - de, hl
// r3 - bc
// r4 - sp
// r5 - wz
//
assign t1467 = tree1 | (id04 & t4f1 & ~id_xthl);
assign t1519 = tree2 | (id00 & t4f1 & ~id_xthl);
assign mxi = inc16 ? (a + 16'h0001)
: dec16 ? (a - 16'h0001)
: a;
assign inc16 = iad16 & ~dec16;
assign dec16 = iad16 & id05 & (t4f1 | t5f1 | m4f1 | m5f1);
assign iad16 = ~(id00 & (t4f1 | t5f1)) & (~minta | m5 | t3144);
assign mxw16 = t3403;
assign mxwadr = t3363 | (t4f1 & ~id_dad & ~id_hlt);
assign t1513 = (t4f1 & id07) | t3335;
assign t1514 = (t4f1 & id08) | t3361;
assign mxrh = t2998 | (id08 & t4f1 & ~i03);
assign mxrl = t3047 | (id08 & t4f1 & i03);
assign mxwh = t2817 | (t2806 & ~i03);
assign mxwl = t2819 | (t2806 & i03);
assign mxr0 = tree0;
assign mxr1 = xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519)
| ~xchg_dh & (t1513 | t1514) & (i14 & ~i25);
assign mxr2 = xchg_dh & (t1513 | t1514) & (i14 & ~i25)
| ~xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519);
assign mxr3 = (t1513 | t1514) & (~i14 & ~i25);
assign mxr4 = t1467 | (t1513 & i14 & i25);
assign mxr5 = ~(t1467 | t1513 | t1514 | t1519 | mxr0);
always @ (posedge clk)
begin
if (f1) t3144 <= t4 | t5 | (m4 & ~id02);
xchg_tt <= id_xchg & t2;
xchg_dh <= ~reset & ((xchg_tt & ~(id_xchg & t2)) ? ~xchg_dh : xchg_dh);
end
always @ (*)
case ({mxr0, mxr1, mxr2, mxr3, mxr4, mxr5})
6'b100000: mxo = r16_pc;
6'b010000: mxo = r16_hl;
6'b001000: mxo = r16_de;
6'b000100: mxo = r16_bc;
6'b000010: mxo = r16_sp;
6'b000001: mxo = r16_wz;
default: mxo = 16'h0000;
endcase
always @ (posedge clk)
if (f2)
begin
if (mxwadr) a <= mxo;
if (mxw16)
begin
if (mxr0) r16_pc <= mxi;
if (mxr1) r16_hl <= mxi;
if (mxr2) r16_de <= mxi;
if (mxr3) r16_bc <= mxi;
if (mxr4) r16_sp <= mxi;
if (mxr5) r16_wz <= mxi;
end
else
begin
if (mxwl)
begin
if (mxr0) r16_pc[7:0] <= d;
if (mxr1) r16_hl[7:0] <= d;
if (mxr2) r16_de[7:0] <= d;
if (mxr3) r16_bc[7:0] <= d;
if (mxr4) r16_sp[7:0] <= d;
if (mxr5) r16_wz[7:0] <= d;
end
if (mxwh)
begin
if (mxr0) r16_pc[15:8] <= d;
if (mxr1) r16_hl[15:8] <= d;
if (mxr2) r16_de[15:8] <= d;
if (mxr3) r16_bc[15:8] <= d;
if (mxr4) r16_sp[15:8] <= d;
if (mxr5) r16_wz[15:8] <= d;
end
end
end
//______________________________________________________________________________
//
// processor state
//
assign sy_hlta = id_hlt;
assign sy_m1 = m1;
assign sy_inp = m5 & id_in;
assign sy_out = m5 & id_out;
assign sy_inta = inta;
assign sy_memr = sy_wo_n & ~sy_inp & ~minta;
assign sy_wo_n = m1 | m2 | m3 | (((m4 & ~id86) | (m5 & ~id85)) & ~ready_int);
always @(posedge clk)
begin
if (f1)
begin
sy_stack <= (t1 & t1460)
| (t3 & m3 & id_cxx & ~jmptake)
| (t5 & m1 & id_rxx & ~jmptake);
end
end
//______________________________________________________________________________
//
// ticks state machine
//
assign twt2 = (t2f1 | twf1) & ~start;
assign thalt = ~m1 & sy_hlta;
always @(posedge clk)
begin
if (f1)
begin
t1f1 <= t1 & ~reset; // ensure the reliable start after reset
t2f1 <= t2;
twf1 <= tw;
t3f1 <= t3;
t4f1 <= t4;
t5f1 <= t5;
end
if (f2)
begin
t1 <= start;
t2 <= ~start & t1f1;
tw <= ~start & (t2f1 | twf1) & (~ready | thalt);
t3 <= ~start & (t2f1 | twf1) & ready & ~thalt;
t4 <= ~start & t3f1 & ms0 & ~ms1;
t5 <= ~start & t4f1 & ms0 & ~ms1;
end
end
//______________________________________________________________________________
//
assign m836 = m1f1 & id82;
assign m839 = ~t976 | ~sy_hlta;
assign m871 = t789 | id81;
assign start = ~m839
| t953
| (eom & ~(hold & t887))
| (f2 & ((~t382 & hold) | t383) & ~(twf1 | t3f1 | t4f1 | t5f1));
assign ms0 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(eom & ~m836);
assign ms1 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(m871 & ~m836) & eom;
always @(posedge clk)
begin
if (f1)
begin
t789 <= (id84 & m3) | (id83 & ~id_mvim & m4) | m5;
t887 <= hold;
t953 <= reset;
t976 <= t980 & m4;
eom <= t5
| t4 & m1 & id80
| t3 & m2
| t3 & m3
| t3 & m4
| t3 & m5 & ~id_xthl;
end
if (f2)
begin
t980 <= sy_inta;
end
end
//______________________________________________________________________________
//
// processor cycles state machine
//
always @(posedge clk)
begin
if (f1)
begin
m1f1 <= m1;
m2f1 <= m2;
m3f1 <= m3;
m4f1 <= m4;
m5f1 <= m5;
end
if (f2)
begin
m1 <= (~ms0 & ~ms1) | (~ms1 & m1f1);
m2 <= (~ms0 | ~ms1) & ((ms0 & m2f1) | (ms1 & m1f1));
m3 <= (ms0 & m3f1) | (ms1 & m2f1);
m4 <= (ms0 & m4f1) | (ms1 & m3f1) | (ms0 & ms1);
m5 <= (ms0 & m5f1) | (ms1 & m4f1);
end
end
//______________________________________________________________________________
//
// interrupt logic
//
assign irq = intr & inte & ~reset & ~hold;
assign pin_inte = inte;
always @(posedge clk)
begin
if (f2) intr <= pin_int;
if (f2) mstart <= ~ms0 & ~ms1;
if (sy_inta) minta <= 1;
if (f1 & t1 & m1) minta <= 0;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
inta <= 0;
inte <= 0;
end
else
begin
if (f1)
begin
if (irq & ((tw & sy_hlta) | (mstart & ~id_eidi))) inta <= 1;
if (~intr | id_eidi | (t5 & id_rst)) inta <= 0;
end
if (f2)
begin
if (t1f1 & id_eidi) inte <= i[3];
if (t1f1 & sy_inta) inte <= 0;
end
end
end
//______________________________________________________________________________
//
// instruction register and decoder
//
function cmp
(
input [7:0] i,
input [7:0] c,
input [7:0] m
);
cmp = &(~(i ^ c) | m);
endfunction
assign imx = ~(id_op | (id_mov & t4));
assign acc_sel = imx ? (i[5:3] == 3'b111) : (i[2:0] == 3'b111);
assign jmpflag = (psw_c & i14 & ~i25) // Intel original: d[0] instead of psw_c
| (psw_p & ~i14 & i25) // Intel original: d[2] instead of psw_p
| (psw_z & ~i14 & ~i25) // Intel original: d[6] instead of psw_z
| (psw_s & i14 & i25); // Intel original: d[7] instead of psw_s
always @(posedge clk)
begin
//
// Simplify the D-bus multiplexer and feed the I-register by input pins directly
//
if (~f2 & (reset | (m1 & t3))) i <= pin_din;
if (f1)
begin
i25 <= imx ? i[5] : i[2];
i14 <= imx ? i[4] : i[1];
i03 <= imx ? i[3] : i[0];
end
end
assign goto = id_rst | id_jmp | id_call | (jmptake & (id_cxx | id_jxx));
assign t1460 = (t1 & ( (m2 & id00)
| (m3 & id00)
| (m4 & (id01 | id04))
| (m5 & (id01 | id04)))
| t2 & ( (m2 & id00)
| (m4 & id01)
| (m5 & id01))
| t3 & ( (m4 & (id04 | id_sphl)))
| t5 & ( (m1 & (id04 | id_sphl)))) & ~(~jmptake & id_cxx & t5);
always @(posedge clk)
begin
if (f2 & t4f1)
begin
jmptake <= i03 ? jmpflag : ~jmpflag;
end
if (f1)
begin
tree0 <= t1 & ( (m1 & ~goto)
| (m2 & ~id_xthl)
| (m3 & ~id_xthl)
| (m4 & id02))
| t2 & ( m1
| (m2 & ~id_xthl)
| (m3 & ~id_xthl)
| (m4 & (id02 | id_rst | id_cxx | id_call))
| (m5 & (id_rst | id_cxx | id_call)))
| t3 & ( (m4 & (id_ret | id_rxx))
| (m5 & (id_ret | id_rxx)))
| t5 & id_pchl;
tree1 <= t1460;
tree2 <= t1 & ( (m4 & (id_mov | id_idr | id_op))
| (m5 & id08))
| t2 & ( (m4 & (id_shld | id00 | id_dad))
| (m5 & (id_shld | id00 | id_dad)))
| t3 & ( (m4 & (id_lhld | id_dad))
| (m5 & (id_lhld | id_dad)))
| t5 & m5;
t2806 <= id08 & ((t3 & m4) | (t5 & m1));
t2817 <= reset | (t3 & (m1 | m3 | (m4 & id_io) | (m5 & id06)));
t2819 <= reset | (t3 & (m2 | (m4 & id06) | (m5 & id_rst)));
t3047 <= m4 & (t1 | t2) & id_dad
| t2 & ((m4 & id_shld) | (m5 & id03));
t2998 <= (t1 | t2) & m5 & id_dad
| t2 & ((m5 & id_shld) | (m4 & id03));
t3403 <= t2 & ( (m1 | m2)
| (m3 & ~id_xthl)
| ((m4 | m5) & ~id_dad & ~id09))
| t3 & m4 & id09
| t5 & (m5 | (m1 & ~id08));
t3363 <= t1 & (m1 | m2 | m3 | ((m4 | m5) & ~id_hlt & ~id_dad));
t3335 <= id07 & ((t1 & (m4 | m5)) | (t3 & (m2 | m3)) | t5);
t3361 <= t1 & m4 & id_lsax
| t2 & id10 & ~sy_wo_n
| t3 & id10 & sy_wo_n & (m4 | m5)
| t5 & id08 & m1;
end
end
assign id_nop = cmp(i, 8'b00xxx000, 8'b00111000);
assign id_lxi = cmp(i, 8'b00xx0001, 8'b00110000);
assign id_lsax = cmp(i, 8'b000xx010, 8'b00011000);
assign id_inx = cmp(i, 8'b00xx0011, 8'b00110000);
assign id_inr = cmp(i, 8'b00xxx100, 8'b00111000);
assign id_dcr = cmp(i, 8'b00xxx101, 8'b00111000);
assign id_idr = cmp(i, 8'b00xxx10x, 8'b00111001);
assign id_mvi = cmp(i, 8'b00xxx110, 8'b00111000);
assign id_dad = cmp(i, 8'b00xx1001, 8'b00110000);
assign id_dcx = cmp(i, 8'b00xx1011, 8'b00110000);
assign id_opa = cmp(i, 8'b00xxx111, 8'b00111000);
assign id_idm = cmp(i, 8'b0011010x, 8'b00000001);
assign id_stlda = cmp(i, 8'b0011x010, 8'b00001000);
assign id_mvim = cmp(i, 8'b00110110, 8'b00000000);
assign id_shld = cmp(i, 8'b00100010, 8'b00000000);
assign id_lhld = cmp(i, 8'b00101010, 8'b00000000);
assign id_mvmr = cmp(i, 8'b01110xxx, 8'b00000111) & ~id_hlt;
assign id_mvrm = cmp(i, 8'b01xxx110, 8'b00111000) & ~id_hlt;
assign id_hlt = cmp(i, 8'b01110110, 8'b00000000);
assign id_mov = cmp(i, 8'b01xxxxxx, 8'b00111111);
assign id_op = cmp(i, 8'b10xxxxxx, 8'b00111111);
assign id_opm = cmp(i, 8'b10xxx110, 8'b00111000);
assign id_pop = cmp(i, 8'b11xx0001, 8'b00110000);
assign id_push = cmp(i, 8'b11xx0101, 8'b00110000);
assign id_rst = cmp(i, 8'b11xxx111, 8'b00111000);
assign id_xthl = cmp(i, 8'b11100011, 8'b00000000);
assign id_sphl = cmp(i, 8'b11111001, 8'b00000000);
assign id_pchl = cmp(i, 8'b11101001, 8'b00000000);
assign id_xchg = cmp(i, 8'b11101011, 8'b00000000);
assign id_cxx = cmp(i, 8'b11xxx100, 8'b00111000);
assign id_jxx = cmp(i, 8'b11xxx010, 8'b00111000);
assign id_rxx = cmp(i, 8'b11xxx000, 8'b00111000);
assign id_ret = cmp(i, 8'b110x1001, 8'b00010000);
assign id_call = cmp(i, 8'b11xx1101, 8'b00110000);
assign id_eidi = cmp(i, 8'b1111x011, 8'b00001000);
assign id_jmp = cmp(i, 8'b1100x011, 8'b00001000);
assign id_io = cmp(i, 8'b1101x011, 8'b00001000);
assign id_opi = cmp(i, 8'b11xxx110, 8'b00111000);
assign id_in = cmp(i, 8'b11011011, 8'b00000000);
assign id_popsw = cmp(i, 8'b11110001, 8'b00000000);
assign id_out = cmp(i, 8'b11010011, 8'b00000000);
assign id_11x = cmp(i, 8'b11xxxxxx, 8'b00111111);
assign id_pupsw = cmp(i, 8'b11110101, 8'b00000000);
assign id_rxc = ~i[5] & i[3] & id_opa;
assign id_sha = ~i[5] & id_opa;
assign id_rlc = (i[5:3] == 3'b000) & id_opa;
assign id_rar = (i[5:3] == 3'b011) & id_opa;
assign id_daa = (i[5:3] == 3'b100) & id_opa;
assign id_cma = (i[5:3] == 3'b101) & id_opa;
assign id_stc = (i[5:3] == 3'b110) & id_opa;
assign id_cmc = (i[5:3] == 3'b111) & id_opa;
assign id_add = (i[5:3] == 3'b000) & (id_op | id_opi);
assign id_adc = (i[5:3] == 3'b001) & (id_op | id_opi);
assign id_sub = (i[5:3] == 3'b010) & (id_op | id_opi);
assign id_sbb = (i[5:3] == 3'b011) & (id_op | id_opi);
assign id_ana = (i[5:3] == 3'b100) & (id_op | id_opi);
assign id_xra = (i[5:3] == 3'b101) & (id_op | id_opi);
assign id_ora = (i[5:3] == 3'b110) & (id_op | id_opi);
assign id_cmp = (i[5:3] == 3'b111) & (id_op | id_opi);
assign id80 = id_lxi | id_pop | id_opm | id_idm | id_dad
| id_xthl | id_xchg | id_jxx | id_ret | id_eidi
| id_nop | id_stlda | id_mvmr | id_mvrm | id_hlt
| id_opa | id_mvim | id_jmp | id_io | id_opi
| id_mvi | id_lsax | id_lhld | id_shld | id_op;
assign id81 = id_dcx | id_inx | id_sphl | id_pchl | id_xchg
| id_eidi | id_nop | id_opa | id_op | id_mov
| (id_idr & ~id82);
assign id82 = id_pop | id_push | id_opm | id_idm | id_dad
| id_rst | id_ret | id_rxx | id_mvrm | id_mvmr
| id_hlt | id_mvim | id_io | id_opi | id_mvi
| id_lsax;
assign id83 = id_opm | id_stlda | id_mvmr | id_mvrm | id_opi
| id_mvi | id_lsax;
assign id84 = id_lxi | id_jxx | id_jmp;
assign id85 = id_push | id_idm | id_rst | id_xthl | id_cxx
| id_call | id_mvim | id_shld | (id_io & ~i[3]);
assign id86 = id_push | id_rst | id_xthl | id_cxx | id_call
| id_mvmr | id_shld | (~i[3] & (id_lsax | id_stlda));
assign id00 = id_xthl | id_pchl | id_sphl;
assign id01 = id_pop | id_rxx | id_ret;
assign id02 = id_mvi | id_opi | id_io;
assign id03 = id_rst | id_push | id_xthl | id_cxx | id_call;
assign id04 = id_rst | id_push | id_xthl | id_cxx | id_call;
assign id05 = id_rst | id_push | id_xthl | id_cxx | id_call | id_dcx;
assign id06 = id_pop | id_rxx | id_ret | id_dad | id_lhld | id_io;
assign id07 = id_dcx | id_inx | id_lxi | id_dad;
assign id08 = id_mov | id_mvi | id_idr | id_op;
assign id09 = id_rst | id_push | id_xthl | id_cxx | id_call | id_shld;
assign id10 = id_pop | id_push | id_mvrm | id_mvi;
//______________________________________________________________________________
//
// function alu
// (
// input rxc,
// input ora,
// input ana,
// input xra,
// input x,
// input r,
// input nc,
// input rn,
// input cp
// );
// alu = x & r & cp & ~(rxc | ora | ana | xra)
// | nc & (cp | x | r) & ~(rxc | ora | ana | xra)
// | rxc & rn
// | ora & (x | r)
// | ana & (x & r)
// | xra & (x ^ r);
// endfunction
//
//
// assign s[0] = alu(id_rxc, id_ora, id_ana, id_xra, x[0], r[0], ~c[0], r[1], cl) | (id_rlc & c[7]);
// assign s[1] = alu(id_rxc, id_ora, id_ana, id_xra, x[1], r[1], ~c[1], r[2], c[0]);
// assign s[2] = alu(id_rxc, id_ora, id_ana, id_xra, x[2], r[2], ~c[2], r[3], c[1]);
// assign s[3] = alu(id_rxc, id_ora, id_ana, id_xra, x[3], r[3], ~c[3], r[4], c[2]);
// assign s[4] = alu(id_rxc, id_ora, id_ana, id_xra, x[4], r[4], ~c[4], r[5], c[3]);
// assign s[5] = alu(id_rxc, id_ora, id_ana, id_xra, x[5], r[5], ~c[5], r[6], c[4]);
// assign s[6] = alu(id_rxc, id_ora, id_ana, id_xra, x[6], r[6], ~c[6], r[7], c[5]);
// assign s[7] = alu(id_rxc, id_ora, id_ana, id_xra, x[7], r[7], ~c[7], ch, c[6]);
//
//
//______________________________________________________________________________
//
// arithmetic and logic unit
//
// assign alu_xwr = (f1 & m1 & t3) | (f2 & (a327 | t4f1 & (id_out | ~id_11x)));
//
assign alu_xwr = (a327 | t4f1 & (id_rst | id_out | ~id_11x));
assign alu_xout = ~(id_sub | id_sbb | id_cmp | id_cma);
assign alu_xrd = t1698 | a358;
assign x = alu_xout ? xr : ~xr;
assign alu_ald = t2222 & ( id_adc | id_add | id_daa | id_xra | id_sbb
| id_sub | id_ana | id_ora | id_sha | id_cma);
assign alu_ard = t1375 | a398;
assign alu_awr = t1497 | a357;
assign alu_r00 = id_dcr & t4f1;
assign alu_srd = t1668;
assign alu_rwr = t1780;
assign alu_rld = t4f1 & (id_sha | id_op | id_opi);
assign daa = id_daa & t4f1;
assign daa_x6 = (acc[3] & (acc[2] | acc[1])) | psw_ac;
assign daa_6x = ((acc[3] & (acc[2] | acc[1])) & acc[4] & acc[7])
| (acc[7] & (acc[6] | acc[5])) | tmp_c;
assign s = {7'b0000000, id_rlc & c[7]}
| ((id_rxc | id_ora | id_ana | id_xra) ? 8'h00 : (x + r + cl))
| (id_rxc ? {ch, r[7:1]} : 8'h00)
| (id_ora ? (x | r) : 8'h00)
| (id_ana ? (x & r) : 8'h00)
| (id_xra ? (x ^ r) : 8'h00);
assign cl = tmp_c & ~id_daa & ~id_rlc & ~id_ora & ~id_xra & ~id_rxc;
assign ch = tmp_c & id_rar | r[0] & ~id_rar;
//
// wire ca0_n, ca2_n, ca1, ca3;
// assign ca0_n = ~(cl & (x[0] | r[0])) & ~(x[0] & r[0]) & ~(id_ana & id_rxc);
// assign ca2_n = ~(ca1 & (x[2] | r[2])) & ~(x[2] & r[2]) & ~(id_ana & id_rxc);
// assign ca1 = ~(~x[1] & ~r[1]) & ~(ca0_n & (~x[1] | ~r[1])) & ~(id_ora | id_rxc | id_xra);
// assign ca3 = ~(~x[3] & ~r[3]) & ~(ca2_n & (~x[3] | ~r[3])) & ~(id_ora | id_rxc | id_xra);
//
assign c[0] = (r[0] & x[0]) | (cl & (r[0] | x[0]));
assign c[1] = (r[1] & x[1]) | (c[0] & (r[1] | x[1]));
assign c[2] = (r[2] & x[2]) | (c[1] & (r[2] | x[2]));
assign c[3] = (r[3] & x[3]) | (c[2] & (r[3] | x[3]));
assign c[4] = (r[4] & x[4]) | (c[3] & (r[4] | x[4]));
assign c[5] = (r[5] & x[5]) | (c[4] & (r[5] | x[5]));
assign c[6] = (r[6] & x[6]) | (c[5] & (r[6] | x[6]));
assign c[7] = (r[7] & x[7]) | (c[6] & (r[7] | x[7]));
assign alu_frd = t2046; /* | t4f1 & (id_11x & ~id_out); */
assign alu_zrd = m1f1 & t3f1;
assign a398 = t1993 & ((t1994 & id08) | id_opa | id_stlda | id_lsax | id_io);
always @(posedge clk)
begin
if (f1)
begin
t1375 <= t2 & m4 & id_pupsw;
t1497 <= t3 & m5 & id_popsw;
t1698 <= t5 & m1 & ~id_inr & ~id_dcr
| t3 & m5 & id_rst;
t1668 <= t2 & m5 & (id_inr | id_dcr)
| t3 & m5 & id_dad
| t3 & m4 & id_dad
| t5 & m1 & (id_inr | id_dcr);
t1780 <= t3 & m1
| t1 & (m4 | m5) & id_dad;
t2222 <= (t2 & m1) | (t1 & m5);
a327 <= t3 & m4 & ~(id_dad | id_out | id_rst)
| t2 & (m4 | m5) & id_dad;
a357 <= t3 & m5 & (id_io | id_mvim) & sy_wo_n
| t3 & m4 & (id_stlda | id_lsax | id_mvmr) & sy_wo_n
| acc_sel & id08 & (t5 & m1 | t3 & m4);
a358 <= t2 & ~sy_wo_n & (id_io | id_mvim | id_stlda | id_lsax | id_mvmr);
psw_ld <= t3 & m4 & id_popsw;
psw_wr <= t2 & m1 & (id_opi | id_inr | id_dcr | id_daa | id_op);
t2046 <= t2 & m5 & id_pupsw; /* | reset | t3 & m1; */
//
// t2047 <= reset
// | t3 & m1
// | t3 & m5 & id_rst;
//
t1993 <= t4 & m1;
t1994 <= acc_sel;
t2133 <= ~id_rxc & c[7];
t2175 <= t3 & m1
| t2 & m5 & id_dad;
end
end
always @(posedge clk)
begin
if (f2)
begin
if (alu_xwr) xr <= id_rst ? (i & 8'b00111000) : d;
if (alu_awr) acc <= d;
if (alu_ald) acc <= s;
if (alu_rld) r <= acc;
if (alu_rwr) r <= d;
if (alu_r00) r <= 8'hff;
if (daa)
begin
r[1] <= daa_x6;
r[2] <= daa_x6;
r[5] <= daa_6x;
r[6] <= daa_6x;
end
if (psw_ld)
begin
psw_c <= d[0]; // x register was in original Intel design
psw_p <= d[2];
psw_ac <= d[4];
psw_z <= d[6];
psw_s <= d[7];
end
if (psw_wr)
begin
psw_p <= ~(^s);
psw_ac <= (c[3] & ~id_xra & ~id_ora & ~id_rxc) | (id_ana & (x[3] | r[3]));
psw_z <= ~(|s);
psw_s <= s[7];
end
if (t2222)
begin
if (id_xra | id_stc | id_ora | id_ana | id_cmc)
psw_c <= ~tmp_c;
if (id_cmp | id_sbb | id_sub)
psw_c <= ~(t2133 | id_rxc & x[0]);
if (id_dad | id_sha | id_adc | id_add)
psw_c <= t2133 | id_rxc & x[0];
end
if (daa & daa_6x)
psw_c <= 1'b1;
if (t2175)
tmp_c <= psw_c;
if (t4f1)
begin
if (id_sbb)
tmp_c <= ~psw_c;
if (id_inr | id_ora | id_xra | id_ana | id_cmp | id_sub)
tmp_c <= 1'b1;
if (id_dad | id_cma | id_dcr | id_add | id_stc)
tmp_c <= 1'b0;
end
end
end
//______________________________________________________________________________
//
endmodule
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