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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file snescmd_buf.v when simulating
// the core, snescmd_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module snescmd_buf(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [8 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_7_b2s_simple_fifo
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/02/2016
// Design Name:
// Module Name: noise_generator
// Project Name:
// Target Devices:
// Tool versions:
// Description: generate random bit on edge of clk
//
// 32 bit LFSR (period 2^32 bits)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module noise_generator(clk,reset,random_bit);
parameter SEED = 32'b10101011101010111010101110101011;// LFSR starting state
parameter TAPS = 31'b0000000000000000000000001100010;// LFSR feedback taps
input clk;
input reset;
output random_bit;
reg [31:0] shift_register;
initial shift_register = SEED;
always @(posedge clk)
begin
if(!reset)
begin
// feedback 1,5,6
if(shift_register[31])
shift_register[31:1] <= shift_register[30:0]^TAPS;
else
shift_register[31:1] <= shift_register[30:0];
// feedback 31
shift_register[0] <= shift_register[31];
end
else
begin
// reset seed
shift_register <= SEED;
end
end
// clock out random bits from the end of the register
assign random_bit = shift_register[31];
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: task_scope.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
// Test for task scope lookup in VVP
module test;
wire w;
jobs j(w);
task ini;
begin
j.set(1'bz);
end
endtask
initial
begin
ini;
#1;
j.set(1'b1);
#1;
if (w===1)
$display("PASSED");
else
$display("FAILED");
end
endmodule // test
module jobs (out);
output out;
reg out;
task set;
input val;
begin
#1 out = val;
end
endtask
endmodule // jobs
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Strings.String.
Require Import Coq.Arith.PeanoNat.
Require Import Coq.micromega.Lia.
Require Import Coq.NArith.NArith.
Require Import Coq.ZArith.ZArith.
Require Import Coq.Init.Byte.
Require Import Coq.Lists.List.
Require Import coqutil.Tactics.Tactics.
Require Import Cava.Util.BitArithmetic.
Require Import Cava.Util.BitArithmeticProperties.
Require Import Cava.Util.Byte.
Require Import Cava.Util.If.
Require Import Cava.Util.List.
Require Import Cava.Util.Nat.
Require Import Cava.Util.Tactics.
Require Import Cava.Types.
Require Import Cava.Expr.
Require Import Cava.ExprProperties.
Require Import Cava.Invariant.
Require Import Cava.Primitives.
Require Import Cava.Semantics.
Require Import HmacSpec.SHA256Properties.
Require Import HmacHardware.Sha256.
Require HmacSpec.SHA256.
Import ListNotations.
Require Import coqutil.Tactics.autoforward.
Ltac autoforward_in db H ::=
let tmp := fresh H in
rename H into tmp;
let A := type of tmp in
pose proof ((ltac:(typeclasses eauto with db) : autoforward A _) tmp) as H;
(* Recently, this `move` was added in coqutil, which breaks this proof script,
because through destruct_one_match_hyp, it depends on the hypotheses order,
and the most straightforward way to fix the broken proofs requires too
much memory to work on CI *)
(* move H after tmp; *)
clear tmp.
Lemma step_rotr n (x : denote_type sha_word) :
step (rotr n) tt (x,tt) = (tt, SHA256.ROTR (N.of_nat n) x).
Proof.
cbv [rotr]. stepsimpl.
cbv [SHA256.ROTR SHA256.truncating_shiftl SHA256.w].
repeat (f_equal; try lia).
Qed.
Hint Rewrite @step_rotr using solve [eauto] : stepsimpl.
Lemma step_sha256_compress
(H : denote_type sha_digest)
(k w : denote_type sha_word) (t : nat) (W : list N) :
k = nth t SHA256.K 0%N ->
w = nth t W 0%N ->
step sha256_compress tt (H,(k,(w,tt)))
= (tt, SHA256.sha256_compress W (List.resize 0%N 8 H) t).
Proof.
intros. rewrite resize_map_nth. cbn [List.map seq].
subst. cbv [sha256_compress]. stepsimpl.
autorewrite with push_nth. reflexivity.
Qed.
Hint Rewrite @step_sha256_compress using solve [eauto] : stepsimpl.
Lemma step_sha256_message_schedule_update
(w0 w1 w9 w14 : denote_type sha_word) (t i : nat) msg :
w0 = nth (t-16) (SHA256Alt.W msg i) 0%N ->
w1 = nth (t-15) (SHA256Alt.W msg i) 0%N ->
w9 = nth (t-7) (SHA256Alt.W msg i) 0%N ->
w14 = nth (t-2) (SHA256Alt.W msg i) 0%N ->
(16 <= t < 64) ->
step sha256_message_schedule_update tt (w0, (w1, (w9, (w14, tt))))
= (tt, nth t (SHA256Alt.W msg i) 0%N).
Proof.
intros. cbv [sha256_message_schedule_update]. stepsimpl.
rewrite nth_W_alt by lia. destruct_one_match; [ lia | ].
repeat match goal with H : _ = nth ?n _ _ |- _ =>
rewrite <-H end.
cbv [SHA256.add_mod SHA256.w]. apply f_equal.
cbv [SHA256.sigma1 SHA256.sigma0 SHA256.SHR].
cbv [N.of_nat Pos.of_succ_nat Pos.succ]. clear.
(* fully compute moduli *)
repeat match goal with |- context [(_ mod ?m)%N] =>
progress compute_expr m end.
(* convert to Z, solve with Z.div_mod_to_equations *)
zify.
repeat rewrite Z.rem_mod_nonneg; Z.div_mod_to_equations; lia.
Qed.
Hint Rewrite @step_sha256_message_schedule_update using solve [eauto] : stepsimpl.
Lemma step_sha256_round_constants (round : denote_type sha_round) :
step sha256_round_constants tt (round, tt)
= (tt, nth (N.to_nat round) SHA256.K 0%N).
Proof. reflexivity. Qed.
Hint Rewrite @step_sha256_round_constants using solve [eauto] : stepsimpl.
(* High-level representation for sha256_inner:
msg : message seen so far (padded)
i : block index
t : round number (compression loop)
inner_done : whether the computation for the current block is complete
cleared : boolean indicating whether the circuit has been cleared
*)
Instance sha256_inner_invariant
: invariant_for sha256_inner (list N * nat * nat * bool * bool) :=
fun (state : denote_type (sha_digest ** sha_block ** Bit ** sha_round))
repr =>
let '(current_digest, (message_schedule, (done, round))) := state in
let '(msg, i, t, inner_done, cleared) := repr in
(* inner_done matches the [done] bit *)
inner_done = done
(* ...and if we've been cleared, then we're in the reset state *)
/\ (if cleared
then current_digest = SHA256.H0
/\ done = true
/\ t = 0
/\ i = 0
/\ msg = []
else
(* ...if we're not cleared, the current digest is the expected digest *)
let initial_digest :=
fold_left (SHA256Alt.sha256_step msg) (seq 0 i) SHA256.H0 in
current_digest = fold_left (SHA256.sha256_compress (SHA256Alt.W msg i))
(seq 0 t) initial_digest
(* ...and the message has (S i) blocks (1 block = 16 words) *)
/\ S i * 16 = length msg
)
/\ if done
then if cleared then t = 0 else t = 64
else
(* the round is < 64 *)
(round < 64)%N
(* ...and inner_round matches [round] *)
/\ t = N.to_nat round
(* ...and the message schedule is the expected slice of the message *)
/\ message_schedule = List.slice 0%N (SHA256Alt.W msg i) (t - 15) 16.
Instance sha256_inner_specification
: specification_for sha256_inner (list N * nat * nat * bool * bool) :=
{| reset_repr := ([], 0%nat, 0%nat, true, true);
update_repr :=
fun (input : denote_type [Bit; sha_block; sha_digest; Bit])
repr =>
let '(block_valid, (block, (initial_digest, (clear,_)))) := input in
let '(msg, i, t, inner_done, cleared) := repr in
let updated_msg := msg ++ block in
if clear
then ([], 0%nat, 0%nat, true, true)
else if inner_done
then if block_valid
then if cleared
then
(* start with i=0 *)
(updated_msg, 0, 0, false, false)
else
(* starting new block *)
(updated_msg, S i, 0, false, false)
else
(* unchanged *)
(msg, i, t, inner_done, cleared)
else (msg, i, S t, t =? 63, false);
precondition :=
fun (input : denote_type [Bit; sha_block; sha_digest; Bit])
repr =>
let '(block_valid, (block, (initial_digest, (clear,_)))) := input in
let '(msg, i, t, inner_done, cleared) := repr in
if block_valid
then
let new_i := if cleared then 0 else S i in
(* a valid block is passed only if we're not busy *)
inner_done = true
(* ...and the initial digest is the digest up to (the new value of) i *)
/\ initial_digest = fold_left (SHA256Alt.sha256_step (msg ++ block))
(seq 0 new_i) SHA256.H0
(* and the length of the block is 16 *)
/\ length block = 16
else
if inner_done
then True (* no requirements; stay in the done state until block is valid *)
else
(* the initial digest is the digest up to i *)
initial_digest = fold_left (SHA256Alt.sha256_step msg)
(seq 0 i) SHA256.H0;
postcondition :=
fun (input : denote_type [Bit; sha_block; sha_digest; Bit])
repr (output : denote_type (sha_digest ** Bit)) =>
let '(block_valid, (block, (initial_digest, (clear,_)))) := input in
let '(msg, i, t, inner_done, cleared) := repr in
let new_done := if clear
then true
else if block_valid
then false
else if inner_done
then true
else t =? 63 in
exists output_value : denote_type sha_digest,
output = (output_value, new_done)
/\ (* the output value is only meaningful in the case when we're done and not
cleared *)
(if cleared
then True (* no guarantees *)
else if clear
then True (* no guarantees *)
else if new_done
then
(* if the initial digest is correct, the output value
matches the expected digest *)
initial_digest = fold_left (SHA256Alt.sha256_step msg) (seq 0 i) SHA256.H0 ->
output_value = fold_left (SHA256Alt.sha256_step msg) (seq 0 (S i)) SHA256.H0
else True (* no guarantees *))
|}.
Lemma sha256_inner_invariant_at_reset : invariant_at_reset sha256_inner.
Proof.
simplify_invariant sha256_inner. repeat split.
Qed.
Local Hint Unfold sha256_inner_state : stepsimpl.
Lemma sha256_inner_invariant_preserved : invariant_preserved sha256_inner.
Proof.
simplify_invariant sha256_inner. cbn [absorb_any].
simplify_spec sha256_inner.
intros (block_valid, (block, (initial_digest, (clear, [])))).
intros (current_digest, (message_schedule, (done, round))).
intros ((((msg, i), t), inner_done), cleared).
intros; logical_simplify; subst.
cbv [sha256_inner K]. cbn [negb]. stepsimpl.
repeat (destruct_pair_let; cbn [fst snd]).
autorewrite with tuple_if; cbn [fst snd].
(* destruct cases for [clear] *)
destruct clear; logical_simplify; [ tauto | ].
(* destruct cases for [block_valid] *)
destruct block_valid; logical_simplify; subst;
[ destruct cleared; logical_simplify; subst;
pull_snoc; natsimpl; push_length;
rewrite ?slice0_W_alt by length_hammer;
ssplit; (lia || reflexivity) | ].
(* destruct cases for [done] *)
destruct done; logical_simplify; subst; boolsimpl;
[ ssplit; auto; tauto | ].
(* destruct cases for [cleared] *)
destruct cleared; logical_simplify; subst; boolsimpl;
[ destr (round =? 63)%N;
ssplit; repeat destruct_one_match; lia | ].
destr (N.to_nat round =? 63);
(destr (round =? 63)%N; try lia; [ ]); subst;
[ ssplit; lazymatch goal with
| |- context [sha256_compress] => idtac
| |- _ => lia
end;
(* handle case involving last compression step *)
subst; destruct_one_match; try lia; [ ];
erewrite step_sha256_compress with (t:=63)
by (push_resize; push_nth; reflexivity);
cbn [fst snd]; push_resize;
rewrite seq_snoc with (len:=63); rewrite fold_left_app;
reflexivity | ].
(* For remaining cases, the new [done] is always 0 *)
cbn [N.lor N.eqb].
(* destruct case statements *)
repeat first [ discriminate
| lia
| destruct_one_match_hyp
| destruct_one_match ].
all:try (rewrite (N.mod_small _ (2 ^ N.of_nat 7))
by (change (2 ^ N.of_nat 7)%N with 128%N; lia)).
all:push_resize; push_nth.
all:repeat match goal with
| |- context [(?x <? ?y)] =>
destr (x <? y); try lia; [ ]
| |- context [(?x =? ?y)] =>
destr (x =? y); try lia; [ ]
end.
all:natsimpl.
all:ssplit;
lazymatch goal with
| |- ?x = ?x => reflexivity
| |- (_ < _)%N => lia
| |- @eq nat _ _ => length_hammer
| |- True => tauto
| _ => idtac
end.
(* solve subgoals about compression *)
all:
lazymatch goal with
| |- context [sha256_compress] =>
erewrite step_sha256_compress with (t:=N.to_nat round) by (f_equal; lia);
cbn [fst snd]; pull_snoc; rewrite ?resize_noop by (symmetry; length_hammer);
try reflexivity
| |- _ => idtac
end.
(* remaining subgoals should all be about message schedule: solve those *)
all:lazymatch goal with
| |- context [sha256_message_schedule_update] =>
erewrite step_sha256_message_schedule_update with (t:=(N.to_nat round+1))
by lazymatch goal with
| |- nth _ _ _ = nth _ _ _ => f_equal; lia
| _ => lia
end; cbn [fst snd];
lazymatch goal with
| |- context [List.slice ?d ?ls ?start ?len ++ [nth ?n ?ls ?d]] =>
replace n with (start + len) by lia
end; rewrite slice_snoc, tl_slice; f_equal; lia
end.
Qed.
Lemma sha256_inner_output_correct : output_correct sha256_inner.
Proof.
simplify_invariant sha256_inner. cbn [absorb_any].
simplify_spec sha256_inner.
intros (block_valid, (block, (initial_digest, (clear, [])))).
intros (current_digest, (message_schedule, (done, round))).
intros ((((msg, i), t), inner_done), cleared).
intros. logical_simplify. subst. cbn [fst snd] in *.
cbv [sha256_inner K]. stepsimpl.
repeat (destruct_pair_let; cbn [fst snd]).
autorewrite with tuple_if; cbn [fst snd].
stepsimpl. push_resize.
(* some general-purpose simplification *)
pull_snoc; natsimpl.
eexists. ssplit; [ | ].
{ apply f_equal2; [ reflexivity | ].
(* prove that done bit matches spec *)
boolsimpl. destr clear;[ reflexivity | ].
destr block_valid; [ reflexivity | ].
destr done; boolsimpl; [ reflexivity | ].
logical_simplify; subst.
destr (N.to_nat round =? 63); destr (round =? 63)%N; lia. }
(* destruct cases for [cleared] *)
destruct cleared; logical_simplify; subst; [ tauto | ].
(* destruct cases for [clear] *)
destruct clear; logical_simplify; subst; [ tauto | ].
(* destruct cases for [block_valid] *)
destruct block_valid; logical_simplify; subst;
[ push_resize; rewrite ?resize_noop by (symmetry; length_hammer);
try reflexivity | ].
(* destruct cases for [done] *)
destruct done; logical_simplify; subst; boolsimpl;
[ intros; subst; rewrite !resize_noop by (symmetry; length_hammer);
reflexivity | ].
push_resize; push_nth.
erewrite step_sha256_compress with (t:=N.to_nat round)
by (repeat destruct_one_match;
repeat destruct_one_match_hyp; f_equal; lia).
cbn [fst snd]. push_resize.
rewrite ?resize_noop by (symmetry; length_hammer).
destr (N.to_nat round =? 63); destr (round =? 63)%N; try lia; [ ].
intros; subst. unfold SHA256Alt.sha256_step.
rewrite seq_snoc with (len:=63); rewrite fold_left_app.
reflexivity.
Qed.
Existing Instances sha256_inner_invariant_at_reset sha256_inner_invariant_preserved
sha256_inner_output_correct.
Global Instance sha256_inner_correctness : correctness_for sha256_inner.
Proof. constructor; typeclasses eauto. Defined.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t;
integer v = 19;
initial begin
if (v==1) begin end
else if (v==2) begin end
else if (v==3) begin end
else if (v==4) begin end
else if (v==5) begin end
else if (v==6) begin end
else if (v==7) begin end
else if (v==8) begin end
else if (v==9) begin end
else if (v==10) begin end
else if (v==11) begin end // Warn about this one
else if (v==12) begin end
end
initial begin
unique0 if (v==1) begin end
else if (v==2) begin end
else if (v==3) begin end
else if (v==4) begin end
else if (v==5) begin end
else if (v==6) begin end
else if (v==7) begin end
else if (v==8) begin end
else if (v==9) begin end
else if (v==10) begin end
else if (v==11) begin end // Warn about this one
else if (v==12) begin end
end
endmodule
|
module keyboard(keyboard_clk, keyboard_data, clock50, reset, read, scan_ready, scan_code);
input keyboard_clk;
input keyboard_data;
input clock50; // 50 Mhz system clock
input reset;
input read;
output scan_ready;
output [7:0] scan_code;
reg ready_set;
reg [7:0] scan_code;
reg scan_ready;
reg read_char;
reg clock; // 25 Mhz internal clock
reg [3:0] incnt;
reg [8:0] shiftin;
reg [7:0] filter;
reg keyboard_clk_filtered;
// scan_ready is set to 1 when scan_code is available.
// user should set read to 1 and then to 0 to clear scan_ready
always @ (posedge ready_set or posedge read)
if (read == 1) scan_ready <= 0;
else scan_ready <= 1;
// divide-by-two 50MHz to 25MHz
always @(posedge clock50)
clock <= ~clock;
// This process filters the raw clock signal coming from the keyboard
// using an eight-bit shift register and two AND gates
always @(posedge clock)
begin
filter <= {keyboard_clk, filter[7:1]};
if (filter==8'b1111_1111) keyboard_clk_filtered <= 1;
else if (filter==8'b0000_0000) keyboard_clk_filtered <= 0;
end
// This process reads in serial data coming from the terminal
always @(posedge keyboard_clk_filtered)
begin
if (reset==1)
begin
incnt <= 4'b0000;
read_char <= 0;
end
else if (keyboard_data==0 && read_char==0)
begin
read_char <= 1;
ready_set <= 0;
end
else
begin
// shift in next 8 data bits to assemble a scan code
if (read_char == 1)
begin
if (incnt < 9)
begin
incnt <= incnt + 1'b1;
shiftin = { keyboard_data, shiftin[8:1]};
ready_set <= 0;
end
else
begin
incnt <= 0;
scan_code <= shiftin[7:0];
read_char <= 0;
ready_set <= 1;
end
end
end
end
endmodule
|
(** * Basics: Functional Programming in Coq *)
(* This library definition is included here temporarily
for backward compatibility with Coq 8.3.
Please ignore. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(**练习题*)
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
|false => true
|true => match b2 with
|true => false
|false => true
end
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1,b2,b3 with
|true,true,true =>true
|true, _ , _ =>false
|false,_ ,_ =>false
end.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(**fengfeng*)
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
|O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
|O => S O
|S n' => mult n (factorial n')
end.
(* FILL IN HERE *)
Example test_factorial1: (factorial 3) = 6.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
(* FILL IN HERE *) Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition EOR(a b :bool):bool:=
match a,b with
| true,true => false
| true,false => true
| false,true => true
| false,false => false
end.
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (EOR (beq_nat n m ) (ble_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
(* FILL IN HERE *)Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
(* FILL IN HERE *) Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
(* FILL IN HERE *)Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more than [simpl] -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword keyword [Theorem] instead of
[Example]. Indeed, the latter difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H.
intros Q.
rewrite->H.
rewrite->Q.
reflexivity. Qed.
(* FILL IN HERE *)
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros H.
rewrite->plus_1_l.
rewrite ->H.
(* FILL IN HERE *) reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intro n. destruct n as[|n'].
reflexivity. reflexivity. Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intro f.
intro H.
intro b.
destruct b.
rewrite ->H.
rewrite ->H.
reflexivity.
rewrite ->H.
rewrite ->H.
reflexivity.
Qed.
(* FILL IN HERE *)
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intro f.
intro H.
intro b.
destruct b.
rewrite->H.
rewrite->H.
reflexivity.
rewrite->H.
rewrite->H.
reflexivity. Qed.
(* FILL IN HERE *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(orb b c=andb b c) ->
b = c.
Proof.
intro b.
intro c.
destruct b.
simpl.
intro H1.
rewrite -> H1.
reflexivity.
simpl.
intro H2.
rewrite ->H2.
reflexivity.
Admitted.
(** **** Exercise: 3 stars (binary) *)(**OKOKOKOK*)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
(* FILL IN HERE *)
Inductive bin:Type :=
|Q: bin
|T: bin->bin
|M: bin->bin.
Definition increment(n :bin):bin:=
match n with
|Q =>M Q
|M n' =>T n'
|T n' =>M (T n')
end.
Check M(T(Q)).
Fixpoint conv_bin_nat(n:bin):nat:=
match n with
|Q => O
|T n' => S(S (conv_bin_nat n'))
|M n' => S ( conv_bin_nat n')
end.
Eval compute in conv_bin_nat(M(T(T Q))).
Eval compute in conv_bin_nat(increment(M(T(T Q)))).
Definition increment_nat(n:nat):nat:=
match n with
|O =>S O
|S n' => S (S n')
end.
Eval compute in increment_nat(conv_bin_nat(M(T(T Q)))).
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(** Fixpoint f(n :nat ):nat :=
match n with
|O=> f(S O)
|S n' =>O
end.*)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
module top;
reg a, q, qb;
reg pass;
always_comb q = a !== 1'bx;
always_comb qb = a === 1'bx;
initial begin
pass = 1'b1;
#0;
// This second delay is needed for vlog95 since it uses #0 to create
// the T0 trigger. vvp also needs it since it puts the event in the
// inactive queue just like a #0 delay.
#0;
if (q !== 1'b0) begin
$display("Expected q = 1'b0 with the default 1'bx input, got %b", q);
pass = 1'b0;
end
if (qb !== 1'b1) begin
$display("Expected qb = 1'b1 with the default 1'bx input, got %b", qb);
pass = 1'b0;
end
#1;
a = 1'b0;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'b0 input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'b1;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'b1 input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'bz;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'bz input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'bx;
#0;
if (q !== 1'b0) begin
$display("Expected q = 1'b0 with an explicit 1'bx input, got %b", q);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x22.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [9:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [9:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({10'b0000000000, di[21:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[21:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({10'b0000000000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/16.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
module wb_stream_reader_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 32*WSB; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1'b1;
reg rst = 1'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_reader_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire wb_m2s_data_we;
wire wb_m2s_data_cyc;
wire wb_m2s_data_stb;
wire [2:0] wb_m2s_data_cti;
wire [1:0] wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire wb_s2m_data_ack;
wire wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire wb_m2s_cfg_we;
wire wb_m2s_cfg_cyc;
wire wb_m2s_cfg_stb;
wire [2:0] wb_m2s_cfg_cti;
wire [1:0] wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire wb_s2m_cfg_ack;
wire wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire stream_valid;
wire stream_ready;
wire irq;
wb_stream_reader
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready),
.irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_writer
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
writer
(.clk (clk),
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (wb_m2s_data_adr),
.wb_dat_i (wb_m2s_data_dat),
.wb_sel_i (wb_m2s_data_sel),
.wb_we_i (wb_m2s_data_we),
.wb_cyc_i (wb_m2s_data_cyc),
.wb_stb_i (wb_m2s_data_stb),
.wb_cti_i (wb_m2s_data_cti),
.wb_bte_i (wb_m2s_data_bte),
.wb_dat_o (wb_s2m_data_dat),
.wb_ack_o (wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err));
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1'b0));
integer transaction;
integer TRANSACTIONS;
reg VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
if($test$plusargs("verbose"))
VERBOSE = 1;
@(negedge rst);
@(posedge clk);
//FIXME: Implement wb slave config IF
writer.rate = 0.1;
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
test_main();
utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end // initial begin
reg [WB_DW-1:0] stimuli [0:MAX_BUF_SIZE/WSB-1];
task test_main;
integer start_adr;
integer buf_size;
integer burst_len;
integer idx;
integer tmp;
integer seed;
reg [WB_DW*8*WSB-1:0] data_block;
begin
//FIXME: Burst length must be > 1
burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
//FIXME: buf_size currently needs to be a multiple of burst_size
//buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
start_adr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
//Generate stimuli
for(idx=0 ; idx<buf_size/WSB ; idx=idx+1) begin
tmp = $random(seed);
stimuli[idx] = tmp[WB_DW-1:0];
end
cfg_write(REG_START_ADDR, start_adr); //Set start address
cfg_write(REG_BUF_SIZE , buf_size);//Set buffer size
cfg_write(REG_BURST_SIZE, burst_len);//Set burst length
cfg_write(REG_CSR, 1); //Start DMA
//Start transmit and receive transactors
fifo_write(buf_size/WSB);
@(posedge irq);
verify(start_adr, buf_size);
cfg_write(REG_CSR, 2); //Clear IRQ
end
endtask
task cfg_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg err;
begin
wb_cfg.write(addr_i, data_i, 4'hf, err);
if(err) begin
$display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_write;
input integer len;
integer idx;
begin
for(idx=0;idx < len ; idx=idx+1) begin
writer.write_word(stimuli[idx]);
end
end
endtask
task verify;
input integer start_adr;
input integer buf_size;
integer idx;
reg [WB_DW-1:0] expected;
reg [WB_DW-1:0] received;
reg err;
begin
for(idx = 0; idx < buf_size/WSB ; idx = idx + 1) begin
expected = stimuli[idx];
received = wb_ram0.mem[start_adr/WSB+idx];
if(received !== expected) begin
$display("%m : Verify failed at address 0x%8x. Expected 0x%8x : Got 0x%8x",
start_adr+idx*WSB,
expected,
received);
$finish;
end
end
end
endtask
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N8_M4_P2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N8_M4_P2(
input [7:0] in1,
input [7:0] in2,
output [8:0] res
);
wire [2:0] temp1, temp2, temp3, temp4;
//C2
wire g0,g1,p0,p1;
wire p1g0;
wire c2;
and and_0(g0,in1[0],in2[0]);
and and_1(g1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
xor xor_1(p1,in1[1],in2[1]);
and and_2(p1g0,p1,g0);
or or_1 (c2,g1,p1g0);
//C4
wire g2,g3,p2,p3;
wire p3g2;
wire c4;
and and_3(g2,in1[2],in2[2]);
and and_4(g3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_3(p3,in1[3],in2[3]);
and and_5(p3g2,p3,g2);
or or_2 (c4,g3,p3g2);
//C6
wire g4,g5,p4,p5;
wire p5g4;
wire c6;
and and_8(g4,in1[4],in2[4]);
and and_9(g5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
xor xor_5(p5,in1[5],in2[5]);
and and_10(p5g4,p5,g4);
or or_4 (c6,g5,p5g4);
// Results
assign temp1[2:0] = in1[1:0] + in2[1:0];
assign temp2[2:0] = in1[3:2] + in2[3:2] + c2;
assign temp3[2:0] = in1[5:4] + in2[5:4] + c4;
assign temp4[2:0] = in1[7:6] + in2[7:6] + c6;
assign res[8:0] = {temp4[2:0],temp3[1:0],temp2[1:0],temp1[1:0]};
endmodule
|
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_regs_dual_port_ram
// Project: NF2.1
// Description: Small RAM for oq_regs
//
// Stats:
// - sync read
// - sync write
// - read-before-write
//
//
///////////////////////////////////////////////////////////////////////////////
module oq_regs_dual_port_ram
#(
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter NUM_OUTPUT_QUEUES = 8,
parameter REG_FILE_ADDR_WIDTH = log2(NUM_OUTPUT_QUEUES)
)
(
input [REG_FILE_ADDR_WIDTH-1:0] addr_a,
input we_a,
input [REG_WIDTH-1:0] din_a,
output reg [REG_WIDTH-1:0] dout_a,
input clk_a,
input [REG_FILE_ADDR_WIDTH-1:0] addr_b,
input we_b,
input [REG_WIDTH-1:0] din_b,
output reg [REG_WIDTH-1:0] dout_b,
input clk_b
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Uncomment the following synthesis attribute to force the memory into
// Block RAM.
//
// Note: The attribute must appear immediately above the RAM register
// declaraion.
//
(* ram_style = "block" *)
reg [REG_WIDTH-1:0] ram[0:NUM_OUTPUT_QUEUES-1];
always @(posedge clk_a) begin
if (we_a)
ram[addr_a] <= din_a;
dout_a <= ram[addr_a];
end
always @(posedge clk_b) begin
if (we_b)
ram[addr_b] <= din_b;
dout_b <= ram[addr_b];
end
endmodule // oq_dual_port_num
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-28 09:12:49
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module csubRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
// input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
generate
//assign i = Stop_I;
if (SW <= 8) begin : GENSTOP
cmult #(.SW(SW))
inst_cmult (
// .clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [0:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign flash_addr_wire =
(valid_csr_erase && valid_csr_sector_erase_addr) ? { flash_sector_addr, 1'b0, {(19){1'b1}} } : flash_page_addr;
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
assign flash_addr_wire = flash_page_addr;
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1) || (avmm_read == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && read_state == READ_STATE_READY);
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
assign avmm_readdata = (csr_status_r_pass) ? flash_drdout : 32'hffffffff;
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
read_wait <= 1;
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_SETUP;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_READ;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 4) begin
read_wait <= 0;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_READING;
avmm_readdatavalid_reg <= 1;
end
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_PP_BLACKBOX_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "32" *)
(* C_ADDRB_WIDTH = "32" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 10.7492 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *)
(* C_READ_DEPTH_B = "2048" *)
(* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "4" *)
(* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "2048" *)
(* C_WRITE_DEPTH_B = "2048" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *)
(* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(rsta),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(rstb),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:0]),
.dinb(dinb[15:0]),
.douta(douta[15:0]),
.doutb(doutb[15:0]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1:0]),
.web(web[1:0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[31:16]),
.dinb(dinb[31:16]),
.douta(douta[31:16]),
.doutb(doutb[31:16]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3:2]),
.web(web[3:2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 ;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[15:0][0:2047]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:16],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:16],doutb}),
.DOPADOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 ;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[31:16][0:2047]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:16],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:16],doutb}),
.DOPADOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* C_ADDRA_WIDTH = "32" *) (* C_ADDRB_WIDTH = "32" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 10.7492 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *) (* C_USE_BYTE_WEA = "1" *) (* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "2048" *) (* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [31:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [31:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[31] = \<const0> ;
assign rdaddrecc[30] = \<const0> ;
assign rdaddrecc[29] = \<const0> ;
assign rdaddrecc[28] = \<const0> ;
assign rdaddrecc[27] = \<const0> ;
assign rdaddrecc[26] = \<const0> ;
assign rdaddrecc[25] = \<const0> ;
assign rdaddrecc[24] = \<const0> ;
assign rdaddrecc[23] = \<const0> ;
assign rdaddrecc[22] = \<const0> ;
assign rdaddrecc[21] = \<const0> ;
assign rdaddrecc[20] = \<const0> ;
assign rdaddrecc[19] = \<const0> ;
assign rdaddrecc[18] = \<const0> ;
assign rdaddrecc[17] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[31] = \<const0> ;
assign s_axi_rdaddrecc[30] = \<const0> ;
assign s_axi_rdaddrecc[29] = \<const0> ;
assign s_axi_rdaddrecc[28] = \<const0> ;
assign s_axi_rdaddrecc[27] = \<const0> ;
assign s_axi_rdaddrecc[26] = \<const0> ;
assign s_axi_rdaddrecc[25] = \<const0> ;
assign s_axi_rdaddrecc[24] = \<const0> ;
assign s_axi_rdaddrecc[23] = \<const0> ;
assign s_axi_rdaddrecc[22] = \<const0> ;
assign s_axi_rdaddrecc[21] = \<const0> ;
assign s_axi_rdaddrecc[20] = \<const0> ;
assign s_axi_rdaddrecc[19] = \<const0> ;
assign s_axi_rdaddrecc[18] = \<const0> ;
assign s_axi_rdaddrecc[17] = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.addra(addra[12:2]),
.addrb(addrb[12:2]),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module soc_system_vga_rgb_resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 31;
parameter ODW = 29;
parameter IEW = 1;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = {stream_in_data[31:24], stream_in_data[31:30]};
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
assign dbg_phy_wrcal[0] = pat_data_match_r;
assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[22] = early1_data;
assign dbg_phy_wrcal[23] = early2_data;
assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r;
assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r;
assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r;
assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r;
assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r;
assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r;
assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r;
assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r;
assign dbg_phy_wrcal[88] = early1_data_match_r;
assign dbg_phy_wrcal[89] = early2_data_match_r;
assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r;
assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r;
assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
//verilint STARC-2.2.3.3 off
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
//verilint STARC-2.2.3.3 on
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_mm_interconnect_0 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire acl_iface_global_reset_reset_bridge_in_reset_reset, // acl_iface_global_reset_reset_bridge_in_reset.reset
input wire acl_iface_kernel_mem0_translator_reset_reset_bridge_in_reset_reset, // acl_iface_kernel_mem0_translator_reset_reset_bridge_in_reset.reset
input wire vector_add_system_clock_reset_reset_reset_bridge_in_reset_reset, // vector_add_system_clock_reset_reset_reset_bridge_in_reset.reset
input wire [29:0] vector_add_system_avm_memgmem0_port_0_0_rw_address, // vector_add_system_avm_memgmem0_port_0_0_rw.address
output wire vector_add_system_avm_memgmem0_port_0_0_rw_waitrequest, // .waitrequest
input wire [4:0] vector_add_system_avm_memgmem0_port_0_0_rw_burstcount, // .burstcount
input wire [31:0] vector_add_system_avm_memgmem0_port_0_0_rw_byteenable, // .byteenable
input wire vector_add_system_avm_memgmem0_port_0_0_rw_read, // .read
output wire [255:0] vector_add_system_avm_memgmem0_port_0_0_rw_readdata, // .readdata
output wire vector_add_system_avm_memgmem0_port_0_0_rw_readdatavalid, // .readdatavalid
input wire vector_add_system_avm_memgmem0_port_0_0_rw_write, // .write
input wire [255:0] vector_add_system_avm_memgmem0_port_0_0_rw_writedata, // .writedata
output wire [29:0] acl_iface_kernel_mem0_address, // acl_iface_kernel_mem0.address
output wire acl_iface_kernel_mem0_write, // .write
output wire acl_iface_kernel_mem0_read, // .read
input wire [255:0] acl_iface_kernel_mem0_readdata, // .readdata
output wire [255:0] acl_iface_kernel_mem0_writedata, // .writedata
output wire [4:0] acl_iface_kernel_mem0_burstcount, // .burstcount
output wire [31:0] acl_iface_kernel_mem0_byteenable, // .byteenable
input wire acl_iface_kernel_mem0_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_mem0_waitrequest, // .waitrequest
output wire acl_iface_kernel_mem0_debugaccess // .debugaccess
);
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest; // acl_iface_kernel_mem0_translator:uav_waitrequest -> vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_waitrequest
wire [255:0] vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata; // acl_iface_kernel_mem0_translator:uav_readdata -> vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_readdata
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_debugaccess -> acl_iface_kernel_mem0_translator:uav_debugaccess
wire [29:0] vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_address -> acl_iface_kernel_mem0_translator:uav_address
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_read -> acl_iface_kernel_mem0_translator:uav_read
wire [31:0] vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_byteenable -> acl_iface_kernel_mem0_translator:uav_byteenable
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid; // acl_iface_kernel_mem0_translator:uav_readdatavalid -> vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_readdatavalid
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_lock -> acl_iface_kernel_mem0_translator:uav_lock
wire vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_write -> acl_iface_kernel_mem0_translator:uav_write
wire [255:0] vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_writedata -> acl_iface_kernel_mem0_translator:uav_writedata
wire [9:0] vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount; // vector_add_system_avm_memgmem0_port_0_0_rw_translator:uav_burstcount -> acl_iface_kernel_mem0_translator:uav_burstcount
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) vector_add_system_avm_memgmem0_port_0_0_rw_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (vector_add_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (vector_add_system_avm_memgmem0_port_0_0_rw_address), // avalon_anti_master_0.address
.av_waitrequest (vector_add_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.av_burstcount (vector_add_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.av_byteenable (vector_add_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.av_read (vector_add_system_avm_memgmem0_port_0_0_rw_read), // .read
.av_readdata (vector_add_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.av_readdatavalid (vector_add_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.av_write (vector_add_system_avm_memgmem0_port_0_0_rw_write), // .write
.av_writedata (vector_add_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_iface_kernel_mem0_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (acl_iface_kernel_mem0_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (vector_add_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_mem0_address), // avalon_anti_slave_0.address
.av_write (acl_iface_kernel_mem0_write), // .write
.av_read (acl_iface_kernel_mem0_read), // .read
.av_readdata (acl_iface_kernel_mem0_readdata), // .readdata
.av_writedata (acl_iface_kernel_mem0_writedata), // .writedata
.av_burstcount (acl_iface_kernel_mem0_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_mem0_byteenable), // .byteenable
.av_readdatavalid (acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.av_waitrequest (acl_iface_kernel_mem0_waitrequest), // .waitrequest
.av_debugaccess (acl_iface_kernel_mem0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module output_queues
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter OP_LUT_STAGE_NUM = 4,
parameter NUM_OUTPUT_QUEUES = 8,
parameter STAGE_NUM = 6,
parameter SRAM_ADDR_WIDTH = 13
)
(// --- data path interface
out_data_0,
out_ctrl_0,
out_rdy_0,
out_wr_0,
out_data_1,
out_ctrl_1,
out_rdy_1,
out_wr_1,
out_data_2,
out_ctrl_2,
out_rdy_2,
out_wr_2,
out_data_3,
out_ctrl_3,
out_rdy_3,
out_wr_3,
out_data_4,
out_ctrl_4,
out_rdy_4,
out_wr_4,
out_data_5,
out_ctrl_5,
out_wr_5,
out_rdy_5,
out_data_6,
out_ctrl_6,
out_wr_6,
out_rdy_6,
out_data_7,
out_ctrl_7,
out_wr_7,
out_rdy_7,
// --- Interface to the previous module
in_data,
in_ctrl,
in_rdy,
in_wr,
// --- Register interface
reg_req_in,
reg_ack_in,
reg_rd_wr_L_in,
reg_addr_in,
reg_data_in,
reg_src_in,
reg_req_out,
reg_ack_out,
reg_rd_wr_L_out,
reg_addr_out,
reg_data_out,
reg_src_out,
// --- SRAM sm interface
wr_0_addr,
wr_0_req,
wr_0_ack,
wr_0_data,
rd_0_ack,
rd_0_data,
rd_0_vld,
rd_0_addr,
rd_0_req,
// --- Misc
clk,
reset
);
output [DATA_WIDTH-1:0] out_data_0;
output [CTRL_WIDTH-1:0] out_ctrl_0;
input out_rdy_0;
output out_wr_0;
output [DATA_WIDTH-1:0] out_data_1;
output [CTRL_WIDTH-1:0] out_ctrl_1;
input out_rdy_1;
output out_wr_1;
output [DATA_WIDTH-1:0] out_data_2;
output [CTRL_WIDTH-1:0] out_ctrl_2;
input out_rdy_2;
output out_wr_2;
output [DATA_WIDTH-1:0] out_data_3;
output [CTRL_WIDTH-1:0] out_ctrl_3;
input out_rdy_3;
output out_wr_3;
output [DATA_WIDTH-1:0] out_data_4;
output [CTRL_WIDTH-1:0] out_ctrl_4;
input out_rdy_4;
output out_wr_4;
output [DATA_WIDTH-1:0] out_data_5;
output [CTRL_WIDTH-1:0] out_ctrl_5;
output out_wr_5;
input out_rdy_5;
output [DATA_WIDTH-1:0] out_data_6;
output [CTRL_WIDTH-1:0] out_ctrl_6;
output out_wr_6;
input out_rdy_6;
output [DATA_WIDTH-1:0] out_data_7;
output [CTRL_WIDTH-1:0] out_ctrl_7;
output out_wr_7;
input out_rdy_7;
// --- Interface to the previous module
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
output in_rdy;
input in_wr;
// --- Register interface
input reg_req_in;
input reg_ack_in;
input reg_rd_wr_L_in;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in;
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in;
output reg_req_out;
output reg_ack_out;
output reg_rd_wr_L_out;
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out;
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out;
// --- SRAM sm interface
output [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output wr_0_req;
input wr_0_ack;
output [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
input rd_0_ack;
input [DATA_WIDTH+CTRL_WIDTH-1:0] rd_0_data;
input rd_0_vld;
output [SRAM_ADDR_WIDTH-1:0] rd_0_addr;
output rd_0_req;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------- Internal Parameters ---------------
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES);
parameter PKT_LEN_WIDTH = 11;
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH);
parameter MAX_PKT = 2048; // allow for 2K bytes
parameter PKT_BYTE_CNT_WIDTH = log2(MAX_PKT);
parameter PKT_WORD_CNT_WIDTH = log2(MAX_PKT/CTRL_WIDTH);
//--------------- Regs/Wires ----------------------
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
wire [NUM_OUTPUT_QUEUES-1:0]src_oq_empty;
wire [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
wire pkt_removed;
wire [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
wire [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] src_oq;
wire [NUM_OQ_WIDTH-1:0] removed_oq;
wire rd_src_addr;
wire [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
wire dst_oq_avail;
wire [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
wire [PKT_BYTE_CNT_WIDTH-1:0] parsed_pkt_byte_len;
wire [PKT_WORD_CNT_WIDTH-1:0] parsed_pkt_word_len;
wire rd_dst_oq;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
wire pkt_stored;
wire pkt_dropped;
wire [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
wire [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
wire [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
wire [NUM_OQ_WIDTH-1:0] dst_oq;
wire rd_dst_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
wire [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
wire [NUM_OUTPUT_QUEUES-1:0]dst_oq_full;
wire input_fifo_rd_en;
wire input_fifo_empty;
wire [DATA_WIDTH-1:0] input_fifo_data_out;
wire [CTRL_WIDTH-1:0] input_fifo_ctrl_out;
wire input_fifo_nearly_full;
//---------------- Modules ------------------------
oq_header_parser
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES))
oq_header_parser
(
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.header_parser_rdy (header_parser_rdy),
.dst_oq_avail (dst_oq_avail),
.rd_dst_oq (rd_dst_oq),
.in_wr (in_wr),
.in_ctrl (in_ctrl),
.in_data (in_data),
.clk (clk),
.reset (reset));
fallthrough_small_fifo
#(.WIDTH(DATA_WIDTH+CTRL_WIDTH),
.MAX_DEPTH_BITS(3))
input_fifo
(.dout({input_fifo_ctrl_out, input_fifo_data_out}),
.full(),
.prog_full (),
.nearly_full(input_fifo_nearly_full),
.empty(input_fifo_empty),
.din({in_ctrl, in_data}),
.wr_en(in_wr),
.rd_en(input_fifo_rd_en),
.reset(reset),
.clk(clk));
store_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
store_pkt
( // --- Interface to header_parser
.dst_oq_avail (dst_oq_avail),
.parsed_dst_oq (parsed_dst_oq),
.parsed_pkt_byte_len (parsed_pkt_byte_len),
.parsed_pkt_word_len (parsed_pkt_word_len),
.rd_dst_oq (rd_dst_oq),
// --- Interface to registers
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.pkt_dropped (pkt_dropped),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Interface to SRAM
.wr_0_addr (wr_0_addr),
.wr_0_req (wr_0_req),
.wr_0_ack (wr_0_ack),
.wr_0_data (wr_0_data),
// --- Interface to input fifo
.input_fifo_rd_en (input_fifo_rd_en),
.input_fifo_empty (input_fifo_empty),
.input_fifo_data_out (input_fifo_data_out),
.input_fifo_ctrl_out (input_fifo_ctrl_out),
// --- misc
.clk (clk),
.reset (reset));
remove_pkt
#(.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.OQ_STAGE_NUM (STAGE_NUM),
.OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
remove_pkt
(// --- Interface to SRAM
.rd_0_ack (rd_0_ack),
.rd_0_data (rd_0_data),
.rd_0_vld (rd_0_vld),
.rd_0_addr (rd_0_addr),
.rd_0_req (rd_0_req),
// --- Interface to regs
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- Interface to datapath
.out_data_0 (out_data_0),
.out_ctrl_0 (out_ctrl_0),
.out_wr_0 (out_wr_0),
.out_rdy_0 (out_rdy_0),
.out_data_1 (out_data_1),
.out_ctrl_1 (out_ctrl_1),
.out_wr_1 (out_wr_1),
.out_rdy_1 (out_rdy_1),
.out_data_2 (out_data_2),
.out_ctrl_2 (out_ctrl_2),
.out_wr_2 (out_wr_2),
.out_rdy_2 (out_rdy_2),
.out_data_3 (out_data_3),
.out_ctrl_3 (out_ctrl_3),
.out_wr_3 (out_wr_3),
.out_rdy_3 (out_rdy_3),
.out_data_4 (out_data_4),
.out_ctrl_4 (out_ctrl_4),
.out_wr_4 (out_wr_4),
.out_rdy_4 (out_rdy_4),
.out_data_5 (out_data_5),
.out_ctrl_5 (out_ctrl_5),
.out_wr_5 (out_wr_5),
.out_rdy_5 (out_rdy_5),
.out_data_6 (out_data_6),
.out_ctrl_6 (out_ctrl_6),
.out_wr_6 (out_wr_6),
.out_rdy_6 (out_rdy_6),
.out_data_7 (out_data_7),
.out_ctrl_7 (out_ctrl_7),
.out_wr_7 (out_wr_7),
.out_rdy_7 (out_rdy_7),
// --- Misc
.clk (clk),
.reset (reset));
oq_regs
#(
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH(PKT_LEN_WIDTH))
oq_regs
(// --- interface to udp_reg_grp
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to remove_pkt
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_empty (src_oq_empty),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
.enable_send_pkt (enable_send_pkt),
// --- interface to store_pkt
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.pkt_dropped (pkt_dropped),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
.dst_oq_full (dst_oq_full),
// --- Misc
.clk (clk),
.reset (reset));
//------------------ Logic ------------------------
assign in_rdy = header_parser_rdy && !input_fifo_nearly_full;
endmodule // output_queues
|
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opA, opB,
op,
result,
result_slt );
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt=op[2];
assign signext=op[1];
assign addsub=op[0];
assign result=sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt=sum[WIDTH];
wire [WIDTH-1:0] oA;
wire [WIDTH-1:0] oB;
wire [WIDTH-1:0] o_B;
assign oA = {signext&opA[WIDTH-1],opA};
assign oB = {signext&opB[WIDTH-1],opB};
//assign o_B = ~{signext&opB[WIDTH-1],opB} + 1'b1;
/*
add_ahead32 aa0(
.sum (o_B),
.cout (),
.a (0),
.b (~{signext&opB[WIDTH-1],opB}),
.cin (1'b1)
);
add_ahead32 aa1(
.sum (sum),
.cout (),
.a (oA),
.b (oB),
.cin (0)
);
blocked_CLA_32bit bcla0(
.sum (o_B),
.carryout (),
.A_in (0),
.B_in (~{signext&opB[WIDTH-1],opB}),
.carryin (1'b1)
);
blocked_CLA_32bit bcla1(
.sum (sum),
.carryout (),
.A_in (oA),
.B_in (oB),
.carryin (0)
);*/
assign sum = (addsub == 1'b1) ? oA + oB : oA - oB;
/*
always @(*) begin
if(addsub == 1'b1) begin
sum = oA + oB;
end else begin
sum = oA + o_B;
end
end
*/
/*
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
defparam
adder_inst.lpm_width=WIDTH+1,
adder_inst.lpm_representation="SIGNED";
*/
assign carry_out=sum[WIDTH];
endmodule
module add_ahead32(sum,cout,a,b,cin);
output[31:0] sum;
output cout;
input[31:0] a,b;
input cin;
wire[31:0] G,P;
wire[31:0] C,sum;
assign G[0]=a[0]&b[0];
assign P[0]=a[0]|b[0];
assign C[0]=cin;
assign sum[0]=G[0]^P[0]^C[0];
assign G[1]=a[1]&b[1];
assign P[1]=a[1]|b[1];
assign C[1]=G[0]|(P[0]&cin);
assign sum[1]=G[1]^P[1]^C[1];
genvar i;
generate
for(i = 2; i < 32; i = i + 1) begin:aaa
assign G[i]=a[i]&b[i];
assign P[i]=a[i]|b[i];
assign C[i]=G[i-1]|(P[i-1]&C[i-1]);
assign sum[i]=G[i]^P[i]^C[i];
end
endgenerate
assign cout=G[31]|(P[31]&C[31]);
endmodule
module carry_lookahead_4bit(s, cout, i1, i2, c0);
output s;
output cout;
input i1;
input i2;
input c0;
wire [3:0] s;
wire cout;
wire [3:0] i1;
wire [3:0] i2;
wire c0;
wire [3:0] g;
wire [3:0] p;
wire [3:1] c;
assign g[3:0]=i1[3:0] & i2[3:0]; //carry generation
assign p[3:0]=i1[3:0] ^ i2[3:0];
assign c[1]=g[0] | (p[0] & c0);
assign c[2]=g[1] | (g[0] & p[1]) | (p[0] & p[1] & c0);
assign c[3]=g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (p[0] & p[1] & p[2] & c0);
assign cout=g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3]) | (g[0] & p[1] & p[2] & p[3]) | (p[0] & p[1] & p[2] & p[3] & c0);
assign s[0]=p[0]^c0;
assign s[3:1]=p[3:1]^c[3:1];
endmodule
module blocked_CLA_32bit(sum, carryout, A_in, B_in, carryin);
output sum;
output carryout;
input A_in;
input B_in;
input carryin;
wire [31:0] sum;
wire carryout;
wire [31:0] A_in;
wire [31:0] B_in;
wire carryin;
wire [6:0] carry;
carry_lookahead_4bit c1 (.s(sum[3:0]), .cout(carry[0]), .i1(A_in[3:0]), .i2(B_in[3:0]), .c0(carryin));
carry_lookahead_4bit c2 (.s(sum[7:4]), .cout(carry[1]), .i1(A_in[7:4]), .i2(B_in[7:4]), .c0(carry[0]));
carry_lookahead_4bit c3 (.s(sum[11:8]), .cout(carry[2]), .i1(A_in[11:8]), .i2(B_in[11:8]), .c0(carry[1]));
carry_lookahead_4bit c4 (.s(sum[15:12]), .cout(carry[3]), .i1(A_in[15:12]), .i2(B_in[15:12]), .c0(carry[2]));
carry_lookahead_4bit c5 (.s(sum[19:16]), .cout(carry[4]), .i1(A_in[19:16]), .i2(B_in[19:16]), .c0(carry[3]));
carry_lookahead_4bit c6 (.s(sum[23:20]), .cout(carry[5]), .i1(A_in[23:20]), .i2(B_in[23:20]), .c0(carry[4]));
carry_lookahead_4bit c7 (.s(sum[27:24]), .cout(carry[6]), .i1(A_in[27:24]), .i2(B_in[27:24]), .c0(carry[5]));
carry_lookahead_4bit c8 (.s(sum[31:28]), .cout(carryout), .i1(A_in[31:28]), .i2(B_in[31:28]), .c0(carry[6]));
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_FAST_t_opr (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_read,
p_src_cols_V_read,
p_src_data_stream_V_dout,
p_src_data_stream_V_empty_n,
p_src_data_stream_V_read,
p_mask_data_stream_V_din,
p_mask_data_stream_V_full_n,
p_mask_data_stream_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st39_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv11_4 = 11'b100;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv11_5 = 11'b101;
parameter ap_const_lv11_6 = 11'b110;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv9_14 = 9'b10100;
parameter ap_const_lv9_1EC = 9'b111101100;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_9 = 4'b1001;
parameter ap_const_lv4_6 = 4'b110;
parameter ap_const_lv4_7 = 4'b111;
parameter ap_const_lv4_4 = 4'b100;
parameter ap_const_lv4_5 = 4'b101;
parameter ap_const_lv4_2 = 4'b10;
parameter ap_const_lv4_3 = 4'b11;
parameter ap_const_lv4_1 = 4'b1;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv5_8 = 5'b1000;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv8_14 = 8'b10100;
parameter ap_const_lv32_FFFFFFEC = 32'b11111111111111111111111111101100;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] p_src_rows_V_read;
input [11:0] p_src_cols_V_read;
input [7:0] p_src_data_stream_V_dout;
input p_src_data_stream_V_empty_n;
output p_src_data_stream_V_read;
output [7:0] p_mask_data_stream_V_din;
input p_mask_data_stream_V_full_n;
output p_mask_data_stream_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_data_stream_V_read;
reg p_mask_data_stream_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_23;
reg [10:0] p_2_reg_515;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it1;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_48;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg [0:0] exitcond_reg_5147;
reg [0:0] or_cond_reg_5156;
reg ap_sig_bdd_61;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg ap_reg_ppiten_pp0_it13 = 1'b0;
reg ap_reg_ppiten_pp0_it14 = 1'b0;
reg ap_reg_ppiten_pp0_it15 = 1'b0;
reg ap_reg_ppiten_pp0_it16 = 1'b0;
reg ap_reg_ppiten_pp0_it17 = 1'b0;
reg ap_reg_ppiten_pp0_it18 = 1'b0;
reg ap_reg_ppiten_pp0_it19 = 1'b0;
reg ap_reg_ppiten_pp0_it20 = 1'b0;
reg ap_reg_ppiten_pp0_it21 = 1'b0;
reg ap_reg_ppiten_pp0_it22 = 1'b0;
reg ap_reg_ppiten_pp0_it23 = 1'b0;
reg ap_reg_ppiten_pp0_it24 = 1'b0;
reg ap_reg_ppiten_pp0_it25 = 1'b0;
reg ap_reg_ppiten_pp0_it26 = 1'b0;
reg ap_reg_ppiten_pp0_it27 = 1'b0;
reg ap_reg_ppiten_pp0_it28 = 1'b0;
reg ap_reg_ppiten_pp0_it29 = 1'b0;
reg ap_reg_ppiten_pp0_it30 = 1'b0;
reg ap_reg_ppiten_pp0_it31 = 1'b0;
reg ap_reg_ppiten_pp0_it32 = 1'b0;
reg ap_reg_ppiten_pp0_it33 = 1'b0;
reg ap_reg_ppiten_pp0_it34 = 1'b0;
reg [0:0] or_cond4_reg_5201;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it34;
reg ap_sig_bdd_136;
reg ap_reg_ppiten_pp0_it35 = 1'b0;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it2;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it3;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it4;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it5;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it6;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it7;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it8;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it9;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it10;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it11;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it12;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it13;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it14;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it15;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it16;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it17;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it18;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it19;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it20;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it21;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it22;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it23;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it24;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it25;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it26;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it27;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it28;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it29;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it30;
reg [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it31;
wire [10:0] tmp_fu_782_p1;
reg [10:0] tmp_reg_5098;
reg ap_sig_bdd_180;
wire [10:0] tmp_15_fu_786_p1;
reg [10:0] tmp_15_reg_5103;
wire [10:0] tmp_s_fu_790_p2;
reg [10:0] tmp_s_reg_5108;
wire [10:0] tmp_5_fu_796_p2;
reg [10:0] tmp_5_reg_5113;
wire [0:0] exitcond1_fu_802_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_196;
wire [10:0] i_V_fu_807_p2;
reg [10:0] i_V_reg_5122;
wire [0:0] tmp_7_fu_813_p2;
reg [0:0] tmp_7_reg_5127;
wire [0:0] tmp_8_fu_818_p2;
reg [0:0] tmp_8_reg_5132;
wire [0:0] tmp_9_fu_824_p2;
reg [0:0] tmp_9_reg_5137;
wire [0:0] icmp_fu_840_p2;
reg [0:0] icmp_reg_5142;
wire [0:0] exitcond_fu_846_p2;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
reg [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it33;
wire [10:0] j_V_fu_851_p2;
reg [10:0] j_V_reg_5151;
wire [0:0] or_cond_fu_862_p2;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
reg [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it33;
reg [10:0] k_buf_val_0_V_addr_reg_5161;
reg [10:0] k_buf_val_1_V_addr_reg_5167;
reg [10:0] k_buf_val_2_V_addr_reg_5173;
reg [10:0] k_buf_val_3_V_addr_reg_5179;
reg [10:0] k_buf_val_4_V_addr_reg_5185;
reg [10:0] k_buf_val_5_V_addr_reg_5191;
wire [0:0] or_cond1_fu_883_p2;
reg [0:0] or_cond1_reg_5197;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
reg [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it32;
wire [0:0] or_cond4_fu_904_p2;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
reg [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
reg [7:0] win_val_0_V_2_1_reg_5205;
reg [7:0] win_val_1_V_4_3_reg_5210;
reg [7:0] win_val_2_V_5_3_reg_5215;
reg [7:0] win_val_3_V_2_3_reg_5220;
reg [7:0] win_val_4_V_5_3_reg_5225;
reg [7:0] win_val_5_V_4_3_reg_5230;
reg [7:0] win_val_6_V_2_2_reg_5235;
wire [8:0] lhs_V_fu_1252_p1;
reg [8:0] lhs_V_reg_5240;
wire [8:0] r_V_fu_1260_p2;
reg [8:0] r_V_reg_5252;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it14;
wire [1:0] phitmp1_fu_1278_p3;
reg [1:0] phitmp1_reg_5261;
wire [0:0] tmp_20_fu_1286_p2;
reg [0:0] tmp_20_reg_5266;
wire [8:0] r_V_s_fu_1296_p2;
reg [8:0] r_V_s_reg_5271;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it23;
wire [1:0] phitmp_1_fu_1314_p3;
reg [1:0] phitmp_1_reg_5280;
wire [0:0] tmp_24_fu_1322_p2;
reg [0:0] tmp_24_reg_5285;
wire [8:0] r_V_2_fu_1332_p2;
reg [8:0] r_V_2_reg_5290;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it16;
wire [1:0] phitmp_2_fu_1350_p3;
reg [1:0] phitmp_2_reg_5299;
wire [0:0] tmp_27_fu_1358_p2;
reg [0:0] tmp_27_reg_5304;
wire [8:0] r_V_3_fu_1368_p2;
reg [8:0] r_V_3_reg_5309;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
reg [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it25;
wire [1:0] phitmp_3_fu_1386_p3;
reg [1:0] phitmp_3_reg_5318;
wire [0:0] tmp_29_fu_1394_p2;
reg [0:0] tmp_29_reg_5323;
wire [8:0] r_V_4_fu_1404_p2;
reg [8:0] r_V_4_reg_5328;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it18;
wire [0:0] tmp_176_4_fu_1410_p2;
reg [0:0] tmp_176_4_reg_5337;
wire [0:0] tmp_177_4_fu_1416_p2;
reg [0:0] tmp_177_4_reg_5343;
wire [8:0] r_V_5_fu_1426_p2;
reg [8:0] r_V_5_reg_5348;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
reg [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it27;
wire [0:0] tmp_176_5_fu_1432_p2;
reg [0:0] tmp_176_5_reg_5357;
wire [0:0] tmp_177_5_fu_1438_p2;
reg [0:0] tmp_177_5_reg_5363;
wire [8:0] r_V_6_fu_1448_p2;
reg [8:0] r_V_6_reg_5368;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it20;
wire [0:0] tmp_176_6_fu_1454_p2;
reg [0:0] tmp_176_6_reg_5377;
wire [0:0] tmp_177_6_fu_1460_p2;
reg [0:0] tmp_177_6_reg_5383;
wire [8:0] r_V_7_fu_1470_p2;
reg [8:0] r_V_7_reg_5388;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
reg [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it29;
wire [0:0] tmp_176_7_fu_1476_p2;
reg [0:0] tmp_176_7_reg_5397;
wire [0:0] tmp_177_7_fu_1482_p2;
reg [0:0] tmp_177_7_reg_5403;
wire [8:0] r_V_1_fu_1516_p2;
reg [8:0] r_V_1_reg_5408;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it22;
wire [1:0] flag_val_V_assign_load_1_s_fu_1521_p3;
reg [1:0] flag_val_V_assign_load_1_s_reg_5417;
reg [1:0] ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
reg [1:0] ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5;
wire [1:0] phitmp3_fu_1539_p3;
reg [1:0] phitmp3_reg_5422;
wire [0:0] tmp_23_fu_1547_p2;
reg [0:0] tmp_23_reg_5427;
wire [8:0] r_V_1_1_fu_1557_p2;
reg [8:0] r_V_1_1_reg_5432;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15;
wire [0:0] tmp_182_1_fu_1568_p2;
reg [0:0] tmp_182_1_reg_5441;
wire [0:0] tmp_184_1_fu_1574_p2;
reg [0:0] tmp_184_1_reg_5447;
wire [8:0] r_V_1_2_fu_1584_p2;
reg [8:0] r_V_1_2_reg_5452;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24;
wire [0:0] tmp_182_2_fu_1595_p2;
reg [0:0] tmp_182_2_reg_5461;
wire [0:0] tmp_184_2_fu_1601_p2;
reg [0:0] tmp_184_2_reg_5467;
wire [8:0] r_V_1_3_fu_1611_p2;
reg [8:0] r_V_1_3_reg_5472;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17;
wire [8:0] r_V_1_4_fu_1626_p2;
reg [8:0] r_V_1_4_reg_5483;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
reg [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26;
wire [8:0] r_V_1_5_fu_1654_p2;
reg [8:0] r_V_1_5_reg_5494;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19;
wire [8:0] r_V_1_6_fu_1682_p2;
reg [8:0] r_V_1_6_reg_5505;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
reg [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28;
wire [8:0] r_V_1_7_fu_1710_p2;
reg [8:0] r_V_1_7_reg_5516;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
reg [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21;
wire [1:0] flag_val_V_assign_load_1_13_fu_1726_p3;
reg [1:0] flag_val_V_assign_load_1_13_reg_5527;
wire [0:0] tmp_39_fu_1740_p2;
reg [0:0] tmp_39_reg_5532;
reg [0:0] ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_39_reg_5532_pp0_it5;
wire [0:0] or_cond5_fu_1746_p2;
reg [0:0] or_cond5_reg_5537;
reg [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it7;
wire [0:0] or_cond6_fu_1764_p2;
reg [0:0] or_cond6_reg_5543;
reg [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it7;
wire [0:0] or_cond7_fu_1782_p2;
reg [0:0] or_cond7_reg_5548;
reg [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it7;
wire [0:0] or_cond8_fu_1800_p2;
reg [0:0] or_cond8_reg_5553;
reg [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it8;
wire [0:0] or_cond9_fu_1818_p2;
reg [0:0] or_cond9_reg_5559;
reg [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it8;
wire [0:0] tmp_181_5_not_fu_1824_p2;
reg [0:0] tmp_181_5_not_reg_5566;
wire [0:0] tmp_183_5_fu_1830_p2;
reg [0:0] tmp_183_5_reg_5572;
wire [0:0] tmp_181_6_not_fu_1836_p2;
reg [0:0] tmp_181_6_not_reg_5578;
wire [0:0] tmp_183_6_fu_1842_p2;
reg [0:0] tmp_183_6_reg_5584;
wire [3:0] count_1_i_0_op_op87_op_fu_1848_p3;
reg [3:0] count_1_i_0_op_op87_op_reg_5590;
wire [3:0] phitmp43_op_op_cast_cast_cast_fu_1856_p3;
reg [3:0] phitmp43_op_op_cast_cast_cast_reg_5595;
wire [0:0] tmp_40_fu_1864_p2;
reg [0:0] tmp_40_reg_5600;
wire [0:0] not_or_cond6_demorgan_fu_1870_p2;
reg [0:0] not_or_cond6_demorgan_reg_5605;
reg [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
reg [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7;
wire [0:0] not_or_cond7_demorgan_fu_1876_p2;
reg [0:0] not_or_cond7_demorgan_reg_5610;
reg [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
reg [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8;
wire [0:0] not_or_cond8_demorgan_fu_1882_p2;
reg [0:0] not_or_cond8_demorgan_reg_5615;
reg [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
reg [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8;
wire [0:0] not_or_cond9_demorgan_fu_1888_p2;
reg [0:0] not_or_cond9_demorgan_reg_5620;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
reg [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9;
wire [1:0] flag_val_V_assign_load_1_3_fu_1930_p3;
reg [1:0] flag_val_V_assign_load_1_3_reg_5625;
wire [1:0] flag_val_V_assign_load_1_5_fu_1962_p3;
reg [1:0] flag_val_V_assign_load_1_5_reg_5631;
wire [0:0] tmp_182_4_fu_1970_p2;
reg [0:0] tmp_182_4_reg_5638;
wire [0:0] tmp_184_4_fu_1975_p2;
reg [0:0] tmp_184_4_reg_5644;
wire [0:0] tmp_182_5_fu_1980_p2;
reg [0:0] tmp_182_5_reg_5649;
wire [0:0] tmp_184_5_fu_1985_p2;
reg [0:0] tmp_184_5_reg_5655;
wire [0:0] or_cond2_fu_1990_p2;
reg [0:0] or_cond2_reg_5660;
reg [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it9;
wire [3:0] count_1_i_6_fu_2036_p3;
reg [3:0] count_1_i_6_reg_5665;
wire [0:0] or_cond10_fu_2055_p2;
reg [0:0] or_cond10_reg_5670;
wire [3:0] count_1_i_7_fu_2061_p3;
reg [3:0] count_1_i_7_reg_5675;
wire [0:0] or_cond11_fu_2075_p2;
reg [0:0] or_cond11_reg_5681;
wire [0:0] tmp_181_9_fu_2081_p2;
reg [0:0] tmp_181_9_reg_5687;
wire [0:0] tmp_183_9_fu_2087_p2;
reg [0:0] tmp_183_9_reg_5693;
wire [0:0] not_or_cond10_demorgan_fu_2093_p2;
reg [0:0] not_or_cond10_demorgan_reg_5699;
reg [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
reg [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9;
wire [0:0] not_or_cond11_demorgan_fu_2097_p2;
reg [0:0] not_or_cond11_demorgan_reg_5704;
reg [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
reg [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
reg [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9;
wire [1:0] flag_val_V_assign_load_1_10_fu_2131_p3;
reg [1:0] flag_val_V_assign_load_1_10_reg_5709;
wire [1:0] flag_val_V_assign_load_1_12_fu_2163_p3;
reg [1:0] flag_val_V_assign_load_1_12_reg_5715;
wire [0:0] tmp_182_7_fu_2171_p2;
reg [0:0] tmp_182_7_reg_5722;
wire [0:0] tmp_184_7_fu_2176_p2;
reg [0:0] tmp_184_7_reg_5728;
wire [0:0] not_or_cond_fu_2186_p2;
reg [0:0] not_or_cond_reg_5733;
reg [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
reg [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
reg [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
reg [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9;
wire [0:0] p_iscorner_0_i_9_fu_2251_p2;
reg [0:0] p_iscorner_0_i_9_reg_5738;
wire [3:0] count_1_i_9_fu_2257_p3;
reg [3:0] count_1_i_9_reg_5743;
wire [0:0] not_or_cond3_demorgan_fu_2286_p2;
reg [0:0] not_or_cond3_demorgan_reg_5748;
wire [3:0] count_1_i_s_fu_2292_p3;
reg [3:0] count_1_i_s_reg_5753;
wire [0:0] or_cond14_fu_2310_p2;
reg [0:0] or_cond14_reg_5759;
wire [0:0] not_or_cond4_demorgan_fu_2316_p2;
reg [0:0] not_or_cond4_demorgan_reg_5764;
wire [0:0] tmp_181_2_fu_2322_p2;
reg [0:0] tmp_181_2_reg_5769;
wire [0:0] tmp_183_10_fu_2328_p2;
reg [0:0] tmp_183_10_reg_5775;
wire [0:0] tmp5_fu_2334_p2;
reg [0:0] tmp5_reg_5781;
reg [0:0] ap_reg_ppstg_tmp5_reg_5781_pp0_it6;
wire [0:0] p_iscorner_0_i_1_fu_2391_p2;
reg [0:0] p_iscorner_0_i_1_reg_5786;
wire [0:0] p_iscorner_0_i_2_fu_2435_p2;
reg [0:0] p_iscorner_0_i_2_reg_5791;
wire [0:0] tmp_185_3_fu_2464_p2;
reg [0:0] tmp_185_3_reg_5796;
wire [0:0] not_or_cond13_demorgan_fu_2470_p2;
reg [0:0] not_or_cond13_demorgan_reg_5801;
wire [3:0] count_1_i_3_fu_2476_p3;
reg [3:0] count_1_i_3_reg_5806;
wire [0:0] or_cond17_fu_2494_p2;
reg [0:0] or_cond17_reg_5811;
wire [0:0] not_or_cond14_demorgan_fu_2500_p2;
reg [0:0] not_or_cond14_demorgan_reg_5816;
wire [0:0] or_cond18_fu_2511_p2;
reg [0:0] or_cond18_reg_5821;
wire [0:0] tmp6_fu_2516_p2;
reg [0:0] tmp6_reg_5827;
wire [0:0] p_iscorner_0_i_5_fu_2581_p2;
reg [0:0] p_iscorner_0_i_5_reg_5832;
wire [4:0] count_3_fu_2594_p2;
reg [4:0] count_3_reg_5837;
wire [4:0] phitmp8_fu_2600_p2;
reg [4:0] phitmp8_reg_5842;
wire [0:0] tmp4_fu_2606_p2;
reg [0:0] tmp4_reg_5847;
wire [0:0] tmp8_fu_2610_p2;
reg [0:0] tmp8_reg_5852;
wire [0:0] tmp9_fu_2614_p2;
reg [0:0] tmp9_reg_5857;
wire [0:0] p_iscorner_0_i_7_fu_2653_p2;
reg [0:0] p_iscorner_0_i_7_reg_5862;
wire [4:0] count_4_fu_2666_p2;
reg [4:0] count_4_reg_5867;
wire [4:0] count_1_i_12_fu_2678_p3;
reg [4:0] count_1_i_12_reg_5872;
wire [0:0] tmp3_fu_2689_p2;
reg [0:0] tmp3_reg_5878;
reg [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
reg [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
reg [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it11;
wire [0:0] tmp12_fu_2694_p2;
reg [0:0] tmp12_reg_5883;
reg [0:0] ap_reg_ppstg_tmp12_reg_5883_pp0_it9;
wire [0:0] p_iscorner_0_i_11_fu_2725_p2;
reg [0:0] p_iscorner_0_i_11_reg_5888;
wire [0:0] tmp_185_13_fu_2743_p2;
reg [0:0] tmp_185_13_reg_5893;
wire [4:0] count_1_i_14_fu_2755_p3;
reg [4:0] count_1_i_14_reg_5898;
wire [0:0] tmp13_fu_2762_p2;
reg [0:0] tmp13_reg_5904;
wire [0:0] p_iscorner_0_i_13_fu_2787_p2;
reg [0:0] p_iscorner_0_i_13_reg_5909;
wire [0:0] tmp_185_15_fu_2805_p2;
reg [0:0] tmp_185_15_reg_5914;
wire [0:0] not_or_cond11_fu_2817_p2;
reg [0:0] not_or_cond11_reg_5919;
wire [0:0] tmp_185_16_fu_2822_p2;
reg [0:0] tmp_185_16_reg_5924;
wire [0:0] tmp2_fu_2828_p2;
reg [0:0] tmp2_reg_5929;
wire [0:0] tmp11_fu_2833_p2;
reg [0:0] tmp11_reg_5934;
reg [0:0] ap_reg_ppstg_tmp11_reg_5934_pp0_it11;
wire [0:0] tmp15_fu_2837_p2;
reg [0:0] tmp15_reg_5939;
wire [0:0] tmp14_fu_2861_p2;
reg [0:0] tmp14_reg_5944;
wire [0:0] iscorner_2_i_s_fu_2870_p2;
reg [0:0] iscorner_2_i_s_reg_5949;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
reg [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32;
wire [31:0] grp_image_filter_reg_int_s_fu_542_ap_return;
reg [31:0] flag_d_min2_1_reg_5953;
reg [31:0] ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
reg [31:0] ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15;
wire [31:0] grp_image_filter_reg_int_s_fu_547_ap_return;
reg [31:0] flag_d_max2_1_reg_5959;
reg [31:0] ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
reg [31:0] ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15;
wire [31:0] grp_image_filter_reg_int_s_fu_572_ap_return;
reg [31:0] flag_d_min2_7_reg_5965;
reg [31:0] ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14;
wire [31:0] grp_image_filter_reg_int_s_fu_577_ap_return;
reg [31:0] flag_d_max2_7_reg_5971;
reg [31:0] ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14;
wire [31:0] tmp_200_3_fu_3031_p3;
reg [31:0] tmp_200_3_reg_5977;
reg [31:0] ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
wire [31:0] tmp_213_3_fu_3045_p3;
reg [31:0] tmp_213_3_reg_5982;
reg [31:0] ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
wire [31:0] grp_image_filter_reg_int_s_fu_582_ap_return;
reg [31:0] flag_d_min4_1_reg_5987;
reg [31:0] ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
reg [31:0] ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16;
wire [31:0] grp_image_filter_reg_int_s_fu_587_ap_return;
reg [31:0] flag_d_max4_1_reg_5993;
reg [31:0] ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
reg [31:0] ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16;
wire [31:0] grp_image_filter_reg_int_s_fu_592_ap_return;
reg [31:0] flag_d_min4_5_reg_5999;
reg [31:0] ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
reg [31:0] ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16;
wire [31:0] grp_image_filter_reg_int_s_fu_597_ap_return;
reg [31:0] flag_d_max4_5_reg_6005;
reg [31:0] ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
reg [31:0] ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16;
wire signed [31:0] flag_d_assign_fu_3143_p1;
reg signed [31:0] flag_d_assign_reg_6011;
wire [31:0] grp_image_filter_reg_int_s_fu_602_ap_return;
reg [31:0] flag_d_min2_9_reg_6017;
wire [31:0] grp_image_filter_reg_int_s_fu_607_ap_return;
reg [31:0] flag_d_max2_9_reg_6023;
wire [31:0] grp_image_filter_reg_int_s_fu_612_ap_return;
reg [31:0] flag_d_min8_1_reg_6029;
wire [31:0] grp_image_filter_reg_int_s_fu_617_ap_return;
reg [31:0] flag_d_max8_1_reg_6036;
wire [0:0] tmp_43_fu_3262_p2;
reg [0:0] tmp_43_reg_6043;
wire [0:0] tmp_67_fu_3268_p2;
reg [0:0] tmp_67_reg_6048;
wire [31:0] grp_image_filter_reg_int_s_fu_652_ap_return;
reg [31:0] flag_d_min4_3_reg_6053;
wire [31:0] grp_image_filter_reg_int_s_fu_657_ap_return;
reg [31:0] flag_d_max4_3_reg_6059;
wire [31:0] grp_image_filter_reg_int_s_fu_662_ap_return;
reg [31:0] flag_d_min4_7_reg_6065;
wire [31:0] grp_image_filter_reg_int_s_fu_667_ap_return;
reg [31:0] flag_d_max4_7_reg_6071;
wire [7:0] p_a_0_flag_d_assign_load_5_fu_3434_p3;
reg [7:0] p_a_0_flag_d_assign_load_5_reg_6077;
wire [31:0] tmp_47_fu_3447_p3;
reg [31:0] tmp_47_reg_6083;
wire [7:0] tmp_48_fu_3454_p1;
reg [7:0] tmp_48_reg_6088;
wire [8:0] b0_fu_3473_p3;
reg [8:0] b0_reg_6093;
wire [31:0] tmp_71_fu_3486_p3;
reg [31:0] tmp_71_reg_6099;
wire [8:0] tmp_81_fu_3493_p1;
reg [8:0] tmp_81_reg_6104;
wire signed [31:0] flag_d_assign_2_fu_3497_p1;
reg signed [31:0] flag_d_assign_2_reg_6109;
wire [31:0] grp_image_filter_reg_int_s_fu_712_ap_return;
reg [31:0] flag_d_min8_3_reg_6115;
wire [31:0] grp_image_filter_reg_int_s_fu_717_ap_return;
reg [31:0] flag_d_max8_3_reg_6122;
wire [31:0] tmp_210_5_fu_3505_p3;
reg [31:0] tmp_210_5_reg_6129;
wire [31:0] tmp_225_5_fu_3517_p3;
reg [31:0] tmp_225_5_reg_6134;
wire [31:0] tmp_210_7_fu_3529_p3;
reg [31:0] tmp_210_7_reg_6139;
reg [31:0] ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
wire [31:0] tmp_225_7_fu_3541_p3;
reg [31:0] tmp_225_7_reg_6144;
reg [31:0] ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
wire [31:0] tmp_210_9_fu_3554_p3;
reg [31:0] tmp_210_9_reg_6149;
reg [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
wire [31:0] tmp_225_9_fu_3568_p3;
reg [31:0] tmp_225_9_reg_6154;
reg [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
wire [31:0] tmp_210_s_fu_3582_p3;
reg [31:0] tmp_210_s_reg_6159;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
wire [31:0] tmp_225_s_fu_3596_p3;
reg [31:0] tmp_225_s_reg_6164;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
wire [31:0] tmp_210_2_fu_3609_p3;
reg [31:0] tmp_210_2_reg_6169;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
wire [31:0] tmp_225_2_fu_3621_p3;
reg [31:0] tmp_225_2_reg_6174;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
wire [31:0] tmp_210_4_fu_3633_p3;
reg [31:0] tmp_210_4_reg_6179;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
reg [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
wire [31:0] tmp_225_4_fu_3645_p3;
reg [31:0] tmp_225_4_reg_6184;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
reg [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
wire [7:0] p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
reg [7:0] p_a_0_flag_d_assign_load_5_tmp_s_reg_6189;
wire [0:0] tmp_209_1_fu_3666_p2;
reg [0:0] tmp_209_1_reg_6195;
wire [8:0] b0_tmp_s_fu_3680_p3;
reg [8:0] b0_tmp_s_reg_6200;
wire [0:0] tmp_221_1_fu_3686_p2;
reg [0:0] tmp_221_1_reg_6206;
wire [7:0] a0_s_fu_3713_p3;
reg [7:0] a0_s_reg_6211;
wire [31:0] tmp_232_1_fu_3725_p3;
reg [31:0] tmp_232_1_reg_6217;
wire [7:0] tmp_57_fu_3732_p1;
reg [7:0] tmp_57_reg_6222;
wire [8:0] b0_s_fu_3754_p3;
reg [8:0] b0_s_reg_6227;
wire [31:0] tmp_239_1_fu_3766_p3;
reg [31:0] tmp_239_1_reg_6233;
wire [8:0] tmp_83_fu_3773_p1;
reg [8:0] tmp_83_reg_6238;
wire signed [31:0] flag_d_assign_4_fu_3777_p1;
reg signed [31:0] flag_d_assign_4_reg_6243;
wire [31:0] grp_image_filter_reg_int_s_fu_722_ap_return;
reg [31:0] flag_d_min8_5_reg_6249;
wire [31:0] grp_image_filter_reg_int_s_fu_727_ap_return;
reg [31:0] flag_d_max8_5_reg_6256;
wire [7:0] a0_tmp_232_1_fu_3788_p3;
reg [7:0] a0_tmp_232_1_reg_6263;
wire [0:0] tmp_209_2_fu_3794_p2;
reg [0:0] tmp_209_2_reg_6269;
wire [8:0] b0_tmp_239_1_fu_3808_p3;
reg [8:0] b0_tmp_239_1_reg_6274;
wire [0:0] tmp_221_2_fu_3814_p2;
reg [0:0] tmp_221_2_reg_6280;
wire [7:0] a0_2_fu_3841_p3;
reg [7:0] a0_2_reg_6285;
wire [31:0] tmp_232_2_fu_3853_p3;
reg [31:0] tmp_232_2_reg_6291;
wire [7:0] tmp_59_fu_3860_p1;
reg [7:0] tmp_59_reg_6296;
wire [8:0] b0_2_fu_3882_p3;
reg [8:0] b0_2_reg_6301;
wire [31:0] tmp_239_2_fu_3894_p3;
reg [31:0] tmp_239_2_reg_6307;
wire [8:0] tmp_85_fu_3901_p1;
reg [8:0] tmp_85_reg_6312;
wire signed [31:0] flag_d_assign_6_fu_3905_p1;
reg signed [31:0] flag_d_assign_6_reg_6317;
wire [31:0] grp_image_filter_reg_int_s_fu_732_ap_return;
reg [31:0] flag_d_min8_7_reg_6323;
wire [31:0] grp_image_filter_reg_int_s_fu_737_ap_return;
reg [31:0] flag_d_max8_7_reg_6330;
wire [7:0] a0_2_tmp_232_2_fu_3916_p3;
reg [7:0] a0_2_tmp_232_2_reg_6337;
wire [0:0] tmp_209_3_fu_3922_p2;
reg [0:0] tmp_209_3_reg_6343;
wire [8:0] b0_2_tmp_239_2_fu_3936_p3;
reg [8:0] b0_2_tmp_239_2_reg_6348;
wire [0:0] tmp_221_3_fu_3942_p2;
reg [0:0] tmp_221_3_reg_6354;
wire [7:0] a0_3_fu_3969_p3;
reg [7:0] a0_3_reg_6359;
wire [31:0] tmp_232_3_fu_3981_p3;
reg [31:0] tmp_232_3_reg_6365;
wire [7:0] tmp_61_fu_3988_p1;
reg [7:0] tmp_61_reg_6370;
wire [8:0] b0_3_fu_4010_p3;
reg [8:0] b0_3_reg_6375;
wire [31:0] tmp_239_3_fu_4022_p3;
reg [31:0] tmp_239_3_reg_6381;
wire [8:0] tmp_87_fu_4029_p1;
reg [8:0] tmp_87_reg_6386;
wire signed [31:0] flag_d_assign_8_fu_4033_p1;
reg signed [31:0] flag_d_assign_8_reg_6391;
wire [31:0] grp_image_filter_reg_int_s_fu_742_ap_return;
reg [31:0] flag_d_min8_9_reg_6397;
wire [31:0] grp_image_filter_reg_int_s_fu_747_ap_return;
reg [31:0] flag_d_max8_9_reg_6404;
wire [7:0] a0_3_tmp_232_3_fu_4044_p3;
reg [7:0] a0_3_tmp_232_3_reg_6411;
wire [0:0] tmp_209_4_fu_4050_p2;
reg [0:0] tmp_209_4_reg_6417;
wire [8:0] b0_3_tmp_239_3_fu_4064_p3;
reg [8:0] b0_3_tmp_239_3_reg_6422;
wire [0:0] tmp_221_4_fu_4070_p2;
reg [0:0] tmp_221_4_reg_6428;
wire [7:0] a0_4_fu_4097_p3;
reg [7:0] a0_4_reg_6433;
wire [31:0] tmp_232_4_fu_4109_p3;
reg [31:0] tmp_232_4_reg_6439;
wire [7:0] tmp_63_fu_4116_p1;
reg [7:0] tmp_63_reg_6444;
wire [8:0] b0_4_fu_4138_p3;
reg [8:0] b0_4_reg_6449;
wire [31:0] tmp_239_4_fu_4150_p3;
reg [31:0] tmp_239_4_reg_6455;
wire [8:0] tmp_89_fu_4157_p1;
reg [8:0] tmp_89_reg_6460;
wire signed [31:0] flag_d_assign_s_fu_4161_p1;
reg signed [31:0] flag_d_assign_s_reg_6465;
wire [31:0] grp_image_filter_reg_int_s_fu_752_ap_return;
reg [31:0] tmp_211_s_reg_6471;
wire [31:0] grp_image_filter_reg_int_s_fu_757_ap_return;
reg [31:0] tmp_226_s_reg_6478;
wire [7:0] a0_4_tmp_232_4_fu_4172_p3;
reg [7:0] a0_4_tmp_232_4_reg_6485;
wire [0:0] tmp_209_5_fu_4178_p2;
reg [0:0] tmp_209_5_reg_6491;
wire [8:0] b0_4_tmp_239_4_fu_4192_p3;
reg [8:0] b0_4_tmp_239_4_reg_6496;
wire [0:0] tmp_221_5_fu_4198_p2;
reg [0:0] tmp_221_5_reg_6502;
wire [7:0] a0_5_fu_4225_p3;
reg [7:0] a0_5_reg_6507;
wire [31:0] tmp_232_5_fu_4237_p3;
reg [31:0] tmp_232_5_reg_6513;
wire [7:0] tmp_65_fu_4244_p1;
reg [7:0] tmp_65_reg_6518;
wire [8:0] b0_5_fu_4266_p3;
reg [8:0] b0_5_reg_6523;
wire [31:0] tmp_239_5_fu_4278_p3;
reg [31:0] tmp_239_5_reg_6529;
wire [8:0] tmp_91_fu_4285_p1;
reg [8:0] tmp_91_reg_6534;
wire signed [31:0] flag_d_assign_11_fu_4289_p1;
reg signed [31:0] flag_d_assign_11_reg_6539;
wire [31:0] grp_image_filter_reg_int_s_fu_762_ap_return;
reg [31:0] tmp_211_1_reg_6545;
wire [31:0] grp_image_filter_reg_int_s_fu_767_ap_return;
reg [31:0] tmp_226_1_reg_6552;
wire [7:0] a0_5_tmp_232_5_fu_4300_p3;
reg [7:0] a0_5_tmp_232_5_reg_6559;
wire [0:0] tmp_209_6_fu_4306_p2;
reg [0:0] tmp_209_6_reg_6565;
wire [8:0] b0_5_tmp_239_5_fu_4320_p3;
reg [8:0] b0_5_tmp_239_5_reg_6570;
wire [0:0] tmp_221_6_fu_4326_p2;
reg [0:0] tmp_221_6_reg_6576;
wire [7:0] a0_6_fu_4353_p3;
reg [7:0] a0_6_reg_6581;
wire [31:0] tmp_232_6_fu_4365_p3;
reg [31:0] tmp_232_6_reg_6587;
wire [7:0] tmp_75_fu_4372_p1;
reg [7:0] tmp_75_reg_6592;
wire [8:0] b0_6_fu_4394_p3;
reg [8:0] b0_6_reg_6597;
wire [31:0] tmp_239_6_fu_4406_p3;
reg [31:0] tmp_239_6_reg_6603;
wire [8:0] tmp_93_fu_4413_p1;
reg [8:0] tmp_93_reg_6608;
wire signed [31:0] flag_d_assign_13_fu_4417_p1;
reg signed [31:0] flag_d_assign_13_reg_6613;
wire [31:0] grp_image_filter_reg_int_s_fu_772_ap_return;
reg [31:0] tmp_211_2_reg_6619;
wire [31:0] grp_image_filter_reg_int_s_fu_777_ap_return;
reg [31:0] tmp_226_2_reg_6626;
wire [7:0] a0_6_tmp_232_6_fu_4428_p3;
reg [7:0] a0_6_tmp_232_6_reg_6633;
wire [0:0] tmp_209_7_fu_4434_p2;
reg [0:0] tmp_209_7_reg_6639;
wire [8:0] b0_6_tmp_239_6_fu_4448_p3;
reg [8:0] b0_6_tmp_239_6_reg_6644;
wire [0:0] tmp_221_7_fu_4454_p2;
reg [0:0] tmp_221_7_reg_6650;
wire [7:0] a0_7_fu_4481_p3;
reg [7:0] a0_7_reg_6655;
wire [31:0] tmp_232_7_fu_4493_p3;
reg [31:0] tmp_232_7_reg_6661;
wire [7:0] tmp_78_fu_4500_p1;
reg [7:0] tmp_78_reg_6666;
wire [8:0] b0_7_fu_4522_p3;
reg [8:0] b0_7_reg_6671;
wire [31:0] tmp_239_7_fu_4534_p3;
reg [31:0] tmp_239_7_reg_6676;
wire [7:0] tmp_95_fu_4541_p1;
reg [7:0] tmp_95_reg_6681;
wire [7:0] tmp_96_fu_4545_p1;
reg [7:0] tmp_96_reg_6686;
wire [7:0] a0_7_tmp_232_7_fu_4557_p3;
reg [7:0] a0_7_tmp_232_7_reg_6691;
wire [7:0] tmp_79_fu_4571_p3;
reg [7:0] tmp_79_reg_6697;
reg [10:0] core_buf_val_0_V_addr_reg_6702;
reg [10:0] core_buf_val_1_V_addr_reg_6708;
reg [10:0] ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
wire [7:0] tmp_100_v_fu_4593_p3;
reg [7:0] tmp_100_v_reg_6714;
wire [0:0] tmp_53_fu_4600_p2;
reg [0:0] tmp_53_reg_6719;
reg [0:0] ap_reg_ppstg_tmp_53_reg_6719_pp0_it33;
wire [7:0] core_buf_val_0_V_q0;
reg [7:0] core_buf_val_0_V_load_reg_6724;
wire [7:0] core_buf_val_1_V_q0;
reg [7:0] core_buf_val_1_V_load_reg_6729;
wire [7:0] phitmp2_fu_4606_p2;
wire [0:0] tmp19_fu_4701_p2;
reg [0:0] tmp19_reg_6739;
wire [0:0] tmp20_fu_4712_p2;
reg [0:0] tmp20_reg_6744;
wire [0:0] tmp23_fu_4723_p2;
reg [0:0] tmp23_reg_6749;
wire [0:0] tmp25_fu_4735_p2;
reg [0:0] tmp25_reg_6754;
wire [10:0] k_buf_val_0_V_address0;
reg k_buf_val_0_V_ce0;
wire [7:0] k_buf_val_0_V_q0;
wire [10:0] k_buf_val_0_V_address1;
reg k_buf_val_0_V_ce1;
reg k_buf_val_0_V_we1;
wire [7:0] k_buf_val_0_V_d1;
wire [10:0] k_buf_val_1_V_address0;
reg k_buf_val_1_V_ce0;
wire [7:0] k_buf_val_1_V_q0;
wire [10:0] k_buf_val_1_V_address1;
reg k_buf_val_1_V_ce1;
reg k_buf_val_1_V_we1;
wire [7:0] k_buf_val_1_V_d1;
wire [10:0] k_buf_val_2_V_address0;
reg k_buf_val_2_V_ce0;
wire [7:0] k_buf_val_2_V_q0;
wire [10:0] k_buf_val_2_V_address1;
reg k_buf_val_2_V_ce1;
reg k_buf_val_2_V_we1;
wire [7:0] k_buf_val_2_V_d1;
wire [10:0] k_buf_val_3_V_address0;
reg k_buf_val_3_V_ce0;
wire [7:0] k_buf_val_3_V_q0;
wire [10:0] k_buf_val_3_V_address1;
reg k_buf_val_3_V_ce1;
reg k_buf_val_3_V_we1;
wire [7:0] k_buf_val_3_V_d1;
wire [10:0] k_buf_val_4_V_address0;
reg k_buf_val_4_V_ce0;
wire [7:0] k_buf_val_4_V_q0;
wire [10:0] k_buf_val_4_V_address1;
reg k_buf_val_4_V_ce1;
reg k_buf_val_4_V_we1;
wire [7:0] k_buf_val_4_V_d1;
wire [10:0] k_buf_val_5_V_address0;
reg k_buf_val_5_V_ce0;
wire [7:0] k_buf_val_5_V_q0;
wire [10:0] k_buf_val_5_V_address1;
reg k_buf_val_5_V_ce1;
reg k_buf_val_5_V_we1;
wire [7:0] k_buf_val_5_V_d1;
wire [10:0] core_buf_val_0_V_address0;
reg core_buf_val_0_V_ce0;
wire [10:0] core_buf_val_0_V_address1;
reg core_buf_val_0_V_ce1;
reg core_buf_val_0_V_we1;
wire [7:0] core_buf_val_0_V_d1;
wire [10:0] core_buf_val_1_V_address0;
reg core_buf_val_1_V_ce0;
wire [10:0] core_buf_val_1_V_address1;
reg core_buf_val_1_V_ce1;
reg core_buf_val_1_V_we1;
wire [7:0] core_buf_val_1_V_d1;
wire [31:0] grp_image_filter_reg_int_s_fu_542_in_r;
reg grp_image_filter_reg_int_s_fu_542_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_547_in_r;
reg grp_image_filter_reg_int_s_fu_547_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_552_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_552_ap_return;
reg grp_image_filter_reg_int_s_fu_552_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_557_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_557_ap_return;
reg grp_image_filter_reg_int_s_fu_557_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_562_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_562_ap_return;
reg grp_image_filter_reg_int_s_fu_562_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_567_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_567_ap_return;
reg grp_image_filter_reg_int_s_fu_567_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_572_in_r;
reg grp_image_filter_reg_int_s_fu_572_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_577_in_r;
reg grp_image_filter_reg_int_s_fu_577_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_582_in_r;
reg grp_image_filter_reg_int_s_fu_582_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_587_in_r;
reg grp_image_filter_reg_int_s_fu_587_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_592_in_r;
reg grp_image_filter_reg_int_s_fu_592_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_597_in_r;
reg grp_image_filter_reg_int_s_fu_597_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_602_in_r;
reg grp_image_filter_reg_int_s_fu_602_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_607_in_r;
reg grp_image_filter_reg_int_s_fu_607_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_612_in_r;
reg grp_image_filter_reg_int_s_fu_612_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_617_in_r;
reg grp_image_filter_reg_int_s_fu_617_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_622_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_622_ap_return;
reg grp_image_filter_reg_int_s_fu_622_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_627_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_627_ap_return;
reg grp_image_filter_reg_int_s_fu_627_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_632_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_632_ap_return;
reg grp_image_filter_reg_int_s_fu_632_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_637_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_637_ap_return;
reg grp_image_filter_reg_int_s_fu_637_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_642_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_642_ap_return;
reg grp_image_filter_reg_int_s_fu_642_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_647_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_647_ap_return;
reg grp_image_filter_reg_int_s_fu_647_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_652_in_r;
reg grp_image_filter_reg_int_s_fu_652_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_657_in_r;
reg grp_image_filter_reg_int_s_fu_657_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_662_in_r;
reg grp_image_filter_reg_int_s_fu_662_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_667_in_r;
reg grp_image_filter_reg_int_s_fu_667_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_672_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_672_ap_return;
reg grp_image_filter_reg_int_s_fu_672_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_677_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_677_ap_return;
reg grp_image_filter_reg_int_s_fu_677_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_682_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_682_ap_return;
reg grp_image_filter_reg_int_s_fu_682_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_687_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_687_ap_return;
reg grp_image_filter_reg_int_s_fu_687_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_692_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_692_ap_return;
reg grp_image_filter_reg_int_s_fu_692_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_697_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_697_ap_return;
reg grp_image_filter_reg_int_s_fu_697_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_702_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_702_ap_return;
reg grp_image_filter_reg_int_s_fu_702_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_707_in_r;
wire [31:0] grp_image_filter_reg_int_s_fu_707_ap_return;
reg grp_image_filter_reg_int_s_fu_707_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_712_in_r;
reg grp_image_filter_reg_int_s_fu_712_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_717_in_r;
reg grp_image_filter_reg_int_s_fu_717_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_722_in_r;
reg grp_image_filter_reg_int_s_fu_722_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_727_in_r;
reg grp_image_filter_reg_int_s_fu_727_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_732_in_r;
reg grp_image_filter_reg_int_s_fu_732_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_737_in_r;
reg grp_image_filter_reg_int_s_fu_737_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_742_in_r;
reg grp_image_filter_reg_int_s_fu_742_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_747_in_r;
reg grp_image_filter_reg_int_s_fu_747_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_752_in_r;
reg grp_image_filter_reg_int_s_fu_752_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_757_in_r;
reg grp_image_filter_reg_int_s_fu_757_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_762_in_r;
reg grp_image_filter_reg_int_s_fu_762_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_767_in_r;
reg grp_image_filter_reg_int_s_fu_767_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_772_in_r;
reg grp_image_filter_reg_int_s_fu_772_ap_ce;
wire [31:0] grp_image_filter_reg_int_s_fu_777_in_r;
reg grp_image_filter_reg_int_s_fu_777_ap_ce;
reg [10:0] p_s_reg_504;
reg ap_sig_cseq_ST_st39_fsm_3;
reg ap_sig_bdd_2075;
reg [10:0] p_2_phi_fu_519_p4;
wire [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it0;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it1;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it2;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it3;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it4;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it5;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it6;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it7;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it8;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it9;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it10;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it11;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it12;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it13;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it14;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it15;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it16;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it17;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it18;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it19;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it20;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it21;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it22;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it23;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it24;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it25;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it26;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it27;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it28;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it29;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it30;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it31;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it32;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it33;
reg [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it34;
wire [63:0] tmp_12_fu_867_p1;
wire [63:0] tmp_14_fu_4577_p1;
reg [7:0] win_val_6_V_5_fu_132;
reg [15:0] core_win_val_0_V_0_fu_136;
reg [15:0] core_win_val_0_V_1_fu_140;
wire [15:0] core_win_val_0_V_2_fu_4620_p1;
reg [7:0] win_val_6_V_4_fu_144;
reg [15:0] core_win_val_1_V_0_fu_148;
reg [15:0] core_win_val_1_V_1_fu_152;
wire [15:0] core_win_val_1_V_2_fu_4623_p1;
reg [7:0] win_val_6_V_3_fu_156;
reg [15:0] core_win_val_2_V_0_fu_160;
reg [15:0] core_win_val_2_V_1_fu_164;
wire [15:0] core_win_val_2_V_1_2_fu_4643_p1;
reg [7:0] win_val_0_V_2_3_fu_168;
reg [7:0] win_val_0_V_2_fu_172;
reg [7:0] win_val_0_V_3_fu_176;
reg [7:0] win_val_0_V_4_fu_180;
reg [7:0] win_val_0_V_5_fu_184;
reg [7:0] win_val_1_V_1_3_fu_188;
reg [7:0] win_val_1_V_1_fu_192;
reg [7:0] win_val_1_V_2_fu_196;
reg [7:0] win_val_1_V_3_fu_200;
reg [7:0] win_val_1_V_4_fu_204;
reg [7:0] win_val_1_V_5_fu_208;
reg [7:0] win_val_2_V_0_3_fu_212;
reg [7:0] win_val_2_V_0_fu_216;
reg [7:0] win_val_2_V_1_fu_220;
reg [7:0] win_val_2_V_2_fu_224;
reg [7:0] win_val_2_V_3_fu_228;
reg [7:0] win_val_2_V_4_fu_232;
reg [7:0] win_val_2_V_5_fu_236;
reg [7:0] win_val_3_V_0_3_fu_240;
reg [7:0] win_val_3_V_0_fu_244;
reg [7:0] win_val_3_V_1_fu_248;
reg [7:0] win_val_3_V_2_fu_252;
reg [7:0] win_val_3_V_3_fu_256;
reg [7:0] win_val_3_V_4_fu_260;
reg [7:0] win_val_3_V_5_fu_264;
reg [7:0] win_val_4_V_0_3_fu_268;
reg [7:0] win_val_4_V_0_fu_272;
reg [7:0] win_val_4_V_1_fu_276;
reg [7:0] win_val_4_V_2_fu_280;
reg [7:0] win_val_4_V_3_fu_284;
reg [7:0] win_val_4_V_4_fu_288;
reg [7:0] win_val_4_V_5_fu_292;
reg [7:0] win_val_5_V_1_3_fu_296;
reg [7:0] win_val_5_V_1_fu_300;
reg [7:0] win_val_5_V_2_fu_304;
reg [7:0] win_val_5_V_3_fu_308;
reg [7:0] win_val_5_V_4_fu_312;
reg [7:0] win_val_5_V_5_fu_316;
reg [7:0] win_val_6_V_2_3_fu_320;
reg [7:0] win_val_6_V_2_fu_324;
wire [7:0] core_win_val_2_V_2_fu_4635_p3;
wire [8:0] tmp_16_fu_830_p4;
wire [0:0] tmp_11_fu_857_p2;
wire [0:0] tmp_17_fu_877_p2;
wire [8:0] tmp_97_fu_888_p4;
wire [0:0] icmp1_fu_898_p2;
wire [8:0] rhs_V_fu_1256_p1;
wire [0:0] tmp_18_fu_1266_p2;
wire [0:0] tmp_19_fu_1272_p2;
wire [8:0] rhs_V_s_fu_1292_p1;
wire [0:0] tmp_176_1_fu_1302_p2;
wire [0:0] tmp_177_1_fu_1308_p2;
wire [8:0] rhs_V_2_fu_1328_p1;
wire [0:0] tmp_176_2_fu_1338_p2;
wire [0:0] tmp_177_2_fu_1344_p2;
wire [8:0] rhs_V_3_fu_1364_p1;
wire [0:0] tmp_176_3_fu_1374_p2;
wire [0:0] tmp_177_3_fu_1380_p2;
wire [8:0] rhs_V_4_fu_1400_p1;
wire [8:0] rhs_V_5_fu_1422_p1;
wire [8:0] rhs_V_6_fu_1444_p1;
wire [8:0] rhs_V_7_fu_1466_p1;
wire [8:0] rhs_V_1_fu_1512_p1;
wire [0:0] tmp_21_fu_1527_p2;
wire [0:0] tmp_22_fu_1533_p2;
wire [8:0] rhs_V_1_1_fu_1553_p1;
wire [8:0] rhs_V_1_2_fu_1580_p1;
wire [8:0] rhs_V_1_3_fu_1607_p1;
wire [8:0] rhs_V_1_4_fu_1622_p1;
wire [0:0] tmp_31_fu_1638_p2;
wire [1:0] phitmp_4_fu_1631_p3;
wire [8:0] rhs_V_1_5_fu_1650_p1;
wire [0:0] tmp_33_fu_1666_p2;
wire [1:0] phitmp_5_fu_1659_p3;
wire [8:0] rhs_V_1_6_fu_1678_p1;
wire [0:0] tmp_35_fu_1694_p2;
wire [1:0] phitmp_6_fu_1687_p3;
wire [8:0] rhs_V_1_7_fu_1706_p1;
wire [0:0] tmp_37_fu_1722_p2;
wire [1:0] phitmp_7_fu_1715_p3;
wire [1:0] flag_val_V_assign_load_1_1_fu_1562_p3;
wire [0:0] tmp_181_0_not_fu_1734_p2;
wire [1:0] flag_val_V_assign_load_1_2_fu_1589_p3;
wire [0:0] tmp_183_1_fu_1758_p2;
wire [0:0] tmp_181_1_not_fu_1752_p2;
wire [1:0] flag_val_V_assign_load_1_4_fu_1616_p3;
wire [0:0] tmp_183_2_fu_1776_p2;
wire [0:0] tmp_181_2_not_fu_1770_p2;
wire [1:0] flag_val_V_assign_load_1_6_fu_1642_p3;
wire [0:0] tmp_183_3_fu_1794_p2;
wire [0:0] tmp_181_3_not_fu_1788_p2;
wire [1:0] flag_val_V_assign_load_1_8_fu_1670_p3;
wire [0:0] tmp_183_4_fu_1812_p2;
wire [0:0] tmp_181_4_not_fu_1806_p2;
wire [1:0] flag_val_V_assign_load_1_11_fu_1698_p3;
wire [0:0] tmp_25_fu_1907_p2;
wire [1:0] phitmp1_1_fu_1900_p3;
wire [0:0] tmp_28_fu_1926_p2;
wire [1:0] phitmp1_2_fu_1919_p3;
wire [0:0] tmp_182_3_fu_1938_p2;
wire [0:0] tmp_184_3_fu_1943_p2;
wire [0:0] tmp_30_fu_1956_p2;
wire [1:0] phitmp1_3_fu_1948_p3;
wire [0:0] tmp_41_fu_2010_p2;
wire [3:0] phitmp42_op_cast_cast_cast_fu_2003_p3;
wire [3:0] count_1_i_2_op_op_fu_1998_p3;
wire [0:0] or_cond3_fu_1994_p2;
wire [0:0] tmp_42_fu_2030_p2;
wire [3:0] phitmp3_cast_cast_cast_fu_2022_p3;
wire [3:0] count_1_i_4_op_fu_2014_p3;
wire [1:0] flag_val_V_assign_load_2_s_fu_1894_p3;
wire [0:0] tmp_183_7_fu_2049_p2;
wire [0:0] tmp_181_7_not_fu_2044_p2;
wire [1:0] flag_val_V_assign_load_1_9_fu_1911_p3;
wire [0:0] tmp_181_8_fu_2069_p2;
wire [0:0] tmp_32_fu_2108_p2;
wire [1:0] phitmp1_4_fu_2101_p3;
wire [0:0] tmp_34_fu_2127_p2;
wire [1:0] phitmp1_5_fu_2120_p3;
wire [0:0] tmp_182_6_fu_2139_p2;
wire [0:0] tmp_184_6_fu_2144_p2;
wire [0:0] tmp_36_fu_2157_p2;
wire [1:0] phitmp1_6_fu_2149_p3;
wire [0:0] tmp_185_7_fu_2181_p2;
wire [3:0] count_8_fu_2197_p2;
wire [0:0] tmp_185_8_fu_2202_p2;
wire [0:0] not_or_cond1_fu_2213_p2;
wire [3:0] phitmp4_fu_2208_p2;
wire [3:0] count_1_i_8_fu_2224_p3;
wire [0:0] not_or_cond2_demorgan_fu_2241_p2;
wire [0:0] tmp_185_9_fu_2235_p2;
wire [0:0] not_or_cond2_fu_2245_p2;
wire [0:0] or_cond12_fu_2231_p2;
wire [0:0] tmp_181_s_fu_2265_p2;
wire [0:0] tmp_183_s_fu_2269_p2;
wire [0:0] or_cond13_fu_2274_p2;
wire [3:0] phitmp5_fu_2280_p2;
wire [1:0] flag_val_V_assign_load_1_7_fu_2112_p3;
wire [0:0] tmp_181_1_fu_2300_p2;
wire [0:0] tmp_183_8_fu_2305_p2;
wire [0:0] iscorner_2_i_7_fu_2191_p2;
wire [0:0] p_iscorner_0_i_8_fu_2218_p2;
wire [0:0] tmp_38_fu_2347_p2;
wire [1:0] phitmp1_7_fu_2340_p3;
wire [3:0] count_s_fu_2359_p2;
wire [0:0] tmp_185_s_fu_2364_p2;
wire [0:0] not_or_cond3_fu_2370_p2;
wire [0:0] tmp_185_1_fu_2381_p2;
wire [0:0] not_or_cond4_fu_2386_p2;
wire [3:0] count_1_i_1_fu_2397_p3;
wire [3:0] count_1_fu_2407_p2;
wire [0:0] not_or_cond12_demorgan_fu_2425_p2;
wire [0:0] tmp_185_2_fu_2413_p2;
wire [0:0] not_or_cond12_fu_2429_p2;
wire [0:0] or_cond15_fu_2403_p2;
wire [3:0] phitmp6_fu_2419_p2;
wire [0:0] tmp_181_3_fu_2449_p2;
wire [0:0] tmp_183_11_fu_2453_p2;
wire [3:0] count_1_i_2_fu_2441_p3;
wire [0:0] or_cond16_fu_2458_p2;
wire [1:0] flag_val_V_assign_load_1_14_fu_2351_p3;
wire [0:0] tmp_181_4_fu_2484_p2;
wire [0:0] tmp_183_12_fu_2489_p2;
wire [0:0] tmp_181_5_fu_2506_p2;
wire [0:0] p_iscorner_0_i_s_fu_2375_p2;
wire [0:0] not_or_cond13_fu_2521_p2;
wire [4:0] count_1_i_3_cast_fu_2531_p1;
wire [4:0] count_2_fu_2534_p2;
wire [0:0] tmp_185_4_fu_2540_p2;
wire [0:0] not_or_cond14_fu_2552_p2;
wire [4:0] phitmp7_fu_2546_p2;
wire [4:0] count_1_i_4_fu_2563_p3;
wire [0:0] tmp_185_5_fu_2570_p2;
wire [0:0] not_or_cond15_fu_2576_p2;
wire [4:0] count_1_i_5_fu_2587_p3;
wire [0:0] p_iscorner_0_i_3_fu_2526_p2;
wire [0:0] p_iscorner_0_i_4_fu_2557_p2;
wire [0:0] tmp_185_6_fu_2620_p2;
wire [0:0] not_or_cond5_fu_2625_p2;
wire [4:0] count_1_i_10_fu_2636_p3;
wire [0:0] tmp_185_10_fu_2642_p2;
wire [0:0] not_or_cond6_fu_2648_p2;
wire [4:0] count_1_i_11_fu_2659_p3;
wire [4:0] phitmp9_fu_2672_p2;
wire [0:0] tmp7_fu_2685_p2;
wire [0:0] p_iscorner_0_i_6_fu_2630_p2;
wire [0:0] tmp_185_11_fu_2699_p2;
wire [0:0] not_or_cond7_fu_2704_p2;
wire [0:0] tmp_185_12_fu_2715_p2;
wire [0:0] not_or_cond8_fu_2720_p2;
wire [4:0] count_1_i_13_fu_2731_p3;
wire [4:0] count_5_fu_2737_p2;
wire [4:0] phitmp10_fu_2749_p2;
wire [0:0] p_iscorner_0_i_10_fu_2709_p2;
wire [0:0] not_or_cond9_fu_2767_p2;
wire [0:0] tmp_185_14_fu_2777_p2;
wire [0:0] not_or_cond10_fu_2782_p2;
wire [4:0] count_1_i_15_fu_2793_p3;
wire [4:0] count_6_fu_2799_p2;
wire [4:0] phitmp_fu_2811_p2;
wire [0:0] p_iscorner_0_i_12_fu_2772_p2;
wire [0:0] p_iscorner_0_i_14_fu_2842_p2;
wire [0:0] p_iscorner_0_i_15_fu_2846_p2;
wire [0:0] tmp17_fu_2850_p2;
wire [0:0] tmp16_fu_2856_p2;
wire [0:0] tmp10_fu_2866_p2;
wire [0:0] tmp_188_1_fu_2875_p2;
wire [8:0] tmp_193_1_fu_2879_p3;
wire [0:0] tmp_195_1_fu_2890_p2;
wire [8:0] tmp_203_1_fu_2894_p3;
wire [0:0] tmp_188_3_fu_2905_p2;
wire [8:0] tmp_193_3_fu_2909_p3;
wire [0:0] tmp_195_3_fu_2920_p2;
wire [8:0] tmp_203_3_fu_2924_p3;
wire [0:0] tmp_188_5_fu_2935_p2;
wire [8:0] tmp_193_5_fu_2939_p3;
wire [0:0] tmp_195_5_fu_2950_p2;
wire [8:0] tmp_203_5_fu_2954_p3;
wire [0:0] tmp_188_7_fu_2965_p2;
wire [8:0] tmp_193_7_fu_2969_p3;
wire [0:0] tmp_195_7_fu_2980_p2;
wire [8:0] tmp_203_7_fu_2984_p3;
wire [0:0] tmp_192_1_fu_2995_p2;
wire [0:0] tmp_202_1_fu_3010_p2;
wire [0:0] tmp_192_3_fu_3025_p2;
wire [0:0] tmp_202_3_fu_3039_p2;
wire [0:0] tmp_192_5_fu_3053_p2;
wire [0:0] tmp_202_5_fu_3068_p2;
wire [0:0] tmp_188_9_fu_3083_p2;
wire [8:0] tmp_193_9_fu_3087_p3;
wire [0:0] tmp_195_9_fu_3098_p2;
wire [8:0] tmp_203_9_fu_3102_p3;
wire [0:0] tmp_199_1_fu_3113_p2;
wire [0:0] tmp_212_1_fu_3128_p2;
wire [0:0] tmp_188_s_fu_3146_p2;
wire [8:0] tmp_193_s_fu_3150_p3;
wire [0:0] tmp_195_s_fu_3161_p2;
wire [8:0] tmp_203_s_fu_3165_p3;
wire [0:0] tmp_188_2_fu_3176_p2;
wire [8:0] tmp_193_2_fu_3180_p3;
wire [0:0] tmp_195_2_fu_3191_p2;
wire [8:0] tmp_203_2_fu_3195_p3;
wire [0:0] tmp_188_4_fu_3206_p2;
wire [8:0] tmp_193_4_fu_3210_p3;
wire [0:0] tmp_195_4_fu_3221_p2;
wire [8:0] tmp_203_4_fu_3225_p3;
wire [0:0] tmp_192_7_fu_3236_p2;
wire [0:0] tmp_202_7_fu_3249_p2;
wire [0:0] tmp_192_9_fu_3277_p2;
wire [0:0] tmp_202_9_fu_3290_p2;
wire [0:0] tmp_192_s_fu_3303_p2;
wire [0:0] tmp_202_s_fu_3318_p2;
wire [0:0] tmp_192_2_fu_3333_p2;
wire [0:0] tmp_202_2_fu_3348_p2;
wire [0:0] tmp_192_4_fu_3363_p2;
wire [0:0] tmp_202_4_fu_3376_p2;
wire [0:0] tmp_199_3_fu_3389_p2;
wire [0:0] tmp_212_3_fu_3404_p2;
wire [31:0] a_0_flag_d_assign_load_5_fu_3419_p3;
wire [0:0] tmp_45_fu_3428_p2;
wire [7:0] tmp_44_fu_3424_p1;
wire signed [31:0] flag_d_assign_9_fu_3274_p1;
wire [0:0] tmp_46_fu_3442_p2;
wire [31:0] tmp_68_fu_3458_p3;
wire [0:0] tmp_69_fu_3467_p2;
wire [8:0] tmp_80_fu_3463_p1;
wire [0:0] tmp_70_fu_3481_p2;
wire [0:0] tmp_199_5_fu_3500_p2;
wire [0:0] tmp_212_5_fu_3512_p2;
wire [0:0] tmp_199_7_fu_3524_p2;
wire [0:0] tmp_212_7_fu_3536_p2;
wire [0:0] tmp_199_9_fu_3548_p2;
wire [0:0] tmp_212_9_fu_3562_p2;
wire [0:0] tmp_199_s_fu_3576_p2;
wire [0:0] tmp_212_s_fu_3590_p2;
wire [0:0] tmp_199_2_fu_3604_p2;
wire [0:0] tmp_212_2_fu_3616_p2;
wire [0:0] tmp_199_4_fu_3628_p2;
wire [0:0] tmp_212_4_fu_3640_p2;
wire [31:0] p_a_0_flag_d_assign_load_5_cast_fu_3652_p1;
wire [0:0] tmp_49_fu_3655_p2;
wire signed [31:0] b0_cast_fu_3672_p1;
wire [0:0] tmp_72_fu_3675_p2;
wire [31:0] tmp_216_1_fu_3698_p3;
wire [31:0] p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1;
wire [0:0] tmp_217_1_fu_3707_p2;
wire [7:0] tmp_56_fu_3703_p1;
wire signed [31:0] flag_d_assign_10_fu_3692_p1;
wire [0:0] tmp_231_1_fu_3720_p2;
wire [31:0] tmp_227_1_fu_3739_p3;
wire signed [31:0] b0_tmp_239_cast_fu_3736_p1;
wire [0:0] tmp_228_1_fu_3748_p2;
wire [8:0] tmp_82_fu_3744_p1;
wire [0:0] tmp_236_1_fu_3761_p2;
wire [31:0] a0_cast_fu_3780_p1;
wire [0:0] tmp_233_1_fu_3783_p2;
wire signed [31:0] b0_cast_50_fu_3800_p1;
wire [0:0] tmp_240_1_fu_3803_p2;
wire [31:0] tmp_216_2_fu_3826_p3;
wire [31:0] a0_tmp_232_1_cast_fu_3823_p1;
wire [0:0] tmp_217_2_fu_3835_p2;
wire [7:0] tmp_58_fu_3831_p1;
wire signed [31:0] flag_d_assign_12_fu_3820_p1;
wire [0:0] tmp_231_2_fu_3848_p2;
wire [31:0] tmp_227_2_fu_3867_p3;
wire signed [31:0] b0_tmp_239_1_cast_fu_3864_p1;
wire [0:0] tmp_228_2_fu_3876_p2;
wire [8:0] tmp_84_fu_3872_p1;
wire [0:0] tmp_236_2_fu_3889_p2;
wire [31:0] a0_2_cast_fu_3908_p1;
wire [0:0] tmp_233_2_fu_3911_p2;
wire signed [31:0] b0_2_cast_fu_3928_p1;
wire [0:0] tmp_240_2_fu_3931_p2;
wire [31:0] tmp_216_3_fu_3954_p3;
wire [31:0] a0_2_tmp_232_2_cast_fu_3951_p1;
wire [0:0] tmp_217_3_fu_3963_p2;
wire [7:0] tmp_60_fu_3959_p1;
wire signed [31:0] flag_d_assign_14_fu_3948_p1;
wire [0:0] tmp_231_3_fu_3976_p2;
wire [31:0] tmp_227_3_fu_3995_p3;
wire signed [31:0] b0_2_tmp_239_2_cast_fu_3992_p1;
wire [0:0] tmp_228_3_fu_4004_p2;
wire [8:0] tmp_86_fu_4000_p1;
wire [0:0] tmp_236_3_fu_4017_p2;
wire [31:0] a0_3_cast_fu_4036_p1;
wire [0:0] tmp_233_3_fu_4039_p2;
wire signed [31:0] b0_3_cast_fu_4056_p1;
wire [0:0] tmp_240_3_fu_4059_p2;
wire [31:0] tmp_216_4_fu_4082_p3;
wire [31:0] a0_3_tmp_232_3_cast_fu_4079_p1;
wire [0:0] tmp_217_4_fu_4091_p2;
wire [7:0] tmp_62_fu_4087_p1;
wire signed [31:0] flag_d_assign_1_fu_4076_p1;
wire [0:0] tmp_231_4_fu_4104_p2;
wire [31:0] tmp_227_4_fu_4123_p3;
wire signed [31:0] b0_3_tmp_239_3_cast_fu_4120_p1;
wire [0:0] tmp_228_4_fu_4132_p2;
wire [8:0] tmp_88_fu_4128_p1;
wire [0:0] tmp_236_4_fu_4145_p2;
wire [31:0] a0_4_cast_fu_4164_p1;
wire [0:0] tmp_233_4_fu_4167_p2;
wire signed [31:0] b0_4_cast_fu_4184_p1;
wire [0:0] tmp_240_4_fu_4187_p2;
wire [31:0] tmp_216_5_fu_4210_p3;
wire [31:0] a0_4_tmp_232_4_cast_fu_4207_p1;
wire [0:0] tmp_217_5_fu_4219_p2;
wire [7:0] tmp_64_fu_4215_p1;
wire signed [31:0] flag_d_assign_3_fu_4204_p1;
wire [0:0] tmp_231_5_fu_4232_p2;
wire [31:0] tmp_227_5_fu_4251_p3;
wire signed [31:0] b0_4_tmp_239_4_cast_fu_4248_p1;
wire [0:0] tmp_228_5_fu_4260_p2;
wire [8:0] tmp_90_fu_4256_p1;
wire [0:0] tmp_236_5_fu_4273_p2;
wire [31:0] a0_5_cast_fu_4292_p1;
wire [0:0] tmp_233_5_fu_4295_p2;
wire signed [31:0] b0_5_cast_fu_4312_p1;
wire [0:0] tmp_240_5_fu_4315_p2;
wire [31:0] tmp_216_6_fu_4338_p3;
wire [31:0] a0_5_tmp_232_5_cast_fu_4335_p1;
wire [0:0] tmp_217_6_fu_4347_p2;
wire [7:0] tmp_66_fu_4343_p1;
wire signed [31:0] flag_d_assign_5_fu_4332_p1;
wire [0:0] tmp_231_6_fu_4360_p2;
wire [31:0] tmp_227_6_fu_4379_p3;
wire signed [31:0] b0_5_tmp_239_5_cast_fu_4376_p1;
wire [0:0] tmp_228_6_fu_4388_p2;
wire [8:0] tmp_92_fu_4384_p1;
wire [0:0] tmp_236_6_fu_4401_p2;
wire [31:0] a0_6_cast_fu_4420_p1;
wire [0:0] tmp_233_6_fu_4423_p2;
wire signed [31:0] b0_6_cast_fu_4440_p1;
wire [0:0] tmp_240_6_fu_4443_p2;
wire [31:0] tmp_216_7_fu_4466_p3;
wire [31:0] a0_6_tmp_232_6_cast_fu_4463_p1;
wire [0:0] tmp_217_7_fu_4475_p2;
wire [7:0] tmp_77_fu_4471_p1;
wire signed [31:0] flag_d_assign_7_fu_4460_p1;
wire [0:0] tmp_231_7_fu_4488_p2;
wire [31:0] tmp_227_7_fu_4507_p3;
wire signed [31:0] b0_6_tmp_239_6_cast_fu_4504_p1;
wire [0:0] tmp_228_7_fu_4516_p2;
wire [8:0] tmp_94_fu_4512_p1;
wire [0:0] tmp_236_7_fu_4529_p2;
wire [31:0] a0_7_cast_fu_4549_p1;
wire [0:0] tmp_233_7_fu_4552_p2;
wire signed [31:0] b0_7_cast_fu_4563_p1;
wire [0:0] tmp_240_7_fu_4566_p2;
wire [7:0] tmp_50_fu_4583_p2;
wire [0:0] tmp_51_fu_4588_p2;
wire [0:0] tmp_52_fu_4647_p2;
wire [0:0] tmp_73_fu_4653_p2;
wire [0:0] tmp_242_1_fu_4659_p2;
wire [0:0] tmp21_fu_4706_p2;
wire [0:0] tmp_74_fu_4671_p2;
wire [0:0] tmp_245_1_fu_4677_p2;
wire [0:0] tmp24_fu_4717_p2;
wire [0:0] tmp_242_2_fu_4665_p2;
wire [0:0] tmp_55_fu_4695_p2;
wire [0:0] tmp_54_fu_4689_p2;
wire [0:0] tmp26_fu_4729_p2;
wire [0:0] tmp_245_2_fu_4683_p2;
wire [0:0] tmp22_fu_4775_p2;
wire [0:0] tmp18_fu_4771_p2;
wire [0:0] tmp_26_fu_4779_p2;
reg [3:0] ap_NS_fsm;
reg ap_sig_bdd_2152;
reg ap_sig_bdd_250;
reg ap_sig_bdd_2159;
reg ap_sig_bdd_2108;
reg ap_sig_bdd_2156;
reg ap_sig_bdd_1776;
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_0_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_0_V_address0 ),
.ce0( k_buf_val_0_V_ce0 ),
.q0( k_buf_val_0_V_q0 ),
.address1( k_buf_val_0_V_address1 ),
.ce1( k_buf_val_0_V_ce1 ),
.we1( k_buf_val_0_V_we1 ),
.d1( k_buf_val_0_V_d1 )
);
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_1_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_1_V_address0 ),
.ce0( k_buf_val_1_V_ce0 ),
.q0( k_buf_val_1_V_q0 ),
.address1( k_buf_val_1_V_address1 ),
.ce1( k_buf_val_1_V_ce1 ),
.we1( k_buf_val_1_V_we1 ),
.d1( k_buf_val_1_V_d1 )
);
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_2_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_2_V_address0 ),
.ce0( k_buf_val_2_V_ce0 ),
.q0( k_buf_val_2_V_q0 ),
.address1( k_buf_val_2_V_address1 ),
.ce1( k_buf_val_2_V_ce1 ),
.we1( k_buf_val_2_V_we1 ),
.d1( k_buf_val_2_V_d1 )
);
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_3_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_3_V_address0 ),
.ce0( k_buf_val_3_V_ce0 ),
.q0( k_buf_val_3_V_q0 ),
.address1( k_buf_val_3_V_address1 ),
.ce1( k_buf_val_3_V_ce1 ),
.we1( k_buf_val_3_V_we1 ),
.d1( k_buf_val_3_V_d1 )
);
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_4_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_4_V_address0 ),
.ce0( k_buf_val_4_V_ce0 ),
.q0( k_buf_val_4_V_q0 ),
.address1( k_buf_val_4_V_address1 ),
.ce1( k_buf_val_4_V_ce1 ),
.we1( k_buf_val_4_V_we1 ),
.d1( k_buf_val_4_V_d1 )
);
image_filter_FAST_t_opr_k_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_val_5_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_val_5_V_address0 ),
.ce0( k_buf_val_5_V_ce0 ),
.q0( k_buf_val_5_V_q0 ),
.address1( k_buf_val_5_V_address1 ),
.ce1( k_buf_val_5_V_ce1 ),
.we1( k_buf_val_5_V_we1 ),
.d1( k_buf_val_5_V_d1 )
);
image_filter_FAST_t_opr_core_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1927 ),
.AddressWidth( 11 ))
core_buf_val_0_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( core_buf_val_0_V_address0 ),
.ce0( core_buf_val_0_V_ce0 ),
.q0( core_buf_val_0_V_q0 ),
.address1( core_buf_val_0_V_address1 ),
.ce1( core_buf_val_0_V_ce1 ),
.we1( core_buf_val_0_V_we1 ),
.d1( core_buf_val_0_V_d1 )
);
image_filter_FAST_t_opr_core_buf_val_0_V #(
.DataWidth( 8 ),
.AddressRange( 1927 ),
.AddressWidth( 11 ))
core_buf_val_1_V_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( core_buf_val_1_V_address0 ),
.ce0( core_buf_val_1_V_ce0 ),
.q0( core_buf_val_1_V_q0 ),
.address1( core_buf_val_1_V_address1 ),
.ce1( core_buf_val_1_V_ce1 ),
.we1( core_buf_val_1_V_we1 ),
.d1( core_buf_val_1_V_d1 )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_542(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_542_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_542_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_542_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_547(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_547_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_547_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_547_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_552(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_552_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_552_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_552_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_557(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_557_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_557_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_557_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_562(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_562_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_562_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_562_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_567(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_567_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_567_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_567_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_572(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_572_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_572_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_572_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_577(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_577_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_577_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_577_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_582(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_582_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_582_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_582_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_587(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_587_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_587_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_587_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_592(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_592_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_592_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_592_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_597(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_597_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_597_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_597_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_602(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_602_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_602_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_602_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_607(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_607_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_607_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_607_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_612(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_612_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_612_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_612_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_617(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_617_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_617_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_617_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_622(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_622_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_622_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_622_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_627(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_627_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_627_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_627_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_632(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_632_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_632_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_632_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_637(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_637_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_637_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_637_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_642(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_642_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_642_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_642_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_647(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_647_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_647_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_647_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_652(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_652_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_652_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_652_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_657(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_657_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_657_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_657_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_662(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_662_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_662_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_662_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_667(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_667_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_667_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_667_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_672(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_672_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_672_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_672_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_677(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_677_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_677_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_677_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_682(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_682_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_682_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_682_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_687(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_687_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_687_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_687_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_692(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_692_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_692_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_692_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_697(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_697_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_697_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_697_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_702(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_702_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_702_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_702_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_707(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_707_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_707_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_707_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_712(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_712_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_712_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_712_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_717(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_717_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_717_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_717_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_722(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_722_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_722_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_722_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_727(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_727_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_727_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_727_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_732(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_732_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_732_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_732_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_737(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_737_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_737_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_737_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_742(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_742_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_742_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_742_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_747(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_747_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_747_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_747_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_752(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_752_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_752_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_752_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_757(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_757_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_757_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_757_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_762(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_762_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_762_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_762_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_767(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_767_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_767_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_767_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_772(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_772_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_772_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_772_ap_ce )
);
image_filter_reg_int_s grp_image_filter_reg_int_s_fu_777(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.in_r( grp_image_filter_reg_int_s_fu_777_in_r ),
.ap_return( grp_image_filter_reg_int_s_fu_777_ap_return ),
.ap_ce( grp_image_filter_reg_int_s_fu_777_ap_ce )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_lv1_0 == exitcond_fu_846_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end
end
end
/// ap_reg_ppiten_pp0_it14 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it14
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end
end
end
/// ap_reg_ppiten_pp0_it15 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it15
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end
end
end
/// ap_reg_ppiten_pp0_it16 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it16
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end
end
end
/// ap_reg_ppiten_pp0_it17 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it17
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end
end
end
/// ap_reg_ppiten_pp0_it18 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it18
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end
end
end
/// ap_reg_ppiten_pp0_it19 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it19
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it20 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it20
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end
end
end
/// ap_reg_ppiten_pp0_it21 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it21
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end
end
end
/// ap_reg_ppiten_pp0_it22 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it22
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end
end
end
/// ap_reg_ppiten_pp0_it23 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it23
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end
end
end
/// ap_reg_ppiten_pp0_it24 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it24
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end
end
end
/// ap_reg_ppiten_pp0_it25 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it25
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end
end
end
/// ap_reg_ppiten_pp0_it26 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it26
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end
end
end
/// ap_reg_ppiten_pp0_it27 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it27
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end
end
end
/// ap_reg_ppiten_pp0_it28 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it28
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end
end
end
/// ap_reg_ppiten_pp0_it29 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it29
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it30 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it30
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end
end
end
/// ap_reg_ppiten_pp0_it31 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it31
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end
end
end
/// ap_reg_ppiten_pp0_it32 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it32
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end
end
end
/// ap_reg_ppiten_pp0_it33 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it33
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end
end
end
/// ap_reg_ppiten_pp0_it34 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it34
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end
end
end
/// ap_reg_ppiten_pp0_it35 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it35
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2)) | (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33)))) begin
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_250) begin
if (ap_sig_bdd_2152) begin
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_const_lv8_0;
end else if ((ap_true == ap_true)) begin
ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_reg_phiprechg_core_1_reg_527pp0_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_2108) begin
if (ap_sig_bdd_2159) begin
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_const_lv8_0;
end else if ((ap_true == ap_true)) begin
ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_reg_phiprechg_core_1_reg_527pp0_it12;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_1776) begin
if (ap_sig_bdd_2156) begin
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= phitmp2_fu_4606_p2;
end else if ((ap_true == ap_true)) begin
ap_reg_phiprechg_core_1_reg_527pp0_it34 <= ap_reg_phiprechg_core_1_reg_527pp0_it33;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
p_2_reg_515 <= j_V_reg_5151;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
p_2_reg_515 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st39_fsm_3)) begin
p_s_reg_504 <= i_V_reg_5122;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_180)) begin
p_s_reg_504 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))) begin
a0_2_reg_6285 <= a0_2_fu_3841_p3;
b0_2_reg_6301 <= b0_2_fu_3882_p3;
tmp_232_2_reg_6291 <= tmp_232_2_fu_3853_p3;
tmp_239_2_reg_6307 <= tmp_239_2_fu_3894_p3;
tmp_59_reg_6296 <= tmp_59_fu_3860_p1;
tmp_85_reg_6312 <= tmp_85_fu_3901_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) begin
a0_2_tmp_232_2_reg_6337 <= a0_2_tmp_232_2_fu_3916_p3;
b0_2_tmp_239_2_reg_6348 <= b0_2_tmp_239_2_fu_3936_p3;
tmp_209_3_reg_6343 <= tmp_209_3_fu_3922_p2;
tmp_221_3_reg_6354 <= tmp_221_3_fu_3942_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))) begin
a0_3_reg_6359 <= a0_3_fu_3969_p3;
b0_3_reg_6375 <= b0_3_fu_4010_p3;
tmp_232_3_reg_6365 <= tmp_232_3_fu_3981_p3;
tmp_239_3_reg_6381 <= tmp_239_3_fu_4022_p3;
tmp_61_reg_6370 <= tmp_61_fu_3988_p1;
tmp_87_reg_6386 <= tmp_87_fu_4029_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) begin
a0_3_tmp_232_3_reg_6411 <= a0_3_tmp_232_3_fu_4044_p3;
b0_3_tmp_239_3_reg_6422 <= b0_3_tmp_239_3_fu_4064_p3;
tmp_209_4_reg_6417 <= tmp_209_4_fu_4050_p2;
tmp_221_4_reg_6428 <= tmp_221_4_fu_4070_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))) begin
a0_4_reg_6433 <= a0_4_fu_4097_p3;
b0_4_reg_6449 <= b0_4_fu_4138_p3;
tmp_232_4_reg_6439 <= tmp_232_4_fu_4109_p3;
tmp_239_4_reg_6455 <= tmp_239_4_fu_4150_p3;
tmp_63_reg_6444 <= tmp_63_fu_4116_p1;
tmp_89_reg_6460 <= tmp_89_fu_4157_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) begin
a0_4_tmp_232_4_reg_6485 <= a0_4_tmp_232_4_fu_4172_p3;
b0_4_tmp_239_4_reg_6496 <= b0_4_tmp_239_4_fu_4192_p3;
tmp_209_5_reg_6491 <= tmp_209_5_fu_4178_p2;
tmp_221_5_reg_6502 <= tmp_221_5_fu_4198_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))) begin
a0_5_reg_6507 <= a0_5_fu_4225_p3;
b0_5_reg_6523 <= b0_5_fu_4266_p3;
tmp_232_5_reg_6513 <= tmp_232_5_fu_4237_p3;
tmp_239_5_reg_6529 <= tmp_239_5_fu_4278_p3;
tmp_65_reg_6518 <= tmp_65_fu_4244_p1;
tmp_91_reg_6534 <= tmp_91_fu_4285_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) begin
a0_5_tmp_232_5_reg_6559 <= a0_5_tmp_232_5_fu_4300_p3;
b0_5_tmp_239_5_reg_6570 <= b0_5_tmp_239_5_fu_4320_p3;
tmp_209_6_reg_6565 <= tmp_209_6_fu_4306_p2;
tmp_221_6_reg_6576 <= tmp_221_6_fu_4326_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))) begin
a0_6_reg_6581 <= a0_6_fu_4353_p3;
b0_6_reg_6597 <= b0_6_fu_4394_p3;
tmp_232_6_reg_6587 <= tmp_232_6_fu_4365_p3;
tmp_239_6_reg_6603 <= tmp_239_6_fu_4406_p3;
tmp_75_reg_6592 <= tmp_75_fu_4372_p1;
tmp_93_reg_6608 <= tmp_93_fu_4413_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) begin
a0_6_tmp_232_6_reg_6633 <= a0_6_tmp_232_6_fu_4428_p3;
b0_6_tmp_239_6_reg_6644 <= b0_6_tmp_239_6_fu_4448_p3;
tmp_209_7_reg_6639 <= tmp_209_7_fu_4434_p2;
tmp_221_7_reg_6650 <= tmp_221_7_fu_4454_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29))) begin
a0_7_reg_6655 <= a0_7_fu_4481_p3;
b0_7_reg_6671 <= b0_7_fu_4522_p3;
tmp_232_7_reg_6661 <= tmp_232_7_fu_4493_p3;
tmp_239_7_reg_6676 <= tmp_239_7_fu_4534_p3;
tmp_78_reg_6666 <= tmp_78_fu_4500_p1;
tmp_95_reg_6681 <= tmp_95_fu_4541_p1;
tmp_96_reg_6686 <= tmp_96_fu_4545_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30))) begin
a0_7_tmp_232_7_reg_6691 <= a0_7_tmp_232_7_fu_4557_p3;
tmp_79_reg_6697 <= tmp_79_fu_4571_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))) begin
a0_s_reg_6211 <= a0_s_fu_3713_p3;
b0_s_reg_6227 <= b0_s_fu_3754_p3;
tmp_232_1_reg_6217 <= tmp_232_1_fu_3725_p3;
tmp_239_1_reg_6233 <= tmp_239_1_fu_3766_p3;
tmp_57_reg_6222 <= tmp_57_fu_3732_p1;
tmp_83_reg_6238 <= tmp_83_fu_3773_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) begin
a0_tmp_232_1_reg_6263 <= a0_tmp_232_1_fu_3788_p3;
b0_tmp_239_1_reg_6274 <= b0_tmp_239_1_fu_3808_p3;
tmp_209_2_reg_6269 <= tmp_209_2_fu_3794_p2;
tmp_221_2_reg_6280 <= tmp_221_2_fu_3814_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it10 <= ap_reg_phiprechg_core_1_reg_527pp0_it9;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it11 <= ap_reg_phiprechg_core_1_reg_527pp0_it10;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it12 <= ap_reg_phiprechg_core_1_reg_527pp0_it11;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it13) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it14 <= ap_reg_phiprechg_core_1_reg_527pp0_it13;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it14) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it15 <= ap_reg_phiprechg_core_1_reg_527pp0_it14;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it15) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it16 <= ap_reg_phiprechg_core_1_reg_527pp0_it15;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it16) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it17 <= ap_reg_phiprechg_core_1_reg_527pp0_it16;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it17) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it18 <= ap_reg_phiprechg_core_1_reg_527pp0_it17;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it18) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it19 <= ap_reg_phiprechg_core_1_reg_527pp0_it18;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it2 <= ap_reg_phiprechg_core_1_reg_527pp0_it1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it19) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it20 <= ap_reg_phiprechg_core_1_reg_527pp0_it19;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it20) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it21 <= ap_reg_phiprechg_core_1_reg_527pp0_it20;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it21) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it22 <= ap_reg_phiprechg_core_1_reg_527pp0_it21;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it22) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it23 <= ap_reg_phiprechg_core_1_reg_527pp0_it22;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it23) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it24 <= ap_reg_phiprechg_core_1_reg_527pp0_it23;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it24) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it25 <= ap_reg_phiprechg_core_1_reg_527pp0_it24;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it25) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it26 <= ap_reg_phiprechg_core_1_reg_527pp0_it25;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it26) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it27 <= ap_reg_phiprechg_core_1_reg_527pp0_it26;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it27) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it28 <= ap_reg_phiprechg_core_1_reg_527pp0_it27;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it28) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it29 <= ap_reg_phiprechg_core_1_reg_527pp0_it28;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it3 <= ap_reg_phiprechg_core_1_reg_527pp0_it2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it29) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it30 <= ap_reg_phiprechg_core_1_reg_527pp0_it29;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it30) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it31 <= ap_reg_phiprechg_core_1_reg_527pp0_it30;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it31) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it32 <= ap_reg_phiprechg_core_1_reg_527pp0_it31;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it33 <= ap_reg_phiprechg_core_1_reg_527pp0_it32;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it4 <= ap_reg_phiprechg_core_1_reg_527pp0_it3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it5 <= ap_reg_phiprechg_core_1_reg_527pp0_it4;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it6 <= ap_reg_phiprechg_core_1_reg_527pp0_it5;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it7 <= ap_reg_phiprechg_core_1_reg_527pp0_it6;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it8 <= ap_reg_phiprechg_core_1_reg_527pp0_it7;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it8) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_phiprechg_core_1_reg_527pp0_it9 <= ap_reg_phiprechg_core_1_reg_527pp0_it8;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 <= core_buf_val_1_V_addr_reg_6708;
ap_reg_ppstg_exitcond_reg_5147_pp0_it10 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
ap_reg_ppstg_exitcond_reg_5147_pp0_it11 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
ap_reg_ppstg_exitcond_reg_5147_pp0_it12 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
ap_reg_ppstg_exitcond_reg_5147_pp0_it13 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
ap_reg_ppstg_exitcond_reg_5147_pp0_it14 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
ap_reg_ppstg_exitcond_reg_5147_pp0_it15 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
ap_reg_ppstg_exitcond_reg_5147_pp0_it16 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
ap_reg_ppstg_exitcond_reg_5147_pp0_it17 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
ap_reg_ppstg_exitcond_reg_5147_pp0_it18 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
ap_reg_ppstg_exitcond_reg_5147_pp0_it19 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
ap_reg_ppstg_exitcond_reg_5147_pp0_it2 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
ap_reg_ppstg_exitcond_reg_5147_pp0_it20 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
ap_reg_ppstg_exitcond_reg_5147_pp0_it21 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
ap_reg_ppstg_exitcond_reg_5147_pp0_it22 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
ap_reg_ppstg_exitcond_reg_5147_pp0_it23 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
ap_reg_ppstg_exitcond_reg_5147_pp0_it24 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
ap_reg_ppstg_exitcond_reg_5147_pp0_it25 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
ap_reg_ppstg_exitcond_reg_5147_pp0_it26 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
ap_reg_ppstg_exitcond_reg_5147_pp0_it27 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
ap_reg_ppstg_exitcond_reg_5147_pp0_it28 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
ap_reg_ppstg_exitcond_reg_5147_pp0_it29 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
ap_reg_ppstg_exitcond_reg_5147_pp0_it3 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
ap_reg_ppstg_exitcond_reg_5147_pp0_it30 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
ap_reg_ppstg_exitcond_reg_5147_pp0_it31 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
ap_reg_ppstg_exitcond_reg_5147_pp0_it32 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
ap_reg_ppstg_exitcond_reg_5147_pp0_it33 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
ap_reg_ppstg_exitcond_reg_5147_pp0_it4 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
ap_reg_ppstg_exitcond_reg_5147_pp0_it5 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
ap_reg_ppstg_exitcond_reg_5147_pp0_it6 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
ap_reg_ppstg_exitcond_reg_5147_pp0_it7 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
ap_reg_ppstg_exitcond_reg_5147_pp0_it8 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
ap_reg_ppstg_exitcond_reg_5147_pp0_it9 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 <= flag_d_max2_1_reg_5959;
ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 <= ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 <= flag_d_max2_7_reg_5971;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 <= flag_d_max4_1_reg_5993;
ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 <= ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 <= flag_d_max4_5_reg_6005;
ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 <= ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 <= flag_d_min2_1_reg_5953;
ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 <= ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 <= flag_d_min2_7_reg_5965;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 <= flag_d_min4_1_reg_5987;
ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 <= ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 <= flag_d_min4_5_reg_5999;
ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 <= ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 <= flag_val_V_assign_load_1_s_reg_5417;
ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 <= ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 <= iscorner_2_i_s_reg_5949;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 <= not_or_cond10_demorgan_reg_5699;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 <= not_or_cond11_demorgan_reg_5704;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 <= not_or_cond6_demorgan_reg_5605;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 <= not_or_cond7_demorgan_reg_5610;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 <= not_or_cond8_demorgan_reg_5615;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 <= not_or_cond9_demorgan_reg_5620;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 <= not_or_cond_reg_5733;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 <= or_cond2_reg_5660;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 <= or_cond5_reg_5537;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 <= or_cond6_reg_5543;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 <= or_cond7_reg_5548;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 <= or_cond8_reg_5553;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 <= or_cond9_reg_5559;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it10 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
ap_reg_ppstg_or_cond_reg_5156_pp0_it11 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
ap_reg_ppstg_or_cond_reg_5156_pp0_it12 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
ap_reg_ppstg_or_cond_reg_5156_pp0_it13 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
ap_reg_ppstg_or_cond_reg_5156_pp0_it14 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
ap_reg_ppstg_or_cond_reg_5156_pp0_it15 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
ap_reg_ppstg_or_cond_reg_5156_pp0_it16 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
ap_reg_ppstg_or_cond_reg_5156_pp0_it17 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
ap_reg_ppstg_or_cond_reg_5156_pp0_it18 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
ap_reg_ppstg_or_cond_reg_5156_pp0_it19 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
ap_reg_ppstg_or_cond_reg_5156_pp0_it2 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
ap_reg_ppstg_or_cond_reg_5156_pp0_it20 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
ap_reg_ppstg_or_cond_reg_5156_pp0_it21 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
ap_reg_ppstg_or_cond_reg_5156_pp0_it22 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
ap_reg_ppstg_or_cond_reg_5156_pp0_it23 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
ap_reg_ppstg_or_cond_reg_5156_pp0_it24 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
ap_reg_ppstg_or_cond_reg_5156_pp0_it25 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
ap_reg_ppstg_or_cond_reg_5156_pp0_it26 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
ap_reg_ppstg_or_cond_reg_5156_pp0_it27 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
ap_reg_ppstg_or_cond_reg_5156_pp0_it28 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
ap_reg_ppstg_or_cond_reg_5156_pp0_it29 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
ap_reg_ppstg_or_cond_reg_5156_pp0_it3 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
ap_reg_ppstg_or_cond_reg_5156_pp0_it30 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
ap_reg_ppstg_or_cond_reg_5156_pp0_it31 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
ap_reg_ppstg_or_cond_reg_5156_pp0_it32 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
ap_reg_ppstg_or_cond_reg_5156_pp0_it33 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
ap_reg_ppstg_or_cond_reg_5156_pp0_it4 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
ap_reg_ppstg_or_cond_reg_5156_pp0_it5 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
ap_reg_ppstg_or_cond_reg_5156_pp0_it6 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
ap_reg_ppstg_or_cond_reg_5156_pp0_it7 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
ap_reg_ppstg_or_cond_reg_5156_pp0_it8 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
ap_reg_ppstg_or_cond_reg_5156_pp0_it9 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
ap_reg_ppstg_p_2_reg_515_pp0_it10 <= ap_reg_ppstg_p_2_reg_515_pp0_it9;
ap_reg_ppstg_p_2_reg_515_pp0_it11 <= ap_reg_ppstg_p_2_reg_515_pp0_it10;
ap_reg_ppstg_p_2_reg_515_pp0_it12 <= ap_reg_ppstg_p_2_reg_515_pp0_it11;
ap_reg_ppstg_p_2_reg_515_pp0_it13 <= ap_reg_ppstg_p_2_reg_515_pp0_it12;
ap_reg_ppstg_p_2_reg_515_pp0_it14 <= ap_reg_ppstg_p_2_reg_515_pp0_it13;
ap_reg_ppstg_p_2_reg_515_pp0_it15 <= ap_reg_ppstg_p_2_reg_515_pp0_it14;
ap_reg_ppstg_p_2_reg_515_pp0_it16 <= ap_reg_ppstg_p_2_reg_515_pp0_it15;
ap_reg_ppstg_p_2_reg_515_pp0_it17 <= ap_reg_ppstg_p_2_reg_515_pp0_it16;
ap_reg_ppstg_p_2_reg_515_pp0_it18 <= ap_reg_ppstg_p_2_reg_515_pp0_it17;
ap_reg_ppstg_p_2_reg_515_pp0_it19 <= ap_reg_ppstg_p_2_reg_515_pp0_it18;
ap_reg_ppstg_p_2_reg_515_pp0_it2 <= ap_reg_ppstg_p_2_reg_515_pp0_it1;
ap_reg_ppstg_p_2_reg_515_pp0_it20 <= ap_reg_ppstg_p_2_reg_515_pp0_it19;
ap_reg_ppstg_p_2_reg_515_pp0_it21 <= ap_reg_ppstg_p_2_reg_515_pp0_it20;
ap_reg_ppstg_p_2_reg_515_pp0_it22 <= ap_reg_ppstg_p_2_reg_515_pp0_it21;
ap_reg_ppstg_p_2_reg_515_pp0_it23 <= ap_reg_ppstg_p_2_reg_515_pp0_it22;
ap_reg_ppstg_p_2_reg_515_pp0_it24 <= ap_reg_ppstg_p_2_reg_515_pp0_it23;
ap_reg_ppstg_p_2_reg_515_pp0_it25 <= ap_reg_ppstg_p_2_reg_515_pp0_it24;
ap_reg_ppstg_p_2_reg_515_pp0_it26 <= ap_reg_ppstg_p_2_reg_515_pp0_it25;
ap_reg_ppstg_p_2_reg_515_pp0_it27 <= ap_reg_ppstg_p_2_reg_515_pp0_it26;
ap_reg_ppstg_p_2_reg_515_pp0_it28 <= ap_reg_ppstg_p_2_reg_515_pp0_it27;
ap_reg_ppstg_p_2_reg_515_pp0_it29 <= ap_reg_ppstg_p_2_reg_515_pp0_it28;
ap_reg_ppstg_p_2_reg_515_pp0_it3 <= ap_reg_ppstg_p_2_reg_515_pp0_it2;
ap_reg_ppstg_p_2_reg_515_pp0_it30 <= ap_reg_ppstg_p_2_reg_515_pp0_it29;
ap_reg_ppstg_p_2_reg_515_pp0_it31 <= ap_reg_ppstg_p_2_reg_515_pp0_it30;
ap_reg_ppstg_p_2_reg_515_pp0_it4 <= ap_reg_ppstg_p_2_reg_515_pp0_it3;
ap_reg_ppstg_p_2_reg_515_pp0_it5 <= ap_reg_ppstg_p_2_reg_515_pp0_it4;
ap_reg_ppstg_p_2_reg_515_pp0_it6 <= ap_reg_ppstg_p_2_reg_515_pp0_it5;
ap_reg_ppstg_p_2_reg_515_pp0_it7 <= ap_reg_ppstg_p_2_reg_515_pp0_it6;
ap_reg_ppstg_p_2_reg_515_pp0_it8 <= ap_reg_ppstg_p_2_reg_515_pp0_it7;
ap_reg_ppstg_p_2_reg_515_pp0_it9 <= ap_reg_ppstg_p_2_reg_515_pp0_it8;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 <= r_V_1_1_reg_5432;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 <= r_V_1_2_reg_5452;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 <= r_V_1_3_reg_5472;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 <= r_V_1_4_reg_5483;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 <= r_V_1_5_reg_5494;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 <= r_V_1_6_reg_5505;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 <= r_V_1_7_reg_5516;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 <= r_V_1_reg_5408;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 <= r_V_2_reg_5290;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 <= r_V_3_reg_5309;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 <= r_V_4_reg_5328;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 <= r_V_5_reg_5348;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 <= r_V_6_reg_5368;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 <= r_V_7_reg_5388;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
ap_reg_ppstg_r_V_reg_5252_pp0_it10 <= ap_reg_ppstg_r_V_reg_5252_pp0_it9;
ap_reg_ppstg_r_V_reg_5252_pp0_it11 <= ap_reg_ppstg_r_V_reg_5252_pp0_it10;
ap_reg_ppstg_r_V_reg_5252_pp0_it12 <= ap_reg_ppstg_r_V_reg_5252_pp0_it11;
ap_reg_ppstg_r_V_reg_5252_pp0_it13 <= ap_reg_ppstg_r_V_reg_5252_pp0_it12;
ap_reg_ppstg_r_V_reg_5252_pp0_it14 <= ap_reg_ppstg_r_V_reg_5252_pp0_it13;
ap_reg_ppstg_r_V_reg_5252_pp0_it3 <= r_V_reg_5252;
ap_reg_ppstg_r_V_reg_5252_pp0_it4 <= ap_reg_ppstg_r_V_reg_5252_pp0_it3;
ap_reg_ppstg_r_V_reg_5252_pp0_it5 <= ap_reg_ppstg_r_V_reg_5252_pp0_it4;
ap_reg_ppstg_r_V_reg_5252_pp0_it6 <= ap_reg_ppstg_r_V_reg_5252_pp0_it5;
ap_reg_ppstg_r_V_reg_5252_pp0_it7 <= ap_reg_ppstg_r_V_reg_5252_pp0_it6;
ap_reg_ppstg_r_V_reg_5252_pp0_it8 <= ap_reg_ppstg_r_V_reg_5252_pp0_it7;
ap_reg_ppstg_r_V_reg_5252_pp0_it9 <= ap_reg_ppstg_r_V_reg_5252_pp0_it8;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 <= r_V_s_reg_5271;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
ap_reg_ppstg_tmp11_reg_5934_pp0_it11 <= tmp11_reg_5934;
ap_reg_ppstg_tmp12_reg_5883_pp0_it9 <= tmp12_reg_5883;
ap_reg_ppstg_tmp3_reg_5878_pp0_it10 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
ap_reg_ppstg_tmp3_reg_5878_pp0_it11 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
ap_reg_ppstg_tmp3_reg_5878_pp0_it9 <= tmp3_reg_5878;
ap_reg_ppstg_tmp5_reg_5781_pp0_it6 <= tmp5_reg_5781;
ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 <= tmp_200_3_reg_5977;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 <= tmp_210_2_reg_6169;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 <= tmp_210_4_reg_6179;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 <= tmp_210_7_reg_6139;
ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 <= tmp_210_9_reg_6149;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 <= tmp_210_s_reg_6159;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 <= tmp_213_3_reg_5982;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 <= tmp_225_2_reg_6174;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 <= tmp_225_4_reg_6184;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 <= tmp_225_7_reg_6144;
ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 <= tmp_225_9_reg_6154;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 <= tmp_225_s_reg_6164;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 <= tmp_39_reg_5532;
ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 <= ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 <= tmp_53_reg_6719;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
ap_reg_ppstg_exitcond_reg_5147_pp0_it1 <= exitcond_reg_5147;
ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 <= or_cond1_reg_5197;
ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 <= or_cond4_reg_5201;
ap_reg_ppstg_or_cond_reg_5156_pp0_it1 <= or_cond_reg_5156;
ap_reg_ppstg_p_2_reg_515_pp0_it1 <= p_2_reg_515;
exitcond_reg_5147 <= exitcond_fu_846_p2;
win_val_0_V_2_1_reg_5205 <= win_val_0_V_2_fu_172;
win_val_1_V_4_3_reg_5210 <= win_val_1_V_4_fu_204;
win_val_2_V_5_3_reg_5215 <= win_val_2_V_5_fu_236;
win_val_3_V_2_3_reg_5220 <= win_val_3_V_2_fu_252;
win_val_4_V_5_3_reg_5225 <= win_val_4_V_5_fu_292;
win_val_5_V_4_3_reg_5230 <= win_val_5_V_4_fu_312;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it15))) begin
b0_reg_6093 <= b0_fu_3473_p3;
p_a_0_flag_d_assign_load_5_reg_6077 <= p_a_0_flag_d_assign_load_5_fu_3434_p3;
tmp_47_reg_6083 <= tmp_47_fu_3447_p3;
tmp_48_reg_6088 <= tmp_48_fu_3454_p1;
tmp_71_reg_6099 <= tmp_71_fu_3486_p3;
tmp_81_reg_6104 <= tmp_81_fu_3493_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))) begin
b0_tmp_s_reg_6200 <= b0_tmp_s_fu_3680_p3;
p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 <= p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
tmp_209_1_reg_6195 <= tmp_209_1_fu_3666_p2;
tmp_221_1_reg_6206 <= tmp_221_1_fu_3686_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it31))) begin
core_buf_val_0_V_addr_reg_6702 <= tmp_14_fu_4577_p1;
core_buf_val_1_V_addr_reg_6708 <= tmp_14_fu_4577_p1;
tmp_53_reg_6719 <= tmp_53_fu_4600_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) begin
core_buf_val_0_V_load_reg_6724 <= core_buf_val_0_V_q0;
core_buf_val_1_V_load_reg_6729 <= core_buf_val_1_V_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
core_win_val_0_V_0_fu_136[0] <= core_win_val_0_V_1_fu_140[0];
core_win_val_0_V_0_fu_136[1] <= core_win_val_0_V_1_fu_140[1];
core_win_val_0_V_0_fu_136[2] <= core_win_val_0_V_1_fu_140[2];
core_win_val_0_V_0_fu_136[3] <= core_win_val_0_V_1_fu_140[3];
core_win_val_0_V_0_fu_136[4] <= core_win_val_0_V_1_fu_140[4];
core_win_val_0_V_0_fu_136[5] <= core_win_val_0_V_1_fu_140[5];
core_win_val_0_V_0_fu_136[6] <= core_win_val_0_V_1_fu_140[6];
core_win_val_0_V_0_fu_136[7] <= core_win_val_0_V_1_fu_140[7];
core_win_val_0_V_1_fu_140[0] <= core_win_val_0_V_2_fu_4620_p1[0];
core_win_val_0_V_1_fu_140[1] <= core_win_val_0_V_2_fu_4620_p1[1];
core_win_val_0_V_1_fu_140[2] <= core_win_val_0_V_2_fu_4620_p1[2];
core_win_val_0_V_1_fu_140[3] <= core_win_val_0_V_2_fu_4620_p1[3];
core_win_val_0_V_1_fu_140[4] <= core_win_val_0_V_2_fu_4620_p1[4];
core_win_val_0_V_1_fu_140[5] <= core_win_val_0_V_2_fu_4620_p1[5];
core_win_val_0_V_1_fu_140[6] <= core_win_val_0_V_2_fu_4620_p1[6];
core_win_val_0_V_1_fu_140[7] <= core_win_val_0_V_2_fu_4620_p1[7];
core_win_val_1_V_0_fu_148[0] <= core_win_val_1_V_1_fu_152[0];
core_win_val_1_V_0_fu_148[1] <= core_win_val_1_V_1_fu_152[1];
core_win_val_1_V_0_fu_148[2] <= core_win_val_1_V_1_fu_152[2];
core_win_val_1_V_0_fu_148[3] <= core_win_val_1_V_1_fu_152[3];
core_win_val_1_V_0_fu_148[4] <= core_win_val_1_V_1_fu_152[4];
core_win_val_1_V_0_fu_148[5] <= core_win_val_1_V_1_fu_152[5];
core_win_val_1_V_0_fu_148[6] <= core_win_val_1_V_1_fu_152[6];
core_win_val_1_V_0_fu_148[7] <= core_win_val_1_V_1_fu_152[7];
core_win_val_1_V_1_fu_152[0] <= core_win_val_1_V_2_fu_4623_p1[0];
core_win_val_1_V_1_fu_152[1] <= core_win_val_1_V_2_fu_4623_p1[1];
core_win_val_1_V_1_fu_152[2] <= core_win_val_1_V_2_fu_4623_p1[2];
core_win_val_1_V_1_fu_152[3] <= core_win_val_1_V_2_fu_4623_p1[3];
core_win_val_1_V_1_fu_152[4] <= core_win_val_1_V_2_fu_4623_p1[4];
core_win_val_1_V_1_fu_152[5] <= core_win_val_1_V_2_fu_4623_p1[5];
core_win_val_1_V_1_fu_152[6] <= core_win_val_1_V_2_fu_4623_p1[6];
core_win_val_1_V_1_fu_152[7] <= core_win_val_1_V_2_fu_4623_p1[7];
core_win_val_2_V_0_fu_160[0] <= core_win_val_2_V_1_fu_164[0];
core_win_val_2_V_0_fu_160[1] <= core_win_val_2_V_1_fu_164[1];
core_win_val_2_V_0_fu_160[2] <= core_win_val_2_V_1_fu_164[2];
core_win_val_2_V_0_fu_160[3] <= core_win_val_2_V_1_fu_164[3];
core_win_val_2_V_0_fu_160[4] <= core_win_val_2_V_1_fu_164[4];
core_win_val_2_V_0_fu_160[5] <= core_win_val_2_V_1_fu_164[5];
core_win_val_2_V_0_fu_160[6] <= core_win_val_2_V_1_fu_164[6];
core_win_val_2_V_0_fu_160[7] <= core_win_val_2_V_1_fu_164[7];
core_win_val_2_V_1_fu_164[0] <= core_win_val_2_V_1_2_fu_4643_p1[0];
core_win_val_2_V_1_fu_164[1] <= core_win_val_2_V_1_2_fu_4643_p1[1];
core_win_val_2_V_1_fu_164[2] <= core_win_val_2_V_1_2_fu_4643_p1[2];
core_win_val_2_V_1_fu_164[3] <= core_win_val_2_V_1_2_fu_4643_p1[3];
core_win_val_2_V_1_fu_164[4] <= core_win_val_2_V_1_2_fu_4643_p1[4];
core_win_val_2_V_1_fu_164[5] <= core_win_val_2_V_1_2_fu_4643_p1[5];
core_win_val_2_V_1_fu_164[6] <= core_win_val_2_V_1_2_fu_4643_p1[6];
core_win_val_2_V_1_fu_164[7] <= core_win_val_2_V_1_2_fu_4643_p1[7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it2) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it2))) begin
count_1_i_0_op_op87_op_reg_5590[0] <= count_1_i_0_op_op87_op_fu_1848_p3[0];
flag_val_V_assign_load_1_13_reg_5527 <= flag_val_V_assign_load_1_13_fu_1726_p3;
flag_val_V_assign_load_1_s_reg_5417 <= flag_val_V_assign_load_1_s_fu_1521_p3;
not_or_cond6_demorgan_reg_5605 <= not_or_cond6_demorgan_fu_1870_p2;
not_or_cond7_demorgan_reg_5610 <= not_or_cond7_demorgan_fu_1876_p2;
not_or_cond8_demorgan_reg_5615 <= not_or_cond8_demorgan_fu_1882_p2;
not_or_cond9_demorgan_reg_5620 <= not_or_cond9_demorgan_fu_1888_p2;
or_cond5_reg_5537 <= or_cond5_fu_1746_p2;
or_cond6_reg_5543 <= or_cond6_fu_1764_p2;
or_cond7_reg_5548 <= or_cond7_fu_1782_p2;
or_cond8_reg_5553 <= or_cond8_fu_1800_p2;
or_cond9_reg_5559 <= or_cond9_fu_1818_p2;
phitmp3_reg_5422 <= phitmp3_fu_1539_p3;
phitmp43_op_op_cast_cast_cast_reg_5595[0] <= phitmp43_op_op_cast_cast_cast_fu_1856_p3[0];
r_V_1_1_reg_5432 <= r_V_1_1_fu_1557_p2;
r_V_1_2_reg_5452 <= r_V_1_2_fu_1584_p2;
r_V_1_3_reg_5472 <= r_V_1_3_fu_1611_p2;
r_V_1_4_reg_5483 <= r_V_1_4_fu_1626_p2;
r_V_1_5_reg_5494 <= r_V_1_5_fu_1654_p2;
r_V_1_6_reg_5505 <= r_V_1_6_fu_1682_p2;
r_V_1_7_reg_5516 <= r_V_1_7_fu_1710_p2;
r_V_1_reg_5408 <= r_V_1_fu_1516_p2;
tmp_181_5_not_reg_5566 <= tmp_181_5_not_fu_1824_p2;
tmp_181_6_not_reg_5578 <= tmp_181_6_not_fu_1836_p2;
tmp_182_1_reg_5441 <= tmp_182_1_fu_1568_p2;
tmp_182_2_reg_5461 <= tmp_182_2_fu_1595_p2;
tmp_183_5_reg_5572 <= tmp_183_5_fu_1830_p2;
tmp_183_6_reg_5584 <= tmp_183_6_fu_1842_p2;
tmp_184_1_reg_5447 <= tmp_184_1_fu_1574_p2;
tmp_184_2_reg_5467 <= tmp_184_2_fu_1601_p2;
tmp_23_reg_5427 <= tmp_23_fu_1547_p2;
tmp_39_reg_5532 <= tmp_39_fu_1740_p2;
tmp_40_reg_5600 <= tmp_40_fu_1864_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it7) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it7))) begin
count_1_i_12_reg_5872 <= count_1_i_12_fu_2678_p3;
count_4_reg_5867 <= count_4_fu_2666_p2;
p_iscorner_0_i_7_reg_5862 <= p_iscorner_0_i_7_fu_2653_p2;
tmp12_reg_5883 <= tmp12_fu_2694_p2;
tmp3_reg_5878 <= tmp3_fu_2689_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it8) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it8))) begin
count_1_i_14_reg_5898 <= count_1_i_14_fu_2755_p3;
p_iscorner_0_i_11_reg_5888 <= p_iscorner_0_i_11_fu_2725_p2;
tmp13_reg_5904 <= tmp13_fu_2762_p2;
tmp_185_13_reg_5893 <= tmp_185_13_fu_2743_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it5) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it5))) begin
count_1_i_3_reg_5806 <= count_1_i_3_fu_2476_p3;
not_or_cond13_demorgan_reg_5801 <= not_or_cond13_demorgan_fu_2470_p2;
not_or_cond14_demorgan_reg_5816 <= not_or_cond14_demorgan_fu_2500_p2;
or_cond17_reg_5811 <= or_cond17_fu_2494_p2;
or_cond18_reg_5821 <= or_cond18_fu_2511_p2;
p_iscorner_0_i_1_reg_5786 <= p_iscorner_0_i_1_fu_2391_p2;
p_iscorner_0_i_2_reg_5791 <= p_iscorner_0_i_2_fu_2435_p2;
tmp6_reg_5827 <= tmp6_fu_2516_p2;
tmp_185_3_reg_5796 <= tmp_185_3_fu_2464_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it3) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it3))) begin
count_1_i_6_reg_5665 <= count_1_i_6_fu_2036_p3;
count_1_i_7_reg_5675 <= count_1_i_7_fu_2061_p3;
flag_val_V_assign_load_1_3_reg_5625 <= flag_val_V_assign_load_1_3_fu_1930_p3;
flag_val_V_assign_load_1_5_reg_5631 <= flag_val_V_assign_load_1_5_fu_1962_p3;
not_or_cond10_demorgan_reg_5699 <= not_or_cond10_demorgan_fu_2093_p2;
not_or_cond11_demorgan_reg_5704 <= not_or_cond11_demorgan_fu_2097_p2;
or_cond10_reg_5670 <= or_cond10_fu_2055_p2;
or_cond11_reg_5681 <= or_cond11_fu_2075_p2;
or_cond2_reg_5660 <= or_cond2_fu_1990_p2;
tmp_181_9_reg_5687 <= tmp_181_9_fu_2081_p2;
tmp_182_4_reg_5638 <= tmp_182_4_fu_1970_p2;
tmp_182_5_reg_5649 <= tmp_182_5_fu_1980_p2;
tmp_183_9_reg_5693 <= tmp_183_9_fu_2087_p2;
tmp_184_4_reg_5644 <= tmp_184_4_fu_1975_p2;
tmp_184_5_reg_5655 <= tmp_184_5_fu_1985_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it4))) begin
count_1_i_9_reg_5743 <= count_1_i_9_fu_2257_p3;
count_1_i_s_reg_5753 <= count_1_i_s_fu_2292_p3;
flag_val_V_assign_load_1_10_reg_5709 <= flag_val_V_assign_load_1_10_fu_2131_p3;
flag_val_V_assign_load_1_12_reg_5715 <= flag_val_V_assign_load_1_12_fu_2163_p3;
not_or_cond3_demorgan_reg_5748 <= not_or_cond3_demorgan_fu_2286_p2;
not_or_cond4_demorgan_reg_5764 <= not_or_cond4_demorgan_fu_2316_p2;
not_or_cond_reg_5733 <= not_or_cond_fu_2186_p2;
or_cond14_reg_5759 <= or_cond14_fu_2310_p2;
p_iscorner_0_i_9_reg_5738 <= p_iscorner_0_i_9_fu_2251_p2;
tmp5_reg_5781 <= tmp5_fu_2334_p2;
tmp_181_2_reg_5769 <= tmp_181_2_fu_2322_p2;
tmp_182_7_reg_5722 <= tmp_182_7_fu_2171_p2;
tmp_183_10_reg_5775 <= tmp_183_10_fu_2328_p2;
tmp_184_7_reg_5728 <= tmp_184_7_fu_2176_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it6))) begin
count_3_reg_5837 <= count_3_fu_2594_p2;
p_iscorner_0_i_5_reg_5832 <= p_iscorner_0_i_5_fu_2581_p2;
tmp4_reg_5847 <= tmp4_fu_2606_p2;
tmp8_reg_5852 <= tmp8_fu_2610_p2;
tmp9_reg_5857 <= tmp9_fu_2614_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26))) begin
flag_d_assign_11_reg_6539 <= flag_d_assign_11_fu_4289_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28))) begin
flag_d_assign_13_reg_6613 <= flag_d_assign_13_fu_4417_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16))) begin
flag_d_assign_2_reg_6109 <= flag_d_assign_2_fu_3497_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18))) begin
flag_d_assign_4_reg_6243 <= flag_d_assign_4_fu_3777_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20))) begin
flag_d_assign_6_reg_6317 <= flag_d_assign_6_fu_3905_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22))) begin
flag_d_assign_8_reg_6391 <= flag_d_assign_8_fu_4033_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14))) begin
flag_d_assign_reg_6011 <= flag_d_assign_fu_3143_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24))) begin
flag_d_assign_s_reg_6465 <= flag_d_assign_s_fu_4161_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949))) begin
flag_d_max2_1_reg_5959 <= grp_image_filter_reg_int_s_fu_547_ap_return;
flag_d_max2_7_reg_5971 <= grp_image_filter_reg_int_s_fu_577_ap_return;
flag_d_min2_1_reg_5953 <= grp_image_filter_reg_int_s_fu_542_ap_return;
flag_d_min2_7_reg_5965 <= grp_image_filter_reg_int_s_fu_572_ap_return;
tmp_200_3_reg_5977 <= tmp_200_3_fu_3031_p3;
tmp_213_3_reg_5982 <= tmp_213_3_fu_3045_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) begin
flag_d_max2_9_reg_6023 <= grp_image_filter_reg_int_s_fu_607_ap_return;
flag_d_max8_1_reg_6036 <= grp_image_filter_reg_int_s_fu_617_ap_return;
flag_d_min2_9_reg_6017 <= grp_image_filter_reg_int_s_fu_602_ap_return;
flag_d_min8_1_reg_6029 <= grp_image_filter_reg_int_s_fu_612_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) begin
flag_d_max4_1_reg_5993 <= grp_image_filter_reg_int_s_fu_587_ap_return;
flag_d_max4_5_reg_6005 <= grp_image_filter_reg_int_s_fu_597_ap_return;
flag_d_min4_1_reg_5987 <= grp_image_filter_reg_int_s_fu_582_ap_return;
flag_d_min4_5_reg_5999 <= grp_image_filter_reg_int_s_fu_592_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) begin
flag_d_max4_3_reg_6059 <= grp_image_filter_reg_int_s_fu_657_ap_return;
flag_d_max4_7_reg_6071 <= grp_image_filter_reg_int_s_fu_667_ap_return;
flag_d_min4_3_reg_6053 <= grp_image_filter_reg_int_s_fu_652_ap_return;
flag_d_min4_7_reg_6065 <= grp_image_filter_reg_int_s_fu_662_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))) begin
flag_d_max8_3_reg_6122 <= grp_image_filter_reg_int_s_fu_717_ap_return;
flag_d_min8_3_reg_6115 <= grp_image_filter_reg_int_s_fu_712_ap_return;
tmp_210_2_reg_6169 <= tmp_210_2_fu_3609_p3;
tmp_210_4_reg_6179 <= tmp_210_4_fu_3633_p3;
tmp_210_5_reg_6129 <= tmp_210_5_fu_3505_p3;
tmp_210_7_reg_6139 <= tmp_210_7_fu_3529_p3;
tmp_210_9_reg_6149 <= tmp_210_9_fu_3554_p3;
tmp_210_s_reg_6159 <= tmp_210_s_fu_3582_p3;
tmp_225_2_reg_6174 <= tmp_225_2_fu_3621_p3;
tmp_225_4_reg_6184 <= tmp_225_4_fu_3645_p3;
tmp_225_5_reg_6134 <= tmp_225_5_fu_3517_p3;
tmp_225_7_reg_6144 <= tmp_225_7_fu_3541_p3;
tmp_225_9_reg_6154 <= tmp_225_9_fu_3568_p3;
tmp_225_s_reg_6164 <= tmp_225_s_fu_3596_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) begin
flag_d_max8_5_reg_6256 <= grp_image_filter_reg_int_s_fu_727_ap_return;
flag_d_min8_5_reg_6249 <= grp_image_filter_reg_int_s_fu_722_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) begin
flag_d_max8_7_reg_6330 <= grp_image_filter_reg_int_s_fu_737_ap_return;
flag_d_min8_7_reg_6323 <= grp_image_filter_reg_int_s_fu_732_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) begin
flag_d_max8_9_reg_6404 <= grp_image_filter_reg_int_s_fu_747_ap_return;
flag_d_min8_9_reg_6397 <= grp_image_filter_reg_int_s_fu_742_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_5122 <= i_V_fu_807_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
icmp_reg_5142 <= icmp_fu_840_p2;
tmp_7_reg_5127 <= tmp_7_fu_813_p2;
tmp_8_reg_5132 <= tmp_8_fu_818_p2;
tmp_9_reg_5137 <= tmp_9_fu_824_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11))) begin
iscorner_2_i_s_reg_5949 <= iscorner_2_i_s_fu_2870_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
j_V_reg_5151 <= j_V_fu_851_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == exitcond_fu_846_p2) & ~(ap_const_lv1_0 == or_cond_fu_862_p2))) begin
k_buf_val_0_V_addr_reg_5161 <= tmp_12_fu_867_p1;
k_buf_val_1_V_addr_reg_5167 <= tmp_12_fu_867_p1;
k_buf_val_2_V_addr_reg_5173 <= tmp_12_fu_867_p1;
k_buf_val_3_V_addr_reg_5179 <= tmp_12_fu_867_p1;
k_buf_val_4_V_addr_reg_5185 <= tmp_12_fu_867_p1;
k_buf_val_5_V_addr_reg_5191 <= tmp_12_fu_867_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it1) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it1))) begin
lhs_V_reg_5240[0] <= lhs_V_fu_1252_p1[0];
lhs_V_reg_5240[1] <= lhs_V_fu_1252_p1[1];
lhs_V_reg_5240[2] <= lhs_V_fu_1252_p1[2];
lhs_V_reg_5240[3] <= lhs_V_fu_1252_p1[3];
lhs_V_reg_5240[4] <= lhs_V_fu_1252_p1[4];
lhs_V_reg_5240[5] <= lhs_V_fu_1252_p1[5];
lhs_V_reg_5240[6] <= lhs_V_fu_1252_p1[6];
lhs_V_reg_5240[7] <= lhs_V_fu_1252_p1[7];
phitmp1_reg_5261 <= phitmp1_fu_1278_p3;
phitmp_1_reg_5280 <= phitmp_1_fu_1314_p3;
phitmp_2_reg_5299 <= phitmp_2_fu_1350_p3;
phitmp_3_reg_5318 <= phitmp_3_fu_1386_p3;
r_V_2_reg_5290 <= r_V_2_fu_1332_p2;
r_V_3_reg_5309 <= r_V_3_fu_1368_p2;
r_V_4_reg_5328 <= r_V_4_fu_1404_p2;
r_V_5_reg_5348 <= r_V_5_fu_1426_p2;
r_V_6_reg_5368 <= r_V_6_fu_1448_p2;
r_V_7_reg_5388 <= r_V_7_fu_1470_p2;
r_V_reg_5252 <= r_V_fu_1260_p2;
r_V_s_reg_5271 <= r_V_s_fu_1296_p2;
tmp_176_4_reg_5337 <= tmp_176_4_fu_1410_p2;
tmp_176_5_reg_5357 <= tmp_176_5_fu_1432_p2;
tmp_176_6_reg_5377 <= tmp_176_6_fu_1454_p2;
tmp_176_7_reg_5397 <= tmp_176_7_fu_1476_p2;
tmp_177_4_reg_5343 <= tmp_177_4_fu_1416_p2;
tmp_177_5_reg_5363 <= tmp_177_5_fu_1438_p2;
tmp_177_6_reg_5383 <= tmp_177_6_fu_1460_p2;
tmp_177_7_reg_5403 <= tmp_177_7_fu_1482_p2;
tmp_20_reg_5266 <= tmp_20_fu_1286_p2;
tmp_24_reg_5285 <= tmp_24_fu_1322_p2;
tmp_27_reg_5304 <= tmp_27_fu_1358_p2;
tmp_29_reg_5323 <= tmp_29_fu_1394_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it9) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it9))) begin
not_or_cond11_reg_5919 <= not_or_cond11_fu_2817_p2;
p_iscorner_0_i_13_reg_5909 <= p_iscorner_0_i_13_fu_2787_p2;
tmp11_reg_5934 <= tmp11_fu_2833_p2;
tmp15_reg_5939 <= tmp15_fu_2837_p2;
tmp2_reg_5929 <= tmp2_fu_2828_p2;
tmp_185_15_reg_5914 <= tmp_185_15_fu_2805_p2;
tmp_185_16_reg_5924 <= tmp_185_16_fu_2822_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == exitcond_fu_846_p2))) begin
or_cond1_reg_5197 <= or_cond1_fu_883_p2;
or_cond4_reg_5201 <= or_cond4_fu_904_p2;
or_cond_reg_5156 <= or_cond_fu_862_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond5_reg_5537_pp0_it6))) begin
phitmp8_reg_5842 <= phitmp8_fu_2600_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it10) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it10))) begin
tmp14_reg_5944 <= tmp14_fu_2861_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
tmp19_reg_6739 <= tmp19_fu_4701_p2;
tmp20_reg_6744 <= tmp20_fu_4712_p2;
tmp23_reg_6749 <= tmp23_fu_4723_p2;
tmp25_reg_6754 <= tmp25_fu_4735_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31))) begin
tmp_100_v_reg_6714 <= tmp_100_v_fu_4593_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_180)) begin
tmp_15_reg_5103 <= tmp_15_fu_786_p1;
tmp_5_reg_5113 <= tmp_5_fu_796_p2;
tmp_reg_5098 <= tmp_fu_782_p1;
tmp_s_reg_5108 <= tmp_s_fu_790_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) begin
tmp_211_1_reg_6545 <= grp_image_filter_reg_int_s_fu_762_ap_return;
tmp_226_1_reg_6552 <= grp_image_filter_reg_int_s_fu_767_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) begin
tmp_211_2_reg_6619 <= grp_image_filter_reg_int_s_fu_772_ap_return;
tmp_226_2_reg_6626 <= grp_image_filter_reg_int_s_fu_777_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) begin
tmp_211_s_reg_6471 <= grp_image_filter_reg_int_s_fu_752_ap_return;
tmp_226_s_reg_6478 <= grp_image_filter_reg_int_s_fu_757_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) begin
tmp_43_reg_6043 <= tmp_43_fu_3262_p2;
tmp_67_reg_6048 <= tmp_67_fu_3268_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it1) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it1))) begin
win_val_0_V_2_3_fu_168 <= win_val_0_V_2_1_reg_5205;
win_val_1_V_1_3_fu_188 <= win_val_1_V_1_fu_192;
win_val_1_V_1_fu_192 <= win_val_1_V_2_fu_196;
win_val_1_V_2_fu_196 <= win_val_1_V_3_fu_200;
win_val_1_V_3_fu_200 <= win_val_1_V_4_3_reg_5210;
win_val_2_V_0_3_fu_212 <= win_val_2_V_0_fu_216;
win_val_2_V_0_fu_216 <= win_val_2_V_1_fu_220;
win_val_2_V_1_fu_220 <= win_val_2_V_2_fu_224;
win_val_2_V_2_fu_224 <= win_val_2_V_3_fu_228;
win_val_2_V_3_fu_228 <= win_val_2_V_4_fu_232;
win_val_2_V_4_fu_232 <= win_val_2_V_5_3_reg_5215;
win_val_3_V_0_3_fu_240 <= win_val_3_V_0_fu_244;
win_val_3_V_0_fu_244 <= win_val_3_V_1_fu_248;
win_val_3_V_1_fu_248 <= win_val_3_V_2_3_reg_5220;
win_val_4_V_0_3_fu_268 <= win_val_4_V_0_fu_272;
win_val_4_V_0_fu_272 <= win_val_4_V_1_fu_276;
win_val_4_V_1_fu_276 <= win_val_4_V_2_fu_280;
win_val_4_V_2_fu_280 <= win_val_4_V_3_fu_284;
win_val_4_V_3_fu_284 <= win_val_4_V_4_fu_288;
win_val_4_V_4_fu_288 <= win_val_4_V_5_3_reg_5225;
win_val_5_V_1_3_fu_296 <= win_val_5_V_1_fu_300;
win_val_5_V_1_fu_300 <= win_val_5_V_2_fu_304;
win_val_5_V_2_fu_304 <= win_val_5_V_3_fu_308;
win_val_5_V_3_fu_308 <= win_val_5_V_4_3_reg_5230;
win_val_6_V_2_3_fu_320 <= win_val_6_V_2_fu_324;
win_val_6_V_2_fu_324 <= win_val_6_V_2_2_reg_5235;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
win_val_0_V_2_fu_172 <= win_val_0_V_3_fu_176;
win_val_0_V_3_fu_176 <= win_val_0_V_4_fu_180;
win_val_0_V_4_fu_180 <= win_val_0_V_5_fu_184;
win_val_0_V_5_fu_184 <= k_buf_val_0_V_q0;
win_val_1_V_4_fu_204 <= win_val_1_V_5_fu_208;
win_val_1_V_5_fu_208 <= k_buf_val_1_V_q0;
win_val_2_V_5_fu_236 <= k_buf_val_2_V_q0;
win_val_3_V_2_fu_252 <= win_val_3_V_3_fu_256;
win_val_3_V_3_fu_256 <= win_val_3_V_4_fu_260;
win_val_3_V_4_fu_260 <= win_val_3_V_5_fu_264;
win_val_3_V_5_fu_264 <= k_buf_val_3_V_q0;
win_val_4_V_5_fu_292 <= k_buf_val_4_V_q0;
win_val_5_V_4_fu_312 <= win_val_5_V_5_fu_316;
win_val_5_V_5_fu_316 <= k_buf_val_5_V_q0;
win_val_6_V_3_fu_156 <= win_val_6_V_4_fu_144;
win_val_6_V_4_fu_144 <= win_val_6_V_5_fu_132;
win_val_6_V_5_fu_132 <= p_src_data_stream_V_dout;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
win_val_6_V_2_2_reg_5235 <= win_val_6_V_3_fu_156;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond1_fu_802_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond1_fu_802_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_48)
begin
if (ap_sig_bdd_48) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_196)
begin
if (ap_sig_bdd_196) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st39_fsm_3 assign process. ///
always @ (ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) begin
ap_sig_cseq_ST_st39_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st39_fsm_3 = ap_const_logic_0;
end
end
/// core_buf_val_0_V_ce0 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it32 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
core_buf_val_0_V_ce0 = ap_const_logic_1;
end else begin
core_buf_val_0_V_ce0 = ap_const_logic_0;
end
end
/// core_buf_val_0_V_ce1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
core_buf_val_0_V_ce1 = ap_const_logic_1;
end else begin
core_buf_val_0_V_ce1 = ap_const_logic_0;
end
end
/// core_buf_val_0_V_we1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it32)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) begin
core_buf_val_0_V_we1 = ap_const_logic_1;
end else begin
core_buf_val_0_V_we1 = ap_const_logic_0;
end
end
/// core_buf_val_1_V_ce0 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it32 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
core_buf_val_1_V_ce0 = ap_const_logic_1;
end else begin
core_buf_val_1_V_ce0 = ap_const_logic_0;
end
end
/// core_buf_val_1_V_ce1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
core_buf_val_1_V_ce1 = ap_const_logic_1;
end else begin
core_buf_val_1_V_ce1 = ap_const_logic_0;
end
end
/// core_buf_val_1_V_we1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it33)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
core_buf_val_1_V_we1 = ap_const_logic_1;
end else begin
core_buf_val_1_V_we1 = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_542_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_542_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_542_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_547_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_547_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_547_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_552_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_552_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_552_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_557_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_557_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_557_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_562_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_562_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_562_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_567_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_567_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_567_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_572_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_572_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_572_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_577_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
grp_image_filter_reg_int_s_fu_577_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_577_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_582_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
grp_image_filter_reg_int_s_fu_582_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_582_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_587_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
grp_image_filter_reg_int_s_fu_587_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_587_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_592_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
grp_image_filter_reg_int_s_fu_592_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_592_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_597_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
grp_image_filter_reg_int_s_fu_597_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_597_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_602_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
grp_image_filter_reg_int_s_fu_602_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_602_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_607_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
grp_image_filter_reg_int_s_fu_607_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_607_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_612_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
grp_image_filter_reg_int_s_fu_612_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_612_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_617_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
grp_image_filter_reg_int_s_fu_617_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_617_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_622_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_622_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_622_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_627_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_627_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_627_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_632_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_632_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_632_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_637_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_637_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_637_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_642_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_642_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_642_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_647_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_647_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_647_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_652_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_652_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_652_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_657_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_657_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_657_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_662_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_662_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_662_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_667_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
grp_image_filter_reg_int_s_fu_667_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_667_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_672_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_672_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_672_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_677_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_677_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_677_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_682_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_682_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_682_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_687_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_687_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_687_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_692_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_692_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_692_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_697_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_697_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_697_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_702_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_702_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_702_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_707_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_707_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_707_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_712_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_712_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_712_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_717_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
grp_image_filter_reg_int_s_fu_717_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_717_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_722_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it17 or ap_reg_ppstg_exitcond_reg_5147_pp0_it18 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))))) begin
grp_image_filter_reg_int_s_fu_722_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_722_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_727_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it17 or ap_reg_ppstg_exitcond_reg_5147_pp0_it18 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))))) begin
grp_image_filter_reg_int_s_fu_727_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_727_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_732_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it19 or ap_reg_ppstg_exitcond_reg_5147_pp0_it20 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))))) begin
grp_image_filter_reg_int_s_fu_732_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_732_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_737_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it19 or ap_reg_ppstg_exitcond_reg_5147_pp0_it20 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))))) begin
grp_image_filter_reg_int_s_fu_737_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_737_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_742_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it21 or ap_reg_ppstg_exitcond_reg_5147_pp0_it22 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))))) begin
grp_image_filter_reg_int_s_fu_742_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_742_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_747_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it21 or ap_reg_ppstg_exitcond_reg_5147_pp0_it22 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))))) begin
grp_image_filter_reg_int_s_fu_747_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_747_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_752_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it23 or ap_reg_ppstg_exitcond_reg_5147_pp0_it24 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))))) begin
grp_image_filter_reg_int_s_fu_752_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_752_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_757_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it23 or ap_reg_ppstg_exitcond_reg_5147_pp0_it24 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))))) begin
grp_image_filter_reg_int_s_fu_757_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_757_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_762_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it25 or ap_reg_ppstg_exitcond_reg_5147_pp0_it26 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))))) begin
grp_image_filter_reg_int_s_fu_762_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_762_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_767_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it25 or ap_reg_ppstg_exitcond_reg_5147_pp0_it26 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))))) begin
grp_image_filter_reg_int_s_fu_767_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_767_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_772_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it27 or ap_reg_ppstg_exitcond_reg_5147_pp0_it28 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))))) begin
grp_image_filter_reg_int_s_fu_772_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_772_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_reg_int_s_fu_777_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it27 or ap_reg_ppstg_exitcond_reg_5147_pp0_it28 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))))) begin
grp_image_filter_reg_int_s_fu_777_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_reg_int_s_fu_777_ap_ce = ap_const_logic_0;
end
end
/// k_buf_val_0_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_0_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_0_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_0_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_0_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_0_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_0_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_0_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_0_V_we1 = ap_const_logic_0;
end
end
/// k_buf_val_1_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_1_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_1_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_1_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_1_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_1_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_1_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_1_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_1_V_we1 = ap_const_logic_0;
end
end
/// k_buf_val_2_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_2_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_2_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_2_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_2_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_2_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_2_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_2_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_2_V_we1 = ap_const_logic_0;
end
end
/// k_buf_val_3_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_3_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_3_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_3_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_3_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_3_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_3_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_3_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_3_V_we1 = ap_const_logic_0;
end
end
/// k_buf_val_4_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_4_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_4_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_4_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_4_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_4_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_4_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_4_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_4_V_we1 = ap_const_logic_0;
end
end
/// k_buf_val_5_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_5_V_ce0 = ap_const_logic_1;
end else begin
k_buf_val_5_V_ce0 = ap_const_logic_0;
end
end
/// k_buf_val_5_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_5_V_ce1 = ap_const_logic_1;
end else begin
k_buf_val_5_V_ce1 = ap_const_logic_0;
end
end
/// k_buf_val_5_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
k_buf_val_5_V_we1 = ap_const_logic_1;
end else begin
k_buf_val_5_V_we1 = ap_const_logic_0;
end
end
/// p_2_phi_fu_519_p4 assign process. ///
always @ (p_2_reg_515 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or ap_reg_ppiten_pp0_it1 or j_V_reg_5151)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
p_2_phi_fu_519_p4 = j_V_reg_5151;
end else begin
p_2_phi_fu_519_p4 = p_2_reg_515;
end
end
/// p_mask_data_stream_V_write assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_lv1_0 == ap_reg_ppstg_or_cond4_reg_5201_pp0_it34) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
p_mask_data_stream_V_write = ap_const_logic_1;
end else begin
p_mask_data_stream_V_write = ap_const_logic_0;
end
end
/// p_src_data_stream_V_read assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
p_src_data_stream_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_sig_bdd_180 or exitcond1_fu_802_p2)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_180) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(ap_const_lv1_0 == exitcond1_fu_802_p2)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33))) begin
ap_NS_fsm = ap_ST_st39_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st39_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign a0_2_cast_fu_3908_p1 = a0_2_reg_6285;
assign a0_2_fu_3841_p3 = ((tmp_217_2_fu_3835_p2)? a0_tmp_232_1_reg_6263: tmp_58_fu_3831_p1);
assign a0_2_tmp_232_2_cast_fu_3951_p1 = a0_2_tmp_232_2_reg_6337;
assign a0_2_tmp_232_2_fu_3916_p3 = ((tmp_233_2_fu_3911_p2)? a0_2_reg_6285: tmp_59_reg_6296);
assign a0_3_cast_fu_4036_p1 = a0_3_reg_6359;
assign a0_3_fu_3969_p3 = ((tmp_217_3_fu_3963_p2)? a0_2_tmp_232_2_reg_6337: tmp_60_fu_3959_p1);
assign a0_3_tmp_232_3_cast_fu_4079_p1 = a0_3_tmp_232_3_reg_6411;
assign a0_3_tmp_232_3_fu_4044_p3 = ((tmp_233_3_fu_4039_p2)? a0_3_reg_6359: tmp_61_reg_6370);
assign a0_4_cast_fu_4164_p1 = a0_4_reg_6433;
assign a0_4_fu_4097_p3 = ((tmp_217_4_fu_4091_p2)? a0_3_tmp_232_3_reg_6411: tmp_62_fu_4087_p1);
assign a0_4_tmp_232_4_cast_fu_4207_p1 = a0_4_tmp_232_4_reg_6485;
assign a0_4_tmp_232_4_fu_4172_p3 = ((tmp_233_4_fu_4167_p2)? a0_4_reg_6433: tmp_63_reg_6444);
assign a0_5_cast_fu_4292_p1 = a0_5_reg_6507;
assign a0_5_fu_4225_p3 = ((tmp_217_5_fu_4219_p2)? a0_4_tmp_232_4_reg_6485: tmp_64_fu_4215_p1);
assign a0_5_tmp_232_5_cast_fu_4335_p1 = a0_5_tmp_232_5_reg_6559;
assign a0_5_tmp_232_5_fu_4300_p3 = ((tmp_233_5_fu_4295_p2)? a0_5_reg_6507: tmp_65_reg_6518);
assign a0_6_cast_fu_4420_p1 = a0_6_reg_6581;
assign a0_6_fu_4353_p3 = ((tmp_217_6_fu_4347_p2)? a0_5_tmp_232_5_reg_6559: tmp_66_fu_4343_p1);
assign a0_6_tmp_232_6_cast_fu_4463_p1 = a0_6_tmp_232_6_reg_6633;
assign a0_6_tmp_232_6_fu_4428_p3 = ((tmp_233_6_fu_4423_p2)? a0_6_reg_6581: tmp_75_reg_6592);
assign a0_7_cast_fu_4549_p1 = a0_7_reg_6655;
assign a0_7_fu_4481_p3 = ((tmp_217_7_fu_4475_p2)? a0_6_tmp_232_6_reg_6633: tmp_77_fu_4471_p1);
assign a0_7_tmp_232_7_fu_4557_p3 = ((tmp_233_7_fu_4552_p2)? a0_7_reg_6655: tmp_78_reg_6666);
assign a0_cast_fu_3780_p1 = a0_s_reg_6211;
assign a0_s_fu_3713_p3 = ((tmp_217_1_fu_3707_p2)? p_a_0_flag_d_assign_load_5_tmp_s_reg_6189: tmp_56_fu_3703_p1);
assign a0_tmp_232_1_cast_fu_3823_p1 = a0_tmp_232_1_reg_6263;
assign a0_tmp_232_1_fu_3788_p3 = ((tmp_233_1_fu_3783_p2)? a0_s_reg_6211: tmp_57_reg_6222);
assign a_0_flag_d_assign_load_5_fu_3419_p3 = ((tmp_43_reg_6043)? flag_d_min8_1_reg_6029: flag_d_assign_reg_6011);
assign ap_reg_phiprechg_core_1_reg_527pp0_it0 = 'bx;
/// ap_sig_bdd_136 assign process. ///
always @ (p_mask_data_stream_V_full_n or ap_reg_ppstg_or_cond4_reg_5201_pp0_it34)
begin
ap_sig_bdd_136 = ((p_mask_data_stream_V_full_n == ap_const_logic_0) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond4_reg_5201_pp0_it34));
end
/// ap_sig_bdd_1776 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_1776 = ((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end
/// ap_sig_bdd_180 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_180 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_196 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_196 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_2075 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2075 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_2108 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it12 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_2108 = ((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end
/// ap_sig_bdd_2152 assign process. ///
always @ (exitcond_fu_846_p2 or or_cond1_fu_883_p2)
begin
ap_sig_bdd_2152 = ((ap_const_lv1_0 == exitcond_fu_846_p2) & (ap_const_lv1_0 == or_cond1_fu_883_p2));
end
/// ap_sig_bdd_2156 assign process. ///
always @ (ap_reg_ppstg_exitcond_reg_5147_pp0_it32 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)
begin
ap_sig_bdd_2156 = ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it32) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32));
end
/// ap_sig_bdd_2159 assign process. ///
always @ (ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or iscorner_2_i_s_fu_2870_p2)
begin
ap_sig_bdd_2159 = ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & (ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2));
end
/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_250 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
ap_sig_bdd_250 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end
/// ap_sig_bdd_48 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_48 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_61 assign process. ///
always @ (p_src_data_stream_V_empty_n or exitcond_reg_5147 or or_cond_reg_5156)
begin
ap_sig_bdd_61 = ((p_src_data_stream_V_empty_n == ap_const_logic_0) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156));
end
assign b0_2_cast_fu_3928_p1 = $signed(b0_2_reg_6301);
assign b0_2_fu_3882_p3 = ((tmp_228_2_fu_3876_p2)? b0_tmp_239_1_reg_6274: tmp_84_fu_3872_p1);
assign b0_2_tmp_239_2_cast_fu_3992_p1 = $signed(b0_2_tmp_239_2_reg_6348);
assign b0_2_tmp_239_2_fu_3936_p3 = ((tmp_240_2_fu_3931_p2)? b0_2_reg_6301: tmp_85_reg_6312);
assign b0_3_cast_fu_4056_p1 = $signed(b0_3_reg_6375);
assign b0_3_fu_4010_p3 = ((tmp_228_3_fu_4004_p2)? b0_2_tmp_239_2_reg_6348: tmp_86_fu_4000_p1);
assign b0_3_tmp_239_3_cast_fu_4120_p1 = $signed(b0_3_tmp_239_3_reg_6422);
assign b0_3_tmp_239_3_fu_4064_p3 = ((tmp_240_3_fu_4059_p2)? b0_3_reg_6375: tmp_87_reg_6386);
assign b0_4_cast_fu_4184_p1 = $signed(b0_4_reg_6449);
assign b0_4_fu_4138_p3 = ((tmp_228_4_fu_4132_p2)? b0_3_tmp_239_3_reg_6422: tmp_88_fu_4128_p1);
assign b0_4_tmp_239_4_cast_fu_4248_p1 = $signed(b0_4_tmp_239_4_reg_6496);
assign b0_4_tmp_239_4_fu_4192_p3 = ((tmp_240_4_fu_4187_p2)? b0_4_reg_6449: tmp_89_reg_6460);
assign b0_5_cast_fu_4312_p1 = $signed(b0_5_reg_6523);
assign b0_5_fu_4266_p3 = ((tmp_228_5_fu_4260_p2)? b0_4_tmp_239_4_reg_6496: tmp_90_fu_4256_p1);
assign b0_5_tmp_239_5_cast_fu_4376_p1 = $signed(b0_5_tmp_239_5_reg_6570);
assign b0_5_tmp_239_5_fu_4320_p3 = ((tmp_240_5_fu_4315_p2)? b0_5_reg_6523: tmp_91_reg_6534);
assign b0_6_cast_fu_4440_p1 = $signed(b0_6_reg_6597);
assign b0_6_fu_4394_p3 = ((tmp_228_6_fu_4388_p2)? b0_5_tmp_239_5_reg_6570: tmp_92_fu_4384_p1);
assign b0_6_tmp_239_6_cast_fu_4504_p1 = $signed(b0_6_tmp_239_6_reg_6644);
assign b0_6_tmp_239_6_fu_4448_p3 = ((tmp_240_6_fu_4443_p2)? b0_6_reg_6597: tmp_93_reg_6608);
assign b0_7_cast_fu_4563_p1 = $signed(b0_7_reg_6671);
assign b0_7_fu_4522_p3 = ((tmp_228_7_fu_4516_p2)? b0_6_tmp_239_6_reg_6644: tmp_94_fu_4512_p1);
assign b0_cast_50_fu_3800_p1 = $signed(b0_s_reg_6227);
assign b0_cast_fu_3672_p1 = $signed(b0_reg_6093);
assign b0_fu_3473_p3 = ((tmp_69_fu_3467_p2)? ap_const_lv9_1EC: tmp_80_fu_3463_p1);
assign b0_s_fu_3754_p3 = ((tmp_228_1_fu_3748_p2)? b0_tmp_s_reg_6200: tmp_82_fu_3744_p1);
assign b0_tmp_239_1_cast_fu_3864_p1 = $signed(b0_tmp_239_1_reg_6274);
assign b0_tmp_239_1_fu_3808_p3 = ((tmp_240_1_fu_3803_p2)? b0_s_reg_6227: tmp_83_reg_6238);
assign b0_tmp_239_cast_fu_3736_p1 = $signed(b0_tmp_s_reg_6200);
assign b0_tmp_s_fu_3680_p3 = ((tmp_72_fu_3675_p2)? b0_reg_6093: tmp_81_reg_6104);
assign core_buf_val_0_V_address0 = tmp_14_fu_4577_p1;
assign core_buf_val_0_V_address1 = core_buf_val_0_V_addr_reg_6702;
assign core_buf_val_0_V_d1 = core_buf_val_1_V_q0;
assign core_buf_val_1_V_address0 = tmp_14_fu_4577_p1;
assign core_buf_val_1_V_address1 = ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
assign core_buf_val_1_V_d1 = core_win_val_2_V_2_fu_4635_p3;
assign core_win_val_0_V_2_fu_4620_p1 = core_buf_val_0_V_load_reg_6724;
assign core_win_val_1_V_2_fu_4623_p1 = core_buf_val_1_V_load_reg_6729;
assign core_win_val_2_V_1_2_fu_4643_p1 = core_win_val_2_V_2_fu_4635_p3;
assign core_win_val_2_V_2_fu_4635_p3 = ((ap_reg_ppstg_or_cond_reg_5156_pp0_it33)? ap_reg_phiprechg_core_1_reg_527pp0_it34: ap_const_lv8_0);
assign count_1_fu_2407_p2 = (count_1_i_1_fu_2397_p3 + ap_const_lv4_1);
assign count_1_i_0_op_op87_op_fu_1848_p3 = ((or_cond5_fu_1746_p2)? ap_const_lv4_8: ap_const_lv4_9);
assign count_1_i_10_fu_2636_p3 = ((ap_reg_ppstg_or_cond5_reg_5537_pp0_it7)? ap_const_lv5_2: phitmp8_reg_5842);
assign count_1_i_11_fu_2659_p3 = ((ap_reg_ppstg_or_cond6_reg_5543_pp0_it7)? ap_const_lv5_1: count_1_i_10_fu_2636_p3);
assign count_1_i_12_fu_2678_p3 = ((ap_reg_ppstg_or_cond7_reg_5548_pp0_it7)? ap_const_lv5_2: phitmp9_fu_2672_p2);
assign count_1_i_13_fu_2731_p3 = ((ap_reg_ppstg_or_cond8_reg_5553_pp0_it8)? ap_const_lv5_1: count_1_i_12_reg_5872);
assign count_1_i_14_fu_2755_p3 = ((ap_reg_ppstg_or_cond9_reg_5559_pp0_it8)? ap_const_lv5_2: phitmp10_fu_2749_p2);
assign count_1_i_15_fu_2793_p3 = ((ap_reg_ppstg_or_cond2_reg_5660_pp0_it9)? ap_const_lv5_1: count_1_i_14_reg_5898);
assign count_1_i_1_fu_2397_p3 = ((or_cond14_reg_5759)? ap_const_lv4_1: count_1_i_s_reg_5753);
assign count_1_i_2_fu_2441_p3 = ((or_cond15_fu_2403_p2)? ap_const_lv4_2: phitmp6_fu_2419_p2);
assign count_1_i_2_op_op_fu_1998_p3 = ((tmp_40_reg_5600)? phitmp43_op_op_cast_cast_cast_reg_5595: count_1_i_0_op_op87_op_reg_5590);
assign count_1_i_3_cast_fu_2531_p1 = count_1_i_3_reg_5806;
assign count_1_i_3_fu_2476_p3 = ((or_cond16_fu_2458_p2)? ap_const_lv4_1: count_1_i_2_fu_2441_p3);
assign count_1_i_4_fu_2563_p3 = ((or_cond17_reg_5811)? ap_const_lv5_2: phitmp7_fu_2546_p2);
assign count_1_i_4_op_fu_2014_p3 = ((tmp_41_fu_2010_p2)? phitmp42_op_cast_cast_cast_fu_2003_p3: count_1_i_2_op_op_fu_1998_p3);
assign count_1_i_5_fu_2587_p3 = ((or_cond18_reg_5821)? ap_const_lv5_1: count_1_i_4_fu_2563_p3);
assign count_1_i_6_fu_2036_p3 = ((tmp_42_fu_2030_p2)? phitmp3_cast_cast_cast_fu_2022_p3: count_1_i_4_op_fu_2014_p3);
assign count_1_i_7_fu_2061_p3 = ((or_cond10_fu_2055_p2)? ap_const_lv4_1: count_1_i_6_fu_2036_p3);
assign count_1_i_8_fu_2224_p3 = ((or_cond11_reg_5681)? ap_const_lv4_2: phitmp4_fu_2208_p2);
assign count_1_i_9_fu_2257_p3 = ((or_cond12_fu_2231_p2)? ap_const_lv4_1: count_1_i_8_fu_2224_p3);
assign count_1_i_s_fu_2292_p3 = ((or_cond13_fu_2274_p2)? ap_const_lv4_2: phitmp5_fu_2280_p2);
assign count_2_fu_2534_p2 = (count_1_i_3_cast_fu_2531_p1 + ap_const_lv5_1);
assign count_3_fu_2594_p2 = (count_1_i_5_fu_2587_p3 + ap_const_lv5_1);
assign count_4_fu_2666_p2 = (count_1_i_11_fu_2659_p3 + ap_const_lv5_1);
assign count_5_fu_2737_p2 = (count_1_i_13_fu_2731_p3 + ap_const_lv5_1);
assign count_6_fu_2799_p2 = (count_1_i_15_fu_2793_p3 + ap_const_lv5_1);
assign count_8_fu_2197_p2 = (count_1_i_7_reg_5675 + ap_const_lv4_1);
assign count_s_fu_2359_p2 = (count_1_i_9_reg_5743 + ap_const_lv4_1);
assign exitcond1_fu_802_p2 = (p_s_reg_504 == tmp_5_reg_5113? 1'b1: 1'b0);
assign exitcond_fu_846_p2 = (p_2_phi_fu_519_p4 == tmp_s_reg_5108? 1'b1: 1'b0);
assign flag_d_assign_10_fu_3692_p1 = $signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17);
assign flag_d_assign_11_fu_4289_p1 = $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26);
assign flag_d_assign_12_fu_3820_p1 = $signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19);
assign flag_d_assign_13_fu_4417_p1 = $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28);
assign flag_d_assign_14_fu_3948_p1 = $signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21);
assign flag_d_assign_1_fu_4076_p1 = $signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it23);
assign flag_d_assign_2_fu_3497_p1 = $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it16);
assign flag_d_assign_3_fu_4204_p1 = $signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it25);
assign flag_d_assign_4_fu_3777_p1 = $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it18);
assign flag_d_assign_5_fu_4332_p1 = $signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it27);
assign flag_d_assign_6_fu_3905_p1 = $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it20);
assign flag_d_assign_7_fu_4460_p1 = $signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it29);
assign flag_d_assign_8_fu_4033_p1 = $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it22);
assign flag_d_assign_9_fu_3274_p1 = $signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15);
assign flag_d_assign_fu_3143_p1 = $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign flag_d_assign_s_fu_4161_p1 = $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24);
assign flag_val_V_assign_load_1_10_fu_2131_p3 = ((tmp_34_fu_2127_p2)? phitmp1_5_fu_2120_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_11_fu_1698_p3 = ((tmp_35_fu_1694_p2)? phitmp_6_fu_1687_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_12_fu_2163_p3 = ((tmp_36_fu_2157_p2)? phitmp1_6_fu_2149_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_13_fu_1726_p3 = ((tmp_37_fu_1722_p2)? phitmp_7_fu_1715_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_14_fu_2351_p3 = ((tmp_38_fu_2347_p2)? phitmp1_7_fu_2340_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_1_fu_1562_p3 = ((tmp_24_reg_5285)? phitmp_1_reg_5280: ap_const_lv2_0);
assign flag_val_V_assign_load_1_2_fu_1589_p3 = ((tmp_27_reg_5304)? phitmp_2_reg_5299: ap_const_lv2_0);
assign flag_val_V_assign_load_1_3_fu_1930_p3 = ((tmp_28_fu_1926_p2)? phitmp1_2_fu_1919_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_4_fu_1616_p3 = ((tmp_29_reg_5323)? phitmp_3_reg_5318: ap_const_lv2_0);
assign flag_val_V_assign_load_1_5_fu_1962_p3 = ((tmp_30_fu_1956_p2)? phitmp1_3_fu_1948_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_6_fu_1642_p3 = ((tmp_31_fu_1638_p2)? phitmp_4_fu_1631_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_7_fu_2112_p3 = ((tmp_32_fu_2108_p2)? phitmp1_4_fu_2101_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_8_fu_1670_p3 = ((tmp_33_fu_1666_p2)? phitmp_5_fu_1659_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_9_fu_1911_p3 = ((tmp_25_fu_1907_p2)? phitmp1_1_fu_1900_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_s_fu_1521_p3 = ((tmp_20_reg_5266)? phitmp1_reg_5261: ap_const_lv2_0);
assign flag_val_V_assign_load_2_s_fu_1894_p3 = ((tmp_23_reg_5427)? phitmp3_reg_5422: ap_const_lv2_0);
assign grp_image_filter_reg_int_s_fu_542_in_r = $signed(tmp_193_1_fu_2879_p3);
assign grp_image_filter_reg_int_s_fu_547_in_r = $signed(tmp_203_1_fu_2894_p3);
assign grp_image_filter_reg_int_s_fu_552_in_r = $signed(tmp_193_3_fu_2909_p3);
assign grp_image_filter_reg_int_s_fu_557_in_r = $signed(tmp_203_3_fu_2924_p3);
assign grp_image_filter_reg_int_s_fu_562_in_r = $signed(tmp_193_5_fu_2939_p3);
assign grp_image_filter_reg_int_s_fu_567_in_r = $signed(tmp_203_5_fu_2954_p3);
assign grp_image_filter_reg_int_s_fu_572_in_r = $signed(tmp_193_7_fu_2969_p3);
assign grp_image_filter_reg_int_s_fu_577_in_r = $signed(tmp_203_7_fu_2984_p3);
assign grp_image_filter_reg_int_s_fu_582_in_r = ((tmp_192_1_fu_2995_p2)? grp_image_filter_reg_int_s_fu_542_ap_return: grp_image_filter_reg_int_s_fu_552_ap_return);
assign grp_image_filter_reg_int_s_fu_587_in_r = ((tmp_202_1_fu_3010_p2)? grp_image_filter_reg_int_s_fu_547_ap_return: grp_image_filter_reg_int_s_fu_557_ap_return);
assign grp_image_filter_reg_int_s_fu_592_in_r = ((tmp_192_5_fu_3053_p2)? grp_image_filter_reg_int_s_fu_562_ap_return: grp_image_filter_reg_int_s_fu_572_ap_return);
assign grp_image_filter_reg_int_s_fu_597_in_r = ((tmp_202_5_fu_3068_p2)? grp_image_filter_reg_int_s_fu_567_ap_return: grp_image_filter_reg_int_s_fu_577_ap_return);
assign grp_image_filter_reg_int_s_fu_602_in_r = $signed(tmp_193_9_fu_3087_p3);
assign grp_image_filter_reg_int_s_fu_607_in_r = $signed(tmp_203_9_fu_3102_p3);
assign grp_image_filter_reg_int_s_fu_612_in_r = ((tmp_199_1_fu_3113_p2)? grp_image_filter_reg_int_s_fu_582_ap_return: grp_image_filter_reg_int_s_fu_592_ap_return);
assign grp_image_filter_reg_int_s_fu_617_in_r = ((tmp_212_1_fu_3128_p2)? grp_image_filter_reg_int_s_fu_587_ap_return: grp_image_filter_reg_int_s_fu_597_ap_return);
assign grp_image_filter_reg_int_s_fu_622_in_r = $signed(tmp_193_s_fu_3150_p3);
assign grp_image_filter_reg_int_s_fu_627_in_r = $signed(tmp_203_s_fu_3165_p3);
assign grp_image_filter_reg_int_s_fu_632_in_r = $signed(tmp_193_2_fu_3180_p3);
assign grp_image_filter_reg_int_s_fu_637_in_r = $signed(tmp_203_2_fu_3195_p3);
assign grp_image_filter_reg_int_s_fu_642_in_r = $signed(tmp_193_4_fu_3210_p3);
assign grp_image_filter_reg_int_s_fu_647_in_r = $signed(tmp_203_4_fu_3225_p3);
assign grp_image_filter_reg_int_s_fu_652_in_r = ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
assign grp_image_filter_reg_int_s_fu_657_in_r = ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
assign grp_image_filter_reg_int_s_fu_662_in_r = ((tmp_192_7_fu_3236_p2)? ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14: grp_image_filter_reg_int_s_fu_602_ap_return);
assign grp_image_filter_reg_int_s_fu_667_in_r = ((tmp_202_7_fu_3249_p2)? ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14: grp_image_filter_reg_int_s_fu_607_ap_return);
assign grp_image_filter_reg_int_s_fu_672_in_r = ((tmp_192_9_fu_3277_p2)? flag_d_min2_9_reg_6017: grp_image_filter_reg_int_s_fu_622_ap_return);
assign grp_image_filter_reg_int_s_fu_677_in_r = ((tmp_202_9_fu_3290_p2)? flag_d_max2_9_reg_6023: grp_image_filter_reg_int_s_fu_627_ap_return);
assign grp_image_filter_reg_int_s_fu_682_in_r = ((tmp_192_s_fu_3303_p2)? grp_image_filter_reg_int_s_fu_622_ap_return: grp_image_filter_reg_int_s_fu_632_ap_return);
assign grp_image_filter_reg_int_s_fu_687_in_r = ((tmp_202_s_fu_3318_p2)? grp_image_filter_reg_int_s_fu_627_ap_return: grp_image_filter_reg_int_s_fu_637_ap_return);
assign grp_image_filter_reg_int_s_fu_692_in_r = ((tmp_192_2_fu_3333_p2)? grp_image_filter_reg_int_s_fu_632_ap_return: grp_image_filter_reg_int_s_fu_642_ap_return);
assign grp_image_filter_reg_int_s_fu_697_in_r = ((tmp_202_2_fu_3348_p2)? grp_image_filter_reg_int_s_fu_637_ap_return: grp_image_filter_reg_int_s_fu_647_ap_return);
assign grp_image_filter_reg_int_s_fu_702_in_r = ((tmp_192_4_fu_3363_p2)? grp_image_filter_reg_int_s_fu_642_ap_return: ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15);
assign grp_image_filter_reg_int_s_fu_707_in_r = ((tmp_202_4_fu_3376_p2)? grp_image_filter_reg_int_s_fu_647_ap_return: ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15);
assign grp_image_filter_reg_int_s_fu_712_in_r = ((tmp_199_3_fu_3389_p2)? grp_image_filter_reg_int_s_fu_652_ap_return: grp_image_filter_reg_int_s_fu_662_ap_return);
assign grp_image_filter_reg_int_s_fu_717_in_r = ((tmp_212_3_fu_3404_p2)? grp_image_filter_reg_int_s_fu_657_ap_return: grp_image_filter_reg_int_s_fu_667_ap_return);
assign grp_image_filter_reg_int_s_fu_722_in_r = tmp_210_5_reg_6129;
assign grp_image_filter_reg_int_s_fu_727_in_r = tmp_225_5_reg_6134;
assign grp_image_filter_reg_int_s_fu_732_in_r = ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
assign grp_image_filter_reg_int_s_fu_737_in_r = ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
assign grp_image_filter_reg_int_s_fu_742_in_r = ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
assign grp_image_filter_reg_int_s_fu_747_in_r = ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
assign grp_image_filter_reg_int_s_fu_752_in_r = ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
assign grp_image_filter_reg_int_s_fu_757_in_r = ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
assign grp_image_filter_reg_int_s_fu_762_in_r = ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
assign grp_image_filter_reg_int_s_fu_767_in_r = ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
assign grp_image_filter_reg_int_s_fu_772_in_r = ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
assign grp_image_filter_reg_int_s_fu_777_in_r = ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
assign i_V_fu_807_p2 = (p_s_reg_504 + ap_const_lv11_1);
assign icmp1_fu_898_p2 = (tmp_97_fu_888_p4 == ap_const_lv9_0? 1'b1: 1'b0);
assign icmp_fu_840_p2 = (tmp_16_fu_830_p4 == ap_const_lv9_0? 1'b1: 1'b0);
assign iscorner_2_i_7_fu_2191_p2 = (tmp_185_7_fu_2181_p2 & not_or_cond_fu_2186_p2);
assign iscorner_2_i_s_fu_2870_p2 = (tmp10_fu_2866_p2 | ap_reg_ppstg_tmp3_reg_5878_pp0_it11);
assign j_V_fu_851_p2 = (p_2_phi_fu_519_p4 + ap_const_lv11_1);
assign k_buf_val_0_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_0_V_address1 = k_buf_val_0_V_addr_reg_5161;
assign k_buf_val_0_V_d1 = k_buf_val_1_V_q0;
assign k_buf_val_1_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_1_V_address1 = k_buf_val_1_V_addr_reg_5167;
assign k_buf_val_1_V_d1 = k_buf_val_2_V_q0;
assign k_buf_val_2_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_2_V_address1 = k_buf_val_2_V_addr_reg_5173;
assign k_buf_val_2_V_d1 = k_buf_val_3_V_q0;
assign k_buf_val_3_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_3_V_address1 = k_buf_val_3_V_addr_reg_5179;
assign k_buf_val_3_V_d1 = k_buf_val_4_V_q0;
assign k_buf_val_4_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_4_V_address1 = k_buf_val_4_V_addr_reg_5185;
assign k_buf_val_4_V_d1 = k_buf_val_5_V_q0;
assign k_buf_val_5_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_5_V_address1 = k_buf_val_5_V_addr_reg_5191;
assign k_buf_val_5_V_d1 = p_src_data_stream_V_dout;
assign lhs_V_fu_1252_p1 = win_val_3_V_2_fu_252;
assign not_or_cond10_demorgan_fu_2093_p2 = (tmp_183_5_reg_5572 | tmp_181_5_not_reg_5566);
assign not_or_cond10_fu_2782_p2 = (ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond11_demorgan_fu_2097_p2 = (tmp_183_6_reg_5584 | tmp_181_6_not_reg_5578);
assign not_or_cond11_fu_2817_p2 = (ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond12_demorgan_fu_2425_p2 = (tmp_181_2_reg_5769 | tmp_183_10_reg_5775);
assign not_or_cond12_fu_2429_p2 = (not_or_cond12_demorgan_fu_2425_p2 ^ ap_const_lv1_1);
assign not_or_cond13_demorgan_fu_2470_p2 = (tmp_181_3_fu_2449_p2 | tmp_183_11_fu_2453_p2);
assign not_or_cond13_fu_2521_p2 = (not_or_cond13_demorgan_reg_5801 ^ ap_const_lv1_1);
assign not_or_cond14_demorgan_fu_2500_p2 = (tmp_181_4_fu_2484_p2 | tmp_183_12_fu_2489_p2);
assign not_or_cond14_fu_2552_p2 = (not_or_cond14_demorgan_reg_5816 ^ ap_const_lv1_1);
assign not_or_cond15_fu_2576_p2 = (or_cond18_reg_5821 ^ ap_const_lv1_1);
assign not_or_cond1_fu_2213_p2 = (or_cond11_reg_5681 ^ ap_const_lv1_1);
assign not_or_cond2_demorgan_fu_2241_p2 = (tmp_181_9_reg_5687 | tmp_183_9_reg_5693);
assign not_or_cond2_fu_2245_p2 = (not_or_cond2_demorgan_fu_2241_p2 ^ ap_const_lv1_1);
assign not_or_cond3_demorgan_fu_2286_p2 = (tmp_181_s_fu_2265_p2 | tmp_183_s_fu_2269_p2);
assign not_or_cond3_fu_2370_p2 = (not_or_cond3_demorgan_reg_5748 ^ ap_const_lv1_1);
assign not_or_cond4_demorgan_fu_2316_p2 = (tmp_181_1_fu_2300_p2 | tmp_183_8_fu_2305_p2);
assign not_or_cond4_fu_2386_p2 = (not_or_cond4_demorgan_reg_5764 ^ ap_const_lv1_1);
assign not_or_cond5_fu_2625_p2 = (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 ^ ap_const_lv1_1);
assign not_or_cond6_demorgan_fu_1870_p2 = (tmp_183_1_fu_1758_p2 | tmp_181_1_not_fu_1752_p2);
assign not_or_cond6_fu_2648_p2 = (ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 ^ ap_const_lv1_1);
assign not_or_cond7_demorgan_fu_1876_p2 = (tmp_183_2_fu_1776_p2 | tmp_181_2_not_fu_1770_p2);
assign not_or_cond7_fu_2704_p2 = (ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 ^ ap_const_lv1_1);
assign not_or_cond8_demorgan_fu_1882_p2 = (tmp_183_3_fu_1794_p2 | tmp_181_3_not_fu_1788_p2);
assign not_or_cond8_fu_2720_p2 = (ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 ^ ap_const_lv1_1);
assign not_or_cond9_demorgan_fu_1888_p2 = (tmp_183_4_fu_1812_p2 | tmp_181_4_not_fu_1806_p2);
assign not_or_cond9_fu_2767_p2 = (ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond_fu_2186_p2 = (or_cond10_reg_5670 ^ ap_const_lv1_1);
assign or_cond10_fu_2055_p2 = (tmp_183_7_fu_2049_p2 | tmp_181_7_not_fu_2044_p2);
assign or_cond11_fu_2075_p2 = (tmp_181_8_fu_2069_p2 | tmp_183_7_fu_2049_p2);
assign or_cond12_fu_2231_p2 = (tmp_181_9_reg_5687 | tmp_183_9_reg_5693);
assign or_cond13_fu_2274_p2 = (tmp_181_s_fu_2265_p2 | tmp_183_s_fu_2269_p2);
assign or_cond14_fu_2310_p2 = (tmp_181_1_fu_2300_p2 | tmp_183_8_fu_2305_p2);
assign or_cond15_fu_2403_p2 = (tmp_181_2_reg_5769 | tmp_183_10_reg_5775);
assign or_cond16_fu_2458_p2 = (tmp_181_3_fu_2449_p2 | tmp_183_11_fu_2453_p2);
assign or_cond17_fu_2494_p2 = (tmp_181_4_fu_2484_p2 | tmp_183_12_fu_2489_p2);
assign or_cond18_fu_2511_p2 = (tmp_181_5_fu_2506_p2 | ap_reg_ppstg_tmp_39_reg_5532_pp0_it5);
assign or_cond1_fu_883_p2 = (tmp_8_reg_5132 & tmp_17_fu_877_p2);
assign or_cond2_fu_1990_p2 = (tmp_183_5_reg_5572 | tmp_181_5_not_reg_5566);
assign or_cond3_fu_1994_p2 = (tmp_183_6_reg_5584 | tmp_181_6_not_reg_5578);
assign or_cond4_fu_904_p2 = (icmp_reg_5142 | icmp1_fu_898_p2);
assign or_cond5_fu_1746_p2 = (tmp_39_fu_1740_p2 | tmp_181_0_not_fu_1734_p2);
assign or_cond6_fu_1764_p2 = (tmp_183_1_fu_1758_p2 | tmp_181_1_not_fu_1752_p2);
assign or_cond7_fu_1782_p2 = (tmp_183_2_fu_1776_p2 | tmp_181_2_not_fu_1770_p2);
assign or_cond8_fu_1800_p2 = (tmp_183_3_fu_1794_p2 | tmp_181_3_not_fu_1788_p2);
assign or_cond9_fu_1818_p2 = (tmp_183_4_fu_1812_p2 | tmp_181_4_not_fu_1806_p2);
assign or_cond_fu_862_p2 = (tmp_7_reg_5127 & tmp_11_fu_857_p2);
assign p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 = p_a_0_flag_d_assign_load_5_reg_6077;
assign p_a_0_flag_d_assign_load_5_fu_3434_p3 = ((tmp_45_fu_3428_p2)? ap_const_lv8_14: tmp_44_fu_3424_p1);
assign p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 = p_a_0_flag_d_assign_load_5_tmp_s_reg_6189;
assign p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 = ((tmp_49_fu_3655_p2)? p_a_0_flag_d_assign_load_5_reg_6077: tmp_48_reg_6088);
assign p_iscorner_0_i_10_fu_2709_p2 = (tmp_185_11_fu_2699_p2 & not_or_cond7_fu_2704_p2);
assign p_iscorner_0_i_11_fu_2725_p2 = (tmp_185_12_fu_2715_p2 & not_or_cond8_fu_2720_p2);
assign p_iscorner_0_i_12_fu_2772_p2 = (tmp_185_13_reg_5893 & not_or_cond9_fu_2767_p2);
assign p_iscorner_0_i_13_fu_2787_p2 = (tmp_185_14_fu_2777_p2 & not_or_cond10_fu_2782_p2);
assign p_iscorner_0_i_14_fu_2842_p2 = (tmp_185_15_reg_5914 & not_or_cond11_reg_5919);
assign p_iscorner_0_i_15_fu_2846_p2 = (tmp2_reg_5929 & tmp_185_16_reg_5924);
assign p_iscorner_0_i_1_fu_2391_p2 = (tmp_185_1_fu_2381_p2 & not_or_cond4_fu_2386_p2);
assign p_iscorner_0_i_2_fu_2435_p2 = (tmp_185_2_fu_2413_p2 & not_or_cond12_fu_2429_p2);
assign p_iscorner_0_i_3_fu_2526_p2 = (tmp_185_3_reg_5796 & not_or_cond13_fu_2521_p2);
assign p_iscorner_0_i_4_fu_2557_p2 = (tmp_185_4_fu_2540_p2 & not_or_cond14_fu_2552_p2);
assign p_iscorner_0_i_5_fu_2581_p2 = (tmp_185_5_fu_2570_p2 & not_or_cond15_fu_2576_p2);
assign p_iscorner_0_i_6_fu_2630_p2 = (tmp_185_6_fu_2620_p2 & not_or_cond5_fu_2625_p2);
assign p_iscorner_0_i_7_fu_2653_p2 = (tmp_185_10_fu_2642_p2 & not_or_cond6_fu_2648_p2);
assign p_iscorner_0_i_8_fu_2218_p2 = (tmp_185_8_fu_2202_p2 & not_or_cond1_fu_2213_p2);
assign p_iscorner_0_i_9_fu_2251_p2 = (tmp_185_9_fu_2235_p2 & not_or_cond2_fu_2245_p2);
assign p_iscorner_0_i_s_fu_2375_p2 = (tmp_185_s_fu_2364_p2 & not_or_cond3_fu_2370_p2);
assign p_mask_data_stream_V_din = ((tmp_26_fu_4779_p2)? ap_const_lv8_FF: ap_const_lv8_0);
assign phitmp10_fu_2749_p2 = (count_1_i_13_fu_2731_p3 + ap_const_lv5_2);
assign phitmp1_1_fu_1900_p3 = ((tmp_182_1_reg_5441)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_2_fu_1919_p3 = ((tmp_182_2_reg_5461)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_3_fu_1948_p3 = ((tmp_182_3_fu_1938_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_4_fu_2101_p3 = ((tmp_182_4_reg_5638)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_5_fu_2120_p3 = ((tmp_182_5_reg_5649)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_6_fu_2149_p3 = ((tmp_182_6_fu_2139_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_7_fu_2340_p3 = ((tmp_182_7_reg_5722)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_fu_1278_p3 = ((tmp_18_fu_1266_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp2_fu_4606_p2 = ($signed(tmp_100_v_reg_6714) + $signed(ap_const_lv8_FF));
assign phitmp3_cast_cast_cast_fu_2022_p3 = ((or_cond3_fu_1994_p2)? ap_const_lv4_2: ap_const_lv4_3);
assign phitmp3_fu_1539_p3 = ((tmp_21_fu_1527_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp42_op_cast_cast_cast_fu_2003_p3 = ((or_cond9_reg_5559)? ap_const_lv4_4: ap_const_lv4_5);
assign phitmp43_op_op_cast_cast_cast_fu_1856_p3 = ((or_cond7_fu_1782_p2)? ap_const_lv4_6: ap_const_lv4_7);
assign phitmp4_fu_2208_p2 = (count_1_i_7_reg_5675 + ap_const_lv4_2);
assign phitmp5_fu_2280_p2 = (count_1_i_9_fu_2257_p3 + ap_const_lv4_2);
assign phitmp6_fu_2419_p2 = (count_1_i_1_fu_2397_p3 + ap_const_lv4_2);
assign phitmp7_fu_2546_p2 = (count_1_i_3_cast_fu_2531_p1 + ap_const_lv5_2);
assign phitmp8_fu_2600_p2 = (count_1_i_5_fu_2587_p3 + ap_const_lv5_2);
assign phitmp9_fu_2672_p2 = (count_1_i_11_fu_2659_p3 + ap_const_lv5_2);
assign phitmp_1_fu_1314_p3 = ((tmp_176_1_fu_1302_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_2_fu_1350_p3 = ((tmp_176_2_fu_1338_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_3_fu_1386_p3 = ((tmp_176_3_fu_1374_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_4_fu_1631_p3 = ((tmp_176_4_reg_5337)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_5_fu_1659_p3 = ((tmp_176_5_reg_5357)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_6_fu_1687_p3 = ((tmp_176_6_reg_5377)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_7_fu_1715_p3 = ((tmp_176_7_reg_5397)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_fu_2811_p2 = (count_1_i_15_fu_2793_p3 + ap_const_lv5_2);
assign r_V_1_1_fu_1557_p2 = (lhs_V_reg_5240 - rhs_V_1_1_fu_1553_p1);
assign r_V_1_2_fu_1584_p2 = (lhs_V_reg_5240 - rhs_V_1_2_fu_1580_p1);
assign r_V_1_3_fu_1611_p2 = (lhs_V_reg_5240 - rhs_V_1_3_fu_1607_p1);
assign r_V_1_4_fu_1626_p2 = (lhs_V_reg_5240 - rhs_V_1_4_fu_1622_p1);
assign r_V_1_5_fu_1654_p2 = (lhs_V_reg_5240 - rhs_V_1_5_fu_1650_p1);
assign r_V_1_6_fu_1682_p2 = (lhs_V_reg_5240 - rhs_V_1_6_fu_1678_p1);
assign r_V_1_7_fu_1710_p2 = (lhs_V_reg_5240 - rhs_V_1_7_fu_1706_p1);
assign r_V_1_fu_1516_p2 = (lhs_V_reg_5240 - rhs_V_1_fu_1512_p1);
assign r_V_2_fu_1332_p2 = (lhs_V_fu_1252_p1 - rhs_V_2_fu_1328_p1);
assign r_V_3_fu_1368_p2 = (lhs_V_fu_1252_p1 - rhs_V_3_fu_1364_p1);
assign r_V_4_fu_1404_p2 = (lhs_V_fu_1252_p1 - rhs_V_4_fu_1400_p1);
assign r_V_5_fu_1426_p2 = (lhs_V_fu_1252_p1 - rhs_V_5_fu_1422_p1);
assign r_V_6_fu_1448_p2 = (lhs_V_fu_1252_p1 - rhs_V_6_fu_1444_p1);
assign r_V_7_fu_1470_p2 = (lhs_V_fu_1252_p1 - rhs_V_7_fu_1466_p1);
assign r_V_fu_1260_p2 = (lhs_V_fu_1252_p1 - rhs_V_fu_1256_p1);
assign r_V_s_fu_1296_p2 = (lhs_V_fu_1252_p1 - rhs_V_s_fu_1292_p1);
assign rhs_V_1_1_fu_1553_p1 = win_val_6_V_2_3_fu_320;
assign rhs_V_1_2_fu_1580_p1 = win_val_5_V_1_3_fu_296;
assign rhs_V_1_3_fu_1607_p1 = win_val_4_V_0_3_fu_268;
assign rhs_V_1_4_fu_1622_p1 = win_val_3_V_0_3_fu_240;
assign rhs_V_1_5_fu_1650_p1 = win_val_2_V_0_3_fu_212;
assign rhs_V_1_6_fu_1678_p1 = win_val_1_V_1_3_fu_188;
assign rhs_V_1_7_fu_1706_p1 = win_val_0_V_2_3_fu_168;
assign rhs_V_1_fu_1512_p1 = win_val_6_V_2_fu_324;
assign rhs_V_2_fu_1328_p1 = win_val_1_V_4_fu_204;
assign rhs_V_3_fu_1364_p1 = win_val_2_V_5_fu_236;
assign rhs_V_4_fu_1400_p1 = win_val_3_V_5_fu_264;
assign rhs_V_5_fu_1422_p1 = win_val_4_V_5_fu_292;
assign rhs_V_6_fu_1444_p1 = win_val_5_V_4_fu_312;
assign rhs_V_7_fu_1466_p1 = win_val_6_V_3_fu_156;
assign rhs_V_fu_1256_p1 = win_val_0_V_2_fu_172;
assign rhs_V_s_fu_1292_p1 = win_val_0_V_3_fu_176;
assign tmp10_fu_2866_p2 = (tmp14_reg_5944 | ap_reg_ppstg_tmp11_reg_5934_pp0_it11);
assign tmp11_fu_2833_p2 = (tmp13_reg_5904 | ap_reg_ppstg_tmp12_reg_5883_pp0_it9);
assign tmp12_fu_2694_p2 = (p_iscorner_0_i_5_reg_5832 | p_iscorner_0_i_6_fu_2630_p2);
assign tmp13_fu_2762_p2 = (p_iscorner_0_i_7_reg_5862 | p_iscorner_0_i_10_fu_2709_p2);
assign tmp14_fu_2861_p2 = (tmp16_fu_2856_p2 | tmp15_reg_5939);
assign tmp15_fu_2837_p2 = (p_iscorner_0_i_11_reg_5888 | p_iscorner_0_i_12_fu_2772_p2);
assign tmp16_fu_2856_p2 = (tmp17_fu_2850_p2 | p_iscorner_0_i_13_reg_5909);
assign tmp17_fu_2850_p2 = (p_iscorner_0_i_14_fu_2842_p2 | p_iscorner_0_i_15_fu_2846_p2);
assign tmp18_fu_4771_p2 = (tmp20_reg_6744 & tmp19_reg_6739);
assign tmp19_fu_4701_p2 = (tmp_52_fu_4647_p2 & tmp_9_reg_5137);
assign tmp20_fu_4712_p2 = (tmp21_fu_4706_p2 & ap_reg_ppstg_tmp_53_reg_6719_pp0_it33);
assign tmp21_fu_4706_p2 = (tmp_73_fu_4653_p2 & tmp_242_1_fu_4659_p2);
assign tmp22_fu_4775_p2 = (tmp25_reg_6754 & tmp23_reg_6749);
assign tmp23_fu_4723_p2 = (tmp24_fu_4717_p2 & tmp_242_2_fu_4665_p2);
assign tmp24_fu_4717_p2 = (tmp_74_fu_4671_p2 & tmp_245_1_fu_4677_p2);
assign tmp25_fu_4735_p2 = (tmp26_fu_4729_p2 & tmp_245_2_fu_4683_p2);
assign tmp26_fu_4729_p2 = (tmp_55_fu_4695_p2 & tmp_54_fu_4689_p2);
assign tmp2_fu_2828_p2 = (not_or_cond11_fu_2817_p2 & ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9);
assign tmp3_fu_2689_p2 = (tmp7_fu_2685_p2 | tmp4_reg_5847);
assign tmp4_fu_2606_p2 = (tmp6_reg_5827 | ap_reg_ppstg_tmp5_reg_5781_pp0_it6);
assign tmp5_fu_2334_p2 = (iscorner_2_i_7_fu_2191_p2 | p_iscorner_0_i_8_fu_2218_p2);
assign tmp6_fu_2516_p2 = (p_iscorner_0_i_9_reg_5738 | p_iscorner_0_i_s_fu_2375_p2);
assign tmp7_fu_2685_p2 = (tmp9_reg_5857 | tmp8_reg_5852);
assign tmp8_fu_2610_p2 = (p_iscorner_0_i_1_reg_5786 | p_iscorner_0_i_2_reg_5791);
assign tmp9_fu_2614_p2 = (p_iscorner_0_i_3_fu_2526_p2 | p_iscorner_0_i_4_fu_2557_p2);
assign tmp_100_v_fu_4593_p3 = ((tmp_51_fu_4588_p2)? a0_7_tmp_232_7_reg_6691: tmp_50_fu_4583_p2);
assign tmp_11_fu_857_p2 = (p_2_phi_fu_519_p4 < tmp_15_reg_5103? 1'b1: 1'b0);
assign tmp_12_fu_867_p1 = p_2_phi_fu_519_p4;
assign tmp_14_fu_4577_p1 = ap_reg_ppstg_p_2_reg_515_pp0_it31;
assign tmp_15_fu_786_p1 = p_src_cols_V_read[10:0];
assign tmp_16_fu_830_p4 = {{p_s_reg_504[ap_const_lv32_A : ap_const_lv32_2]}};
assign tmp_176_1_fu_1302_p2 = ($signed(r_V_s_fu_1296_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_2_fu_1338_p2 = ($signed(r_V_2_fu_1332_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_3_fu_1374_p2 = ($signed(r_V_3_fu_1368_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_4_fu_1410_p2 = ($signed(r_V_4_fu_1404_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_5_fu_1432_p2 = ($signed(r_V_5_fu_1426_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_6_fu_1454_p2 = ($signed(r_V_6_fu_1448_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_7_fu_1476_p2 = ($signed(r_V_7_fu_1470_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_177_1_fu_1308_p2 = ($signed(r_V_s_fu_1296_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_2_fu_1344_p2 = ($signed(r_V_2_fu_1332_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_3_fu_1380_p2 = ($signed(r_V_3_fu_1368_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_4_fu_1416_p2 = ($signed(r_V_4_fu_1404_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_5_fu_1438_p2 = ($signed(r_V_5_fu_1426_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_6_fu_1460_p2 = ($signed(r_V_6_fu_1448_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_7_fu_1482_p2 = ($signed(r_V_7_fu_1470_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_17_fu_877_p2 = (p_2_phi_fu_519_p4 > ap_const_lv11_5? 1'b1: 1'b0);
assign tmp_181_0_not_fu_1734_p2 = (flag_val_V_assign_load_1_s_fu_1521_p3 != flag_val_V_assign_load_1_1_fu_1562_p3? 1'b1: 1'b0);
assign tmp_181_1_fu_2300_p2 = (flag_val_V_assign_load_1_5_reg_5631 != flag_val_V_assign_load_1_7_fu_2112_p3? 1'b1: 1'b0);
assign tmp_181_1_not_fu_1752_p2 = (flag_val_V_assign_load_1_1_fu_1562_p3 != flag_val_V_assign_load_1_2_fu_1589_p3? 1'b1: 1'b0);
assign tmp_181_2_fu_2322_p2 = (flag_val_V_assign_load_1_7_fu_2112_p3 != flag_val_V_assign_load_1_10_fu_2131_p3? 1'b1: 1'b0);
assign tmp_181_2_not_fu_1770_p2 = (flag_val_V_assign_load_1_2_fu_1589_p3 != flag_val_V_assign_load_1_4_fu_1616_p3? 1'b1: 1'b0);
assign tmp_181_3_fu_2449_p2 = (flag_val_V_assign_load_1_10_reg_5709 != flag_val_V_assign_load_1_12_reg_5715? 1'b1: 1'b0);
assign tmp_181_3_not_fu_1788_p2 = (flag_val_V_assign_load_1_4_fu_1616_p3 != flag_val_V_assign_load_1_6_fu_1642_p3? 1'b1: 1'b0);
assign tmp_181_4_fu_2484_p2 = (flag_val_V_assign_load_1_12_reg_5715 != flag_val_V_assign_load_1_14_fu_2351_p3? 1'b1: 1'b0);
assign tmp_181_4_not_fu_1806_p2 = (flag_val_V_assign_load_1_6_fu_1642_p3 != flag_val_V_assign_load_1_8_fu_1670_p3? 1'b1: 1'b0);
assign tmp_181_5_fu_2506_p2 = (flag_val_V_assign_load_1_14_fu_2351_p3 != ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5? 1'b1: 1'b0);
assign tmp_181_5_not_fu_1824_p2 = (flag_val_V_assign_load_1_8_fu_1670_p3 != flag_val_V_assign_load_1_11_fu_1698_p3? 1'b1: 1'b0);
assign tmp_181_6_not_fu_1836_p2 = (flag_val_V_assign_load_1_11_fu_1698_p3 != flag_val_V_assign_load_1_13_fu_1726_p3? 1'b1: 1'b0);
assign tmp_181_7_not_fu_2044_p2 = (flag_val_V_assign_load_1_13_reg_5527 != flag_val_V_assign_load_2_s_fu_1894_p3? 1'b1: 1'b0);
assign tmp_181_8_fu_2069_p2 = (flag_val_V_assign_load_2_s_fu_1894_p3 != flag_val_V_assign_load_1_9_fu_1911_p3? 1'b1: 1'b0);
assign tmp_181_9_fu_2081_p2 = (flag_val_V_assign_load_1_9_fu_1911_p3 != flag_val_V_assign_load_1_3_fu_1930_p3? 1'b1: 1'b0);
assign tmp_181_s_fu_2265_p2 = (flag_val_V_assign_load_1_3_reg_5625 != flag_val_V_assign_load_1_5_reg_5631? 1'b1: 1'b0);
assign tmp_182_1_fu_1568_p2 = ($signed(r_V_1_1_fu_1557_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_2_fu_1595_p2 = ($signed(r_V_1_2_fu_1584_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_3_fu_1938_p2 = ($signed(r_V_1_3_reg_5472) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_4_fu_1970_p2 = ($signed(r_V_1_4_reg_5483) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_5_fu_1980_p2 = ($signed(r_V_1_5_reg_5494) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_6_fu_2139_p2 = ($signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_7_fu_2171_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_183_10_fu_2328_p2 = (flag_val_V_assign_load_1_7_fu_2112_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_11_fu_2453_p2 = (flag_val_V_assign_load_1_10_reg_5709 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_12_fu_2489_p2 = (flag_val_V_assign_load_1_12_reg_5715 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_1_fu_1758_p2 = (flag_val_V_assign_load_1_1_fu_1562_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_2_fu_1776_p2 = (flag_val_V_assign_load_1_2_fu_1589_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_3_fu_1794_p2 = (flag_val_V_assign_load_1_4_fu_1616_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_4_fu_1812_p2 = (flag_val_V_assign_load_1_6_fu_1642_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_5_fu_1830_p2 = (flag_val_V_assign_load_1_8_fu_1670_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_6_fu_1842_p2 = (flag_val_V_assign_load_1_11_fu_1698_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_7_fu_2049_p2 = (flag_val_V_assign_load_2_s_fu_1894_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_8_fu_2305_p2 = (flag_val_V_assign_load_1_5_reg_5631 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_9_fu_2087_p2 = (flag_val_V_assign_load_1_9_fu_1911_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_s_fu_2269_p2 = (flag_val_V_assign_load_1_3_reg_5625 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_184_1_fu_1574_p2 = ($signed(r_V_1_1_fu_1557_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_2_fu_1601_p2 = ($signed(r_V_1_2_fu_1584_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_3_fu_1943_p2 = ($signed(r_V_1_3_reg_5472) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_4_fu_1975_p2 = ($signed(r_V_1_4_reg_5483) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_5_fu_1985_p2 = ($signed(r_V_1_5_reg_5494) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_6_fu_2144_p2 = ($signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_7_fu_2176_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_185_10_fu_2642_p2 = (count_1_i_10_fu_2636_p3 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_11_fu_2699_p2 = (count_4_reg_5867 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_12_fu_2715_p2 = (count_1_i_12_reg_5872 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_13_fu_2743_p2 = (count_5_fu_2737_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_14_fu_2777_p2 = (count_1_i_14_reg_5898 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_15_fu_2805_p2 = (count_6_fu_2799_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_16_fu_2822_p2 = (phitmp_fu_2811_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_1_fu_2381_p2 = (count_1_i_s_reg_5753 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_2_fu_2413_p2 = (count_1_fu_2407_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_3_fu_2464_p2 = (count_1_i_2_fu_2441_p3 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_4_fu_2540_p2 = (count_2_fu_2534_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_5_fu_2570_p2 = (count_1_i_4_fu_2563_p3 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_6_fu_2620_p2 = (count_3_reg_5837 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_7_fu_2181_p2 = (count_1_i_6_reg_5665 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_8_fu_2202_p2 = (count_8_fu_2197_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_9_fu_2235_p2 = (count_1_i_8_fu_2224_p3 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_s_fu_2364_p2 = (count_s_fu_2359_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_188_1_fu_2875_p2 = ($signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) < $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_2_fu_3176_p2 = ($signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) < $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)? 1'b1: 1'b0);
assign tmp_188_3_fu_2905_p2 = ($signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) < $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_4_fu_3206_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) < $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)? 1'b1: 1'b0);
assign tmp_188_5_fu_2935_p2 = ($signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) < $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_7_fu_2965_p2 = ($signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) < $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_9_fu_3083_p2 = ($signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) < $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)? 1'b1: 1'b0);
assign tmp_188_s_fu_3146_p2 = ($signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) < $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)? 1'b1: 1'b0);
assign tmp_18_fu_1266_p2 = ($signed(r_V_fu_1260_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_192_1_fu_2995_p2 = ($signed(grp_image_filter_reg_int_s_fu_542_ap_return) < $signed(grp_image_filter_reg_int_s_fu_552_ap_return)? 1'b1: 1'b0);
assign tmp_192_2_fu_3333_p2 = ($signed(grp_image_filter_reg_int_s_fu_632_ap_return) < $signed(grp_image_filter_reg_int_s_fu_642_ap_return)? 1'b1: 1'b0);
assign tmp_192_3_fu_3025_p2 = ($signed(grp_image_filter_reg_int_s_fu_552_ap_return) < $signed(grp_image_filter_reg_int_s_fu_562_ap_return)? 1'b1: 1'b0);
assign tmp_192_4_fu_3363_p2 = ($signed(grp_image_filter_reg_int_s_fu_642_ap_return) < $signed(ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15)? 1'b1: 1'b0);
assign tmp_192_5_fu_3053_p2 = ($signed(grp_image_filter_reg_int_s_fu_562_ap_return) < $signed(grp_image_filter_reg_int_s_fu_572_ap_return)? 1'b1: 1'b0);
assign tmp_192_7_fu_3236_p2 = ($signed(ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14) < $signed(grp_image_filter_reg_int_s_fu_602_ap_return)? 1'b1: 1'b0);
assign tmp_192_9_fu_3277_p2 = ($signed(flag_d_min2_9_reg_6017) < $signed(grp_image_filter_reg_int_s_fu_622_ap_return)? 1'b1: 1'b0);
assign tmp_192_s_fu_3303_p2 = ($signed(grp_image_filter_reg_int_s_fu_622_ap_return) < $signed(grp_image_filter_reg_int_s_fu_632_ap_return)? 1'b1: 1'b0);
assign tmp_193_1_fu_2879_p3 = ((tmp_188_1_fu_2875_p2)? ap_reg_ppstg_r_V_s_reg_5271_pp0_it11: ap_reg_ppstg_r_V_2_reg_5290_pp0_it11);
assign tmp_193_2_fu_3180_p3 = ((tmp_188_2_fu_3176_p2)? ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14: ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14);
assign tmp_193_3_fu_2909_p3 = ((tmp_188_3_fu_2905_p2)? ap_reg_ppstg_r_V_3_reg_5309_pp0_it11: ap_reg_ppstg_r_V_4_reg_5328_pp0_it11);
assign tmp_193_4_fu_3210_p3 = ((tmp_188_4_fu_3206_p2)? ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14: ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign tmp_193_5_fu_2939_p3 = ((tmp_188_5_fu_2935_p2)? ap_reg_ppstg_r_V_5_reg_5348_pp0_it11: ap_reg_ppstg_r_V_6_reg_5368_pp0_it11);
assign tmp_193_7_fu_2969_p3 = ((tmp_188_7_fu_2965_p2)? ap_reg_ppstg_r_V_7_reg_5388_pp0_it11: ap_reg_ppstg_r_V_1_reg_5408_pp0_it11);
assign tmp_193_9_fu_3087_p3 = ((tmp_188_9_fu_3083_p2)? ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13: ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13);
assign tmp_193_s_fu_3150_p3 = ((tmp_188_s_fu_3146_p2)? ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14: ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14);
assign tmp_195_1_fu_2890_p2 = ($signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) > $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_2_fu_3191_p2 = ($signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) > $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)? 1'b1: 1'b0);
assign tmp_195_3_fu_2920_p2 = ($signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) > $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_4_fu_3221_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) > $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)? 1'b1: 1'b0);
assign tmp_195_5_fu_2950_p2 = ($signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) > $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_7_fu_2980_p2 = ($signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) > $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_9_fu_3098_p2 = ($signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) > $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)? 1'b1: 1'b0);
assign tmp_195_s_fu_3161_p2 = ($signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) > $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)? 1'b1: 1'b0);
assign tmp_199_1_fu_3113_p2 = ($signed(grp_image_filter_reg_int_s_fu_582_ap_return) < $signed(grp_image_filter_reg_int_s_fu_592_ap_return)? 1'b1: 1'b0);
assign tmp_199_2_fu_3604_p2 = ($signed(grp_image_filter_reg_int_s_fu_692_ap_return) < $signed(ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16)? 1'b1: 1'b0);
assign tmp_199_3_fu_3389_p2 = ($signed(grp_image_filter_reg_int_s_fu_652_ap_return) < $signed(grp_image_filter_reg_int_s_fu_662_ap_return)? 1'b1: 1'b0);
assign tmp_199_4_fu_3628_p2 = ($signed(grp_image_filter_reg_int_s_fu_702_ap_return) < $signed(flag_d_min4_3_reg_6053)? 1'b1: 1'b0);
assign tmp_199_5_fu_3500_p2 = ($signed(ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16) < $signed(grp_image_filter_reg_int_s_fu_672_ap_return)? 1'b1: 1'b0);
assign tmp_199_7_fu_3524_p2 = ($signed(flag_d_min4_7_reg_6065) < $signed(grp_image_filter_reg_int_s_fu_682_ap_return)? 1'b1: 1'b0);
assign tmp_199_9_fu_3548_p2 = ($signed(grp_image_filter_reg_int_s_fu_672_ap_return) < $signed(grp_image_filter_reg_int_s_fu_692_ap_return)? 1'b1: 1'b0);
assign tmp_199_s_fu_3576_p2 = ($signed(grp_image_filter_reg_int_s_fu_682_ap_return) < $signed(grp_image_filter_reg_int_s_fu_702_ap_return)? 1'b1: 1'b0);
assign tmp_19_fu_1272_p2 = ($signed(r_V_fu_1260_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_200_3_fu_3031_p3 = ((tmp_192_3_fu_3025_p2)? grp_image_filter_reg_int_s_fu_552_ap_return: grp_image_filter_reg_int_s_fu_562_ap_return);
assign tmp_202_1_fu_3010_p2 = ($signed(grp_image_filter_reg_int_s_fu_547_ap_return) > $signed(grp_image_filter_reg_int_s_fu_557_ap_return)? 1'b1: 1'b0);
assign tmp_202_2_fu_3348_p2 = ($signed(grp_image_filter_reg_int_s_fu_637_ap_return) > $signed(grp_image_filter_reg_int_s_fu_647_ap_return)? 1'b1: 1'b0);
assign tmp_202_3_fu_3039_p2 = ($signed(grp_image_filter_reg_int_s_fu_557_ap_return) > $signed(grp_image_filter_reg_int_s_fu_567_ap_return)? 1'b1: 1'b0);
assign tmp_202_4_fu_3376_p2 = ($signed(grp_image_filter_reg_int_s_fu_647_ap_return) > $signed(ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15)? 1'b1: 1'b0);
assign tmp_202_5_fu_3068_p2 = ($signed(grp_image_filter_reg_int_s_fu_567_ap_return) > $signed(grp_image_filter_reg_int_s_fu_577_ap_return)? 1'b1: 1'b0);
assign tmp_202_7_fu_3249_p2 = ($signed(ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14) > $signed(grp_image_filter_reg_int_s_fu_607_ap_return)? 1'b1: 1'b0);
assign tmp_202_9_fu_3290_p2 = ($signed(flag_d_max2_9_reg_6023) > $signed(grp_image_filter_reg_int_s_fu_627_ap_return)? 1'b1: 1'b0);
assign tmp_202_s_fu_3318_p2 = ($signed(grp_image_filter_reg_int_s_fu_627_ap_return) > $signed(grp_image_filter_reg_int_s_fu_637_ap_return)? 1'b1: 1'b0);
assign tmp_203_1_fu_2894_p3 = ((tmp_195_1_fu_2890_p2)? ap_reg_ppstg_r_V_s_reg_5271_pp0_it11: ap_reg_ppstg_r_V_2_reg_5290_pp0_it11);
assign tmp_203_2_fu_3195_p3 = ((tmp_195_2_fu_3191_p2)? ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14: ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14);
assign tmp_203_3_fu_2924_p3 = ((tmp_195_3_fu_2920_p2)? ap_reg_ppstg_r_V_3_reg_5309_pp0_it11: ap_reg_ppstg_r_V_4_reg_5328_pp0_it11);
assign tmp_203_4_fu_3225_p3 = ((tmp_195_4_fu_3221_p2)? ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14: ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign tmp_203_5_fu_2954_p3 = ((tmp_195_5_fu_2950_p2)? ap_reg_ppstg_r_V_5_reg_5348_pp0_it11: ap_reg_ppstg_r_V_6_reg_5368_pp0_it11);
assign tmp_203_7_fu_2984_p3 = ((tmp_195_7_fu_2980_p2)? ap_reg_ppstg_r_V_7_reg_5388_pp0_it11: ap_reg_ppstg_r_V_1_reg_5408_pp0_it11);
assign tmp_203_9_fu_3102_p3 = ((tmp_195_9_fu_3098_p2)? ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13: ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13);
assign tmp_203_s_fu_3165_p3 = ((tmp_195_s_fu_3161_p2)? ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14: ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14);
assign tmp_209_1_fu_3666_p2 = ($signed(grp_image_filter_reg_int_s_fu_712_ap_return) < $signed(flag_d_assign_2_fu_3497_p1)? 1'b1: 1'b0);
assign tmp_209_2_fu_3794_p2 = ($signed(grp_image_filter_reg_int_s_fu_722_ap_return) < $signed(flag_d_assign_4_fu_3777_p1)? 1'b1: 1'b0);
assign tmp_209_3_fu_3922_p2 = ($signed(grp_image_filter_reg_int_s_fu_732_ap_return) < $signed(flag_d_assign_6_fu_3905_p1)? 1'b1: 1'b0);
assign tmp_209_4_fu_4050_p2 = ($signed(grp_image_filter_reg_int_s_fu_742_ap_return) < $signed(flag_d_assign_8_fu_4033_p1)? 1'b1: 1'b0);
assign tmp_209_5_fu_4178_p2 = ($signed(grp_image_filter_reg_int_s_fu_752_ap_return) < $signed(flag_d_assign_s_fu_4161_p1)? 1'b1: 1'b0);
assign tmp_209_6_fu_4306_p2 = ($signed(grp_image_filter_reg_int_s_fu_762_ap_return) < $signed(flag_d_assign_11_fu_4289_p1)? 1'b1: 1'b0);
assign tmp_209_7_fu_4434_p2 = ($signed(grp_image_filter_reg_int_s_fu_772_ap_return) < $signed(flag_d_assign_13_fu_4417_p1)? 1'b1: 1'b0);
assign tmp_20_fu_1286_p2 = (tmp_18_fu_1266_p2 | tmp_19_fu_1272_p2);
assign tmp_210_2_fu_3609_p3 = ((tmp_199_2_fu_3604_p2)? grp_image_filter_reg_int_s_fu_692_ap_return: ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16);
assign tmp_210_4_fu_3633_p3 = ((tmp_199_4_fu_3628_p2)? grp_image_filter_reg_int_s_fu_702_ap_return: flag_d_min4_3_reg_6053);
assign tmp_210_5_fu_3505_p3 = ((tmp_199_5_fu_3500_p2)? ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16: grp_image_filter_reg_int_s_fu_672_ap_return);
assign tmp_210_7_fu_3529_p3 = ((tmp_199_7_fu_3524_p2)? flag_d_min4_7_reg_6065: grp_image_filter_reg_int_s_fu_682_ap_return);
assign tmp_210_9_fu_3554_p3 = ((tmp_199_9_fu_3548_p2)? grp_image_filter_reg_int_s_fu_672_ap_return: grp_image_filter_reg_int_s_fu_692_ap_return);
assign tmp_210_s_fu_3582_p3 = ((tmp_199_s_fu_3576_p2)? grp_image_filter_reg_int_s_fu_682_ap_return: grp_image_filter_reg_int_s_fu_702_ap_return);
assign tmp_212_1_fu_3128_p2 = ($signed(grp_image_filter_reg_int_s_fu_587_ap_return) > $signed(grp_image_filter_reg_int_s_fu_597_ap_return)? 1'b1: 1'b0);
assign tmp_212_2_fu_3616_p2 = ($signed(grp_image_filter_reg_int_s_fu_697_ap_return) > $signed(ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16)? 1'b1: 1'b0);
assign tmp_212_3_fu_3404_p2 = ($signed(grp_image_filter_reg_int_s_fu_657_ap_return) > $signed(grp_image_filter_reg_int_s_fu_667_ap_return)? 1'b1: 1'b0);
assign tmp_212_4_fu_3640_p2 = ($signed(grp_image_filter_reg_int_s_fu_707_ap_return) > $signed(flag_d_max4_3_reg_6059)? 1'b1: 1'b0);
assign tmp_212_5_fu_3512_p2 = ($signed(ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16) > $signed(grp_image_filter_reg_int_s_fu_677_ap_return)? 1'b1: 1'b0);
assign tmp_212_7_fu_3536_p2 = ($signed(flag_d_max4_7_reg_6071) > $signed(grp_image_filter_reg_int_s_fu_687_ap_return)? 1'b1: 1'b0);
assign tmp_212_9_fu_3562_p2 = ($signed(grp_image_filter_reg_int_s_fu_677_ap_return) > $signed(grp_image_filter_reg_int_s_fu_697_ap_return)? 1'b1: 1'b0);
assign tmp_212_s_fu_3590_p2 = ($signed(grp_image_filter_reg_int_s_fu_687_ap_return) > $signed(grp_image_filter_reg_int_s_fu_707_ap_return)? 1'b1: 1'b0);
assign tmp_213_3_fu_3045_p3 = ((tmp_202_3_fu_3039_p2)? grp_image_filter_reg_int_s_fu_557_ap_return: grp_image_filter_reg_int_s_fu_567_ap_return);
assign tmp_216_1_fu_3698_p3 = ((tmp_209_1_reg_6195)? flag_d_min8_3_reg_6115: flag_d_assign_2_reg_6109);
assign tmp_216_2_fu_3826_p3 = ((tmp_209_2_reg_6269)? flag_d_min8_5_reg_6249: flag_d_assign_4_reg_6243);
assign tmp_216_3_fu_3954_p3 = ((tmp_209_3_reg_6343)? flag_d_min8_7_reg_6323: flag_d_assign_6_reg_6317);
assign tmp_216_4_fu_4082_p3 = ((tmp_209_4_reg_6417)? flag_d_min8_9_reg_6397: flag_d_assign_8_reg_6391);
assign tmp_216_5_fu_4210_p3 = ((tmp_209_5_reg_6491)? tmp_211_s_reg_6471: flag_d_assign_s_reg_6465);
assign tmp_216_6_fu_4338_p3 = ((tmp_209_6_reg_6565)? tmp_211_1_reg_6545: flag_d_assign_11_reg_6539);
assign tmp_216_7_fu_4466_p3 = ((tmp_209_7_reg_6639)? tmp_211_2_reg_6619: flag_d_assign_13_reg_6613);
assign tmp_217_1_fu_3707_p2 = ($signed(p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1) > $signed(tmp_216_1_fu_3698_p3)? 1'b1: 1'b0);
assign tmp_217_2_fu_3835_p2 = ($signed(a0_tmp_232_1_cast_fu_3823_p1) > $signed(tmp_216_2_fu_3826_p3)? 1'b1: 1'b0);
assign tmp_217_3_fu_3963_p2 = ($signed(a0_2_tmp_232_2_cast_fu_3951_p1) > $signed(tmp_216_3_fu_3954_p3)? 1'b1: 1'b0);
assign tmp_217_4_fu_4091_p2 = ($signed(a0_3_tmp_232_3_cast_fu_4079_p1) > $signed(tmp_216_4_fu_4082_p3)? 1'b1: 1'b0);
assign tmp_217_5_fu_4219_p2 = ($signed(a0_4_tmp_232_4_cast_fu_4207_p1) > $signed(tmp_216_5_fu_4210_p3)? 1'b1: 1'b0);
assign tmp_217_6_fu_4347_p2 = ($signed(a0_5_tmp_232_5_cast_fu_4335_p1) > $signed(tmp_216_6_fu_4338_p3)? 1'b1: 1'b0);
assign tmp_217_7_fu_4475_p2 = ($signed(a0_6_tmp_232_6_cast_fu_4463_p1) > $signed(tmp_216_7_fu_4466_p3)? 1'b1: 1'b0);
assign tmp_21_fu_1527_p2 = ($signed(r_V_1_fu_1516_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_221_1_fu_3686_p2 = ($signed(grp_image_filter_reg_int_s_fu_717_ap_return) > $signed(flag_d_assign_2_fu_3497_p1)? 1'b1: 1'b0);
assign tmp_221_2_fu_3814_p2 = ($signed(grp_image_filter_reg_int_s_fu_727_ap_return) > $signed(flag_d_assign_4_fu_3777_p1)? 1'b1: 1'b0);
assign tmp_221_3_fu_3942_p2 = ($signed(grp_image_filter_reg_int_s_fu_737_ap_return) > $signed(flag_d_assign_6_fu_3905_p1)? 1'b1: 1'b0);
assign tmp_221_4_fu_4070_p2 = ($signed(grp_image_filter_reg_int_s_fu_747_ap_return) > $signed(flag_d_assign_8_fu_4033_p1)? 1'b1: 1'b0);
assign tmp_221_5_fu_4198_p2 = ($signed(grp_image_filter_reg_int_s_fu_757_ap_return) > $signed(flag_d_assign_s_fu_4161_p1)? 1'b1: 1'b0);
assign tmp_221_6_fu_4326_p2 = ($signed(grp_image_filter_reg_int_s_fu_767_ap_return) > $signed(flag_d_assign_11_fu_4289_p1)? 1'b1: 1'b0);
assign tmp_221_7_fu_4454_p2 = ($signed(grp_image_filter_reg_int_s_fu_777_ap_return) > $signed(flag_d_assign_13_fu_4417_p1)? 1'b1: 1'b0);
assign tmp_225_2_fu_3621_p3 = ((tmp_212_2_fu_3616_p2)? grp_image_filter_reg_int_s_fu_697_ap_return: ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16);
assign tmp_225_4_fu_3645_p3 = ((tmp_212_4_fu_3640_p2)? grp_image_filter_reg_int_s_fu_707_ap_return: flag_d_max4_3_reg_6059);
assign tmp_225_5_fu_3517_p3 = ((tmp_212_5_fu_3512_p2)? ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16: grp_image_filter_reg_int_s_fu_677_ap_return);
assign tmp_225_7_fu_3541_p3 = ((tmp_212_7_fu_3536_p2)? flag_d_max4_7_reg_6071: grp_image_filter_reg_int_s_fu_687_ap_return);
assign tmp_225_9_fu_3568_p3 = ((tmp_212_9_fu_3562_p2)? grp_image_filter_reg_int_s_fu_677_ap_return: grp_image_filter_reg_int_s_fu_697_ap_return);
assign tmp_225_s_fu_3596_p3 = ((tmp_212_s_fu_3590_p2)? grp_image_filter_reg_int_s_fu_687_ap_return: grp_image_filter_reg_int_s_fu_707_ap_return);
assign tmp_227_1_fu_3739_p3 = ((tmp_221_1_reg_6206)? flag_d_max8_3_reg_6122: flag_d_assign_2_reg_6109);
assign tmp_227_2_fu_3867_p3 = ((tmp_221_2_reg_6280)? flag_d_max8_5_reg_6256: flag_d_assign_4_reg_6243);
assign tmp_227_3_fu_3995_p3 = ((tmp_221_3_reg_6354)? flag_d_max8_7_reg_6330: flag_d_assign_6_reg_6317);
assign tmp_227_4_fu_4123_p3 = ((tmp_221_4_reg_6428)? flag_d_max8_9_reg_6404: flag_d_assign_8_reg_6391);
assign tmp_227_5_fu_4251_p3 = ((tmp_221_5_reg_6502)? tmp_226_s_reg_6478: flag_d_assign_s_reg_6465);
assign tmp_227_6_fu_4379_p3 = ((tmp_221_6_reg_6576)? tmp_226_1_reg_6552: flag_d_assign_11_reg_6539);
assign tmp_227_7_fu_4507_p3 = ((tmp_221_7_reg_6650)? tmp_226_2_reg_6626: flag_d_assign_13_reg_6613);
assign tmp_228_1_fu_3748_p2 = ($signed(b0_tmp_239_cast_fu_3736_p1) < $signed(tmp_227_1_fu_3739_p3)? 1'b1: 1'b0);
assign tmp_228_2_fu_3876_p2 = ($signed(b0_tmp_239_1_cast_fu_3864_p1) < $signed(tmp_227_2_fu_3867_p3)? 1'b1: 1'b0);
assign tmp_228_3_fu_4004_p2 = ($signed(b0_2_tmp_239_2_cast_fu_3992_p1) < $signed(tmp_227_3_fu_3995_p3)? 1'b1: 1'b0);
assign tmp_228_4_fu_4132_p2 = ($signed(b0_3_tmp_239_3_cast_fu_4120_p1) < $signed(tmp_227_4_fu_4123_p3)? 1'b1: 1'b0);
assign tmp_228_5_fu_4260_p2 = ($signed(b0_4_tmp_239_4_cast_fu_4248_p1) < $signed(tmp_227_5_fu_4251_p3)? 1'b1: 1'b0);
assign tmp_228_6_fu_4388_p2 = ($signed(b0_5_tmp_239_5_cast_fu_4376_p1) < $signed(tmp_227_6_fu_4379_p3)? 1'b1: 1'b0);
assign tmp_228_7_fu_4516_p2 = ($signed(b0_6_tmp_239_6_cast_fu_4504_p1) < $signed(tmp_227_7_fu_4507_p3)? 1'b1: 1'b0);
assign tmp_22_fu_1533_p2 = ($signed(r_V_1_fu_1516_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_231_1_fu_3720_p2 = ($signed(flag_d_min8_3_reg_6115) < $signed(flag_d_assign_10_fu_3692_p1)? 1'b1: 1'b0);
assign tmp_231_2_fu_3848_p2 = ($signed(flag_d_min8_5_reg_6249) < $signed(flag_d_assign_12_fu_3820_p1)? 1'b1: 1'b0);
assign tmp_231_3_fu_3976_p2 = ($signed(flag_d_min8_7_reg_6323) < $signed(flag_d_assign_14_fu_3948_p1)? 1'b1: 1'b0);
assign tmp_231_4_fu_4104_p2 = ($signed(flag_d_min8_9_reg_6397) < $signed(flag_d_assign_1_fu_4076_p1)? 1'b1: 1'b0);
assign tmp_231_5_fu_4232_p2 = ($signed(tmp_211_s_reg_6471) < $signed(flag_d_assign_3_fu_4204_p1)? 1'b1: 1'b0);
assign tmp_231_6_fu_4360_p2 = ($signed(tmp_211_1_reg_6545) < $signed(flag_d_assign_5_fu_4332_p1)? 1'b1: 1'b0);
assign tmp_231_7_fu_4488_p2 = ($signed(tmp_211_2_reg_6619) < $signed(flag_d_assign_7_fu_4460_p1)? 1'b1: 1'b0);
assign tmp_232_1_fu_3725_p3 = ((tmp_231_1_fu_3720_p2)? flag_d_min8_3_reg_6115: flag_d_assign_10_fu_3692_p1);
assign tmp_232_2_fu_3853_p3 = ((tmp_231_2_fu_3848_p2)? flag_d_min8_5_reg_6249: flag_d_assign_12_fu_3820_p1);
assign tmp_232_3_fu_3981_p3 = ((tmp_231_3_fu_3976_p2)? flag_d_min8_7_reg_6323: flag_d_assign_14_fu_3948_p1);
assign tmp_232_4_fu_4109_p3 = ((tmp_231_4_fu_4104_p2)? flag_d_min8_9_reg_6397: flag_d_assign_1_fu_4076_p1);
assign tmp_232_5_fu_4237_p3 = ((tmp_231_5_fu_4232_p2)? tmp_211_s_reg_6471: flag_d_assign_3_fu_4204_p1);
assign tmp_232_6_fu_4365_p3 = ((tmp_231_6_fu_4360_p2)? tmp_211_1_reg_6545: flag_d_assign_5_fu_4332_p1);
assign tmp_232_7_fu_4493_p3 = ((tmp_231_7_fu_4488_p2)? tmp_211_2_reg_6619: flag_d_assign_7_fu_4460_p1);
assign tmp_233_1_fu_3783_p2 = ($signed(a0_cast_fu_3780_p1) > $signed(tmp_232_1_reg_6217)? 1'b1: 1'b0);
assign tmp_233_2_fu_3911_p2 = ($signed(a0_2_cast_fu_3908_p1) > $signed(tmp_232_2_reg_6291)? 1'b1: 1'b0);
assign tmp_233_3_fu_4039_p2 = ($signed(a0_3_cast_fu_4036_p1) > $signed(tmp_232_3_reg_6365)? 1'b1: 1'b0);
assign tmp_233_4_fu_4167_p2 = ($signed(a0_4_cast_fu_4164_p1) > $signed(tmp_232_4_reg_6439)? 1'b1: 1'b0);
assign tmp_233_5_fu_4295_p2 = ($signed(a0_5_cast_fu_4292_p1) > $signed(tmp_232_5_reg_6513)? 1'b1: 1'b0);
assign tmp_233_6_fu_4423_p2 = ($signed(a0_6_cast_fu_4420_p1) > $signed(tmp_232_6_reg_6587)? 1'b1: 1'b0);
assign tmp_233_7_fu_4552_p2 = ($signed(a0_7_cast_fu_4549_p1) > $signed(tmp_232_7_reg_6661)? 1'b1: 1'b0);
assign tmp_236_1_fu_3761_p2 = ($signed(flag_d_max8_3_reg_6122) > $signed(flag_d_assign_10_fu_3692_p1)? 1'b1: 1'b0);
assign tmp_236_2_fu_3889_p2 = ($signed(flag_d_max8_5_reg_6256) > $signed(flag_d_assign_12_fu_3820_p1)? 1'b1: 1'b0);
assign tmp_236_3_fu_4017_p2 = ($signed(flag_d_max8_7_reg_6330) > $signed(flag_d_assign_14_fu_3948_p1)? 1'b1: 1'b0);
assign tmp_236_4_fu_4145_p2 = ($signed(flag_d_max8_9_reg_6404) > $signed(flag_d_assign_1_fu_4076_p1)? 1'b1: 1'b0);
assign tmp_236_5_fu_4273_p2 = ($signed(tmp_226_s_reg_6478) > $signed(flag_d_assign_3_fu_4204_p1)? 1'b1: 1'b0);
assign tmp_236_6_fu_4401_p2 = ($signed(tmp_226_1_reg_6552) > $signed(flag_d_assign_5_fu_4332_p1)? 1'b1: 1'b0);
assign tmp_236_7_fu_4529_p2 = ($signed(tmp_226_2_reg_6626) > $signed(flag_d_assign_7_fu_4460_p1)? 1'b1: 1'b0);
assign tmp_239_1_fu_3766_p3 = ((tmp_236_1_fu_3761_p2)? flag_d_max8_3_reg_6122: flag_d_assign_10_fu_3692_p1);
assign tmp_239_2_fu_3894_p3 = ((tmp_236_2_fu_3889_p2)? flag_d_max8_5_reg_6256: flag_d_assign_12_fu_3820_p1);
assign tmp_239_3_fu_4022_p3 = ((tmp_236_3_fu_4017_p2)? flag_d_max8_7_reg_6330: flag_d_assign_14_fu_3948_p1);
assign tmp_239_4_fu_4150_p3 = ((tmp_236_4_fu_4145_p2)? flag_d_max8_9_reg_6404: flag_d_assign_1_fu_4076_p1);
assign tmp_239_5_fu_4278_p3 = ((tmp_236_5_fu_4273_p2)? tmp_226_s_reg_6478: flag_d_assign_3_fu_4204_p1);
assign tmp_239_6_fu_4406_p3 = ((tmp_236_6_fu_4401_p2)? tmp_226_1_reg_6552: flag_d_assign_5_fu_4332_p1);
assign tmp_239_7_fu_4534_p3 = ((tmp_236_7_fu_4529_p2)? tmp_226_2_reg_6626: flag_d_assign_7_fu_4460_p1);
assign tmp_23_fu_1547_p2 = (tmp_21_fu_1527_p2 | tmp_22_fu_1533_p2);
assign tmp_240_1_fu_3803_p2 = ($signed(b0_cast_50_fu_3800_p1) < $signed(tmp_239_1_reg_6233)? 1'b1: 1'b0);
assign tmp_240_2_fu_3931_p2 = ($signed(b0_2_cast_fu_3928_p1) < $signed(tmp_239_2_reg_6307)? 1'b1: 1'b0);
assign tmp_240_3_fu_4059_p2 = ($signed(b0_3_cast_fu_4056_p1) < $signed(tmp_239_3_reg_6381)? 1'b1: 1'b0);
assign tmp_240_4_fu_4187_p2 = ($signed(b0_4_cast_fu_4184_p1) < $signed(tmp_239_4_reg_6455)? 1'b1: 1'b0);
assign tmp_240_5_fu_4315_p2 = ($signed(b0_5_cast_fu_4312_p1) < $signed(tmp_239_5_reg_6529)? 1'b1: 1'b0);
assign tmp_240_6_fu_4443_p2 = ($signed(b0_6_cast_fu_4440_p1) < $signed(tmp_239_6_reg_6603)? 1'b1: 1'b0);
assign tmp_240_7_fu_4566_p2 = ($signed(b0_7_cast_fu_4563_p1) < $signed(tmp_239_7_reg_6676)? 1'b1: 1'b0);
assign tmp_242_1_fu_4659_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_1_fu_140)? 1'b1: 1'b0);
assign tmp_242_2_fu_4665_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_2_fu_4620_p1)? 1'b1: 1'b0);
assign tmp_245_1_fu_4677_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_1_fu_164)? 1'b1: 1'b0);
assign tmp_245_2_fu_4683_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_1_2_fu_4643_p1)? 1'b1: 1'b0);
assign tmp_24_fu_1322_p2 = (tmp_176_1_fu_1302_p2 | tmp_177_1_fu_1308_p2);
assign tmp_25_fu_1907_p2 = (tmp_182_1_reg_5441 | tmp_184_1_reg_5447);
assign tmp_26_fu_4779_p2 = (tmp22_fu_4775_p2 & tmp18_fu_4771_p2);
assign tmp_27_fu_1358_p2 = (tmp_176_2_fu_1338_p2 | tmp_177_2_fu_1344_p2);
assign tmp_28_fu_1926_p2 = (tmp_182_2_reg_5461 | tmp_184_2_reg_5467);
assign tmp_29_fu_1394_p2 = (tmp_176_3_fu_1374_p2 | tmp_177_3_fu_1380_p2);
assign tmp_30_fu_1956_p2 = (tmp_182_3_fu_1938_p2 | tmp_184_3_fu_1943_p2);
assign tmp_31_fu_1638_p2 = (tmp_176_4_reg_5337 | tmp_177_4_reg_5343);
assign tmp_32_fu_2108_p2 = (tmp_182_4_reg_5638 | tmp_184_4_reg_5644);
assign tmp_33_fu_1666_p2 = (tmp_176_5_reg_5357 | tmp_177_5_reg_5363);
assign tmp_34_fu_2127_p2 = (tmp_182_5_reg_5649 | tmp_184_5_reg_5655);
assign tmp_35_fu_1694_p2 = (tmp_176_6_reg_5377 | tmp_177_6_reg_5383);
assign tmp_36_fu_2157_p2 = (tmp_182_6_fu_2139_p2 | tmp_184_6_fu_2144_p2);
assign tmp_37_fu_1722_p2 = (tmp_176_7_reg_5397 | tmp_177_7_reg_5403);
assign tmp_38_fu_2347_p2 = (tmp_182_7_reg_5722 | tmp_184_7_reg_5728);
assign tmp_39_fu_1740_p2 = (flag_val_V_assign_load_1_s_fu_1521_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_40_fu_1864_p2 = (or_cond7_fu_1782_p2 | or_cond6_fu_1764_p2);
assign tmp_41_fu_2010_p2 = (or_cond9_reg_5559 | or_cond8_reg_5553);
assign tmp_42_fu_2030_p2 = (or_cond3_fu_1994_p2 | or_cond2_fu_1990_p2);
assign tmp_43_fu_3262_p2 = ($signed(grp_image_filter_reg_int_s_fu_612_ap_return) < $signed(flag_d_assign_fu_3143_p1)? 1'b1: 1'b0);
assign tmp_44_fu_3424_p1 = a_0_flag_d_assign_load_5_fu_3419_p3[7:0];
assign tmp_45_fu_3428_p2 = ($signed(a_0_flag_d_assign_load_5_fu_3419_p3) < $signed(32'b10100)? 1'b1: 1'b0);
assign tmp_46_fu_3442_p2 = ($signed(flag_d_min8_1_reg_6029) < $signed(flag_d_assign_9_fu_3274_p1)? 1'b1: 1'b0);
assign tmp_47_fu_3447_p3 = ((tmp_46_fu_3442_p2)? flag_d_min8_1_reg_6029: flag_d_assign_9_fu_3274_p1);
assign tmp_48_fu_3454_p1 = tmp_47_fu_3447_p3[7:0];
assign tmp_49_fu_3655_p2 = ($signed(p_a_0_flag_d_assign_load_5_cast_fu_3652_p1) > $signed(tmp_47_reg_6083)? 1'b1: 1'b0);
assign tmp_50_fu_4583_p2 = (ap_const_lv8_0 - tmp_79_reg_6697);
assign tmp_51_fu_4588_p2 = (a0_7_tmp_232_7_reg_6691 > tmp_50_fu_4583_p2? 1'b1: 1'b0);
assign tmp_52_fu_4647_p2 = (core_win_val_1_V_1_fu_152 != ap_const_lv16_0? 1'b1: 1'b0);
assign tmp_53_fu_4600_p2 = (ap_reg_ppstg_p_2_reg_515_pp0_it31 > ap_const_lv11_6? 1'b1: 1'b0);
assign tmp_54_fu_4689_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_1_V_0_fu_148)? 1'b1: 1'b0);
assign tmp_55_fu_4695_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_1_V_2_fu_4623_p1)? 1'b1: 1'b0);
assign tmp_56_fu_3703_p1 = tmp_216_1_fu_3698_p3[7:0];
assign tmp_57_fu_3732_p1 = tmp_232_1_fu_3725_p3[7:0];
assign tmp_58_fu_3831_p1 = tmp_216_2_fu_3826_p3[7:0];
assign tmp_59_fu_3860_p1 = tmp_232_2_fu_3853_p3[7:0];
assign tmp_5_fu_796_p2 = (tmp_fu_782_p1 + ap_const_lv11_4);
assign tmp_60_fu_3959_p1 = tmp_216_3_fu_3954_p3[7:0];
assign tmp_61_fu_3988_p1 = tmp_232_3_fu_3981_p3[7:0];
assign tmp_62_fu_4087_p1 = tmp_216_4_fu_4082_p3[7:0];
assign tmp_63_fu_4116_p1 = tmp_232_4_fu_4109_p3[7:0];
assign tmp_64_fu_4215_p1 = tmp_216_5_fu_4210_p3[7:0];
assign tmp_65_fu_4244_p1 = tmp_232_5_fu_4237_p3[7:0];
assign tmp_66_fu_4343_p1 = tmp_216_6_fu_4338_p3[7:0];
assign tmp_67_fu_3268_p2 = ($signed(grp_image_filter_reg_int_s_fu_617_ap_return) > $signed(flag_d_assign_fu_3143_p1)? 1'b1: 1'b0);
assign tmp_68_fu_3458_p3 = ((tmp_67_reg_6048)? flag_d_max8_1_reg_6036: flag_d_assign_reg_6011);
assign tmp_69_fu_3467_p2 = ($signed(tmp_68_fu_3458_p3) > $signed(32'b11111111111111111111111111101100)? 1'b1: 1'b0);
assign tmp_70_fu_3481_p2 = ($signed(flag_d_max8_1_reg_6036) > $signed(flag_d_assign_9_fu_3274_p1)? 1'b1: 1'b0);
assign tmp_71_fu_3486_p3 = ((tmp_70_fu_3481_p2)? flag_d_max8_1_reg_6036: flag_d_assign_9_fu_3274_p1);
assign tmp_72_fu_3675_p2 = ($signed(b0_cast_fu_3672_p1) < $signed(tmp_71_reg_6099)? 1'b1: 1'b0);
assign tmp_73_fu_4653_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_0_fu_136)? 1'b1: 1'b0);
assign tmp_74_fu_4671_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_0_fu_160)? 1'b1: 1'b0);
assign tmp_75_fu_4372_p1 = tmp_232_6_fu_4365_p3[7:0];
assign tmp_77_fu_4471_p1 = tmp_216_7_fu_4466_p3[7:0];
assign tmp_78_fu_4500_p1 = tmp_232_7_fu_4493_p3[7:0];
assign tmp_79_fu_4571_p3 = ((tmp_240_7_fu_4566_p2)? tmp_95_reg_6681: tmp_96_reg_6686);
assign tmp_7_fu_813_p2 = (p_s_reg_504 < tmp_reg_5098? 1'b1: 1'b0);
assign tmp_80_fu_3463_p1 = tmp_68_fu_3458_p3[8:0];
assign tmp_81_fu_3493_p1 = tmp_71_fu_3486_p3[8:0];
assign tmp_82_fu_3744_p1 = tmp_227_1_fu_3739_p3[8:0];
assign tmp_83_fu_3773_p1 = tmp_239_1_fu_3766_p3[8:0];
assign tmp_84_fu_3872_p1 = tmp_227_2_fu_3867_p3[8:0];
assign tmp_85_fu_3901_p1 = tmp_239_2_fu_3894_p3[8:0];
assign tmp_86_fu_4000_p1 = tmp_227_3_fu_3995_p3[8:0];
assign tmp_87_fu_4029_p1 = tmp_239_3_fu_4022_p3[8:0];
assign tmp_88_fu_4128_p1 = tmp_227_4_fu_4123_p3[8:0];
assign tmp_89_fu_4157_p1 = tmp_239_4_fu_4150_p3[8:0];
assign tmp_8_fu_818_p2 = (p_s_reg_504 > ap_const_lv11_5? 1'b1: 1'b0);
assign tmp_90_fu_4256_p1 = tmp_227_5_fu_4251_p3[8:0];
assign tmp_91_fu_4285_p1 = tmp_239_5_fu_4278_p3[8:0];
assign tmp_92_fu_4384_p1 = tmp_227_6_fu_4379_p3[8:0];
assign tmp_93_fu_4413_p1 = tmp_239_6_fu_4406_p3[8:0];
assign tmp_94_fu_4512_p1 = tmp_227_7_fu_4507_p3[8:0];
assign tmp_95_fu_4541_p1 = b0_7_fu_4522_p3[7:0];
assign tmp_96_fu_4545_p1 = tmp_239_7_fu_4534_p3[7:0];
assign tmp_97_fu_888_p4 = {{p_2_phi_fu_519_p4[ap_const_lv32_A : ap_const_lv32_2]}};
assign tmp_9_fu_824_p2 = (p_s_reg_504 > ap_const_lv11_6? 1'b1: 1'b0);
assign tmp_fu_782_p1 = p_src_rows_V_read[10:0];
assign tmp_s_fu_790_p2 = (tmp_15_fu_786_p1 + ap_const_lv11_4);
always @ (posedge ap_clk)
begin
lhs_V_reg_5240[8] <= 1'b0;
count_1_i_0_op_op87_op_reg_5590[3:1] <= 3'b100;
phitmp43_op_op_cast_cast_cast_reg_5595[3:1] <= 3'b011;
core_win_val_0_V_0_fu_136[15:8] <= 8'b00000000;
core_win_val_0_V_1_fu_140[15:8] <= 8'b00000000;
core_win_val_1_V_0_fu_148[15:8] <= 8'b00000000;
core_win_val_1_V_1_fu_152[15:8] <= 8'b00000000;
core_win_val_2_V_0_fu_160[15:8] <= 8'b00000000;
core_win_val_2_V_1_fu_164[15:8] <= 8'b00000000;
end
endmodule //image_filter_FAST_t_opr
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Eqdep JMeq List.
Require Import Cpdt.CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{Reasoning About Equality Proofs}% *)
(** In traditional mathematics, the concept of equality is usually taken as a given. On the other hand, in type theory, equality is a very contentious subject. There are at least three different notions of equality that are important in Coq, and researchers are actively investigating new definitions of what it means for two terms to be equal. Even once we fix a notion of equality, there are inevitably tricky issues that arise in proving properties of programs that manipulate equality proofs explicitly. In this chapter, I will focus on design patterns for circumventing these tricky issues, and I will introduce the different notions of equality as they are germane. *)
(** * The Definitional Equality *)
(** We have seen many examples so far where proof goals follow "by computation." That is, we apply computational reduction rules to reduce the goal to a normal form, at which point it follows trivially. Exactly when this works and when it does not depends on the details of Coq's%\index{definitional equality}% _definitional equality_. This is an untyped binary relation appearing in the formal metatheory of CIC. CIC contains a typing rule allowing the conclusion [E : T] from the premise [E : T'] and a proof that [T] and [T'] are definitionally equal.
The %\index{tactics!cbv}%[cbv] tactic will help us illustrate the rules of Coq's definitional equality. We redefine the natural number predecessor function in a somewhat convoluted way and construct a manual proof that it returns [0] when applied to [1]. *)
Definition pred' (x : nat) :=
match x with
| O => O
| S n' => let y := n' in y
end.
Theorem reduce_me : pred' 1 = 0.
(* begin thide *)
(** CIC follows the traditions of lambda calculus in associating reduction rules with Greek letters. Coq can certainly be said to support the familiar alpha reduction rule, which allows capture-avoiding renaming of bound variables, but we never need to apply alpha explicitly, since Coq uses a de Bruijn representation%~\cite{DeBruijn}% that encodes terms canonically.
The %\index{delta reduction}%delta rule is for unfolding global definitions. We can use it here to unfold the definition of [pred']. We do this with the [cbv] tactic, which takes a list of reduction rules and makes as many call-by-value reduction steps as possible, using only those rules. There is an analogous tactic %\index{tactics!lazy}%[lazy] for call-by-need reduction. *)
cbv delta.
(** %\vspace{-.15in}%[[
============================
(fun x : nat => match x with
| 0 => 0
| S n' => let y := n' in y
end) 1 = 0
]]
At this point, we want to apply the famous %\index{beta reduction}%beta reduction of lambda calculus, to simplify the application of a known function abstraction. *)
cbv beta.
(** %\vspace{-.15in}%[[
============================
match 1 with
| 0 => 0
| S n' => let y := n' in y
end = 0
]]
Next on the list is the %\index{iota reduction}%iota reduction, which simplifies a single [match] term by determining which pattern matches. *)
cbv iota.
(** %\vspace{-.15in}%[[
============================
(fun n' : nat => let y := n' in y) 0 = 0
]]
Now we need another beta reduction. *)
cbv beta.
(** %\vspace{-.15in}%[[
============================
(let y := 0 in y) = 0
]]
The final reduction rule is %\index{zeta reduction}%zeta, which replaces a [let] expression by its body with the appropriate term substituted. *)
cbv zeta.
(** %\vspace{-.15in}%[[
============================
0 = 0
]]
*)
reflexivity.
Qed.
(* end thide *)
(** The [beta] reduction rule applies to recursive functions as well, and its behavior may be surprising in some instances. For instance, we can run some simple tests using the reduction strategy [compute], which applies all applicable rules of the definitional equality. *)
Definition id (n : nat) := n.
Eval compute in fun x => id x.
(** %\vspace{-.15in}%[[
= fun x : nat => x
]]
*)
Fixpoint id' (n : nat) := n.
Eval compute in fun x => id' x.
(** %\vspace{-.15in}%[[
= fun x : nat => (fix id' (n : nat) : nat := n) x
]]
By running [compute], we ask Coq to run reduction steps until no more apply, so why do we see an application of a known function, where clearly no beta reduction has been performed? The answer has to do with ensuring termination of all Gallina programs. One candidate rule would say that we apply recursive definitions wherever possible. However, this would clearly lead to nonterminating reduction sequences, since the function may appear fully applied within its own definition, and we would %\%naive%{}%ly "simplify" such applications immediately. Instead, Coq only applies the beta rule for a recursive function when _the top-level structure of the recursive argument is known_. For [id'] above, we have only one argument [n], so clearly it is the recursive argument, and the top-level structure of [n] is known when the function is applied to [O] or to some [S e] term. The variable [x] is neither, so reduction is blocked.
What are recursive arguments in general? Every recursive function is compiled by Coq to a %\index{Gallina terms!fix}%[fix] expression, for anonymous definition of recursive functions. Further, every [fix] with multiple arguments has one designated as the recursive argument via a [struct] annotation. The recursive argument is the one that must decrease across recursive calls, to appease Coq's termination checker. Coq will generally infer which argument is recursive, though we may also specify it manually, if we want to tweak reduction behavior. For instance, consider this definition of a function to add two lists of [nat]s elementwise: *)
Fixpoint addLists (ls1 ls2 : list nat) : list nat :=
match ls1, ls2 with
| n1 :: ls1' , n2 :: ls2' => n1 + n2 :: addLists ls1' ls2'
| _, _ => nil
end.
(** By default, Coq chooses [ls1] as the recursive argument. We can see that [ls2] would have been another valid choice. The choice has a critical effect on reduction behavior, as these two examples illustrate: *)
Eval compute in fun ls => addLists nil ls.
(** %\vspace{-.15in}%[[
= fun _ : list nat => nil
]]
*)
Eval compute in fun ls => addLists ls nil.
(** %\vspace{-.15in}%[[
= fun ls : list nat =>
(fix addLists (ls1 ls2 : list nat) : list nat :=
match ls1 with
| nil => nil
| n1 :: ls1' =>
match ls2 with
| nil => nil
| n2 :: ls2' =>
(fix plus (n m : nat) : nat :=
match n with
| 0 => m
| S p => S (plus p m)
end) n1 n2 :: addLists ls1' ls2'
end
end) ls nil
]]
The outer application of the [fix] expression for [addLists] was only simplified in the first case, because in the second case the recursive argument is [ls], whose top-level structure is not known.
The opposite behavior pertains to a version of [addLists] with [ls2] marked as recursive. *)
Fixpoint addLists' (ls1 ls2 : list nat) {struct ls2} : list nat :=
match ls1, ls2 with
| n1 :: ls1' , n2 :: ls2' => n1 + n2 :: addLists' ls1' ls2'
| _, _ => nil
end.
(* begin hide *)
(* begin thide *)
Definition foo := (@eq, plus).
(* end thide *)
(* end hide *)
Eval compute in fun ls => addLists' ls nil.
(** %\vspace{-.15in}%[[
= fun ls : list nat => match ls with
| nil => nil
| _ :: _ => nil
end
]]
We see that all use of recursive functions has been eliminated, though the term has not quite simplified to [nil]. We could get it to do so by switching the order of the [match] discriminees in the definition of [addLists'].
Recall that co-recursive definitions have a dual rule: a co-recursive call only simplifies when it is the discriminee of a [match]. This condition is built into the beta rule for %\index{Gallina terms!cofix}%[cofix], the anonymous form of [CoFixpoint].
%\medskip%
The standard [eq] relation is critically dependent on the definitional equality. The relation [eq] is often called a%\index{propositional equality}% _propositional equality_, because it reifies definitional equality as a proposition that may or may not hold. Standard axiomatizations of an equality predicate in first-order logic define equality in terms of properties it has, like reflexivity, symmetry, and transitivity. In contrast, for [eq] in Coq, those properties are implicit in the properties of the definitional equality, which are built into CIC's metatheory and the implementation of Gallina. We could add new rules to the definitional equality, and [eq] would keep its definition and methods of use.
This all may make it sound like the choice of [eq]'s definition is unimportant. To the contrary, in this chapter, we will see examples where alternate definitions may simplify proofs. Before that point, I will introduce proof methods for goals that use proofs of the standard propositional equality "as data." *)
(** * Heterogeneous Lists Revisited *)
(** One of our example dependent data structures from the last chapter (code repeated below) was the heterogeneous list and its associated "cursor" type. The recursive version poses some special challenges related to equality proofs, since it uses such proofs in its definition of [fmember] types. *)
Section fhlist.
Variable A : Type.
Variable B : A -> Type.
Fixpoint fhlist (ls : list A) : Type :=
match ls with
| nil => unit
| x :: ls' => B x * fhlist ls'
end%type.
Variable elm : A.
Fixpoint fmember (ls : list A) : Type :=
match ls with
| nil => Empty_set
| x :: ls' => (x = elm) + fmember ls'
end%type.
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls return fhlist ls -> fmember ls -> B elm with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl pf => match pf with
| eq_refl => fst mls
end
| inr idx' => fhget ls' (snd mls) idx'
end
end.
End fhlist.
Arguments fhget [A B elm ls] _ _.
(* begin hide *)
(* begin thide *)
Definition map := O.
(* end thide *)
(* end hide *)
(** We can define a [map]-like function for [fhlist]s. *)
Section fhlist_map.
Variables A : Type.
Variables B C : A -> Type.
Variable f : forall x, B x -> C x.
Fixpoint fhmap (ls : list A) : fhlist B ls -> fhlist C ls :=
match ls return fhlist B ls -> fhlist C ls with
| nil => fun _ => tt
| _ :: _ => fun hls => (f (fst hls), fhmap _ (snd hls))
end.
Arguments fhmap [ls] _.
(* begin hide *)
(* begin thide *)
Definition ilist := O.
Definition get := O.
Definition imap := O.
(* end thide *)
(* end hide *)
(** For the inductive versions of the [ilist] definitions, we proved a lemma about the interaction of [get] and [imap]. It was a strategic choice not to attempt such a proof for the definitions that we just gave, which sets us on a collision course with the problems that are the subject of this chapter. *)
Variable elm : A.
Theorem fhget_fhmap : forall ls (mem : fmember elm ls) (hls : fhlist B ls),
fhget (fhmap hls) mem = f (fhget hls mem).
(* begin hide *)
induction ls; crush; case a0; reflexivity.
(* end hide *)
(** %\vspace{-.2in}%[[
induction ls; crush.
]]
%\vspace{-.15in}%In Coq 8.2, one subgoal remains at this point. Coq 8.3 has added some tactic improvements that enable [crush] to complete all of both inductive cases. To introduce the basics of reasoning about equality, it will be useful to review what was necessary in Coq 8.2.
Part of our single remaining subgoal is:
[[
a0 : a = elm
============================
match a0 in (_ = a2) return (C a2) with
| eq_refl => f a1
end = f match a0 in (_ = a2) return (B a2) with
| eq_refl => a1
end
]]
This seems like a trivial enough obligation. The equality proof [a0] must be [eq_refl], the only constructor of [eq]. Therefore, both the [match]es reduce to the point where the conclusion follows by reflexivity.
[[
destruct a0.
]]
<<
User error: Cannot solve a second-order unification problem
>>
This is one of Coq's standard error messages for informing us of a failure in its heuristics for attempting an instance of an undecidable problem about dependent typing. We might try to nudge things in the right direction by stating the lemma that we believe makes the conclusion trivial.
[[
assert (a0 = eq_refl _).
]]
<<
The term "eq_refl ?98" has type "?98 = ?98"
while it is expected to have type "a = elm"
>>
In retrospect, the problem is not so hard to see. Reflexivity proofs only show [x = x] for particular values of [x], whereas here we are thinking in terms of a proof of [a = elm], where the two sides of the equality are not equal syntactically. Thus, the essential lemma we need does not even type-check!
Is it time to throw in the towel? Luckily, the answer is "no." In this chapter, we will see several useful patterns for proving obligations like this.
For this particular example, the solution is surprisingly straightforward. The [destruct] tactic has a simpler sibling [case] which should behave identically for any inductive type with one constructor of no arguments.
[[
case a0.
============================
f a1 = f a1
]]
It seems that [destruct] was trying to be too smart for its own good.
[[
reflexivity.
]]
%\vspace{-.2in}% *)
Qed.
(* end thide *)
(** It will be helpful to examine the proof terms generated by this sort of strategy. A simpler example illustrates what is going on. *)
Lemma lemma1 : forall x (pf : x = elm), O = match pf with eq_refl => O end.
(* begin thide *)
simple destruct pf; reflexivity.
Qed.
(* end thide *)
(** The tactic %\index{tactics!simple destruct}%[simple destruct pf] is a convenient form for applying [case]. It runs [intro] to bring into scope all quantified variables up to its argument. *)
Print lemma1.
(** %\vspace{-.15in}% [[
lemma1 =
fun (x : A) (pf : x = elm) =>
match pf as e in (_ = y) return (0 = match e with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end
: forall (x : A) (pf : x = elm), 0 = match pf with
| eq_refl => 0
end
]]
Using what we know about shorthands for [match] annotations, we can write this proof in shorter form manually. *)
(* begin thide *)
Definition lemma1' (x : A) (pf : x = elm) :=
match pf return (0 = match pf with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end.
(* end thide *)
(** Surprisingly, what seems at first like a _simpler_ lemma is harder to prove. *)
Lemma lemma2 : forall (x : A) (pf : x = x), O = match pf with eq_refl => O end.
(* begin thide *)
(** %\vspace{-.25in}%[[
simple destruct pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
*)
Abort.
(** Nonetheless, we can adapt the last manual proof to handle this theorem. *)
(* begin thide *)
Definition lemma2 :=
fun (x : A) (pf : x = x) =>
match pf return (0 = match pf with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end.
(* end thide *)
(** We can try to prove a lemma that would simplify proofs of many facts like [lemma2]: *)
(* begin hide *)
(* begin thide *)
Definition lemma3' := O.
(* end thide *)
(* end hide *)
Lemma lemma3 : forall (x : A) (pf : x = x), pf = eq_refl x.
(* begin thide *)
(** %\vspace{-.25in}%[[
simple destruct pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
%\vspace{-.15in}%*)
Abort.
(** This time, even our manual attempt fails.
[[
Definition lemma3' :=
fun (x : A) (pf : x = x) =>
match pf as pf' in (_ = x') return (pf' = eq_refl x') with
| eq_refl => eq_refl _
end.
]]
<<
The term "eq_refl x'" has type "x' = x'" while it is expected to have type
"x = x'"
>>
The type error comes from our [return] annotation. In that annotation, the [as]-bound variable [pf'] has type [x = x'], referring to the [in]-bound variable [x']. To do a dependent [match], we _must_ choose a fresh name for the second argument of [eq]. We are just as constrained to use the "real" value [x] for the first argument. Thus, within the [return] clause, the proof we are matching on _must_ equate two non-matching terms, which makes it impossible to equate that proof with reflexivity.
Nonetheless, it turns out that, with one catch, we _can_ prove this lemma. *)
Lemma lemma3 : forall (x : A) (pf : x = x), pf = eq_refl x.
intros; apply UIP_refl.
Qed.
Check UIP_refl.
(** %\vspace{-.15in}% [[
UIP_refl
: forall (U : Type) (x : U) (p : x = x), p = eq_refl x
]]
The theorem %\index{Gallina terms!UIP\_refl}%[UIP_refl] comes from the [Eqdep] module of the standard library. (Its name uses the acronym "UIP" for "unicity of identity proofs.") Do the Coq authors know of some clever trick for building such proofs that we have not seen yet? If they do, they did not use it for this proof. Rather, the proof is based on an _axiom_, the term [eq_rect_eq] below. *)
(* begin hide *)
Import Eq_rect_eq.
(* end hide *)
Print eq_rect_eq.
(** %\vspace{-.15in}% [[
*** [ eq_rect_eq :
forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h ]
]]
The axiom %\index{Gallina terms!eq\_rect\_eq}%[eq_rect_eq] states a "fact" that seems like common sense, once the notation is deciphered. The term [eq_rect] is the automatically generated recursion principle for [eq]. Calling [eq_rect] is another way of [match]ing on an equality proof. The proof we match on is the argument [h], and [x] is the body of the [match]. The statement of [eq_rect_eq] just says that [match]es on proofs of [p = p], for any [p], are superfluous and may be removed. We can see this intuition better in code by asking Coq to simplify the theorem statement with the [compute] reduction strategy. *)
(* begin hide *)
(* begin thide *)
Definition False' := False.
(* end thide *)
(* end hide *)
Eval compute in (forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h).
(** %\vspace{-.15in}%[[
= forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = match h in (_ = y) return (Q y) with
| eq_refl => x
end
]]
Perhaps surprisingly, we cannot prove [eq_rect_eq] from within Coq. This proposition is introduced as an %\index{axioms}%axiom; that is, a proposition asserted as true without proof. We cannot assert just any statement without proof. Adding [False] as an axiom would allow us to prove any proposition, for instance, defeating the point of using a proof assistant. In general, we need to be sure that we never assert _inconsistent_ sets of axioms. A set of axioms is inconsistent if its conjunction implies [False]. For the case of [eq_rect_eq], consistency has been verified outside of Coq via "informal" metatheory%~\cite{AxiomK}%, in a study that also established unprovability of the axiom in CIC.
This axiom is equivalent to another that is more commonly known and mentioned in type theory circles. *)
(* begin hide *)
(* begin thide *)
Definition Streicher_K' := UIP_refl__Streicher_K.
(* end thide *)
(* end hide *)
Check Streicher_K.
(* end thide *)
(** %\vspace{-.15in}% [[
Streicher_K
: forall (U : Type) (x : U) (P : x = x -> Prop),
P eq_refl -> forall p : x = x, P p
]]
This is the opaquely named %\index{axiom K}%"Streicher's axiom K," which says that a predicate on properly typed equality proofs holds of all such proofs if it holds of reflexivity. *)
End fhlist_map.
(* begin hide *)
(* begin thide *)
Require Eqdep_dec.
(* end thide *)
(* end hide *)
(** It is worth remarking that it is possible to avoid axioms altogether for equalities on types with decidable equality. The [Eqdep_dec] module of the standard library contains a parametric proof of [UIP_refl] for such cases. To simplify presentation, we will stick with the axiom version in the rest of this chapter. *)
(** * Type-Casts in Theorem Statements *)
(** Sometimes we need to use tricks with equality just to state the theorems that we care about. To illustrate, we start by defining a concatenation function for [fhlist]s. *)
Section fhapp.
Variable A : Type.
Variable B : A -> Type.
Fixpoint fhapp (ls1 ls2 : list A)
: fhlist B ls1 -> fhlist B ls2 -> fhlist B (ls1 ++ ls2) :=
match ls1 with
| nil => fun _ hls2 => hls2
| _ :: _ => fun hls1 hls2 => (fst hls1, fhapp _ _ (snd hls1) hls2)
end.
Arguments fhapp [ls1 ls2] _ _.
(* EX: Prove that fhapp is associative. *)
(* begin thide *)
(** We might like to prove that [fhapp] is associative.
[[
Theorem fhapp_assoc : forall ls1 ls2 ls3
(hls1 : fhlist B ls1) (hls2 : fhlist B ls2) (hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) = fhapp (fhapp hls1 hls2) hls3.
]]
<<
The term
"fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3) (fhapp (ls1:=ls1) (ls2:=ls2) hls1 hls2)
hls3" has type "fhlist B ((ls1 ++ ls2) ++ ls3)"
while it is expected to have type "fhlist B (ls1 ++ ls2 ++ ls3)"
>>
This first cut at the theorem statement does not even type-check. We know that the two [fhlist] types appearing in the error message are always equal, by associativity of normal list append, but this fact is not apparent to the type checker. This stems from the fact that Coq's equality is%\index{intensional type theory}% _intensional_, in the sense that type equality theorems can never be applied after the fact to get a term to type-check. Instead, we need to make use of equality explicitly in the theorem statement. *)
Theorem fhapp_assoc : forall ls1 ls2 ls3
(pf : (ls1 ++ ls2) ++ ls3 = ls1 ++ (ls2 ++ ls3))
(hls1 : fhlist B ls1) (hls2 : fhlist B ls2) (hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3)
= match pf in (_ = ls) return fhlist _ ls with
| eq_refl => fhapp (fhapp hls1 hls2) hls3
end.
induction ls1; crush.
(** The first remaining subgoal looks trivial enough:
[[
============================
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3 =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl => fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3
end
]]
We can try what worked in previous examples.
[[
case pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
It seems we have reached another case where it is unclear how to use a dependent [match] to implement case analysis on our proof. The [UIP_refl] theorem can come to our rescue again. *)
rewrite (UIP_refl _ _ pf).
(** [[
============================
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3 =
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3
]]
*)
reflexivity.
(** Our second subgoal is trickier.
[[
pf : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3
============================
(a0,
fhapp (ls1:=ls1) (ls2:=ls2 ++ ls3) b
(fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3)) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
rewrite (UIP_refl _ _ pf).
]]
<<
The term "pf" has type "a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3"
while it is expected to have type "?556 = ?556"
>>
We can only apply [UIP_refl] on proofs of equality with syntactically equal operands, which is not the case of [pf] here. We will need to manipulate the form of this subgoal to get us to a point where we may use [UIP_refl]. A first step is obtaining a proof suitable to use in applying the induction hypothesis. Inversion on the structure of [pf] is sufficient for that. *)
injection pf; intro pf'.
(** [[
pf : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3
pf' : (ls1 ++ ls2) ++ ls3 = ls1 ++ ls2 ++ ls3
============================
(a0,
fhapp (ls1:=ls1) (ls2:=ls2 ++ ls3) b
(fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3)) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
]]
Now we can rewrite using the inductive hypothesis. *)
rewrite (IHls1 _ _ pf').
(** [[
============================
(a0,
match pf' in (_ = ls) return (fhlist B ls) with
| eq_refl =>
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3
end) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
]]
We have made an important bit of progress, as now only a single call to [fhapp] appears in the conclusion, repeated twice. Trying case analysis on our proofs still will not work, but there is a move we can make to enable it. Not only does just one call to [fhapp] matter to us now, but it also _does not matter what the result of the call is_. In other words, the subgoal should remain true if we replace this [fhapp] call with a fresh variable. The %\index{tactics!generalize}%[generalize] tactic helps us do exactly that. *)
generalize (fhapp (fhapp b hls2) hls3).
(** [[
forall f : fhlist B ((ls1 ++ ls2) ++ ls3),
(a0,
match pf' in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
The conclusion has gotten markedly simpler. It seems counterintuitive that we can have an easier time of proving a more general theorem, but such a phenomenon applies to the case here and to many other proofs that use dependent types heavily. Speaking informally, the reason why this kind of activity helps is that [match] annotations contain some positions where only variables are allowed. By reducing more elements of a goal to variables, built-in tactics can have more success building [match] terms under the hood.
In this case, it is helpful to generalize over our two proofs as well. *)
generalize pf pf'.
(** [[
forall (pf0 : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3)
(pf'0 : (ls1 ++ ls2) ++ ls3 = ls1 ++ ls2 ++ ls3)
(f : fhlist B ((ls1 ++ ls2) ++ ls3)),
(a0,
match pf'0 in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf0 in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
To an experienced dependent types hacker, the appearance of this goal term calls for a celebration. The formula has a critical property that indicates that our problems are over. To get our proofs into the right form to apply [UIP_refl], we need to use associativity of list append to rewrite their types. We could not do so before because other parts of the goal require the proofs to retain their original types. In particular, the call to [fhapp] that we generalized must have type [(ls1 ++ ls2) ++ ls3], for some values of the list variables. If we rewrite the type of the proof used to type-cast this value to something like [ls1 ++ ls2 ++ ls3 = ls1 ++ ls2 ++ ls3], then the lefthand side of the equality would no longer match the type of the term we are trying to cast.
However, now that we have generalized over the [fhapp] call, the type of the term being type-cast appears explicitly in the goal and _may be rewritten as well_. In particular, the final masterstroke is rewriting everywhere in our goal using associativity of list append. *)
rewrite app_assoc.
(** [[
============================
forall (pf0 : a :: ls1 ++ ls2 ++ ls3 = a :: ls1 ++ ls2 ++ ls3)
(pf'0 : ls1 ++ ls2 ++ ls3 = ls1 ++ ls2 ++ ls3)
(f : fhlist B (ls1 ++ ls2 ++ ls3)),
(a0,
match pf'0 in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf0 in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
We can see that we have achieved the crucial property: the type of each generalized equality proof has syntactically equal operands. This makes it easy to finish the proof with [UIP_refl]. *)
intros.
rewrite (UIP_refl _ _ pf0).
rewrite (UIP_refl _ _ pf'0).
reflexivity.
Qed.
(* end thide *)
End fhapp.
Arguments fhapp [A B ls1 ls2] _ _.
(** This proof strategy was cumbersome and unorthodox, from the perspective of mainstream mathematics. The next section explores an alternative that leads to simpler developments in some cases. *)
(** * Heterogeneous Equality *)
(** There is another equality predicate, defined in the %\index{Gallina terms!JMeq}%[JMeq] module of the standard library, implementing%\index{heterogeneous equality}% _heterogeneous equality_. *)
Print JMeq.
(** %\vspace{-.15in}% [[
Inductive JMeq (A : Type) (x : A) : forall B : Type, B -> Prop :=
JMeq_refl : JMeq x x
]]
The identifier [JMeq] stands for %\index{John Major equality}%"John Major equality," a name coined by Conor McBride%~\cite{JMeq}% as an inside joke about British politics. The definition [JMeq] starts out looking a lot like the definition of [eq]. The crucial difference is that we may use [JMeq] _on arguments of different types_. For instance, a lemma that we failed to establish before is trivial with [JMeq]. It makes for prettier theorem statements to define some syntactic shorthand first. *)
Infix "==" := JMeq (at level 70, no associativity).
(* EX: Prove UIP_refl' : forall (A : Type) (x : A) (pf : x = x), pf == eq_refl x *)
(* begin thide *)
Definition UIP_refl' (A : Type) (x : A) (pf : x = x) : pf == eq_refl x :=
match pf return (pf == eq_refl _) with
| eq_refl => JMeq_refl _
end.
(* end thide *)
(** There is no quick way to write such a proof by tactics, but the underlying proof term that we want is trivial.
Suppose that we want to use [UIP_refl'] to establish another lemma of the kind we have run into several times so far. *)
Lemma lemma4 : forall (A : Type) (x : A) (pf : x = x),
O = match pf with eq_refl => O end.
(* begin thide *)
intros; rewrite (UIP_refl' pf); reflexivity.
Qed.
(* end thide *)
(** All in all, refreshingly straightforward, but there really is no such thing as a free lunch. The use of [rewrite] is implemented in terms of an axiom: *)
Check JMeq_eq.
(** %\vspace{-.15in}% [[
JMeq_eq
: forall (A : Type) (x y : A), x == y -> x = y
]]
It may be surprising that we cannot prove that heterogeneous equality implies normal equality. The difficulties are the same kind we have seen so far, based on limitations of [match] annotations. The [JMeq_eq] axiom has been proved on paper to be consistent, but asserting it may still be considered to complicate the logic we work in, so there is some motivation for avoiding it.
We can redo our [fhapp] associativity proof based around [JMeq]. *)
Section fhapp'.
Variable A : Type.
Variable B : A -> Type.
(** This time, the %\%naive%{}% theorem statement type-checks. *)
(* EX: Prove [fhapp] associativity using [JMeq]. *)
(* begin thide *)
Theorem fhapp_assoc' : forall ls1 ls2 ls3 (hls1 : fhlist B ls1) (hls2 : fhlist B ls2)
(hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) == fhapp (fhapp hls1 hls2) hls3.
induction ls1; crush.
(** Even better, [crush] discharges the first subgoal automatically. The second subgoal is:
[[
============================
(a0, fhapp b (fhapp hls2 hls3)) == (a0, fhapp (fhapp b hls2) hls3)
]]
It looks like one rewrite with the inductive hypothesis should be enough to make the goal trivial. Here is what happens when we try that in Coq 8.2:
[[
rewrite IHls1.
]]
<<
Error: Impossible to unify "fhlist B ((ls1 ++ ?1572) ++ ?1573)" with
"fhlist B (ls1 ++ ?1572 ++ ?1573)"
>>
Coq 8.4 currently gives an error message about an uncaught exception. Perhaps that will be fixed soon. In any case, it is educational to consider a more explicit approach.
We see that [JMeq] is not a silver bullet. We can use it to simplify the statements of equality facts, but the Coq type-checker uses non-trivial heterogeneous equality facts no more readily than it uses standard equality facts. Here, the problem is that the form [(e1, e2)] is syntactic sugar for an explicit application of a constructor of an inductive type. That application mentions the type of each tuple element explicitly, and our [rewrite] tries to change one of those elements without updating the corresponding type argument.
We can get around this problem by another multiple use of [generalize]. We want to bring into the goal the proper instance of the inductive hypothesis, and we also want to generalize the two relevant uses of [fhapp]. *)
generalize (fhapp b (fhapp hls2 hls3))
(fhapp (fhapp b hls2) hls3)
(IHls1 _ _ b hls2 hls3).
(** %\vspace{-.15in}%[[
============================
forall (f : fhlist B (ls1 ++ ls2 ++ ls3))
(f0 : fhlist B ((ls1 ++ ls2) ++ ls3)), f == f0 -> (a0, f) == (a0, f0)
]]
Now we can rewrite with append associativity, as before. *)
rewrite app_assoc.
(** %\vspace{-.15in}%[[
============================
forall f f0 : fhlist B (ls1 ++ ls2 ++ ls3), f == f0 -> (a0, f) == (a0, f0)
]]
From this point, the goal is trivial. *)
intros f f0 H; rewrite H; reflexivity.
Qed.
(* end thide *)
End fhapp'.
(** This example illustrates a general pattern: heterogeneous equality often simplifies theorem statements, but we still need to do some work to line up some dependent pattern matches that tactics will generate for us.
The proof we have found relies on the [JMeq_eq] axiom, which we can verify with a command%\index{Vernacular commands!Print Assumptions}% that we will discuss more in two chapters. *)
Print Assumptions fhapp_assoc'.
(** %\vspace{-.15in}%[[
Axioms:
JMeq_eq : forall (A : Type) (x y : A), x == y -> x = y
]]
It was the [rewrite H] tactic that implicitly appealed to the axiom. By restructuring the proof, we can avoid axiom dependence. A general lemma about pairs provides the key element. (Our use of [generalize] above can be thought of as reducing the proof to another, more complex and specialized lemma.) *)
Lemma pair_cong : forall A1 A2 B1 B2 (x1 : A1) (x2 : A2) (y1 : B1) (y2 : B2),
x1 == x2
-> y1 == y2
-> (x1, y1) == (x2, y2).
intros until y2; intros Hx Hy; rewrite Hx; rewrite Hy; reflexivity.
Qed.
Hint Resolve pair_cong.
Section fhapp''.
Variable A : Type.
Variable B : A -> Type.
Theorem fhapp_assoc'' : forall ls1 ls2 ls3 (hls1 : fhlist B ls1) (hls2 : fhlist B ls2)
(hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) == fhapp (fhapp hls1 hls2) hls3.
induction ls1; crush.
Qed.
End fhapp''.
Print Assumptions fhapp_assoc''.
(** <<
Closed under the global context
>>
One might wonder exactly which elements of a proof involving [JMeq] imply that [JMeq_eq] must be used. For instance, above we noticed that [rewrite] had brought [JMeq_eq] into the proof of [fhapp_assoc'], yet here we have also used [rewrite] with [JMeq] hypotheses while avoiding axioms! One illuminating exercise is comparing the types of the lemmas that [rewrite] uses under the hood to implement the rewrites. Here is the normal lemma for [eq] rewriting:%\index{Gallina terms!eq\_ind\_r}% *)
Check eq_ind_r.
(** %\vspace{-.15in}%[[
eq_ind_r
: forall (A : Type) (x : A) (P : A -> Prop),
P x -> forall y : A, y = x -> P y
]]
The corresponding lemma used for [JMeq] in the proof of [pair_cong] is defined internally by [rewrite] as needed, but its type happens to be the following. *)
(** %\vspace{-.15in}%[[
internal_JMeq_rew_r
: forall (A : Type) (x : A) (B : Type) (b : B)
(P : forall B0 : Type, B0 -> Type), P B b -> x == b -> P A x
]]
The key difference is that, where the [eq] lemma is parameterized on a predicate of type [A -> Prop], the [JMeq] lemma is parameterized on a predicate of type more like [forall A : Type, A -> Prop]. To apply [eq_ind_r] with a proof of [x = y], it is only necessary to rearrange the goal into an application of a [fun] abstraction to [y]. In contrast, to apply the alternative principle, it is necessary to rearrange the goal to an application of a [fun] abstraction to both [y] and _its type_. In other words, the predicate must be _polymorphic_ in [y]'s type; any type must make sense, from a type-checking standpoint. There may be cases where the former rearrangement is easy to do in a type-correct way, but the second rearrangement done %\%naive%{}%ly leads to a type error.
When [rewrite] cannot figure out how to apply the alternative principle for [x == y] where [x] and [y] have the same type, the tactic can instead use a different theorem, which is easy to prove as a composition of [eq_ind_r] and [JMeq_eq]. *)
Check JMeq_ind_r.
(** %\vspace{-.15in}%[[
JMeq_ind_r
: forall (A : Type) (x : A) (P : A -> Prop),
P x -> forall y : A, y == x -> P y
]]
Ironically, where in the proof of [fhapp_assoc'] we used [rewrite app_assoc] to make it clear that a use of [JMeq] was actually homogeneously typed, we created a situation where [rewrite] applied the axiom-based [JMeq_ind_r] instead of the axiom-free principle!
For another simple example, consider this theorem that applies a heterogeneous equality to prove a congruence fact. *)
Theorem out_of_luck : forall n m : nat,
n == m
-> S n == S m.
intros n m H.
(** Applying [JMeq_ind_r] is easy, as the %\index{tactics!pattern}%[pattern] tactic will transform the goal into an application of an appropriate [fun] to a term that we want to abstract. (In general, [pattern] abstracts over a term by introducing a new anonymous function taking that term as argument.) *)
pattern n.
(** %\vspace{-.15in}%[[
n : nat
m : nat
H : n == m
============================
(fun n0 : nat => S n0 == S m) n
]]
*)
apply JMeq_ind_r with (x := m); auto.
(** However, we run into trouble trying to get the goal into a form compatible with the alternative principle. *)
Undo 2.
(** %\vspace{-.15in}%[[
pattern nat, n.
]]
<<
Error: The abstracted term "fun (P : Set) (n0 : P) => S n0 == S m"
is not well typed.
Illegal application (Type Error):
The term "S" of type "nat -> nat"
cannot be applied to the term
"n0" : "P"
This term has type "P" which should be coercible to
"nat".
>>
In other words, the successor function [S] is insufficiently polymorphic. If we try to generalize over the type of [n], we find that [S] is no longer legal to apply to [n]. *)
Abort.
(** Why did we not run into this problem in our proof of [fhapp_assoc'']? The reason is that the pair constructor is polymorphic in the types of the pair components, while functions like [S] are not polymorphic at all. Use of such non-polymorphic functions with [JMeq] tends to push toward use of axioms. The example with [nat] here is a bit unrealistic; more likely cases would involve functions that have _some_ polymorphism, but not enough to allow abstractions of the sort we attempted above with [pattern]. For instance, we might have an equality between two lists, where the goal only type-checks when the terms involved really are lists, though everything is polymorphic in the types of list data elements. The {{http://www.mpi-sws.org/~gil/Heq/}Heq} library builds up a slightly different foundation to help avoid such problems. *)
(** * Equivalence of Equality Axioms *)
(* EX: Show that the approaches based on K and JMeq are equivalent logically. *)
(* begin thide *)
(** Assuming axioms (like axiom K and [JMeq_eq]) is a hazardous business. The due diligence associated with it is necessarily global in scope, since two axioms may be consistent alone but inconsistent together. It turns out that all of the major axioms proposed for reasoning about equality in Coq are logically equivalent, so that we only need to pick one to assert without proof. In this section, we demonstrate by showing how each of the previous two sections' approaches reduces to the other logically.
To show that [JMeq] and its axiom let us prove [UIP_refl], we start from the lemma [UIP_refl'] from the previous section. The rest of the proof is trivial. *)
Lemma UIP_refl'' : forall (A : Type) (x : A) (pf : x = x), pf = eq_refl x.
intros; rewrite (UIP_refl' pf); reflexivity.
Qed.
(** The other direction is perhaps more interesting. Assume that we only have the axiom of the [Eqdep] module available. We can define [JMeq] in a way that satisfies the same interface as the combination of the [JMeq] module's inductive definition and axiom. *)
Definition JMeq' (A : Type) (x : A) (B : Type) (y : B) : Prop :=
exists pf : B = A, x = match pf with eq_refl => y end.
Infix "===" := JMeq' (at level 70, no associativity).
(** remove printing exists *)
(** We say that, by definition, [x] and [y] are equal if and only if there exists a proof [pf] that their types are equal, such that [x] equals the result of casting [y] with [pf]. This statement can look strange from the standpoint of classical math, where we almost never mention proofs explicitly with quantifiers in formulas, but it is perfectly legal Coq code.
We can easily prove a theorem with the same type as that of the [JMeq_refl] constructor of [JMeq]. *)
Theorem JMeq_refl' : forall (A : Type) (x : A), x === x.
intros; unfold JMeq'; exists (eq_refl A); reflexivity.
Qed.
(** printing exists $\exists$ *)
(** The proof of an analogue to [JMeq_eq] is a little more interesting, but most of the action is in appealing to [UIP_refl]. *)
Theorem JMeq_eq' : forall (A : Type) (x y : A),
x === y -> x = y.
unfold JMeq'; intros.
(** [[
H : exists pf : A = A,
x = match pf in (_ = T) return T with
| eq_refl => y
end
============================
x = y
]]
*)
destruct H.
(** [[
x0 : A = A
H : x = match x0 in (_ = T) return T with
| eq_refl => y
end
============================
x = y
]]
*)
rewrite H.
(** [[
x0 : A = A
============================
match x0 in (_ = T) return T with
| eq_refl => y
end = y
]]
*)
rewrite (UIP_refl _ _ x0); reflexivity.
Qed.
(** We see that, in a very formal sense, we are free to switch back and forth between the two styles of proofs about equality proofs. One style may be more convenient than the other for some proofs, but we can always interconvert between our results. The style that does not use heterogeneous equality may be preferable in cases where many results do not require the tricks of this chapter, since then the use of axioms is avoided altogether for the simple cases, and a wider audience will be able to follow those "simple" proofs. On the other hand, heterogeneous equality often makes for shorter and more readable theorem statements. *)
(* end thide *)
(** * Equality of Functions *)
(** The following seems like a reasonable theorem to want to hold, and it does hold in set theory.
%\vspace{-.15in}%[[
Theorem two_funs : (fun n => n) = (fun n => n + 0).
]]
%\vspace{-.15in}%Unfortunately, this theorem is not provable in CIC without additional axioms. None of the definitional equality rules force function equality to be%\index{extensionality of function equality}% _extensional_. That is, the fact that two functions return equal results on equal inputs does not imply that the functions are equal. We _can_ assert function extensionality as an axiom, and indeed the standard library already contains that axiom. *)
Require Import FunctionalExtensionality.
About functional_extensionality.
(** %\vspace{-.15in}%[[
functional_extensionality :
forall (A B : Type) (f g : A -> B), (forall x : A, f x = g x) -> f = g
]]
*)
(** This axiom has been verified metatheoretically to be consistent with CIC and the two equality axioms we considered previously. With it, the proof of [two_funs] is trivial. *)
Theorem two_funs : (fun n => n) = (fun n => n + 0).
(* begin thide *)
apply functional_extensionality; crush.
Qed.
(* end thide *)
(** The same axiom can help us prove equality of types, where we need to "reason under quantifiers." *)
Theorem forall_eq : (forall x : nat, match x with
| O => True
| S _ => True
end)
= (forall _ : nat, True).
(** There are no immediate opportunities to apply [functional_extensionality], but we can use %\index{tactics!change}%[change] to fix that problem. *)
(* begin thide *)
change ((forall x : nat, (fun x => match x with
| 0 => True
| S _ => True
end) x) = (nat -> True)).
rewrite (functional_extensionality (fun x => match x with
| 0 => True
| S _ => True
end) (fun _ => True)).
(** [[
2 subgoals
============================
(nat -> True) = (nat -> True)
subgoal 2 is:
forall x : nat, match x with
| 0 => True
| S _ => True
end = True
]]
*)
reflexivity.
destruct x; constructor.
Qed.
(* end thide *)
(** Unlike in the case of [eq_rect_eq], we have no way of deriving this axiom of%\index{functional extensionality}% _functional extensionality_ for types with decidable equality. To allow equality reasoning without axioms, it may be worth rewriting a development to replace functions with alternate representations, such as finite map types for which extensionality is derivable in CIC. *)
|
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//sdram_clkgen.v
`timescale 1 ns/1 ps
module sdram_clkgen (
input clk,
input rst,
output locked,
output out_clk,
output phy_out_clk
);
wire clkfbout_buf;
wire clkfbout;
wire clkout0;
wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire phy_bufout;
PLL_BASE #(
.BANDWIDTH ("OPTIMIZED" ),
.CLK_FEEDBACK ("CLKFBOUT" ),
.COMPENSATION ("SYSTEM_SYNCHRONOUS" ),
.DIVCLK_DIVIDE (1 ),
.CLKFBOUT_MULT (18 ),
.CLKFBOUT_PHASE (0.000 ),
.CLKOUT0_DIVIDE (9 ),
//Simulations differ from real world in that the phase must be 0, not 90 degrees
`ifndef SIMULATION
.CLKOUT0_PHASE (180.00 ),
`else
.CLKOUT0_PHASE (0.00 ),
`endif
.CLKOUT0_DUTY_CYCLE (0.500 ),
.CLKOUT1_DIVIDE (9 ),
.CLKOUT1_DUTY_CYCLE (0.500 ),
.CLKIN_PERIOD (20.000 ),
.REF_JITTER (0.010 )
) pll (
//Input Clock and Input Clock Control
.CLKFBIN (clkfbout_buf ),
.CLKIN (clk ),
//Status/Control
.LOCKED (locked ),
.RST (rst ),
//Feedback Output
.CLKFBOUT (clkfbout ),
.CLKOUT0 (clkout0 ),
.CLKOUT1 (clkout1 ),
.CLKOUT2 (clkout2 ),
.CLKOUT3 (clkout3 ),
.CLKOUT4 (clkout4 ),
.CLKOUT5 (clkout5 )
);
BUFG bufg_sdram_clk (
.I(clkout0),
.O(out_clk)
);
BUFG pll_fb (
.I (clkfbout),
.O (clkfbout_buf)
);
BUFG phy_clock_out (
.I(clkout1),
.O(phy_bufout)
);
ODDR2 #(
.DDR_ALIGNMENT ("NONE" ), //Sets output alignment to NON
.INIT (1'b0 ), //Sets the inital state to 0
.SRTYPE ("SYNC" ) //Specified "SYNC" or "ASYNC" reset
) pad_buf (
.Q (phy_out_clk ),
.C0 (phy_bufout ),
.C1 (~phy_bufout ),
.CE (1'b1 ),
.D0 (1'b1 ),
.D1 (1'b0 ),
.R (1'b0 ),
.S (1'b0 )
);
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_async_fifo;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(input_clk,
input_rst,
output_clk,
output_rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo.lxt");
$dumpvars(0, test_axis_async_fifo);
end
axis_async_fifo #(
.ADDR_WIDTH(2),
.DATA_WIDTH(8)
)
UUT (
// AXI input
.input_clk(input_clk),
.input_rst(input_rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_clk(output_clk),
.output_rst(output_rst),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
`default_nettype wire
module damy_memory_16entry_512bit(
input iCLOCK,
input [63:0] iBYTE_ENA,
//Write
input iWR_ENA,
input [3:0] iWR_ADDR,
input [511:0] iWR_DATA,
//Read
input [3:0] iRD_ADDR,
output [511:0] oRD_DATA
);
reg [511:0] b_mem[0:15];
always@(posedge iCLOCK)begin
if(iWR_ENA)begin
b_mem[iWR_ADDR] <= func_byteena_o(iBYTE_ENA, b_mem[iWR_ADDR], iWR_DATA);
end
end
function [511:0] func_byteena_o;
input [63:0] func_byteena;
input [511:0] func_current_data;
input [511:0] func_new_data;
reg [511:0] func_local_data;
begin
func_local_data[7:0] = (func_byteena[0])? func_new_data[7:0] : func_current_data[7:0];
func_local_data[15:8] = (func_byteena[1])? func_new_data[15:8] : func_current_data[15:8];
func_local_data[23:16] = (func_byteena[2])? func_new_data[23:16] : func_current_data[23:16];
func_local_data[31:24] = (func_byteena[3])? func_new_data[31:24] : func_current_data[31:24];
func_local_data[39:32] = (func_byteena[4])? func_new_data[39:32] : func_current_data[39:32];
func_local_data[47:40] = (func_byteena[5])? func_new_data[47:40] : func_current_data[47:40];
func_local_data[55:48] = (func_byteena[6])? func_new_data[55:48] : func_current_data[55:48];
func_local_data[63:56] = (func_byteena[7])? func_new_data[63:56] : func_current_data[63:56];
func_local_data[71:64] = (func_byteena[8])? func_new_data[71:64] : func_current_data[71:64];
func_local_data[79:72] = (func_byteena[9])? func_new_data[79:72] : func_current_data[79:72];
func_local_data[87:80] = (func_byteena[10])? func_new_data[87:80] : func_current_data[87:80];
func_local_data[95:88] = (func_byteena[11])? func_new_data[95:88] : func_current_data[95:88];
func_local_data[103:96] = (func_byteena[12])? func_new_data[103:96] : func_current_data[103:96];
func_local_data[111:104] = (func_byteena[13])? func_new_data[111:104] : func_current_data[111:104];
func_local_data[119:112] = (func_byteena[14])? func_new_data[119:112] : func_current_data[119:112];
func_local_data[127:120] = (func_byteena[15])? func_new_data[127:120] : func_current_data[127:120];
func_local_data[135:128] = (func_byteena[16])? func_new_data[135:128] : func_current_data[135:128];
func_local_data[143:136] = (func_byteena[17])? func_new_data[143:136] : func_current_data[143:136];
func_local_data[151:144] = (func_byteena[18])? func_new_data[151:144] : func_current_data[151:144];
func_local_data[159:152] = (func_byteena[19])? func_new_data[159:152] : func_current_data[159:152];
func_local_data[167:160] = (func_byteena[20])? func_new_data[167:160] : func_current_data[167:160];
func_local_data[175:168] = (func_byteena[21])? func_new_data[175:168] : func_current_data[175:168];
func_local_data[183:176] = (func_byteena[22])? func_new_data[183:176] : func_current_data[183:176];
func_local_data[191:184] = (func_byteena[23])? func_new_data[191:184] : func_current_data[191:184];
func_local_data[199:192] = (func_byteena[24])? func_new_data[199:192] : func_current_data[199:192];
func_local_data[207:200] = (func_byteena[25])? func_new_data[207:200] : func_current_data[207:200];
func_local_data[215:208] = (func_byteena[26])? func_new_data[215:208] : func_current_data[215:208];
func_local_data[223:216] = (func_byteena[27])? func_new_data[223:216] : func_current_data[223:216];
func_local_data[231:224] = (func_byteena[28])? func_new_data[231:224] : func_current_data[231:224];
func_local_data[239:232] = (func_byteena[29])? func_new_data[239:232] : func_current_data[239:232];
func_local_data[247:240] = (func_byteena[30])? func_new_data[247:240] : func_current_data[247:240];
func_local_data[255:248] = (func_byteena[31])? func_new_data[255:248] : func_current_data[255:248];
func_local_data[263:256] = (func_byteena[32])? func_new_data[263:256] : func_current_data[263:256];
func_local_data[271:264] = (func_byteena[33])? func_new_data[271:264] : func_current_data[271:264];
func_local_data[279:272] = (func_byteena[34])? func_new_data[279:272] : func_current_data[279:272];
func_local_data[287:280] = (func_byteena[35])? func_new_data[287:280] : func_current_data[287:280];
func_local_data[295:288] = (func_byteena[36])? func_new_data[295:288] : func_current_data[295:288];
func_local_data[303:296] = (func_byteena[37])? func_new_data[303:296] : func_current_data[303:296];
func_local_data[311:304] = (func_byteena[38])? func_new_data[311:304] : func_current_data[311:304];
func_local_data[319:312] = (func_byteena[39])? func_new_data[319:312] : func_current_data[319:312];
func_local_data[327:320] = (func_byteena[40])? func_new_data[327:320] : func_current_data[327:320];
func_local_data[335:328] = (func_byteena[41])? func_new_data[335:328] : func_current_data[335:328];
func_local_data[343:336] = (func_byteena[42])? func_new_data[343:336] : func_current_data[343:336];
func_local_data[351:344] = (func_byteena[43])? func_new_data[351:344] : func_current_data[351:344];
func_local_data[359:352] = (func_byteena[44])? func_new_data[359:352] : func_current_data[359:352];
func_local_data[367:360] = (func_byteena[45])? func_new_data[367:360] : func_current_data[367:360];
func_local_data[375:368] = (func_byteena[46])? func_new_data[375:368] : func_current_data[375:368];
func_local_data[383:376] = (func_byteena[47])? func_new_data[383:376] : func_current_data[383:376];
func_local_data[391:384] = (func_byteena[48])? func_new_data[391:384] : func_current_data[391:384];
func_local_data[399:392] = (func_byteena[49])? func_new_data[399:392] : func_current_data[399:392];
func_local_data[407:400] = (func_byteena[50])? func_new_data[407:400] : func_current_data[407:400];
func_local_data[415:408] = (func_byteena[51])? func_new_data[415:408] : func_current_data[415:408];
func_local_data[423:416] = (func_byteena[52])? func_new_data[423:416] : func_current_data[423:416];
func_local_data[431:424] = (func_byteena[53])? func_new_data[431:424] : func_current_data[431:424];
func_local_data[439:432] = (func_byteena[54])? func_new_data[439:432] : func_current_data[439:432];
func_local_data[447:440] = (func_byteena[55])? func_new_data[447:440] : func_current_data[447:440];
func_local_data[455:448] = (func_byteena[56])? func_new_data[455:448] : func_current_data[455:448];
func_local_data[463:456] = (func_byteena[57])? func_new_data[463:456] : func_current_data[463:456];
func_local_data[471:464] = (func_byteena[58])? func_new_data[471:464] : func_current_data[471:464];
func_local_data[479:472] = (func_byteena[59])? func_new_data[479:472] : func_current_data[479:472];
func_local_data[487:480] = (func_byteena[60])? func_new_data[487:480] : func_current_data[487:480];
func_local_data[495:488] = (func_byteena[61])? func_new_data[495:488] : func_current_data[495:488];
func_local_data[503:496] = (func_byteena[62])? func_new_data[503:496] : func_current_data[503:496];
func_local_data[511:504] = (func_byteena[63])? func_new_data[511:504] : func_current_data[511:504];
func_byteena_o = func_local_data;
end
endfunction
assign oRD_DATA = b_mem[iRD_ADDR];
endmodule
`default_nettype none |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// CLK I 1 clock
// RST_N I 1 reset
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTop_HW_Side(CLK,
RST_N);
input CLK;
input RST_N;
// register rg_banner_printed
reg rg_banner_printed;
wire rg_banner_printed$D_IN, rg_banner_printed$EN;
// register rg_console_in_poll
reg [11 : 0] rg_console_in_poll;
wire [11 : 0] rg_console_in_poll$D_IN;
wire rg_console_in_poll$EN;
// ports of submodule mem_model
wire [352 : 0] mem_model$mem_server_request_put;
wire [255 : 0] mem_model$mem_server_response_get;
wire mem_model$EN_mem_server_request_put,
mem_model$EN_mem_server_response_get,
mem_model$RDY_mem_server_request_put,
mem_model$RDY_mem_server_response_get;
// ports of submodule soc_top
wire [352 : 0] soc_top$to_raw_mem_request_get;
wire [255 : 0] soc_top$to_raw_mem_response_put;
wire [63 : 0] soc_top$mv_tohost_value,
soc_top$set_verbosity_logdelay,
soc_top$set_watch_tohost_tohost_addr;
wire [7 : 0] soc_top$get_to_console_get,
soc_top$mv_status,
soc_top$put_from_console_put;
wire [3 : 0] soc_top$set_verbosity_verbosity;
wire soc_top$EN_get_to_console_get,
soc_top$EN_ma_ddr4_ready,
soc_top$EN_put_from_console_put,
soc_top$EN_set_verbosity,
soc_top$EN_set_watch_tohost,
soc_top$EN_to_raw_mem_request_get,
soc_top$EN_to_raw_mem_response_put,
soc_top$RDY_get_to_console_get,
soc_top$RDY_put_from_console_put,
soc_top$RDY_to_raw_mem_request_get,
soc_top$RDY_to_raw_mem_response_put,
soc_top$set_watch_tohost_watch_tohost;
// rule scheduling signals
wire CAN_FIRE_RL_memCnx_ClientServerRequest,
CAN_FIRE_RL_memCnx_ClientServerResponse,
CAN_FIRE_RL_rl_relay_console_in,
CAN_FIRE_RL_rl_relay_console_out,
CAN_FIRE_RL_rl_step0,
CAN_FIRE_RL_rl_terminate,
CAN_FIRE_RL_rl_terminate_tohost,
WILL_FIRE_RL_memCnx_ClientServerRequest,
WILL_FIRE_RL_memCnx_ClientServerResponse,
WILL_FIRE_RL_rl_relay_console_in,
WILL_FIRE_RL_rl_relay_console_out,
WILL_FIRE_RL_rl_step0,
WILL_FIRE_RL_rl_terminate,
WILL_FIRE_RL_rl_terminate_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h749;
reg [31 : 0] v__h790;
reg [31 : 0] v__h903;
reg [31 : 0] v__h1037;
reg TASK_testplusargs___d12;
reg TASK_testplusargs___d11;
reg TASK_testplusargs___d15;
reg [63 : 0] tohost_addr__h618;
reg [31 : 0] v__h680;
reg [7 : 0] v__h1235;
reg [31 : 0] v__h674;
reg [31 : 0] v__h784;
reg [31 : 0] v__h1031;
reg [31 : 0] v__h743;
reg [31 : 0] v__h897;
// synopsys translate_on
// remaining internal signals
wire [63 : 0] test_num__h937;
// submodule mem_model
mkMem_Model mem_model(.CLK(CLK),
.RST_N(RST_N),
.mem_server_request_put(mem_model$mem_server_request_put),
.EN_mem_server_request_put(mem_model$EN_mem_server_request_put),
.EN_mem_server_response_get(mem_model$EN_mem_server_response_get),
.RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put),
.mem_server_response_get(mem_model$mem_server_response_get),
.RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get));
// submodule soc_top
mkSoC_Top soc_top(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(soc_top$put_from_console_put),
.set_verbosity_logdelay(soc_top$set_verbosity_logdelay),
.set_verbosity_verbosity(soc_top$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost),
.to_raw_mem_response_put(soc_top$to_raw_mem_response_put),
.EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put),
.EN_get_to_console_get(soc_top$EN_get_to_console_get),
.EN_put_from_console_put(soc_top$EN_put_from_console_put),
.EN_set_verbosity(soc_top$EN_set_verbosity),
.EN_set_watch_tohost(soc_top$EN_set_watch_tohost),
.EN_ma_ddr4_ready(soc_top$EN_ma_ddr4_ready),
.to_raw_mem_request_get(soc_top$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put),
.get_to_console_get(soc_top$get_to_console_get),
.RDY_get_to_console_get(soc_top$RDY_get_to_console_get),
.RDY_put_from_console_put(soc_top$RDY_put_from_console_put),
.status(),
.RDY_set_verbosity(),
.RDY_set_watch_tohost(),
.mv_tohost_value(soc_top$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(soc_top$mv_status));
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = soc_top$mv_status != 8'd0 ;
assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ;
// rule RL_rl_terminate_tohost
assign CAN_FIRE_RL_rl_terminate_tohost = soc_top$mv_tohost_value != 64'd0 ;
assign WILL_FIRE_RL_rl_terminate_tohost = CAN_FIRE_RL_rl_terminate_tohost ;
// rule RL_rl_step0
assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ;
assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ;
// rule RL_rl_relay_console_out
assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
// rule RL_rl_relay_console_in
assign CAN_FIRE_RL_rl_relay_console_in =
rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ;
assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ;
// rule RL_memCnx_ClientServerRequest
assign CAN_FIRE_RL_memCnx_ClientServerRequest =
soc_top$RDY_to_raw_mem_request_get &&
mem_model$RDY_mem_server_request_put ;
assign WILL_FIRE_RL_memCnx_ClientServerRequest =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
// rule RL_memCnx_ClientServerResponse
assign CAN_FIRE_RL_memCnx_ClientServerResponse =
soc_top$RDY_to_raw_mem_response_put &&
mem_model$RDY_mem_server_response_get ;
assign WILL_FIRE_RL_memCnx_ClientServerResponse =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// register rg_banner_printed
assign rg_banner_printed$D_IN = 1'd1 ;
assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ;
// register rg_console_in_poll
assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ;
assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ;
// submodule mem_model
assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ;
assign mem_model$EN_mem_server_request_put =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign mem_model$EN_mem_server_response_get =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// submodule soc_top
assign soc_top$put_from_console_put = v__h1235 ;
assign soc_top$set_verbosity_logdelay = 64'd0 ;
assign soc_top$set_verbosity_verbosity =
TASK_testplusargs___d11 ?
4'd2 :
(TASK_testplusargs___d12 ? 4'd1 : 4'd0) ;
assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h618 ;
assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ;
assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ;
assign soc_top$EN_to_raw_mem_request_get =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign soc_top$EN_to_raw_mem_response_put =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ;
assign soc_top$EN_put_from_console_put =
WILL_FIRE_RL_rl_relay_console_in &&
rg_console_in_poll == 12'd0 &&
v__h1235 != 8'd0 ;
assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_ma_ddr4_ready = CAN_FIRE_RL_rl_step0 ;
// remaining internal signals
assign test_num__h937 = { 1'd0, soc_top$mv_tohost_value[63:1] } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_banner_printed$EN)
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN;
if (rg_console_in_poll$EN)
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_banner_printed = 1'h0;
rg_console_in_poll = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h749 = $stime;
#0;
end
v__h743 = v__h749 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)",
v__h743,
soc_top$mv_status,
soc_top$mv_status);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h790 = $stime;
#0;
end
v__h784 = v__h790 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$imported_c_end_timing({ 32'd0, v__h784 });
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$display("****************************************************************");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
begin
v__h903 = $stime;
#0;
end
v__h897 = v__h903 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$display("%0d: %m:.rl_terminate_tohost: tohost_value is 0x%0h (= 0d%0d)",
v__h897,
soc_top$mv_tohost_value,
soc_top$mv_tohost_value);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost &&
soc_top$mv_tohost_value[63:1] == 63'd0)
$display(" PASS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost &&
soc_top$mv_tohost_value[63:1] != 63'd0)
$display(" FAIL <test_%0d>", test_num__h937);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
begin
v__h1037 = $stime;
#0;
end
v__h1031 = v__h1037 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost)
$imported_c_end_timing({ 32'd0, v__h1031 });
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate_tohost) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Bluespec RISC-V WindSoC simulation v1.2");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Copyright (c) 2017-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d12 = $test$plusargs("v1");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d11 = $test$plusargs("v2");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d15 = $test$plusargs("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
tohost_addr__h618 = $imported_c_get_symbol_val("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h",
TASK_testplusargs___d15,
tohost_addr__h618);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
v__h680 = $stime;
#0;
end
v__h674 = v__h680 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h674 });
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get)
$write("%c", soc_top$get_to_console_get);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0)
begin
v__h1235 = $imported_c_trygetchar(8'hAA);
#0;
end
end
// synopsys translate_on
endmodule // mkTop_HW_Side
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
|
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
localparam rep = 1<<(4-WIDTH);
wire [3:0] I;
generate
if(WIDTH == 1) begin
assign I = {1'b0, 1'b0, 1'b0, A[0]};
end else if(WIDTH == 2) begin
assign I = {1'b0, 1'b0, A[1], A[0]};
end else if(WIDTH == 3) begin
assign I = {1'b0, A[2], A[1], A[0]};
end else if(WIDTH == 4) begin
assign I = {A[3], A[2], A[1], A[0]};
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
endmodule
// DFFs
module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
// IO- "$__" cells for the iopadmap pass.
module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule
module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_phy3_62p5.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_phy3_62p5 (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "2000",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "2000",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "375.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "2.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "2.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy3_62p5.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "2000"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "2000"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.ppf TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / General Purpose Buffer
// /___/ /\ Filename : BUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUF (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEIVE",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEIVE",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEIVE",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_intp2_4 (
clk,
data,
// outputs
intp2_0,
intp2_1,
intp2_2,
intp2_3);
input clk;
input [15:0] data;
// outputs
output [15:0] intp2_0;
output [15:0] intp2_1;
output [15:0] intp2_2;
output [15:0] intp2_3;
// internal registers
reg [15:0] data_s0 = 'd0;
reg [15:0] data_s1 = 'd0;
reg [15:0] data_s2 = 'd0;
reg [15:0] data_s3 = 'd0;
reg [15:0] data_s4 = 'd0;
reg [15:0] data_s5 = 'd0;
reg [15:0] data_s6 = 'd0;
reg [15:0] data_s7 = 'd0;
// internal signals
wire [15:0] intp2_0_s;
wire [15:0] intp2_1_s;
// delay registers
always @(posedge clk) begin
data_s0 <= data_s2;
data_s1 <= data_s3;
data_s2 <= data_s4;
data_s3 <= data_s5;
data_s4 <= data_s6;
data_s5 <= data_s7;
data_s6 <= intp2_0_s;
data_s7 <= intp2_1_s;
end
// interpolators (stage-2)
ad_mac_1 i_mac_1_0 (
.clk (clk),
.data_s0 (data_s0),
.data_s1 (data_s1),
.data_s2 (data_s2),
.data_s3 (data_s3),
.data_s4 (data_s4),
.data_s5 (data_s5),
.mac_data_0 (intp2_0),
.mac_data_1 (intp2_1));
// interpolators (stage-2)
ad_mac_1 i_mac_1_1 (
.clk (clk),
.data_s0 (data_s1),
.data_s1 (data_s2),
.data_s2 (data_s3),
.data_s3 (data_s4),
.data_s4 (data_s5),
.data_s5 (data_s6),
.mac_data_0 (intp2_2),
.mac_data_1 (intp2_3));
// interpolators (stage-1)
ad_intp2_2 i_intp2_2 (
.clk (clk),
.data (data),
.intp2_0 (intp2_0_s),
.intp2_1 (intp2_1_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32x256.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_32x256 (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input rden;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.rden_b (rden),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK1",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL rdaddress[7..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL wraddress[7..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// File: RAMConcur_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Jun 27 01:12:16 2018
`timescale 1ns/10ps
module RAMConcur_TBV (
);
// Verilog Only Testbench for `RAMConcur`
reg [3:0] addr = 0;
wire [3:0] dout;
reg clk = 0;
reg [3:0] din = 0;
reg writeE = 0;
reg [3:0] RAMConcur0_0_1_2_memory [0:4-1];
initial begin: INITIALIZE_RAMCONCUR0_0_1_2_MEMORY
integer i;
for(i=0; i<4; i=i+1) begin
RAMConcur0_0_1_2_memory[i] = 0;
end
end
always @(posedge clk) begin: RAMCONCUR_TBV_RAMCONCUR0_0_1_2_WRITEACTION
if (writeE) begin
RAMConcur0_0_1_2_memory[addr] <= din;
end
end
assign dout = RAMConcur0_0_1_2_memory[addr];
initial begin: RAMCONCUR_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: RAMCONCUR_TBV_STIMULES
integer i;
for (i=0; i<1; i=i+1) begin
@(negedge clk);
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case (i)
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case ((-i))
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
$finish;
end
always @(posedge clk) begin: RAMCONCUR_TBV_PRINT_DATA
$write("%h", addr);
$write(" ");
$write("%h", din);
$write(" ");
$write("%h", writeE);
$write(" ");
$write("%h", dout);
$write(" ");
$write("%h", clk);
$write("\n");
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../lib/radar_config.vh"
module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Control and configuration outputs
output reset_o;
output tx_side_o;
output dbg_o;
output tx_strobe_o;
output tx_ctrl_o;
output rx_ctrl_o;
output [15:0] ampl_o;
output [31:0] fstart_o;
output [31:0] fincr_o;
output [15:0] pulse_num_o;
output io_tx_ena_o;
// Internal configuration
wire lp_ena;
wire md_ena;
wire dr_ena;
wire [1:0] chirps;
wire [15:0] t_on;
wire [15:0] t_sw;
wire [15:0] t_look;
wire [31:0] t_idle;
wire [31:0] atrdel;
// Configuration from host
wire [31:0] mode;
setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(mode));
assign reset_o = mode[0];
assign tx_side_o = mode[1];
assign lp_ena = mode[2];
assign md_ena = mode[3];
assign dr_ena = mode[4];
assign chirps = mode[6:5];
assign dbg_o = mode[7];
setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_on));
setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_sw));
setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_look));
setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_idle));
setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(ampl_o));
setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fstart_o));
setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fincr_o));
setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(atrdel));
// Pulse state machine
`define ST_ON 4'b0001
`define ST_SW 4'b0010
`define ST_LOOK 4'b0100
`define ST_IDLE 4'b1000
reg [3:0] state;
reg [31:0] count;
reg [15:0] pulse_num_o;
always @(posedge clk_i)
if (reset_o)
begin
state <= `ST_ON;
count <= 32'b0;
pulse_num_o <= 16'b0;
end
else
case (state)
`ST_ON:
if (count == {16'b0,t_on})
begin
state <= `ST_SW;
count <= 32'b0;
pulse_num_o <= pulse_num_o + 16'b1;
end
else
count <= count + 32'b1;
`ST_SW:
if (count == {16'b0,t_sw})
begin
state <= `ST_LOOK;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_LOOK:
if (count == {16'b0,t_look})
begin
state <= `ST_IDLE;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_IDLE:
if (count == t_idle)
begin
state <= `ST_ON;
count <= 32'b0;
end
else
count <= count + 32'b1;
default: // Invalid state, reset state machine
begin
state <= `ST_ON;
count <= 32'b0;
end
endcase
assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
assign tx_ctrl_o = (state == `ST_ON);
assign rx_ctrl_o = (state == `ST_LOOK);
// Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
.tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
.atr_tx_o(io_tx_ena_o));
endmodule // radar_control
|
`timescale 1ns / 1ps
module testbench;
parameter [0:0] NEG_TRIGGER = 0;
parameter [0:0] C_REG = 0;
parameter [0:0] A_REG = 0;
parameter [0:0] B_REG = 0;
parameter [0:0] D_REG = 0;
parameter [0:0] TOP_8x8_MULT_REG = 0;
parameter [0:0] BOT_8x8_MULT_REG = 0;
parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
parameter [1:0] TOPOUTPUT_SELECT = 0;
parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
parameter [1:0] BOTOUTPUT_SELECT = 0;
parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
parameter [0:0] MODE_8x8 = 0;
parameter [0:0] A_SIGNED = 0;
parameter [0:0] B_SIGNED = 0;
reg CLK, CE;
reg [15:0] C, A, B, D;
reg AHOLD, BHOLD, CHOLD, DHOLD;
reg IRSTTOP, IRSTBOT;
reg ORSTTOP, ORSTBOT;
reg OLOADTOP, OLOADBOT;
reg ADDSUBTOP, ADDSUBBOT;
reg OHOLDTOP, OHOLDBOT;
reg CI, ACCUMCI, SIGNEXTIN;
output [31:0] REF_O, UUT_O;
output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
integer errcount = 0;
task clkcycle;
begin
#5;
CLK = ~CLK;
#10;
CLK = ~CLK;
#2;
if (REF_O !== UUT_O) begin
$display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
errcount = errcount + 1;
end
if (REF_CO !== UUT_CO) begin
$display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
errcount = errcount + 1;
end
if (REF_ACCUMCO !== UUT_ACCUMCO) begin
$display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
errcount = errcount + 1;
end
if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
$display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
errcount = errcount + 1;
end
#3;
end
endtask
initial begin
$dumpfile("test_dsp_model.vcd");
$dumpvars(0, testbench);
#2;
CLK = NEG_TRIGGER;
CE = 1;
{C, A, B, D} = 0;
{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
{OLOADTOP, OLOADBOT} = 0;
{ADDSUBTOP, ADDSUBBOT} = 0;
{OHOLDTOP, OHOLDBOT} = 0;
{CI, ACCUMCI, SIGNEXTIN} = 0;
{IRSTTOP, IRSTBOT} = ~0;
{ORSTTOP, ORSTBOT} = ~0;
#3;
{IRSTTOP, IRSTBOT} = 0;
{ORSTTOP, ORSTBOT} = 0;
repeat (300) begin
clkcycle;
A = $urandom;
B = $urandom;
C = $urandom;
D = $urandom;
{AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
{OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
{ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
{OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
{CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
{IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
{ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
end
if (errcount == 0) begin
$display("All tests passed.");
$finish;
end else begin
$display("Caught %1d errors.", errcount);
$stop;
end
end
SB_MAC16 #(
.NEG_TRIGGER (NEG_TRIGGER ),
.C_REG (C_REG ),
.A_REG (A_REG ),
.B_REG (B_REG ),
.D_REG (D_REG ),
.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
.MODE_8x8 (MODE_8x8 ),
.A_SIGNED (A_SIGNED ),
.B_SIGNED (B_SIGNED )
) ref (
.CLK (CLK ),
.CE (CE ),
.C (C ),
.A (A ),
.B (B ),
.D (D ),
.AHOLD (AHOLD ),
.BHOLD (BHOLD ),
.CHOLD (CHOLD ),
.DHOLD (DHOLD ),
.IRSTTOP (IRSTTOP ),
.IRSTBOT (IRSTBOT ),
.ORSTTOP (ORSTTOP ),
.ORSTBOT (ORSTBOT ),
.OLOADTOP (OLOADTOP ),
.OLOADBOT (OLOADBOT ),
.ADDSUBTOP (ADDSUBTOP ),
.ADDSUBBOT (ADDSUBBOT ),
.OHOLDTOP (OHOLDTOP ),
.OHOLDBOT (OHOLDBOT ),
.CI (CI ),
.ACCUMCI (ACCUMCI ),
.SIGNEXTIN (SIGNEXTIN ),
.O (REF_O ),
.CO (REF_CO ),
.ACCUMCO (REF_ACCUMCO ),
.SIGNEXTOUT (REF_SIGNEXTOUT)
);
SB_MAC16_UUT #(
.NEG_TRIGGER (NEG_TRIGGER ),
.C_REG (C_REG ),
.A_REG (A_REG ),
.B_REG (B_REG ),
.D_REG (D_REG ),
.TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ),
.BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ),
.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
.TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ),
.TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ),
.TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ),
.TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ),
.BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ),
.BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ),
.BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ),
.BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ),
.MODE_8x8 (MODE_8x8 ),
.A_SIGNED (A_SIGNED ),
.B_SIGNED (B_SIGNED )
) uut (
.CLK (CLK ),
.CE (CE ),
.C (C ),
.A (A ),
.B (B ),
.D (D ),
.AHOLD (AHOLD ),
.BHOLD (BHOLD ),
.CHOLD (CHOLD ),
.DHOLD (DHOLD ),
.IRSTTOP (IRSTTOP ),
.IRSTBOT (IRSTBOT ),
.ORSTTOP (ORSTTOP ),
.ORSTBOT (ORSTBOT ),
.OLOADTOP (OLOADTOP ),
.OLOADBOT (OLOADBOT ),
.ADDSUBTOP (ADDSUBTOP ),
.ADDSUBBOT (ADDSUBBOT ),
.OHOLDTOP (OHOLDTOP ),
.OHOLDBOT (OHOLDBOT ),
.CI (CI ),
.ACCUMCI (ACCUMCI ),
.SIGNEXTIN (SIGNEXTIN ),
.O (UUT_O ),
.CO (UUT_CO ),
.ACCUMCO (UUT_ACCUMCO ),
.SIGNEXTOUT (UUT_SIGNEXTOUT)
);
endmodule
module testbench_comb_8x8_A;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_8x8_A_signedA;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_8x8_A_signedB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_comb_8x8_A_signedAB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_comb_8x8_B;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_8x8_B_signedA;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_8x8_B_signedB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_comb_8x8_B_signedAB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_comb_16x16;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_16x16_signedA;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_comb_16x16_signedB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_comb_16x16_signedAB;
testbench #(
.NEG_TRIGGER (0),
.C_REG (0),
.A_REG (0),
.B_REG (0),
.D_REG (0),
.TOP_8x8_MULT_REG (0),
.BOT_8x8_MULT_REG (0),
.PIPELINE_16x16_MULT_REG1 (0),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (1),
.B_SIGNED (1)
) testbench ();
endmodule
module testbench_seq_16x16_A;
testbench #(
.NEG_TRIGGER (0),
.C_REG (1),
.A_REG (1),
.B_REG (1),
.D_REG (1),
.TOP_8x8_MULT_REG (1),
.BOT_8x8_MULT_REG (1),
.PIPELINE_16x16_MULT_REG1 (1),
.PIPELINE_16x16_MULT_REG2 (1),
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (0)
) testbench ();
endmodule
module testbench_seq_16x16_B;
testbench #(
.NEG_TRIGGER (0),
.C_REG (1),
.A_REG (1),
.B_REG (1),
.D_REG (1),
.TOP_8x8_MULT_REG (1),
.BOT_8x8_MULT_REG (1),
.PIPELINE_16x16_MULT_REG1 (1),
.PIPELINE_16x16_MULT_REG2 (0),
.TOPOUTPUT_SELECT (1), // 0=P, 1=Q, 2=8x8, 3=16x16
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.BOTOUTPUT_SELECT (1), // 0=R, 1=S, 2=8x8, 3=16x16
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
.MODE_8x8 (0),
.A_SIGNED (0),
.B_SIGNED (0)
) testbench ();
endmodule
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
|
`timescale 1ns / 1ps
//*************************************************************************
// > ÎļþÃû: regfile.v
// > ÃèÊö £º¼Ä´æÆ÷¶ÑÄ£¿é£¬Í¬²½Ð´£¬Òì²½¶Á
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module regfile(
input clk,
input wen,
input [4 :0] raddr1,
input [4 :0] raddr2,
input [4 :0] waddr,
input [31:0] wdata,
output reg [31:0] rdata1,
output reg [31:0] rdata2,
input [4 :0] test_addr,
output reg [31:0] test_data
);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
always @(posedge clk)
begin
if (wen)
begin
rf[waddr] <= wdata;
end
end
//¶Á¶Ë¿Ú1
always @(*)
begin
case (raddr1)
5'd1 : rdata1 <= rf[1 ];
5'd2 : rdata1 <= rf[2 ];
5'd3 : rdata1 <= rf[3 ];
5'd4 : rdata1 <= rf[4 ];
5'd5 : rdata1 <= rf[5 ];
5'd6 : rdata1 <= rf[6 ];
5'd7 : rdata1 <= rf[7 ];
5'd8 : rdata1 <= rf[8 ];
5'd9 : rdata1 <= rf[9 ];
5'd10: rdata1 <= rf[10];
5'd11: rdata1 <= rf[11];
5'd12: rdata1 <= rf[12];
5'd13: rdata1 <= rf[13];
5'd14: rdata1 <= rf[14];
5'd15: rdata1 <= rf[15];
5'd16: rdata1 <= rf[16];
5'd17: rdata1 <= rf[17];
5'd18: rdata1 <= rf[18];
5'd19: rdata1 <= rf[19];
5'd20: rdata1 <= rf[20];
5'd21: rdata1 <= rf[21];
5'd22: rdata1 <= rf[22];
5'd23: rdata1 <= rf[23];
5'd24: rdata1 <= rf[24];
5'd25: rdata1 <= rf[25];
5'd26: rdata1 <= rf[26];
5'd27: rdata1 <= rf[27];
5'd28: rdata1 <= rf[28];
5'd29: rdata1 <= rf[29];
5'd30: rdata1 <= rf[30];
5'd31: rdata1 <= rf[31];
default : rdata1 <= 32'd0;
endcase
end
//¶Á¶Ë¿Ú2
always @(*)
begin
case (raddr2)
5'd1 : rdata2 <= rf[1 ];
5'd2 : rdata2 <= rf[2 ];
5'd3 : rdata2 <= rf[3 ];
5'd4 : rdata2 <= rf[4 ];
5'd5 : rdata2 <= rf[5 ];
5'd6 : rdata2 <= rf[6 ];
5'd7 : rdata2 <= rf[7 ];
5'd8 : rdata2 <= rf[8 ];
5'd9 : rdata2 <= rf[9 ];
5'd10: rdata2 <= rf[10];
5'd11: rdata2 <= rf[11];
5'd12: rdata2 <= rf[12];
5'd13: rdata2 <= rf[13];
5'd14: rdata2 <= rf[14];
5'd15: rdata2 <= rf[15];
5'd16: rdata2 <= rf[16];
5'd17: rdata2 <= rf[17];
5'd18: rdata2 <= rf[18];
5'd19: rdata2 <= rf[19];
5'd20: rdata2 <= rf[20];
5'd21: rdata2 <= rf[21];
5'd22: rdata2 <= rf[22];
5'd23: rdata2 <= rf[23];
5'd24: rdata2 <= rf[24];
5'd25: rdata2 <= rf[25];
5'd26: rdata2 <= rf[26];
5'd27: rdata2 <= rf[27];
5'd28: rdata2 <= rf[28];
5'd29: rdata2 <= rf[29];
5'd30: rdata2 <= rf[30];
5'd31: rdata2 <= rf[31];
default : rdata2 <= 32'd0;
endcase
end
//µ÷ÊԶ˿ڣ¬¶Á³ö¼Ä´æÆ÷ÖµÏÔʾÔÚ´¥ÃþÆÁÉÏ
always @(*)
begin
case (test_addr)
5'd1 : test_data <= rf[1 ];
5'd2 : test_data <= rf[2 ];
5'd3 : test_data <= rf[3 ];
5'd4 : test_data <= rf[4 ];
5'd5 : test_data <= rf[5 ];
5'd6 : test_data <= rf[6 ];
5'd7 : test_data <= rf[7 ];
5'd8 : test_data <= rf[8 ];
5'd9 : test_data <= rf[9 ];
5'd10: test_data <= rf[10];
5'd11: test_data <= rf[11];
5'd12: test_data <= rf[12];
5'd13: test_data <= rf[13];
5'd14: test_data <= rf[14];
5'd15: test_data <= rf[15];
5'd16: test_data <= rf[16];
5'd17: test_data <= rf[17];
5'd18: test_data <= rf[18];
5'd19: test_data <= rf[19];
5'd20: test_data <= rf[20];
5'd21: test_data <= rf[21];
5'd22: test_data <= rf[22];
5'd23: test_data <= rf[23];
5'd24: test_data <= rf[24];
5'd25: test_data <= rf[25];
5'd26: test_data <= rf[26];
5'd27: test_data <= rf[27];
5'd28: test_data <= rf[28];
5'd29: test_data <= rf[29];
5'd30: test_data <= rf[30];
5'd31: test_data <= rf[31];
default : test_data <= 32'd0;
endcase
end
endmodule
|
module wavepool_tb;
//wires
reg clk;
reg rst;
reg fetch_reserve_valid, fetch_basereg_wr, buff2fetchwave_ack, issue_wf_done_en,
salu_branch_en, salu_branch_taken;
reg[5:0] fetch_reserve_slotid, fetch_basereg_wfid, issue_wf_done_wf_id,
salu_branch_wfid;
reg[8:0] fetch_sgpr_base;
reg[9:0] fetch_vgpr_base;
reg[15:0] fetch_lds_base;
reg[31:0] buff_instr;
reg[38:0] buff_tag;
reg[39:0] issue_valid_entries;
reg decode_ins_half_rqd;
reg[5:0] decode_ins_half_wfid;
wire decode_instr_valid;
wire[5:0] decode_wfid;
wire[8:0] decode_sgpr_base;
wire[9:0] decode_vgpr_base;
wire[15:0] decode_lds_base;
wire[31:0] decode_instr, decode_instr_pc;
wire[39:0] fetch_stop_fetch;
//instantiation of dut
wavepool wavepool0(
.fetch_reserve_slotid(fetch_reserve_slotid),
.fetch_reserve_valid(fetch_reserve_valid),
.fetch_basereg_wr(fetch_basereg_wr),
.fetch_basereg_wfid(fetch_basereg_wfid),
.fetch_vgpr_base(fetch_vgpr_base),
.fetch_sgpr_base(fetch_sgpr_base),
.fetch_lds_base(fetch_lds_base),
.issue_valid_entries(issue_valid_entries),
.decode_ins_half_rqd(decode_ins_half_rqd),
.decode_ins_half_wfid(decode_ins_half_wfid),
.buff_tag(buff_tag),
.buff_instr(buff_instr),
.buff2fetchwave_ack(buff2fetchwave_ack),
.issue_wf_done_en(issue_wf_done_en),
.issue_wf_done_wf_id(issue_wf_done_wf_id),
.salu_branch_wfid(salu_branch_wfid),
.salu_branch_en(salu_branch_en),
.salu_branch_taken(salu_branch_taken),
.fetch_stop_fetch(fetch_stop_fetch),
.decode_instr_valid(decode_instr_valid),
.decode_instr(decode_instr),
.decode_wfid(decode_wfid),
.decode_vgpr_base(decode_vgpr_base),
.decode_sgpr_base(decode_sgpr_base),
.decode_lds_base(decode_lds_base),
.decode_instr_pc(decode_instr_pc),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
fetch_reserve_valid = 1'b0;
fetch_basereg_wr = 1'b0;
issue_valid_entries = 1'b0;
decode_ins_half_rqd = 1'b0;
buff2fetchwave_ack = 1'b0;
issue_wf_done_en = 1'b0;
salu_branch_en = 1'b0;
salu_branch_taken = 1'b0;
#10 rst = 1'b0;
#2000;
$finish;
end
initial begin
#31;
fetch_reserve_valid = 1'b1;
fetch_reserve_slotid = 6'd17;
#10;
fetch_reserve_valid = 1'b0;
buff2fetchwave_ack = 1'b1;
buff_instr = 32'hdead_babe;
buff_tag = {1'b1,6'd17,32'hcafe_f00d};
#10;
buff2fetchwave_ack = 1'b0;
fetch_reserve_valid = 1'b1;
fetch_reserve_slotid = 6'd17;
#10;
fetch_reserve_valid = 1'b0;
buff2fetchwave_ack = 1'b1;
buff_instr = 32'hdeaf_beef;
buff_tag = {1'b0,6'd17,32'hcafe_f011};
#10;
buff2fetchwave_ack = 1'b0;
#30;
decode_ins_half_rqd = 1'b1;
decode_ins_half_wfid = 6'd17;
#10;
decode_ins_half_rqd = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor("test output = %b", rst);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,wavepool_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
// file: Clock65MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock65MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock65MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
`include "bsg_defines.v"
// MBT 11/26/2014, bsg_fsb_node_trace_replay
// Shaolin 01/06/2018, generalized from the bsg_trace_replay
// trace format (see enum below)
//
// Debug Display Levels:
// 0 = suppress all non-errors. only shows mismatch and unknown op
// (default) 1 = adds finish and done
// 2 = all messages. adds send, recv, cycle dec, and cycle init
module bsg_trace_replay
#( parameter payload_width_p =80
, parameter rom_addr_width_p=6
, parameter counter_width_p=`BSG_MIN(payload_width_p,16)
, parameter debug_p = 1
, parameter finish_on_error_p = 1
//The operation code is always 4 bits.
, parameter opcode_width_lp = 4
)
( input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [payload_width_p-1:0] data_i
, output logic ready_o
// output channel
, output logic v_o
, output logic [payload_width_p-1:0] data_o
, input yumi_i
// connection to rom
// note: asynchronous reads
, output [rom_addr_width_p-1:0] rom_addr_o
, input [payload_width_p+4-1:0] rom_data_i
// true outputs
, output logic done_o
, output logic error_o
);
// 0: wait one cycle
// 1: send data
// 2: receive data (and check its value)
// 3: assert done_o; test complete.
// 4: end test; call $finish
// 5: decrement cycle counter; wait for cycle_counter == 0
// 6: initialized cycle counter with 16 bits
// in theory, we could add branching, etc.
// before we know it, we have a processor =)
typedef enum logic [opcode_width_lp-1:0] {
eNop=4'd0,
eSend=4'd1,
eReceive=4'd2,
eDone=4'd3,
eFinish=4'd4,
eCycleDec=4'd5,
eCycleInit=4'd6
} eOp;
logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n;
logic [rom_addr_width_p-1:0] addr_r, addr_n;
logic done_r, done_n;
logic error_r, error_n;
assign rom_addr_o = addr_r;
assign data_o = rom_data_i[0+:payload_width_p];
assign done_o = done_r;
assign error_o = error_r;
always_ff @(posedge clk_i) begin
if (reset_i) begin
addr_r <= 0;
done_r <= 0;
error_r <= 0;
cycle_ctr_r <= 16'b1;
end else begin
addr_r <= addr_n;
done_r <= done_n;
error_r <= error_n;
cycle_ctr_r <= cycle_ctr_n;
end
end // always_ff @
logic [3:0] op;
assign op = rom_data_i[payload_width_p+:4];
logic instr_completed;
assign addr_n = instr_completed ? (addr_r+1'b1) : addr_r;
// handle outputs
always_comb begin
// defaults; not sending and not receiving unless done
v_o = 1'b0;
ready_o = done_r;
done_n = done_r;
if (!done_r & en_i & ~reset_i) begin
case (op)
eSend: v_o = 1'b1;
eReceive: ready_o = 1'b1;
eDone: done_n = 1'b1;
default:
begin
end
endcase
end
end // always_comb
// next instruction logic
always_comb begin
instr_completed = 1'b0;
error_n = error_r;
cycle_ctr_n = cycle_ctr_r;
if (!done_r & en_i & ~reset_i) begin
case (op)
eNop: instr_completed = 1'b1;
eSend: if (yumi_i) instr_completed = 1'b1;
eReceive: begin
if (v_i)
begin
instr_completed = 1'b1;
if (error_r == 0)
error_n = data_i != data_o;
end
end
eDone: instr_completed = 1'b1;
eFinish: instr_completed = 1'b1;
eCycleDec:
begin
cycle_ctr_n = cycle_ctr_r - 1'b1;
instr_completed = ~(|cycle_ctr_r);
end
eCycleInit:
begin
cycle_ctr_n = rom_data_i[counter_width_p-1:0];
instr_completed = 1'b1;
end
default:
begin
error_n = 1'b1;
instr_completed = 1'b1;
end
endcase // case (op)
end
end
// non-synthesizeable components
always @(negedge clk_i) begin
if (instr_completed & ~reset_i & ~done_r) begin
case(op)
eNop: begin end
eSend: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay SEND %d'b%b (%m)", payload_width_p,data_o);
end
end
eReceive: begin
if (data_i !== data_o) begin
$display("############################################################################");
$display("### bsg_trace_replay RECEIVE unmatched (%m) ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_o);
$display("############################################################################");
if (finish_on_error_p == 1) begin
$finish();
end
end else begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay RECEIVE matched %h (%m)", data_o);
end
end // else: !if(data_i != data_o)
end
eDone: begin
if (debug_p >= 1) begin
$display("############################################################################");
$display("###### bsg_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o);
$display("############################################################################");
end
end
eFinish: begin
if (debug_p >= 1) begin
$display("############################################################################");
$display("###### bsg_trace_replay FINISH (trace finished; CALLING $finish) (%m)");
$display("############################################################################");
end
$finish;
end
eCycleDec: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r);
end
end
eCycleInit: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n);
end
end
default: begin
$error("### bsg_trace_replay UNKNOWN op %x (%m)\n", op);
if (finish_on_error_p == 1) begin
$finish();
end
end
endcase // case (op)
end // if (instr_completed & ~reset_i & ~done_r)
end // always @ (negedge clk_i)
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_master_wbs_16
*/
module test_i2c_master_wbs_16;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [2:0] wbs_adr_i = 0;
reg [15:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg [1:0] wbs_sel_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire [15:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbs_adr_i,
wbs_dat_i,
wbs_we_i,
wbs_sel_i,
wbs_stb_i,
wbs_cyc_i,
i2c_scl_i,
i2c_sda_i
);
$to_myhdl(
wbs_dat_o,
wbs_ack_o,
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t
);
// dump file
$dumpfile("test_i2c_master_wbs_16.lxt");
$dumpvars(0, test_i2c_master_wbs_16);
end
i2c_master_wbs_16 #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_stb_i(wbs_stb_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// AXI4MasterInterfaceWriteChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4 master interface write channel
// Module Name: AXI4MasterInterfaceWriteChannel
// File Name: AXI4MasterInterfaceWriteChannel.v
//
// Version: v1.0.0
//
// Description: AXI4 compliant write channel control for master interface
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4MasterInterfaceWriteChannel
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter MaxDivider = 16
)
(
ACLK ,
ARESETN ,
OUTER_AWADDR ,
OUTER_AWLEN ,
OUTER_AWSIZE ,
OUTER_AWBURST ,
OUTER_AWCACHE ,
OUTER_AWPROT ,
OUTER_AWVALID ,
OUTER_AWREADY ,
OUTER_WDATA ,
OUTER_WSTRB ,
OUTER_WLAST ,
OUTER_WVALID ,
OUTER_WREADY ,
OUTER_BRESP ,
OUTER_BVALID ,
OUTER_BREADY ,
INNER_AWADDR ,
INNER_AWLEN ,
INNER_AWVALID ,
INNER_AWREADY ,
INNER_WDATA ,
INNER_WLAST ,
INNER_WVALID ,
INNER_WREADY
);
input ACLK ;
input ARESETN ;
output [AddressWidth - 1:0] OUTER_AWADDR ;
output [7:0] OUTER_AWLEN ;
output [2:0] OUTER_AWSIZE ;
output [1:0] OUTER_AWBURST ;
output [3:0] OUTER_AWCACHE ;
output [2:0] OUTER_AWPROT ;
output OUTER_AWVALID ;
input OUTER_AWREADY ;
output [DataWidth - 1:0] OUTER_WDATA ;
output [(DataWidth/8) - 1:0] OUTER_WSTRB ;
output OUTER_WLAST ;
output OUTER_WVALID ;
input OUTER_WREADY ;
input [1:0] OUTER_BRESP ;
input OUTER_BVALID ;
output OUTER_BREADY ;
input [AddressWidth - 1:0] INNER_AWADDR ;
input [InnerIFLengthWidth - 1:0] INNER_AWLEN ;
input INNER_AWVALID ;
output INNER_AWREADY ;
input [DataWidth - 1:0] INNER_WDATA ;
input INNER_WLAST ;
input INNER_WVALID ;
output INNER_WREADY ;
wire [AddressWidth - 1:0] wDivAddress ;
wire [7:0] wDivLength ;
wire wDivValid ;
wire wDivReady ;
wire wDivFlush ;
wire wWCmdQPopSignal ;
wire wIsWCmdQFull ;
wire wIsWCmdQEmpty ;
wire [AddressWidth - 1:0] wQdDivAddress ;
wire [7:0] wQdDivLength ;
wire wQdDivValid ;
wire wQdDivReady ;
wire wDivReadyCond ;
reg rBREADY ;
reg [15:0] rBREADYCount ;
assign OUTER_BREADY = rBREADY;
always @ (posedge ACLK)
if (!ARESETN)
rBREADYCount <= 16'b0;
else
if ((OUTER_AWVALID & OUTER_AWREADY) && !(OUTER_BVALID & OUTER_BREADY))
rBREADYCount <= rBREADYCount + 1'b1;
else if (!(OUTER_AWVALID & OUTER_AWREADY) && (OUTER_BVALID & OUTER_BREADY))
rBREADYCount <= rBREADYCount - 1'b1;
always @ (*)
if (OUTER_BVALID && (rBREADYCount != 16'b0))
rBREADY <= 1'b1;
else
rBREADY <= 1'b0;
AXI4CommandDivider
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.MaxDivider (MaxDivider )
)
Inst_AXI4WriteCommandDivider
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.SRCADDR (INNER_AWADDR ),
.SRCLEN (INNER_AWLEN ),
.SRCVALID (INNER_AWVALID ),
.SRCREADY (INNER_AWREADY ),
.SRCREADYCOND (1'b1 ),
.DIVADDR (wDivAddress ),
.DIVLEN (wDivLength ),
.DIVVALID (wDivValid ),
.DIVREADY (wDivReady ),
.DIVFLUSH (wDivFlush )
);
assign wDivReady = !wIsWCmdQFull;
SCFIFO_80x64_withCount
Inst_AXI4WriteCommandQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData ({wDivAddress, wDivLength} ),
.iPushEnable (wDivValid & wDivReady ),
.oIsFull (wIsWCmdQFull ),
.oPopData ({wQdDivAddress, wQdDivLength} ),
.iPopEnable (wWCmdQPopSignal ),
.oIsEmpty (wIsWCmdQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4WriteCommandQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wWCmdQPopSignal),
.iEmpty (wIsWCmdQEmpty ),
.oValid (wQdDivValid ),
.iReady (wQdDivReady )
);
AXI4CommandDriver
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth )
)
Inst_AXI4WriteCommandDriver
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.AXADDR (OUTER_AWADDR ),
.AXLEN (OUTER_AWLEN ),
.AXSIZE (OUTER_AWSIZE ),
.AXBURST (OUTER_AWBURST ),
.AXCACHE (OUTER_AWCACHE ),
.AXPROT (OUTER_AWPROT ),
.AXVALID (OUTER_AWVALID ),
.AXREADY (OUTER_AWREADY ),
.SRCADDR (wQdDivAddress ),
.SRCLEN (wQdDivLength ),
.SRCVALID (wQdDivValid ),
.SRCREADY (wQdDivReady ),
.SRCFLUSH (wDivFlush ),
.SRCREADYCOND (wDivReadyCond )
);
wire [InnerIFLengthWidth - 1:0] wQdWLen ;
wire wIsWLenQFull ;
wire wIsWLenQEmpty ;
wire wWLenQPopSignal ;
wire wQdWLenValid ;
wire wQdWLenReady ;
assign wDivReadyCond = !wIsWLenQFull;
SCFIFO_40x64_withCount
Inst_AXI4WriteLengthQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData (wQdDivLength ),
.iPushEnable (wQdDivValid && wQdDivReady ),
.oIsFull (wIsWLenQFull ),
.oPopData (wQdWLen ),
.iPopEnable (wWLenQPopSignal ),
.oIsEmpty (wIsWLenQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4WriteLengthQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wWLenQPopSignal),
.iEmpty (wIsWLenQEmpty ),
.oValid (wQdWLenValid ),
.iReady (wQdWLenReady )
);
wire [DataWidth - 1:0] wQdWData ;
wire wIsWDataQFull ;
wire wIsWDataQEmpty ;
wire wWDataQPopSignal;
wire wQdWDataValid ;
wire wQdWDataReady ;
assign INNER_WREADY = !wIsWDataQFull;
SCFIFO_64x64_withCount
Inst_AXI4WriteDataQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData (INNER_WDATA ),
.iPushEnable (INNER_WVALID && INNER_WREADY ),
.oIsFull (wIsWDataQFull ),
.oPopData (wQdWData ),
.iPopEnable (wWDataQPopSignal ),
.oIsEmpty (wIsWDataQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4WriteDataQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wWDataQPopSignal ),
.iEmpty (wIsWDataQEmpty ),
.oValid (wQdWDataValid ),
.iReady (wQdWDataReady )
);
AXI4DataDriver
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.LengthWidth (8 )
)
Inst_AXI4WriteDataDriver
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.SRCLEN (wQdWLen ),
.SRCVALID (wQdWLenValid ),
.SRCREADY (wQdWLenReady ),
.DATA (wQdWData ),
.DVALID (wQdWDataValid ),
.DREADY (wQdWDataReady ),
.XDATA (OUTER_WDATA ),
.XDVALID (OUTER_WVALID ),
.XDREADY (OUTER_WREADY ),
.XDLAST (OUTER_WLAST )
);
assign OUTER_WSTRB = {(DataWidth/8){1'b1}};
endmodule
|
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_4_wrapper.v
//-----------------------------------------------------------------------------
module system_nfa_accept_samples_generic_hw_top_4_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD4000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD40000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_4 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_mux.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_arb_mux #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
parameter nCS_PER_RANK = 1,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nSLOTS = 2,
parameter nWR = 6, // Write recovery (CKs)
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(/*AUTOARG*/
// Outputs
output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
output col_periodic_rd, // From arb_select0 of arb_select.v
output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
output col_rmw, // From arb_select0 of arb_select.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
output col_size, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v
output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_pre,
output sent_col, // From arb_row_col0 of arb_row_col.v
output sent_col_r, // From arb_row_col0 of arb_row_col.v
output sent_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_col,
output rnk_config_strobe,
output insert_maint_r1,
output rnk_config_kill_rts_col,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
input insert_maint_r, // To arb_row_col0 of arb_row_col.v
input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
input maint_zq_r, // To arb_select0 of arb_select.v
input maint_sre_r, // To arb_select0 of arb_select.v
input maint_srx_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
input [7:0] slot_0_present, // To arb_select0 of arb_select.v
input [7:0] slot_1_present // To arb_select0 of arb_select.v
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cs_en0; // From arb_row_col0 of arb_row_col.v
wire cs_en1; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_col;
wire send_cmd2_row;
wire send_cmd2_col;
wire send_cmd2_pre;
wire send_cmd3_col;
wire [5:0] col_channel_offset;
// End of automatics
wire sent_col_i;
wire cs_en2;
wire cs_en3;
assign sent_col = sent_col_i;
mig_7series_v2_3_arb_row_col #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.CWL (CWL),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nRAS (nRAS),
.nRCD (nRCD),
.nWR (nWR))
arb_row_col0
(/*AUTOINST*/
// Outputs
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.sent_row (sent_row),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col_i),
.sent_col_r (sent_col_r),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.col_channel_offset (col_channel_offset),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.clk (clk),
.rst (rst),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.rts_col (rts_col[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
mig_7series_v2_3_arb_select #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nSLOTS (nSLOTS),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_select0
(/*AUTOINST*/
// Outputs
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_size (col_size),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_cas_slot (mc_cas_slot),
.col_channel_offset (col_channel_offset),
.rnk_config (rnk_config),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 11:45:21 03/21/2016
// Design Name:
// Module Name: timing_generator_VGA
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timing_generator_VGA
(
input wire clk,reset,
output wire hsync,vsync,video_on,p_tick,
output wire [9:0] pixel_x, pixel_y
);
//Declaración de constantes
//Parámetros para VGA 640x480
localparam HD = 640;//área de despliegue horizontal
localparam HF = 48;// borde izquierdo horizontal
localparam HB = 16;//borde derecho horizontal(16)
localparam HR = 96;//retraso horizontal
localparam VD = 480;//área de despliegue vertical
localparam VF = 10;//borde superior vertical
localparam VB = 33;//borde inferior vertical
localparam VR = 2;//retraso vertical
//Contadores
//Contador para la división de frecuencia (100 MHz a 25 MHz)
//reg mod2_reg;
//wire mod2_next;
reg cuenta, CV;
//Contadores de "timing" vertical y horizontal
reg[9:0] h_count_reg, h_count_next;
reg[9:0] v_count_reg, v_count_next;
reg h_sync_reg, v_sync_reg;
wire h_sync_next, v_sync_next;
//Señales de status
wire h_end, v_end;
wire pixel_tick;
//Definición de comportamiento
//Registros
always @(posedge clk, posedge reset)
begin
if(reset)
begin
//mod2_reg <= 1'b0;
h_count_reg <= 0;
v_count_reg <= 0;
h_sync_reg <= 1'b0;
v_sync_reg <= 1'b0;
end
else
begin
//mod2_reg <= mod2_next;
h_count_reg <= h_count_next;
v_count_reg <= v_count_next;
h_sync_reg <= h_sync_next;
v_sync_reg <= v_sync_next;
end
end
//Para generar 25 MHz
always@(posedge clk, posedge reset)
begin
if(reset)
begin
cuenta <= 0;
CV <= 0;
end
else
begin
if (cuenta == 1'b1)
begin
cuenta <= 0;
CV <= ~CV;
end
else
cuenta <= cuenta + 1'b1;
end
end
//assign mod2_next = ~mod2_reg;
assign pixel_tick = CV;
//Definición señales de status
//Final del contador horizontal (799)
assign h_end = (h_count_reg == (HD+HF+HB+HR-1));
//Final contador vertical (524)
assign v_end = (v_count_reg == (VD+VF+VB+VR-1));
//Lógicas de estado siguiente de los contadores
//Contador horizontal
always@(negedge pixel_tick)
begin
//if(pixel_tick) //pulso de 25 MHz
if(h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1'b1;
/* else
h_count_next = h_count_reg; //Mantiene la cuenta*/
end
//Contador vertical
always@(negedge pixel_tick)
begin
//if(pixel_tick & h_end) //pulso de 25 MHz y final de fila
if(h_end) //pulso de 25 MHz y final de fila
if(v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1'b1;
else
v_count_next = v_count_reg; //Mantiene la cuenta
end
/*h_sync_next puesto en bajo para generar retraso
entre la cuentas 656 y 751*/
assign h_sync_next = (h_count_reg >= (HD+HB)&&
h_count_reg <=(HD+HB+HR-1));
/*v_sync_next puesto en bajo para generar retraso
entre la cuentas 490 y 491*/
assign v_sync_next = (v_count_reg >= (VD+VB)&&
v_count_reg <=(VD+VB+VR-1));
//Asignación de salidas
//Para generar señal video on/off
assign video_on = (h_count_reg < HD) && (v_count_reg < VD); //Para mantener una forma de saber si el pixel está en la región visible
assign hsync = ~h_sync_reg;
assign vsync = ~v_sync_reg;
assign pixel_x = h_count_reg; //Coordenada x
assign pixel_y = v_count_reg; //Coordenada y
assign p_tick = pixel_tick; //Ayuda a coordinar la creación de imágenes (módulo de generación de píxeles)
endmodule
/*Notas:
1. La frecuencia del "timing" vertical
define el tiempo de refresco de la pantalla
(30 fps, 60 fps,etc)
2. 25 MHz es la frecuencia de escritura de cada
píxel (pixel_clk)
3.video_on debe tener un período igual al que corresponde escribir sobre la región visible*/
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 21:40:24 02/29/2016
// Design Name: MDF
// Module Name: D:/ISE/Proyecto1/TB_MDF.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
// Inputs
reg clk;
reg rst;
reg [3:0] entrada;
// Outputs
wire salida;
wire [15:0]q;
// Instantiate the Unit Under Test (UUT)
MDF uut (
.clk(clk),
.rst(rst),
.entrada(entrada),
.salida(salida),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
entrada = 0;
// Wait 100 ns for global reset to finish
#10;
entrada = 4'b1111;
#10000;
entrada = 4'b1010;
end
always #1000 clk = ~clk;
/* initial
begin
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,rst,div,clkd);
end
initial
#500 $finish;
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_TB_V
`define SKY130_FD_SC_LS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_TB_V
|
/*
Anthony De Caria - April 4, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableSixteenAsyncMuxedInput(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [15:0] d;
output [15:0] q;
wire [15:1]muxOut;
mux2to1_1bit One_mux(.data1x(d[1]), .data0x(q[0]), .sel(select), .result(muxOut[1]) );
mux2to1_1bit Two_mux(.data1x(d[2]), .data0x(q[1]), .sel(select), .result(muxOut[2]) );
mux2to1_1bit Three_mux(.data1x(d[3]), .data0x(q[2]), .sel(select), .result(muxOut[3]) );
mux2to1_1bit Four_mux(.data1x(d[4]), .data0x(q[3]), .sel(select), .result(muxOut[4]) );
mux2to1_1bit Five_mux(.data1x(d[5]), .data0x(q[4]), .sel(select), .result(muxOut[5]) );
mux2to1_1bit Six_mux(.data1x(d[6]), .data0x(q[5]), .sel(select), .result(muxOut[6]) );
mux2to1_1bit Seven_mux(.data1x(d[7]), .data0x(q[6]), .sel(select), .result(muxOut[7]) );
mux2to1_1bit Eight_mux(.data1x(d[8]), .data0x(q[7]), .sel(select), .result(muxOut[8]) );
mux2to1_1bit Nine_mux(.data1x(d[9]), .data0x(q[8]), .sel(select), .result(muxOut[9]) );
mux2to1_1bit Ten_mux(.data1x(d[10]), .data0x(q[9]), .sel(select), .result(muxOut[10]) );
mux2to1_1bit Eleven_mux(.data1x(d[11]), .data0x(q[10]), .sel(select), .result(muxOut[11]) );
mux2to1_1bit Twelve_mux(.data1x(d[12]), .data0x(q[11]), .sel(select), .result(muxOut[12]) );
mux2to1_1bit Thirteen_mux(.data1x(d[13]), .data0x(q[12]), .sel(select), .result(muxOut[13]) );
mux2to1_1bit Fourteen_mux(.data1x(d[14]), .data0x(q[13]), .sel(select), .result(muxOut[14]) );
mux2to1_1bit Fifteen_mux(.data1x(d[15]), .data0x(q[14]), .sel(select), .result(muxOut[15]) );
D_FF_with_Enable Zero(.clk(clk), .resetn(resetn), .enable(enable), .d(d[0]), .q(q[0]) );
D_FF_with_Enable One(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[1]), .q(q[1]) );
D_FF_with_Enable Two(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[2]), .q(q[2]) );
D_FF_with_Enable Three(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[3]), .q(q[3]) );
D_FF_with_Enable Four(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[4]), .q(q[4]) );
D_FF_with_Enable Five(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[5]), .q(q[5]) );
D_FF_with_Enable Six(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[6]), .q(q[6]) );
D_FF_with_Enable Seven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[7]), .q(q[7]) );
D_FF_with_Enable Eight(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[8]), .q(q[8]) );
D_FF_with_Enable Nine(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[9]), .q(q[9]) );
D_FF_with_Enable Ten(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[10]), .q(q[10]) );
D_FF_with_Enable Eleven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[11]), .q(q[11]) );
D_FF_with_Enable Twelve(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[12]), .q(q[12]) );
D_FF_with_Enable Thirteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[13]), .q(q[13]) );
D_FF_with_Enable Fourteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[14]), .q(q[14]) );
D_FF_with_Enable Fifteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[15]), .q(q[15]) );
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEV",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEV",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEV",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
// NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.0sp1 232 at 2015.10.21.10:55:06
`timescale 1 ps / 1 ps
module NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [0:0] CS_N, // .CS_N_out
output wire [3:0] ByteEnable_N, // .ByteEnable_N_out
output wire [0:0] OutputEnable_N, // .OutputEnable_N_out
output wire [0:0] Write_N, // .Write_N_out
output wire [31:0] data, // .data_out
input wire [31:0] data_in, // .data_in
output wire data_outen, // .data_outen
output wire [18:0] addr, // .addr_out
output wire [0:0] rst_N, // .rst_N_out
output wire [0:0] begin_N, // .begin_N_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [0:0] tcs0_chipselect_n_out, // .chipselect_n_out
input wire [3:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [31:0] tcs0_data_out, // .data_out
output wire [31:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [18:0] tcs0_address_out, // .address_out
input wire [0:0] tcs0_reset_n_out, // .reset_n_out
input wire [0:0] tcs0_begintransfer_n_out // .begintransfer_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_SRAM_tcm -> arbiter:sink0_valid
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.CS_N (CS_N), // .CS_N_out
.ByteEnable_N (ByteEnable_N), // .ByteEnable_N_out
.OutputEnable_N (OutputEnable_N), // .OutputEnable_N_out
.Write_N (Write_N), // .Write_N_out
.data (data), // .data_out
.data_in (data_in), // .data_in
.data_outen (data_outen), // .data_outen
.addr (addr), // .addr_out
.rst_N (rst_N), // .rst_N_out
.begin_N (begin_N), // .begin_N_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_reset_n_out (tcs0_reset_n_out), // .reset_n_out
.tcs0_tcm_begintransfer_n_out (tcs0_begintransfer_n_out), // .begintransfer_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_SRAM_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_100_125.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 175 10/25/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_100_125 (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
wire [5:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire3 = 1'h0;
wire [0:0] sub_wire5 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire [5:0] sub_wire4 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire5};
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire3, sub_wire6};
wire [3:0] sub_wire8 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3};
altpll altpll_component (
.clkena (sub_wire4),
.inclk (sub_wire7),
.extclkena (sub_wire8),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire2)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 4,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0,
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_wave*.jpg FALSE FALSE
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// interrupt controller for Z80
module interrupts(
clk_24mhz,
clk_z80,
m1_n,
iorq_n,
int_n
);
parameter MAX_INT_LEN = 100;
input clk_24mhz;
input clk_z80;
input m1_n;
input iorq_n;
output reg int_n;
reg [9:0] ctr640;
reg int_24;
reg int_sync1,int_sync2,int_sync3;
reg int_ack_sync,int_ack;
reg int_gen;
// generate int signal
always @(posedge clk_24mhz)
begin
if( ctr640 == 10'd639 )
ctr640 <= 10'd0;
else
ctr640 <= ctr640 + 10'd1;
if( ctr640 == 10'd0 )
int_24 <= 1'b1;
else if( ctr640 == MAX_INT_LEN )
int_24 <= 1'b0;
end
// generate interrupt signal in clk_z80 domain
always @(negedge clk_z80)
begin
int_sync3 <= int_sync2;
int_sync2 <= int_sync1;
int_sync1 <= int_24; // sync in from 24mhz, allow for edge detection (int_sync3!=int_sync2)
int_ack_sync <= ~(m1_n | iorq_n);
int_ack <= int_ack_sync; // interrupt acknowledge from Z80
// control interrupt generation signal
if( int_ack || ( int_sync3 && (!int_sync2) ) )
int_gen <= 1'b0;
else if( (!int_sync3) && int_sync2 )
int_gen <= 1'b1;
end
always @(posedge clk_z80)
begin
int_n <= ~int_gen;
end
endmodule
|
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #
(
// depth of synchronizer
parameter N = 2
)
(
input wire clk,
input wire rst,
output wire out
);
(* srl_style = "register" *)
reg [N-1:0] sync_reg = {N{1'b1}};
assign out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
sync_reg <= {N{1'b1}};
end else begin
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
end
endmodule
`resetall
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_v2h (
// hdmi interface
hdmi_clk,
hdmi_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_be,
vdma_data,
vdma_last,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug interface (chipscope)
vdma_dbg_data,
vdma_dbg_trigger,
hdmi_dbg_data,
hdmi_dbg_trigger);
// hdmi interface
input hdmi_clk;
output [15:0] hdmi_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [ 7:0] vdma_be;
input [63:0] vdma_data;
input vdma_last;
output vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 3:0] up_status;
// debug interface (chipscope)
output [35:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
output [59:0] hdmi_dbg_data;
output [ 7:0] hdmi_dbg_trigger;
reg up_crcb_init = 'd0;
reg up_full_range = 'd0;
reg up_tpg_enable = 'd0;
reg up_csc_bypass = 'd0;
reg up_enable = 'd0;
reg [15:0] up_hs_width = 'd0;
reg [15:0] up_hs_count = 'd0;
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_vs_count = 'd0;
reg up_hdmi_tpm_oos_hold = 'd0;
reg up_vdma_tpm_oos_hold = 'd0;
reg up_vdma_be_error_hold = 'd0;
reg up_vdma_ovf_hold = 'd0;
reg up_vdma_unf_hold = 'd0;
reg up_cp_en = 'd0;
reg [23:0] up_cp = 'd0;
reg [ 3:0] up_status = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_hdmi_tpm_oos_m1 = 'd0;
reg up_vdma_tpm_oos_m1 = 'd0;
reg up_vdma_be_error_m1 = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_vdma_tpm_oos = 'd0;
reg up_vdma_be_error = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf = 'd0;
wire up_wr_s;
wire up_ack_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_tpm_oos_s;
wire vdma_be_error_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// processor write interface (see regmap.txt for details)
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_crcb_init <= 'd0;
up_full_range <= 'd0;
up_tpg_enable <= 'd0;
up_csc_bypass <= 'd0;
up_enable <= 'd0;
up_hs_width <= 'd0;
up_hs_count <= 'd0;
up_vs_width <= 'd0;
up_vs_count <= 'd0;
up_hdmi_tpm_oos_hold <= 'd0;
up_vdma_tpm_oos_hold <= 'd0;
up_vdma_be_error_hold <= 'd0;
up_vdma_ovf_hold <= 'd0;
up_vdma_unf_hold <= 'd0;
up_cp_en <= 'd0;
up_cp <= 'd0;
up_status <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_crcb_init <= up_wdata[4];
up_full_range <= up_wdata[3];
up_tpg_enable <= up_wdata[2];
up_csc_bypass <= up_wdata[1];
up_enable <= up_wdata[0];
end
if ((up_addr == 5'h02) && (up_wr_s == 1'b1)) begin
up_hs_width <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0];
end
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_vs_width <= up_wdata[31:16];
up_vs_count <= up_wdata[15:0];
end
if (up_hdmi_tpm_oos == 1'b1) begin
up_hdmi_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_hdmi_tpm_oos_hold <= up_hdmi_tpm_oos_hold & (~up_wdata[4]);
end
if (up_vdma_tpm_oos == 1'b1) begin
up_vdma_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_vdma_tpm_oos_hold <= up_vdma_tpm_oos_hold & (~up_wdata[3]);
end
if (up_vdma_be_error == 1'b1) begin
up_vdma_be_error_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_vdma_be_error_hold <= up_vdma_be_error_hold & (~up_wdata[2]);
end
if (up_vdma_ovf == 1'b1) begin
up_vdma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_vdma_ovf_hold <= up_vdma_ovf_hold & (~up_wdata[1]);
end
if (up_vdma_unf == 1'b1) begin
up_vdma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_vdma_unf_hold <= up_vdma_unf_hold & (~up_wdata[0]);
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_cp_en <= up_wdata[24];
up_cp <= up_wdata[23:0];
end
up_status <= {up_enable, up_vdma_be_error_hold, (up_hdmi_tpm_oos_hold | up_vdma_tpm_oos_hold),
(up_vdma_ovf_hold | up_vdma_unf_hold)};
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {27'd0, up_crcb_init, up_full_range, up_tpg_enable,
up_csc_bypass, up_enable};
5'h02: up_rdata <= {up_hs_width, up_hs_count};
5'h03: up_rdata <= {up_vs_width, up_vs_count};
5'h04: up_rdata <= {27'd0, up_hdmi_tpm_oos_hold, up_vdma_tpm_oos_hold,
up_vdma_be_error_hold, up_vdma_ovf_hold, up_vdma_unf_hold};
5'h05: up_rdata <= {7'd0, up_cp_en, up_cp};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// the hdmi status signals transferred to the processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_hdmi_tpm_oos_m1 <= 'd0;
up_vdma_tpm_oos_m1 <= 'd0;
up_vdma_be_error_m1 <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_hdmi_tpm_oos <= 'd0;
up_vdma_tpm_oos <= 'd0;
up_vdma_be_error <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf <= 'd0;
end else begin
up_hdmi_tpm_oos_m1 <= hdmi_tpm_oos_s;
up_vdma_tpm_oos_m1 <= vdma_tpm_oos_s;
up_vdma_be_error_m1 <= vdma_be_error_s;
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_unf_m1 <= vdma_unf_s;
up_hdmi_tpm_oos <= up_hdmi_tpm_oos_m1;
up_vdma_tpm_oos <= up_vdma_tpm_oos_m1;
up_vdma_be_error <= up_vdma_be_error_m1;
up_vdma_ovf <= up_vdma_ovf_m1;
up_vdma_unf <= up_vdma_unf_m1;
end
end
// vdma interface
cf_v2h_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_be (vdma_be),
.vdma_data (vdma_data),
.vdma_last (vdma_last),
.vdma_ready (vdma_ready),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_be_error (vdma_be_error_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.debug_data (vdma_dbg_data),
.debug_trigger (vdma_dbg_trigger));
// hdmi interface
cf_v2h_hdmi i_hdmi (
.hdmi_clk (hdmi_clk),
.hdmi_data (hdmi_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.up_enable (up_enable),
.up_crcb_init (up_crcb_init),
.up_full_range (up_full_range),
.up_tpg_enable (up_tpg_enable),
.up_csc_bypass (up_csc_bypass),
.up_hs_width (up_hs_width),
.up_hs_count (up_hs_count),
.up_vs_width (up_vs_width),
.up_vs_count (up_vs_count),
.up_cp_en (up_cp_en),
.up_cp (up_cp),
.debug_data (hdmi_dbg_data),
.debug_trigger (hdmi_dbg_trigger));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
/*
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy
*
* NOTE: Add Pullups to all the signals, this will tell the host we are
* an SD Device, not a SPI Device
* Description: SDIO Stack
* Manages the entire SDIO communication flow, in the end users should
* Write into the stack and it should arrive on the other side.
*
* Data Link Layer:
* Sends and receive commands and responses from the physical layer.
* Manages all register read and writes that will be used to configure
* the entire stack.
*
* Phy Layer:
* Sends and receives streams of bits with the host and manages CRC
* generation and analysis. The bottom part of this layer is connected
* to the physical pins of the FPGA and the top is connected to the data
* link layer
*
* Changes:
* 2015.08.09: Inital Commit
*/
module sdio_device_stack (
input sdio_clk,
input sdio_clk_x2,
input rst,
output o_mem_en,
//Function Configuration
output [7:0] o_func_enable, //Bitmask Function Enable
input [7:0] i_func_ready, //Bitmask Function is Ready
output [2:0] o_func_abort_stb,
input [7:0] i_func_exec_status,
input [7:0] i_func_ready_for_data,
// Function Interface From CIA
output o_fbr1_csa_en,
output [3:0] o_fbr1_pwr_mode,
output [15:0] o_fbr1_block_size,
output o_fbr2_csa_en,
output [3:0] o_fbr2_pwr_mode,
output [15:0] o_fbr2_block_size,
output o_fbr3_csa_en,
output [3:0] o_fbr3_pwr_mode,
output [15:0] o_fbr3_block_size,
output o_fbr4_csa_en,
output [3:0] o_fbr4_pwr_mode,
output [15:0] o_fbr4_block_size,
output o_fbr5_csa_en,
output [3:0] o_fbr5_pwr_mode,
output [15:0] o_fbr5_block_size,
output o_fbr6_csa_en,
output [3:0] o_fbr6_pwr_mode,
output [15:0] o_fbr6_block_size,
output o_fbr7_csa_en,
output [3:0] o_fbr7_pwr_mode,
output [15:0] o_fbr7_block_size,
//Function 1 Interface
output o_func1_wr_stb,
output [7:0] o_func1_wr_data,
input i_func1_rd_stb,
input [7:0] i_func1_rd_data,
output o_func1_hst_rdy,
input i_func1_com_rdy,
output o_func1_activate,
//Function 2 Interface
output o_func2_wr_stb,
output [7:0] o_func2_wr_data,
input i_func2_rd_stb,
input [7:0] i_func2_rd_data,
output o_func2_hst_rdy,
input i_func2_com_rdy,
output o_func2_activate,
//Function 3 Interface
output o_func3_wr_stb,
output [7:0] o_func3_wr_data,
input i_func3_rd_stb,
input [7:0] i_func3_rd_data,
output o_func3_hst_rdy,
input i_func3_com_rdy,
output o_func3_activate,
//Function 4 Interface
output o_func4_wr_stb,
output [7:0] o_func4_wr_data,
input i_func4_rd_stb,
input [7:0] i_func4_rd_data,
output o_func4_hst_rdy,
input i_func4_com_rdy,
output o_func4_activate,
//Function 5 Interface
output o_func5_wr_stb,
output [7:0] o_func5_wr_data,
input i_func5_rd_stb,
input [7:0] i_func5_rd_data,
output o_func5_hst_rdy,
input i_func5_com_rdy,
output o_func5_activate,
//Function 6 Interface
output o_func6_wr_stb,
output [7:0] o_func6_wr_data,
input i_func6_rd_stb,
input [7:0] i_func6_rd_data,
output o_func6_hst_rdy,
input i_func6_com_rdy,
output o_func6_activate,
//Function 7 Interface
output o_func7_wr_stb,
output [7:0] o_func7_wr_data,
input i_func7_rd_stb,
input [7:0] i_func7_rd_data,
output o_func7_hst_rdy,
input i_func7_com_rdy,
output o_func7_activate,
//Memory Interface
output o_mem_wr_stb,
output [7:0] o_mem_wr_data,
input i_mem_rd_stb,
input [7:0] i_mem_rd_data,
output o_mem_hst_rdy,
input i_mem_com_rdy,
output o_mem_activate,
//Broadcast Values that go to all Functions/Memory
output o_func_write_flag,
output o_func_block_mode,
output [3:0] o_func_num,
output o_func_rd_after_wr,
output o_func_inc_addr,
output [17:0] o_func_addr,
output [12:0] o_func_data_count,
input [7:0] i_interrupt,
//Platform Spectific posedge strobe
input i_phy_posedge_stb,
//FPGA Interface
output o_sd_cmd_dir,
input i_sd_cmd_in,
output o_sd_cmd_out,
output o_sd_data_dir,
output [7:0] o_sd_data_out,
input [7:0] i_sd_data_in
);
//local parameters
//registes/wires
wire [3:0] sdio_state;
wire sdio_cmd_in;
wire sdio_cmd_out;
wire sdio_cmd_dir;
wire [3:0] sdio_data_in;
wire [3:0] sdio_data_out;
wire sdio_data_dir;
//Phy Configuration
wire spi_phy;
wire sd1_phy;
wire sd4_phy;
//Phy Interface
wire cmd_phy_idle;
wire cmd_stb;
wire cmd_crc_stb;
wire [5:0] cmd;
wire [31:0] cmd_arg;
wire [17:0] cmd_addr;
wire [12:0] cmd_data_cnt;
wire [39:0] rsps;
wire [7:0] rsps_len;
wire rsps_fail;
wire rsps_idle;
wire interrupt;
wire chip_select_n;
//Function Level
wire cmd_bus_sel;
wire tunning_block;
wire soft_reset;
//SDIO Configuration Flags
wire en_card_detect_n;
wire en_4bit_block_int;
wire bus_release_req_stb;
wire [15:0] f0_block_size;
wire cfg_1_bit_mode;
wire cfg_4_bit_mode;
wire cfg_8_bit_mode;
wire sdr_12;
wire sdr_25;
wire sdr_50;
wire ddr_50;
wire sdr_104;
wire driver_type_a;
wire driver_type_b;
wire driver_type_c;
wire driver_type_d;
wire enable_async_interrupt;
wire [7:0] i_func_ready;
wire [7:0] func_int_enable;
wire [7:0] func_int_pending;
wire data_bus_busy;
wire data_read_avail;
wire [7:0] cmd_func_write_data;
wire [7:0] cmd_func_read_data;
wire cmd_func_data_rdy;
wire cmd_func_host_rdy;
wire [17:0] cmd_func_data_count;
wire cmd_func_activate;
wire cmd_func_finished;
wire data_phy_activate;
wire data_phy_finished;
wire data_phy_wr_stb;
wire [7:0] data_phy_wr_data;
wire data_phy_rd_stb;
wire [7:0] data_phy_rd_data;
wire data_phy_hst_rdy;
wire data_phy_com_rdy;
wire cia_wr_stb;
wire [7:0] cia_wr_data;
wire cia_rd_stb;
wire [7:0] cia_rd_data;
wire cia_hst_rdy;
wire cia_com_rdy;
wire cia_activate;
wire cia_finished;
//Submodules
sdio_card_control card_controller (
.sdio_clk (sdio_clk ),/* Run from the SDIO Clock */
.rst (rst ),
.i_soft_reset (i_soft_reset ),
.i_func_interrupt (i_interrupt ),
.i_func_interrupt_en (func_int_enable ),
.o_interrupt (interrupt ),
.o_mem_en (o_mem_en ),
.o_func_num (o_func_num ),/* CMD -> FUNC: Function Number to activate */
.o_func_inc_addr (o_func_inc_addr ),/* CMD -> FUNC: Inc address after every read/write */
.o_func_block_mode (o_func_block_mode ),/* CMD -> FUNC: This is a block level transfer, not byte */
.o_func_write_flag (o_func_write_flag ),/* CMD -> FUNC: We are writing */
.o_func_rd_after_wr (o_func_rd_after_wr ),/* CMD -> FUNC: Read the value after a write */
.o_func_addr (cmd_addr ),/* CMD -> FUNC: Address we are talking to */
.o_func_data_count (cmd_data_cnt ),/* CMD -> FUNC: number of data bytes/blocks to read/write */
//Command Data Bus
.o_cmd_bus_sel (cmd_bus_sel ),/* CMD -> FUNC: Indicate that data will be on command bus */
.o_func_activate (cmd_func_activate ),/* CMD -> FUNC: Start a function layer transaction */
.i_func_finished (cmd_func_finished ),/* FUNC -> CMD: Function has finished */
.o_func_write_data (cmd_func_write_data ),/* CMD -> FUNC: Data to Write */
.i_func_read_data (cmd_func_read_data ),/* FUNC -> CMD: Read Data */
.o_tunning_block (tunning_block ),
.i_cmd_phy_idle (cmd_phy_idle ),/* PHY -> CMD: Command portion of phy layer is IDLE */
.i_cmd_stb (cmd_stb ),/* PHY -> CMD: Command signal strobe */
.i_cmd_crc_good_stb (cmd_crc_good_stb ),/* PHY -> CMD: CRC is good */
.i_cmd (cmd ),/* PHY -> CMD: Command */
.i_cmd_arg (cmd_arg ),/* PHY -> CMD: Command Arg */
.i_chip_select_n (chip_select_n ),/* Chip Select used to determine if this is a SPI host */
.o_rsps (rsps ),/* Response Generated by this layer*/
.o_rsps_len (rsps_len ),/* Length of response*/
.o_rsps_stb (rsps_stb ),
.o_rsps_fail (rsps_fail ),
.i_rsps_idle (rsps_idle )
);
sdio_data_control data_bus_interconnect(
.clk (sdio_clk ),
.rst (rst ),
.o_data_bus_busy (data_bus_busy ),
.o_data_read_avail (data_read_avail ),
.i_write_flg (o_func_write_flag ), /* CMD -> *: We are writing */
.i_block_mode_flg (o_func_block_mode ), /* CMD -> DATA CNTRL: this is a block mode transfer */
.i_data_cnt (cmd_data_cnt ),
.o_total_data_cnt (o_func_data_count ),
.i_inc_addr_flg (o_func_inc_addr ),
.i_cmd_address (cmd_addr ),
.o_address (o_func_addr ),
.i_activate (cmd_func_activate ), /* CMD -> DATA CNTRL: Activate transaction */
.o_finished (cmd_func_finished ), /* DATA CNTRL -> CMD: Finished with transaction */
.i_cmd_bus_sel (cmd_bus_sel ), /* If this is high we can only read/write one byte */
.i_mem_sel (o_mem_en ), /* When high this selects the memory */
.i_func_sel (o_func_num ), /* Select the function number */
//Command Bus Interface
.i_cmd_wr_data (cmd_func_write_data ), /* CMD -> FUNC: Write Data */
.o_cmd_rd_data (cmd_func_read_data ), /* FUNC -> CMD: Data from func to host */
//Phy Data Bus Inteface
.i_data_phy_wr_stb (data_phy_wr_stb ),
.i_data_phy_wr_data (data_phy_wr_data ),
.o_data_phy_rd_stb (data_phy_rd_stb ),
.o_data_phy_rd_data (data_phy_rd_data ),
.i_data_phy_hst_rdy (data_phy_hst_rdy ), /* DATA PHY -> Func: Ready for receive data */
.o_data_phy_com_rdy (data_phy_com_rdy ),
.o_data_phy_activate (data_phy_activate ), /* DATA CNTRL -> DATA PHY: tell the phy that it should be ready */
.i_data_phy_finished (data_phy_finished ),
//CIA Interface
.o_cia_wr_stb (cia_wr_stb ),
.o_cia_wr_data (cia_wr_data ),
.i_cia_rd_stb (cia_rd_stb ),
.i_cia_rd_data (cia_rd_data ),
.o_cia_hst_rdy (cia_hst_rdy ),
.i_cia_com_rdy (cia_com_rdy ),
.o_cia_activate (cia_activate ),
.i_cia_block_size (f0_block_size ),
//Function Interface
.o_func1_wr_stb (o_func1_wr_stb ),
.o_func1_wr_data (o_func1_wr_data ),
.i_func1_rd_stb (i_func1_rd_stb ),
.i_func1_rd_data (i_func1_rd_data ),
.o_func1_hst_rdy (o_func1_hst_rdy ),
.i_func1_com_rdy (i_func1_com_rdy ),
.o_func1_activate (o_func1_activate ),
.i_func1_block_size (o_fbr1_block_size ),
//Function Interface
.o_func2_wr_stb (o_func2_wr_stb ),
.o_func2_wr_data (o_func2_wr_data ),
.i_func2_rd_stb (i_func2_rd_stb ),
.i_func2_rd_data (i_func2_rd_data ),
.o_func2_hst_rdy (o_func2_hst_rdy ),
.i_func2_com_rdy (i_func2_com_rdy ),
.o_func2_activate (o_func2_activate ),
.i_func2_block_size (o_fbr2_block_size ),
//Function Interface
.o_func3_wr_stb (o_func3_wr_stb ),
.o_func3_wr_data (o_func3_wr_data ),
.i_func3_rd_stb (i_func3_rd_stb ),
.i_func3_rd_data (i_func3_rd_data ),
.o_func3_hst_rdy (o_func3_hst_rdy ),
.i_func3_com_rdy (i_func3_com_rdy ),
.o_func3_activate (o_func3_activate ),
.i_func3_block_size (o_fbr3_block_size ),
//Function Interface
.o_func4_wr_stb (o_func4_wr_stb ),
.o_func4_wr_data (o_func4_wr_data ),
.i_func4_rd_stb (i_func4_rd_stb ),
.i_func4_rd_data (i_func4_rd_data ),
.o_func4_hst_rdy (o_func4_hst_rdy ),
.i_func4_com_rdy (i_func4_com_rdy ),
.o_func4_activate (o_func4_activate ),
.i_func4_block_size (o_fbr4_block_size ),
//Function Interface
.o_func5_wr_stb (o_func5_wr_stb ),
.o_func5_wr_data (o_func5_wr_data ),
.i_func5_rd_stb (i_func5_rd_stb ),
.i_func5_rd_data (i_func5_rd_data ),
.o_func5_hst_rdy (o_func5_hst_rdy ),
.i_func5_com_rdy (i_func5_com_rdy ),
.o_func5_activate (o_func5_activate ),
.i_func5_block_size (o_fbr5_block_size ),
//Function Interface
.o_func6_wr_stb (o_func6_wr_stb ),
.o_func6_wr_data (o_func6_wr_data ),
.i_func6_rd_stb (i_func6_rd_stb ),
.i_func6_rd_data (i_func6_rd_data ),
.o_func6_hst_rdy (o_func6_hst_rdy ),
.i_func6_com_rdy (i_func6_com_rdy ),
.o_func6_activate (o_func6_activate ),
.i_func6_block_size (o_fbr6_block_size ),
//Function Interface
.o_func7_wr_stb (o_func7_wr_stb ),
.o_func7_wr_data (o_func7_wr_data ),
.i_func7_rd_stb (i_func7_rd_stb ),
.i_func7_rd_data (i_func7_rd_data ),
.o_func7_hst_rdy (o_func7_hst_rdy ),
.i_func7_com_rdy (i_func7_com_rdy ),
.o_func7_activate (o_func7_activate ),
.i_func7_block_size (o_fbr7_block_size ),
//Memory Interface
.o_mem_wr_stb (o_mem_wr_stb ),
.o_mem_wr_data (o_mem_wr_data ),
.i_mem_rd_stb (i_mem_rd_stb ),
.i_mem_rd_data (i_mem_rd_data ),
.o_mem_hst_rdy (o_mem_hst_rdy ),
.i_mem_com_rdy (i_mem_com_rdy ),
.o_mem_activate (o_mem_activate ),
.i_mem_block_size (16'h0000 )
);
sdio_cia cia (
.clk (sdio_clk ),
.rst (rst ),
.i_write_flag (o_func_write_flag ),
.i_address (o_func_addr ),
.i_inc_addr (o_func_inc_addr ),
.i_data_count (o_func_data_count ),
//SDIO Data Interface
.i_activate (cia_activate ),
.o_finished (cia_finished ),
.i_ready (cia_hst_rdy ),
.i_data_stb (cia_wr_stb ),
.i_data_in (cia_wr_data ),
.o_ready (cia_com_rdy ),
.o_data_out (cia_rd_data ),
.o_data_stb (cia_rd_stb ),
//FBR Interface
.o_fbr1_csa_en (o_fbr1_csa_en ),
.o_fbr1_pwr_mode (o_fbr1_pwr_mode ),
.o_fbr1_block_size (o_fbr1_block_size ),
.o_fbr2_csa_en (o_fbr2_csa_en ),
.o_fbr2_pwr_mode (o_fbr2_pwr_mode ),
.o_fbr2_block_size (o_fbr2_block_size ),
.o_fbr3_csa_en (o_fbr3_csa_en ),
.o_fbr3_pwr_mode (o_fbr3_pwr_mode ),
.o_fbr3_block_size (o_fbr3_block_size ),
.o_fbr4_csa_en (o_fbr4_csa_en ),
.o_fbr4_pwr_mode (o_fbr4_pwr_mode ),
.o_fbr4_block_size (o_fbr4_block_size ),
.o_fbr5_csa_en (o_fbr5_csa_en ),
.o_fbr5_pwr_mode (o_fbr5_pwr_mode ),
.o_fbr5_block_size (o_fbr5_block_size ),
.o_fbr6_csa_en (o_fbr6_csa_en ),
.o_fbr6_pwr_mode (o_fbr6_pwr_mode ),
.o_fbr6_block_size (o_fbr6_block_size ),
.o_fbr7_csa_en (o_fbr7_csa_en ),
.o_fbr7_pwr_mode (o_fbr7_pwr_mode ),
.o_fbr7_block_size (o_fbr7_block_size ),
//Function Configuration Interface
.o_func_enable (o_func_enable ),
.i_func_ready (i_func_ready ),
.o_func_int_enable (func_int_enable ),
.i_func_int_pending (func_int_pending ),
.i_func_ready_for_data (i_func_ready_for_data ),
.o_func_abort_stb (o_func_abort_stb ),
// .o_func_select (o_func_select ), //XXX: Track this down!
.i_func_exec_status (i_func_exec_status ),
.i_data_bus_busy (data_bus_busy ),
//SDCard Configuration Interface
.o_en_card_detect_n (en_card_detect_n ),
.o_en_4bit_block_int (en_4bit_block_int ),
.o_bus_release_req_stb (bus_release_req_stb ),
.o_soft_reset (soft_reset ),
.i_data_read_avail (data_read_avail ),
.o_f0_block_size (f0_block_size ),
.o_1_bit_mode (cfg_1_bit_mode ),
.o_4_bit_mode (cfg_4_bit_mode ),
.o_8_bit_mode (cfg_8_bit_mode ),
.o_sdr_12 (sdr_12 ),
.o_sdr_25 (sdr_25 ),
.o_sdr_50 (sdr_50 ),
.o_ddr_50 (ddr_50 ),
.o_sdr_104 (sdr_104 ),
.o_driver_type_a (driver_type_a ),
.o_driver_type_b (driver_type_b ),
.o_driver_type_c (driver_type_c ),
.o_driver_type_d (driver_type_d ),
.o_enable_async_interrupt (enable_async_interrupt )
);
sdio_device_phy phy(
.rst (rst ),
.i_posedge_stb (i_phy_posedge_stb ),
//Configuration
.i_spi_phy (spi_phy ),/* Flag: SPI PHY (not supported now) */
.i_sd1_phy (sd1_phy ),/* Flag: SD PHY with one data lane */
.i_sd4_phy (sd4_phy ),/* Flag: SD PHY with four data lanes */
.o_cmd_phy_idle (cmd_phy_idle ),/* PHY -> CMD: Command portion of phy layer is IDLE */
//Command Interface
.o_cmd_stb (cmd_stb ),/* PHY -> CMD: Command signal strobe */
.o_cmd_crc_good_stb (cmd_crc_good_stb ),/* PHY -> CMD: CRC is good */
.o_cmd (cmd ),/* PHY -> CMD: Command */
.o_cmd_arg (cmd_arg ),/* PHY -> CMD: Command Arg */
.i_rsps_stb (rsps_stb ),/* CMD -> PHY: Response initiate */
.i_rsps (rsps ),/* CMD -> PHY: Response Value */
.i_rsps_len (rsps_len ),/* CMD -> PHY: Response Length */
.i_rsps_fail (rsps_fail ),/* CMD -> PHY: Response Failed */
.o_rsps_idle (rsps_idle ),/* PHY -> CMD: Response is IDLE */
.i_interrupt (interrupt ),/* Interrupt */
.i_data_count (o_func_data_count ),/* CMD -> PHY: Number of bytes to read/write */
//Data Interface
.i_data_activate (data_phy_activate ),
.o_data_finished (data_phy_finished ),
.i_write_flag (o_func_write_flag ),
.o_data_wr_stb (data_phy_wr_stb ),
.o_data_wr_data (data_phy_wr_data ),
.i_data_rd_stb (data_phy_rd_stb ),
.i_data_rd_data (data_phy_rd_data ),
.o_data_hst_rdy (data_phy_hst_rdy ),
.i_data_com_rdy (data_phy_com_rdy ),
//FPGA Interface
.i_sdio_clk (sdio_clk ),
.i_sdio_clk_x2 (sdio_clk_x2 ),
.o_sdio_cmd_dir (o_sd_cmd_dir ),
.i_sdio_cmd_in (i_sd_cmd_in ),
.o_sdio_cmd_out (o_sd_cmd_out ),
.o_sdio_data_dir (o_sd_data_dir ),
.i_sdio_data_in (i_sd_data_in ),
.o_sdio_data_out (o_sd_data_out )
);
//asynchronous logic
/*
assign sdio_cmd = sdio_cmd_dir ? sdio_cmd_out : sdio_cmd_in;
assign sdio_data = sdio_data_dir ? sdio_data_out : sdio_data_in;
assign chip_select_n = sdio_data[3];
*/
assign func_int_pending = i_interrupt;
//synchronous logic
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module logicblock_add(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign o_dataout = dataa + datab;
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
// nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0 (
input wire avl_clk_out_clk_clk, // avl_clk_out_clk.clk
input wire cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset
input wire [19:0] cpu_inst_data_master_address, // cpu_inst_data_master.address
output wire cpu_inst_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_inst_data_master_byteenable, // .byteenable
input wire cpu_inst_data_master_read, // .read
output wire [31:0] cpu_inst_data_master_readdata, // .readdata
input wire cpu_inst_data_master_write, // .write
input wire [31:0] cpu_inst_data_master_writedata, // .writedata
input wire [16:0] cpu_inst_instruction_master_address, // cpu_inst_instruction_master.address
output wire cpu_inst_instruction_master_waitrequest, // .waitrequest
input wire cpu_inst_instruction_master_read, // .read
output wire [31:0] cpu_inst_instruction_master_readdata, // .readdata
output wire [12:0] sequencer_data_mgr_inst_avl_address, // sequencer_data_mgr_inst_avl.address
output wire sequencer_data_mgr_inst_avl_write, // .write
output wire sequencer_data_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_data_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_data_mgr_inst_avl_writedata, // .writedata
input wire sequencer_data_mgr_inst_avl_waitrequest, // .waitrequest
output wire [11:0] sequencer_mem_s1_address, // sequencer_mem_s1.address
output wire sequencer_mem_s1_write, // .write
input wire [31:0] sequencer_mem_s1_readdata, // .readdata
output wire [31:0] sequencer_mem_s1_writedata, // .writedata
output wire [3:0] sequencer_mem_s1_byteenable, // .byteenable
output wire sequencer_mem_s1_chipselect, // .chipselect
output wire [12:0] sequencer_phy_mgr_inst_avl_address, // sequencer_phy_mgr_inst_avl.address
output wire sequencer_phy_mgr_inst_avl_write, // .write
output wire sequencer_phy_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_phy_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_phy_mgr_inst_avl_writedata, // .writedata
input wire sequencer_phy_mgr_inst_avl_waitrequest, // .waitrequest
output wire [3:0] sequencer_reg_file_inst_avl_address, // sequencer_reg_file_inst_avl.address
output wire sequencer_reg_file_inst_avl_write, // .write
output wire sequencer_reg_file_inst_avl_read, // .read
input wire [31:0] sequencer_reg_file_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_reg_file_inst_avl_writedata, // .writedata
output wire [3:0] sequencer_reg_file_inst_avl_byteenable, // .byteenable
input wire sequencer_reg_file_inst_avl_waitrequest, // .waitrequest
output wire [12:0] sequencer_rw_mgr_inst_avl_address, // sequencer_rw_mgr_inst_avl.address
output wire sequencer_rw_mgr_inst_avl_write, // .write
output wire sequencer_rw_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_rw_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_rw_mgr_inst_avl_writedata, // .writedata
input wire sequencer_rw_mgr_inst_avl_waitrequest, // .waitrequest
output wire [12:0] sequencer_scc_mgr_inst_avl_address, // sequencer_scc_mgr_inst_avl.address
output wire sequencer_scc_mgr_inst_avl_write, // .write
output wire sequencer_scc_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_scc_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_scc_mgr_inst_avl_writedata, // .writedata
input wire sequencer_scc_mgr_inst_avl_waitrequest // .waitrequest
);
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
wire [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
wire [95:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_agent:av_debugaccess
wire [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_agent:av_read
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_agent:av_write
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_agent:av_writedata
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_inst_instruction_master_agent:rp_valid
wire [95:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_inst_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // cpu_inst_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_inst_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_inst_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_inst_instruction_master_agent:rp_endofpacket
wire [31:0] sequencer_phy_mgr_inst_avl_agent_m0_readdata; // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_agent:m0_readdata
wire sequencer_phy_mgr_inst_avl_agent_m0_waitrequest; // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_phy_mgr_inst_avl_agent_m0_debugaccess; // sequencer_phy_mgr_inst_avl_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
wire [19:0] sequencer_phy_mgr_inst_avl_agent_m0_address; // sequencer_phy_mgr_inst_avl_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_phy_mgr_inst_avl_agent_m0_byteenable; // sequencer_phy_mgr_inst_avl_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
wire sequencer_phy_mgr_inst_avl_agent_m0_read; // sequencer_phy_mgr_inst_avl_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
wire sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_phy_mgr_inst_avl_agent_m0_lock; // sequencer_phy_mgr_inst_avl_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_phy_mgr_inst_avl_agent_m0_writedata; // sequencer_phy_mgr_inst_avl_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
wire sequencer_phy_mgr_inst_avl_agent_m0_write; // sequencer_phy_mgr_inst_avl_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_phy_mgr_inst_avl_agent_m0_burstcount; // sequencer_phy_mgr_inst_avl_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
wire sequencer_phy_mgr_inst_avl_agent_rf_source_valid; // sequencer_phy_mgr_inst_avl_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [96:0] sequencer_phy_mgr_inst_avl_agent_rf_source_data; // sequencer_phy_mgr_inst_avl_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_phy_mgr_inst_avl_agent_rf_source_ready; // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_agent:rf_source_ready
wire sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_phy_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_phy_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_agent:rf_sink_valid
wire [96:0] sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_agent:rf_sink_data
wire sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_phy_mgr_inst_avl_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> sequencer_phy_mgr_inst_avl_agent:cp_valid
wire [95:0] cmd_mux_src_data; // cmd_mux:src_data -> sequencer_phy_mgr_inst_avl_agent:cp_data
wire cmd_mux_src_ready; // sequencer_phy_mgr_inst_avl_agent:cp_ready -> cmd_mux:src_ready
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> sequencer_phy_mgr_inst_avl_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_data_mgr_inst_avl_agent_m0_readdata; // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_agent:m0_readdata
wire sequencer_data_mgr_inst_avl_agent_m0_waitrequest; // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_data_mgr_inst_avl_agent_m0_debugaccess; // sequencer_data_mgr_inst_avl_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
wire [19:0] sequencer_data_mgr_inst_avl_agent_m0_address; // sequencer_data_mgr_inst_avl_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_data_mgr_inst_avl_agent_m0_byteenable; // sequencer_data_mgr_inst_avl_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
wire sequencer_data_mgr_inst_avl_agent_m0_read; // sequencer_data_mgr_inst_avl_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
wire sequencer_data_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_data_mgr_inst_avl_agent_m0_lock; // sequencer_data_mgr_inst_avl_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_data_mgr_inst_avl_agent_m0_writedata; // sequencer_data_mgr_inst_avl_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
wire sequencer_data_mgr_inst_avl_agent_m0_write; // sequencer_data_mgr_inst_avl_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_data_mgr_inst_avl_agent_m0_burstcount; // sequencer_data_mgr_inst_avl_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
wire sequencer_data_mgr_inst_avl_agent_rf_source_valid; // sequencer_data_mgr_inst_avl_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [96:0] sequencer_data_mgr_inst_avl_agent_rf_source_data; // sequencer_data_mgr_inst_avl_agent:rf_source_data -> sequencer_data_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_data_mgr_inst_avl_agent_rf_source_ready; // sequencer_data_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_agent:rf_source_ready
wire sequencer_data_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_data_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_data_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_data_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_data_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_agent:rf_sink_valid
wire [96:0] sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_data_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_agent:rf_sink_data
wire sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_data_mgr_inst_avl_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_data_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sequencer_data_mgr_inst_avl_agent:cp_valid
wire [95:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sequencer_data_mgr_inst_avl_agent:cp_data
wire cmd_mux_001_src_ready; // sequencer_data_mgr_inst_avl_agent:cp_ready -> cmd_mux_001:src_ready
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sequencer_data_mgr_inst_avl_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sequencer_data_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sequencer_data_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_rw_mgr_inst_avl_agent_m0_readdata; // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_agent:m0_readdata
wire sequencer_rw_mgr_inst_avl_agent_m0_waitrequest; // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_rw_mgr_inst_avl_agent_m0_debugaccess; // sequencer_rw_mgr_inst_avl_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
wire [19:0] sequencer_rw_mgr_inst_avl_agent_m0_address; // sequencer_rw_mgr_inst_avl_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_rw_mgr_inst_avl_agent_m0_byteenable; // sequencer_rw_mgr_inst_avl_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
wire sequencer_rw_mgr_inst_avl_agent_m0_read; // sequencer_rw_mgr_inst_avl_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
wire sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_rw_mgr_inst_avl_agent_m0_lock; // sequencer_rw_mgr_inst_avl_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_rw_mgr_inst_avl_agent_m0_writedata; // sequencer_rw_mgr_inst_avl_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
wire sequencer_rw_mgr_inst_avl_agent_m0_write; // sequencer_rw_mgr_inst_avl_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_rw_mgr_inst_avl_agent_m0_burstcount; // sequencer_rw_mgr_inst_avl_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
wire sequencer_rw_mgr_inst_avl_agent_rf_source_valid; // sequencer_rw_mgr_inst_avl_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [96:0] sequencer_rw_mgr_inst_avl_agent_rf_source_data; // sequencer_rw_mgr_inst_avl_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_rw_mgr_inst_avl_agent_rf_source_ready; // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_agent:rf_source_ready
wire sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_rw_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_rw_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_agent:rf_sink_valid
wire [96:0] sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_agent:rf_sink_data
wire sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_rw_mgr_inst_avl_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sequencer_rw_mgr_inst_avl_agent:cp_valid
wire [95:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sequencer_rw_mgr_inst_avl_agent:cp_data
wire cmd_mux_002_src_ready; // sequencer_rw_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sequencer_rw_mgr_inst_avl_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_mem_s1_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_agent:m0_readdata
wire sequencer_mem_s1_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_agent:m0_waitrequest
wire sequencer_mem_s1_agent_m0_debugaccess; // sequencer_mem_s1_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
wire [19:0] sequencer_mem_s1_agent_m0_address; // sequencer_mem_s1_agent:m0_address -> sequencer_mem_s1_translator:uav_address
wire [3:0] sequencer_mem_s1_agent_m0_byteenable; // sequencer_mem_s1_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
wire sequencer_mem_s1_agent_m0_read; // sequencer_mem_s1_agent:m0_read -> sequencer_mem_s1_translator:uav_read
wire sequencer_mem_s1_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_agent:m0_readdatavalid
wire sequencer_mem_s1_agent_m0_lock; // sequencer_mem_s1_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
wire [31:0] sequencer_mem_s1_agent_m0_writedata; // sequencer_mem_s1_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
wire sequencer_mem_s1_agent_m0_write; // sequencer_mem_s1_agent:m0_write -> sequencer_mem_s1_translator:uav_write
wire [2:0] sequencer_mem_s1_agent_m0_burstcount; // sequencer_mem_s1_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
wire sequencer_mem_s1_agent_rf_source_valid; // sequencer_mem_s1_agent:rf_source_valid -> sequencer_mem_s1_agent_rsp_fifo:in_valid
wire [96:0] sequencer_mem_s1_agent_rf_source_data; // sequencer_mem_s1_agent:rf_source_data -> sequencer_mem_s1_agent_rsp_fifo:in_data
wire sequencer_mem_s1_agent_rf_source_ready; // sequencer_mem_s1_agent_rsp_fifo:in_ready -> sequencer_mem_s1_agent:rf_source_ready
wire sequencer_mem_s1_agent_rf_source_startofpacket; // sequencer_mem_s1_agent:rf_source_startofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_startofpacket
wire sequencer_mem_s1_agent_rf_source_endofpacket; // sequencer_mem_s1_agent:rf_source_endofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_endofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_valid; // sequencer_mem_s1_agent_rsp_fifo:out_valid -> sequencer_mem_s1_agent:rf_sink_valid
wire [96:0] sequencer_mem_s1_agent_rsp_fifo_out_data; // sequencer_mem_s1_agent_rsp_fifo:out_data -> sequencer_mem_s1_agent:rf_sink_data
wire sequencer_mem_s1_agent_rsp_fifo_out_ready; // sequencer_mem_s1_agent:rf_sink_ready -> sequencer_mem_s1_agent_rsp_fifo:out_ready
wire sequencer_mem_s1_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_agent:rf_sink_startofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sequencer_mem_s1_agent:cp_valid
wire [95:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sequencer_mem_s1_agent:cp_data
wire cmd_mux_003_src_ready; // sequencer_mem_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sequencer_mem_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sequencer_mem_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sequencer_mem_s1_agent:cp_endofpacket
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_scc_mgr_inst_avl_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [19:0] sequencer_scc_mgr_inst_avl_agent_m0_address; // sequencer_scc_mgr_inst_avl_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_scc_mgr_inst_avl_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_agent_m0_read; // sequencer_scc_mgr_inst_avl_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_agent_m0_lock; // sequencer_scc_mgr_inst_avl_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire sequencer_scc_mgr_inst_avl_agent_m0_write; // sequencer_scc_mgr_inst_avl_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_scc_mgr_inst_avl_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire sequencer_scc_mgr_inst_avl_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [96:0] sequencer_scc_mgr_inst_avl_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_agent:rf_sink_valid
wire [96:0] sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> sequencer_scc_mgr_inst_avl_agent:cp_valid
wire [95:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> sequencer_scc_mgr_inst_avl_agent:cp_data
wire cmd_mux_004_src_ready; // sequencer_scc_mgr_inst_avl_agent:cp_ready -> cmd_mux_004:src_ready
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> sequencer_scc_mgr_inst_avl_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_agent:m0_readdata
wire sequencer_reg_file_inst_avl_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_agent:m0_waitrequest
wire sequencer_reg_file_inst_avl_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
wire [19:0] sequencer_reg_file_inst_avl_agent_m0_address; // sequencer_reg_file_inst_avl_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
wire [3:0] sequencer_reg_file_inst_avl_agent_m0_byteenable; // sequencer_reg_file_inst_avl_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
wire sequencer_reg_file_inst_avl_agent_m0_read; // sequencer_reg_file_inst_avl_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
wire sequencer_reg_file_inst_avl_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_agent:m0_readdatavalid
wire sequencer_reg_file_inst_avl_agent_m0_lock; // sequencer_reg_file_inst_avl_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_writedata; // sequencer_reg_file_inst_avl_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
wire sequencer_reg_file_inst_avl_agent_m0_write; // sequencer_reg_file_inst_avl_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
wire [2:0] sequencer_reg_file_inst_avl_agent_m0_burstcount; // sequencer_reg_file_inst_avl_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
wire sequencer_reg_file_inst_avl_agent_rf_source_valid; // sequencer_reg_file_inst_avl_agent:rf_source_valid -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_valid
wire [96:0] sequencer_reg_file_inst_avl_agent_rf_source_data; // sequencer_reg_file_inst_avl_agent:rf_source_data -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_data
wire sequencer_reg_file_inst_avl_agent_rf_source_ready; // sequencer_reg_file_inst_avl_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_agent:rf_source_ready
wire sequencer_reg_file_inst_avl_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_reg_file_inst_avl_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_agent:rf_sink_valid
wire [96:0] sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_agent:rf_sink_data
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sequencer_reg_file_inst_avl_agent:cp_valid
wire [95:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sequencer_reg_file_inst_avl_agent:cp_data
wire cmd_mux_005_src_ready; // sequencer_reg_file_inst_avl_agent:cp_ready -> cmd_mux_005:src_ready
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sequencer_reg_file_inst_avl_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sequencer_reg_file_inst_avl_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sequencer_reg_file_inst_avl_agent:cp_endofpacket
wire cpu_inst_data_master_agent_cp_valid; // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
wire [95:0] cpu_inst_data_master_agent_cp_data; // cpu_inst_data_master_agent:cp_data -> router:sink_data
wire cpu_inst_data_master_agent_cp_ready; // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
wire cpu_inst_data_master_agent_cp_startofpacket; // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_inst_data_master_agent_cp_endofpacket; // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [95:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire cpu_inst_instruction_master_agent_cp_valid; // cpu_inst_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [95:0] cpu_inst_instruction_master_agent_cp_data; // cpu_inst_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_inst_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_inst_instruction_master_agent:cp_ready
wire cpu_inst_instruction_master_agent_cp_startofpacket; // cpu_inst_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire cpu_inst_instruction_master_agent_cp_endofpacket; // cpu_inst_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [95:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire sequencer_phy_mgr_inst_avl_agent_rp_valid; // sequencer_phy_mgr_inst_avl_agent:rp_valid -> router_002:sink_valid
wire [95:0] sequencer_phy_mgr_inst_avl_agent_rp_data; // sequencer_phy_mgr_inst_avl_agent:rp_data -> router_002:sink_data
wire sequencer_phy_mgr_inst_avl_agent_rp_ready; // router_002:sink_ready -> sequencer_phy_mgr_inst_avl_agent:rp_ready
wire sequencer_phy_mgr_inst_avl_agent_rp_startofpacket; // sequencer_phy_mgr_inst_avl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire sequencer_phy_mgr_inst_avl_agent_rp_endofpacket; // sequencer_phy_mgr_inst_avl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [95:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire sequencer_data_mgr_inst_avl_agent_rp_valid; // sequencer_data_mgr_inst_avl_agent:rp_valid -> router_003:sink_valid
wire [95:0] sequencer_data_mgr_inst_avl_agent_rp_data; // sequencer_data_mgr_inst_avl_agent:rp_data -> router_003:sink_data
wire sequencer_data_mgr_inst_avl_agent_rp_ready; // router_003:sink_ready -> sequencer_data_mgr_inst_avl_agent:rp_ready
wire sequencer_data_mgr_inst_avl_agent_rp_startofpacket; // sequencer_data_mgr_inst_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire sequencer_data_mgr_inst_avl_agent_rp_endofpacket; // sequencer_data_mgr_inst_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [95:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire sequencer_rw_mgr_inst_avl_agent_rp_valid; // sequencer_rw_mgr_inst_avl_agent:rp_valid -> router_004:sink_valid
wire [95:0] sequencer_rw_mgr_inst_avl_agent_rp_data; // sequencer_rw_mgr_inst_avl_agent:rp_data -> router_004:sink_data
wire sequencer_rw_mgr_inst_avl_agent_rp_ready; // router_004:sink_ready -> sequencer_rw_mgr_inst_avl_agent:rp_ready
wire sequencer_rw_mgr_inst_avl_agent_rp_startofpacket; // sequencer_rw_mgr_inst_avl_agent:rp_startofpacket -> router_004:sink_startofpacket
wire sequencer_rw_mgr_inst_avl_agent_rp_endofpacket; // sequencer_rw_mgr_inst_avl_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [95:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sequencer_mem_s1_agent_rp_valid; // sequencer_mem_s1_agent:rp_valid -> router_005:sink_valid
wire [95:0] sequencer_mem_s1_agent_rp_data; // sequencer_mem_s1_agent:rp_data -> router_005:sink_data
wire sequencer_mem_s1_agent_rp_ready; // router_005:sink_ready -> sequencer_mem_s1_agent:rp_ready
wire sequencer_mem_s1_agent_rp_startofpacket; // sequencer_mem_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire sequencer_mem_s1_agent_rp_endofpacket; // sequencer_mem_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [95:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_valid; // sequencer_scc_mgr_inst_avl_agent:rp_valid -> router_006:sink_valid
wire [95:0] sequencer_scc_mgr_inst_avl_agent_rp_data; // sequencer_scc_mgr_inst_avl_agent:rp_data -> router_006:sink_data
wire sequencer_scc_mgr_inst_avl_agent_rp_ready; // router_006:sink_ready -> sequencer_scc_mgr_inst_avl_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [95:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sequencer_reg_file_inst_avl_agent_rp_valid; // sequencer_reg_file_inst_avl_agent:rp_valid -> router_007:sink_valid
wire [95:0] sequencer_reg_file_inst_avl_agent_rp_data; // sequencer_reg_file_inst_avl_agent:rp_data -> router_007:sink_data
wire sequencer_reg_file_inst_avl_agent_rp_ready; // router_007:sink_ready -> sequencer_reg_file_inst_avl_agent:rp_ready
wire sequencer_reg_file_inst_avl_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [95:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [95:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [95:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [95:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [95:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [95:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [95:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_003:sink1_valid
wire [95:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src0_ready
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_003:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [95:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [95:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [95:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [95:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink0_valid
wire [95:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_003:src1_ready
wire [5:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [95:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [95:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_data_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_data_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> sequencer_data_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> sequencer_data_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> sequencer_data_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // sequencer_data_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> sequencer_data_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_mem_s1_agent_rdata_fifo_src_valid; // sequencer_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sequencer_mem_s1_agent_rdata_fifo_src_data; // sequencer_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire sequencer_mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sequencer_mem_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sequencer_mem_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sequencer_mem_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sequencer_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sequencer_mem_s1_agent:rdata_fifo_sink_error
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> sequencer_reg_file_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_phy_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_phy_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_phy_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_phy_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_phy_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_phy_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_phy_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_phy_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_phy_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_phy_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_phy_mgr_inst_avl_write), // .write
.av_read (sequencer_phy_mgr_inst_avl_read), // .read
.av_readdata (sequencer_phy_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_phy_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_phy_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_data_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_data_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_data_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_data_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_data_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_data_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_data_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_data_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_data_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_data_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_data_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_data_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_data_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_data_mgr_inst_avl_write), // .write
.av_read (sequencer_data_mgr_inst_avl_read), // .read
.av_readdata (sequencer_data_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_data_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_data_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rw_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_rw_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rw_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rw_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_rw_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rw_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rw_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rw_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rw_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rw_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_rw_mgr_inst_avl_write), // .write
.av_read (sequencer_rw_mgr_inst_avl_read), // .read
.av_readdata (sequencer_rw_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_rw_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_rw_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_mem_s1_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_mem_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_mem_s1_agent_m0_read), // .read
.uav_write (sequencer_mem_s1_agent_m0_write), // .write
.uav_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.uav_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_mem_s1_address), // avalon_anti_slave_0.address
.av_write (sequencer_mem_s1_write), // .write
.av_readdata (sequencer_mem_s1_readdata), // .readdata
.av_writedata (sequencer_mem_s1_writedata), // .writedata
.av_byteenable (sequencer_mem_s1_byteenable), // .byteenable
.av_chipselect (sequencer_mem_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_reg_file_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_reg_file_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_reg_file_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_reg_file_inst_avl_write), // .write
.av_read (sequencer_reg_file_inst_avl_read), // .read
.av_readdata (sequencer_reg_file_inst_avl_readdata), // .readdata
.av_writedata (sequencer_reg_file_inst_avl_writedata), // .writedata
.av_byteenable (sequencer_reg_file_inst_avl_byteenable), // .byteenable
.av_waitrequest (sequencer_reg_file_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_data_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_instruction_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_phy_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_phy_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_phy_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_phy_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_phy_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_phy_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_phy_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_phy_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_phy_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_phy_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_phy_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_phy_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_phy_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_phy_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_phy_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_phy_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_phy_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_phy_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_phy_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_phy_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_phy_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_data_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_data_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_data_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_data_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_data_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_data_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_data_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_data_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_data_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_data_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_data_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_data_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_data_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_data_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_data_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_data_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_data_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_data_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_data_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_data_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_data_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_data_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_data_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_data_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_data_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_data_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_data_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_data_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_data_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_rw_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_rw_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rw_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rw_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rw_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rw_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_rw_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rw_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_rw_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rw_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_rw_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rw_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_rw_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_rw_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rw_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rw_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rw_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rw_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_rw_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_rw_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_rw_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_mem_s1_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_mem_s1_agent_m0_address), // m0.address
.m0_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.m0_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_mem_s1_agent_m0_read), // .read
.m0_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.m0_write (sequencer_mem_s1_agent_m0_write), // .write
.rp_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_mem_s1_agent_rp_ready), // .ready
.rp_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.rp_data (sequencer_mem_s1_agent_rp_data), // .data
.rp_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_mem_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_mem_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_mem_s1_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_mem_s1_agent_rf_source_data), // in.data
.in_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.in_ready (sequencer_mem_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_scc_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (95),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_reg_file_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_reg_file_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_reg_file_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router router (
.sink_ready (cpu_inst_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_inst_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_002 router_002 (
.sink_ready (sequencer_phy_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_phy_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_phy_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_phy_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_phy_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_002 router_003 (
.sink_ready (sequencer_data_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_data_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_data_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_data_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_data_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_002 router_004 (
.sink_ready (sequencer_rw_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rw_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_rw_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_rw_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rw_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_005 router_005 (
.sink_ready (sequencer_mem_s1_agent_rp_ready), // sink.ready
.sink_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.sink_data (sequencer_mem_s1_agent_rp_data), // .data
.sink_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_002 router_006 (
.sink_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_router_002 router_007 (
.sink_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux cmd_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 rsp_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_rsp_demux_003 rsp_demux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_004 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_005 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_rsp_mux rsp_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_003_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_003_src1_valid), // .valid
.sink0_channel (rsp_demux_003_src1_channel), // .channel
.sink0_data (rsp_demux_003_src1_data), // .data
.sink0_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_data_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:05 12/03/2016
// Design Name:
// Module Name: animation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module animationV(clk, rst, height, ram_address, ram_data, mode, on_off);
input clk, rst, mode, on_off; //0 is home mode; 1 is party mode
input [8:0] ram_address;
output reg [47:0] ram_data;
reg [23:0] top, bottom;
input[3:0] height;
reg [4:0] inner_height;
reg [23:0] color;
reg addsub;
//parameter height = 9;
initial begin
top<=0;
bottom<=0;
ram_data <=0;
inner_height<=0;
color<=0;
addsub<=0;
end
//Top half of panel is controlled by last 24 bits of ram_data
always @ (posedge clk) begin
if ( mode == 1'b1) begin
if (ram_address == 0) begin
color<= color+1'b1;
inner_height<={0,height};
end
bottom <= {24{1'b0}};
top <= {24{1'b0}};
if (ram_address > 512 - 1 - $unsigned(inner_height)* 32 ) begin
top <= color;
//bottom <= {24{1'b0}};
end
if (ram_address < $unsigned(inner_height) * 32) begin
//top <= {24{1'b0}};
bottom <= color;
end
ram_data <= {bottom, top};
end
else begin
if (on_off == 1'b1) begin
ram_data <= {8'd179, 8'd255, 8'd255, 8'd179, 8'd255, 8'd255};
end
else begin
ram_data <= 48'b0;
end
end
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * Finite set library *)
(** Set interfaces, inspired by the one of Ocaml. When compared with
Ocaml, the main differences are:
- the lack of [iter] function, useless since Coq is purely functional
- the use of [option] types instead of [Not_found] exceptions
- the use of [nat] instead of [int] for the [cardinal] function
Several variants of the set interfaces are available:
- [WSetsOn] : functorial signature for weak sets
- [WSets] : self-contained version of [WSets]
- [SetsOn] : functorial signature for ordered sets
- [Sets] : self-contained version of [Sets]
- [WRawSets] : a signature for weak sets that may be ill-formed
- [RawSets] : same for ordered sets
If unsure, [S = Sets] is probably what you're looking for: most other
signatures are subsets of it, while [Sets] can be obtained from
[RawSets] via the use of a subset type (see (W)Raw2Sets below).
*)
Require Export Bool SetoidList RelationClasses Morphisms
RelationPairs Equalities Orders OrdersFacts.
Set Implicit Arguments.
Unset Strict Implicit.
Module Type TypElt.
Parameters t elt : Type.
End TypElt.
Module Type HasWOps (Import T:TypElt).
Parameter empty : t.
(** The empty set. *)
Parameter is_empty : t -> bool.
(** Test whether a set is empty or not. *)
Parameter mem : elt -> t -> bool.
(** [mem x s] tests whether [x] belongs to the set [s]. *)
Parameter add : elt -> t -> t.
(** [add x s] returns a set containing all elements of [s],
plus [x]. If [x] was already in [s], [s] is returned unchanged. *)
Parameter singleton : elt -> t.
(** [singleton x] returns the one-element set containing only [x]. *)
Parameter remove : elt -> t -> t.
(** [remove x s] returns a set containing all elements of [s],
except [x]. If [x] was not in [s], [s] is returned unchanged. *)
Parameter union : t -> t -> t.
(** Set union. *)
Parameter inter : t -> t -> t.
(** Set intersection. *)
Parameter diff : t -> t -> t.
(** Set difference. *)
Parameter equal : t -> t -> bool.
(** [equal s1 s2] tests whether the sets [s1] and [s2] are
equal, that is, contain equal elements. *)
Parameter subset : t -> t -> bool.
(** [subset s1 s2] tests whether the set [s1] is a subset of
the set [s2]. *)
Parameter fold : forall A : Type, (elt -> A -> A) -> t -> A -> A.
(** [fold f s a] computes [(f xN ... (f x2 (f x1 a))...)],
where [x1 ... xN] are the elements of [s].
The order in which elements of [s] are presented to [f] is
unspecified. *)
Parameter for_all : (elt -> bool) -> t -> bool.
(** [for_all p s] checks if all elements of the set
satisfy the predicate [p]. *)
Parameter exists_ : (elt -> bool) -> t -> bool.
(** [exists p s] checks if at least one element of
the set satisfies the predicate [p]. *)
Parameter filter : (elt -> bool) -> t -> t.
(** [filter p s] returns the set of all elements in [s]
that satisfy predicate [p]. *)
Parameter partition : (elt -> bool) -> t -> t * t.
(** [partition p s] returns a pair of sets [(s1, s2)], where
[s1] is the set of all the elements of [s] that satisfy the
predicate [p], and [s2] is the set of all the elements of
[s] that do not satisfy [p]. *)
Parameter cardinal : t -> nat.
(** Return the number of elements of a set. *)
Parameter elements : t -> list elt.
(** Return the list of all elements of the given set, in any order. *)
Parameter choose : t -> option elt.
(** Return one element of the given set, or [None] if
the set is empty. Which element is chosen is unspecified.
Equal sets could return different elements. *)
End HasWOps.
Module Type WOps (E : DecidableType).
Definition elt := E.t.
Parameter t : Type. (** the abstract type of sets *)
Include HasWOps.
End WOps.
(** ** Functorial signature for weak sets
Weak sets are sets without ordering on base elements, only
a decidable equality. *)
Module Type WSetsOn (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Include IsEq. (** [eq] is obviously an equivalence, for subtyping only *)
Include HasEqDec.
(** Specifications of set operators *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : mem x s = true <-> In x s.
Parameter equal_spec : equal s s' = true <-> s[=]s'.
Parameter subset_spec : subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
(** When compared with ordered sets, here comes the only
property that is really weaker: *)
Parameter elements_spec2w : NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WSetsOn.
(** ** Static signature for weak sets
Similar to the functorial signature [WSetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type WSets.
Declare Module E : DecidableType.
Include WSetsOn E.
End WSets.
(** ** Functorial signature for sets on ordered elements
Based on [WSetsOn], plus ordering on sets and [min_elt] and [max_elt]
and some stronger specifications for other functions. *)
Module Type HasOrdOps (Import T:TypElt).
Parameter compare : t -> t -> comparison.
(** Total ordering between sets. Can be used as the ordering function
for doing sets of sets. *)
Parameter min_elt : t -> option elt.
(** Return the smallest element of the given set
(with respect to the [E.compare] ordering),
or [None] if the set is empty. *)
Parameter max_elt : t -> option elt.
(** Same as [min_elt], but returns the largest element of the
given set. *)
End HasOrdOps.
Module Type Ops (E : OrderedType) := WOps E <+ HasOrdOps.
Module Type SetsOn (E : OrderedType).
Include WSetsOn E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
Parameter compare_spec : CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : sort E.lt (elements s).
(** Remark: since [fold] is specified via [elements], this stronger
specification of [elements] has an indirect impact on [fold],
which can now be proved to receive elements in increasing order.
*)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : choose s = Some x -> choose s' = Some y ->
Equal s s' -> E.eq x y.
End Spec.
End SetsOn.
(** ** Static signature for sets on ordered elements
Similar to the functorial signature [SetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type Sets.
Declare Module E : OrderedType.
Include SetsOn E.
End Sets.
Module Type S := Sets.
(** ** Some subtyping tests
<<
WSetsOn ---> WSets
| |
| |
V V
SetsOn ---> Sets
Module S_WS (M : Sets) <: WSets := M.
Module Sfun_WSfun (E:OrderedType)(M : SetsOn E) <: WSetsOn E := M.
Module S_Sfun (M : Sets) <: SetsOn M.E := M.
Module WS_WSfun (M : WSets) <: WSetsOn M.E := M.
>>
*)
(** ** Signatures for set representations with ill-formed values.
Motivation:
For many implementation of finite sets (AVL trees, sorted
lists, lists without duplicates), we use the same two-layer
approach:
- A first module deals with the datatype (eg. list or tree) without
any restriction on the values we consider. In this module (named
"Raw" in the past), some results are stated under the assumption
that some invariant (e.g. sortedness) holds for the input sets. We
also prove that this invariant is preserved by set operators.
- A second module implements the exact Sets interface by
using a subtype, for instance [{ l : list A | sorted l }].
This module is a mere wrapper around the first Raw module.
With the interfaces below, we give some respectability to
the "Raw" modules. This allows the interested users to directly
access them via the interfaces. Even better, we can build once
and for all a functor doing the transition between Raw and usual Sets.
Description:
The type [t] of sets may contain ill-formed values on which our
set operators may give wrong answers. In particular, [mem]
may not see a element in a ill-formed set (think for instance of a
unsorted list being given to an optimized [mem] that stops
its search as soon as a strictly larger element is encountered).
Unlike optimized operators, the [In] predicate is supposed to
always be correct, even on ill-formed sets. Same for [Equal] and
other logical predicates.
A predicate parameter [Ok] is used to discriminate between
well-formed and ill-formed values. Some lemmas hold only on sets
validating [Ok]. This predicate [Ok] is required to be
preserved by set operators. Moreover, a boolean function [isok]
should exist for identifying (at least some of) the well-formed sets.
*)
Module Type WRawSets (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Is a set well-formed or ill-formed ? *)
Parameter IsOk : t -> Prop.
Class Ok (s:t) : Prop := ok : IsOk s.
(** In order to be able to validate (at least some) particular sets as
well-formed, we ask for a boolean function for (semi-)deciding
predicate [Ok]. If [Ok] isn't decidable, [isok] may be the
always-false function. *)
Parameter isok : t -> bool.
Declare Instance isok_Ok s `(isok s = true) : Ok s | 10.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Declare Instance eq_equiv : Equivalence eq.
(** First, all operations are compatible with the well-formed predicate. *)
Declare Instance empty_ok : Ok empty.
Declare Instance add_ok s x `(Ok s) : Ok (add x s).
Declare Instance remove_ok s x `(Ok s) : Ok (remove x s).
Declare Instance singleton_ok x : Ok (singleton x).
Declare Instance union_ok s s' `(Ok s, Ok s') : Ok (union s s').
Declare Instance inter_ok s s' `(Ok s, Ok s') : Ok (inter s s').
Declare Instance diff_ok s s' `(Ok s, Ok s') : Ok (diff s s').
Declare Instance filter_ok s f `(Ok s) : Ok (filter f s).
Declare Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Declare Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
(** Now, the specifications, with constraints on the input sets. *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : forall `{Ok s}, mem x s = true <-> In x s.
Parameter equal_spec : forall `{Ok s, Ok s'},
equal s s' = true <-> s[=]s'.
Parameter subset_spec : forall `{Ok s, Ok s'},
subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : forall `{Ok s},
In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : forall `{Ok s},
In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : forall `{Ok s, Ok s'},
In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : forall `{Ok s, Ok s'},
In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : forall `{Ok s, Ok s'},
In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : forall `{Ok s},
cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
Parameter elements_spec2w : forall `{Ok s}, NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WRawSets.
(** From weak raw sets to weak usual sets *)
Module WRaw2SetsOn (E:DecidableType)(M:WRawSets E) <: WSetsOn E.
(** We avoid creating induction principles for the Record *)
Local Unset Elimination Schemes.
Local Unset Case Analysis Schemes.
Definition elt := E.t.
Record t_ := Mkt {this :> M.t; is_ok : M.Ok this}.
Definition t := t_.
Arguments Mkt this {is_ok}.
Hint Resolve is_ok : typeclass_instances.
Definition In (x : elt)(s : t) := M.In x s.(this).
Definition Equal (s s' : t) := forall a : elt, In a s <-> In a s'.
Definition Subset (s s' : t) := forall a : elt, In a s -> In a s'.
Definition Empty (s : t) := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop)(s : t) := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop)(s : t) := exists x, In x s /\ P x.
Definition mem (x : elt)(s : t) := M.mem x s.
Definition add (x : elt)(s : t) : t := Mkt (M.add x s).
Definition remove (x : elt)(s : t) : t := Mkt (M.remove x s).
Definition singleton (x : elt) : t := Mkt (M.singleton x).
Definition union (s s' : t) : t := Mkt (M.union s s').
Definition inter (s s' : t) : t := Mkt (M.inter s s').
Definition diff (s s' : t) : t := Mkt (M.diff s s').
Definition equal (s s' : t) := M.equal s s'.
Definition subset (s s' : t) := M.subset s s'.
Definition empty : t := Mkt M.empty.
Definition is_empty (s : t) := M.is_empty s.
Definition elements (s : t) : list elt := M.elements s.
Definition choose (s : t) : option elt := M.choose s.
Definition fold (A : Type)(f : elt -> A -> A)(s : t) : A -> A := M.fold f s.
Definition cardinal (s : t) := M.cardinal s.
Definition filter (f : elt -> bool)(s : t) : t := Mkt (M.filter f s).
Definition for_all (f : elt -> bool)(s : t) := M.for_all f s.
Definition exists_ (f : elt -> bool)(s : t) := M.exists_ f s.
Definition partition (f : elt -> bool)(s : t) : t * t :=
let p := M.partition f s in (Mkt (fst p), Mkt (snd p)).
Instance In_compat : Proper (E.eq==>eq==>iff) In.
Proof. repeat red. intros; apply M.In_compat; congruence. Qed.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Definition eq_dec : forall (s s':t), { eq s s' }+{ ~eq s s' }.
Proof.
intros (s,Hs) (s',Hs').
change ({M.Equal s s'}+{~M.Equal s s'}).
destruct (M.equal s s') eqn:H; [left|right];
rewrite <- M.equal_spec; congruence.
Defined.
Section Spec.
Variable s s' : t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Lemma mem_spec : mem x s = true <-> In x s.
Proof. exact (@M.mem_spec _ _ _). Qed.
Lemma equal_spec : equal s s' = true <-> Equal s s'.
Proof. exact (@M.equal_spec _ _ _ _). Qed.
Lemma subset_spec : subset s s' = true <-> Subset s s'.
Proof. exact (@M.subset_spec _ _ _ _). Qed.
Lemma empty_spec : Empty empty.
Proof. exact M.empty_spec. Qed.
Lemma is_empty_spec : is_empty s = true <-> Empty s.
Proof. exact (@M.is_empty_spec _). Qed.
Lemma add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Proof. exact (@M.add_spec _ _ _ _). Qed.
Lemma remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Proof. exact (@M.remove_spec _ _ _ _). Qed.
Lemma singleton_spec : In y (singleton x) <-> E.eq y x.
Proof. exact (@M.singleton_spec _ _). Qed.
Lemma union_spec : In x (union s s') <-> In x s \/ In x s'.
Proof. exact (@M.union_spec _ _ _ _ _). Qed.
Lemma inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Proof. exact (@M.inter_spec _ _ _ _ _). Qed.
Lemma diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Proof. exact (@M.diff_spec _ _ _ _ _). Qed.
Lemma fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (fun a e => f e a) (elements s) i.
Proof. exact (@M.fold_spec _). Qed.
Lemma cardinal_spec : cardinal s = length (elements s).
Proof. exact (@M.cardinal_spec s _). Qed.
Lemma filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Proof. exact (@M.filter_spec _ _ _). Qed.
Lemma for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Proof. exact (@M.for_all_spec _ _). Qed.
Lemma exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Proof. exact (@M.exists_spec _ _). Qed.
Lemma partition_spec1 : compatb f -> Equal (fst (partition f s)) (filter f s).
Proof. exact (@M.partition_spec1 _ _). Qed.
Lemma partition_spec2 : compatb f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. exact (@M.partition_spec2 _ _). Qed.
Lemma elements_spec1 : InA E.eq x (elements s) <-> In x s.
Proof. exact (@M.elements_spec1 _ _). Qed.
Lemma elements_spec2w : NoDupA E.eq (elements s).
Proof. exact (@M.elements_spec2w _ _). Qed.
Lemma choose_spec1 : choose s = Some x -> In x s.
Proof. exact (@M.choose_spec1 _ _). Qed.
Lemma choose_spec2 : choose s = None -> Empty s.
Proof. exact (@M.choose_spec2 _). Qed.
End Spec.
End WRaw2SetsOn.
Module WRaw2Sets (D:DecidableType)(M:WRawSets D) <: WSets with Module E := D.
Module E := D.
Include WRaw2SetsOn D M.
End WRaw2Sets.
(** Same approach for ordered sets *)
Module Type RawSets (E : OrderedType).
Include WRawSets E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
(** Specification of [compare] *)
Parameter compare_spec : forall `{Ok s, Ok s'}, CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : forall `{Ok s}, sort E.lt (elements s).
(** Specification of [min_elt] *)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : forall `{Ok s}, min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
(** Specification of [max_elt] *)
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : forall `{Ok s}, max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : forall `{Ok s, Ok s'},
choose s = Some x -> choose s' = Some y -> Equal s s' -> E.eq x y.
End Spec.
End RawSets.
(** From Raw to usual sets *)
Module Raw2SetsOn (O:OrderedType)(M:RawSets O) <: SetsOn O.
Include WRaw2SetsOn O M.
Definition compare (s s':t) := M.compare s s'.
Definition min_elt (s:t) : option elt := M.min_elt s.
Definition max_elt (s:t) : option elt := M.max_elt s.
Definition lt (s s':t) := M.lt s s'.
(** Specification of [lt] *)
Instance lt_strorder : StrictOrder lt.
Proof. constructor ; unfold lt; red.
unfold complement. red. intros. apply (irreflexivity H).
intros. transitivity y; auto.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
repeat red. unfold eq, lt.
intros (s1,p1) (s2,p2) E (s1',p1') (s2',p2') E'; simpl.
change (M.eq s1 s2) in E.
change (M.eq s1' s2') in E'.
rewrite E,E'; intuition.
Qed.
Section Spec.
Variable s s' s'' : t.
Variable x y : elt.
Lemma compare_spec : CompSpec eq lt s s' (compare s s').
Proof. unfold compare; destruct (@M.compare_spec s s' _ _); auto. Qed.
(** Additional specification of [elements] *)
Lemma elements_spec2 : sort O.lt (elements s).
Proof. exact (@M.elements_spec2 _ _). Qed.
(** Specification of [min_elt] *)
Lemma min_elt_spec1 : min_elt s = Some x -> In x s.
Proof. exact (@M.min_elt_spec1 _ _). Qed.
Lemma min_elt_spec2 : min_elt s = Some x -> In y s -> ~ O.lt y x.
Proof. exact (@M.min_elt_spec2 _ _ _ _). Qed.
Lemma min_elt_spec3 : min_elt s = None -> Empty s.
Proof. exact (@M.min_elt_spec3 _). Qed.
(** Specification of [max_elt] *)
Lemma max_elt_spec1 : max_elt s = Some x -> In x s.
Proof. exact (@M.max_elt_spec1 _ _). Qed.
Lemma max_elt_spec2 : max_elt s = Some x -> In y s -> ~ O.lt x y.
Proof. exact (@M.max_elt_spec2 _ _ _ _). Qed.
Lemma max_elt_spec3 : max_elt s = None -> Empty s.
Proof. exact (@M.max_elt_spec3 _). Qed.
(** Additional specification of [choose] *)
Lemma choose_spec3 :
choose s = Some x -> choose s' = Some y -> Equal s s' -> O.eq x y.
Proof. exact (@M.choose_spec3 _ _ _ _ _ _). Qed.
End Spec.
End Raw2SetsOn.
Module Raw2Sets (O:OrderedType)(M:RawSets O) <: Sets with Module E := O.
Module E := O.
Include Raw2SetsOn O M.
End Raw2Sets.
(** It is in fact possible to provide an ordering on sets with
very little information on them (more or less only the [In]
predicate). This generic build of ordering is in fact not
used for the moment, we rather use a simplier version
dedicated to sets-as-sorted-lists, see [MakeListOrdering].
*)
Module Type IN (O:OrderedType).
Parameter Inline t : Type.
Parameter Inline In : O.t -> t -> Prop.
Declare Instance In_compat : Proper (O.eq==>eq==>iff) In.
Definition Equal s s' := forall x, In x s <-> In x s'.
Definition Empty s := forall x, ~In x s.
End IN.
Module MakeSetOrdering (O:OrderedType)(Import M:IN O).
Module Import MO := OrderedTypeFacts O.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Instance : Proper (O.eq==>eq==>iff) In.
Proof.
intros x x' Ex s s' Es. rewrite Ex. apply Es.
Qed.
Definition Below x s := forall y, In y s -> O.lt y x.
Definition Above x s := forall y, In y s -> O.lt x y.
Definition EquivBefore x s s' :=
forall y, O.lt y x -> (In y s <-> In y s').
Definition EmptyBetween x y s :=
forall z, In z s -> O.lt z y -> O.lt z x.
Definition lt s s' := exists x, EquivBefore x s s' /\
((In x s' /\ Below x s) \/
(In x s /\ exists y, In y s' /\ O.lt x y /\ EmptyBetween x y s')).
Instance : Proper (O.eq==>eq==>eq==>iff) EquivBefore.
Proof.
unfold EquivBefore. intros x x' E s1 s1' E1 s2 s2' E2.
setoid_rewrite E; setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Below.
Proof.
unfold Below. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Above.
Proof.
unfold Above. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>O.eq==>eq==>iff) EmptyBetween.
Proof.
unfold EmptyBetween. intros x x' Ex y y' Ey s s' Es.
setoid_rewrite Ex; setoid_rewrite Ey; setoid_rewrite Es; intuition.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
unfold lt. intros s1 s1' E1 s2 s2' E2.
setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
intros s (x & _ & [(IN,Em)|(IN & y & IN' & LT & Be)]).
specialize (Em x IN); order.
specialize (Be x IN LT); order.
(* transitive *)
intros s1 s2 s3 (x & EQ & [(IN,Pre)|(IN,Lex)])
(x' & EQ' & [(IN',Pre')|(IN',Lex')]).
(* 1) Pre / Pre --> Pre *)
assert (O.lt x x') by (specialize (Pre' x IN); auto).
exists x; split.
intros y Hy; rewrite <- (EQ' y); auto; order.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2) Pre / Lex *)
elim_compare x x'.
(* 2a) x=x' --> Pre *)
destruct Lex' as (y & INy & LT & Be).
exists y; split.
intros z Hz. split; intros INz.
specialize (Pre z INz). rewrite <- (EQ' z), <- (EQ z); auto; order.
specialize (Be z INz Hz). rewrite (EQ z), (EQ' z); auto; order.
left; split; auto.
intros z Hz. transitivity x; auto; order.
(* 2b) x<x' --> Pre *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
(* 3) Lex / Pre --> Lex *)
destruct Lex as (y & INy & LT & Be).
specialize (Pre' y INy).
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz; apply Be; auto. rewrite (EQ' z); auto; order.
(* 4) Lex / Lex *)
elim_compare x x'.
(* 4a) x=x' --> impossible *)
destruct Lex as (y & INy & LT & Be).
setoid_replace x with x' in LT; auto.
specialize (Be x' IN' LT); order.
(* 4b) x<x' --> Lex *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
destruct Lex as (y & INy & LT & Be).
elim_compare y x'.
(* 4ba *)
destruct Lex' as (y' & Iny' & LT' & Be').
exists y'; repeat split; auto. order.
intros z Hz LTz. specialize (Be' z Hz LTz).
rewrite <- (EQ' z) in Hz by order.
apply Be; auto. order.
(* 4bb *)
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz. apply Be; auto. rewrite (EQ' z); auto; order.
(* 4bc*)
assert (O.lt x' x) by auto. order.
(* 4c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
Qed.
Lemma lt_empty_r : forall s s', Empty s' -> ~ lt s s'.
Proof.
intros s s' Hs' (x & _ & [(IN,_)|(_ & y & IN & _)]).
elim (Hs' x IN).
elim (Hs' y IN).
Qed.
Definition Add x s s' := forall y, In y s' <-> O.eq x y \/ In y s.
Lemma lt_empty_l : forall x s1 s2 s2',
Empty s1 -> Above x s2 -> Add x s2 s2' -> lt s1 s2'.
Proof.
intros x s1 s2 s2' Em Ab Ad.
exists x; split.
intros y Hy; split; intros IN.
elim (Em y IN).
rewrite (Ad y) in IN; destruct IN as [EQ|IN]. order.
specialize (Ab y IN). order.
left; split.
rewrite (Ad x). now left.
intros y Hy. elim (Em y Hy).
Qed.
Lemma lt_add_lt : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.lt x1 x2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 LT.
exists x1; split; [ | right; split]; auto.
intros y Hy. rewrite (Ad1 y), (Ad2 y).
split; intros [U|U]; try order.
specialize (Ab1 y U). order.
specialize (Ab2 y U). order.
rewrite (Ad1 x1); auto with *.
exists x2; repeat split; auto.
rewrite (Ad2 x2); now left.
intros y. rewrite (Ad2 y). intros [U|U]. order.
specialize (Ab2 y U). order.
Qed.
Lemma lt_add_eq : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.eq x1 x2 -> lt s1 s2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 Hx (x & EQ & Disj).
assert (O.lt x1 x).
destruct Disj as [(IN,_)|(IN,_)]; auto. rewrite Hx; auto.
exists x; split.
intros z Hz. rewrite (Ad1 z), (Ad2 z).
split; intros [U|U]; try (left; order); right.
rewrite <- (EQ z); auto.
rewrite (EQ z); auto.
destruct Disj as [(IN,Em)|(IN & y & INy & LTy & Be)].
left; split; auto.
rewrite (Ad2 x); auto.
intros z. rewrite (Ad1 z); intros [U|U]; try specialize (Ab1 z U); auto; order.
right; split; auto.
rewrite (Ad1 x); auto.
exists y; repeat split; auto.
rewrite (Ad2 y); auto.
intros z. rewrite (Ad2 z). intros [U|U]; try specialize (Ab2 z U); auto; order.
Qed.
End MakeSetOrdering.
Module MakeListOrdering (O:OrderedType).
Module MO:=OrderedTypeFacts O.
Local Notation t := (list O.t).
Local Notation In := (InA O.eq).
Definition eq s s' := forall x, In x s <-> In x s'.
Instance eq_equiv : Equivalence eq := _.
Inductive lt_list : t -> t -> Prop :=
| lt_nil : forall x s, lt_list nil (x :: s)
| lt_cons_lt : forall x y s s',
O.lt x y -> lt_list (x :: s) (y :: s')
| lt_cons_eq : forall x y s s',
O.eq x y -> lt_list s s' -> lt_list (x :: s) (y :: s').
Hint Constructors lt_list.
Definition lt := lt_list.
Hint Unfold lt.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
assert (forall s s', s=s' -> ~lt s s').
red; induction 2.
discriminate.
inversion H; subst.
apply (StrictOrder_Irreflexive y); auto.
inversion H; subst; auto.
intros s Hs; exact (H s s (eq_refl s) Hs).
(* transitive *)
intros s s' s'' H; generalize s''; clear s''; elim H.
intros x l s'' H'; inversion_clear H'; auto.
intros x x' l l' E s'' H'; inversion_clear H'; auto.
constructor 2. transitivity x'; auto.
constructor 2. rewrite <- H0; auto.
intros.
inversion_clear H3.
constructor 2. rewrite H0; auto.
constructor 3; auto. transitivity y; auto. unfold lt in *; auto.
Qed.
Instance lt_compat' :
Proper (eqlistA O.eq==>eqlistA O.eq==>iff) lt.
Proof.
apply proper_sym_impl_iff_2; auto with *.
intros s1 s1' E1 s2 s2' E2 H.
revert s1' E1 s2' E2.
induction H; intros; inversion_clear E1; inversion_clear E2.
constructor 1.
constructor 2. MO.order.
constructor 3. MO.order. unfold lt in *; auto.
Qed.
Lemma eq_cons :
forall l1 l2 x y,
O.eq x y -> eq l1 l2 -> eq (x :: l1) (y :: l2).
Proof.
unfold eq; intros l1 l2 x y Exy E12 z.
split; inversion_clear 1.
left; MO.order. right; rewrite <- E12; auto.
left; MO.order. right; rewrite E12; auto.
Qed.
Hint Resolve eq_cons.
Lemma cons_CompSpec : forall c x1 x2 l1 l2, O.eq x1 x2 ->
CompSpec eq lt l1 l2 c -> CompSpec eq lt (x1::l1) (x2::l2) c.
Proof.
destruct c; simpl; inversion_clear 2; auto with relations.
Qed.
Hint Resolve cons_CompSpec.
End MakeListOrdering.
|
`timescale 1 ns / 1 ps
`include "Speck_Block_Cipher_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Speck_Block_Cipher_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v2_3_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v2_3_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v2_3_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
//
`timescale 1ns/1ps
module stage3(
input reset,
input core_sp_clk,
input [31:0] previous_bblock,
input [31:0] previous_nhop,
input [31:0] fifo_pr_bblock, // previous block read from the fifo
input [31:0] fifo_pr_nhop,
output [12:2] jump_index_addr,
output [31:0] jump_bblock
);
reg [12:2] jump_index_addr_reg;
assign jump_index_addr = jump_index_addr_reg;
reg [31:0] jump_bblock_reg;
reg [31:0] jump_bblock_reg_tmp;
assign jump_bblock = jump_bblock_reg;
always @(posedge core_sp_clk)
begin
if(reset) begin
jump_index_addr_reg <= 0;
jump_bblock_reg <= 32'b00000000000000000000000000000001;
end else begin
if ((fifo_pr_bblock == previous_bblock) || ((fifo_pr_bblock+1'b1) == previous_bblock) || ((fifo_pr_bblock-1'b1) == previous_bblock)) begin
jump_index_addr_reg <= 0;
jump_bblock_reg_tmp <= 32'b00000000000000000000000000000001;
end else begin
jump_index_addr_reg <= fifo_pr_nhop[12:2];
jump_bblock_reg_tmp <= previous_bblock;
end
jump_bblock_reg <= jump_bblock_reg_tmp;
end
end
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic dual-port RAM
*/
module ram_dp #
(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
)
(
// port A
input wire a_clk,
input wire a_we,
input wire [ADDR_WIDTH-1:0] a_addr,
input wire [DATA_WIDTH-1:0] a_din,
output wire [DATA_WIDTH-1:0] a_dout,
// port B
input wire b_clk,
input wire b_we,
input wire [ADDR_WIDTH-1:0] b_addr,
input wire [DATA_WIDTH-1:0] b_din,
output wire [DATA_WIDTH-1:0] b_dout
);
reg [DATA_WIDTH-1:0] a_dout_reg = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] b_dout_reg = {DATA_WIDTH{1'b0}};
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
assign a_dout = a_dout_reg;
assign b_dout = b_dout_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
// port A
always @(posedge a_clk) begin
a_dout_reg <= mem[a_addr];
if (a_we) begin
mem[a_addr] <= a_din;
a_dout_reg <= a_din;
end
end
// port B
always @(posedge b_clk) begin
b_dout_reg <= mem[b_addr];
if (b_we) begin
mem[b_addr] <= b_din;
b_dout_reg <= b_din;
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_icmp(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall, i_settings);
parameter DATA_WIDTH = 32;
parameter MODE_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output reg o_dataout;
output o_dataout_valid;
input i_stall;
input [MODE_WIDTH-1:0] i_settings;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire signed [DATA_WIDTH-1:0] sdataa;
wire signed [DATA_WIDTH-1:0] sdatab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign sdataa = dataa;
assign sdatab = datab;
always @(*)
begin
case (i_settings)
5'h0: // EQ
begin
o_dataout <= (dataa == datab) ? 1'b1 : 1'b0;
end
5'h1: // NE
begin
o_dataout <= (dataa != datab) ? 1'b1 : 1'b0;
end
5'h2: // UGT
begin
o_dataout <= (dataa > datab) ? 1'b1 : 1'b0;
end
5'h3: // UGE
begin
o_dataout <= (dataa >= datab) ? 1'b1 : 1'b0;
end
5'h4: // ULT
begin
o_dataout <= (dataa < datab) ? 1'b1 : 1'b0;
end
5'h5: // ULE
begin
o_dataout <= (dataa <= datab) ? 1'b1 : 1'b0;
end
5'h6: // SGT
begin
o_dataout <= (sdataa > sdatab) ? 1'b1 : 1'b0;
end
5'h7: // SGE
begin
o_dataout <= (sdataa >= sdatab) ? 1'b1 : 1'b0;
end
5'h8: // SLT
begin
o_dataout <= (sdataa < sdatab) ? 1'b1 : 1'b0;
end
5'h9: // SLE
begin
o_dataout <= (sdataa <= sdatab) ? 1'b1 : 1'b0;
end
default:
begin
o_dataout <= 1'b0;
end
endcase
end
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
/////////////////////////////////////////////////////////////////////////
//
// pLIB
// D-FLIP-FLOPS
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// p_I_FD FD error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD (Q,D,C,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
defparam FD_z.INIT=INIT;
FD FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD FD error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD (Q,D,C,E);
parameter INIT = 1'b0;
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FD_1 FD_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD_1 FD_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC FDC error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC FDC error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC_1 FDC_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC_1 FDC_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE FDCE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE_1 FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE_1 FDCE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP FDCP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP FDCP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP_1 FDCP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP_1 FDCP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE FDCPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE FDCPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE_1 FDCPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE_1 FDCPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE FDE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE FDE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE (Q,D,C,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE #(.INIT(INIT)) p_O_FDEFD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE_1 FDE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE_1 FDE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP FDP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP FDP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP_1 FDP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP_1 FDP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE FDPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE FDPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE_1 FDPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE_1 FDPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR FDR error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR FDR error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR (Q,D,C,R,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
defparam FD_z.INIT=INIT;
// Xilinx FD instance
FDR FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR_1 FDR_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR_1 FDR_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE FDRE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE FDRE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE (Q,D,C,R,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE_1 FDRE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE_1 FDRE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS FDRS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS_1 FDRS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS_1 FDRS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE FDRSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE_1 FDRSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE_1 FDRSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS FDS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS FDS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS_1 FDS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS_1 FDS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE FDSE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE FDSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE_1 FDSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE_1 FDSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:14:07 AM
// Design Name:
// Module Name: FPU_UART
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_UART
#(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//-- Single Precision*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
input wire clk,
input wire rst,
output wire TX
);
//local parameters
localparam shift_region = 2'b00;
localparam N = 2; //2 para 32 bits, 3 para 64 bits
localparam op = 1'b0;
localparam d = 0;
localparam r_mode=2'b00;
//signal declaration
wire ready_op;
wire max_tick_address;
wire max_tick_ch;
wire TX_DONE;
wire beg_op;
wire ack_op;
wire load_address;
wire enab_address;
wire enab_ch;
wire load_ch;
wire TX_START;
wire [W-1:0] Data_X;
wire [W-1:0] Data_Y;
wire [W-1:0] final_result_ieee;
wire [7:0] TX_DATA;
wire [9:0] cont_address_sig;
wire [N-1:0] cont_ch;
FSM_test fsm_test_uart
(
.clk(clk),
.rst(rst),
.ready_op(ready_op),
.max_tick_address(max_tick_address),
.max_tick_ch(max_tick_ch),
.TX_DONE(TX_DONE),
.beg_op(beg_op),
.ack_op(ack_op),
.load_address(load_address),
.enab_address(enab_address),
.enab_ch(enab_ch),
.load_ch(load_ch),
.TX_START(TX_START)
);
//Adder-Subtract//////////////////////////////////////////////////////////////////////////////
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) Add_Subt_uart(
.clk(clk), //System clock
.rst(rst), //System reset
.beg_FSM(beg_op), //Start operation control signal
.ack_FSM(ack_op), //Acknoledge control signal
.Data_X(Data_X), //Data_X
.Data_Y(Data_Y), //Data_Y
.add_subt(op), //1'b0 =Adder, 1'b1=Substract
.r_mode(r_mode), //Rounding control signal. 2'b00=no round, 2'b01= -infinite round , 2'b10 +infinite round
//.overflow_flag,
//.underflow_flag,
.ready(ready_op), //Ready flag
.final_result_ieee(final_result_ieee) //Result of the operation
);//*/
//Multiplication
/*FPU_Multiplication_Function #(.W(W),.EW(EW),.SW(SW)) Multiplication_uart(
.clk(clk),
.rst(rst),
.beg_FSM(beg_op),
.ack_FSM(ack_op),
.Data_MX(Data_X),
.Data_MY(Data_Y),
.round_mode(r_mode),
//.overflow_flag,
//.underflow_flag,
.ready(ready_op),
.final_result_ieee(final_result_ieee)
);
//*/
Uart uart_mod
(
.RST(rst),
.CLK(clk),
.TX_START(TX_START),
.TX_DATA(TX_DATA),
.TX(TX),
.TX_DONE(TX_DONE)
);
///Data file ROM
ROM_test #(.W(W),.N(0)) rom_test_uart_X
(
.address(cont_address_sig),
.data(Data_X)
);
ROM_test #(.W(W),.N(1)) rom_test_uart_Y
(
.address(cont_address_sig),
.data(Data_Y)
);
cont_test #(.W(10)) cont_address
(
.clk(clk),
.rst(rst),
.load(load_address),
.enable(enab_address),
.d(d),
.max_tick(max_tick_address),
.q(cont_address_sig)
);
cont_test #(.W(N)) con_mux_data
(
.clk(clk),
.rst(rst),
.load(load_ch),
.enable(enab_ch),
.d(d),
.max_tick(max_tick_ch),
.q(cont_ch)
);
generate
case(W)
32:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
64:
begin
Mux_8x1 mux_64_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.ch_4(final_result_ieee[39:32]),
.ch_5(final_result_ieee[47:40]),
.ch_6(final_result_ieee[55:48]),
.ch_7(final_result_ieee[63:56]),
.data_out(TX_DATA)
);
end
default:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
endcase
endgenerate
endmodule |
(** * Stlc_J: 単純型付きラムダ計算 *)
(* * Stlc: The Simply Typed Lambda-Calculus *)
(* $Date: 2011-06-09 16:11:42 -0400 (Thu, 09 Jun 2011) $ *)
Require Export Types_J.
(* ###################################################################### *)
(* * The Simply Typed Lambda-Calculus *)
(** * 単純型付きラムダ計算 *)
(* The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as above when formalizing
of this calculus (syntax, small-step semantics, typing rules) and
its main properties (progress and preservation). The new
technical challenges (which will take some work to deal with) all
arise from the mechanisms of _variable binding_ and
_substitution_. *)
(** 単純型付きラムダ計算(Simply Typed Lambda-Calculus, STLC)は、
関数抽象(_functional abstraction_)を具現する、小さな、核となる計算体系です。
関数抽象は、ほとんどすべての実世界のプログラミング言語に何らかの形
(関数、手続き、メソッド等)で現れます。
ここでは、この計算体系(構文、スモールステップ意味論、
型付け規則)とその性質(進行と保存)の形式化を、
これまでやったのとまったく同じパターンで行います。
(扱うためにいくらかの作業が必要になる)新しい技術的挑戦は、
すべて変数束縛(_variable binding_)と置換(_substitution_)の機構から生じます。*)
(* ###################################################################### *)
(* ** Overview *)
(** ** 概観 *)
(* The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below):
<<<
t ::= x variable
| \x:T.t1 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
>>
The [\] symbol in a function abstraction [\x:T.t1] is often
written as a greek "lambda" (hence the name of the calculus). The
variable [x] is called the _parameter_ to the function; the term
[t1] is its _body_. The annotation [:T] specifies the type of
arguments that the function can be applied to.
Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true].
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function.
As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions.
<<
T ::= Bool
| T1 -> T2
>>
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
- [\f:Bool->Bool. f (f true)] has type [(Bool->Bool) -> Bool]
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)] has type [Bool]
*)
(** STLC は基本型(_base types_)の何らかの集まりの上に構成されます。
基本型はブール型、数値、文字列などです。
実際にどの基本型を選択するかは問題ではありません。
どう選択しても、言語の構成とその理論的性質はまったく同じように導かれます。
これから、簡潔にするため、しばらくは[Bool]だけとしましょう。
この章の終わりには、さらに基本型を追加する方法がわかるでしょう。
また後の章では、純粋なSTLCに、対、レコード、サブタイプ、
変更可能状態などの他の便利な構成要素をとり入れてよりリッチなものにします。
ブール値から始めて3つのものを追加します:
- 変数
- 関数抽象
- (関数)適用
これから、以下の抽象構文コンストラクタが出てきます
(ここではこれを非形式的BNF記法で書き出します。後に形式化します。):
<<
t ::= x 変数
| \x:T.t1 関数抽象
| t1 t2 関数適用
| true 定数 true
| false 定数 false
| if t1 then t2 else t3 条件式
>>
関数抽象 [\x:T.t1] の [\]記号はよくギリシャ文字のラムダ(λ)で記述されます
(これがラムダ計算の名前の由来です)。
変数[x]は関数のパラメータ(_parameter_)、
項[t1]は関数の本体(_body_)と呼ばれます。
付記された [:T] は関数が適用される引数の型を定めます。
例をいくつか:
- [\x:Bool. x]
ブール値の恒等関数。
- [(\x:Bool. x) true]
ブール値[true]に適用された、ブール値の恒等関数。
- [\x:Bool. if x then false else true]
ブール値の否定関数。
- [\x:Bool. true]
すべての(ブール値の)引数に対して[true]を返す定数関数。
- [\x:Bool. \y:Bool. x]
2つのブール値をとり、最初のものを返す2引数関数。
(なお、Coqと同様、2引数関数は、実際には本体が1引数関数である1引数関数です。)
- [(\x:Bool. \y:Bool. x) false true]
2つのブール値をとり、最初のものを返す2引数関数を、ブール値[false]と[true]
に適用したもの。
なお、Coqと同様、関数適用は左結合です。つまり、この式は
[((\x:Bool. \y:Bool. x) false) true] と構文解析されます。
- [\f:Bool->Bool. f (f true)]
(ブール値からブール値への)「関数」[f]を引数にとる高階関数。
この高階関数は、[f]を[true]に適用し、その値にさらに[f]を適用します。
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
上記高階関数を、常に[false]を返す定数関数に適用したもの。
最後のいくつかの例で示されたように、STLCは高階(_higher-order_)関数の言語です。
他の関数を引数として取る関数や、結果として他の関数を返す関数を書き下すことができます。
別の注目点は、名前を持つ(_named_)関数を定義する基本構文を、STLCは何も持っていないことです。
すべての関数は「名無し」("anonymous")です。
後の[MoreStlc_J]章で、この体系に名前を持つ関数を追加することが簡単であることがわかるでしょう。
実のところ、基本的な命名と束縛の機構はまったく同じです。
STLCの型には[Bool]が含まれます。
この型はブール値定数[true]と[false]、および結果がブール値になるより複雑な計算の型です。
それに加えて「関数型」(_arrow types_)があります。
これは関数の型です。
<<
T ::= Bool
| T1 -> T2
>>
例えば:
- [\x:Bool. false] は型 [Bool->Bool] を持ちます。
- [\x:Bool. x] は型 [Bool->Bool] を持ちます。
- [(\x:Bool. x) true] は型 [Bool] を持ちます。
- [\x:Bool. \y:Bool. x] は型 [Bool->Bool->Bool]
(つまり [Bool -> (Bool->Bool)])を持ちます。
- [(\x:Bool. \y:Bool. x) false] は型 [Bool->Bool] を持ちます。
- [(\x:Bool. \y:Bool. x) false true] は型 [Bool] を持ちます。
- [\f:Bool->Bool. f (f true)] は型 [(Bool->Bool) -> Bool] を持ちます。
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)] は型 [Bool] を持ちます。
*)
(* ###################################################################### *)
(* ** Syntax *)
(** ** 構文 *)
Module STLC.
(* ################################### *)
(* *** Types *)
(** *** 型 *)
Inductive ty : Type :=
| ty_Bool : ty
| ty_arrow : ty -> ty -> ty.
(* ################################### *)
(* *** Terms *)
(** *** 項 *)
Inductive tm : Type :=
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_true : tm
| tm_false : tm
| tm_if : tm -> tm -> tm -> tm.
(* Something to note here is that an abstraction [\x:T.t] (formally,
[tm_abs x T t]) is always annotated with the type ([T]) of its
parameter. This is in contrast to Coq (and other functional
languages like ML, Haskell, etc.), which use _type inference_ to
fill in missing annotations. *)
(** ここで注目すべきは、関数抽象 [\x:T.t] (形式的には [tm_abs x T t])
には常にパラメータの型([T])が付記されることです。
これは Coq(あるいは他のML、Haskellといった関数型言語)と対照的です。
それらは、付記がないものを型推論で補完します。*)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app"
| Case_aux c "tm_abs" | Case_aux c "tm_true"
| Case_aux c "tm_false" | Case_aux c "tm_if" ].
(* Some examples... *)
(** いくつかの例... *)
Notation a := (Id 0).
Notation b := (Id 1).
Notation c := (Id 2).
(** [idB = \a:Bool. a] *)
Notation idB :=
(tm_abs a ty_Bool (tm_var a)).
(** [idBB = \a:Bool->Bool. a] *)
Notation idBB :=
(tm_abs a (ty_arrow ty_Bool ty_Bool) (tm_var a)).
(** [idBBBB = \a:(Bool->Bool)->(Bool->Bool). a] *)
Notation idBBBB :=
(tm_abs a (ty_arrow (ty_arrow ty_Bool ty_Bool)
(ty_arrow ty_Bool ty_Bool))
(tm_var a)).
(** [k = \a:Bool. \b:Bool. a] *)
Notation k := (tm_abs a ty_Bool (tm_abs b ty_Bool (tm_var a))).
(* (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(** (これらを[Definition]ではなく[Notation]とすることで、
[auto]に扱いやすくしています。) *)
(* ###################################################################### *)
(* ** Operational Semantics *)
(** ** 操作的意味論 *)
(* To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(** STLC項のスモールステップ意味論を定義するために、いつものように、
値の集合を定義することから始めます。
次に、自由変数(_free variables_)と置換(_substitution_)という、
重大な概念を定義します。これらは関数適用式の簡約規則に使われます。
そして最後に、スモールステップ関係自体を与えます。*)
(* ################################### *)
(* *** Values *)
(** *** 値 *)
(* To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. (An [if]
expression is never a value.)
Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do.
Third, for abstractions, we have a choice:
- We can say that [\a:A.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\a:A.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq makes the first choice -- for example,
[[
Eval simpl in (fun a:bool => 3 + 4)
]]
yields [fun a:bool => 7]. But most real functional
programming languages make the second choice -- reduction of
a function's body only begins when the function is actually
applied to an argument. We also make the second choice here.
Finally, having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(** STLCの値を定義するために、いくつかの場合を考えなければなりません。
最初に、言語のブール値については、状況は明確です:
[true]と[false]だけが値です。([if]式は決して値ではありません。)
二番目に、関数適用は明らかに値ではありません。
関数適用は関数が何らかの引数に対して呼ばれたことを表しているのですから、
明らかにこれからやることが残っています。
三番目に、関数抽象については選択肢があります:
- [\a:A.t1] が値であるのは、[t1]が値であるときのみである、
とすることができます。
つまり、関数の本体が
(どのような引数に適用されるかわからない状態で可能な限り)
簡約済みであるときのみ、ということです。
- あるいは、[\a:A.t1] は常に値である、とすることもできます。
[t1]が値であるかどうかに関係なく、です。
言いかえると、簡約は関数抽象で止まる、とすることです。
Coq は最初の選択肢を取っています。例えば、
[[
Eval simpl in (fun a:bool => 3 + 4)
]]
は [fun a:bool => 7] となります。
しかし実際の関数型プログラミング言語のほとんどは、
第二の選択肢を取っています。
つまり、関数の本体の簡約は、関数が実際に引数に適用されたときにのみ開始されます。
ここでは、同様に第二の選択肢を選びます。
最後に、関数抽象の中を簡約することを選択しなかったため、
変数が値であるかをどうかを心配する必要はなくなります。なぜなら、
プログラムの簡約は常に「外側から内側に」行われ、
[step]関係は常に閉じた(自由変数を持たない)項だけを対象とするからです。*)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tm_abs x T t)
| t_true :
value tm_true
| t_false :
value tm_false.
Hint Constructors value.
(* ###################################################################### *)
(* *** Free Variables and Substitution *)
(** *** 自由変数と置換 *)
(* Now we come to the heart of the matter: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
[[
(\x:Bool. if x then true else x) false
]]
to [false] by substituting [false] for the parameter [x] in the
body of the function. In general, we need to be able to
substitute some given term [s] for occurrences of some variable
[x] in another term [t]. In informal discussions, this is usually
written [ [s/x]t ] and pronounced "substitute [s] for [x] in [t]."
Here are some examples:
- [[true / a] (if a then a else false)] yields [if true then true else false]
- [[true / a] a] yields [true]
- [[true / a] (if a then a else b)] yields [if true then true else b]
- [[true / a] b] yields [b]
- [[true / a] false] yields [false] (vacuous substitution)
- [[true / a] (\y:Bool. if y then a else false)] yields [\y:Bool. if y then true else false]
- [[true / a] (\y:Bool. a)] yields [\y:Bool. true]
- [[true / a] (\y:Bool. y)] yields [\y:Bool. y]
- [[true / a] (\a:Bool. a)] yields [\a:Bool. a]
The last example is very important: substituting [true] for [a] in
[\a:Bool. a] does _not_ yield [\a:Bool. true]! The reason for
this is that the [a] in the body of [\a:Bool. a] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [a].
Here is the definition, informally...
[[
[s/x]x = s
[s/x]y = y if x <> y
[s/x](\x:T11.t12) = \x:T11. t12
[s/x](\y:T11.t12) = \y:T11. [s/x]t12 if x <> y
[s/x](t1 t2) = ([s/x]t1) ([s/x]t2)
[s/x]true = true
[s/x]false = false
[s/x](if t1 then t2 else t3) =
if [s/x]t1 then [s/x]t2 else [s/x]t3
]]
... and formally: *)
(** これから問題の核心に入ります: 項の変数を別の項で置換する操作です。
この操作は後で関数適用の操作的意味論を定義するために使います。
関数適用では、関数本体の中の関数パラメータを引数項で置換することが必要になります。
例えば、
[[
(\x:Bool. if x then true else x) false
]]
は、関数の本体のパラメータ[x]を[false]で置換することで、[false]に簡約されます。
一般に、ある項[t]の変数[x]の出現を、与えらえた項[s]で置換できることが必要です。
非形式的な議論では、これは通常 [ [s/x]t ] と書き、「[t]の[x]を[s]で置換する」と読みます。
いくつかの例を示します:
- [[true / a] (if a then a else false)] は [if true then true else false]
となります。
- [[true / a] a] は [true] となります。
- [[true / a] (if a then a else b)] は [if true then true else b]
となります。
- [[true / a] b] は [b] となります。
- [[true / a] false] は [false] となります(何もしない置換です)。
- [[true / a] (\y:Bool. if y then a else false)] は
[\y:Bool. if y then true else false] となります。
- [[true / a] (\y:Bool. a)] は [\y:Bool. true] となります。
- [[true / a] (\y:Bool. y)] は [\y:Bool. y] となります。
- [[true / a] (\a:Bool. a)] は [\a:Bool. a] となります。
最後の例はとても重要です。[\a:Bool. a] の [a] を [true] で置換したものは、
[\a:Bool. true] に「なりません」! 理由は、[\a:Bool. a] の本体の [a]
は関数抽象で束縛されている(_bound_)からです。
この[a]は新しいローカルな名前で、たまたまグローバルな名前[a]と同じ綴りであったものです。
以下が、非形式的な定義です...
[[
[s/x]x = s
[s/x]y = y if x <> y
[s/x](\x:T11.t12) = \x:T11. t12
[s/x](\y:T11.t12) = \y:T11. [s/x]t12 if x <> y
[s/x](t1 t2) = ([s/x]t1) ([s/x]t2)
[s/x]true = true
[s/x]false = false
[s/x](if t1 then t2 else t3) =
if [s/x]t1 then [s/x]t2 else [s/x]t3
]]
... そして形式的には: *)
Fixpoint subst (s:tm) (x:id) (t:tm) : tm :=
match t with
| tm_var x' => if beq_id x x' then s else t
| tm_abs x' T t1 => tm_abs x' T (if beq_id x x' then t1 else (subst s x t1))
| tm_app t1 t2 => tm_app (subst s x t1) (subst s x t2)
| tm_true => tm_true
| tm_false => tm_false
| tm_if t1 t2 t3 => tm_if (subst s x t1) (subst s x t2) (subst s x t3)
end.
(* Technical note: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested in defining the [step] relation on
closed terms here, we can avoid this extra complexity. *)
(** 技術的注釈: 置換は、もし[s]、つまり他の項の変数を置換する項が、
それ自身に自由変数を含むときを考えると、
定義がよりトリッキーなものになります。
ここで興味があるのは閉じた項についての[step]関係の定義のみなので、
そのさらなる複雑さは避けることができます。*)
(* ################################### *)
(* *** Reduction *)
(** *** 簡約 *)
(* The small-step reduction relation for STLC follows the same
pattern as the ones we have seen before. Intuitively, to
reduce a function application, we first reduce its left-hand
side until it becomes a literal function; then we reduce its
right-hand side (the argument) until it is also a value; and
finally we substitute the argument for the bound variable in
the body of the function. This last rule, written informally
as
[[
(\a:T.t12) v2 ==> [v2/a]t12
]]
is traditionally called "beta-reduction".
Informally:
[[[
--------------------------- (ST_AppAbs)
(\a:T.t12) v2 ==> [v2/a]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
]]]
(plus the usual rules for booleans).
Formally:
*)
(** STLCのスモールステップ簡約関係は、これまで見てきたものと同じパターンに従います。
直観的には、関数適用を簡約するため、最初に左側をリテラル関数になるまで簡約します。
次に左側(引数)を値になるまで簡約します。そして最後に関数の本体の束縛変数を引数で置換します。
この最後の規則は、非形式的には次のように書きます:
[[
(\a:T.t12) v2 ==> [v2/a]t12
]]
これは伝統的にベータ簡約("beta-reduction")と呼ばれます。
非形式的に:
[[
--------------------------- (ST_AppAbs)
(\a:T.t12) v2 ==> [v2/a]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
]]
(これに通常のブール値の規則をプラスします)。
形式的には:
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tm_app (tm_abs x T t12) v2) ==> (subst v2 x t12)
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tm_app t1 t2 ==> tm_app t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tm_app v1 t2 ==> tm_app v1 t2'
| ST_IfTrue : forall t1 t2,
(tm_if tm_true t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tm_if tm_false t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tm_if t1 t2 t3) ==> (tm_if t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Notation stepmany := (refl_step_closure step).
Notation "t1 '==>*' t2" := (stepmany t1 t2) (at level 40).
Hint Constructors step.
(* ##################################### *)
(* *** Examples *)
(** *** 例 *)
Lemma step_example1 :
(tm_app idBB idB) ==>* idB.
Proof.
eapply rsc_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply rsc_refl. Qed.
(* A more automatic proof *)
Lemma step_example1' :
(tm_app idBB idB) ==>* idB.
Proof. normalize. Qed.
Lemma step_example2 :
(tm_app idBB (tm_app idBB idB)) ==>* idB.
Proof.
eapply rsc_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply rsc_step.
apply ST_AppAbs. simpl. auto.
simpl. apply rsc_refl. Qed.
(* Again, we can use the [normalize] tactic from above to simplify
the proof. *)
(** 再び、上述の[normalize]タクティックを使って、証明を簡単にすることができます。*)
Lemma step_example2' :
(tm_app idBB (tm_app idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
(* **** Exercise: 2 stars (step_example3) *)
(** **** 練習問題: ★★ (step_example3) *)
(* Try to do this one both with and without [normalize]. *)
(** 次の証明を[normalize]を使う方法と使わない方法の両方で行ないなさい。*)
Lemma step_example3 :
(tm_app (tm_app idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(* ** Typing *)
(** ** 型付け *)
(* ################################### *)
(* *** Contexts *)
(** *** コンテキスト *)
(* Question: What is the type of the term "[x y]"?
Answer: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t : T], where [Gamma] is a "typing context"
-- a mapping from variables to their types.
We hide the definition of partial maps in a module since it is
actually defined in SfLib. *)
(** 問い: 項 "[x y]" の型は何でしょう？
答え: それは [x] と [y] の型に依存します!
つまり、項に型を付けるためには、
その自由変数の型についてどういう仮定をしなければならないかを知る必要があります。
このために、3つのものの間の型付けジャッジメント("typing judgment")を用意します。
これを非形式的には [Gamma |- t : T] と記述します。ここで
[Gamma] は「型付けコンテキスト」("typing context")、つまり、
変数から型への写像です。
モジュールにおける部分写像の定義は隠蔽します。
なぜなら、実際には SfLib で定義されているからです。*)
Definition context := partial_map ty.
Module Context.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if beq_id x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite <- beq_id_refl. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
beq_id x2 x1 = false ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite H. auto.
Qed.
End Context.
(* ################################### *)
(* *** Typing Relation *)
(** *** 型付け関係 *)
(* Informally:
[[[
Gamma x = T
-------------- (T_Var)
Gamma |- x : T
Gamma , x:T11 |- t12 : T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 : T11->T12
Gamma |- t1 : T11->T12
Gamma |- t2 : T11
---------------------- (T_App)
Gamma |- t1 t2 : T12
-------------------- (T_True)
Gamma |- true : Bool
--------------------- (T_False)
Gamma |- false : Bool
Gamma |- t1 : Bool Gamma |- t2 : T Gamma |- t3 : T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 : T
]]]
The notation [ Gamma , x:T ] means "extend the partial function [Gamma]
to also map [x] to [T]."
*)
(** 非形式的に:
[[
Gamma x = T
-------------- (T_Var)
Gamma |- x : T
Gamma , x:T11 |- t12 : T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 : T11->T12
Gamma |- t1 : T11->T12
Gamma |- t2 : T11
---------------------- (T_App)
Gamma |- t1 t2 : T12
-------------------- (T_True)
Gamma |- true : Bool
--------------------- (T_False)
Gamma |- false : Bool
Gamma |- t1 : Bool Gamma |- t2 : T Gamma |- t3 : T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 : T
]]
記法 [ Gamma , x:T ] は「部分写像[Gamma]を拡張して[x]を[T]に写像するようにしたもの」を表します。
*)
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tm_var x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tm_abs x T11 t12) (ty_arrow T11 T12)
| T_App : forall T11 T12 Gamma t1 t2,
has_type Gamma t1 (ty_arrow T11 T12) ->
has_type Gamma t2 T11 ->
has_type Gamma (tm_app t1 t2) T12
| T_True : forall Gamma,
has_type Gamma tm_true ty_Bool
| T_False : forall Gamma,
has_type Gamma tm_false ty_Bool
| T_If : forall t1 t2 t3 T Gamma,
has_type Gamma t1 ty_Bool ->
has_type Gamma t2 T ->
has_type Gamma t3 T ->
has_type Gamma (tm_if t1 t2 t3) T.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(* *** Examples *)
(** *** 例 *)
Example typing_example_1 :
has_type empty (tm_abs a ty_Bool (tm_var a)) (ty_arrow ty_Bool ty_Bool).
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(* Note that since we added the has_type constructors to the
hints database, auto can actually solve this one immediately.
*)
(** has_typeコンストラクタをヒントデータベースに追加したことから、
これを auto は直接解くことができることに注意します。*)
Example typing_example_1' :
has_type empty (tm_abs a ty_Bool (tm_var a)) (ty_arrow ty_Bool ty_Bool).
Proof. auto. Qed.
Hint Unfold beq_id beq_nat extend.
(* Written informally, the next one is:
[[
empty |- \a:A. \b:A->A. b (b a))
: A -> (A->A) -> A.
]]
*)
(** 非形式的に書くと
[[
empty |- \a:A. \b:A->A. b (b a))
: A -> (A->A) -> A.
]]
となるものが次の例です:
*)
Example typing_example_2 :
has_type empty
(tm_abs a ty_Bool
(tm_abs b (ty_arrow ty_Bool ty_Bool)
(tm_app (tm_var b) (tm_app (tm_var b) (tm_var a)))))
(ty_arrow ty_Bool (ty_arrow (ty_arrow ty_Bool ty_Bool) ty_Bool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(* **** Exercise: 2 stars, optional *)
(** **** 練習問題: ★★, optional *)
(* Prove the same result without using [auto], [eauto], or
[eapply]. *)
(** [auto]、[eauto]、[eapply] を使わずに同じ結果を証明しなさい。*)
Example typing_example_2_full :
has_type empty
(tm_abs a ty_Bool
(tm_abs b (ty_arrow ty_Bool ty_Bool)
(tm_app (tm_var b) (tm_app (tm_var b) (tm_var a)))))
(ty_arrow ty_Bool (ty_arrow (ty_arrow ty_Bool ty_Bool) ty_Bool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars (typing_example_3) *)
(** **** 練習問題: ★★ (typing_example_3) *)
(* Formally prove the following typing derivation holds:
[[
empty |- (\a:Bool->B. \b:Bool->Bool. \c:Bool.
b (a c))
: T.
]]
*)
(** 次の型付けが成立することを形式的に証明しなさい:
[[
empty |- (\a:Bool->B. \b:Bool->Bool. \c:Bool.
b (a c))
: T.
]]
*)
Example typing_example_3 :
exists T,
has_type empty
(tm_abs a (ty_arrow ty_Bool ty_Bool)
(tm_abs b (ty_arrow ty_Bool ty_Bool)
(tm_abs c ty_Bool
(tm_app (tm_var b) (tm_app (tm_var a) (tm_var c))))))
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\a:Bool. \b:Bool, a b] -- i.e.,
[[
~ exists T,
empty |- (\a:Bool. \b:Bool, a b) : T.
]]
*)
(** 項が「型付けできない」ことを証明することもできます。
例えば [\a:Bool. \b:Bool, a b] に型をつける型付けが存在しないこと、
つまり、
[[
~ exists T,
empty |- (\a:Bool. \b:Bool, a b) : T.
]]
を形式的にチェックしましょう。
*)
Example typing_nonexample_1 :
~ exists T,
has_type empty
(tm_abs a ty_Bool
(tm_abs b ty_Bool
(tm_app (tm_var a) (tm_var b))))
T.
Proof.
intros C. destruct C.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(* **** Exercise: 3 stars (typing_nonexample_3) *)
(** **** 練習問題: ★★★ (typing_nonexample_3) *)
(* Another nonexample:
[[
~ (exists S, exists T,
empty |- (\a:S. a a) : T).
]]
*)
(** 別の型を持たない例:
[[
~ (exists S, exists T,
empty |- (\a:S. a a) : T).
]]
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
has_type empty
(tm_abs a S
(tm_app (tm_var a) (tm_var a)))
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star (typing_statements) *)
(** **** 練習問題: ★ (typing_statements) *)
(* Which of the following propositions are provable?
- [b:Bool |- \a:Bool.a : Bool->Bool]
- [exists T, empty |- (\b:Bool->Bool. \a:Bool. b a) : T]
- [exists T, empty |- (\b:Bool->Bool. \a:Bool. a b) : T]
- [exists S, a:S |- (\b:Bool->Bool. b) a : S]
- [exists S, exists T, a:S |- (a a a) : T]
[]
*)
(** 以下のうち証明できるのものを挙げなさい。
- [b:Bool |- \a:Bool.a : Bool->Bool]
- [exists T, empty |- (\b:Bool->Bool. \a:Bool. b a) : T]
- [exists T, empty |- (\b:Bool->Bool. \a:Bool. a b) : T]
- [exists S, a:S |- (\b:Bool->Bool. b) a : S]
- [exists S, exists T, a:S |- (a a a) : T]
[]
*)
(* **** Exercise: 1 star, optional (more_typing_statements) *)
(** **** 練習問題: ★, optional (more_typing_statements) *)
(* Which of the following propositions are provable? For the
ones that are, give witnesses for the existentially bound
variables.
- [exists T, empty |- (\b:B->B->B. \a:B, b a) : T]
- [exists T, empty |- (\a:A->B, \b:B-->C, \c:A, b (a c)):T]
- [exists S, exists U, exists T, a:S, b:U |- \c:A. a (b c) : T]
- [exists S, exists T, a:S |- \b:A. a (a b) : T]
- [exists S, exists U, exists T, a:S |- a (\c:U. c a) : T]
[]
*)
(** 以下の命題のうち証明できるものを挙げなさい。証明できるものについては、
存在限量された変数に入る具体的な値を示しなさい。
- [exists T, empty |- (\b:B->B->B. \a:B, b a) : T]
- [exists T, empty |- (\a:A->B, \b:B-->C, \c:A, b (a c)):T]
- [exists S, exists U, exists T, a:S, b:U |- \c:A. a (b c) : T]
- [exists S, exists T, a:S |- \b:A. a (a b) : T]
- [exists S, exists U, exists T, a:S |- a (\c:U. c a) : T]
[]
*)
(* ###################################################################### *)
(* ** Properties *)
(** ** 性質 *)
(* ###################################################################### *)
(* *** Free Occurrences *)
(** *** 自由な出現 *)
(* A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
(** 変数[x]が項 t に自由に出現する(_appears free in_ a term _t_)とは、
[t]が[x]の出現を含み、その出現が[x]のラベルが付けられた関数抽象のスコープ内にないことです。
例えば:
- [\x:T->U. x y] において[y]は自由に現れますが[x]はそうではありません。
- [(\x:T->U. x y) x] においては[x]と[y]はともに自由に現れます。
- [\x:T->U. \y:T. x y] においては自由に現れる変数はありません。*)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tm_var x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_app t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_app t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tm_abs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tm_if t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(* A term in which no variables appear free is said to be _closed_. *)
(** 自由に現れる変数を持たない項を「閉じている」(_closed_)と言います。 *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(* *** Substitution *)
(** *** 置換 *)
(* We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
(** 最初に、自由変数と型付けコンテキストを結び付ける技術的な補題が必要になります。
変数[x]が項[t]に自由に現れ、[t]がコンテキスト[Gamma]で型付けされるならば、
[Gamma]は[x]に型を付けなければなりません。*)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
(* _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
(** 「証明」: [x]が[t]に自由に現れることの証明についての帰納法によって、
すべてのコンテキスト[Gamma]について、
[t]が[Gamma]のもとで型付けされるならば[Gamma]は[x]に型をつけることを示す。
- 最後の規則が [afi_var] の場合、[t = x] である。そして、[t]が[Gamma]
で型付けされるという仮定から、そのまま、[Gamma]で[x]に型付けされることが言える。
- 最後の規則が [afi_app1] の場合、[t = t1 t2] で[x]は[t1]に自由に出現する。
[t]が[Gamma]のもとで型付けされることから、型付け規則から[t1]も型付けされることになる。
従って帰納仮定より[Gamma]は[x]に型を付ける。
- 他のほとんどの場合も同様である。[x]が[t]の部分項に自由に現れ、
[t]が[Gamma]で片付けされることから、[x]が出現している[t]の部分項は同様に[Gamma]
で型付けされる。従って帰納仮定より求めるべき結果が得られる。
- 残るのは、最後の規則が [afi_abs] の場合だけである。この場合、
[t = \y:T11.t12] で[x]は[t12]に自由に現れる。
また[x]は[y]と異なっている。前の場合との違いは、
[t]は[Gamma]のもとで型付けされているが、
その本体[t12]は [(Gamma, y:T11)] のもとで型付けされているという点である。
このため、帰納仮定は、拡張されたコンテキスト [(Gamma, y:T11)] で[x]
に型付けされる、という主張になる。
[Gamma]のもとで[x]に型が付けられるという結論を得るため、
[x]と[y]が異なっているという点に注意して、補題[extend_neq]を使う。*)
Proof.
intros. generalize dependent Gamma. generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
apply not_eq_beq_id_false in H.
rewrite extend_neq in H7; assumption.
Qed.
(* Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
(** 次に、空コンテキストで型付けされる任意の項は閉じている(自由変数を持たない)、
という事実を必要とします。*)
(* **** Exercise: 2 stars (typable_empty__closed) *)
(** **** 練習問題: ★★ (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
(** しばしば、証明 [Gamma |- t : T] があるとき、コンテキスト[Gamma]
を別のコンテキスト[Gamma']に置換する必要が出てきます。
これはどのような場合に安全でしょうか？
直観的には、[t]に自由に現れるすべての変数について、[Gamma']が
[Gamma]と同じ型を割当てることが少なくとも必要です。
実際、この条件だけが必要になります。*)
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
(* _Proof_: By induction on a derivation of [Gamma |- t : T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t : T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 : T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' |- \y:T11. t12 :
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 :
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 : T2 -> T] and [Gamma |- t2 : T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
(** 「証明」: [Gamma |- t : T] の導出についての帰納法を使う。
- 導出の最後の規則が[T_Var]のとき、[t = x] かつ [Gamma x = T] である。
仮定から [Gamma' x = T] であるから、[T_Var] より [Gamma' |- t : T] となる。
- 最後の規則が [T_Abs] のとき、[t = \y:T11. t12] かつ [T = T11 -> T12]
かつ [Gamma, y:T11 |- t12 : T12] である。
帰納法の仮定は、任意のコンテキスト[Gamma'']について、
もし [Gamma, y:T11] と [Gamma''] が [t12]
内のすべての自由変数に同じ型を割り当てるならば、
[t12] は [Gamma''] のもとで型[T12]を持つ、である。
[Gamma']を、[t]内の自由変数について[Gamma]
と同じ割当てをするコンテキストとする。
示すべきことは [Gamma' |- \y:T11. t12 : T11 -> T12] である。
[T_Abs] より、[Gamma', y:T11 |- t12 : T12] を示せば十分である。
帰納仮定(ただし [Gamma'' = Gamma', y:T11] とする)より、
[Gamma, y:T11] と [Gamma', y:T11] が
[t12]内に自由に現れるすべての変数について割当てが一致することを示せば十分である。
[t12]に自由に出現する任意の変数は[y]であるか、それ以外の変数かである。
[Gamma, y:T11] と [Gamma', y:T11] は明らかに[y]については一致する。
それ以外の場合、[t12]に自由に出現する[y]以外の任意の変数は
[t = \y:T11. t12] にも自由に現れることに注意すると、[Gamma] と [Gamma']
がそのような変数について割当てが一致するという仮定より、
[Gamma, y:T11] と [Gamma', y:T11] も一致する。
- 最後の規則が [T_App] の場合、[t = t1 t2] かつ [Gamma |- t1 : T2 -> T]
かつ [Gamma |- t2 : T2] である。
帰納法の仮定の1つは、すべてのコンテキスト[Gamma']について、
[Gamma']と[Gamma]が[t1]のすべての自由変数について同じ割当てをするならば、
[Gamma']のもとで[t1]は型 [T2 -> T] を持つ、となる。
[t2]についても同様の帰納仮定がある。
証明すべきことは、[Gamma']が[Gamma]と [t1 t2]
のすべての自由変数について同一の割当てをするという仮定の上で、
[Gamma']のもとでも [t1 t2] が型[T]を持つ、ということである。
[T_App]より、[t1] と [t2] がそれぞれ
[Gamma']と[Gamma]のもとで同じ型を持つことを示せば十分である。
しかし、[t1]のすべての自由変数は [t1 t2] でも自由変数であり、
[t2]の自由変数についても同様である。ゆえに、2つの帰納仮定から求める結果が得られる。
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x0 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. remember (beq_id x x0) as e. destruct e...
Case "T_App".
apply T_App with T11...
Qed.
(* Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** ついに、簡約が型を保存することの証明の概念的な核心です。
つまり、「置換」が型を保存することを調べます。
非形式的には、置換補題(_Substitution Lemma_)と呼ばれる補題は次のことを主張します:
項[t]が自由変数[x]を持ち、[x]が型[U]を持つという仮定のもとで[t]に型[T]が付けられるとする。
また、別の項[v]について、[v]が型[U]を持つことが示されるとする。このとき、
[v]は[t]の型付けに関する[x]についての上述の仮定を満たすことから、[t]におけるそれぞれの
[x]の出現を[v]で置換することはできるはずであり、
その置換によって型が[T]のままである新しい項を得る。*)
(* (訳注：冒頭の "Formally" は "Informally" の間違いと文脈から判断。) *)
(* _Lemma_: If [Gamma,x:U |- t : T] and [|- v : U], then [Gamma |-
[v/x]t : T]. *)
(** 「補題」: もし [Gamma,x:U |- t : T] かつ [|- v : U] ならば [Gamma |-
[v/x]t : T]. *)
Lemma substitution_preserves_typing : forall Gamma x U v t T,
has_type (extend Gamma x U) t T ->
has_type empty v U ->
has_type Gamma (subst v x t) T.
(* One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma |- v :
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T-Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U |- t : T] and [|- v : U], then [Gamma |-
[v/x]t : T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x : T] we
conclude that [U = T]. We must show that [[v/x]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 : T']
and [|- v : U], then [Gamma' |- [v/x]t12 : T']. In
particular, if [Gamma,y:T11,x:U |- t12 : T12] and [|- v : U],
then [Gamma,y:T11 |- [v/x]t12 : T12]. There are again two
cases to consider, depending on whether [x] and [y] are the
same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[v/x]t = t], so we just need to show [Gamma |-
t : T]. But we know [Gamma,x:U |- t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma |- t : T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 :
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
|- t12 : T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 |- [v/x]t12 :
T12]. By [T_Abs], [Gamma |- \y:T11. [v/x]t12 : T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma |- \y:T11. [v/x]t12 : T11->T12], as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[has_type (extend Gamma x U) t T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
(** 補題の主張について技術的に巧妙な点の1つは、[v]に型[U]を割当てるのが
「空」コンテキストであることです。言い換えると、[v]が閉じていると仮定しています。
この仮定は[T_Abs]の場合の証明を
(この場面でとりうる別の仮定である [Gamma |- v : U] を仮定するのに比べて)
大幅に簡単にします。
なぜなら、コンテキスト不変補題(the context invariance lemma)が、
どんなコンテキストでも[v]が型[U]を持つことを示すからです。
[v]内の自由変数が
[T-Abs]によってコンテキストに導入された変数と衝突することを心配する必要はありません。
「証明」: [t]についての帰納法によって、すべての [T] と [Gamma] について
[Gamma,x:U |- t : T] かつ [|- v : U] ならば、[Gamma |- [v/x]t : T]
であることを証明する。
- [t]が変数のとき、[t]が[x]であるか否かによって2つの場合がある。
- [t = x] の場合、[Gamma, x:U |- x : T] という事実から、
[U = T] になる。
ここで示すべきことは、空コンテキストのもとで[v]が型 [U = T] という仮定の上で、
[Gamma]のもとで [[v/x]x = v] が型[T]を持つことである。
これは、コンテキスト不変補題、
つまり、閉じた項が空コンテキストのもとで型[T]を持つならば、
その項は任意のコンテキストのもとで型[T]を持つ、ということから得られる。
- [t]が[x]以外の変数[y]である場合、[y]の型は[Gamma,x:U]のもとでも
[Gamma]のもとでも変わらないということに注意するだけでよい。
- [t]が関数抽象 [\y:T11. t12] のとき、帰納仮定から、すべての[Gamma']と[T']について、
[Gamma',x:U |- t12 : T'] かつ [|- v : U] ならば [Gamma' |- [v/x]t12 : T']
となる。
特に [Gamma,y:T11,x:U |- t12 : T12] かつ [|- v : U] ならば
[Gamma,y:T11 |- [v/x]t12 : T12] となる。
[x]と[y]が同じ変数か否かでまた2つの場合がある。
最初に [x = y] とすると、置換の定義から [[v/x]t = t] である。
これから [Gamma |- t : T] を示すだけで良い。しかし、[Gamma,x:U |- t : T]
であって、[\y:T11. t12]に[y]は自由に出現することはないから、
コンテキスト不変補題から [Gamma |- t : T] となる。
次に [x <> y] とする。型付け関係の反転から [Gamma,x:U,y:T11 |- t12 :
T12] であり、これとコンテキスト不変補題から [Gamma,y:T11,x:U |- t12 : T12]
となる。これから帰納仮定を使って、[Gamma,y:T11 |- [v/x]t12 : T12] が得られる。
[T_Abs]から [Gamma |- \y:T11. [v/x]t12 : T11->T12] となり、
置換の定義から([x <> y] に注意すると)求める
[Gamma |- \y:T11. [v/x]t12 : T11->T12] が得られる。
- [t] が関数適用 [t1 t2] のときは、結果は置換の定義と帰納法の仮定から直ぐに
得られる。
- 他の場合は、関数適用の場合と同様である。
別の技術的な注: この証明は、
型の導出についての帰納法ではなく項についての帰納法を使うことが議論をより簡単にするという、
珍しいものです。この理由は、仮定 [has_type (extend Gamma x U) t T]
がある意味で完全に一般化されていないからです。
ある意味というのは、型関係の1つの「スロット」、つまりコンテキストが、
単に1つの変数ではないということです。
このことにより、Coq がもともと持っている帰納法のタクティックでは必要な帰納法の仮定が導かれません。
これを回避することは可能ですが、そのために必要な一般化はちょっとトリッキーです。
これに対して項[t]は完全に一般化されています。*)
Proof with eauto.
intros Gamma x U v t T Ht Hv.
generalize dependent Gamma. generalize dependent T.
tm_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tm_var".
rename i into y. remember (beq_id x y) as e. destruct e.
SCase "x=y".
apply beq_id_eq in Heqe. subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tm_abs".
rename i into y. apply T_Abs.
remember (beq_id x y) as e. destruct e.
SCase "x=y".
eapply context_invariance...
apply beq_id_eq in Heqe. subst.
intros x Hafi. unfold extend.
destruct (beq_id y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
remember (beq_id y z) as e0. destruct e0...
apply beq_id_eq in Heqe0. subst.
rewrite <- Heqe...
Qed.
(* The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [v/x] t ] -- the result is the same either
way. *)
(** 置換補題は一種の「交換性」("commutation" property)と見なせます。
直観的には、置換と型付けはどの順でやってもよいということを主張しています。
(適切なコンテキストのもとで)
項[t]と[v]に個別に型付けをしてから置換によって両者を組合せても良いし、
置換を先にやって後から [ [v/x] t ] に型をつけることもできます。
どちらでも結果は同じです。*)
(* ###################################################################### *)
(* *** Preservation *)
(** *** 保存 *)
(* We now have the tools we need to prove _preservation_: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
(** さて、(型の)保存(_preservation_)を証明する道具立ては揃いました。
保存とは、閉じた項[t]が型[T]を持ち、[t']への評価ステップを持つならば、
[t']はまた型[T]を持つ閉じた項である、という性質です。
言い換えると、スモールステップ評価関係は型を保存するということです。
*)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
(* _Proof_: by induction on the derivation of [|- t : T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [subst t2 x t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
(** 「証明」: [|- t : T] の導出についての帰納法を使う。
- まず最後の規則が [T_Var]、[T_Abs]、[T_True]、[T_False]
である場合は外して良い。なぜなら、これらの場合、
[t]はステップを進むことができないからである。
- 導出の最後の規則が [T_App] のとき、[t = t1 t2] である。
このとき、[t1 t2] が [t'] にステップを進めたことを示すのに使われた規則について、
3つの場合が考えられる。
- [t1 t2] が[ST_App1]によってステップを進めた場合、
[t1]がステップを進めたものを[t1']とする。すると帰納仮定より
[t1']は[t1]と同じ型を持ち、したがって、[t1' t2] は [t1 t2] と同じ型を持つ。
- [ST_App2]の場合は同様である。
- [t1 t2] が[ST_AppAbs]によってステップを進めた場合、
[t1 = \x:T11.t12] であり、
[t1 t2] は [subst t2 x t12] にステップする。
すると置換が型を保存するという事実から求める結果となる。
- 導出の最後の規則が [T_If] のとき、[t = if t1 then t2 else t3] であり、
やはり[t]のステップについて3つの場合がある。
- [t]が[t2]または[t3]にステップした場合、結果は直ぐである。なぜなら
[t2]と[t3]は[t]と同じ型だからである。
- そうでない場合、[t]は[ST_If]でステップする。このとき、
帰納法の仮定から直接求める結果が得られる。
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [auto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(* **** Exercise: 2 stars, recommended (subject_expansion_stlc) *)
(** **** 練習問題: ★★, recommended (subject_expansion_stlc) *)
(* An exercise earlier in this file asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That
is, is it always the case that, if [t ==> t'] and [has_type
t' T], then [has_type t T]? If so, prove it. If not, give a
counter-example.
(* FILL IN HERE *)
[]
*)
(** このファイルの前の練習問題で、
算術式とブール式の簡単な言語についての主部展開性についてききました
(訳注:実際には Types_J.v内の練習問題)。
STLCでこの性質は成立するでしょうか？つまり、
[t ==> t'] かつ [has_type t' T] ならば [has_type t T]
ということが常に言えるでしょうか？
もしそうならば証明しなさい。そうでなければ、反例を挙げなさい。
(* FILL IN HERE *)
[]
*)
(* ###################################################################### *)
(* *** Progress *)
(** *** 進行 *)
(* Finally, the _progress_ theorem tells us that closed, well-typed
terms are never stuck: either a well-typed term is a value, or
else it can take an evaluation step.
*)
(** 最後に、
「進行」定理(the _progress_ theorem)は閉じた、
型が付けられる項は行き詰まらないことを示します。
つまり、型が付けられる項は、値であるか、または評価ステップを進むことができるか、どちらかです。
*)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
(* _Proof_: by induction on the derivation of [|- t : T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[|- t1 : T2 -> T] and [|- t2 : T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
is either a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
(** 「証明」: [|- t : T] の導出についての帰納法による。
- 導出の最後の規則は[T_Var]ではありえない。なぜなら、
空コンテキストにおいて変数には型付けできないからである。
- [T_True]、[T_False]、[T_Abs]の場合は自明である。
なぜなら、これらの場合 [t]は値だからである。
- 導出の最後の規則が[T_App]の場合、[t = t1 t2] であり、
[t1]および[t2]はどちらも空コンテキストで型付けされる。
特に型[T2]があって、[|- t1 : T2 -> T] かつ [|- t2 : T2] となる。
帰納法の仮定から、[t1]は値であるか、評価ステップを進むことができる。
- [t1]が値のとき、[t2]を考えると、
帰納仮定からさらに値である場合と評価ステップを進む場合がある。
- [t2]が値のとき、[t1]は値で関数型であるから、ラムダ抽象である。
ゆえに、[t1 t2] は [ST_AppAbs] でステップを進むことができる。
- そうでなければ、[t2]はステップを進むことができる。したがって
[ST_App2]で [t1 t2] もステップを進むことができる。
- [t1]がステップを進むことができるとき、[ST_App1] で [t1 t2]
もステップを進むことができる。
- 導出の最後の規則が[T_If]のとき、[t = if t1 then t2 else t3] で
[t1] は型[Bool]を持つ。帰納仮定より[t1]は値かステップを進むことができるかどちらかである。
- [t1]が値のとき、その型が[Bool]であることから[t1]は[true]または[false]である。
[true]ならば[t]は[t2]に進み、そうでなければ[t3]に進む。
- そうでないとき、[t1]はステップを進むことができる。したがって([ST_If]より)
[t]もステップを進むことができる。
*)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst Gamma...
Case "T_Var".
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
Case "T_App".
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is also a value".
(* Since [t1] is a value and has an arrow type, it
must be an abs. Sometimes this is proved separately
and called a "canonical forms" lemma. *)
inversion H; subst. exists (subst t2 x t)...
solve by inversion. solve by inversion.
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tm_app t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tm_app t1' t2)...
Case "T_If".
right. destruct IHHt1...
SCase "t1 is a value".
(* Since [t1] is a value of boolean type, it must
be true or false *)
inversion H; subst. solve by inversion.
SSCase "t1 = true". eauto.
SSCase "t1 = false". eauto.
SCase "t1 also steps".
destruct H as [t1' Hstp]. exists (tm_if t1' t2 t3)...
Qed.
(* **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** **** 練習問題: ★★★, optional (progress_from_term_ind) *)
(* Show that progress can also be proved by induction on terms
instead of types. *)
(** 型についての帰納法ではなく項についての帰納法でも進行の証明ができることを示しなさい。*)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
tm_cases (induction t) Case; intros T Ht; auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(* *** Uniqueness of Types *)
(** *** 型の一意性 *)
(* **** Exercise: 3 stars (types_unique) *)
(** **** 練習問題: ★★★ (types_unique) *)
(* Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** STLCの別の好ましい性質は、型が唯一であることです。
つまり、与えらえた項については(与えられたコンテキストで)
高々1つの型しか型付けされません。*)
(* Formalize this statement and prove it. *)
(** この主張を形式化し、証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(* ** Additional Exercises *)
(** ** さらなる練習問題 *)
(* **** Exercise: 1 star (progress_preservation_statement) *)
(** **** 練習問題: ★ (progress_preservation_statement) *)
(* Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(** なにも見ることなく、単純型付きラムダ計算の進行定理と保存定理を書き下しなさい。*)
(** [] *)
(* **** Exercise: 2 stars, optional (stlc_variation1) *)
(** **** 練習問題: ★★, optional (stlc_variation1) *)
(* Suppose we add the following new rule to the evaluation
relation of the STLC:
[[
| T_Strange : forall x t,
has_type empty (tm_abs x Bool t) Bool
]]
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinacy of [step]
- Progress
- Preservation
[]
*)
(** STLCの評価関係に次の新しい規則を加えたとします:
[[
| T_Strange : forall x t,
has_type empty (tm_abs x Bool t) Bool
]]
この規則を加えても真であるSTLCの性質は以下のうちどれでしょうか？
それぞれについて、「真のまま」または「偽に変わる」と書きなさい。
偽に変わるものについては、反例を挙げなさい。
- [step]の決定性
- 進行
- 保存
[]
*)
(* **** Exercise: 2 stars (stlc_variation2) *)
(** **** 練習問題: ★★ (stlc_variation2) *)
(* Suppose we remove the rule [ST_App1] from the [step]
relation. Which of the three properties in the previous
exercise become false in the absence of this rule? For each
that becomes false, give a counterexample.
[]
*)
(** [step]関係から[ST_App1]規則を除いたとします。
このとき前の練習問題の3つの性質のうち、偽になるものはどれでしょう？
偽になるものについては、反例を挙げなさい。
[]
*)
End STLC.
(* ###################################################################### *)
(* ###################################################################### *)
(* * Exercise: STLC with Arithmetic *)
(** * 練習問題: 算術を持つSTLC *)
(* To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
(** STLCが実際のプログラミング言語の核として機能することを見るため、
数値についての具体的な基本型と定数、いくつかの基本操作を追加しましょう。*)
Module STLCArith.
(* ###################################################################### *)
(* ** Syntax and Operational Semantics *)
(** ** 構文と操作的意味 *)
(* To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
(** 型について、自然数を基本型として加えます(そして簡潔さのためブール型を除きます)。 *)
Inductive ty : Type :=
| ty_arrow : ty -> ty -> ty
| ty_Nat : ty.
(* To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
(** 項について、自然数の定数、1つ前をとる関数、1つ後をとる関数、積算、ゼロか否かのテスト...
を加えます。 *)
Inductive tm : Type :=
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_nat : nat -> tm
| tm_succ : tm -> tm
| tm_pred : tm -> tm
| tm_mult : tm -> tm -> tm
| tm_if0 : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app"
| Case_aux c "tm_abs" | Case_aux c "tm_nat"
| Case_aux c "tm_succ" | Case_aux c "tm_pred"
| Case_aux c "tm_mult" | Case_aux c "tm_if0" ].
(* **** Exercise: 4 stars, recommended (STLCArith) *)
(** **** 練習問題: ★★★★, recommended (STLCArith) *)
(* Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties of the original STLC to deal
with the new syntactic forms. Make sure Coq accepts the whole file. *)
(** 算術を拡張したSTLCの定義と性質の形式化を完成させなさい。特に:
- STLCについてここまでやってきたこと(定義から進行定理まで)の全体をコピーして、
ファイルのこの部分にペーストしなさい。
- [subst]操作と[step]関係の定義を拡張して、算術の操作の適切な節を含むようにしなさい。
- オリジナルのSTLCの性質の証明を拡張して、新しい構文を扱うようにしなさい。
Coq がその証明を受理することを確認しなさい。*)
(* FILL IN HERE *)
(** [] *)
End STLCArith.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_TB_V
`define SKY130_FD_SC_LP__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The Branch Resolve module to resolve the branch instructions
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_branchslv(
// The BJP condition final result need to be resolved at ALU
input cmt_i_valid,
output cmt_i_ready,
input cmt_i_rv32,
input cmt_i_dret,// The dret instruction
input cmt_i_mret,// The ret instruction
input cmt_i_fencei,// The fencei instruction
input cmt_i_bjp,
input cmt_i_bjp_prdt,// The predicted ture/false
input cmt_i_bjp_rslv,// The resolved ture/false
input [`E203_PC_SIZE-1:0] cmt_i_pc,
input [`E203_XLEN-1:0] cmt_i_imm,// The resolved ture/false
input [`E203_PC_SIZE-1:0] csr_epc_r,
input [`E203_PC_SIZE-1:0] csr_dpc_r,
input nonalu_excpirq_flush_req_raw,
input brchmis_flush_ack,
output brchmis_flush_req,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op1,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] brchmis_flush_pc,
`endif//}
output cmt_mret_ena,
output cmt_dret_ena,
output cmt_fencei_ena,
input clk,
input rst_n
);
wire brchmis_flush_ack_pre;
wire brchmis_flush_req_pre;
assign brchmis_flush_req = brchmis_flush_req_pre & (~nonalu_excpirq_flush_req_raw);
assign brchmis_flush_ack_pre = brchmis_flush_ack & (~nonalu_excpirq_flush_req_raw);
// In Two stage impelmentation, several branch instructions are handled as below:
// * It is predicted at IFU, and target is handled in IFU. But
// we need to check if it is predicted correctly or not. If not,
// we need to flush the pipeline
// Note: the JUMP instrution will always jump, hence they will be
// both predicted and resolved as true
wire brchmis_need_flush = (
(cmt_i_bjp & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv))
// If it is a FenceI instruction, it is always Flush
| cmt_i_fencei
// If it is a RET instruction, it is always jump
| cmt_i_mret
// If it is a DRET instruction, it is always jump
| cmt_i_dret
);
wire cmt_i_is_branch = (
cmt_i_bjp
| cmt_i_fencei
| cmt_i_mret
| cmt_i_dret
);
assign brchmis_flush_req_pre = cmt_i_valid & brchmis_need_flush;
// * If it is a DRET instruction, the new target PC is DPC register
// * If it is a RET instruction, the new target PC is EPC register
// * If predicted as taken, but actually it is not taken, then
// The new target PC should caculated by PC+2/4
// * If predicted as not taken, but actually it is taken, then
// The new target PC should caculated by PC+offset
assign brchmis_flush_add_op1 = cmt_i_dret ? csr_dpc_r : cmt_i_mret ? csr_epc_r : cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_dret ? `E203_PC_SIZE'b0 : cmt_i_mret ? `E203_PC_SIZE'b0 :
(cmt_i_fencei | cmt_i_bjp_prdt) ? (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)
: cmt_i_imm[`E203_PC_SIZE-1:0];
`ifdef E203_TIMING_BOOST//}
// Replicated two adders here to trade area with timing
assign brchmis_flush_pc =
// The fenceI is also need to trigger the flush to its next instructions
(cmt_i_fencei | (cmt_i_bjp & cmt_i_bjp_prdt)) ? (cmt_i_pc + (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)) :
(cmt_i_bjp & (~cmt_i_bjp_prdt)) ? (cmt_i_pc + cmt_i_imm[`E203_PC_SIZE-1:0]) :
cmt_i_dret ? csr_dpc_r :
//cmt_i_mret ? csr_epc_r :
csr_epc_r ;// Last condition cmt_i_mret commented
// to save gatecount and timing
`endif//}
wire brchmis_flush_hsked = brchmis_flush_req & brchmis_flush_ack;
assign cmt_mret_ena = cmt_i_mret & brchmis_flush_hsked;
assign cmt_dret_ena = cmt_i_dret & brchmis_flush_hsked;
assign cmt_fencei_ena = cmt_i_fencei & brchmis_flush_hsked;
assign cmt_i_ready = (~cmt_i_is_branch) |
(
(brchmis_need_flush ? brchmis_flush_ack_pre : 1'b1)
// The Non-ALU flush will override the ALU flush
& (~nonalu_excpirq_flush_req_raw)
);
endmodule
|
// file: clk_divider_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_divider_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_divider_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
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// reasonably foreseeable or Xilinx had been advised of the
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.91
// \ \ Application: MIG
// / / Filename: phy_rddata_sync.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Synchronization of captured read data along with appropriately delayed
// valid signal (both in clk_rsync domain) to MC/PHY rdlvl logic clock (clk)
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_rddata_sync.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_rddata_sync.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_rddata_sync #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter nDQS_COL0 = 4, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 4, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 4, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 4, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 32'h03020100, // DQS grps in col #1
parameter DQS_LOC_COL1 = 32'h07060504, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0 // DQS grps in col #4
)
(
input clk,
input [3:0] clk_rsync,
input [3:0] rst_rsync,
// Captured data in resync clock domain
input [DQ_WIDTH-1:0] rd_data_rise0,
input [DQ_WIDTH-1:0] rd_data_fall0,
input [DQ_WIDTH-1:0] rd_data_rise1,
input [DQ_WIDTH-1:0] rd_data_fall1,
input [DQS_WIDTH-1:0] rd_dqs_rise0,
input [DQS_WIDTH-1:0] rd_dqs_fall0,
input [DQS_WIDTH-1:0] rd_dqs_rise1,
input [DQS_WIDTH-1:0] rd_dqs_fall1,
// Synchronized data/valid back to MC/PHY rdlvl logic
output reg [4*DQ_WIDTH-1:0] dfi_rddata,
output reg [4*DQS_WIDTH-1:0] dfi_rd_dqs
);
// Ensure nonzero width for certain buses to prevent syntax errors
// during compile in the event they are not used (e.g. buses that have to
// do with column #2 in a single column design never get used, although
// those buses still will get declared)
localparam COL0_VECT_WIDTH = (nDQS_COL0 > 0) ? nDQS_COL0 : 1;
localparam COL1_VECT_WIDTH = (nDQS_COL1 > 0) ? nDQS_COL1 : 1;
localparam COL2_VECT_WIDTH = (nDQS_COL2 > 0) ? nDQS_COL2 : 1;
localparam COL3_VECT_WIDTH = (nDQS_COL3 > 0) ? nDQS_COL3 : 1;
reg [4*DRAM_WIDTH*COL0_VECT_WIDTH-1:0] data_c0;
reg [4*DRAM_WIDTH*COL1_VECT_WIDTH-1:0] data_c1;
reg [4*DRAM_WIDTH*COL2_VECT_WIDTH-1:0] data_c2;
reg [4*DRAM_WIDTH*COL3_VECT_WIDTH-1:0] data_c3;
reg [DQ_WIDTH-1:0] data_fall0_sync;
reg [DQ_WIDTH-1:0] data_fall1_sync;
reg [DQ_WIDTH-1:0] data_rise0_sync;
reg [DQ_WIDTH-1:0] data_rise1_sync;
wire [4*DRAM_WIDTH*COL0_VECT_WIDTH-1:0] data_sync_c0;
wire [4*DRAM_WIDTH*COL1_VECT_WIDTH-1:0] data_sync_c1;
wire [4*DRAM_WIDTH*COL2_VECT_WIDTH-1:0] data_sync_c2;
wire [4*DRAM_WIDTH*COL3_VECT_WIDTH-1:0] data_sync_c3;
reg [4*COL0_VECT_WIDTH-1:0] dqs_c0;
reg [4*COL1_VECT_WIDTH-1:0] dqs_c1;
reg [4*COL2_VECT_WIDTH-1:0] dqs_c2;
reg [4*COL3_VECT_WIDTH-1:0] dqs_c3;
reg [DQS_WIDTH-1:0] dqs_fall0_sync;
reg [DQS_WIDTH-1:0] dqs_fall1_sync;
reg [DQS_WIDTH-1:0] dqs_rise0_sync;
reg [DQS_WIDTH-1:0] dqs_rise1_sync;
wire [4*COL0_VECT_WIDTH-1:0] dqs_sync_c0;
wire [4*COL1_VECT_WIDTH-1:0] dqs_sync_c1;
wire [4*COL2_VECT_WIDTH-1:0] dqs_sync_c2;
wire [4*COL3_VECT_WIDTH-1:0] dqs_sync_c3;
//***************************************************************************
// Synchronization of both data and active/valid signal from clk_rsync to
// clk domain
// NOTES:
// 1. For now, assume both rddata_valid0 and rddata_valid1 are driven at
// same time. PHY returns data aligned in this manner
// 2. Circular buffer implementation is preliminary (i.e. shortcuts have
// been taken!). Will later need some sort of calibration.
// - Substitute this with enhanced circular buffer design for
// release (5 deep design)
// 3. Up to 4 circular buffers are used, one for each CLK_RSYNC[x] domain.
// 4. RD_ACTIVE synchronized to CLK_RSYNC[0] circular buffer. This is
// TEMPORARY only. For release, do not need this - RD_ACTIVE will
//. remain totally in the
// A single circular buffer is used for the entire data bus. This will
// be an issue in H/W - will need to examine this based on clock
// frequency, and skew matching achievable in H/W.
//***************************************************************************
generate
genvar c0_i;
if (nDQS_COL0 > 0) begin: gen_c0
for (c0_i = 0; c0_i < nDQS_COL0; c0_i = c0_i + 1) begin: gen_loop_c0
// Steer data to circular buffer - merge FALL/RISE data into single bus
always @(rd_dqs_fall0 or rd_dqs_fall1 or
rd_dqs_rise0 or rd_dqs_rise1)
dqs_c0[4*(c0_i+1)-1-:4]
= {rd_dqs_fall1[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]],
rd_dqs_rise1[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]],
rd_dqs_fall0[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]],
rd_dqs_rise0[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]]};
always @(rd_data_rise0 or rd_data_rise1 or
rd_data_fall0 or rd_data_fall1)
data_c0[4*DRAM_WIDTH*(c0_i+1)-1-:4*DRAM_WIDTH]
= {rd_data_fall1[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])],
rd_data_rise1[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])],
rd_data_fall0[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])],
rd_data_rise0[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])]};
// Reassemble data from circular buffer
always @(dqs_sync_c0[4*c0_i] or
dqs_sync_c0[4*c0_i+1] or
dqs_sync_c0[4*c0_i+2] or
dqs_sync_c0[4*c0_i+3]) begin
dqs_fall1_sync[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]]
= dqs_sync_c0[4*c0_i+3];
dqs_rise1_sync[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]]
= dqs_sync_c0[4*c0_i+2];
dqs_fall0_sync[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]]
= dqs_sync_c0[4*c0_i+1];
dqs_rise0_sync[DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]]
= dqs_sync_c0[4*c0_i];
end
always @(data_sync_c0[4*DRAM_WIDTH*c0_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i] or
data_sync_c0[4*DRAM_WIDTH*c0_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+DRAM_WIDTH] or
data_sync_c0[4*DRAM_WIDTH*c0_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+2*DRAM_WIDTH] or
data_sync_c0[4*DRAM_WIDTH*c0_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+3*DRAM_WIDTH]) begin
data_fall1_sync[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])]
= data_sync_c0[4*DRAM_WIDTH*c0_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+3*DRAM_WIDTH];
data_rise1_sync[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])]
= data_sync_c0[4*DRAM_WIDTH*c0_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+2*DRAM_WIDTH];
data_fall0_sync[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])]
= data_sync_c0[4*DRAM_WIDTH*c0_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i+DRAM_WIDTH];
data_rise0_sync[DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL0[(8*(c0_i+1))-1:8*c0_i])]
= data_sync_c0[4*DRAM_WIDTH*c0_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c0_i];
end
end
circ_buffer #
(
.TCQ (TCQ),
.DATA_WIDTH ((4*nDQS_COL0)+(4*DRAM_WIDTH*nDQS_COL0)),
.BUF_DEPTH (6)
)
u_rddata_sync_c0
(
.rclk (clk),
.wclk (clk_rsync[0]),
.rst (rst_rsync[0]),
.wdata ({dqs_c0,data_c0}),
.rdata ({dqs_sync_c0,data_sync_c0})
);
end
endgenerate
generate
genvar c1_i;
if (nDQS_COL1 > 0) begin: gen_c1
for (c1_i = 0; c1_i < nDQS_COL1; c1_i = c1_i + 1) begin: gen_loop_c1
// Steer data to circular buffer - merge FALL/RISE data into single bus
always @(rd_dqs_fall0 or rd_dqs_fall1 or
rd_dqs_rise0 or rd_dqs_rise1)
dqs_c1[4*(c1_i+1)-1-:4]
= {rd_dqs_fall1[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]],
rd_dqs_rise1[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]],
rd_dqs_fall0[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]],
rd_dqs_rise0[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]]};
always @(rd_data_rise0 or rd_data_rise1 or
rd_data_fall0 or rd_data_fall1)
data_c1[4*DRAM_WIDTH*(c1_i+1)-1-:4*DRAM_WIDTH]
= {rd_data_fall1[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])],
rd_data_rise1[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])],
rd_data_fall0[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])],
rd_data_rise0[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])]};
// Reassemble data from circular buffer
always @(dqs_sync_c1[4*c1_i] or
dqs_sync_c1[4*c1_i+1] or
dqs_sync_c1[4*c1_i+2] or
dqs_sync_c1[4*c1_i+3] ) begin
dqs_fall1_sync[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]]
= dqs_sync_c1[4*c1_i+3];
dqs_rise1_sync[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]]
= dqs_sync_c1[4*c1_i+2];
dqs_fall0_sync[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]]
= dqs_sync_c1[4*c1_i+1];
dqs_rise0_sync[DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]]
= dqs_sync_c1[4*c1_i];
end
always @(data_sync_c1[4*DRAM_WIDTH*c1_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i] or
data_sync_c1[4*DRAM_WIDTH*c1_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+DRAM_WIDTH] or
data_sync_c1[4*DRAM_WIDTH*c1_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+2*DRAM_WIDTH] or
data_sync_c1[4*DRAM_WIDTH*c1_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+3*DRAM_WIDTH]) begin
data_fall1_sync[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])]
= data_sync_c1[4*DRAM_WIDTH*c1_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+3*DRAM_WIDTH];
data_rise1_sync[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])]
= data_sync_c1[4*DRAM_WIDTH*c1_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+2*DRAM_WIDTH];
data_fall0_sync[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])]
= data_sync_c1[4*DRAM_WIDTH*c1_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i+DRAM_WIDTH];
data_rise0_sync[DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL1[(8*(c1_i+1))-1:8*c1_i])]
= data_sync_c1[4*DRAM_WIDTH*c1_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c1_i];
end
end
circ_buffer #
(
.TCQ (TCQ),
.DATA_WIDTH ((4*nDQS_COL1)+(4*DRAM_WIDTH*nDQS_COL1)),
.BUF_DEPTH (6)
)
u_rddata_sync_c1
(
.rclk (clk),
.wclk (clk_rsync[1]),
.rst (rst_rsync[1]),
.wdata ({dqs_c1,data_c1}),
.rdata ({dqs_sync_c1,data_sync_c1})
);
end
endgenerate
generate
genvar c2_i;
if (nDQS_COL2 > 0) begin: gen_c2
for (c2_i = 0; c2_i < nDQS_COL2; c2_i = c2_i + 1) begin: gen_loop_c2
// Steer data to circular buffer - merge FALL/RISE data into single bus
always @(rd_dqs_fall0 or rd_dqs_fall1 or
rd_dqs_rise0 or rd_dqs_rise1)
dqs_c2[4*(c2_i+1)-1-:4]
= {rd_dqs_fall1[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]],
rd_dqs_rise1[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]],
rd_dqs_fall0[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]],
rd_dqs_rise0[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]]};
always @(rd_data_fall0 or rd_data_fall1 or
rd_data_rise0 or rd_data_rise1)
data_c2[4*DRAM_WIDTH*(c2_i+1)-1-:4*DRAM_WIDTH]
= {rd_data_fall1[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])],
rd_data_rise1[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])],
rd_data_fall0[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])],
rd_data_rise0[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])]};
// Reassemble data from circular buffer
always @(dqs_sync_c2[4*c2_i] or
dqs_sync_c2[4*c2_i+1] or
dqs_sync_c2[4*c2_i+2] or
dqs_sync_c2[4*c2_i+3] ) begin
dqs_fall1_sync[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]]
= dqs_sync_c2[4*c2_i+3];
dqs_rise1_sync[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]]
= dqs_sync_c2[4*c2_i+2];
dqs_fall0_sync[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]]
= dqs_sync_c2[4*c2_i+1];
dqs_rise0_sync[DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]]
= dqs_sync_c2[4*c2_i];
end
always @(data_sync_c2[4*DRAM_WIDTH*c2_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i] or
data_sync_c2[4*DRAM_WIDTH*c2_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+DRAM_WIDTH] or
data_sync_c2[4*DRAM_WIDTH*c2_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+2*DRAM_WIDTH] or
data_sync_c2[4*DRAM_WIDTH*c2_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+3*DRAM_WIDTH]) begin
data_fall1_sync[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])]
= data_sync_c2[4*DRAM_WIDTH*c2_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+3*DRAM_WIDTH];
data_rise1_sync[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])]
= data_sync_c2[4*DRAM_WIDTH*c2_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+2*DRAM_WIDTH];
data_fall0_sync[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])]
= data_sync_c2[4*DRAM_WIDTH*c2_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i+DRAM_WIDTH];
data_rise0_sync[DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL2[(8*(c2_i+1))-1:8*c2_i])]
= data_sync_c2[4*DRAM_WIDTH*c2_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c2_i];
end
end
circ_buffer #
(
.TCQ (TCQ),
.DATA_WIDTH ((4*nDQS_COL2)+(4*DRAM_WIDTH*nDQS_COL2)),
.BUF_DEPTH (6)
)
u_rddata_sync_c2
(
.rclk (clk),
.wclk (clk_rsync[2]),
.rst (rst_rsync[2]),
.wdata ({dqs_c2,data_c2}),
.rdata ({dqs_sync_c2,data_sync_c2})
);
end
endgenerate
generate
genvar c3_i;
if (nDQS_COL3 > 0) begin: gen_c3
for (c3_i = 0; c3_i < nDQS_COL3; c3_i = c3_i + 1) begin: gen_loop_c3
// Steer data to circular buffer - merge FALL/RISE data into
// single bus
always @(rd_dqs_fall0 or rd_dqs_fall1 or
rd_dqs_rise0 or rd_dqs_rise1)
dqs_c3[4*(c3_i+1)-1-:4]
= {rd_dqs_fall1[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]],
rd_dqs_rise1[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]],
rd_dqs_fall0[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]],
rd_dqs_rise0[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]]};
always @(rd_data_fall0 or rd_data_fall1 or
rd_data_rise0 or rd_data_rise1)
data_c3[4*DRAM_WIDTH*(c3_i+1)-1-:4*DRAM_WIDTH]
= {rd_data_fall1[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])],
rd_data_rise1[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])],
rd_data_fall0[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])],
rd_data_rise0[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])]};
// Reassemble data from circular buffer
always @(dqs_sync_c3[4*c3_i] or
dqs_sync_c3[4*c3_i+1] or
dqs_sync_c3[4*c3_i+2] or
dqs_sync_c3[4*c3_i+3]) begin
dqs_fall1_sync[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]]
= dqs_sync_c3[4*c3_i+3];
dqs_rise1_sync[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]]
= dqs_sync_c3[4*c3_i+2];
dqs_fall0_sync[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]]
= dqs_sync_c3[4*c3_i+1];
dqs_rise0_sync[DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]]
= dqs_sync_c3[4*c3_i];
end
always @(data_sync_c3[4*DRAM_WIDTH*c3_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i] or
data_sync_c3[4*DRAM_WIDTH*c3_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+DRAM_WIDTH] or
data_sync_c3[4*DRAM_WIDTH*c3_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+2*DRAM_WIDTH] or
data_sync_c3[4*DRAM_WIDTH*c3_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+3*DRAM_WIDTH]) begin
data_fall1_sync[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])]
= data_sync_c3[4*DRAM_WIDTH*c3_i+4*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+3*DRAM_WIDTH];
data_rise1_sync[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])]
= data_sync_c3[4*DRAM_WIDTH*c3_i+3*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+2*DRAM_WIDTH];
data_fall0_sync[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])]
= data_sync_c3[4*DRAM_WIDTH*c3_i+2*DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i+DRAM_WIDTH];
data_rise0_sync[DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i]+1)-1:
DRAM_WIDTH*(DQS_LOC_COL3[(8*(c3_i+1))-1:8*c3_i])]
= data_sync_c3[4*DRAM_WIDTH*c3_i+DRAM_WIDTH-1:4*DRAM_WIDTH*c3_i];
end
end
circ_buffer #
(
.TCQ (TCQ),
.DATA_WIDTH ((4*nDQS_COL3)+(4*DRAM_WIDTH*nDQS_COL3)),
.BUF_DEPTH (6)
)
u_rddata_sync_c3
(
.rclk (clk),
.wclk (clk_rsync[3]),
.rst (rst_rsync[3]),
.wdata ({dqs_c3,data_c3}),
.rdata ({dqs_sync_c3,data_sync_c3})
);
end
endgenerate
//***************************************************************************
// Pipeline stage only required if timing not met otherwise
always @(posedge clk) begin
dfi_rddata <= #TCQ {data_fall1_sync,
data_rise1_sync,
data_fall0_sync,
data_rise0_sync};
dfi_rd_dqs <= #TCQ {dqs_fall1_sync,
dqs_rise1_sync,
dqs_fall0_sync,
dqs_rise0_sync};
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:23 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_stub.v
// Design : system_vga_sync_ref_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_0_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
module regblock(
readdata,
clk,
rst,
readregsel,
writeregsel,
writedata,
write
);
parameter BITWIDTH = 11;
input clk, rst;
input [5:0] readregsel;
input [5:0] writeregsel;
input [(BITWIDTH-1):0] writedata;
input write;
output [(BITWIDTH-1):0] readdata;
wire write_dff;
wire [(BITWIDTH-1):0] data0,data_flop0;
wire [(BITWIDTH-1):0] data1,data_flop1;
wire [(BITWIDTH-1):0] data2,data_flop2;
wire [(BITWIDTH-1):0] data3,data_flop3;
wire [(BITWIDTH-1):0] data4,data_flop4;
wire [(BITWIDTH-1):0] data5,data_flop5;
wire [(BITWIDTH-1):0] data6,data_flop6;
wire [(BITWIDTH-1):0] data7,data_flop7;
wire [(BITWIDTH-1):0] data8,data_flop8;
wire [(BITWIDTH-1):0] data9,data_flop9;
wire [(BITWIDTH-1):0] data10,data_flop10;
wire [(BITWIDTH-1):0] data11,data_flop11;
wire [(BITWIDTH-1):0] data12,data_flop12;
wire [(BITWIDTH-1):0] data13,data_flop13;
wire [(BITWIDTH-1):0] data14,data_flop14;
wire [(BITWIDTH-1):0] data15,data_flop15;
wire [(BITWIDTH-1):0] data16,data_flop16;
wire [(BITWIDTH-1):0] data17,data_flop17;
wire [(BITWIDTH-1):0] data18,data_flop18;
wire [(BITWIDTH-1):0] data19,data_flop19;
wire [(BITWIDTH-1):0] data20,data_flop20;
wire [(BITWIDTH-1):0] data21,data_flop21;
wire [(BITWIDTH-1):0] data22,data_flop22;
wire [(BITWIDTH-1):0] data23,data_flop23;
wire [(BITWIDTH-1):0] data24,data_flop24;
wire [(BITWIDTH-1):0] data25,data_flop25;
wire [(BITWIDTH-1):0] data26,data_flop26;
wire [(BITWIDTH-1):0] data27,data_flop27;
wire [(BITWIDTH-1):0] data28,data_flop28;
wire [(BITWIDTH-1):0] data29,data_flop29;
wire [(BITWIDTH-1):0] data30,data_flop30;
wire [(BITWIDTH-1):0] data31,data_flop31;
wire [(BITWIDTH-1):0] data32,data_flop32;
wire [(BITWIDTH-1):0] data33,data_flop33;
wire [(BITWIDTH-1):0] data34,data_flop34;
wire [(BITWIDTH-1):0] data35,data_flop35;
wire [(BITWIDTH-1):0] data36,data_flop36;
wire [(BITWIDTH-1):0] data37,data_flop37;
wire [(BITWIDTH-1):0] data38,data_flop38;
wire [(BITWIDTH-1):0] data39,data_flop39;
assign write_dff = 1'b1;
regfile #(BITWIDTH) r_file0 (data0,write_dff,data_flop0,clk,rst);
regfile #(BITWIDTH) r_file1 (data1,write_dff,data_flop1,clk,rst);
regfile #(BITWIDTH) r_file2 (data2,write_dff,data_flop2,clk,rst);
regfile #(BITWIDTH) r_file3 (data3,write_dff,data_flop3,clk,rst);
regfile #(BITWIDTH) r_file4 (data4,write_dff,data_flop4,clk,rst);
regfile #(BITWIDTH) r_file5 (data5,write_dff,data_flop5,clk,rst);
regfile #(BITWIDTH) r_file6 (data6,write_dff,data_flop6,clk,rst);
regfile #(BITWIDTH) r_file7 (data7,write_dff,data_flop7,clk,rst);
regfile #(BITWIDTH) r_file8 (data8,write_dff,data_flop8,clk,rst);
regfile #(BITWIDTH) r_file9 (data9,write_dff,data_flop9,clk,rst);
regfile #(BITWIDTH) r_file10 (data10,write_dff,data_flop10,clk,rst);
regfile #(BITWIDTH) r_file11 (data11,write_dff,data_flop11,clk,rst);
regfile #(BITWIDTH) r_file12 (data12,write_dff,data_flop12,clk,rst);
regfile #(BITWIDTH) r_file13 (data13,write_dff,data_flop13,clk,rst);
regfile #(BITWIDTH) r_file14 (data14,write_dff,data_flop14,clk,rst);
regfile #(BITWIDTH) r_file15 (data15,write_dff,data_flop15,clk,rst);
regfile #(BITWIDTH) r_file16 (data16,write_dff,data_flop16,clk,rst);
regfile #(BITWIDTH) r_file17 (data17,write_dff,data_flop17,clk,rst);
regfile #(BITWIDTH) r_file18 (data18,write_dff,data_flop18,clk,rst);
regfile #(BITWIDTH) r_file19 (data19,write_dff,data_flop19,clk,rst);
regfile #(BITWIDTH) r_file20 (data20,write_dff,data_flop20,clk,rst);
regfile #(BITWIDTH) r_file21 (data21,write_dff,data_flop21,clk,rst);
regfile #(BITWIDTH) r_file22 (data22,write_dff,data_flop22,clk,rst);
regfile #(BITWIDTH) r_file23 (data23,write_dff,data_flop23,clk,rst);
regfile #(BITWIDTH) r_file24 (data24,write_dff,data_flop24,clk,rst);
regfile #(BITWIDTH) r_file25 (data25,write_dff,data_flop25,clk,rst);
regfile #(BITWIDTH) r_file26 (data26,write_dff,data_flop26,clk,rst);
regfile #(BITWIDTH) r_file27 (data27,write_dff,data_flop27,clk,rst);
regfile #(BITWIDTH) r_file28 (data28,write_dff,data_flop28,clk,rst);
regfile #(BITWIDTH) r_file29 (data29,write_dff,data_flop29,clk,rst);
regfile #(BITWIDTH) r_file30 (data30,write_dff,data_flop30,clk,rst);
regfile #(BITWIDTH) r_file31 (data31,write_dff,data_flop31,clk,rst);
regfile #(BITWIDTH) r_file32 (data32,write_dff,data_flop32,clk,rst);
regfile #(BITWIDTH) r_file33 (data33,write_dff,data_flop33,clk,rst);
regfile #(BITWIDTH) r_file34 (data34,write_dff,data_flop34,clk,rst);
regfile #(BITWIDTH) r_file35 (data35,write_dff,data_flop35,clk,rst);
regfile #(BITWIDTH) r_file36 (data36,write_dff,data_flop36,clk,rst);
regfile #(BITWIDTH) r_file37 (data37,write_dff,data_flop37,clk,rst);
regfile #(BITWIDTH) r_file38 (data38,write_dff,data_flop38,clk,rst);
regfile #(BITWIDTH) r_file39 (data39,write_dff,data_flop39,clk,rst);
assign readdata = (readregsel==6'd0)?data_flop0:
(readregsel==6'd1)?data_flop1:
(readregsel==6'd2)?data_flop2:
(readregsel==6'd3)?data_flop3:
(readregsel==6'd4)?data_flop4:
(readregsel==6'd5)?data_flop5:
(readregsel==6'd6)?data_flop6:
(readregsel==6'd7)?data_flop7:
(readregsel==6'd8)?data_flop8:
(readregsel==6'd9)?data_flop9:
(readregsel==6'd10)?data_flop10:
(readregsel==6'd11)?data_flop11:
(readregsel==6'd12)?data_flop12:
(readregsel==6'd13)?data_flop13:
(readregsel==6'd14)?data_flop14:
(readregsel==6'd15)?data_flop15:
(readregsel==6'd16)?data_flop16:
(readregsel==6'd17)?data_flop17:
(readregsel==6'd18)?data_flop18:
(readregsel==6'd19)?data_flop19:
(readregsel==6'd20)?data_flop20:
(readregsel==6'd21)?data_flop21:
(readregsel==6'd22)?data_flop22:
(readregsel==6'd23)?data_flop23:
(readregsel==6'd24)?data_flop24:
(readregsel==6'd25)?data_flop25:
(readregsel==6'd26)?data_flop26:
(readregsel==6'd27)?data_flop27:
(readregsel==6'd28)?data_flop28:
(readregsel==6'd29)?data_flop29:
(readregsel==6'd30)?data_flop30:
(readregsel==6'd31)?data_flop31:
(readregsel==6'd32)?data_flop32:
(readregsel==6'd33)?data_flop33:
(readregsel==6'd34)?data_flop34:
(readregsel==6'd35)?data_flop35:
(readregsel==6'd36)?data_flop36:
(readregsel==6'd37)?data_flop37:
(readregsel==6'd38)?data_flop38:
(readregsel==6'd39)?data_flop39:
11'd0;
assign data0=(write & (writeregsel==6'd0))? writedata:data_flop0;
assign data1=(write & (writeregsel==6'd1))? writedata:data_flop1;
assign data2=(write & (writeregsel==6'd2))? writedata:data_flop2;
assign data3=(write & (writeregsel==6'd3))? writedata:data_flop3;
assign data4=(write & (writeregsel==6'd4))? writedata:data_flop4;
assign data5=(write & (writeregsel==6'd5))? writedata:data_flop5;
assign data6=(write & (writeregsel==6'd6))? writedata:data_flop6;
assign data7=(write & (writeregsel==6'd7))? writedata:data_flop7;
assign data8=(write & (writeregsel==6'd8))? writedata:data_flop8;
assign data9=(write & (writeregsel==6'd9))? writedata:data_flop9;
assign data10=(write & (writeregsel==6'd10))? writedata:data_flop10;
assign data11=(write & (writeregsel==6'd11))? writedata:data_flop11;
assign data12=(write & (writeregsel==6'd12))? writedata:data_flop12;
assign data13=(write & (writeregsel==6'd13))? writedata:data_flop13;
assign data14=(write & (writeregsel==6'd14))? writedata:data_flop14;
assign data15=(write & (writeregsel==6'd15))? writedata:data_flop15;
assign data16=(write & (writeregsel==6'd16))? writedata:data_flop16;
assign data17=(write & (writeregsel==6'd17))? writedata:data_flop17;
assign data18=(write & (writeregsel==6'd18))? writedata:data_flop18;
assign data19=(write & (writeregsel==6'd19))? writedata:data_flop19;
assign data20=(write & (writeregsel==6'd20))? writedata:data_flop20;
assign data21=(write & (writeregsel==6'd21))? writedata:data_flop21;
assign data22=(write & (writeregsel==6'd22))? writedata:data_flop22;
assign data23=(write & (writeregsel==6'd23))? writedata:data_flop23;
assign data24=(write & (writeregsel==6'd24))? writedata:data_flop24;
assign data25=(write & (writeregsel==6'd25))? writedata:data_flop25;
assign data26=(write & (writeregsel==6'd26))? writedata:data_flop26;
assign data27=(write & (writeregsel==6'd27))? writedata:data_flop27;
assign data28=(write & (writeregsel==6'd28))? writedata:data_flop28;
assign data29=(write & (writeregsel==6'd29))? writedata:data_flop29;
assign data30=(write & (writeregsel==6'd30))? writedata:data_flop30;
assign data31=(write & (writeregsel==6'd31))? writedata:data_flop31;
assign data32=(write & (writeregsel==6'd32))? writedata:data_flop32;
assign data33=(write & (writeregsel==6'd33))? writedata:data_flop33;
assign data34=(write & (writeregsel==6'd34))? writedata:data_flop34;
assign data35=(write & (writeregsel==6'd35))? writedata:data_flop35;
assign data36=(write & (writeregsel==6'd36))? writedata:data_flop36;
assign data37=(write & (writeregsel==6'd37))? writedata:data_flop37;
assign data38=(write & (writeregsel==6'd38))? writedata:data_flop38;
assign data39=(write & (writeregsel==6'd39))? writedata:data_flop39;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 11:24:36 03/17/2013
// Design Name:
// Module Name: Coun_Baud
// Project Name:
// Target Devices:
// Tool versions:
// Description: Contador de Bauds, lo que genera es un tick
//////////////////////////////////////////////////////////////////////////////////
module Coun_Baud // este modo es para generar los pulsos necesarios para el modo receptor y transmisor
#(
parameter N=10, // number of bits incounter = log2(M)
M=656 // mod-M Para una frecuencia de relog 100 MHZ --->9600bauds
) // M se obtiene de 100MHZ/(2X8X9600)
(
input wire clk, reset,
output wire max_tick
);
// Declaracion de Se;ales
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// Registro de estado
always @ (posedge clk , posedge reset)
if (reset)
r_reg <= 0 ;
else
r_reg <= r_next;
// Logica de estado siguiente
assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;
//Logica de salida
assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;
endmodule
|
//-----------------------------------------------------------------------------
//-- Divisor de frecuencia generico
//-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- Entrada: clk_in. Señal original
//-- Salida: clk_out. Señal de frecuencia 1/M de la original
module divider(input wire clk_in, output wire clk_out);
//-- Valor por defecto del divisor
//-- Lo ponemos a 1 Hz
parameter M = `F_2KHz;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con la funcion de verilog $clog2, que nos devuelve el
//-- numero de bits necesarios para representar el numero M
//-- Es un parametro local, que no se puede modificar al instanciar
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk_in)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar el bit mas significativo por clk_out
assign clk_out = divcounter[N-1];
endmodule
//-- Contador módulo M: Otra manera de implementarlo
/*
always @(posedge clk_in)
if (divcounter == M - 1)
divcounter <= 0;
else
divcounter <= divcounter + 1;
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_PP_SYMBOL_V
|
`include "project_include.v"
module master(
input clk,
input rst,
output reg o_master_ready, //Goes high until enough data for an
//entire command is read.
// For Ping, this is just the command
// For Read, just the command
// For Config, (Read) just the command
// For Config, (Write) command + the
// amount of data to read from host
// For Write, command + the amount of
// data to read from the host
//Master Interface
input [7:0] i_command,
input [7:0] i_flag,
input [31:0] i_rw_count,
input [31:0] i_address,
input i_command_rdy_stb,
output reg [7:0] o_status,
output [7:0] o_status_flags,
output reg [31:0] o_read_size,
output reg o_status_rdy_stb,
output reg [31:0] o_address, //Calculated end address, this can be
//used to verify that the mem was
//calculated correctly
//Write side FIFO interface
input i_wpath_ready,
output reg o_wpath_activate,
input [23:0] i_wpath_packet_size,
input [31:0] i_wpath_data,
output reg o_wpath_strobe,
//Read side FIFO interface
input [1:0] i_rpath_ready,
output reg [1:0] o_rpath_activate,
input [23:0] i_rpath_size,
output reg [31:0] o_rpath_data,
output reg o_rpath_strobe
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PING = 4'h1;
localparam WRITE = 4'h2;
localparam READ = 4'h3;
localparam CONFIG = 4'h4;
//Registers/Wires
reg [3:0] state;
reg [3:0] next_state;
reg [23:0] r_wdata_count;
reg [23:0] r_rdata_count;
reg [31:0] r_write_count;
reg [31:0] r_read_count;
reg [23:0] r_status_index;
reg r_status_strobe;
reg r_process_command;
reg [31:0] r_status;
wire [7:0] w_status_flags;
wire w_error; //Indicate that some error occured
wire w_error_bus_timeout; //Timeout with axi bus
wire w_error_comm_timeout; //Timeout with communication
wire w_interrupt;
reg r_send_status;
reg r_status_sent;
wire w_status_send_finished;
reg [23:0] r_rpath_fifo_count;
wire w_out_path_ready;
//Trigger Declaration
reg r_trig_send_status;
reg r_trig_send_finished;
//Submodules
//Asynchronous Logic
//assign o_master_ready = (state == IDLE);
assign w_out_path_ready = ((o_rpath_activate > 0) && (r_rpath_fifo_count < i_rpath_size));
assign w_status_send_finished = (!r_send_status && !r_status_sent);
assign w_error_bus_timeout = 0;
assign w_error_comm_timeout= 0;
assign w_error = (w_error_bus_timeout ||
w_error_comm_timeout);
assign w_interrupt = 0;
assign o_status_flags = 8'h0;
//Triggers
//Send Status Trigger
always @ (posedge clk) begin
if (rst) begin
r_trig_send_status <= 0;
r_trig_send_finished <= 0;
o_master_ready <= 0;
end
else begin
r_trig_send_status <= 0;
o_master_ready <= 0;
case (state)
IDLE: begin
r_trig_send_finished <= 0;
o_master_ready <= 1;
end
PING: begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
WRITE: begin
o_master_ready <= 1;
if (r_write_count >= i_rw_count) begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
end
READ: begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
CONFIG: begin
if (i_rw_count > 0) begin
o_master_ready <= 1;
end
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
endcase
end
end
always @ (*) begin
if (rst) begin
r_status = 0;
end
else begin
if (w_error) begin
//Error Occured :(
r_status = {`IDENTIFICATION_ERR,
o_status_flags,
~i_command};
end
else if (w_interrupt) begin
//Send OH HI!
r_status = {`IDENTIFICATION_INT,
o_status_flags,
`INTERRUPT_STATUS};
end
else begin
//Normal Response
//Check if there is an error condition here
r_status = {`IDENTIFICATION_RESP,
o_status_flags,
~i_command};
end
end
end
//strobe (i_command_rdy_stb) to enable (r_process_command)
always @ (*) begin
if (rst) begin
r_process_command = 0;
end
else begin
if (i_command_rdy_stb && (state == IDLE)) begin
r_process_command = 1;
end
else if (state != IDLE) begin
r_process_command = 0;
end
else begin
r_process_command = r_process_command;
end
end
end
//State Machine
always @ (*) begin
if (rst) begin
next_state = IDLE;
end
else begin
next_state = state;
case (state)
IDLE: begin
if (r_process_command) begin
case (i_command)
`PING_COMMAND: begin
next_state = PING;
end
`WRITE_COMMAND: begin
next_state = WRITE;
end
`READ_COMMAND: begin
$display ("Detected Read Request");
next_state = READ;
end
`CONFIG_COMMAND: begin
next_state = CONFIG;
end
endcase
end
else begin
next_state = IDLE;
end
end
PING: begin
//Just Send a response
if (!r_trig_send_finished) begin
next_state = IDLE;
end
else begin
next_state = PING;
end
end
WRITE: begin
//Data comes in from the host and writes to the FPGA
if (!r_trig_send_finished && (r_write_count >= i_rw_count)) begin
next_state = IDLE;
end
else begin
next_state = WRITE;
end
end
READ: begin
//Read Data from the i_address
if (r_read_count >= o_read_size) begin
next_state = IDLE;
end
else begin
next_state = READ;
end
end
CONFIG: begin
//Write and read configuration data
if (r_write_count >= i_rw_count) begin
next_state = IDLE;
end
end
endcase
end
end
//Synchronous Logic
//Synchronize state
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
//Set up the out read size and the out address
always @ (posedge clk) begin
if (rst) begin
o_read_size <= 0;
o_address <= 0;
end
else begin
if (i_command_rdy_stb) begin
case (i_command)
`PING_COMMAND: begin
o_read_size <= 0;
o_address <= i_address;
end
`WRITE_COMMAND: begin
o_read_size <= 0;
o_address <= i_address;
end
`READ_COMMAND: begin
o_read_size <= i_rw_count;
o_address <= i_address;
end
`CONFIG_COMMAND: begin
o_read_size <= `CONFIG_LENGTH;
o_address <= i_address;
end
endcase
end
end
end
//Input Path (All incomming data goes through here)
always @ (posedge clk) begin
if (rst) begin
o_wpath_activate <= 0;
o_wpath_strobe <= 0;
r_wdata_count <= 0; //Count for packet
r_write_count <= 0; //Count for the total data (independent of packet size)
end
else begin
o_wpath_strobe <= 0;
//Write Path (Incomming)
if (i_wpath_ready && !o_wpath_activate) begin
r_wdata_count <= 0;
o_wpath_activate <= 1;
end
else if (o_wpath_activate) begin
if (r_wdata_count >= i_wpath_packet_size) begin
o_wpath_activate <= 0;
end
end
if (o_wpath_strobe) begin
r_write_count <= r_write_count + 1;
end
if (state == WRITE) begin
if ((o_wpath_activate > 0) && (r_wdata_count < i_wpath_packet_size)) begin
o_wpath_strobe <= 1;
r_wdata_count <= r_wdata_count + 1;
end
//for now just suck all the data out of the incomming ping pong FIFO
//whenever it's available. In the future this will interface with the
//Axi Out Path
end
else if (state == IDLE) begin
r_write_count <= 0;
end
end
end
//Output Path (All outgoing data goes through here)
always @ (posedge clk) begin
if (rst) begin
o_status <= 0;
o_status_rdy_stb <= 0;
r_status_index <= 0;
r_status_strobe <= 0;
r_send_status <= 0;
r_status_sent <= 0;
o_rpath_activate <= 0;
o_rpath_data <= 0;
o_rpath_strobe <= 0;
r_rpath_fifo_count <= 0;
end
else begin
//Strobe
o_rpath_strobe <= 0;
o_status_rdy_stb <= 0;
r_status_strobe <= 0;
//Ping Pong FIFO Read Path (Outgoing)
if ((i_rpath_ready > 0) && (o_rpath_activate == 0)) begin
r_rpath_fifo_count <= 0;
if (i_rpath_ready[0]) begin
o_rpath_activate[0] <= 1;
end
else begin
o_rpath_activate[1] <= 1;
end
end
// else if (o_rpath_activate > 0)begin
// if (r_rpath_fifo_count < i_rpath_size) begin
// if (o_rpath_strobe) begin
// r_rpath_fifo_count <= r_rpath_fifo_count + 1;
// end
// end
// else begin
// o_rpath_activate <= 0;
// end
// end
//Take care of the send status trigger setup so we don't send multiple
//status packets
if (r_trig_send_status) begin
r_send_status <= 1;
end
else if (r_status_sent) begin
r_send_status <= 0;
r_status_sent <= 0;
end
//Conditions to disable the current Ping Pong FIFO
if ((state == IDLE) && (r_rpath_fifo_count > 0) && !o_rpath_strobe) begin
//Condition to flush the FIFO
o_rpath_activate <= 0;
end
//Condition to reset the read count
if (state == IDLE) begin
r_read_count <= 0;
r_status_index <= 0;
end
//Send Status
if (o_rpath_activate && r_send_status) begin
case (r_status_index)
`STATUS_DATA_0: begin
o_status <= r_status;
o_rpath_data <= r_status;
r_status_index <= r_status_index + 1;
o_rpath_strobe <= 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
end
`STATUS_DATA_1: begin
o_rpath_data <= o_read_size;
r_status_index <= r_status_index + 1;
o_rpath_strobe <= 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
end
`STATUS_DATA_2: begin
o_rpath_data <= o_address;
o_status_rdy_stb <= 1;
o_rpath_strobe <= 1;
r_status_index <= r_status_index + 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
if (i_command != `READ_COMMAND) begin
r_status_sent <= 1;
end
end
default: begin
if (r_read_count < o_read_size ) begin
if (o_rpath_activate > 0) begin
if (r_rpath_fifo_count < i_rpath_size) begin
o_rpath_strobe <= 1;
o_rpath_data <= r_read_count;
r_read_count <= r_read_count + 1;
r_rpath_fifo_count<= r_rpath_fifo_count + 1;
end
else begin
o_rpath_activate <= 0;
end
end
end
else begin
r_status_sent <= 1;
end
end
endcase
end
end
end
endmodule
|
// Model of FIFO in Altera
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 2048;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output wrempty;
output [10:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [10:0] rdusedw;
reg [10:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_2k
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input Arith16;
input Z16;
input [3:0] ALU_Op ;
input [5:0] IR;
input [1:0] ISet;
input [7:0] BusA;
input [7:0] BusB;
input [7:0] F_In;
output [7:0] Q;
output [7:0] F_Out;
reg [7:0] Q;
reg [7:0] F_Out;
function [4:0] AddSub4;
input [3:0] A;
input [3:0] B;
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
end
endfunction // AddSub4
function [3:0] AddSub3;
input [2:0] A;
input [2:0] B;
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
end
endfunction // AddSub4
function [1:0] AddSub1;
input A;
input B;
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
end
endfunction // AddSub4
// AddSub variables (temporary signals)
reg UseCarry;
reg Carry7_v;
reg OverFlow_v;
reg HalfCarry_v;
reg Carry_v;
reg [7:0] Q_v;
reg [7:0] BitMask;
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
begin
case (IR[5:3])
3'b000 : BitMask = 8'b00000001;
3'b001 : BitMask = 8'b00000010;
3'b010 : BitMask = 8'b00000100;
3'b011 : BitMask = 8'b00001000;
3'b100 : BitMask = 8'b00010000;
3'b101 : BitMask = 8'b00100000;
3'b110 : BitMask = 8'b01000000;
default: BitMask = 8'b10000000;
endcase // case(IR[5:3])
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
OverFlow_v = Carry_v ^ Carry7_v;
end // always @ *
reg [7:0] Q_t;
reg [8:0] DAA_Q;
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
or Carry_v or F_In or HalfCarry_v or IR or ISet
or OverFlow_v or Q_v or Z16)
begin
Q_t = 8'hxx;
DAA_Q = {9{1'bx}};
F_Out = F_In;
case (ALU_Op)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
F_Out[Flag_N] = 1'b0;
F_Out[Flag_C] = 1'b0;
case (ALU_Op[2:0])
3'b000, 3'b001 : // ADD, ADC
begin
Q_t = Q_v;
F_Out[Flag_C] = Carry_v;
F_Out[Flag_H] = HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
begin
Q_t = Q_v;
F_Out[Flag_N] = 1'b1;
F_Out[Flag_C] = ~ Carry_v;
F_Out[Flag_H] = ~ HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b100 : // AND
begin
Q_t[7:0] = BusA & BusB;
F_Out[Flag_H] = 1'b1;
end
3'b101 : // XOR
begin
Q_t[7:0] = BusA ^ BusB;
F_Out[Flag_H] = 1'b0;
end
default : // OR 3'b110
begin
Q_t[7:0] = BusA | BusB;
F_Out[Flag_H] = 1'b0;
end
endcase // case(ALU_OP[2:0])
if (ALU_Op[2:0] == 3'b111 )
begin // CP
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
else
begin
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
end
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
if (Z16 == 1'b1 )
begin
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
end
end
else
begin
F_Out[Flag_Z] = 1'b0;
end // else: !if(Q_t[7:0] == 8'b00000000 )
F_Out[Flag_S] = Q_t[7];
case (ALU_Op[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
;
default :
F_Out[Flag_P] = ~(^Q_t);
endcase // case(ALU_Op[2:0])
if (Arith16 == 1'b1 )
begin
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
F_Out[Flag_P] = F_In[Flag_P];
end
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
4'b1100 :
begin
// DAA
F_Out[Flag_H] = F_In[Flag_H];
F_Out[Flag_C] = F_In[Flag_C];
DAA_Q[7:0] = BusA;
DAA_Q[8] = 1'b0;
if (F_In[Flag_N] == 1'b0 )
begin
// After addition
// Alow > 9 || H == 1
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if ((DAA_Q[3:0] > 9) )
begin
F_Out[Flag_H] = 1'b1;
end
else
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q = DAA_Q + 6;
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
// new Ahigh > 9 || C == 1
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q + 96; // 0x60
end
end
else
begin
// After subtraction
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if (DAA_Q[3:0] > 5 )
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q[7:0] = DAA_Q[7:0] - 6;
end
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q - 352; // 0x160
end
end // else: !if(F_In[Flag_N] == 1'b0 )
F_Out[Flag_X] = DAA_Q[3];
F_Out[Flag_Y] = DAA_Q[5];
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
Q_t = DAA_Q[7:0];
if (DAA_Q[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = DAA_Q[7];
F_Out[Flag_P] = ~ (^DAA_Q);
end // case: 4'b1100
4'b1101, 4'b1110 :
begin
// RLD, RRD
Q_t[7:4] = BusA[7:4];
if (ALU_Op[0] == 1'b1 )
begin
Q_t[3:0] = BusB[7:4];
end
else
begin
Q_t[3:0] = BusB[3:0];
end
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = Q_t[7];
F_Out[Flag_P] = ~(^Q_t);
end // case: when 4'b1101, 4'b1110
4'b1001 :
begin
// BIT
Q_t[7:0] = BusB & BitMask;
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
F_Out[Flag_P] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
F_Out[Flag_P] = 1'b0;
end
F_Out[Flag_H] = 1'b1;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = 1'b0;
F_Out[Flag_Y] = 1'b0;
if (IR[2:0] != 3'b110 )
begin
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
end // case: when 4'b1001
4'b1010 :
// SET
Q_t[7:0] = BusB | BitMask;
4'b1011 :
// RES
Q_t[7:0] = BusB & ~ BitMask;
4'b1000 :
begin
// ROT
case (IR[5:3])
3'b000 : // RLC
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = BusA[7];
F_Out[Flag_C] = BusA[7];
end
3'b010 : // RL
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = F_In[Flag_C];
F_Out[Flag_C] = BusA[7];
end
3'b001 : // RRC
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[0];
F_Out[Flag_C] = BusA[0];
end
3'b011 : // RR
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = F_In[Flag_C];
F_Out[Flag_C] = BusA[0];
end
3'b100 : // SLA
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b0;
F_Out[Flag_C] = BusA[7];
end
3'b110 : // SLL (Undocumented) / SWAP
begin
if (Mode == 3 )
begin
Q_t[7:4] = BusA[3:0];
Q_t[3:0] = BusA[7:4];
F_Out[Flag_C] = 1'b0;
end
else
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b1;
F_Out[Flag_C] = BusA[7];
end // else: !if(Mode == 3 )
end // case: 3'b110
3'b101 : // SRA
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[7];
F_Out[Flag_C] = BusA[0];
end
default : // SRL
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = 1'b0;
F_Out[Flag_C] = BusA[0];
end
endcase // case(IR[5:3])
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_P] = ~(^Q_t);
if (ISet == 2'b00 )
begin
F_Out[Flag_P] = F_In[Flag_P];
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
end
end // case: 4'b1000
default :
;
endcase // case(ALU_Op)
Q = Q_t;
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
endmodule // T80_ALU
|
// $File: //acds/rel/14.0/ip/sopc/components/altera_avalon_dc_fifo/altera_avalon_dc_fifo.v $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
// Description: Dual clocked single channel FIFO with fill levels and status
// information.
// ---------------------------------------------------------------------
`timescale 1 ns / 100 ps
//altera message_off 10036 10858 10230 10030 10034
module altera_avalon_dc_fifo(
in_clk,
in_reset_n,
out_clk,
out_reset_n,
// sink
in_data,
in_valid,
in_ready,
in_startofpacket,
in_endofpacket,
in_empty,
in_error,
in_channel,
// source
out_data,
out_valid,
out_ready,
out_startofpacket,
out_endofpacket,
out_empty,
out_error,
out_channel,
// in csr
in_csr_address,
in_csr_write,
in_csr_read,
in_csr_readdata,
in_csr_writedata,
// out csr
out_csr_address,
out_csr_write,
out_csr_read,
out_csr_readdata,
out_csr_writedata,
// streaming in status
almost_full_valid,
almost_full_data,
// streaming out status
almost_empty_valid,
almost_empty_data,
// (internal, experimental interface) space available st source
space_avail_data
);
// ---------------------------------------------------------------------
// Parameters
// ---------------------------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FIFO_DEPTH = 16;
parameter CHANNEL_WIDTH = 0;
parameter ERROR_WIDTH = 0;
parameter USE_PACKETS = 0;
parameter USE_IN_FILL_LEVEL = 0;
parameter USE_OUT_FILL_LEVEL = 0;
parameter WR_SYNC_DEPTH = 2;
parameter RD_SYNC_DEPTH = 2;
parameter STREAM_ALMOST_FULL = 0;
parameter STREAM_ALMOST_EMPTY = 0;
parameter BACKPRESSURE_DURING_RESET = 0;
// optimizations
parameter LOOKAHEAD_POINTERS = 0;
parameter PIPELINE_POINTERS = 0;
// experimental, internal parameter
parameter USE_SPACE_AVAIL_IF = 0;
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
localparam EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT);
localparam PACKET_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// ---------------------------------------------------------------------
// Input/Output Signals
// ---------------------------------------------------------------------
input in_clk;
input in_reset_n;
input out_clk;
input out_reset_n;
input [DATA_WIDTH - 1 : 0] in_data;
input in_valid;
input in_startofpacket;
input in_endofpacket;
input [((EMPTY_WIDTH > 0) ? EMPTY_WIDTH - 1 : 0) : 0] in_empty;
input [((ERROR_WIDTH > 0) ? ERROR_WIDTH - 1 : 0) : 0] in_error;
input [((CHANNEL_WIDTH > 0) ? CHANNEL_WIDTH - 1 : 0) : 0] in_channel;
output in_ready;
output [DATA_WIDTH - 1 : 0] out_data;
output reg out_valid;
output out_startofpacket;
output out_endofpacket;
output [((EMPTY_WIDTH > 0) ? EMPTY_WIDTH - 1 : 0) : 0] out_empty;
output [((ERROR_WIDTH > 0) ? ERROR_WIDTH - 1 : 0) : 0] out_error;
output [((CHANNEL_WIDTH > 0) ? CHANNEL_WIDTH - 1 : 0) : 0] out_channel;
input out_ready;
input in_csr_address;
input in_csr_read;
input in_csr_write;
input [31 : 0] in_csr_writedata;
output reg [31 : 0] in_csr_readdata;
input out_csr_address;
input out_csr_read;
input out_csr_write;
input [31 : 0] out_csr_writedata;
output reg [31 : 0] out_csr_readdata;
output reg almost_full_valid;
output reg almost_full_data;
output reg almost_empty_valid;
output reg almost_empty_data;
output [ADDR_WIDTH : 0] space_avail_data;
// ---------------------------------------------------------------------
// Memory Pointers
// ---------------------------------------------------------------------
(* ramstyle="no_rw_check" *) reg [PAYLOAD_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
wire [ADDR_WIDTH - 1 : 0] mem_wr_ptr;
wire [ADDR_WIDTH - 1 : 0] mem_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr_lookahead;
reg [ADDR_WIDTH : 0] out_rd_ptr;
reg [ADDR_WIDTH : 0] out_rd_ptr_lookahead;
// ---------------------------------------------------------------------
// Internal Signals
// ---------------------------------------------------------------------
wire [ADDR_WIDTH : 0] next_out_wr_ptr;
wire [ADDR_WIDTH : 0] next_in_wr_ptr;
wire [ADDR_WIDTH : 0] next_out_rd_ptr;
wire [ADDR_WIDTH : 0] next_in_rd_ptr;
reg [ADDR_WIDTH : 0] in_wr_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] out_wr_ptr_gray;
reg [ADDR_WIDTH : 0] out_rd_ptr_gray /*synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D102" */;
wire [ADDR_WIDTH : 0] in_rd_ptr_gray;
reg [ADDR_WIDTH : 0] out_wr_ptr_gray_reg;
reg [ADDR_WIDTH : 0] in_rd_ptr_gray_reg;
reg full;
reg empty;
wire [PAYLOAD_WIDTH - 1 : 0] in_payload;
reg [PAYLOAD_WIDTH - 1 : 0] out_payload;
reg [PAYLOAD_WIDTH - 1 : 0] internal_out_payload;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] in_packet_signals;
wire [PACKET_SIGNALS_WIDTH - 1 : 0] out_packet_signals;
wire internal_out_ready;
wire internal_out_valid;
wire [ADDR_WIDTH : 0] out_fill_level;
reg [ADDR_WIDTH : 0] out_fifo_fill_level;
reg [ADDR_WIDTH : 0] in_fill_level;
reg [ADDR_WIDTH : 0] in_space_avail;
reg [23 : 0] almost_empty_threshold;
reg [23 : 0] almost_full_threshold;
reg sink_in_reset;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign in_payload = in_data;
assign out_data = out_payload;
end
end
assign out_packet_signals = 'b0;
end
endgenerate
// ---------------------------------------------------------------------
// Memory
//
// Infers a simple dual clock memory with unregistered outputs
// ---------------------------------------------------------------------
always @(posedge in_clk) begin
if (in_valid && in_ready)
mem[mem_wr_ptr] <= in_payload;
end
always @(posedge out_clk) begin
internal_out_payload <= mem[mem_rd_ptr];
end
assign mem_rd_ptr = next_out_rd_ptr;
assign mem_wr_ptr = in_wr_ptr;
// ---------------------------------------------------------------------
// Pointer Management
//
// Increment our good old read and write pointers on their native
// clock domains.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_wr_ptr <= 0;
in_wr_ptr_lookahead <= 1;
end
else begin
in_wr_ptr <= next_in_wr_ptr;
in_wr_ptr_lookahead <= (in_valid && in_ready) ? in_wr_ptr_lookahead + 1'b1 : in_wr_ptr_lookahead;
end
end
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_rd_ptr <= 0;
out_rd_ptr_lookahead <= 1;
end
else begin
out_rd_ptr <= next_out_rd_ptr;
out_rd_ptr_lookahead <= (internal_out_valid && internal_out_ready) ? out_rd_ptr_lookahead + 1'b1 : out_rd_ptr_lookahead;
end
end
generate if (LOOKAHEAD_POINTERS) begin : lookahead_pointers
assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr_lookahead : in_wr_ptr;
assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr_lookahead : out_rd_ptr;
end
else begin : non_lookahead_pointers
assign next_in_wr_ptr = (in_ready && in_valid) ? in_wr_ptr + 1'b1 : in_wr_ptr;
assign next_out_rd_ptr = (internal_out_ready && internal_out_valid) ? out_rd_ptr + 1'b1 : out_rd_ptr;
end
endgenerate
// ---------------------------------------------------------------------
// Empty/Full Signal Generation
//
// We keep read and write pointers that are one bit wider than
// required, and use that additional bit to figure out if we're
// full or empty.
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if(!out_reset_n)
empty <= 1;
else
empty <= (next_out_rd_ptr == next_out_wr_ptr);
end
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
full <= 0;
sink_in_reset <= 1'b1;
end
else begin
full <= (next_in_rd_ptr[ADDR_WIDTH - 1 : 0] == next_in_wr_ptr[ADDR_WIDTH - 1 : 0]) && (next_in_rd_ptr[ADDR_WIDTH] != next_in_wr_ptr[ADDR_WIDTH]);
sink_in_reset <= 1'b0;
end
end
// ---------------------------------------------------------------------
// Write Pointer Clock Crossing
//
// Clock crossing is done with gray encoding of the pointers. What? You
// want to know more? We ensure a one bit change at sampling time,
// and then metastable harden the sampled gray pointer.
// ---------------------------------------------------------------------
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_wr_ptr_gray <= 0;
else
in_wr_ptr_gray <= bin2gray(in_wr_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(WR_SYNC_DEPTH))
write_crosser (
.clk(out_clk),
.reset_n(out_reset_n),
.din(in_wr_ptr_gray),
.dout(out_wr_ptr_gray)
);
// ---------------------------------------------------------------------
// Optionally pipeline the gray to binary conversion for the write pointer.
// Doing this will increase the latency of the FIFO, but increase fmax.
// ---------------------------------------------------------------------
generate if (PIPELINE_POINTERS) begin : wr_ptr_pipeline
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_wr_ptr_gray_reg <= 0;
else
out_wr_ptr_gray_reg <= gray2bin(out_wr_ptr_gray);
end
assign next_out_wr_ptr = out_wr_ptr_gray_reg;
end
else begin : no_wr_ptr_pipeline
assign next_out_wr_ptr = gray2bin(out_wr_ptr_gray);
end
endgenerate
// ---------------------------------------------------------------------
// Read Pointer Clock Crossing
//
// Go the other way, go the other way...
// ---------------------------------------------------------------------
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n)
out_rd_ptr_gray <= 0;
else
out_rd_ptr_gray <= bin2gray(out_rd_ptr);
end
altera_dcfifo_synchronizer_bundle #(.WIDTH(ADDR_WIDTH+1), .DEPTH(RD_SYNC_DEPTH))
read_crosser (
.clk(in_clk),
.reset_n(in_reset_n),
.din(out_rd_ptr_gray),
.dout(in_rd_ptr_gray)
);
// ---------------------------------------------------------------------
// Optionally pipeline the gray to binary conversion of the read pointer.
// Doing this will increase the pessimism of the FIFO, but increase fmax.
// ---------------------------------------------------------------------
generate if (PIPELINE_POINTERS) begin : rd_ptr_pipeline
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n)
in_rd_ptr_gray_reg <= 0;
else
in_rd_ptr_gray_reg <= gray2bin(in_rd_ptr_gray);
end
assign next_in_rd_ptr = in_rd_ptr_gray_reg;
end
else begin : no_rd_ptr_pipeline
assign next_in_rd_ptr = gray2bin(in_rd_ptr_gray);
end
endgenerate
// ---------------------------------------------------------------------
// Avalon ST Signals
// ---------------------------------------------------------------------
assign in_ready = BACKPRESSURE_DURING_RESET ? !(full || sink_in_reset) : !full;
assign internal_out_valid = !empty;
// --------------------------------------------------
// Output Pipeline Stage
//
// We do this on the single clock FIFO to keep fmax
// up because the memory outputs are kind of slow.
// Therefore, this stage is even more critical on a dual clock
// FIFO, wouldn't you say? No one wants a slow dcfifo.
// --------------------------------------------------
assign internal_out_ready = out_ready || !out_valid;
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid;
out_payload <= internal_out_payload;
end
end
end
// ---------------------------------------------------------------------
// Out Fill Level
//
// As in the SCFIFO, we account for the output stage as well in the
// fill level calculations. This means that the out fill level always
// gives the most accurate fill level report.
//
// On a full 16-deep FIFO, the out fill level will read 17. Funny, but
// accurate.
//
// That's essential on the output side, because a downstream component
// might want to know the exact amount of data in the FIFO at any time.
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_fifo_fill_level <= 0;
end
else begin
out_fifo_fill_level <= next_out_wr_ptr - next_out_rd_ptr;
end
end
assign out_fill_level = out_fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
endgenerate
// ---------------------------------------------------------------------
// Almost Empty Streaming Status & Out CSR
//
// This is banal by now, but where's the empty signal? The output side.
// Where's the almost empty status? The output side.
//
// The almost empty signal is asserted when the output fill level
// in the FIFO falls below the user-specified threshold.
//
// Output CSR address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | Out fill level |
// | 1 | RW | Reserved | Almost empty threshold |
// ---------------------------------------------------------------------
generate
if (USE_OUT_FILL_LEVEL || STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
out_csr_readdata <= 0;
if (STREAM_ALMOST_EMPTY)
almost_empty_threshold <= 0;
end
else begin
if (out_csr_write) begin
if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
almost_empty_threshold <= out_csr_writedata[23 : 0];
end
else if (out_csr_read) begin
out_csr_readdata <= 0;
if (out_csr_address == 0)
out_csr_readdata[23 : 0] <= out_fill_level;
else if (STREAM_ALMOST_EMPTY && (out_csr_address == 1))
out_csr_readdata[23 : 0] <= almost_empty_threshold;
end
end
end
end
if (STREAM_ALMOST_EMPTY) begin
always @(posedge out_clk or negedge out_reset_n) begin
if (!out_reset_n) begin
almost_empty_valid <= 0;
almost_empty_data <= 0;
end
else begin
almost_empty_valid <= 1'b1;
almost_empty_data <= (out_fill_level <= almost_empty_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// In Fill Level & In Status Connection Point
//
// Note that the input fill level does not account for the output
// stage i.e it is only the fifo fill level.
//
// Is this a problem? No, because the input fill is usually used to
// see how much data can still be pushed into this FIFO. The FIFO
// fill level gives exactly this information, and there's no need to
// make our lives more difficult by including the output stage here.
//
// One might ask: why not just report a space available level on the
// input side? Well, I'd like to make this FIFO be as similar as possible
// to its single clock cousin, and that uses fill levels and
// fill thresholds with nary a mention of space available.
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_fill_level <= 0;
end
else begin
in_fill_level <= next_in_wr_ptr - next_in_rd_ptr;
end
end
end
endgenerate
generate
if (USE_SPACE_AVAIL_IF) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_space_avail <= FIFO_DEPTH;
end
else begin
// -------------------------------------
// space = DEPTH-fill = DEPTH-(wr-rd) = DEPTH+rd-wr
// Conveniently, DEPTH requires the same number of bits
// as the pointers, e.g. a dcfifo with depth = 8
// requires 4-bit pointers.
//
// Adding 8 to a 4-bit pointer is simply negating the
// first bit... as is done below.
// -------------------------------------
in_space_avail <= {~next_in_rd_ptr[ADDR_WIDTH],
next_in_rd_ptr[ADDR_WIDTH-1:0]} -
next_in_wr_ptr;
end
end
assign space_avail_data = in_space_avail;
end
else begin : gen_blk13_else
assign space_avail_data = 'b0;
end
endgenerate
// ---------------------------------------------------------------------
// Almost Full Streaming Status & In CSR
//
// Where's the full signal? The input side.
// Where's the almost full status? The input side.
//
// The almost full data bit is asserted when the input fill level
// in the FIFO goes above the user-specified threshold.
//
// Input csr port address map:
//
// | Addr | RW | 31 - 24 | 23 - 0 |
// | 0 | R | Reserved | In fill level |
// | 1 | RW | Reserved | Almost full threshold |
// ---------------------------------------------------------------------
generate
if (USE_IN_FILL_LEVEL || STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
in_csr_readdata <= 0;
if (STREAM_ALMOST_FULL)
almost_full_threshold <= 0;
end
else begin
if (in_csr_write) begin
if (STREAM_ALMOST_FULL && (in_csr_address == 1))
almost_full_threshold <= in_csr_writedata[23 : 0];
end
else if (in_csr_read) begin
in_csr_readdata <= 0;
if (in_csr_address == 0)
in_csr_readdata[23 : 0] <= in_fill_level;
else if (STREAM_ALMOST_FULL && (in_csr_address == 1))
in_csr_readdata[23 : 0] <= almost_full_threshold;
end
end
end
end
if (STREAM_ALMOST_FULL) begin
always @(posedge in_clk or negedge in_reset_n) begin
if (!in_reset_n) begin
almost_full_valid <= 0;
almost_full_data <= 0;
end
else begin
almost_full_valid <= 1'b1;
almost_full_data <= (in_fill_level >= almost_full_threshold);
end
end
end
endgenerate
// ---------------------------------------------------------------------
// Gray Functions
//
// These are real beasts when you look at them. But they'll be
// tested thoroughly.
// ---------------------------------------------------------------------
function [ADDR_WIDTH : 0] bin2gray;
input [ADDR_WIDTH : 0] bin_val;
integer i;
for (i = 0; i <= ADDR_WIDTH; i = i + 1)
begin
if (i == ADDR_WIDTH)
bin2gray[i] = bin_val[i];
else
bin2gray[i] = bin_val[i+1] ^ bin_val[i];
end
endfunction
function [ADDR_WIDTH : 0] gray2bin;
input [ADDR_WIDTH : 0] gray_val;
integer i;
integer j;
for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin
gray2bin[i] = gray_val[i];
for (j = ADDR_WIDTH; j > i; j = j - 1) begin
gray2bin[i] = gray2bin[i] ^ gray_val[j];
end
end
endfunction
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module RS232TX (
input wire clk,
input wire rst,
output reg rs232TX,
input wire[7:0] data,
input wire startTX,
output reg busy,
input wire bps,
output reg startBPS
);
reg startTX0, startTX1, startTX2;
always @(posedge clk) begin
if (rst) begin
startTX0 <= 1'b0;
startTX1 <= 1'b0;
startTX2 <= 1'b0;
end else begin
startTX0 <= startTX;
startTX1 <= startTX0;
startTX2 <= startTX1;
end
end
wire startTXPosEdge = ~startTX2 & startTX1;
reg[7:0] txData;
reg[3:0] state;
always @(posedge clk) begin
if (rst) begin
startBPS <= 1'b0;
busy <= 1'b0;
txData <= 8'b0;
end else if (startTXPosEdge) begin
startBPS <= 1'b1;
txData <= data;
busy <= 1'b1;
end else if (state == 4'd11) begin
startBPS <= 1'b0;
busy <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
state <= 4'b0;
rs232TX <= 1'b1;
end
else if (busy) begin
if (bps) begin
state <= state + 1;
case (state)
4'd0: rs232TX <= 1'b0;
4'd1: rs232TX <= txData[0];
4'd2: rs232TX <= txData[1];
4'd3: rs232TX <= txData[2];
4'd4: rs232TX <= txData[3];
4'd5: rs232TX <= txData[4];
4'd6: rs232TX <= txData[5];
4'd7: rs232TX <= txData[6];
4'd8: rs232TX <= txData[7];
4'd9: rs232TX <= 1'b1;
default: rs232TX <= 1'b1;
endcase
end else if (state == 4'd11) state <= 4'd0;
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_mem_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive Memory Data State Machine module. This module takes the
// data from the width conversion fifo (data_trn_mem_fifo) and send it into the
// dma_ddr2_if block
// that passes the data off to the MIG memory controller to write to the DDR2
// memory.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang
// add TX descriptor handling here ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_mem_data_fsm(
input wire clk,
input wire rst,
//interface to dma_ddr2_if block
output reg [127:0] ingress_data,
// output reg [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
output reg ingress_fifo_wren,
// input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
output reg [2:0] ingress_xfer_size,
output reg [27:6] ingress_start_addr,
output reg ingress_data_req,
input wire ingress_data_ack,
//interface to xfer_trn_mem_fifo
input wire isDes_fifo, /// Jiansong: added for TX des
input wire [27:6] mem_dest_addr_fifo,
input wire [10:0] mem_dma_size_fifo,
input wire mem_dma_start,//start signal not used-monitor empty instead
input wire mem_trn_fifo_empty,
output reg mem_trn_fifo_rden,
//interface to data_trn_mem_fifo
input wire [127:0] data_fifo_data,
output reg data_fifo_cntrl,
input wire data_fifo_status,
///Jiansong: interface to dma control wrapper
output reg new_des_one, /// Jiansong: is one cycle ok?
output wire [31:0] SourceAddr_L,
output wire [31:0] SourceAddr_H,
output wire [31:0] DestAddr,
output wire [23:0] FrameSize,
output wire [7:0] FrameControl
// output reg [4:0] state /// liuchang: for debug
);
reg [4:0] state;
reg [9:0] cnt;
//reg [1:0] ingress_fifo_ctrl_pipe = 2'b00;
reg ingress_fifo_wren_pipe;
/// liuchang
reg [10:0] mem_dma_size_fifo_r;
reg [27:6] mem_dest_addr_fifo_r;
/// Jiansong
reg [127:0] TX_des_1;
reg [127:0] TX_des_2;
/// Jiansong: parse TX descriptor
assign SourceAddr_L[31:0] = TX_des_1[95:64];
assign SourceAddr_H[31:0] = TX_des_1[127:96];
assign DestAddr[31:0] = TX_des_2[31:0];
assign FrameSize[23:0] = TX_des_2[87:64];
assign FrameControl[7:0] = TX_des_2[95:88];
/// Jiansong: check own bit?
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// Jiansong: data fifo empty pipeline
reg data_fifo_status_r;
always@(posedge clk) data_fifo_status_r <= data_fifo_status;
localparam IDLE = 5'b00000;
localparam WREQ = 5'b00001;
localparam WDATA2 = 5'b00010;
localparam WDONE = 5'b00011;
localparam MREQ = 5'b00100;
localparam MREQ2 = 5'b00101;
localparam MREQ_WAIT = 5'b00110; /// liuchang
/// Jiansong:
localparam PARSE_TX_DES = 5'b01000;
localparam READ_TX_DES_1 = 5'b10000;
localparam READ_TX_DES_2 = 5'b11000;
//This state machine block waits for the xfer_trn_mem_fifo to go non-empty.
//It then performs the following steps:
// 1. read the transfer size and destination
// information out of the xfer_trn_mem_fifo
// 2. encode the transfer size info from DWORDS to the encoding used by
// dma_ddr2_if block
// 3. transfer the correct amount of data from the data_trn_mem_fifo to
// the dma_ddr2_if (ingress data fifo)
always @ (posedge clk)
begin
if(rst_reg)
begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
new_des_one <= 1'b0;
TX_des_1 <= 128'h00000000_00000000_00000000_00000000;
TX_des_2 <= 128'h00000000_00000000_00000000_00000000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
else
begin
case(state)
IDLE: begin
new_des_one <= 1'b0;
//wait for non-empty case and assert the read enable if so
if(~mem_trn_fifo_empty)begin
mem_trn_fifo_rden <= 1'b1;
ingress_data_req <= 1'b0;
state <= MREQ;
end else begin
state <= IDLE;
end
end
MREQ: begin //deassert the read enable
mem_trn_fifo_rden <= 1'b0;
// state <= MREQ2; /// liuchang
state <= MREQ_WAIT; /// liuchang
end
MREQ_WAIT: begin /// liuchang
mem_dma_size_fifo_r <= mem_dma_size_fifo;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo[27:6];
state <= MREQ2;
end
MREQ2:begin
if(isDes_fifo) begin /// Jiansong: parse TX des
// check whether TX descriptor data arrived in
// if (~data_fifo_status)begin
if (~data_fifo_status_r)begin
state <= PARSE_TX_DES;
data_fifo_cntrl <= 1'b1; /// read enable the 1st cycle
end else begin
state <= MREQ2;
data_fifo_cntrl <= 1'b0;
end
end else begin
state <= WREQ;
//encode the transfer size information for the dma_ddr2_if
//also load a counter with the number of 128-bit (16 byte)
//transfers it will require to fullfill the total data
/// liuchang
if(mem_dma_size_fifo_r[10]) begin
ingress_xfer_size <= 3'b110; // 4k byte
cnt <= 10'h100;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b10000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b1000000;
end else if(mem_dma_size_fifo_r[9]) begin // 2k
ingress_xfer_size <= 3'b101;
cnt <= 10'h080;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b01000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0100000;
end else if(mem_dma_size_fifo_r[8]) begin // 1k
ingress_xfer_size <= 3'b100;
cnt <= 10'h040;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00100000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0010000;
end else if(mem_dma_size_fifo_r[7]) begin // 512
ingress_xfer_size <= 3'b011;
cnt <= 10'h020;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00010000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0001000;
end else if(mem_dma_size_fifo_r[6]) begin // 256
ingress_xfer_size <= 3'b010;
cnt <= 10'h010;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00001000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000100;
end else if(mem_dma_size_fifo_r[5]) begin // 128
ingress_xfer_size <= 3'b001;
cnt <= 10'h008;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000100000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000010;
end else if(mem_dma_size_fifo_r[4]) begin // 64 byte
ingress_xfer_size <= 3'b000;
cnt <= 10'h004;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000010000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000001;
end
/// liuchang
/*
case(mem_dma_size_fifo)
11'b00000010000: begin //64 byte
ingress_xfer_size <= 3'b000;
//64 bytes / 16 byte/xfer = 4 xfers
cnt <= 10'h004;
end
11'b00000100000: begin //128
ingress_xfer_size <= 3'b001;
cnt <= 10'h008;
end
11'b00001000000: begin //256
ingress_xfer_size <= 3'b010;
cnt <= 10'h010;
end
11'b00010000000: begin //512
ingress_xfer_size <= 3'b011;
cnt <= 10'h020;
end
11'b00100000000: begin //1k
ingress_xfer_size <= 3'b100;
cnt <= 10'h040;
end
11'b01000000000: begin //2k
ingress_xfer_size <= 3'b101;
cnt <= 10'h080;
end
11'b10000000000: begin //4k
ingress_xfer_size <= 3'b110;
cnt <= 10'h100;
end
endcase
*/
ingress_start_addr[27:6] <= mem_dest_addr_fifo_r[27:6];
ingress_data_req <= 1'b1;//request access to ingress fifo
end
end
/// Jiansong: parse TX des
PARSE_TX_DES: begin
state <= READ_TX_DES_1;
data_fifo_cntrl <= 1'b1; /// read enable the 2nd cycle
end
READ_TX_DES_1: begin
state <= READ_TX_DES_2;
data_fifo_cntrl <= 1'b0;
/// read data, 1st cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
new_des_one <= 1'b0;
end
READ_TX_DES_2: begin
state <= IDLE; /// Jiansong: possible timing problem here
/// read data, 2nd cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
TX_des_1[127:0] <= TX_des_2[127:0];
new_des_one <= 1'b1;
end
WREQ: begin /// Jiansong: data should be already in data_trn_mem_fifo
if(ingress_data_ack) begin//wait for a grant from the dma_ddr2_if
state <= WDATA2;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b1;
end else begin
state <= WREQ;
end
end
WDATA2: begin
//keep data_fifo_cntrl asserted until cnt is 1 - then deassert
//and finish
if(cnt == 10'h001)begin
state <= WDONE;
data_fifo_cntrl <= 1'b0;
end else begin
cnt <= cnt - 1'b1;
data_fifo_cntrl <= 1'b1;
state <= WDATA2;
end
end
WDONE: begin
// state <= IDLE; /// liuchang
if(mem_dma_size_fifo_r[10:4] == 7'h00) /// liuchang
state <= IDLE;
else
state <= MREQ2;
end
default:begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
endcase
end
end
/// Jiansong: timing ok? all driven by the same clk
//data_fifo_cntrl is used as both a read enable to the data_trn_mem_fifo and
//a write enable to the ingress fifo (in dma_ddr2_if). The write enable
//needs to be pipelined by two clocks so that it is synched with the
//ingress_data (normally it would only need one pipeline register but since
//ingress_data is pipelined, it requires two.
always@(posedge clk) begin // Jiansong: add logic to prevent TX des write into DDR
// ingress_fifo_ctrl_pipe[1:0] <= {1'b0,(data_fifo_cntrl&(~isDes_fifo))};//1st pipeline
// ingress_fifo_ctrl[1:0] <= ingress_fifo_ctrl_pipe[1:0]; //2nd pipeline
ingress_fifo_wren_pipe <= data_fifo_cntrl&(~isDes_fifo); //1st pipeline
ingress_fifo_wren <= ingress_fifo_wren_pipe; //2nd pipeline
ingress_data[127:0] <= data_fifo_data[127:0]; //pipelined data
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 20:15:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
// system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.v
// Design : system_buffer_register_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_buffer_register_0_0_buffer_register
(val_out,
val_in,
clk);
output [31:0]val_out;
input [31:0]val_in;
input clk;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
FDRE \val_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(val_in[0]),
.Q(val_out[0]),
.R(1'b0));
FDRE \val_out_reg[10]
(.C(clk),
.CE(1'b1),
.D(val_in[10]),
.Q(val_out[10]),
.R(1'b0));
FDRE \val_out_reg[11]
(.C(clk),
.CE(1'b1),
.D(val_in[11]),
.Q(val_out[11]),
.R(1'b0));
FDRE \val_out_reg[12]
(.C(clk),
.CE(1'b1),
.D(val_in[12]),
.Q(val_out[12]),
.R(1'b0));
FDRE \val_out_reg[13]
(.C(clk),
.CE(1'b1),
.D(val_in[13]),
.Q(val_out[13]),
.R(1'b0));
FDRE \val_out_reg[14]
(.C(clk),
.CE(1'b1),
.D(val_in[14]),
.Q(val_out[14]),
.R(1'b0));
FDRE \val_out_reg[15]
(.C(clk),
.CE(1'b1),
.D(val_in[15]),
.Q(val_out[15]),
.R(1'b0));
FDRE \val_out_reg[16]
(.C(clk),
.CE(1'b1),
.D(val_in[16]),
.Q(val_out[16]),
.R(1'b0));
FDRE \val_out_reg[17]
(.C(clk),
.CE(1'b1),
.D(val_in[17]),
.Q(val_out[17]),
.R(1'b0));
FDRE \val_out_reg[18]
(.C(clk),
.CE(1'b1),
.D(val_in[18]),
.Q(val_out[18]),
.R(1'b0));
FDRE \val_out_reg[19]
(.C(clk),
.CE(1'b1),
.D(val_in[19]),
.Q(val_out[19]),
.R(1'b0));
FDRE \val_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(val_in[1]),
.Q(val_out[1]),
.R(1'b0));
FDRE \val_out_reg[20]
(.C(clk),
.CE(1'b1),
.D(val_in[20]),
.Q(val_out[20]),
.R(1'b0));
FDRE \val_out_reg[21]
(.C(clk),
.CE(1'b1),
.D(val_in[21]),
.Q(val_out[21]),
.R(1'b0));
FDRE \val_out_reg[22]
(.C(clk),
.CE(1'b1),
.D(val_in[22]),
.Q(val_out[22]),
.R(1'b0));
FDRE \val_out_reg[23]
(.C(clk),
.CE(1'b1),
.D(val_in[23]),
.Q(val_out[23]),
.R(1'b0));
FDRE \val_out_reg[24]
(.C(clk),
.CE(1'b1),
.D(val_in[24]),
.Q(val_out[24]),
.R(1'b0));
FDRE \val_out_reg[25]
(.C(clk),
.CE(1'b1),
.D(val_in[25]),
.Q(val_out[25]),
.R(1'b0));
FDRE \val_out_reg[26]
(.C(clk),
.CE(1'b1),
.D(val_in[26]),
.Q(val_out[26]),
.R(1'b0));
FDRE \val_out_reg[27]
(.C(clk),
.CE(1'b1),
.D(val_in[27]),
.Q(val_out[27]),
.R(1'b0));
FDRE \val_out_reg[28]
(.C(clk),
.CE(1'b1),
.D(val_in[28]),
.Q(val_out[28]),
.R(1'b0));
FDRE \val_out_reg[29]
(.C(clk),
.CE(1'b1),
.D(val_in[29]),
.Q(val_out[29]),
.R(1'b0));
FDRE \val_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(val_in[2]),
.Q(val_out[2]),
.R(1'b0));
FDRE \val_out_reg[30]
(.C(clk),
.CE(1'b1),
.D(val_in[30]),
.Q(val_out[30]),
.R(1'b0));
FDRE \val_out_reg[31]
(.C(clk),
.CE(1'b1),
.D(val_in[31]),
.Q(val_out[31]),
.R(1'b0));
FDRE \val_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(val_in[3]),
.Q(val_out[3]),
.R(1'b0));
FDRE \val_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(val_in[4]),
.Q(val_out[4]),
.R(1'b0));
FDRE \val_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(val_in[5]),
.Q(val_out[5]),
.R(1'b0));
FDRE \val_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(val_in[6]),
.Q(val_out[6]),
.R(1'b0));
FDRE \val_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(val_in[7]),
.Q(val_out[7]),
.R(1'b0));
FDRE \val_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(val_in[8]),
.Q(val_out[8]),
.R(1'b0));
FDRE \val_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(val_in[9]),
.Q(val_out[9]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_buffer_register_0_0,buffer_register,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "buffer_register,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_buffer_register_0_0
(clk,
val_in,
val_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [31:0]val_in;
output [31:0]val_out;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
system_buffer_register_0_0_buffer_register U0
(.clk(clk),
.val_in(val_in),
.val_out(val_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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