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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
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//-----------------------------------------------------------------------------
//
// Description: Address AXI3 Slave Converter
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_axi3_conv
// axic_fifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AUSER_WIDTH = 1,
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface (W/R)
output wire cmd_valid,
output wire cmd_split,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire [4-1:0] cmd_length,
input wire cmd_ready,
// Command Interface (B)
output wire cmd_b_valid,
output wire cmd_b_split,
output wire [4-1:0] cmd_b_repeat,
input wire cmd_b_ready,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [1-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AQOS,
input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [4-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AQOS,
output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Constants used to generate size mask.
localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1'b1}}, 8'b0000_0000};
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_incr;
wire [4-1:0] num_transactions;
wire incr_need_to_split;
reg [C_AXI_ADDR_WIDTH-1:0] next_mi_addr;
reg split_ongoing;
reg [4-1:0] pushed_commands;
reg [16-1:0] addr_step;
reg [16-1:0] first_step;
wire [8-1:0] first_beats;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask;
// Access decoding related signals for internal pipestage.
reg access_is_incr_q;
reg incr_need_to_split_q;
wire need_to_split_q;
reg [4-1:0] num_transactions_q;
reg [16-1:0] addr_step_q;
reg [16-1:0] first_step_q;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask_q;
// Command buffer help signals.
reg [C_FIFO_DEPTH_LOG:0] cmd_depth;
reg cmd_empty;
reg [C_AXI_ID_WIDTH-1:0] queue_id;
wire id_match;
wire cmd_id_check;
wire s_ready;
wire cmd_full;
wire allow_this_cmd;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
reg [C_FIFO_DEPTH_LOG:0] cmd_b_depth;
reg cmd_b_empty;
wire cmd_b_full;
wire cmd_b_push;
reg cmd_b_push_block;
wire pushed_new_cmd;
wire last_incr_split;
wire last_split;
wire first_split;
wire no_cmd;
wire allow_split_cmd;
wire almost_empty;
wire no_b_cmd;
wire allow_non_split_cmd;
wire almost_b_empty;
reg multiple_id_non_split;
reg split_in_progress;
// Internal Command Interface signals (W/R).
wire cmd_split_i;
wire [C_AXI_ID_WIDTH-1:0] cmd_id_i;
reg [4-1:0] cmd_length_i;
// Internal Command Interface signals (B).
wire cmd_b_split_i;
wire [4-1:0] cmd_b_repeat_i;
// Throttling help signals.
wire mi_stalling;
reg command_ongoing;
// Internal SI-side signals.
reg [C_AXI_ID_WIDTH-1:0] S_AXI_AID_Q;
reg [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR_Q;
reg [8-1:0] S_AXI_ALEN_Q;
reg [3-1:0] S_AXI_ASIZE_Q;
reg [2-1:0] S_AXI_ABURST_Q;
reg [2-1:0] S_AXI_ALOCK_Q;
reg [4-1:0] S_AXI_ACACHE_Q;
reg [3-1:0] S_AXI_APROT_Q;
reg [4-1:0] S_AXI_AQOS_Q;
reg [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER_Q;
reg S_AXI_AREADY_I;
// Internal MI-side signals.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
wire [3-1:0] M_AXI_ASIZE_I;
wire [2-1:0] M_AXI_ABURST_I;
reg [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AQOS_I;
wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ARESET};
end
/////////////////////////////////////////////////////////////////////////////
// Capture SI-Side signals.
//
/////////////////////////////////////////////////////////////////////////////
// Register SI-Side signals.
always @ (posedge ACLK) begin
if ( ARESET ) begin
S_AXI_AID_Q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_AADDR_Q <= {C_AXI_ADDR_WIDTH{1'b0}};
S_AXI_ALEN_Q <= 8'b0;
S_AXI_ASIZE_Q <= 3'b0;
S_AXI_ABURST_Q <= 2'b0;
S_AXI_ALOCK_Q <= 2'b0;
S_AXI_ACACHE_Q <= 4'b0;
S_AXI_APROT_Q <= 3'b0;
S_AXI_AQOS_Q <= 4'b0;
S_AXI_AUSER_Q <= {C_AXI_AUSER_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
S_AXI_AID_Q <= S_AXI_AID;
S_AXI_AADDR_Q <= S_AXI_AADDR;
S_AXI_ALEN_Q <= S_AXI_ALEN;
S_AXI_ASIZE_Q <= S_AXI_ASIZE;
S_AXI_ABURST_Q <= S_AXI_ABURST;
S_AXI_ALOCK_Q <= S_AXI_ALOCK;
S_AXI_ACACHE_Q <= S_AXI_ACACHE;
S_AXI_APROT_Q <= S_AXI_APROT;
S_AXI_AQOS_Q <= S_AXI_AQOS;
S_AXI_AUSER_Q <= S_AXI_AUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Decode the Incoming Transaction.
//
// Extract transaction type and the number of splits that may be needed.
//
// Calculate the step size so that the address for each part of a split can
// can be calculated.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
// Get number of transactions for split INCR.
assign num_transactions = S_AXI_ALEN[4 +: 4];
assign first_beats = {3'b0, S_AXI_ALEN[0 +: 4]} + 7'b01;
// Generate address increment of first split transaction.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: first_step = first_beats << 0;
3'b001: first_step = first_beats << 1;
3'b010: first_step = first_beats << 2;
3'b011: first_step = first_beats << 3;
3'b100: first_step = first_beats << 4;
3'b101: first_step = first_beats << 5;
3'b110: first_step = first_beats << 6;
3'b111: first_step = first_beats << 7;
endcase
end
// Generate address increment for remaining split transactions.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: addr_step = 16'h0010;
3'b001: addr_step = 16'h0020;
3'b010: addr_step = 16'h0040;
3'b011: addr_step = 16'h0080;
3'b100: addr_step = 16'h0100;
3'b101: addr_step = 16'h0200;
3'b110: addr_step = 16'h0400;
3'b111: addr_step = 16'h0800;
endcase
end
// Generate address mask bits to remove split transaction unalignment.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
3'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
3'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
3'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
3'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
3'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
3'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
3'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Transfer SI-Side signals to internal Pipeline Stage.
//
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
if ( ARESET ) begin
access_is_incr_q <= 1'b0;
incr_need_to_split_q <= 1'b0;
num_transactions_q <= 4'b0;
addr_step_q <= 16'b0;
first_step_q <= 16'b0;
size_mask_q <= {C_AXI_ADDR_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
access_is_incr_q <= access_is_incr;
incr_need_to_split_q <= incr_need_to_split;
num_transactions_q <= num_transactions;
addr_step_q <= addr_step;
first_step_q <= first_step;
size_mask_q <= size_mask;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Generate Command Information.
//
// Detect if current transation needs to be split, and keep track of all
// the generated split transactions.
//
//
/////////////////////////////////////////////////////////////////////////////
// Detect when INCR must be split.
assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
( C_SUPPORT_SPLITTING == 1 ) &
( C_SUPPORT_BURSTS == 1 );
// Detect when a command has to be split.
assign need_to_split_q = incr_need_to_split_q;
// Handle progress of split transactions.
always @ (posedge ACLK) begin
if ( ARESET ) begin
split_ongoing <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
split_ongoing <= need_to_split_q & ~last_split;
end
end
end
// Keep track of number of transactions generated.
always @ (posedge ACLK) begin
if ( ARESET ) begin
pushed_commands <= 4'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
pushed_commands <= 4'b0;
end else if ( pushed_new_cmd ) begin
pushed_commands <= pushed_commands + 4'b1;
end
end
end
// Detect last part of a command, split or not.
assign last_incr_split = access_is_incr_q & ( num_transactions_q == pushed_commands );
assign last_split = last_incr_split | ~access_is_incr_q |
( C_SUPPORT_SPLITTING == 0 ) |
( C_SUPPORT_BURSTS == 0 );
assign first_split = (pushed_commands == 4'b0);
// Calculate base for next address.
always @ (posedge ACLK) begin
if ( ARESET ) begin
next_mi_addr = {C_AXI_ADDR_WIDTH{1'b0}};
end else if ( pushed_new_cmd ) begin
next_mi_addr = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
end
end
/////////////////////////////////////////////////////////////////////////////
// Translating Transaction.
//
// Set Split transaction information on all part except last for a transaction
// that needs splitting.
// The B Channel will only get one command for a Split transaction and in
// the Split bflag will be set in that case.
//
// The AWID is extracted and applied to all commands generated for the current
// incomming SI-Side transaction.
//
// The address is increased for each part of a Split transaction, the amount
// depends on the siSIZE for the transaction.
//
// The length has to be changed for Split transactions. All part except tha
// last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
// transaction as length.
//
// Non-Split has untouched address and length information.
//
// Exclusive access are diasabled for a Split transaction because it is not
// possible to guarantee concistency between all the parts.
//
/////////////////////////////////////////////////////////////////////////////
// Assign Split signals.
assign cmd_split_i = need_to_split_q & ~last_split;
assign cmd_b_split_i = need_to_split_q & ~last_split;
// Copy AW ID to W.
assign cmd_id_i = S_AXI_AID_Q;
// Set B Responses to merge.
assign cmd_b_repeat_i = num_transactions_q;
// Select new size or remaining size.
always @ *
begin
if ( split_ongoing & access_is_incr_q ) begin
M_AXI_AADDR_I = next_mi_addr & size_mask_q;
end else begin
M_AXI_AADDR_I = S_AXI_AADDR_Q;
end
end
// Generate the base length for each transaction.
always @ *
begin
if ( first_split | ~need_to_split_q ) begin
M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
end else begin
M_AXI_ALEN_I = 4'hF;
cmd_length_i = 4'hF;
end
end
// Kill Exclusive for Split transactions.
always @ *
begin
if ( need_to_split_q ) begin
M_AXI_ALOCK_I = 2'b00;
end else begin
M_AXI_ALOCK_I = {1'b0, S_AXI_ALOCK_Q};
end
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes ID and Split checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Move SI-side transaction to internal pipe stage.
always @ (posedge ACLK) begin
if (ARESET) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b0;
end else begin
if (areset_d == 2'b10) begin
S_AXI_AREADY_I <= 1'b1;
end else begin
if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
command_ongoing <= 1'b1;
S_AXI_AREADY_I <= 1'b0;
end else if ( pushed_new_cmd & last_split ) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b1;
end
end
end
end
// Generate ready signal.
assign S_AXI_AREADY = S_AXI_AREADY_I;
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn't need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// QOS - Quality of Service is static 0.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID_I = S_AXI_AID_Q;
assign M_AXI_ASIZE_I = S_AXI_ASIZE_Q;
assign M_AXI_ABURST_I = S_AXI_ABURST_Q;
assign M_AXI_ACACHE_I = S_AXI_ACACHE_Q;
assign M_AXI_APROT_I = S_AXI_APROT_Q;
assign M_AXI_AQOS_I = S_AXI_AQOS_Q;
assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Control command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue(s)
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is always OK to let them proceed.
// Or, if no split transaction is ongoing any ID can be allowed.
//
/////////////////////////////////////////////////////////////////////////////
// Keep track of current ID in queue.
always @ (posedge ACLK) begin
if (ARESET) begin
queue_id <= {C_AXI_ID_WIDTH{1'b0}};
multiple_id_non_split <= 1'b0;
split_in_progress <= 1'b0;
end else begin
if ( cmd_push ) begin
// Store ID (it will be matching ID or a "new beginning").
queue_id <= S_AXI_AID_Q;
end
if ( no_cmd & no_b_cmd ) begin
multiple_id_non_split <= 1'b0;
end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
multiple_id_non_split <= 1'b1;
end
if ( no_cmd & no_b_cmd ) begin
split_in_progress <= 1'b0;
end else if ( cmd_push & allow_split_cmd ) begin
split_in_progress <= 1'b1;
end
end
end
// Determine if the command FIFOs are empty.
assign no_cmd = almost_empty & cmd_ready | cmd_empty;
assign no_b_cmd = almost_b_empty & cmd_b_ready | cmd_b_empty;
// Check ID to make sure this command is allowed.
assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
assign cmd_id_check = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
// Command type affects possibility to push immediately or wait.
assign allow_split_cmd = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
assign allow_non_split_cmd = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
assign allow_this_cmd = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
// Check if it is allowed to push more commands.
assign allow_new_cmd = (~cmd_full & ~cmd_b_full & allow_this_cmd) |
cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
assign cmd_b_push = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
cmd_push_block <= 1'b0;
end else if ( cmd_push & mi_stalling ) begin
cmd_push_block <= 1'b1;
end
end
end
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_block <= 1'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
cmd_b_push_block <= 1'b0;
end else if ( cmd_b_push ) begin
cmd_b_push_block <= 1'b1;
end
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue (W/R):
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// The features from Command FIFO can be reduced depending on configuration:
// Read Channel only need the split information.
// Write Channel always require ID information. When bursts are supported
// Split and Length information is also used.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_split_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_split}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_id = {C_AXI_ID_WIDTH{1'b0}};
assign cmd_length = 4'b0;
end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i, cmd_length_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id, cmd_length}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
end else begin : NO_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
assign cmd_length = 4'b0;
end
endgenerate
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_empty <= 1'b1;
cmd_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_push & ~cmd_ready ) begin
// Push only => Increase depth.
cmd_depth <= cmd_depth + 1'b1;
cmd_empty <= 1'b0;
end else if ( ~cmd_push & cmd_ready ) begin
// Pop only => Decrease depth.
cmd_depth <= cmd_depth - 1'b1;
cmd_empty <= almost_empty;
end
end
end
assign almost_empty = ( cmd_depth == 1 );
/////////////////////////////////////////////////////////////////////////////
// Command Queue (B):
//
// Add command queue for B channel only when it is AW channel and both burst
// and splitting is supported.
//
// When turned off the command appears always empty.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
wire cmd_b_valid_i;
wire s_b_ready;
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1+4),
.C_FIFO_TYPE("lut")
)
cmd_b_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
.S_VALID(cmd_b_push),
.S_READY(s_b_ready),
.M_MESG({cmd_b_split, cmd_b_repeat}),
.M_VALID(cmd_b_valid_i),
.M_READY(cmd_b_ready)
);
// Queue is concidered full when not ready.
assign cmd_b_full = ~s_b_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_b_push & ~cmd_b_ready ) begin
// Push only => Increase depth.
cmd_b_depth <= cmd_b_depth + 1'b1;
cmd_b_empty <= 1'b0;
end else if ( ~cmd_b_push & cmd_b_ready ) begin
// Pop only => Decrease depth.
cmd_b_depth <= cmd_b_depth - 1'b1;
cmd_b_empty <= ( cmd_b_depth == 1 );
end
end
end
assign almost_b_empty = ( cmd_b_depth == 1 );
// Assign external signal.
assign cmd_b_valid = cmd_b_valid_i;
end else begin : NO_B_CHANNEL
// Assign external command signals.
assign cmd_b_valid = 1'b0;
assign cmd_b_split = 1'b0;
assign cmd_b_repeat = 4'b0;
// Assign internal command FIFO signals.
assign cmd_b_full = 1'b0;
assign almost_b_empty = 1'b0;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
// Constant FF due to ModelSim behavior.
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID = M_AXI_AID_I;
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AUSER = M_AXI_AUSER_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
endmodule
|
/*
* NAME
* ----
*
* mem_ctl - memory control
*
*
* DESCRIPTION
* -----------
*
* Module for interfacing an Alliance AS6C1008 128x8 RAM chip
* on to an 8-bit data bus and a 7-bit address bus.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module mem_ctl(
input read_n,
write_n,
ce_n,
input [6:0] address_bus,
inout [7:0] data_bus,
inout [7:0] mem_data,
output [16:0] mem_address,
output wire ceh_n,
ce2,
we_n,
oe_n);
// tie unused address bits low
assign mem_address[16:7] = 0;
assign mem_address[6:0] = address_bus;
// if read enabled, drive current data, otherwise go hi Z
// for READ
assign data_bus = (~(ce_n | read_n | ~write_n)) ? mem_data : 8'bz;
// The following line is used to test read cycle, see mem_ctl-test.v
// Comment out the one above when using it.
//assign data_bus = (~(ce_n | read_n | ~write_n)) ? 8'hee : 8'bz;
// for WRITE
assign mem_data = (~(ce_n | write_n | ~read_n)) ? data_bus : 8'bz;
// No "timing" is required for the control lines.
// This just follows the truth table given on page 3 of
// the Alliance RAM data sheet.
assign ceh_n = 1'b0;
assign ce2 = 1'b1;
// for READ
assign oe_n = (~(ce_n | read_n)) ? 1'b0 : 1'b1;
// for WRITE
assign we_n = (~(ce_n | write_n | ~read_n)) ? 1'b0 : 1'b1;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program demonstrates the mixing of reg and memories in l-value
* contatenations.
*/
module main;
reg [3:0] mem [2:0];
reg a, b;
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
{b, mem[1], a} = 6'b0_0000_1;
if (a !== 1'b1) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[1] !== 4'b0000) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
{b, mem[1], a} = 6'b0_1111_0;
if (a !== 1'b0) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[0] !== 4'b0000) begin
$display("FAILED -- mem[0] - %b", mem[0]);
$finish;
end
if (mem[1] !== 4'b1111) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// Copyright 2008, Martin Whitaker.
// This file may be freely copied for any purpose.
module constant_integer_div_mod();
initial begin
$display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d",
31'd10 / 'd3,
31'd11 / 'd3,
31'd12 / 'd3,
31'sd10 / 3,
31'sd11 / 3,
31'sd12 / 3,
-31'sd10 / 3,
-31'sd11 / 3,
-31'sd12 / 3,
31'sd10 / -3,
31'sd11 / -3,
31'sd12 / -3,
-31'sd10 / -3,
-31'sd11 / -3,
-31'sd12 / -3);
$display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d",
65'd10 / 'd3,
65'd11 / 'd3,
65'd12 / 'd3,
65'sd10 / 3,
65'sd11 / 3,
65'sd12 / 3,
-65'sd10 / 3,
-65'sd11 / 3,
-65'sd12 / 3,
65'sd10 / -3,
65'sd11 / -3,
65'sd12 / -3,
-65'sd10 / -3,
-65'sd11 / -3,
-65'sd12 / -3);
$display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d",
31'd10 % 'd3,
31'd11 % 'd3,
31'd12 % 'd3,
31'sd10 % 3,
31'sd11 % 3,
31'sd12 % 3,
-31'sd10 % 3,
-31'sd11 % 3,
-31'sd12 % 3,
31'sd10 % -3,
31'sd11 % -3,
31'sd12 % -3,
-31'sd10 % -3,
-31'sd11 % -3,
-31'sd12 % -3);
$display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d",
65'd10 % 'd3,
65'd11 % 'd3,
65'd12 % 'd3,
65'sd10 % 3,
65'sd11 % 3,
65'sd12 % 3,
-65'sd10 % 3,
-65'sd11 % 3,
-65'sd12 % 3,
65'sd10 % -3,
65'sd11 % -3,
65'sd12 % -3,
-65'sd10 % -3,
-65'sd11 % -3,
-65'sd12 % -3);
end
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_dcache.v
// Title : Data cache
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for user-selected resource usage when implementing
// : cache memory. Additional parameters must be defined when
// : invoking lm32_ram.v
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_DCACHE_ENABLED
`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
`define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
`define LM32_DC_TAGS_VALID_RNG 0
`define LM32_DC_STATE_RNG 2:0
`define LM32_DC_STATE_FLUSH 3'b001
`define LM32_DC_STATE_CHECK 3'b010
`define LM32_DC_STATE_REFILL 3'b100
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_dcache (
// ----- Inputs -----
clk_i,
rst_i,
stall_a,
stall_x,
stall_m,
address_x,
address_m,
load_q_m,
store_q_m,
store_data,
store_byte_select,
refill_ready,
refill_data,
dflush,
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
refilling,
load_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // Stall A stage
input stall_x; // Stall X stage
input stall_m; // Stall M stage
input [`LM32_WORD_RNG] address_x; // X stage load/store address
input [`LM32_WORD_RNG] address_m; // M stage load/store address
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input [`LM32_WORD_RNG] store_data; // Data to store
input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
input refill_ready; // Indicates next word of refill data is ready
input [`LM32_WORD_RNG] refill_data; // Refill data
input dflush; // Indicates cache should be flushed
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output stall_request; // Request pipeline be stalled because cache is busy
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
reg restart_request;
output refill_request; // Request a refill
reg refill_request;
output [`LM32_WORD_RNG] refill_address; // Address to refill from
reg [`LM32_WORD_RNG] refill_address;
output refilling; // Indicates if the cache is currently refilling
reg refilling;
output [`LM32_WORD_RNG] load_data; // Data read from cache
wire [`LM32_WORD_RNG] load_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire read_port_enable; // Cache memory read port clock enable
wire write_port_enable; // Cache memory write port clock enable
wire [0:associativity-1] way_tmem_we; // Tag memory write enable
wire [0:associativity-1] way_dmem_we; // Data memory write enable
wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
wire [0:associativity-1] way_valid; // Indicates which ways are valid
wire [0:associativity-1] way_match; // Indicates which ways matched
wire miss; // Indicates no ways matched
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
wire flushing; // Indicates if cache is currently flushing
wire check; // Indicates if cache is currently checking for hits/misses
wire refill; // Indicates if cache is currently refilling
wire valid_store; // Indicates if there is a valid store instruction
reg [associativity-1:0] refill_way_select; // Which way should be refilled
reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
wire last_refill; // Indicates when on last cycle of cache refill
reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
genvar i, j;
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
// Way data
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin : data_memories
lm32_ram
#(
// ----- Parameters -------
.data_width (32),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH),
`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
.RAM_IMPLEMENTATION ("EBR"),
.RAM_TYPE ("RAM_DP_TRUE")
`else
`ifdef CFG_DCACHE_DAT_USE_SLICE
.RAM_IMPLEMENTATION ("SLICE")
`else
.RAM_IMPLEMENTATION ("AUTO")
`endif
`endif
) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (dmem_read_address),
.enable_read (read_port_enable),
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i]),
.write_data (dmem_write_data),
// ----- Outputs -------
.read_data (way_data[i])
);
end
else
begin
for (j = 0; j < 4; j = j + 1)
begin : byte_memories
lm32_ram
#(
// ----- Parameters -------
.data_width (8),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH),
`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
.RAM_IMPLEMENTATION ("EBR"),
.RAM_TYPE ("RAM_DP_TRUE")
`else
`ifdef CFG_DCACHE_DAT_USE_SLICE
.RAM_IMPLEMENTATION ("SLICE")
`else
.RAM_IMPLEMENTATION ("AUTO")
`endif
`endif
) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (dmem_read_address),
.enable_read (read_port_enable),
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
.write_data (dmem_write_data[(j+1)*8-1:j*8]),
// ----- Outputs -------
.read_data (way_data[i][(j+1)*8-1:j*8])
);
end
end
// Way tags
lm32_ram
#(
// ----- Parameters -------
.data_width (`LM32_DC_TAGS_WIDTH),
.address_width (`LM32_DC_TMEM_ADDR_WIDTH),
`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
.RAM_IMPLEMENTATION ("EBR"),
.RAM_TYPE ("RAM_DP_TRUE")
`else
`ifdef CFG_DCACHE_DAT_USE_SLICE
.RAM_IMPLEMENTATION ("SLICE")
`else
.RAM_IMPLEMENTATION ("AUTO")
`endif
`endif
) way_0_tag_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (tmem_read_address),
.enable_read (read_port_enable),
.write_address (tmem_write_address),
.enable_write (`TRUE),
.write_enable (way_tmem_we[i]),
.write_data (tmem_write_data),
// ----- Outputs -------
.read_data ({way_tag[i], way_valid[i]})
);
end
endgenerate
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Compute which ways in the cache match the address being read
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
end
endgenerate
// Select data from way that matched the address being read
generate
if (associativity == 1)
begin : data_1
assign load_data = way_data[0];
end
else if (associativity == 2)
begin : data_2
assign load_data = way_match[0] ? way_data[0] : way_data[1];
end
endgenerate
generate
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin
// Select data to write to data memories
always @(*)
begin
if (refill == `TRUE)
dmem_write_data = refill_data;
else
begin
dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
end
end
end
else
begin
// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
always @(*)
begin
if (refill == `TRUE)
dmem_write_data = refill_data;
else
dmem_write_data = store_data;
end
end
endgenerate
// Compute address to use to index into the data memories
generate
if (bytes_per_line > 4)
assign dmem_write_address = (refill == `TRUE)
? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
: address_m[`LM32_DC_ADDR_IDX_RNG];
else
assign dmem_write_address = (refill == `TRUE)
? refill_address[`LM32_DC_ADDR_SET_RNG]
: address_m[`LM32_DC_ADDR_IDX_RNG];
endgenerate
assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
// Compute address to use to index into the tag memories
assign tmem_write_address = (flushing == `TRUE)
? flush_set
: refill_address[`LM32_DC_ADDR_SET_RNG];
assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
// Compute signal to indicate when we are on the last refill accesses
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
assign last_refill = `TRUE;
endgenerate
// Compute data and tag memory access enable
assign read_port_enable = (stall_x == `FALSE);
assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
// Determine when we have a valid store
assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
// Compute data and tag memory write enables
generate
if (associativity == 1)
begin : we_1
assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
end
else
begin : we_2
assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
end
endgenerate
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
// Signals that indicate which state we are in
assign flushing = state[0];
assign check = state[1];
assign refill = state[2];
assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
assign stall_request = (check == `FALSE);
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Record way selected for replacement on a cache miss
generate
if (associativity >= 2)
begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1};
else
begin
if (refill_request == `TRUE)
refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]};
end
end
end
endgenerate
// Record whether we are currently refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refilling <= #1 `FALSE;
else
refilling <= #1 refill;
end
// Instruction cache control FSM
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= #1 `LM32_DC_STATE_FLUSH;
flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
refill_request <= #1 `FALSE;
refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}};
restart_request <= #1 `FALSE;
end
else
begin
case (state)
// Flush the cache
`LM32_DC_STATE_FLUSH:
begin
if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
state <= #1 `LM32_DC_STATE_CHECK;
flush_set <= #1 flush_set - 1'b1;
end
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
if (stall_a == `FALSE)
restart_request <= #1 `FALSE;
if (miss == `TRUE)
begin
refill_request <= #1 `TRUE;
refill_address <= #1 address_m;
state <= #1 `LM32_DC_STATE_REFILL;
end
else if (dflush == `TRUE)
state <= #1 `LM32_DC_STATE_FLUSH;
end
// Refill a cache line
`LM32_DC_STATE_REFILL:
begin
refill_request <= #1 `FALSE;
if (refill_ready == `TRUE)
begin
if (last_refill == `TRUE)
begin
restart_request <= #1 `TRUE;
state <= #1 `LM32_DC_STATE_CHECK;
end
end
end
endcase
end
end
generate
if (bytes_per_line > 4)
begin
// Refill offset
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_offset <= #1 {addr_offset_width{1'b0}};
else
begin
case (state)
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
if (miss == `TRUE)
refill_offset <= #1 {addr_offset_width{1'b0}};
end
// Refill a cache line
`LM32_DC_STATE_REFILL:
begin
if (refill_ready == `TRUE)
refill_offset <= #1 refill_offset + 1'b1;
end
endcase
end
end
end
endgenerate
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_TB_V
`define SKY130_FD_SC_LS__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ls__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_TB_V
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Creator: Kris Kalavantavanich ([email protected])
// Create Date: 05/22/2017 08:17:18 PM
// Design Name: SPI Communication Master
// Module Name: spiCommMaster
// Project Name: SD_2017
// Target Devices: Basys3
// Description: Communication Master manages Command and Response loop.
// Doesn't do data receive/send separately (managed by main module).
// Dependencies: main.v
// Revision: 1.02
// Revision 1.02 - Debug
// Revision 1.00 - Finished Read Operation
// Revision 0.01 - File Created
// Additional Comments:
// - Doesn't interpret response -- (Master of this)'s job.
// - All signals are synchronous (including reset). Reset without clock means nothing.
// --- Except enable signal
//////////////////////////////////////////////////////////////////////////////////
module spiCommMaster(
input cpuClock, // CPU Clock Input
input enable, // If LOW => all outputs will be Z (high impedence) (Active HIGH)
input reset, // IF HIGH => Reset to ST_IDLE (Active HIGH)
input spiClockEn, // Enable SPI Clock (SD_SDLK) (Active HIGH)
input spiClockBS, // 0 = normal, 1 = byte sync mode
output errorInterrupt, // HIGH <= Error has occurred
output [3:0] errorType, // output the type of error
output [3:0] errorState, // output the last error if an error occurs
input cmdTransmitBit, // Transmit bit of CMD (second MSB of CMD)
input [5:0] cmdIndex, // CMD Index
input [31:0] cmdArgument, // CMD Argument(s)
input [1:0] readMode, // Reading Mode (00 = readSingle, 01 = readDouble, 10 = readWide, 11 = reserved)
output [39:0] readResponse, // Response of Slave SPI Device. If response is less than 40-bits, response is aligned right and left-filled with 0.
input commStart, // (Signal) Start Communication Cycle from ST_IDLE. posedge = Start, negedge = Stop.
output commFinish, // (Signal) Finished Communication Cycle and waiting for Response to be fetched. HIGH only if ST_FINISH.
input SD_MISO, // SD Master In Slave Out
input SD_CD, // SD Chip Detected
input SD_WP, // SD Write Protect
output SD_SCLK, // SD SPI Clock (Controlled only with spiClockEn; not by enable)
output SD_MOSI, // SD Master Out Slave In
output SD_CS // SD Chip Select
);
// Common Acronyms //
// ST = State
// STA = Start
// STO = Stop
// EN = Enable (out value or high impedence)
// RST = Reset
// FIN = Finished
// OUT = wire data out
// BUFF = reg data
// DEFINE CONSTANTS //
localparam ST_IDLE = 4'b0000; // Wait for `commStart` HIGH
localparam ST_GEN_CRC = 4'b0010; // Wait for previous cooldown and start CRC Generation
localparam ST_SEND = 4'b0100; // Wait for CRC generation and start sending
localparam ST_READ = 4'b0110; // Wait for Sending finish and start reading
localparam ST_INPUT = 4'b1000; // Wait for Reading
localparam ST_COOLDOWN = 4'b1010; // Cooldown Requied (does nothing)
localparam ST_FINISH = 4'b1100; // Finish and wait for `commStart` LOW
localparam ST_ERROR = 4'b1111; // Error state
localparam ER_UNKN = 4'b0000; // No Error / Unknown Error
localparam ER_IVST = 4'b0001; // Invalid State Error
localparam ER_TMOT = 4'b0010; // Timeout Error
localparam ER_RESP = 4'b0100; // Response Error
localparam ER_UDEV = 4'b0110; // Unknown Device Error
// STATE //
reg [3:0] CST = ST_IDLE; // Current State
reg [3:0] NST = ST_IDLE; // Next State
// ERRORS //
reg EINT = 0; // Error Interrupt
reg EINTE = 1; // Error Interrupt Enable
reg [3:0] EST = 0; // Internal Error State (State before ST_ERROR)
reg [3:0] ETYPE = 0; // Error Type
assign errorInterrupt = enable ? (EINTE ? EINT : 1'b0) : 1'bZ;
assign errorType = enable ? ETYPE : 4'bZ;
assign errorState = enable ? EST : 4'bZ;
// BUFFERED ENABLE OUTPUTS //
wire [39:0] readData; // Internal Read Response Wiring
assign readResponse = enable ? readData : 40'bZ;
wire MOSI; // MOSI Data
reg MOSI_EN = 0; // MOSI Enable (Active HIGH)
assign SD_MOSI = enable ? (MOSI_EN ? MOSI : 1'b1): 1'bZ;
reg CS = 1; // Chip Select (Active LOW)
assign SD_CS = enable ? CS : 1'bZ;
assign commFinish = (CST == 4'b1100);
// SPI CLOCK //
wire spiClock, _spiClock; // _spiClock is without enable, spiClock is with enable
clockDiv #(8) SPICLKM (cpuClock, _spiClock); // run _spiClock at 390.6 kHz
//clockDiv #(9) c4(cpuClock, _spiClock); // run _spiClock at 195.3 kHz
wire byte_sync;
assign spiClock = (spiClockEn && enable) ? byte_sync & _spiClock : 1; // spiClock is active low
assign SD_SCLK = (spiClockEn ? byte_sync & _spiClock : 1);
// SPI TIMEOUT TIMER (TMTO)//
localparam TMTO_bitSize = 16;
reg TMTO_RST = 1;
wire [TMTO_bitSize-1 :0] TMTO_OUT;
wire TMTO_OV;
wire [TMTO_bitSize-1 :0] TMTO_VAL; // Value for timeout
wire TMTO_TOI; // Timeout Interrupt
assign TMTO_TOI = (TMTO_OUT >= TMTO_VAL);
counter #(TMTO_bitSize) TMTOM (_spiClock, TMTO_RST, TMTO_OUT, TMTO_OV);
// SPI COOLDOWN TIMER (TMWC)//
localparam TMWC_bitSize = 4;
reg TMWC_RST = 1;
wire [TMWC_bitSize-1 :0] TMWC_OUT;
wire TMWC_OV; // set whether cooldown timer finished
wire TMWC_MSB; // set whether SD_CS is on
assign TMWC_MSB = TMWC_OUT[TMWC_bitSize - 1];
counter #(TMWC_bitSize) TMWCM (_spiClock, TMWC_RST, TMWC_OUT, TMWC_OV);
// SPI BYTE SYNC TIMER (TMBS) //
// every 9 bit 1 bit is down
localparam TMBS_bitSize = 4;
reg TMBS_RST = 1;
wire [TMBS_bitSize-1 :0] TMBS_OUT;
wire TMBS_OV; // set whether cooldown timer finished
wire TMBS_MSB; // set whether SD_CS is on
counter #(TMBS_bitSize, 8) TMBSM (_spiClock, TMBS_RST, TMBS_OUT, TMBS_OV);
wire TMBS_TOGGLE;
assign TMBS_TOGGLE = TMBS_OUT[3];
assign byte_sync = spiClockBS ? ~TMBS_TOGGLE : 1'b1;
reg [1:0] spiClockBS_BUFF = 0;
always @ (negedge _spiClock) begin
if ({spiClockBS_BUFF, spiClockBS} == 2'b01) begin // posedge
TMBS_RST = 0;
end else if ({spiClockBS_BUFF, spiClockBS} == 2'b10) begin // negedge
TMBS_RST = 1;
end
spiClockBS_BUFF <= {spiClockBS_BUFF, spiClockBS};
end
// COMMANDS //
// Constructed from (Inputs to Module)
wire [5:0] CMD_INDEX; // Command Index (CMD0 - CMD63)
wire [31:0] CMD_ARG; // 32-bit Command Argument
wire [6:0] CMD_CRC; // CRC-7 Code
wire CMD_TRANSMIT; // 0 => Receiver, 1 => Transmitter
wire [47:0] CMD; // 48-bit command
assign CMD_INDEX = cmdIndex;
assign CMD_ARG = cmdArgument;
assign CMD_TRANSMIT = cmdTransmitBit;
assign CMD = {1'b0, CMD_TRANSMIT, CMD_INDEX, CMD_ARG, CMD_CRC, 1'b1};
// SPI SEND (SPS) //
reg SPS_STA = 0;
reg [47:0] SPS_BUFF;
wire SPS_FIN;
spiSend SPSM (spiClock, SPS_STA, SPS_BUFF, MOSI, SPS_FIN);
// SPI READ (SPR) //
// Normal Response (Single Byte) (SPRS)
reg SPRS_STA = 0; // SPRSM Start
wire [7:0] SPRS_OUT; // Output from SPRSM (Can be high impedence)
wire SPRS_FIN; // SPRSM Finish
spiRead SPRSM (spiClock, SPRS_STA, SD_MISO, SPRS_FIN, SPRS_OUT, 1'b1);
// Double Byte Response (Double Byte) (SPRD)
reg SPRD_STA = 0;
wire [15:0] SPRD_OUT;
wire SPRD_FIN;
spiRead #(2) SPRDM (spiClock, SPRD_STA, SD_MISO, SPRD_FIN, SPRD_OUT, 1'b1);
// Wide Response (R3 / R7) -- 5 bytes (R1 + Rn) (SPRW)
reg SPRW_STA = 0;
wire [39:0] SPRW_OUT;
wire SPRW_FIN;
spiRead #(5) SPRWM (spiClock, SPRW_STA, SD_MISO, SPRW_FIN, SPRW_OUT, 1'b1);
// SPI Reading -- Common //
wire SPR_FIN;
assign SPR_FIN = (readMode == 2'b00 ? SPRS_FIN : (readMode == 2'b01 ? SPRD_FIN : SPRW_FIN));
reg [39:0] SPR_BUFF;
assign readData = SPR_BUFF;
assign TMTO_VAL = (readMode == 2'b00 ? 100 : (readMode == 2'b01 ? 200 : 500));
// 'Response' CRC-7 (CRCR) //
// uses CPU CLOCK
wire [39:0] CRCR_IN;
reg CRCR_EN = 0;
wire CRCR_FIN;
wire [6:0] CRCR_OUT;
wire [2:0] CRCR_ST;
crcGenMaster CRCRM (cpuClock, CRCR_EN, CRCR_IN, 8'b10001001, CRCR_OUT, CRCR_FIN, CRCR_ST);
assign CRCR_IN = {1'b0, CMD_TRANSMIT, CMD_INDEX, CMD_ARG};
assign CMD_CRC = CRCR_OUT;
// MAIN STATE MACHINE //
always @ (negedge cpuClock) begin
if (reset) begin
NST <= ST_IDLE; // Set Next State to IDLE
EINT <= 0; // Clear Error Interrupt
ETYPE <= 0; // Clear Error Type
EST <= 0; // Clear Error State
MOSI_EN <= 0; // Disable MOSI
CS <= 1; // Disable Chip Select
TMTO_RST <= 1; // Stop Timeout Timer
TMWC_RST <= 1; // Stop Warmup/Cooldown Timer
SPS_STA <= 0; // Stop Sending (SPS)
SPS_BUFF <= 0; // Clear Sending Buffer
SPRS_STA <= 0; // Stop Reading Single
SPRD_STA <= 0; // Stop Reading Double
SPRW_STA <= 0; // Stop Reading Wide
SPR_BUFF <= 0; // Clear Reading Buffer
CRCR_EN <= 0; // Disable CRC-7 Generation
end else begin
case (CST)
ST_IDLE: begin
if (commStart) begin
NST <= ST_GEN_CRC;
end
end
ST_GEN_CRC: begin // Start CRC generation if previous cooldown finished. CMD data *must* be stable and complete.
if (!TMWC_OV) begin
CS <= 1; // CS HIGH before warmup
TMWC_RST <= 0; // Start warmup/cooldown timer
CRCR_EN <= 1; // Start CRC7 generation
NST <= ST_SEND; // goto 'send' state
end
end
ST_SEND: begin // Wait for CRC generation/warmup and start sending.
if (CRCR_FIN && TMWC_OV) begin
TMWC_RST <= 1; // Stop warmup/cooldown timer
CS <= 0; // Chip Select Must be LOW
SPS_STA <= 1; // Start Sending
SPS_BUFF <= CMD; // Copy CMD to SPS Internal Buffer
MOSI_EN <= 1; // Enable MOSI
CRCR_EN <= 0; // Stop CRC7 generation
NST <= ST_READ; // goto 'read' state
end else begin
CS <= ~TMWC_MSB; // Set CS to be half HIGH, half LOW for TMWC duration
end
end
ST_READ: begin // Wait for sending and start reading.
if (SPS_FIN) begin
SPS_STA <= 0; // Stop Sending
MOSI_EN <= 0; // Disable MOSI
TMTO_RST <= 0; // Start timeout timer (TMTO)
case (readMode) // Start Reader
2'b00: SPRS_STA <= 1;
2'b01: SPRD_STA <= 1;
default: SPRW_STA <= 1;
endcase
NST <= ST_INPUT;
end
end
ST_INPUT: begin // Wait for Reading
if (TMTO_TOI) begin
NST <= ST_ERROR;
ETYPE <= ER_TMOT; // Timeout Error
EINT <= 1; // Raise Error Interrupt
EST <= CST; // Store Error State
end else if (SPR_FIN) begin
TMTO_RST <= 1; // Stop Timeout Timer
TMWC_RST <= 0; // Start Cooldown Timer
case (readMode) // Copy data out to buffer
2'b00: SPR_BUFF <= {32'b0, SPRS_OUT};
2'b01: SPR_BUFF <= {24'b0, SPRD_OUT};
default: SPR_BUFF <= SPRW_OUT;
endcase
case (readMode) // Stop Readers
2'b00: SPRS_STA <= 0;
2'b01: SPRD_STA <= 0;
default: SPRW_STA <= 0;
endcase
NST <= ST_COOLDOWN; // goto `cooldown` state
end
end
ST_COOLDOWN: begin
if (TMWC_OV) begin
TMWC_RST <= 1; // Stop Cooldown Timer
CS <= 1; // CS HIGH After cooldown
NST <= ST_FINISH; // goto `finish` state
end else begin
CS <= TMWC_MSB; // Set value of CS to be half LOW, half HIGH during TMWC duration
end
end
ST_FINISH: begin // Finished Comm Cycle State. Waiting for start LOW
if (!commStart) begin
NST <= ST_IDLE;
end
end
ST_ERROR: begin // Error State. Will stay in this state until `reset` HIGH
end
default: begin
NST <= ST_ERROR;
ETYPE <= ER_IVST;
EST <= 0;
end
endcase
end
end // MAIN STATE MACHINE//
always @ (posedge cpuClock) begin
CST <= NST;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg [127:0] in;
check #(48) check48 (.*);
check #(31) check31 (.*);
check #(32) check32 (.*);
check #(63) check63 (.*);
check #(64) check64 (.*);
check #(96) check96 (.*);
check #(128) check128 (.*);
always_comb begin
if (crc[2:0] == 0) in = '0;
else if (crc[2:0] == 1) in = ~'0;
else if (crc[2:0] == 2) in = 128'b1;
else if (crc[2:0] == 3) in = ~ 128'b1;
else begin
in = {crc, crc};
if (crc[3]) in[31:0] = '0;
if (crc[4]) in[63:32] = '0;
if (crc[5]) in[95:64] = '0;
if (crc[6]) in[127:96] = '0;
if (crc[7]) in[31:0] = ~'0;
if (crc[8]) in[63:32] = ~'0;
if (crc[9]) in[95:64] = ~'0;
if (crc[10]) in[127:96] = ~'0;
end
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x\n", $time, cyc, in);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc == 99) begin
`checkr(check48.sum, 14574057015683440.000000);
`checkr(check31.sum, 114141374814.000000);
`checkr(check32.sum, 236547942750.000000);
`checkr(check63.sum, 513694866079917670400.000000);
`checkr(check64.sum, 1002533584033221181440.000000);
`checkr(check96.sum, 4377373669974269260279175970816.000000);
`checkr(check128.sum, 18358899571808044815012294240949812330496.000000);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module check(/*AUTOARG*/
// Inputs
in, clk, cyc
);
parameter WIDTH = 128;
input [127:0] in;
wire [WIDTH-1:0] ci = in[WIDTH-1:0];
wire signed [WIDTH-1:0] cis = in[WIDTH-1:0];
real r;
real rs;
always_comb r = ci;
always_comb rs = cis;
input clk;
input integer cyc;
real sum;
always_ff @ (negedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum);
`endif
if (cyc < 10) sum <= 0;
else sum <= sum + r + rs;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module defines an iterator over work item space.
// Semantics:
//
// - Items for the same workgroup are issued contiguously.
// That is, items from different workgroups are never interleaved.
//
// - Subject to the previous constraint, we make the lower
// order ids (e.g. local_id[0]) iterate faster than
// higher order (e.g. local_id[2])
//
// - Id values start at zero and only increase.
//
// - Behaviour is unspecified if "issue" is asserted more than
// global_id[0] * global_id[1] * global_id[2] times between times
// that "start" is asserted.
module acl_work_item_iterator #(parameter WIDTH=32) (
input clock,
input resetn,
input start, // Assert to restart the iterators
input issue, // Assert to issue another item, i.e. advance the counters
// We assume these values are steady while "start" is not asserted.
input [WIDTH-1:0] local_size[2:0],
input [WIDTH-1:0] global_size[2:0],
// inputs from id_iterator
input [WIDTH-1:0] global_id_base[2:0],
// The counter values we export.
output reg [WIDTH-1:0] local_id[2:0],
output reg [WIDTH-1:0] global_id[2:0],
// output to id_iterator
output last_in_group
);
// This is the invariant relationship between the various ids.
// Keep these around for debugging.
wire [WIDTH-1:0] global_total = global_id[0] + global_size[0] * ( global_id[1] + global_size[1] * global_id[2] );
wire [WIDTH-1:0] local_total = local_id[0] + local_size[0] * ( local_id[1] + local_size[1] * local_id[2] );
function [WIDTH-1:0] incr_lid ( input [WIDTH-1:0] old_lid, input to_incr, input last );
if ( to_incr )
if ( last )
incr_lid = {WIDTH{1'b0}};
else
incr_lid = old_lid + 2'b01;
else
incr_lid = old_lid;
endfunction
//////////////////////////////////
// Handle local ids.
reg [WIDTH-1:0] max_local_id[2:0];
wire last_local_id[2:0];
assign last_local_id[0] = (local_id[0] == max_local_id[0] );
assign last_local_id[1] = (local_id[1] == max_local_id[1] );
assign last_local_id[2] = (local_id[2] == max_local_id[2] );
assign last_in_group = last_local_id[0] & last_local_id[1] & last_local_id[2];
wire bump_local_id[2:0];
assign bump_local_id[0] = (max_local_id[0] != 0);
assign bump_local_id[1] = (max_local_id[1] != 0) && last_local_id[0];
assign bump_local_id[2] = (max_local_id[2] != 0) && last_local_id[0] && last_local_id[1];
// Local id register updates.
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
max_local_id[0] <= {WIDTH{1'b0}};
max_local_id[1] <= {WIDTH{1'b0}};
max_local_id[2] <= {WIDTH{1'b0}};
end else if ( start ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
max_local_id[0] <= local_size[0] - 2'b01;
max_local_id[1] <= local_size[1] - 2'b01;
max_local_id[2] <= local_size[2] - 2'b01;
end else // We presume that start and issue are mutually exclusive.
begin
if ( issue ) begin
local_id[0] <= incr_lid (local_id[0], bump_local_id[0], last_local_id[0]);
local_id[1] <= incr_lid (local_id[1], bump_local_id[1], last_local_id[1]);
local_id[2] <= incr_lid (local_id[2], bump_local_id[2], last_local_id[2]);
end
end
end
// goes high one cycle after last_in_group. stays high until
// next cycle where 'issue' is high.
reg just_seen_last_in_group;
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
just_seen_last_in_group <= 1'b1;
else if ( start )
just_seen_last_in_group <= 1'b1;
else if (last_in_group & issue)
just_seen_last_in_group <= 1'b1;
else if (issue)
just_seen_last_in_group <= 1'b0;
else
just_seen_last_in_group <= just_seen_last_in_group;
end
//////////////////////////////////
// Handle global ids.
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else if ( start ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else // We presume that start and issue are mutually exclusive.
begin
if ( issue ) begin
if ( !last_in_group ) begin
if ( just_seen_last_in_group ) begin
// get new global_id starting point from dispatcher.
// global_id_base will be one cycle late, so get it on the next cycle
// after encountering last element in previous group.
// id iterator will know to ignore the global id value on that cycle.
global_id[0] <= global_id_base[0] + bump_local_id[0];
global_id[1] <= global_id_base[1] + bump_local_id[1];
global_id[2] <= global_id_base[2] + bump_local_id[2];
end else begin
if ( bump_local_id[0] ) global_id[0] <= (last_local_id[0] ? (global_id[0] - max_local_id[0]) : (global_id[0] + 2'b01));
if ( bump_local_id[1] ) global_id[1] <= (last_local_id[1] ? (global_id[1] - max_local_id[1]) : (global_id[1] + 2'b01));
if ( bump_local_id[2] ) global_id[2] <= (last_local_id[2] ? (global_id[2] - max_local_id[2]) : (global_id[2] + 2'b01));
end
end
end
end
end
endmodule
// vim:set filetype=verilog:
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:03 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_dm_iob.v,v 1.1 2011/06/02 07:18:03 mishra Exp $
**$Date: 2011/06/02 07:18:03 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_dm_iob.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_dm_iob #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCWL = 5, // CAS Write Latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter WRLVL = "ON", // "OFF" for "DDR3" component interface
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_HP_MODE = "ON", // IODELAY High Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem,
input clk,
input clk_rsync,
input rst,
// IODELAY I/F
input [4:0] dlyval,
input dm_ce,
input inv_dqs,
input [1:0] wr_calib_dly,
input mask_data_rise0,
input mask_data_fall0,
input mask_data_rise1,
input mask_data_fall1,
output ddr_dm
);
// Set performance mode for IODELAY (power vs. performance tradeoff)
localparam HIGH_PERFORMANCE_MODE
= (IODELAY_HP_MODE == "OFF") ? "FALSE" :
((IODELAY_HP_MODE == "ON") ? "TRUE" : "ILLEGAL");
wire dm_odelay;
wire dm_oq;
reg mask_data_fall0_r1;
reg mask_data_fall0_r2;
reg mask_data_fall0_r3;
reg mask_data_fall0_r4;
reg mask_data_fall1_r1;
reg mask_data_fall1_r2;
reg mask_data_fall1_r3;
reg mask_data_fall1_r4;
reg mask_data_rise0_r1;
reg mask_data_rise0_r2;
reg mask_data_rise0_r3;
reg mask_data_rise0_r4;
reg mask_data_rise1_r1;
reg mask_data_rise1_r2;
reg mask_data_rise1_r3;
reg mask_data_rise1_r4;
reg out_d1;
reg out_d2;
reg out_d3;
reg out_d4;
//***************************************************************************
// Data Mask Bitslip
//***************************************************************************
// dfi_wrdata_en0 - even clk cycles channel 0
// dfi_wrdata_en1 - odd clk cycles channel 1
// tphy_wrlat set to 0 clk cycle for CWL = 5,6,7,8
// Valid dfi_wrdata* sent 1 clk cycle after dfi_wrdata_en* is asserted
// mask_data_rise0 - first rising edge data mask (rise0)
// mask_data_fall0 - first falling edge data mask (fall0)
// mask_data_rise1 - second rising edge data mask (rise1)
// mask_data_fall1 - second falling edge data mask (fall1)
always @(posedge clk) begin
if (DRAM_TYPE == "DDR3")begin
mask_data_rise0_r1 <= #TCQ dm_ce & mask_data_rise0;
mask_data_fall0_r1 <= #TCQ dm_ce & mask_data_fall0;
mask_data_rise1_r1 <= #TCQ dm_ce & mask_data_rise1;
mask_data_fall1_r1 <= #TCQ dm_ce & mask_data_fall1;
end else begin
mask_data_rise0_r1 <= #TCQ mask_data_rise0;
mask_data_fall0_r1 <= #TCQ mask_data_fall0;
mask_data_rise1_r1 <= #TCQ mask_data_rise1;
mask_data_fall1_r1 <= #TCQ mask_data_fall1;
end
mask_data_rise0_r2 <= #TCQ mask_data_rise0_r1;
mask_data_fall0_r2 <= #TCQ mask_data_fall0_r1;
mask_data_rise1_r2 <= #TCQ mask_data_rise1_r1;
mask_data_fall1_r2 <= #TCQ mask_data_fall1_r1;
mask_data_rise0_r3 <= #TCQ mask_data_rise0_r2;
mask_data_fall0_r3 <= #TCQ mask_data_fall0_r2;
mask_data_rise1_r3 <= #TCQ mask_data_rise1_r2;
mask_data_fall1_r3 <= #TCQ mask_data_fall1_r2;
mask_data_rise0_r4 <= #TCQ mask_data_rise0_r3;
mask_data_fall0_r4 <= #TCQ mask_data_fall0_r3;
mask_data_rise1_r4 <= #TCQ mask_data_rise1_r3;
mask_data_fall1_r4 <= #TCQ mask_data_fall1_r3;
end
// Different nCWL values: 5, 6, 7, 8, 9
generate
if (DRAM_TYPE == "DDR3")begin: gen_dm_ddr3_write_lat
if ((nCWL == 5) | (nCWL == 7) | (nCWL == 9)) begin: gen_dm_ncwl5_odd
always @(posedge clk) begin
if (WRLVL == "OFF") begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end else begin
// write command sent by MC on channel1
// D3,D4 inputs of the OCB used to send write command to DDR3
// Shift bitslip logic by 1 or 2 clk_mem cycles
// Write calibration currently supports only upto 2 clk_mem cycles
case ({wr_calib_dly[1:0], inv_dqs})
// 0 clk_mem delay required as per write calibration
3'b000: begin
out_d1 <= #TCQ mask_data_fall0_r1;
out_d2 <= #TCQ mask_data_rise1_r1;
out_d3 <= #TCQ mask_data_fall1_r1;
out_d4 <= #TCQ mask_data_rise0;
end
// DQS inverted during write leveling
3'b001: begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end
// 1 clk_mem delay required as per write cal
3'b010: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
// DQS inverted during write leveling
// 1 clk_mem delay required per write cal
3'b011: begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end
// 2 clk_mem delay required as per write cal
3'b100: begin
out_d1 <= #TCQ mask_data_fall0_r2;
out_d2 <= #TCQ mask_data_rise1_r2;
out_d3 <= #TCQ mask_data_fall1_r2;
out_d4 <= #TCQ mask_data_rise0_r1;
end
// DQS inverted during write leveling
// 2 clk_mem delay required as per write cal
3'b101: begin
out_d1 <= #TCQ mask_data_rise0_r2;
out_d2 <= #TCQ mask_data_fall0_r2;
out_d3 <= #TCQ mask_data_rise1_r2;
out_d4 <= #TCQ mask_data_fall1_r2;
end
// 3 clk_mem delay required as per write cal
3'b110: begin
out_d1 <= #TCQ mask_data_fall1_r3;
out_d2 <= #TCQ mask_data_rise0_r2;
out_d3 <= #TCQ mask_data_fall0_r2;
out_d4 <= #TCQ mask_data_rise1_r2;
end
// DQS inverted during write leveling
// 3 clk_mem delay required as per write cal
3'b111: begin
out_d1 <= #TCQ mask_data_rise1_r3;
out_d2 <= #TCQ mask_data_fall1_r3;
out_d3 <= #TCQ mask_data_rise0_r2;
out_d4 <= #TCQ mask_data_fall0_r2;
end
// defaults to 0 clk_mem delay
default: begin
out_d1 <= #TCQ mask_data_fall0_r1;
out_d2 <= #TCQ mask_data_rise1_r1;
out_d3 <= #TCQ mask_data_fall1_r1;
out_d4 <= #TCQ mask_data_rise0;
end
endcase
end
end
end else if ((nCWL == 6) | (nCWL == 8)) begin: gen_dm_ncwl_even
always @(posedge clk) begin
if (WRLVL == "OFF") begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end else begin
// write command sent by MC on channel1
// D3,D4 inputs of the OCB used to send write command to DDR3
// Shift bitslip logic by 1 or 2 clk_mem cycles
// Write calibration currently supports only upto 2 clk_mem cycles
case ({wr_calib_dly[1:0], inv_dqs})
// 0 clk_mem delay required as per write calibration
// could not test 0011 case
3'b000: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
// DQS inverted during write leveling
3'b001: begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end
// 1 clk_mem delay required as per write cal
3'b010: begin
out_d1 <= #TCQ mask_data_fall0_r2;
out_d2 <= #TCQ mask_data_rise1_r2;
out_d3 <= #TCQ mask_data_fall1_r2;
out_d4 <= #TCQ mask_data_rise0_r1;
end
// DQS inverted during write leveling
// 1 clk_mem delay required as per write cal
3'b011: begin
out_d1 <= #TCQ mask_data_rise0_r2;
out_d2 <= #TCQ mask_data_fall0_r2;
out_d3 <= #TCQ mask_data_rise1_r2;
out_d4 <= #TCQ mask_data_fall1_r2;
end
// 2 clk_mem delay required as per write cal
3'b100: begin
out_d1 <= #TCQ mask_data_fall1_r3;
out_d2 <= #TCQ mask_data_rise0_r2;
out_d3 <= #TCQ mask_data_fall0_r2;
out_d4 <= #TCQ mask_data_rise1_r2;
end
// DQS inverted during write leveling
// 2 clk_mem delay required as per write cal
3'b101: begin
out_d1 <= #TCQ mask_data_rise1_r3;
out_d2 <= #TCQ mask_data_fall1_r3;
out_d3 <= #TCQ mask_data_rise0_r2;
out_d4 <= #TCQ mask_data_fall0_r2;
end
// 3 clk_mem delay required as per write cal
3'b110: begin
out_d1 <= #TCQ mask_data_fall0_r3;
out_d2 <= #TCQ mask_data_rise1_r3;
out_d3 <= #TCQ mask_data_fall1_r3;
out_d4 <= #TCQ mask_data_rise0_r2;
end
// DQS inverted during write leveling
// 3 clk_mem delay required as per write cal
3'b111: begin
out_d1 <= #TCQ mask_data_rise0_r3;
out_d2 <= #TCQ mask_data_fall0_r3;
out_d3 <= #TCQ mask_data_rise1_r3;
out_d4 <= #TCQ mask_data_fall1_r3;
end
// defaults to 0 clk_mem delay
default: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
endcase
end
end
end
end else if (DRAM_TYPE == "DDR2") begin: gen_dm_lat_ddr2
if (nCWL == 2) begin: gen_ddr2_ncwl2
always @(mask_data_rise1_r1 or mask_data_fall1_r1 or
mask_data_rise0 or mask_data_fall0) begin
out_d1 = mask_data_rise1_r1;
out_d2 = mask_data_fall1_r1;
out_d3 = mask_data_rise0;
out_d4 = mask_data_fall0;
end
end else if (nCWL == 3) begin: gen_ddr2_ncwl3
always @(posedge clk) begin
out_d1 <= #TCQ mask_data_rise0;
out_d2 <= #TCQ mask_data_fall0;
out_d3 <= #TCQ mask_data_rise1;
out_d4 <= #TCQ mask_data_fall1;
end
end else if (nCWL == 4) begin: gen_ddr2_ncwl4
always @(posedge clk) begin
out_d1 = mask_data_rise1_r1;
out_d2 = mask_data_fall1_r1;
out_d3 = mask_data_rise0;
out_d4 = mask_data_fall0;
end
end else if (nCWL == 5) begin: gen_ddr2_ncwl5
always @(posedge clk) begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end
end else if (nCWL == 6) begin: gen_ddr2_ncwl6
always @(posedge clk) begin
out_d1 = mask_data_rise1_r2;
out_d2 = mask_data_fall1_r2;
out_d3 = mask_data_rise0_r1;
out_d4 = mask_data_fall0_r1;
end
end
end
endgenerate
//***************************************************************************
OSERDESE1 #
(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.DDR3_DATA (0),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"),
.ODELAY_USED (0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4)
)
u_oserdes_dm
(
.OCBEXTEND (),
.OFB (),
.OQ (dm_oq),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TQ (),
.CLK (clk_mem),
.CLKDIV (clk),
.CLKPERF (),
.CLKPERFDELAY (),
.D1 (out_d1),
.D2 (out_d2),
.D3 (out_d3),
.D4 (out_d4),
.D5 (),
.D6 (),
.OCE (1'b1),
.ODV (1'b0),
.SHIFTIN1 (),
.SHIFTIN2 (),
.RST (rst),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TFB (),
.TCE (1'b1),
.WC (1'b0)
);
// Output of OSERDES drives IODELAY (ODELAY)
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #
(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("O"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("VAR_LOADABLE"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (REFCLK_FREQ),
.SIGNAL_PATTERN ("DATA")
)
u_odelay_dm
(
.DATAOUT (dm_odelay),
.C (clk_rsync),
.CE (1'b0),
.DATAIN (),
.IDATAIN (),
.INC (1'b0),
.ODATAIN (dm_oq),
.RST (1'b1),
.T (),
.CNTVALUEIN (dlyval),
.CNTVALUEOUT (),
.CLKIN (),
.CINVCTRL (1'b0)
);
// Output of ODELAY drives OBUF
OBUF u_obuf_dm
(
.I (dm_odelay),
.O (ddr_dm)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module secret #(parameter GATED_CLK = 0)
(
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input s1up_in[2],
output logic s1up_out[2],
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
/*verilator lint_off LITENDIAN*/
input [0:15] s6x16up_in[0:1][2:0],
output logic [0:15] s6x16up_out[0:1][2:0],
/*verilator lint_on LITENDIAN*/
input [15:0] s8x16up_in[1:0][0:3],
output logic [15:0] s8x16up_out[1:0][0:3],
input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1],
input clk_en,
input clk /*verilator clocker*/);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");
logic the_clk;
generate
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
/* verilator lint_off LATCH */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on LATCH */
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign the_clk = clk;
end
endgenerate
always @(posedge the_clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s1up_out = s1up_in;
s2_out = s2_in;
s8_out = s8_in;
s64_out = s64_in;
s65_out = s65_in;
s129_out = s129_in;
s4x32_out = s4x32_in;
end
for (genvar i = 0; i < 3; ++i) begin
assign s6x16up_out[0][i] = s6x16up_in[0][i];
assign s6x16up_out[1][i] = s6x16up_in[1][i];
end
for (genvar i = 0; i < 4; ++i) begin
assign s8x16up_out[0][i] = s8x16up_in[0][i];
assign s8x16up_out[1][i] = s8x16up_in[1][i];
end
for (genvar i = 0; i < 8; ++i) begin
assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]];
end
sub sub (.sub_in(s33_in), .sub_out(s33_out));
// Test sequential path
assign accum_out = secret_accum_q;
// Test mixed combinatorial/sequential path
assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
final $display("destroying %m");
endmodule
module sub (
input [32:0] sub_in,
output [32:0] sub_out);
/*verilator no_inline_module*/
assign sub_out = sub_in;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
// This test demonstrates how not only parameters but the type of a parent
// interface could propagate down to child modules, changing their data type
// determinations. Note presently unsupported in all commercial simulators.
interface ifc;
parameter MODE = 0;
generate
// Note block must be named per SystemVerilog 2005
if (MODE==1) begin : g
integer value;
end
else if (MODE==2) begin : g
real value;
end
endgenerate
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itop1a();
ifc #(1) itop1b();
ifc #(2) itop2a();
ifc #(2) itop2b();
wrapper c1 (.isuba(itop1a),
.isubb(itop1b),
.i_valuea(14.1),
.i_valueb(15.2));
wrapper c2 (.isuba(itop2a),
.isubb(itop2b),
.i_valuea(24.3),
.i_valueb(25.4));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (itop1a.g.value != 14) $stop;
if (itop1b.g.value != 15) $stop;
if (itop2a.g.value != 24) $stop;
if (itop2b.g.value != 25) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module wrapper
(
ifc isuba,
ifc isubb,
input real i_valuea,
input real i_valueb
);
lower subsuba (.isub(isuba), .i_value(i_valuea));
lower subsubb (.isub(isubb), .i_value(i_valueb));
endmodule
module lower
(
ifc isub,
input real i_value
);
always @* begin
`error Commercial sims choke on cross ref here
isub.g.value = i_value;
end
endmodule
|
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Test:
tri t;
bufif1 (t, crc[1], cyc[1:0]==2'b00);
bufif1 (t, crc[2], cyc[1:0]==2'b10);
tri0 t0;
bufif1 (t0, crc[1], cyc[1:0]==2'b00);
bufif1 (t0, crc[2], cyc[1:0]==2'b10);
tri1 t1;
bufif1 (t1, crc[1], cyc[1:0]==2'b00);
bufif1 (t1, crc[2], cyc[1:0]==2'b10);
tri t2;
t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t2, crc[2], cyc[1:0]==2'b10);
tri t3;
t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t3, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h04f91df71371e950
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_tri2 (/*AUTOARG*/
// Outputs
t2,
// Inputs
d, oe
);
output t2;
input d;
input oe;
tri1 t2;
bufif1 (t2, d, oe);
endmodule
module t_tri3 (/*AUTOARG*/
// Outputs
t3,
// Inputs
d, oe
);
output tri1 t3;
input d;
input oe;
bufif1 (t3, d, oe);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Top level multiplier and MAC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Multiplier is 32x32 however multiply instructions only ////
//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
//// ////
//// To Do: ////
//// - make signed division better, w/o negating the operands ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.2 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:38 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
reg div_free;
`ifdef OR1200_IMPL_DIV
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`endif
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
`ifdef OR1200_MULT_IMPLEMENTED
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
casex(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV:
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL: begin
result = mul_prod_r[31:0];
end
default:
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
`endif
endcase
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
if (rst) begin
mul_prod_r <= #1 64'h0000_0000_0000_0000;
div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
div_cntr <= #1 6'b00_0000;
`endif
end
`ifdef OR1200_IMPL_DIV
else if (|div_cntr) begin
if (div_tmp[31])
mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= #1 div_cntr - 1'b1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
div_cntr <= #1 6'b10_0000;
div_free <= #1 1'b0;
end
`endif // OR1200_IMPL_DIV
else if (div_free | !ex_freeze) begin
mul_prod_r <= #1 mul_prod[63:0];
div_free <= #1 1'b1;
end
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= #1 mac_op;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= #1 mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= #1 mac_op_r2;
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
if (rst)
mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= #1 spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= #1 spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= #1 mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= #1 mac_r - mul_prod_r;
else if (macrc_op & !ex_freeze)
mac_r <= #1 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
if (rst)
mac_stall_r <= #1 1'b0;
else
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
| (|div_cntr)
`endif
;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipcpu.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//{{{
// Purpose: This is the top level module holding the core of the Zip CPU
// together. The Zip CPU is designed to be as simple as possible.
// (actual implementation aside ...) The instruction set is about as
// RISC as you can get, with only 26 instruction types currently supported.
// (There are still 8-instruction Op-Codes reserved for floating point,
// and 5 which can be used for transactions not requiring registers.)
// Please see the accompanying spec.pdf file for a description of these
// instructions.
//
// All instructions are 32-bits wide. All bus accesses, both address and
// data, are 32-bits over a wishbone bus.
//
// The Zip CPU is fully pipelined with the following pipeline stages:
//
// 1. Prefetch, returns the instruction from memory.
//
// 2. Instruction Decode
//
// 3. Read Operands
//
// 4. Apply Instruction
//
// 4. Write-back Results
//
// Further information about the inner workings of this CPU, such as
// what causes pipeline stalls, may be found in the spec.pdf file. (The
// documentation within this file had become out of date and out of sync
// with the spec.pdf, so look to the spec.pdf for accurate and up to date
// information.)
//
//
// In general, the pipelining is controlled by three pieces of logic
// per stage: _ce, _stall, and _valid. _valid means that the stage
// holds a valid instruction. _ce means that the instruction from the
// previous stage is to move into this one, and _stall means that the
// instruction from the previous stage may not move into this one.
// The difference between these control signals allows individual stages
// to propagate instructions independently. In general, the logic works
// as:
//
//
// assign (n)_ce = (n-1)_valid && (!(n)_stall)
//
//
// always @(posedge i_clk)
// if ((i_rst)||(clear_pipeline))
// (n)_valid = 0
// else if (n)_ce
// (n)_valid = 1
// else if (n+1)_ce
// (n)_valid = 0
//
// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
// || ( (n)_valid && (n+1)_stall );
//
// and ...
//
// always @(posedge i_clk)
// if (n)_ce
// (n)_variable = ... whatever logic for this stage
//
// Note that a stage can stall even if no instruction is loaded into
// it.
//
//}}}
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//{{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//}}}
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
`define CPU_TRAP_BIT 9 // User TRAP has taken place
`define CPU_ILL_BIT 8 // Illegal instruction
`define CPU_BREAK_BIT 7
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions
`define CPU_GIE_BIT 5
`define CPU_SLEEP_BIT 4
// Compile time defines
//
`include "cpudefs.v"
//
//
module zipcpu(i_clk, i_rst, i_interrupt,
// Debug interface
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
o_dbg_stall, o_dbg_reg, o_dbg_cc,
o_break,
// CPU interface to the wishbone bus
o_wb_gbl_cyc, o_wb_gbl_stb,
o_wb_lcl_cyc, o_wb_lcl_stb,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data,
i_wb_err,
// Accounting/CPU usage interface
o_op_stall, o_pf_stall, o_i_count
`ifdef DEBUG_SCOPE
, o_debug
`endif
);
// Parameters
//{{{
parameter [31:0] RESET_ADDRESS=32'h0100000;
parameter ADDRESS_WIDTH=30,
LGICACHE=8;
`ifdef OPT_MULTIPLY
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
`else
parameter IMPLEMENT_MPY = 0;
`endif
`ifdef OPT_DIVIDE
parameter IMPLEMENT_DIVIDE = 1;
`else
parameter IMPLEMENT_DIVIDE = 0;
`endif
`ifdef OPT_IMPLEMENT_FPU
parameter IMPLEMENT_FPU = 1,
`else
parameter IMPLEMENT_FPU = 0,
`endif
IMPLEMENT_LOCK=1;
`ifdef OPT_EARLY_BRANCHING
parameter EARLY_BRANCHING = 1;
`else
parameter EARLY_BRANCHING = 0;
`endif
parameter WITH_LOCAL_BUS = 1;
localparam AW=ADDRESS_WIDTH;
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2];
//}}}
// I/O declarations
//{{{
input wire i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
input wire i_halt, i_clear_pf_cache;
input wire [4:0] i_dbg_reg;
input wire i_dbg_we;
input wire [31:0] i_dbg_data;
// Debug interface -- outputs
output wire o_dbg_stall;
output reg [31:0] o_dbg_reg;
output reg [3:0] o_dbg_cc;
output wire o_break;
// Wishbone interface -- outputs
output wire o_wb_gbl_cyc, o_wb_gbl_stb;
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
output wire [(AW-1):0] o_wb_addr;
output wire [31:0] o_wb_data;
output wire [3:0] o_wb_sel;
// Wishbone interface -- inputs
input wire i_wb_ack, i_wb_stall;
input wire [31:0] i_wb_data;
input wire i_wb_err;
// Accounting outputs ... to help us count stalls and usage
output wire o_op_stall;
output wire o_pf_stall;
output wire o_i_count;
//
`ifdef DEBUG_SCOPE
output reg [31:0] o_debug;
`endif
//}}}
// Registers
//
// The distributed RAM style comment is necessary on the
// SPARTAN6 with XST to prevent XST from oversimplifying the register
// set and in the process ruining everything else. It basically
// optimizes logic away, to where it no longer works. The logic
// as described herein will work, this just makes sure XST implements
// that logic.
//
(* ram_style = "distributed" *)
`ifdef OPT_NO_USERMODE
reg [31:0] regset [0:15];
`else
reg [31:0] regset [0:31];
`endif
// Condition codes
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
reg [3:0] flags, iflags;
wire [14:0] w_uflags, w_iflags;
reg break_en, step, sleep, r_halted;
wire break_pending, trap, gie, ubreak;
wire w_clear_icache, ill_err_u;
reg ill_err_i;
reg ibus_err_flag;
wire ubus_err_flag;
wire idiv_err_flag, udiv_err_flag;
wire ifpu_err_flag, ufpu_err_flag;
wire ihalt_phase, uhalt_phase;
// The master chip enable
wire master_ce;
//
//
// PIPELINE STAGE #1 :: Prefetch
// Variable declarations
//
//{{{
reg [(AW+1):0] pf_pc;
reg new_pc;
wire clear_pipeline;
assign clear_pipeline = new_pc;
wire dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err;
wire [(AW-1):0] pf_addr;
wire [31:0] pf_data;
wire [31:0] pf_instruction;
wire [(AW-1):0] pf_instruction_pc;
wire pf_valid, pf_gie, pf_illegal;
//}}}
//
//
// PIPELINE STAGE #2 :: Instruction Decode
// Variable declarations
//
//
//{{{
reg op_valid /* verilator public_flat */,
op_valid_mem, op_valid_alu;
reg op_valid_div, op_valid_fpu;
wire op_stall, dcd_ce, dcd_phase;
wire [3:0] dcd_opn;
wire [4:0] dcd_A, dcd_B, dcd_R;
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc;
wire [3:0] dcd_F;
wire dcd_wR, dcd_rA, dcd_rB,
dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
dcd_wF, dcd_gie, dcd_break, dcd_lock,
dcd_pipe, dcd_ljmp;
wire dcd_valid;
wire [AW:0] dcd_pc /* verilator public_flat */;
wire [31:0] dcd_I;
wire dcd_zI; // true if dcd_I == 0
wire dcd_A_stall, dcd_B_stall, dcd_F_stall;
wire dcd_illegal;
wire dcd_early_branch, dcd_early_branch_stb;
wire [(AW-1):0] dcd_branch_pc;
wire dcd_sim;
wire [22:0] dcd_sim_immv;
//}}}
//
//
// PIPELINE STAGE #3 :: Read Operands
// Variable declarations
//
//
//
//{{{
// Now, let's read our operands
reg [4:0] alu_reg;
wire [3:0] op_opn;
wire [4:0] op_R;
reg [31:0] r_op_Av, r_op_Bv;
reg [(AW-1):0] op_pc;
wire [31:0] w_op_Av, w_op_Bv;
wire [31:0] op_Av, op_Bv;
reg op_wR, op_wF;
wire op_gie, op_Rcc;
wire [3:0] op_Fl;
reg [6:0] r_op_F;
wire [7:0] op_F;
wire op_ce, op_phase, op_pipe, op_change_data_ce;
// Some pipeline control wires
reg op_illegal;
wire op_break;
wire op_lock;
`ifdef VERILATOR
reg op_sim /* verilator public_flat */;
reg [22:0] op_sim_immv /* verilator public_flat */;
`endif
//}}}
//
//
// PIPELINE STAGE #4 :: ALU / Memory
// Variable declarations
//
//
//{{{
wire [(AW-1):0] alu_pc;
reg r_alu_pc_valid, mem_pc_valid;
wire alu_pc_valid;
wire alu_phase;
wire alu_ce /* verilator public_flat */, alu_stall;
wire [31:0] alu_result;
wire [3:0] alu_flags;
wire alu_valid, alu_busy;
wire set_cond;
reg alu_wR, alu_wF;
wire alu_gie, alu_illegal;
wire mem_ce, mem_stalled;
wire mem_pipe_stalled;
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
wire [4:0] mem_wreg;
wire mem_busy, mem_rdbusy;
wire [(AW-1):0] mem_addr;
wire [31:0] mem_data, mem_result;
wire [3:0] mem_sel;
wire div_ce, div_error, div_busy, div_valid;
wire [31:0] div_result;
wire [3:0] div_flags;
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
wire [31:0] fpu_result;
wire [3:0] fpu_flags;
assign div_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_div)
&&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
&&(set_cond);
assign fpu_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_fpu)
&&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
&&(set_cond);
wire adf_ce_unconditional;
//}}}
//
//
// PIPELINE STAGE #5 :: Write-back
// Variable declarations
//
//{{{
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
wr_write_scc, wr_write_ucc;
wire [4:0] wr_reg_id;
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
wire w_switch_to_interrupt, w_release_from_interrupt;
reg [(AW+1):0] ipc;
wire [(AW+1):0] upc;
//}}}
//
// MASTER: clock enable.
//
assign master_ce = ((!i_halt)||(alu_phase))&&(!o_break)&&(!sleep);
//
// PIPELINE STAGE #1 :: Prefetch
// Calculate stall conditions
//
// These are calculated externally, within the prefetch module.
//
//
// PIPELINE STAGE #2 :: Instruction Decode
// Calculate stall conditions
assign dcd_stalled = (dcd_valid)&&(op_stall);
//
// PIPELINE STAGE #3 :: Read Operands
// Calculate stall conditions
//{{{
wire prelock_stall;
`ifdef OPT_PIPELINED
reg cc_invalid_for_dcd;
always @(posedge i_clk)
cc_invalid_for_dcd <= (wr_flags_ce)
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG)))
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG)))
||(mem_busy)||(div_busy)||(fpu_busy);
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
//{{{
// Stall if we're stopped, and not allowed to execute
// an instruction
// (!master_ce) // Already captured in alu_stall
//
// Stall if going into the ALU and the ALU is stalled
// i.e. if the memory is busy, or we are single
// stepping. This also includes our stalls for
// op_break and op_lock, so we don't need to
// include those as well here.
// This also includes whether or not the divide or
// floating point units are busy.
(alu_stall)
||(((op_valid_div)||(op_valid_fpu))
&&(!adf_ce_unconditional))
//
// Stall if we are going into memory with an operation
// that cannot be pipelined, and the memory is
// already busy
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled
||(op_Rcc)
)
||(dcd_valid)&&(
// Stall if we need to wait for an operand A
// to be ready to read
(dcd_A_stall)
// Likewise for B, also includes logic
// regarding immediate offset (register must
// be in register file if we need to add to
// an immediate)
||(dcd_B_stall)
// Or if we need to wait on flags to work on the
// CC register
||(dcd_F_stall)
);
//}}}
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
`else
assign op_stall = (alu_busy)||(div_busy)||(fpu_busy)||(wr_reg_ce)
||(mem_busy)||(op_valid)||(wr_flags_ce);
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
`endif
// BUT ... op_ce is too complex for many of the data operations. So
// let's make their circuit enable code simpler. In particular, if
// op_ doesn't need to be preserved, we can change it all we want
// ... right? The clear_pipeline code, for example, really only needs
// to determine whether op_valid is true.
assign op_change_data_ce = (!op_stall);
//}}}
//
// PIPELINE STAGE #4 :: ALU / Memory
// Calculate stall conditions
//
//{{{
// 1. Basic stall is if the previous stage is valid and the next is
// busy.
// 2. Also stall if the prior stage is valid and the master clock enable
// is de-selected
// 3. Stall if someone on the other end is writing the CC register,
// since we don't know if it'll put us to sleep or not.
// 4. Last case: Stall if we would otherwise move a break instruction
// through the ALU. Break instructions are not allowed through
// the ALU.
`ifdef OPT_PIPELINED
assign alu_stall = (((!master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
||(prelock_stall)
||((op_valid)&&(op_break))
||(wr_reg_ce)&&(wr_write_cc)
||(div_busy)||(fpu_busy);
assign alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)
&&(!clear_pipeline);
`else
assign alu_stall = (op_valid_alu)&&((!master_ce)||(op_break));
assign alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)&&(!clear_pipeline);
`endif
//
//
// Note: if you change the conditions for mem_ce, you must also change
// alu_pc_valid.
//
assign mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled)
&&(!clear_pipeline);
`ifdef OPT_PIPELINED_BUS_ACCESS
assign mem_stalled = (!master_ce)||(alu_busy)||((op_valid_mem)&&(
(mem_pipe_stalled)
||(prelock_stall)
||((!op_pipe)&&(mem_busy))
||(div_busy)
||(fpu_busy)
// Stall waiting for flags to be valid
// Or waiting for a write to the PC register
// Or CC register, since that can change the
// PC as well
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&((wr_write_pc)||(wr_write_cc)))));
`else
`ifdef OPT_PIPELINED
assign mem_stalled = (mem_busy)||((op_valid_mem)&&(
(!master_ce)
// Stall waiting for flags to be valid
// Or waiting for a write to the PC register
// Or CC register, since that can change the
// PC as well
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
`else
assign mem_stalled = (op_valid_mem)&&(!master_ce);
`endif
`endif
//}}}
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
assign adf_ce_unconditional = (master_ce)&&(!clear_pipeline)&&(op_valid)
&&(!op_valid_mem)&&(!mem_rdbusy)
&&((!op_valid_alu)||(!alu_stall))&&(!op_break)
&&(!div_busy)&&(!fpu_busy)&&(!clear_pipeline);
//
//
// PIPELINE STAGE #1 :: Prefetch
//
//
//{{{
wire pf_stalled;
assign pf_stalled = (dcd_stalled)||(dcd_phase);
wire pf_new_pc;
assign pf_new_pc = (new_pc)||((dcd_early_branch_stb)&&(!clear_pipeline));
wire [(AW-1):0] pf_request_address;
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
? dcd_branch_pc:pf_pc[(AW+1):2];
assign pf_gie = gie;
`ifdef OPT_SINGLE_FETCH
prefetch #(ADDRESS_WIDTH)
//{{{
pf(i_clk, (i_rst), pf_new_pc, w_clear_icache,
(!pf_stalled),
pf_request_address,
pf_instruction, pf_instruction_pc,
pf_valid, pf_illegal,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data);
//}}}
`else
`ifdef OPT_DOUBLE_FETCH
dblfetch #(ADDRESS_WIDTH)
//{{{
pf(i_clk, i_rst, pf_new_pc, w_clear_icache,
(!pf_stalled),
pf_request_address,
pf_instruction, pf_instruction_pc,
pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
pf_illegal);
//}}}
`else // Not single fetch and not double fetch
`ifdef OPT_TRADITIONAL_PFCACHE
pfcache #(LGICACHE, ADDRESS_WIDTH)
//{{{
pf(i_clk, i_rst, pf_new_pc, w_clear_icache,
// dcd_pc,
(!pf_stalled),
pf_request_address,
pf_instruction, pf_instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
pf_illegal);
//}}}
`else
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
//{{{
pf(i_clk, i_rst, pf_new_pc,
w_clear_icache, (!pf_stalled),
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
pf_instruction, pf_instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
(mem_cyc_lcl)||(mem_cyc_gbl),
pf_illegal);
//}}}
`endif // OPT_TRADITIONAL_CACHE
`endif // OPT_DOUBLE_FETCH
`endif // OPT_SINGLE_FETCH
//}}}
//
//
// PIPELINE STAGE #2 :: Instruction Decode
//
//
//{{{
assign dcd_ce = (!dcd_valid)||(!dcd_stalled);
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk,
(clear_pipeline)||(w_clear_icache),
dcd_ce,
dcd_stalled, pf_instruction, pf_gie,
pf_instruction_pc, pf_valid, pf_illegal,
dcd_valid, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcd_Rcc, dcd_Rpc, dcd_R },
{ dcd_Acc, dcd_Apc, dcd_A },
{ dcd_Bcc, dcd_Bpc, dcd_B },
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock,
dcd_wR,dcd_rA, dcd_rB,
dcd_early_branch, dcd_early_branch_stb,
dcd_branch_pc, dcd_ljmp,
dcd_pipe,
dcd_sim, dcd_sim_immv);
//}}}
//
//
// PIPELINE STAGE #3 :: Read Operands (Registers)
//
//
//{{{
`ifdef OPT_PIPELINED_BUS_ACCESS
reg r_op_pipe;
initial r_op_pipe = 1'b0;
// To be a pipeable operation, there must be
// two valid adjacent instructions
// Both must be memory instructions
// Both must be writes, or both must be reads
// Both operations must be to the same identical address,
// or at least a single (one) increment above that address
//
// However ... we need to know this before this clock, hence this is
// calculated in the instruction decoder.
always @(posedge i_clk)
if (clear_pipeline)
r_op_pipe <= 1'b0;
else if (op_ce)
r_op_pipe <= dcd_pipe;
else if (mem_ce) // Clear us any time an op_ is clocked in
r_op_pipe <= 1'b0;
assign op_pipe = r_op_pipe;
`else
assign op_pipe = 1'b0;
`endif
`ifdef OPT_NO_USERMODE
assign w_op_Av = regset[dcd_A[3:0]];
assign w_op_Bv = regset[dcd_B[3:0]];
`else
assign w_op_Av = regset[dcd_A];
assign w_op_Bv = regset[dcd_B];
`endif
wire [8:0] w_cpu_info;
assign w_cpu_info = {
//{{{
1'b1,
(IMPLEMENT_MPY >0)? 1'b1:1'b0,
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0,
(IMPLEMENT_FPU >0)? 1'b1:1'b0,
`ifdef OPT_PIPELINED
1'b1,
`else
1'b0,
`endif
`ifdef OPT_TRADITIONAL_CACHE
1'b1,
`else
1'b0,
`endif
`ifdef OPT_EARLY_BRANCHING
1'b1,
`else
1'b0,
`endif
`ifdef OPT_PIPELINED_BUS_ACCESS
1'b1,
`else
1'b0,
`endif
`ifdef OPT_CIS
1'b1
`else
1'b0
`endif
};
//}}}
wire [31:0] w_pcA_v;
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie)
? { dcd_pc[AW:1], 2'b00 }
: { upc[(AW+1):2], uhalt_phase, 1'b0 } };
generate
if (AW < 30)
assign w_pcA_v[31:(AW+2)] = 0;
endgenerate
`ifdef OPT_PIPELINED
reg [4:0] op_Aid, op_Bid;
reg op_rA, op_rB;
always @(posedge i_clk)
if (op_ce)
begin
op_Aid <= dcd_A;
op_Bid <= dcd_B;
op_rA <= dcd_rA;
op_rB <= dcd_rB;
end
`endif
always @(posedge i_clk)
if (op_ce)
begin
`ifdef OPT_PIPELINED
if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
r_op_Av <= wr_gpreg_vl;
else
`endif
if (dcd_Apc)
r_op_Av <= w_pcA_v;
else if (dcd_Acc)
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
else
r_op_Av <= w_op_Av;
`ifdef OPT_PIPELINED
end else
begin
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
r_op_Av <= wr_gpreg_vl;
`endif
end
wire [31:0] w_op_BnI, w_pcB_v;
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie)
? { dcd_pc[AW:1], 2'b00 }
: { upc[(AW+1):2], uhalt_phase, 1'b0 } };
generate
if (AW < 30)
assign w_pcB_v[31:(AW+2)] = 0;
endgenerate
assign w_op_BnI = (!dcd_rB) ? 32'h00
`ifdef OPT_PIPELINED
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl
`endif
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14],
1'b0, (dcd_B[4])?w_uflags:w_iflags}
: w_op_Bv);
always @(posedge i_clk)
`ifdef OPT_PIPELINED
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB))
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
else if (op_ce)
r_op_Bv <= w_op_BnI + dcd_I;
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB))
r_op_Bv <= wr_gpreg_vl;
`else
if(op_ce)
begin
if ((dcd_Bpc)&&(dcd_rB))
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
else
r_op_Bv <= w_op_BnI + dcd_I;
end
`endif
// The logic here has become more complex than it should be, no thanks
// to Xilinx's Vivado trying to help. The conditions are supposed to
// be two sets of four bits: the top bits specify what bits matter, the
// bottom specify what those top bits must equal. However, two of
// conditions check whether bits are on, and those are the only two
// conditions checking those bits. Therefore, Vivado complains that
// these two bits are redundant. Hence the convoluted expression
// below, arriving at what we finally want in the (now wire net)
// op_F.
always @(posedge i_clk)
if (op_ce) // Cannot do op_change_data_ce here since op_F depends
// upon being either correct for a valid op, or correct
// for the last valid op
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
case(dcd_F[2:0])
3'h0: r_op_F <= 7'h00; // Always
3'h1: r_op_F <= 7'h11; // Z
3'h2: r_op_F <= 7'h44; // LT
3'h3: r_op_F <= 7'h22; // C
3'h4: r_op_F <= 7'h08; // V
3'h5: r_op_F <= 7'h10; // NE
3'h6: r_op_F <= 7'h40; // GE (!N)
3'h7: r_op_F <= 7'h20; // NC
endcase
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
assign op_F = { r_op_F[3], r_op_F[6:0] };
wire w_op_valid;
assign w_op_valid = (!clear_pipeline)&&(dcd_valid)&&(!dcd_ljmp)&&(!dcd_early_branch);
initial op_valid = 1'b0;
initial op_valid_alu = 1'b0;
initial op_valid_mem = 1'b0;
initial op_valid_div = 1'b0;
initial op_valid_fpu = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
begin
op_valid <= 1'b0;
op_valid_alu <= 1'b0;
op_valid_mem <= 1'b0;
op_valid_div <= 1'b0;
op_valid_fpu <= 1'b0;
end else if (op_ce)
begin
// Do we have a valid instruction?
// The decoder may vote to stall one of its
// instructions based upon something we currently
// have in our queue. This instruction must then
// move forward, and get a stall cycle inserted.
// Hence, the test on dcd_stalled here. If we must
// wait until our operands are valid, then we aren't
// valid yet until then.
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
||(dcd_early_branch));
op_valid_mem <= (dcd_M)&&(!dcd_illegal)&&(w_op_valid);
op_valid_div <= (dcd_DIV)&&(!dcd_illegal)&&(w_op_valid);
op_valid_fpu <= (dcd_FP)&&(!dcd_illegal)&&(w_op_valid);
end else if ((adf_ce_unconditional)||(mem_ce))
begin
op_valid <= 1'b0;
op_valid_alu <= 1'b0;
op_valid_mem <= 1'b0;
op_valid_div <= 1'b0;
op_valid_fpu <= 1'b0;
end
// Here's part of our debug interface. When we recognize a break
// instruction, we set the op_break flag. That'll prevent this
// instruction from entering the ALU, and cause an interrupt before
// this instruction. Thus, returning to this code will cause the
// break to repeat and continue upon return. To get out of this
// condition, replace the break instruction with what it is supposed
// to be, step through it, and then replace it back. In this fashion,
// a debugger can step through code.
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
reg r_op_break;
initial r_op_break = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0;
else if (op_ce)
r_op_break <= (dcd_break);
else if (!op_valid)
r_op_break <= 1'b0;
assign op_break = r_op_break;
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_op_lock;
initial r_op_lock = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
r_op_lock <= 1'b0;
else if (op_ce)
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(!clear_pipeline);
assign op_lock = r_op_lock;
end else begin
assign op_lock = 1'b0;
end endgenerate
`else
assign op_lock = 1'b0;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
initial op_illegal = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
op_illegal <= 1'b0;
else if(op_ce)
`ifdef OPT_PIPELINED
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
`else
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock));
`endif
else if(alu_ce)
op_illegal <= 1'b0;
`endif
always @(posedge i_clk)
if (op_ce)
begin
op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
&&(!dcd_early_branch)&&(!dcd_illegal);
op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal);
end
`ifdef VERILATOR
`ifdef SINGLE_FETCH
always @(*)
begin
op_sim = dcd_sim;
op_sim_immv = dcd_sim_immv;
end
`else
always @(posedge i_clk)
if (op_change_data_ce)
begin
op_sim <= dcd_sim;
op_sim_immv <= dcd_sim_immv;
end
`endif
`endif
reg [3:0] r_op_opn;
reg [4:0] r_op_R;
reg r_op_Rcc;
reg r_op_gie;
initial r_op_gie = 1'b0;
always @(posedge i_clk)
if (op_change_data_ce)
begin
// Which ALU operation? Early branches are
// unimplemented moves
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn;
// opM <= dcd_M; // Is this a memory operation?
// What register will these results be written into?
r_op_R <= dcd_R;
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
// User level (1), vs supervisor (0)/interrupts disabled
r_op_gie <= dcd_gie;
//
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
end
assign op_opn = r_op_opn;
assign op_R = r_op_R;
assign op_gie = r_op_gie;
assign op_Rcc = r_op_Rcc;
assign op_Fl = (op_gie)?(w_uflags[3:0]):(w_iflags[3:0]);
`ifdef OPT_CIS
reg r_op_phase;
initial r_op_phase = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
r_op_phase <= 1'b0;
else if (op_change_data_ce)
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc));
assign op_phase = r_op_phase;
`else
assign op_phase = 1'b0;
`endif
// This is tricky. First, the PC and Flags registers aren't kept in
// register set but in special registers of their own. So step one
// is to select the right register. Step to is to replace that
// register with the results of an ALU or memory operation, if such
// results are now available. Otherwise, we'd need to insert a wait
// state of some type.
//
// The alternative approach would be to define some sort of
// op_stall wire, which would stall any upstream stage.
// We'll create a flag here to start our coordination. Once we
// define this flag to something other than just plain zero, then
// the stalls will already be in place.
`ifdef OPT_PIPELINED
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA))
? wr_gpreg_vl : r_op_Av;
`else
assign op_Av = r_op_Av;
`endif
`ifdef OPT_PIPELINED
// Stall if we have decoded an instruction that will read register A
// AND ... something that may write a register is running
// AND (series of conditions here ...)
// The operation might set flags, and we wish to read the
// CC register
// OR ... (No other conditions)
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere
&&((op_valid)||(mem_rdbusy)
||(div_busy)||(fpu_busy))
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc))
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd));
`else
// There are no pipeline hazards, if we aren't pipelined
assign dcd_A_stall = 1'b0;
`endif
`ifdef OPT_PIPELINED
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB))
? wr_gpreg_vl: r_op_Bv;
`else
assign op_Bv = r_op_Bv;
`endif
`ifdef OPT_PIPELINED
// Stall if we have decoded an instruction that will read register B
// AND ... something that may write a (unknown) register is running
// AND (series of conditions here ...)
// The operation might set flags, and we wish to read the
// CC register
// OR the operation might set register B, and we still need
// a clock to add the offset to it
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere
//{{{
// If the op stage isn't valid, yet something
// is running, then it must have been valid.
// We'll use the last values from that stage
// (op_wR, op_wF, op_R) in our logic below.
&&((op_valid)||(mem_rdbusy)
||(div_busy)||(fpu_busy)||(alu_busy))
&&(
// Okay, what happens if the result register
// from instruction 1 becomes the input for
// instruction two, *and* there's an immediate
// offset in instruction two? In that case, we
// need an extra clock between the two
// instructions to calculate the base plus
// offset.
//
// What if instruction 1 (or before) is in a
// memory pipeline? We may no longer know what
// the register was! We will then need to
// blindly wait. We'll temper this only waiting
// if we're not piping this new instruction.
// If we were piping, the pipe logic in the
// decode circuit has told us that the hazard
// is clear, so we're okay then.
//
((!dcd_zI)&&(
((op_R == dcd_B)&&(op_wR))
||((mem_rdbusy)&&(!dcd_pipe))
))
// Stall following any instruction that will
// set the flags, if we're going to need the
// flags (CC) register for op_B.
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
// Stall on any ongoing memory operation that
// will write to op_B -- captured above
// ||((mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI))
)
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
//}}}
assign dcd_F_stall = ((!dcd_F[3])
//{{{
||((dcd_rA)&&(dcd_Acc))
||((dcd_rB)&&(dcd_Bcc)))
&&(op_valid)&&(op_Rcc);
// &&(dcd_valid) is checked for elsewhere
//}}}
`else
// No stalls without pipelining, 'cause how can you have a pipeline
// hazard without the pipeline?
assign dcd_B_stall = 1'b0;
assign dcd_F_stall = 1'b0;
`endif
//}}}
//
//
// PIPELINE STAGE #4 :: Apply Instruction
//
//
// ALU
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline),
//{{{
alu_ce, op_opn, op_Av, op_Bv,
alu_result, alu_flags, alu_valid, alu_busy);
//}}}
// Divide
//{{{
generate
if (IMPLEMENT_DIVIDE != 0)
begin
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0],
op_Av, op_Bv, div_busy, div_valid, div_error, div_result,
div_flags);
end else begin
assign div_error = 1'b0; // Can't be high unless div_valid
assign div_busy = 1'b0;
assign div_valid = 1'b0;
assign div_result= 32'h00;
assign div_flags = 4'h0;
end endgenerate
//}}}
// (Non-existent) FPU
//{{{
generate
if (IMPLEMENT_FPU != 0)
begin
//
// sfpu thefpu(i_clk, i_rst, fpu_ce,
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result,
// fpu_flags);
//
assign fpu_error = 1'b0; // Must only be true if fpu_valid
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end else begin
assign fpu_error = 1'b0;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end endgenerate
//}}}
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]);
initial alu_wF = 1'b0;
initial alu_wR = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
alu_wR <= 1'b0;
alu_wF <= 1'b0;
end else if (alu_ce)
begin
// alu_reg <= op_R;
alu_wR <= (op_wR)&&(set_cond);
alu_wF <= (op_wF)&&(set_cond);
end else if (!alu_busy) begin
// These are strobe signals, so clear them if not
// set for any particular clock
alu_wR <= (i_halt)&&(i_dbg_we);
alu_wF <= 1'b0;
end
`ifdef OPT_CIS
reg r_alu_phase;
initial r_alu_phase = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_alu_phase <= 1'b0;
else if ((adf_ce_unconditional)||(mem_ce))
r_alu_phase <= op_phase;
assign alu_phase = r_alu_phase;
`else
assign alu_phase = 1'b0;
`endif
`ifdef OPT_PIPELINED
always @(posedge i_clk)
if (adf_ce_unconditional)
alu_reg <= op_R;
else if ((i_halt)&&(i_dbg_we))
alu_reg <= i_dbg_reg;
`else
always @(posedge i_clk)
if ((i_halt)&&(i_dbg_we))
alu_reg <= i_dbg_reg;
else
alu_reg <= op_R;
`endif
//
// DEBUG Register write access starts here
//
//{{{
reg dbgv;
initial dbgv = 1'b0;
always @(posedge i_clk)
dbgv <= (!i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
reg [31:0] dbg_val;
always @(posedge i_clk)
dbg_val <= i_dbg_data;
`ifdef OPT_NO_USERMODE
assign alu_gie = 1'b0;
`else
`ifdef OPT_PIPELINED
reg r_alu_gie;
always @(posedge i_clk)
if ((adf_ce_unconditional)||(mem_ce))
r_alu_gie <= op_gie;
assign alu_gie = r_alu_gie;
`else
assign alu_gie = op_gie;
`endif
`endif
//}}}
`ifdef OPT_PIPELINED
reg [(AW-1):0] r_alu_pc;
always @(posedge i_clk)
if ((adf_ce_unconditional)
||((master_ce)&&(op_valid_mem)&&(!clear_pipeline)
&&(!mem_stalled)))
r_alu_pc <= op_pc;
assign alu_pc = r_alu_pc;
`else
assign alu_pc = op_pc;
`endif
reg r_alu_illegal;
initial r_alu_illegal = 0;
always @(posedge i_clk)
if (clear_pipeline)
r_alu_illegal <= 1'b0;
else if (alu_ce)
r_alu_illegal <= op_illegal;
else
r_alu_illegal <= 1'b0;
assign alu_illegal = (r_alu_illegal);
initial r_alu_pc_valid = 1'b0;
initial mem_pc_valid = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
r_alu_pc_valid <= 1'b0;
else if ((adf_ce_unconditional)&&(!op_phase))
r_alu_pc_valid <= 1'b1;
else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline))
r_alu_pc_valid <= 1'b0;
assign alu_pc_valid = (r_alu_pc_valid)&&((!alu_busy)&&(!div_busy)&&(!fpu_busy));
always @(posedge i_clk)
if (i_rst)
mem_pc_valid <= 1'b0;
else
mem_pc_valid <= (mem_ce);
// Bus lock logic
//{{{
wire bus_lock;
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_prelock_stall;
initial r_prelock_stall = 1'b0;
always @(posedge i_clk)
if (clear_pipeline)
r_prelock_stall <= 1'b0;
else if ((op_valid)&&(op_lock)&&(op_ce))
r_prelock_stall <= 1'b1;
else if ((op_valid)&&(dcd_valid)&&(pf_valid))
r_prelock_stall <= 1'b0;
assign prelock_stall = r_prelock_stall;
reg r_prelock_primed;
always @(posedge i_clk)
if (clear_pipeline)
r_prelock_primed <= 1'b0;
else if (r_prelock_stall)
r_prelock_primed <= 1'b1;
else if ((adf_ce_unconditional)||(mem_ce))
r_prelock_primed <= 1'b0;
reg [1:0] r_bus_lock;
initial r_bus_lock = 2'b00;
always @(posedge i_clk)
if (clear_pipeline)
r_bus_lock <= 2'b00;
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce)))
begin
if (r_prelock_primed)
r_bus_lock <= 2'b10;
else if (r_bus_lock != 2'h0)
r_bus_lock <= r_bus_lock + 2'b11;
end
assign bus_lock = |r_bus_lock;
end else begin
assign prelock_stall = 1'b0;
assign bus_lock = 1'b0;
end endgenerate
`else
assign prelock_stall = 1'b0;
assign bus_lock = 1'b0;
`endif
//}}}
// Memory interface
//{{{
`ifdef OPT_PIPELINED_BUS_ACCESS
pipemem #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,
///{{{
(mem_ce)&&(set_cond), bus_lock,
(op_opn[2:0]), op_Bv, op_Av, op_R,
mem_busy, mem_pipe_stalled,
mem_valid, bus_err, mem_wreg, mem_result,
mem_cyc_gbl, mem_cyc_lcl,
mem_stb_gbl, mem_stb_lcl,
mem_we, mem_addr, mem_data, mem_sel,
mem_ack, mem_stall, mem_err, i_wb_data);
//}}}
`else // PIPELINED_BUS_ACCESS
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,
//{{{
(mem_ce)&&(set_cond), bus_lock,
(op_opn[2:0]), op_Bv, op_Av, op_R,
mem_busy,
mem_valid, bus_err, mem_wreg, mem_result,
mem_cyc_gbl, mem_cyc_lcl,
mem_stb_gbl, mem_stb_lcl,
mem_we, mem_addr, mem_data, mem_sel,
mem_ack, mem_stall, mem_err, i_wb_data);
//}}}
assign mem_pipe_stalled = 1'b0;
`endif // PIPELINED_BUS_ACCESS
assign mem_rdbusy = ((mem_busy)&&(!mem_we));
// Either the prefetch or the instruction gets the memory bus, but
// never both.
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
//{{{
// Memory access to the arbiter, priority position
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
mem_we, mem_addr, mem_data, mem_sel,
mem_ack, mem_stall, mem_err,
// Prefetch access to the arbiter
//
// At a first glance, we might want something like:
//
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf,
//
// However, we know that the prefetch will not generate any
// writes. Therefore, the write specific lines (mem_data and
// mem_sel) can be shared with the memory in order to ease
// timing and LUT usage.
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel,
pf_ack, pf_stall, pf_err,
// Common wires, in and out, of the arbiter
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err);
//}}}
//}}}
//
//
//
//
//
//
//
//
// PIPELINE STAGE #5 :: Write-back results
//
//{{{
//
// This stage is not allowed to stall. If results are ready to be
// written back, they are written back at all cost. Sleepy CPU's
// won't prevent write back, nor debug modes, halting the CPU, nor
// anything else. Indeed, the (master_ce) bit is only as relevant
// as knowinig something is available for writeback.
//
// Write back to our generic register set ...
// When shall we write back? On one of two conditions
// Note that the flags needed to be checked before issuing the
// bus instruction, so they don't need to be checked here.
// Further, alu_wR includes (set_cond), so we don't need to
// check for that here either.
assign wr_reg_ce = (dbgv)||(mem_valid)
||((!clear_pipeline)&&(!alu_illegal)
&&(((alu_wR)&&(alu_valid))
||(div_valid)||(fpu_valid)));
// Which register shall be written?
// COULD SIMPLIFY THIS: by adding three bits to these registers,
// One or PC, one for CC, and one for GIE match
// Note that the alu_reg is the register to write on a divide or
// FPU operation.
`ifdef OPT_NO_USERMODE
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid)
? alu_reg[3:0]:mem_wreg[3:0];
assign wr_reg_id[4] = 1'b0;
`else
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg;
`endif
// Are we writing to the CC register?
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
// Are we writing to the PC?
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
// What value to write?
assign wr_gpreg_vl = ((mem_valid) ? mem_result
:((div_valid|fpu_valid))
? ((div_valid) ? div_result:fpu_result)
:((dbgv) ? dbg_val : alu_result));
assign wr_spreg_vl = ((mem_valid) ? mem_result
:((dbgv) ? dbg_val : alu_result));
always @(posedge i_clk)
if (wr_reg_ce)
`ifdef OPT_NO_USERMODE
regset[wr_reg_id[3:0]] <= wr_gpreg_vl;
`else
regset[wr_reg_id] <= wr_gpreg_vl;
`endif
//
// Write back to the condition codes/flags register ...
// When shall we write to our flags register? alu_wF already
// includes the set condition ...
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(!clear_pipeline)&&(!alu_illegal);
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
ubreak, step, 1'b1, sleep,
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
break_en, 1'b0, 1'b0, sleep,
((wr_flags_ce)&&(!alu_gie))?alu_flags:iflags };
// What value to write?
always @(posedge i_clk)
// If explicitly writing the register itself
if ((wr_reg_ce)&&(wr_write_ucc))
flags <= wr_gpreg_vl[3:0];
// Otherwise if we're setting the flags from an ALU operation
else if ((wr_flags_ce)&&(alu_gie))
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
always @(posedge i_clk)
if ((wr_reg_ce)&&(wr_write_scc))
iflags <= wr_gpreg_vl[3:0];
else if ((wr_flags_ce)&&(!alu_gie))
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
// The 'break' enable bit. This bit can only be set from supervisor
// mode. It control what the CPU does upon encountering a break
// instruction.
//
// The goal, upon encountering a break is that the CPU should stop and
// not execute the break instruction, choosing instead to enter into
// either interrupt mode or halt first.
// if ((break_en) AND (break_instruction)) // user mode or not
// HALT CPU
// else if (break_instruction) // only in user mode
// set an interrupt flag, set the user break bit,
// go to supervisor mode, allow supervisor to step the CPU.
// Upon a CPU halt, any break condition will be reset. The
// external debugger will then need to deal with whatever
// condition has taken place.
initial break_en = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_halt))
break_en <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_scc))
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
`ifdef OPT_PIPELINED
reg r_break_pending;
initial r_break_pending = 1'b0;
always @(posedge i_clk)
if ((clear_pipeline)||(!op_valid))
r_break_pending <= 1'b0;
else if (op_break)
r_break_pending <= (!alu_busy)&&(!div_busy)&&(!fpu_busy)&&(!mem_busy)&&(!wr_reg_ce);
else
r_break_pending <= 1'b0;
assign break_pending = r_break_pending;
`else
assign break_pending = op_break;
`endif
assign o_break = ((break_en)||(!op_gie))&&(break_pending)
&&(!clear_pipeline)
||((!alu_gie)&&(bus_err))
||((!alu_gie)&&(div_error))
||((!alu_gie)&&(fpu_error))
||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline));
// The sleep register. Setting the sleep register causes the CPU to
// sleep until the next interrupt. Setting the sleep register within
// interrupt mode causes the processor to halt until a reset. This is
// a panic/fault halt. The trick is that you cannot be allowed to
// set the sleep bit and switch to supervisor mode in the same
// instruction: users are not allowed to halt the CPU.
initial sleep = 1'b0;
`ifdef OPT_NO_USERMODE
reg r_sleep_is_halt;
initial r_sleep_is_halt = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_sleep_is_halt <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_cc)
&&(wr_spreg_vl[`CPU_SLEEP_BIT])
&&(!wr_spreg_vl[`CPU_GIE_BIT]))
r_sleep_is_halt <= 1'b1;
// Trying to switch to user mode, either via a WAIT or an RTU
// instruction will cause the CPU to sleep until an interrupt, in
// the NO-USERMODE build.
always @(posedge i_clk)
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt)))
sleep <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_cc)
&&(wr_spreg_vl[`CPU_GIE_BIT]))
sleep <= 1'b1;
`else
always @(posedge i_clk)
if ((i_rst)||(w_switch_to_interrupt))
sleep <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_cc)&&(!alu_gie))
// In supervisor mode, we have no protections. The
// supervisor can set the sleep bit however he wants.
// Well ... not quite. Switching to user mode and
// sleep mode shouold only be possible if the interrupt
// flag isn't set.
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
// don't set the sleep bit
// otherwise however it would o.w. be set
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
&&((!i_interrupt)||(!wr_spreg_vl[`CPU_GIE_BIT]));
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
// In user mode, however, you can only set the sleep
// mode while remaining in user mode. You can't switch
// to sleep mode *and* supervisor mode at the same
// time, lest you halt the CPU.
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
`endif
always @(posedge i_clk)
if (i_rst)
step <= 1'b0;
else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc))
step <= wr_spreg_vl[`CPU_STEP_BIT];
// The GIE register. Only interrupts can disable the interrupt register
`ifdef OPT_NO_USERMODE
assign w_switch_to_interrupt = 1'b0;
assign w_release_from_interrupt = 1'b0;
`else
assign w_switch_to_interrupt = (gie)&&(
// On interrupt (obviously)
((i_interrupt)&&(!alu_phase)&&(!bus_lock))
// If we are stepping the CPU
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(!alu_phase)&&(!bus_lock))
// If we encounter a break instruction, if the break
// enable isn't set.
||((master_ce)&&(break_pending)&&(!break_en))
// On an illegal instruction
||((alu_illegal)&&(!clear_pipeline))
// On division by zero. If the divide isn't
// implemented, div_valid and div_error will be short
// circuited and that logic will be bypassed
||(div_error)
// Same thing on a floating point error. Note that
// fpu_error must *never* be set unless fpu_valid is
// also set as well, else this will fail.
||(fpu_error)
//
||(bus_err)
// If we write to the CC register
||((wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
);
assign w_release_from_interrupt = (!gie)&&(!i_interrupt)
// Then if we write the sCC register
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
&&(wr_write_scc))
);
`endif
`ifdef OPT_NO_USERMODE
assign gie = 1'b0;
`else
reg r_gie;
initial r_gie = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_gie <= 1'b0;
else if (w_switch_to_interrupt)
r_gie <= 1'b0;
else if (w_release_from_interrupt)
r_gie <= 1'b1;
assign gie = r_gie;
`endif
`ifdef OPT_NO_USERMODE
assign trap = 1'b0;
assign ubreak = 1'b0;
`else
reg r_trap;
initial r_trap = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(w_release_from_interrupt))
r_trap <= 1'b0;
else if ((alu_gie)&&(wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
r_trap <= 1'b1;
else if ((wr_reg_ce)&&(wr_write_ucc)&&(!alu_gie))
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
reg r_ubreak;
initial r_ubreak = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(w_release_from_interrupt))
r_ubreak <= 1'b0;
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
r_ubreak <= 1'b1;
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
assign trap = r_trap;
assign ubreak = r_ubreak;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
initial ill_err_i = 1'b0;
always @(posedge i_clk)
if (i_rst)
ill_err_i <= 1'b0;
// Only the debug interface can clear this bit
else if ((dbgv)&&(wr_write_scc))
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
else if ((alu_illegal)&&(!alu_gie)&&(!clear_pipeline))
ill_err_i <= 1'b1;
`ifdef OPT_NO_USERMODE
assign ill_err_u = 1'b0;
`else
reg r_ill_err_u;
initial r_ill_err_u = 1'b0;
always @(posedge i_clk)
// The bit is automatically cleared on release from interrupt
// or reset
if ((i_rst)||(w_release_from_interrupt))
r_ill_err_u <= 1'b0;
// If the supervisor (or debugger) writes to this register,
// clearing the bit, then clear it
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
r_ill_err_u <= 1'b1;
assign ill_err_u = r_ill_err_u;
`endif
`else
assign ill_err_u = 1'b0;
assign ill_err_i = 1'b0;
`endif
// Supervisor/interrupt bus error flag -- this will crash the CPU if
// ever set.
initial ibus_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
ibus_err_flag <= 1'b0;
else if ((dbgv)&&(wr_write_scc))
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
else if ((bus_err)&&(!alu_gie))
ibus_err_flag <= 1'b1;
// User bus error flag -- if ever set, it will cause an interrupt to
// supervisor mode.
`ifdef OPT_NO_USERMODE
assign ubus_err_flag = 1'b0;
`else
reg r_ubus_err_flag;
initial r_ubus_err_flag = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(w_release_from_interrupt))
r_ubus_err_flag <= 1'b0;
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
else if ((bus_err)&&(alu_gie))
r_ubus_err_flag <= 1'b1;
assign ubus_err_flag = r_ubus_err_flag;
`endif
generate
if (IMPLEMENT_DIVIDE != 0)
begin
reg r_idiv_err_flag, r_udiv_err_flag;
// Supervisor/interrupt divide (by zero) error flag -- this will
// crash the CPU if ever set. This bit is thus available for us
// to be able to tell if/why the CPU crashed.
initial r_idiv_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_idiv_err_flag <= 1'b0;
else if ((dbgv)&&(wr_write_scc))
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
else if ((div_error)&&(!alu_gie))
r_idiv_err_flag <= 1'b1;
assign idiv_err_flag = r_idiv_err_flag;
`ifdef OPT_NO_USERMODE
assign udiv_err_flag = 1'b0;
`else
// User divide (by zero) error flag -- if ever set, it will
// cause a sudden switch interrupt to supervisor mode.
initial r_udiv_err_flag = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(w_release_from_interrupt))
r_udiv_err_flag <= 1'b0;
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
&&(wr_write_ucc))
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
else if ((div_error)&&(alu_gie))
r_udiv_err_flag <= 1'b1;
assign udiv_err_flag = r_udiv_err_flag;
`endif
end else begin
assign idiv_err_flag = 1'b0;
assign udiv_err_flag = 1'b0;
end endgenerate
generate
if (IMPLEMENT_FPU !=0)
begin
// Supervisor/interrupt floating point error flag -- this will
// crash the CPU if ever set.
reg r_ifpu_err_flag, r_ufpu_err_flag;
initial r_ifpu_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ifpu_err_flag <= 1'b0;
else if ((dbgv)&&(wr_write_scc))
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
else if ((fpu_error)&&(fpu_valid)&&(!alu_gie))
r_ifpu_err_flag <= 1'b1;
// User floating point error flag -- if ever set, it will cause
// a sudden switch interrupt to supervisor mode.
initial r_ufpu_err_flag = 1'b0;
always @(posedge i_clk)
if ((i_rst)&&(w_release_from_interrupt))
r_ufpu_err_flag <= 1'b0;
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
&&(wr_write_ucc))
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
r_ufpu_err_flag <= 1'b1;
assign ifpu_err_flag = r_ifpu_err_flag;
assign ufpu_err_flag = r_ufpu_err_flag;
end else begin
assign ifpu_err_flag = 1'b0;
assign ufpu_err_flag = 1'b0;
end endgenerate
`ifdef OPT_CIS
reg r_ihalt_phase;
initial r_ihalt_phase = 0;
always @(posedge i_clk)
if (i_rst)
r_ihalt_phase <= 1'b0;
else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline))
r_ihalt_phase <= alu_phase;
assign ihalt_phase = r_ihalt_phase;
`ifdef OPT_NO_USERMODE
assign uhalt_phase = 1'b0;
`else
reg r_uhalt_phase;
initial r_uhalt_phase = 0;
always @(posedge i_clk)
if ((i_rst)||(w_release_from_interrupt))
r_uhalt_phase <= 1'b0;
else if ((alu_gie)&&(alu_pc_valid))
r_uhalt_phase <= alu_phase;
else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
assign uhalt_phase = r_uhalt_phase;
`endif
`else
assign ihalt_phase = 1'b0;
assign uhalt_phase = 1'b0;
`endif
//
// Write backs to the PC register, and general increments of it
// We support two: upc and ipc. If the instruction is normal,
// we increment upc, if interrupt level we increment ipc. If
// the instruction writes the PC, we write whichever PC is appropriate.
//
// Do we need to all our partial results from the pipeline?
// What happens when the pipeline has gie and !gie instructions within
// it? Do we clear both? What if a gie instruction tries to clear
// a non-gie instruction?
`ifdef OPT_NO_USERMODE
assign upc = {(AW+2){1'b0}};
`else
reg [(AW+1):0] r_upc;
always @(posedge i_clk)
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
else if ((alu_gie)&&
(((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
||(mem_pc_valid)))
r_upc <= { alu_pc, 2'b00 };
assign upc = r_upc;
`endif
always @(posedge i_clk)
if (i_rst)
ipc <= { RESET_BUS_ADDRESS, 2'b00 };
else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc))
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
else if ((!alu_gie)&&(!alu_phase)&&
(((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
||(mem_pc_valid)))
ipc <= { alu_pc, 2'b00 };
always @(posedge i_clk)
if (i_rst)
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
else if ((w_switch_to_interrupt)||((!gie)&&(w_clear_icache)))
pf_pc <= { ipc[(AW+1):2], 2'b00 };
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
pf_pc <= { upc[(AW+1):2], 2'b00 };
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
else if ((dcd_early_branch)&&(!clear_pipeline))
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
// If we aren't pipelined, or equivalently if we have no cache, these
// instructions will get quietly (or not so quietly) ignored by the
// optimizer.
reg r_clear_icache;
initial r_clear_icache = 1'b1;
always @(posedge i_clk)
if ((i_rst)||(i_clear_pf_cache))
r_clear_icache <= 1'b1;
else if ((wr_reg_ce)&&(wr_write_scc))
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
else
r_clear_icache <= 1'b0;
assign w_clear_icache = r_clear_icache;
initial new_pc = 1'b1;
always @(posedge i_clk)
if ((i_rst)||(w_clear_icache))
new_pc <= 1'b1;
else if (w_switch_to_interrupt)
new_pc <= 1'b1;
else if (w_release_from_interrupt)
new_pc <= 1'b1;
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
new_pc <= 1'b1;
else
new_pc <= 1'b0;
//
// The debug write-back interface
//{{{
wire [31:0] w_debug_pc;
`ifdef OPT_NO_USERMODE
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 };
`else
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4])
? { upc[(AW+1):2], uhalt_phase, 1'b0 }
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } };
`endif
generate
if (AW<30)
assign w_debug_pc[31:(AW+2)] = 0;
endgenerate
always @(posedge i_clk)
begin
`ifdef OPT_NO_USERMODE
o_dbg_reg <= regset[i_dbg_reg[3:0]];
if (i_dbg_reg[3:0] == `CPU_PC_REG)
o_dbg_reg <= w_debug_pc;
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[14:0] <= w_iflags;
o_dbg_reg[15] <= 1'b0;
o_dbg_reg[31:23] <= w_cpu_info;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
`else
o_dbg_reg <= regset[i_dbg_reg];
if (i_dbg_reg[3:0] == `CPU_PC_REG)
o_dbg_reg <= w_debug_pc;
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[15] <= 1'b0;
o_dbg_reg[31:23] <= w_cpu_info;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
`endif
end
always @(posedge i_clk)
o_dbg_cc <= { o_break, bus_err, gie, sleep };
`ifdef OPT_PIPELINED
always @(posedge i_clk)
r_halted <= (i_halt)&&(
// To be halted, any long lasting instruction must
// be completed.
(!pf_cyc)&&(!mem_busy)&&(!alu_busy)
&&(!div_busy)&&(!fpu_busy)
// Operations must either be valid, or illegal
&&((op_valid)||(i_rst)||(dcd_illegal))
// Decode stage must be either valid, in reset, or ill
&&((dcd_valid)||(i_rst)||(pf_illegal)));
`else
always @(posedge i_clk)
r_halted <= (i_halt)&&((op_valid)||(i_rst));
`endif
assign o_dbg_stall = !r_halted;
//}}}
//}}}
//
//
// Produce accounting outputs: Account for any CPU stalls, so we can
// later evaluate how well we are doing.
//
//
assign o_op_stall = (master_ce)&&(op_stall);
assign o_pf_stall = (master_ce)&&(!pf_valid);
assign o_i_count = (alu_pc_valid)&&(!clear_pipeline);
`ifdef DEBUG_SCOPE
//{{{
always @(posedge i_clk)
o_debug <= {
/*
o_break, i_wb_err, pf_pc[1:0],
flags,
pf_valid, dcd_valid, op_valid, alu_valid, mem_valid,
op_ce, alu_ce, mem_ce,
//
master_ce, op_valid_alu, op_valid_mem,
//
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
mem_we,
// ((op_valid_alu)&&(alu_stall))
// ||((op_valid_mem)&&(~op_pipe)&&(mem_busy))
// ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
// op_Av[23:20], op_Av[3:0],
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
*/
/*
i_rst, master_ce, (new_pc),
((dcd_early_branch)&&(dcd_valid)),
pf_valid, pf_illegal,
op_ce, dcd_ce, dcd_valid, dcd_stalled,
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
pf_pc[7:0], pf_addr[7:0]
*/
i_wb_err, gie, alu_illegal,
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
mem_busy,
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
o_wb_addr[8:0] }
: { pf_instruction[31:21] },
pf_valid, (pf_valid) ? alu_pc[14:0]
:{ pf_cyc, pf_stb, pf_pc[14:2] }
/*
i_wb_err, gie, new_pc, dcd_early_branch, // 4
pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4
pf_instruction[30:27], // 4
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
dcd_valid,
((dcd_early_branch)&&(~clear_pipeline)) // 15
? dcd_branch_pc[14:0]:pf_pc[14:0]
*/
};
//}}}
`endif
// Make verilator happy
//{{{
// verilator lint_off UNUSED
wire [56:0] unused;
assign unused = { pf_new_pc,
fpu_ce, pf_data, wr_spreg_vl[1:0],
ipc[1:0], upc[1:0], pf_pc[1:0],
dcd_rA, dcd_pipe, dcd_zI,
dcd_A_stall, dcd_B_stall, dcd_F_stall,
op_Rcc, op_pipe, op_lock, mem_pipe_stalled, prelock_stall,
dcd_F };
generate if (AW+2 < 32)
begin
wire [31:(AW+2)] generic_ignore;
assign generic_ignore = wr_spreg_vl[31:(AW+2)];
end endgenerate
// verilator lint_on UNUSED
//}}}
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of enumerated type methods
//
// This code exercises the various enumeration methods
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
// **** Pin Identifiers ****
typedef enum int
{
PINID_A0 = 32'd0, // MUST BE ZERO!
// - Standard Ports -
PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7,
PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7,
PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7,
PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7,
PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7,
PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7,
PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7,
PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7,
// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1
PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7,
PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7,
PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7,
PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7,
PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7,
// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0
PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7,
PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7,
PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7,
// - AUX Port (Custom) -
PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7,
// - PDI Port -
PINID_D2W_DAT, PINID_D2W_CLK,
// - Power Pins -
PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3,
PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3,
// - Maximum number of pins -
PINID_MAX
} t_pinid;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
test test_i (/*AUTOINST*/
// Inputs
.clk (clk));
// This is a compile time only test. Immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module test (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Use the enumeration size to initialize a dynamic array
t_pinid e;
int myarray1 [] = new [e.num];
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Enumeration has %d members\n", e.num);
`endif
e = e.first;
forever begin
myarray1[e] <= e.prev;
`ifdef TEST_VERBOSE
$write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]);
`endif
if (e == e.last) begin
break;
end
else begin
e = e.next;
end
end
end
endmodule
|
// Model of FIFO in Altera
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 2048;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output wrempty;
output [10:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [10:0] rdusedw;
reg [10:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_2k
|
// DESCRIPTION::Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
typedef enum logic [1:0]
{ ZERO = 2'd0,
ONE = 2'd1,
TWO = 2'd2,
THREE = 2'd3,
XXX = 2'dx
} num_t;
function automatic logic is_odd;
input en;
input num_t number;
case (en)
1'b1: begin
unique if (number inside {ONE, THREE})
is_odd = 1'b1;
else if (number inside {ZERO, TWO})
is_odd = 1'b0;
else
is_odd = 1'bx;
end
1'b0: is_odd = 1'bx;
default: is_odd = 1'bx;
endcase
endfunction
function automatic bit is_00_to_04 (input byte value);
return value inside { [ 8'h0 : 8'h04 ] };
endfunction
function automatic bit is_fe_to_ff (input byte value);
return value inside { [ 8'hfe : 8'hff ] };
endfunction
initial begin
`checkh ((4'd4 inside {4'd1,4'd5}), 1'b0);
`checkh ((4'd4 inside {4'd1,4'd4}), 1'b1);
//
`checkh ((4'b1011 inside {4'b1001}), 1'b0);
`checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1??1}), 1'b1);
`ifndef VERILATOR
`checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx);
`endif
// Range
`checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches
`checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
//
// Unsupported $ bound
//
// Unsupported if unpacked array, elements tranversed
//int unpackedarray [$] = '{8,9};
//( expr inside {2, 3, unpackedarray}) // { 2,3,8,9}
//
`checkh (is_odd(1'b1, ZERO), 1'd0);
`checkh (is_odd(1'b1, ONE), 1'd1);
`checkh (is_odd(1'b1, TWO), 1'd0);
`checkh (is_odd(1'b1, THREE),1'd1);
`ifndef VERILATOR
`checkh (is_odd(1'b1, XXX), 1'dx);
`endif
//
// Should not give UNSIGNED/CMPCONST warnings
// (Verilator converts to 8'h00 >= 8'h00 which is always true)
`checkh(is_00_to_04(8'h00), 1'b1);
`checkh(is_00_to_04(8'h04), 1'b1);
`checkh(is_00_to_04(8'h05), 1'b0);
`checkh(is_fe_to_ff(8'hfd), 1'b0);
`checkh(is_fe_to_ff(8'hfe), 1'b1);
`checkh(is_fe_to_ff(8'hff), 1'b1);
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of case and if
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
st3_testbench st3_testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Closing message
// **************************************************************************
final begin
$write("*-* All Finished *-*\n");
end
endmodule
module st3_testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
logic clk;
logic rst;
logic [8*16-1:0] wide_input_bus;
logic decrementA; // 0=Up-counting, 1=down-counting
logic dual_countA; // Advance counter by 2 steps at a time
logic cntA_en; // Enable Counter A
logic decrementB; // 0=Up-counting, 1=down-counting
logic dual_countB; // Advance counter by 2 steps at a time
logic cntB_en; // Enable counter B
logic [47:0] selected_out;
integer i;
initial begin
decrementA = 1'b0;
dual_countA = 1'b0;
cntA_en = 1'b1;
decrementB = 1'b0;
dual_countB = 1'b0;
cntB_en = 1'b1;
wide_input_bus = {8'hf5,
8'hef,
8'hd5,
8'hc5,
8'hb5,
8'ha5,
8'h95,
8'h85,
8'ha7,
8'ha6,
8'ha5,
8'ha4,
8'ha3,
8'ha2,
8'ha1,
8'ha0};
i = 0;
end
simple_test_3
simple_test_3_i
(// Outputs
.selected_out (selected_out[47:0]),
// Inputs
.wide_input_bus (wide_input_bus[8*16-1:0]),
.rst (rst),
.clk (clk),
.decrementA (decrementA),
.dual_countA (dual_countA),
.cntA_en (cntA_en),
.decrementB (decrementB),
.dual_countB (dual_countB),
.cntB_en (cntB_en));
// Logic to print outputs and then finish.
always @(posedge clk) begin
if (i < 50) begin
`ifdef TEST_VERBOSE
$display("%x", simple_test_3_i.cntA_reg ,"%x",
simple_test_3_i.cntB_reg ," ", "%x", selected_out);
`endif
i <= i + 1;
end
else begin
$finish();
end
end // always @ (posedge clk)
endmodule
// Module testing:
// - Unique case
// - Priority case
// - Unique if
// - ++, --, =- and =+ operands.
module simple_test_3
(input logic [8*16-1:0] wide_input_bus,
input logic rst,
input logic clk,
// Counter A
input logic decrementA, // 0=Up-counting, 1=down-counting
input logic dual_countA, // Advance counter by 2 steps at a time
input logic cntA_en, // Enable Counter A
// Counter B
input logic decrementB, // 0=Up-counting, 1=down-counting
input logic dual_countB, // Advance counter by 2 steps at a time
input logic cntB_en, // Enable counter B
// Outputs
output logic [47:0] selected_out);
// Declarations
logic [3:0] cntA_reg; // Registered version of cntA
logic [3:0] cntB_reg; // Registered version of cntA
counterA
counterA_inst
(/*AUTOINST*/
// Outputs
.cntA_reg (cntA_reg[3:0]),
// Inputs
.decrementA (decrementA),
.dual_countA (dual_countA),
.cntA_en (cntA_en),
.clk (clk),
.rst (rst));
counterB
counterB_inst
(/*AUTOINST*/
// Outputs
.cntB_reg (cntB_reg[3:0]),
// Inputs
.decrementB (decrementB),
.dual_countB (dual_countB),
.cntB_en (cntB_en),
.clk (clk),
.rst (rst));
simple_test_3a
sta
(.wide_input_bus (wide_input_bus),
.selector (cntA_reg),
.selected_out (selected_out[7:0]));
simple_test_3b
stb
(.wide_input_bus (wide_input_bus),
.selector (cntA_reg),
.selected_out (selected_out[15:8]));
simple_test_3c
stc
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[23:16]));
simple_test_3d
std
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[31:24]));
simple_test_3e
ste
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[39:32]));
simple_test_3f
stf
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[47:40]));
endmodule // simple_test_3
module counterA
(output logic [3:0] cntA_reg, // Registered version of cntA
input logic decrementA, // 0=Up-counting, 1=down-counting
input logic dual_countA, // Advance counter by 2 steps at a time
input logic cntA_en, // Enable Counter A
input logic clk, // Clock
input logic rst); // Synchronous reset
logic [3:0] cntA; // combinational count variable.
// Counter A
// Sequential part of counter CntA
always_ff @(posedge clk)
begin
cntA_reg <= cntA;
end
// Combinational part of counter
// Had to be split up to test C-style update, as there are no
// non-blocking version like -<=
always_comb
if (rst)
cntA = 0;
else begin
cntA = cntA_reg; // Necessary to avoid latch
if (cntA_en) begin
if (decrementA)
if (dual_countA)
//cntA = cntA - 2;
cntA -= 2;
else
//cntA = cntA - 1;
cntA--;
else
if (dual_countA)
//cntA = cntA + 2;
cntA += 2;
else
//cntA = cntA + 1;
cntA++;
end // if (cntA_en)
end
endmodule // counterA
module counterB
(output logic [3:0] cntB_reg, // Registered version of cntA
input logic decrementB, // 0=Up-counting, 1=down-counting
input logic dual_countB, // Advance counter by 2 steps at a time
input logic cntB_en, // Enable counter B
input logic clk, // Clock
input logic rst); // Synchronous reset
// Counter B - tried to write sequential only, but ended up without
// SystemVerilog.
always_ff @(posedge clk) begin
if (rst)
cntB_reg <= 0;
else
if (cntB_en) begin
if (decrementB)
if (dual_countB)
cntB_reg <= cntB_reg - 2;
else
cntB_reg <= cntB_reg - 1;
// Attempts to write in SystemVerilog:
else
if (dual_countB)
cntB_reg <= cntB_reg + 2;
else
cntB_reg <= cntB_reg + 1;
// Attempts to write in SystemVerilog:
end
end // always_ff @
endmodule
// A multiplexor in terms of look-up
module simple_test_3a
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb
selected_out = {wide_input_bus[selector*8+7],
wide_input_bus[selector*8+6],
wide_input_bus[selector*8+5],
wide_input_bus[selector*8+4],
wide_input_bus[selector*8+3],
wide_input_bus[selector*8+2],
wide_input_bus[selector*8+1],
wide_input_bus[selector*8]};
endmodule // simple_test_3a
// A multiplexer in terms of standard case
module simple_test_3b
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
case (selector)
4'h0: selected_out = wide_input_bus[ 7: 0];
4'h1: selected_out = wide_input_bus[ 15: 8];
4'h2: selected_out = wide_input_bus[ 23: 16];
4'h3: selected_out = wide_input_bus[ 31: 24];
4'h4: selected_out = wide_input_bus[ 39: 32];
4'h5: selected_out = wide_input_bus[ 47: 40];
4'h6: selected_out = wide_input_bus[ 55: 48];
4'h7: selected_out = wide_input_bus[ 63: 56];
4'h8: selected_out = wide_input_bus[ 71: 64];
4'h9: selected_out = wide_input_bus[ 79: 72];
4'ha: selected_out = wide_input_bus[ 87: 80];
4'hb: selected_out = wide_input_bus[ 95: 88];
4'hc: selected_out = wide_input_bus[103: 96];
4'hd: selected_out = wide_input_bus[111:104];
4'he: selected_out = wide_input_bus[119:112];
4'hf: selected_out = wide_input_bus[127:120];
endcase // case (selector)
end
endmodule // simple_test_3b
// A multiplexer in terms of unique case
module simple_test_3c
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
unique case (selector)
4'h0: selected_out = wide_input_bus[ 7: 0];
4'h1: selected_out = wide_input_bus[ 15: 8];
4'h2: selected_out = wide_input_bus[ 23: 16];
4'h3: selected_out = wide_input_bus[ 31: 24];
4'h4: selected_out = wide_input_bus[ 39: 32];
4'h5: selected_out = wide_input_bus[ 47: 40];
4'h6: selected_out = wide_input_bus[ 55: 48];
4'h7: selected_out = wide_input_bus[ 63: 56];
4'h8: selected_out = wide_input_bus[ 71: 64];
4'h9: selected_out = wide_input_bus[ 79: 72];
4'ha: selected_out = wide_input_bus[ 87: 80];
4'hb: selected_out = wide_input_bus[ 95: 88];
4'hc: selected_out = wide_input_bus[103: 96];
4'hd: selected_out = wide_input_bus[111:104];
4'he: selected_out = wide_input_bus[119:112];
4'hf: selected_out = wide_input_bus[127:120];
endcase // case (selector)
end
endmodule // simple_test_3c
// A multiplexer in terms of unique if
module simple_test_3d
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
unique if (selector == 4'h0) selected_out = wide_input_bus[ 7: 0];
else if (selector == 4'h1) selected_out = wide_input_bus[ 15: 8];
else if (selector == 4'h2) selected_out = wide_input_bus[ 23: 16];
else if (selector == 4'h3) selected_out = wide_input_bus[ 31: 24];
else if (selector == 4'h4) selected_out = wide_input_bus[ 39: 32];
else if (selector == 4'h5) selected_out = wide_input_bus[ 47: 40];
else if (selector == 4'h6) selected_out = wide_input_bus[ 55: 48];
else if (selector == 4'h7) selected_out = wide_input_bus[ 63: 56];
else if (selector == 4'h8) selected_out = wide_input_bus[ 71: 64];
else if (selector == 4'h9) selected_out = wide_input_bus[ 79: 72];
else if (selector == 4'ha) selected_out = wide_input_bus[ 87: 80];
else if (selector == 4'hb) selected_out = wide_input_bus[ 95: 88];
else if (selector == 4'hc) selected_out = wide_input_bus[103: 96];
else if (selector == 4'hd) selected_out = wide_input_bus[111:104];
else if (selector == 4'he) selected_out = wide_input_bus[119:112];
else if (selector == 4'hf) selected_out = wide_input_bus[127:120];
end
endmodule // simple_test_3d
// Test of priority case
// Note: This does NOT try to implement the same function as above.
module simple_test_3e
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
priority case (1'b1)
selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority
selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1
selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2
selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority
default: selected_out = wide_input_bus[127:120]; // for selector = 0.
endcase // case (selector)
end
endmodule // simple_test_3e
// Test of "inside"
// Note: This does NOT try to implement the same function as above.
// Note: Support for "inside" is a separate Verilator feature request, so is
// not used inside a this version of the test.
module simple_test_3f
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
/* -----\/----- EXCLUDED -----\/-----
if ( selector[3:0] inside { 4'b?00?, 4'b1100}) // Matching 0000, 0001, 1000, 1100, 1001
// if ( selector[3:2] inside { 2'b?0, selector[1:0]})
selected_out = wide_input_bus[ 7: 0];
else
-----/\----- EXCLUDED -----/\----- */
/* verilator lint_off CASEOVERLAP */
priority casez (selector[3:0])
4'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110
4'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in "if" above)
4'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur
default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111
endcase // case (selector)
/* verilator lint_on CASEOVERLAP */
end
endmodule // simple_test_3f
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_1_V
`define SKY130_FD_SC_LP__A2111O_1_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_1_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../niosII_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "niosII_system_onchip_memory2_0.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: msu_databuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module msu_databuf (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]"
// Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_4_V
`define SKY130_FD_SC_HDLL__NAND3_4_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_4_V
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Listens for configuration command updates.
* This will parse out configuration commands. Currently it only listens for
* a few specific configuration values including:
* -max payload size
* -BAR0 - 5 Addresses
* Changes:
* 3/24/2016: Initial Version
*/
`include "pcie_defines.v"
`define MAX_READ_COUNT 5
module config_parser (
input rst,
input clk,
input i_en,
output reg o_finished,
// Host (CFG) Interface
input [31:0] i_cfg_do,
input i_cfg_rd_wr_done,
output reg [9:0] o_cfg_dwaddr,
output reg o_cfg_rd_en,
//AXI Stream Input
output reg [31:0] o_bar_addr0,
output reg [31:0] o_bar_addr1,
output reg [31:0] o_bar_addr2,
output reg [31:0] o_bar_addr3,
output reg [31:0] o_bar_addr4,
output reg [31:0] o_bar_addr5
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PREP_ADDR = 4'h1;
localparam WAIT_STATE = 4'h2;
localparam READ_DATA = 4'h3;
localparam READ_NEXT = 4'h4;
//Registers/Wires
reg [3:0] state;
reg [3:0] index;
wire [9:0] w_cfg_addr[0:`MAX_READ_COUNT];
//Submodules
//Asynchronous Logic
//Get Header Size
assign w_cfg_addr[0] = `BAR_ADDR0 >> 2;
assign w_cfg_addr[1] = `BAR_ADDR1 >> 2;
assign w_cfg_addr[2] = `BAR_ADDR2 >> 2;
assign w_cfg_addr[3] = `BAR_ADDR3 >> 2;
assign w_cfg_addr[4] = `BAR_ADDR4 >> 2;
assign w_cfg_addr[5] = `BAR_ADDR5 >> 2;
//Synchronous Logic
always @ (posedge clk) begin
o_cfg_rd_en <= 0;
if (rst) begin
state <= IDLE;
index <= 0;
o_cfg_dwaddr <= w_cfg_addr[0];
o_bar_addr0 <= 0;
o_bar_addr1 <= 0;
o_bar_addr2 <= 0;
o_bar_addr3 <= 0;
o_bar_addr4 <= 0;
o_bar_addr5 <= 0;
o_finished <= 0;
end
else begin
case (state)
IDLE: begin
o_finished <= 0;
index <= 0;
if (i_en) begin
state <= PREP_ADDR;
end
end
PREP_ADDR: begin
case (index)
0: begin
//o_cfg_dwaddr <= `BAR_ADDR0 >> 2;
o_cfg_dwaddr <= 4;
end
1: begin
//o_cfg_dwaddr <= `BAR_ADDR1 >> 2;
o_cfg_dwaddr <= 5;
end
2: begin
//o_cfg_dwaddr <= `BAR_ADDR2 >> 2;
o_cfg_dwaddr <= 6;
end
3: begin
//o_cfg_dwaddr <= `BAR_ADDR3 >> 2;
o_cfg_dwaddr <= 7;
end
4: begin
//o_cfg_dwaddr <= `BAR_ADDR4 >> 2;
o_cfg_dwaddr <= 8;
end
5: begin
//o_cfg_dwaddr <= `BAR_ADDR5 >> 2;
o_cfg_dwaddr <= 9;
end
endcase
state <= WAIT_STATE;
end
WAIT_STATE: begin
o_cfg_rd_en <= 1;
if (i_cfg_rd_wr_done) begin
state <= READ_DATA;
end
end
READ_DATA: begin
o_cfg_rd_en <= 1;
if (i_cfg_rd_wr_done) begin
case (index)
0: begin
o_bar_addr0 <= i_cfg_do;
end
1: begin
o_bar_addr1 <= i_cfg_do;
end
2: begin
o_bar_addr2 <= i_cfg_do;
end
3: begin
o_bar_addr3 <= i_cfg_do;
end
4: begin
o_bar_addr4 <= i_cfg_do;
end
5: begin
o_bar_addr5 <= i_cfg_do;
end
default: begin
end
endcase
state <= READ_NEXT;
end
end
READ_NEXT: begin
if (!i_cfg_rd_wr_done) begin
if (index < `MAX_READ_COUNT + 1) begin
state <= PREP_ADDR;
index <= index + 1;
end
else begin
o_finished <= 1;
if (!i_en) begin
state <= IDLE;
end
end
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N16_M4_P4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LOAGDA_St_N16_M4_P4(
input [15:0] in1,
input [15:0] in2,
output [16:0] res
);
wire [4:0] temp1, temp2, temp3, temp4;
//C4
wire g0,g1,g2,g3,p0,p1,p2,p3;
wire p3g2,p3p2,p3p2g1,p3p2p1,p3p2p1g0;
wire res_or_1, res_or_2;
wire c4;
and and_3(g3,in1[3],in2[3]);
and and_2(g2,in1[2],in2[2]);
and and_1(g1,in1[1],in2[1]);
and and_0(g0,in1[0],in2[0]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
and and_4(p3g2,p3,g2);
and and_5(p3p2,p3,p2);
and and_6(p3p2g1,p3p2,g1);
and and_7(p3p2p1,p3p2,p1);
and and_8(p3p2p1g0,p3p2p1,g0);
or or_3(res_or_1,g3,p3g2);
or or_2(res_or_2,p3p2g1,p3p2p1g0);
or or_1(c4,res_or_1,res_or_2);
//C8
wire g4,g5,g6,g7,p4,p5,p6,p7;
wire p7g6,p7p6,p7p6g5,p7p6p5,p7p6p5g4;
wire res_or_3, res_or_4;
wire c8;
and and_9 (g7,in1[7],in2[7]);
and and_10(g6,in1[6],in2[6]);
and and_11(g5,in1[5],in2[5]);
and and_12(g4,in1[4],in2[4]);
xor xor_7(p7,in1[7],in2[7]);
xor xor_6(p6,in1[6],in2[6]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
and and_13(p7g6,p7,g6);
and and_14(p7p6,p7,p6);
and and_15(p7p6g5,p7p6,g5);
and and_16(p7p6p5,p7p6,p5);
and and_17(p7p6p5g4,p7p6p5,g4);
or or_6(res_or_3,g7,p7g6);
or or_5(res_or_4,p7p6g5,p7p6p5g4);
or or_4(c8,res_or_3,res_or_4);
//C12
wire g8,g9,g10,g11,p8,p9,p10,p11;
wire p11g10,p11p10,p11p10g9,p11p10p9;
wire res_or_5, res_or_6;
wire c12;
and and_18(g11,in1[11],in2[11]);
and and_19(g10,in1[10],in2[10]);
and and_20(g9,in1[9],in2[9]);
and and_21(g8,in1[8],in2[8]);
xor xor_11(p11,in1[11],in2[11]);
xor xor_10(p10,in1[10],in2[10]);
xor xor_9(p9,in1[9],in2[9]);
xor xor_8(p8,in1[8],in2[8]);
and and_22(p11g10,p11,g10);
and and_23(p11p10,p11,p10);
and and_24(p11p10g9,p11p10,g9);
and and_25(p11p10p9,p11p10,p9);
and and_26(p11p10p9g8,p11p10p9,g8);
or or_9(res_or_5,g11,p11g10);
or or_8(res_or_6,p11p10g9,p11p10p9g8);
or or_7(c12,res_or_5,res_or_6);
// Results
assign temp1[4:0] = (in1[ 3: 0] | in2[ 3: 0]);
assign temp2[4:0] = (in1[ 7: 4] | in2[ 7: 4]) + c4;
assign temp3[4:0] = (in1[11: 8] + in2[11: 8]) + c8;
assign temp4[4:0] = in1[15:12] + in2[15:12] + c12;
assign res[16:0] = {temp4[4:0],temp3[3:0],temp2[3:0],temp1[3:0]};
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_crossbar_v2_1_8_axi_crossbar,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=7,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x000000004044000000000000404300000000000040420000000000004041000000000000404000000000000043c000000000000041200000,C_M_AXI_ADDR_WIDTH=0x00000010000000100000001000000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *)
output wire [223 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *)
output wire [27 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *)
input wire [223 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_rready;
axi_crossbar_v2_1_8_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(7),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(448'H000000004044000000000000404300000000000040420000000000004041000000000000404000000000000043c000000000000041200000),
.C_M_AXI_ADDR_WIDTH(224'H00000010000000100000001000000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(224'H00000000000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(7'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(7'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(7'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(7'H7F),
.m_axi_ruser(7'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Barrel Shifter for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Provides 32-bit shifts LSL, LSR, ASR and ROR //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_barrel_shift (
input [31:0] i_in,
input i_carry_in,
input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
input [1:0] i_function,
output [31:0] o_out,
output o_carry_out
);
`include "a23_localparams.vh"
// MSB is carry out
wire [32:0] lsl_out;
wire [32:0] lsr_out;
wire [32:0] asr_out;
wire [32:0] ror_out;
// Logical shift right zero is redundant as it is the same as logical shift left zero, so
// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow
// lsr #32 to be specified.
// lsl #0 is a special case, where the shifter carry out is the old value of the status flags
// C flag. The contents of Rm are used directly as the second operand.
// assign lsl_out = i_shift_imm_zero ? {i_carry_in, i_in } : // fall through case
// i_shift_amount == 8'd 0 ? {i_carry_in, i_in } : // fall through case
// i_shift_amount == 8'd 1 ? {i_in[31], i_in[30: 0], 1'd0} :
// i_shift_amount == 8'd 2 ? {i_in[30], i_in[29: 0], 2'd0} :
// i_shift_amount == 8'd 3 ? {i_in[29], i_in[28: 0], 3'd0} :
// i_shift_amount == 8'd 4 ? {i_in[28], i_in[27: 0], 4'd0} :
// i_shift_amount == 8'd 5 ? {i_in[27], i_in[26: 0], 5'd0} :
// i_shift_amount == 8'd 6 ? {i_in[26], i_in[25: 0], 6'd0} :
// i_shift_amount == 8'd 7 ? {i_in[25], i_in[24: 0], 7'd0} :
// i_shift_amount == 8'd 8 ? {i_in[24], i_in[23: 0], 8'd0} :
// i_shift_amount == 8'd 9 ? {i_in[23], i_in[22: 0], 9'd0} :
// i_shift_amount == 8'd10 ? {i_in[22], i_in[21: 0], 10'd0} :
// i_shift_amount == 8'd11 ? {i_in[21], i_in[20: 0], 11'd0} :
// i_shift_amount == 8'd12 ? {i_in[20], i_in[19: 0], 12'd0} :
// i_shift_amount == 8'd13 ? {i_in[19], i_in[18: 0], 13'd0} :
// i_shift_amount == 8'd14 ? {i_in[18], i_in[17: 0], 14'd0} :
// i_shift_amount == 8'd15 ? {i_in[17], i_in[16: 0], 15'd0} :
// i_shift_amount == 8'd16 ? {i_in[16], i_in[15: 0], 16'd0} :
// i_shift_amount == 8'd17 ? {i_in[15], i_in[14: 0], 17'd0} :
// i_shift_amount == 8'd18 ? {i_in[14], i_in[13: 0], 18'd0} :
// i_shift_amount == 8'd19 ? {i_in[13], i_in[12: 0], 19'd0} :
// i_shift_amount == 8'd20 ? {i_in[12], i_in[11: 0], 20'd0} :
// i_shift_amount == 8'd21 ? {i_in[11], i_in[10: 0], 21'd0} :
// i_shift_amount == 8'd22 ? {i_in[10], i_in[ 9: 0], 22'd0} :
// i_shift_amount == 8'd23 ? {i_in[ 9], i_in[ 8: 0], 23'd0} :
// i_shift_amount == 8'd24 ? {i_in[ 8], i_in[ 7: 0], 24'd0} :
// i_shift_amount == 8'd25 ? {i_in[ 7], i_in[ 6: 0], 25'd0} :
// i_shift_amount == 8'd26 ? {i_in[ 6], i_in[ 5: 0], 26'd0} :
// i_shift_amount == 8'd27 ? {i_in[ 5], i_in[ 4: 0], 27'd0} :
// i_shift_amount == 8'd28 ? {i_in[ 4], i_in[ 3: 0], 28'd0} :
// i_shift_amount == 8'd29 ? {i_in[ 3], i_in[ 2: 0], 29'd0} :
// i_shift_amount == 8'd30 ? {i_in[ 2], i_in[ 1: 0], 30'd0} :
// i_shift_amount == 8'd31 ? {i_in[ 1], i_in[ 0: 0], 31'd0} :
// i_shift_amount == 8'd32 ? {i_in[ 0], 32'd0 } : // 32
// {1'd0, 32'd0 } ; // > 32
wire [32:0] lsl_out_struct;
lsl_struct #(.CTRL(5)) u_lsl_struct(i_in, i_shift_amount[4:0], lsl_out_struct);
assign lsl_out[32] = i_shift_amount == 5'd0 ? i_carry_in: lsl_out_struct[32];
assign lsl_out[31:0] = lsl_out_struct[31:0];
// The form of the shift field which might be expected to correspond to LSR #0 is used
// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output.
// carry out, < -------- out ---------->
// assign lsr_out = i_shift_imm_zero ? {i_in[31], 32'd0 } :
// i_shift_amount == 8'd 0 ? {i_carry_in, i_in } : // fall through case
// i_shift_amount == 8'd 1 ? {i_in[ 0], 1'd0, i_in[31: 1]} :
// i_shift_amount == 8'd 2 ? {i_in[ 1], 2'd0, i_in[31: 2]} :
// i_shift_amount == 8'd 3 ? {i_in[ 2], 3'd0, i_in[31: 3]} :
// i_shift_amount == 8'd 4 ? {i_in[ 3], 4'd0, i_in[31: 4]} :
// i_shift_amount == 8'd 5 ? {i_in[ 4], 5'd0, i_in[31: 5]} :
// i_shift_amount == 8'd 6 ? {i_in[ 5], 6'd0, i_in[31: 6]} :
// i_shift_amount == 8'd 7 ? {i_in[ 6], 7'd0, i_in[31: 7]} :
// i_shift_amount == 8'd 8 ? {i_in[ 7], 8'd0, i_in[31: 8]} :
// i_shift_amount == 8'd 9 ? {i_in[ 8], 9'd0, i_in[31: 9]} :
// i_shift_amount == 8'd10 ? {i_in[ 9], 10'd0, i_in[31:10]} :
// i_shift_amount == 8'd11 ? {i_in[10], 11'd0, i_in[31:11]} :
// i_shift_amount == 8'd12 ? {i_in[11], 12'd0, i_in[31:12]} :
// i_shift_amount == 8'd13 ? {i_in[12], 13'd0, i_in[31:13]} :
// i_shift_amount == 8'd14 ? {i_in[13], 14'd0, i_in[31:14]} :
// i_shift_amount == 8'd15 ? {i_in[14], 15'd0, i_in[31:15]} :
// i_shift_amount == 8'd16 ? {i_in[15], 16'd0, i_in[31:16]} :
// i_shift_amount == 8'd17 ? {i_in[16], 17'd0, i_in[31:17]} :
// i_shift_amount == 8'd18 ? {i_in[17], 18'd0, i_in[31:18]} :
// i_shift_amount == 8'd19 ? {i_in[18], 19'd0, i_in[31:19]} :
// i_shift_amount == 8'd20 ? {i_in[19], 20'd0, i_in[31:20]} :
// i_shift_amount == 8'd21 ? {i_in[20], 21'd0, i_in[31:21]} :
// i_shift_amount == 8'd22 ? {i_in[21], 22'd0, i_in[31:22]} :
// i_shift_amount == 8'd23 ? {i_in[22], 23'd0, i_in[31:23]} :
// i_shift_amount == 8'd24 ? {i_in[23], 24'd0, i_in[31:24]} :
// i_shift_amount == 8'd25 ? {i_in[24], 25'd0, i_in[31:25]} :
// i_shift_amount == 8'd26 ? {i_in[25], 26'd0, i_in[31:26]} :
// i_shift_amount == 8'd27 ? {i_in[26], 27'd0, i_in[31:27]} :
// i_shift_amount == 8'd28 ? {i_in[27], 28'd0, i_in[31:28]} :
// i_shift_amount == 8'd29 ? {i_in[28], 29'd0, i_in[31:29]} :
// i_shift_amount == 8'd30 ? {i_in[29], 30'd0, i_in[31:30]} :
// i_shift_amount == 8'd31 ? {i_in[30], 31'd0, i_in[31 ]} :
// i_shift_amount == 8'd32 ? {i_in[31], 32'd0 } :
// {1'd0, 32'd0 } ; // > 32
wire [32:0] lsr_out_struct;
lsr_struct #(.CTRL(5)) u_lsr_struct(i_in, i_shift_amount[4:0], lsr_out_struct);
assign lsr_out[32] = i_shift_amount == 5'd0 ? i_carry_in: lsr_out_struct[32];
assign lsr_out[31:0] = lsr_out_struct[31:0];
// The form of the shift field which might be expected to give ASR #0 is used to encode
// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is
// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to
// the value of bit 31 of Rm.
// carry out, < -------- out ---------->
// assign asr_out = i_shift_imm_zero ? {i_in[31], {32{i_in[31]}} } :
// i_shift_amount == 8'd 0 ? {i_carry_in, i_in } : // fall through case
// i_shift_amount == 8'd 1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} :
// i_shift_amount == 8'd 2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} :
// i_shift_amount == 8'd 3 ? {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} :
// i_shift_amount == 8'd 4 ? {i_in[ 3], { 5{i_in[31]}}, i_in[30: 4]} :
// i_shift_amount == 8'd 5 ? {i_in[ 4], { 6{i_in[31]}}, i_in[30: 5]} :
// i_shift_amount == 8'd 6 ? {i_in[ 5], { 7{i_in[31]}}, i_in[30: 6]} :
// i_shift_amount == 8'd 7 ? {i_in[ 6], { 8{i_in[31]}}, i_in[30: 7]} :
// i_shift_amount == 8'd 8 ? {i_in[ 7], { 9{i_in[31]}}, i_in[30: 8]} :
// i_shift_amount == 8'd 9 ? {i_in[ 8], {10{i_in[31]}}, i_in[30: 9]} :
// i_shift_amount == 8'd10 ? {i_in[ 9], {11{i_in[31]}}, i_in[30:10]} :
// i_shift_amount == 8'd11 ? {i_in[10], {12{i_in[31]}}, i_in[30:11]} :
// i_shift_amount == 8'd12 ? {i_in[11], {13{i_in[31]}}, i_in[30:12]} :
// i_shift_amount == 8'd13 ? {i_in[12], {14{i_in[31]}}, i_in[30:13]} :
// i_shift_amount == 8'd14 ? {i_in[13], {15{i_in[31]}}, i_in[30:14]} :
// i_shift_amount == 8'd15 ? {i_in[14], {16{i_in[31]}}, i_in[30:15]} :
// i_shift_amount == 8'd16 ? {i_in[15], {17{i_in[31]}}, i_in[30:16]} :
// i_shift_amount == 8'd17 ? {i_in[16], {18{i_in[31]}}, i_in[30:17]} :
// i_shift_amount == 8'd18 ? {i_in[17], {19{i_in[31]}}, i_in[30:18]} :
// i_shift_amount == 8'd19 ? {i_in[18], {20{i_in[31]}}, i_in[30:19]} :
// i_shift_amount == 8'd20 ? {i_in[19], {21{i_in[31]}}, i_in[30:20]} :
// i_shift_amount == 8'd21 ? {i_in[20], {22{i_in[31]}}, i_in[30:21]} :
// i_shift_amount == 8'd22 ? {i_in[21], {23{i_in[31]}}, i_in[30:22]} :
// i_shift_amount == 8'd23 ? {i_in[22], {24{i_in[31]}}, i_in[30:23]} :
// i_shift_amount == 8'd24 ? {i_in[23], {25{i_in[31]}}, i_in[30:24]} :
// i_shift_amount == 8'd25 ? {i_in[24], {26{i_in[31]}}, i_in[30:25]} :
// i_shift_amount == 8'd26 ? {i_in[25], {27{i_in[31]}}, i_in[30:26]} :
// i_shift_amount == 8'd27 ? {i_in[26], {28{i_in[31]}}, i_in[30:27]} :
// i_shift_amount == 8'd28 ? {i_in[27], {29{i_in[31]}}, i_in[30:28]} :
// i_shift_amount == 8'd29 ? {i_in[28], {30{i_in[31]}}, i_in[30:29]} :
// i_shift_amount == 8'd30 ? {i_in[29], {31{i_in[31]}}, i_in[30 ]} :
// i_shift_amount == 8'd31 ? {i_in[30], {32{i_in[31]}} } :
// {i_in[31], {32{i_in[31]}} } ; // >= 32
wire [32:0] asr_out_struct;
asr_struct #(.CTRL(5)) u_asr_struct(i_in, i_shift_amount[4:0], asr_out_struct);
assign asr_out[32] = i_shift_amount == 5'd0 ? i_carry_in: asr_out_struct[32];
assign asr_out[31:0] = asr_out_struct[31:0];
// carry out, < ------- out --------->
// assign ror_out = i_shift_imm_zero ? {i_in[ 0], i_carry_in, i_in[31: 1]} : // RXR, (ROR w/ imm 0)
// i_shift_amount[7:0] == 8'd 0 ? {i_carry_in, i_in } : // fall through case
// i_shift_amount[4:0] == 5'd 0 ? {i_in[31], i_in } : // Rs > 31
// i_shift_amount[4:0] == 5'd 1 ? {i_in[ 0], i_in[ 0], i_in[31: 1]} :
// i_shift_amount[4:0] == 5'd 2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} :
// i_shift_amount[4:0] == 5'd 3 ? {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} :
// i_shift_amount[4:0] == 5'd 4 ? {i_in[ 3], i_in[ 3: 0], i_in[31: 4]} :
// i_shift_amount[4:0] == 5'd 5 ? {i_in[ 4], i_in[ 4: 0], i_in[31: 5]} :
// i_shift_amount[4:0] == 5'd 6 ? {i_in[ 5], i_in[ 5: 0], i_in[31: 6]} :
// i_shift_amount[4:0] == 5'd 7 ? {i_in[ 6], i_in[ 6: 0], i_in[31: 7]} :
// i_shift_amount[4:0] == 5'd 8 ? {i_in[ 7], i_in[ 7: 0], i_in[31: 8]} :
// i_shift_amount[4:0] == 5'd 9 ? {i_in[ 8], i_in[ 8: 0], i_in[31: 9]} :
// i_shift_amount[4:0] == 5'd10 ? {i_in[ 9], i_in[ 9: 0], i_in[31:10]} :
// i_shift_amount[4:0] == 5'd11 ? {i_in[10], i_in[10: 0], i_in[31:11]} :
// i_shift_amount[4:0] == 5'd12 ? {i_in[11], i_in[11: 0], i_in[31:12]} :
// i_shift_amount[4:0] == 5'd13 ? {i_in[12], i_in[12: 0], i_in[31:13]} :
// i_shift_amount[4:0] == 5'd14 ? {i_in[13], i_in[13: 0], i_in[31:14]} :
// i_shift_amount[4:0] == 5'd15 ? {i_in[14], i_in[14: 0], i_in[31:15]} :
// i_shift_amount[4:0] == 5'd16 ? {i_in[15], i_in[15: 0], i_in[31:16]} :
// i_shift_amount[4:0] == 5'd17 ? {i_in[16], i_in[16: 0], i_in[31:17]} :
// i_shift_amount[4:0] == 5'd18 ? {i_in[17], i_in[17: 0], i_in[31:18]} :
// i_shift_amount[4:0] == 5'd19 ? {i_in[18], i_in[18: 0], i_in[31:19]} :
// i_shift_amount[4:0] == 5'd20 ? {i_in[19], i_in[19: 0], i_in[31:20]} :
// i_shift_amount[4:0] == 5'd21 ? {i_in[20], i_in[20: 0], i_in[31:21]} :
// i_shift_amount[4:0] == 5'd22 ? {i_in[21], i_in[21: 0], i_in[31:22]} :
// i_shift_amount[4:0] == 5'd23 ? {i_in[22], i_in[22: 0], i_in[31:23]} :
// i_shift_amount[4:0] == 5'd24 ? {i_in[23], i_in[23: 0], i_in[31:24]} :
// i_shift_amount[4:0] == 5'd25 ? {i_in[24], i_in[24: 0], i_in[31:25]} :
// i_shift_amount[4:0] == 5'd26 ? {i_in[25], i_in[25: 0], i_in[31:26]} :
// i_shift_amount[4:0] == 5'd27 ? {i_in[26], i_in[26: 0], i_in[31:27]} :
// i_shift_amount[4:0] == 5'd28 ? {i_in[27], i_in[27: 0], i_in[31:28]} :
// i_shift_amount[4:0] == 5'd29 ? {i_in[28], i_in[28: 0], i_in[31:29]} :
// i_shift_amount[4:0] == 5'd30 ? {i_in[29], i_in[29: 0], i_in[31:30]} :
// {i_in[30], i_in[30: 0], i_in[31:31]} ;
wire [32:0] ror_out_struct;
ror_struct #(.CTRL(5)) u_ror_struct(i_in, i_shift_amount[4:0], ror_out_struct);
assign ror_out[32] = i_shift_amount == 5'd0 ? i_carry_in: ror_out_struct[32];
assign ror_out[31:0] = ror_out_struct[31:0];
assign {o_carry_out, o_out} = i_function == LSL ? lsl_out :
i_function == LSR ? lsr_out :
i_function == ASR ? asr_out :
ror_out ;
endmodule
module ror_struct
#(
parameter CTRL=5,
parameter WIDTH=2**CTRL
)
(
input [WIDTH-1:0] in,
input [ CTRL-1:0] shift,
output [WIDTH:0] out
);
wire [WIDTH:0] tmp [CTRL:0];
assign tmp[CTRL] = {in[31], in};
assign out = tmp[0];
genvar i;
generate
for (i = 0; i < CTRL; i = i + 1) begin: mux
assign tmp[i] = shift[i] ? {tmp[i+1][(2**i)-1], tmp[i+1][(2**i)-1:0],tmp[i+1][WIDTH-1:(2**i)]} : tmp[i+1];
end
endgenerate
endmodule
module asr_struct
#(
parameter CTRL=5,
parameter WIDTH=2**CTRL
)
(
input [WIDTH-1:0] in,
input [ CTRL-1:0] shift,
output [WIDTH:0] out
);
wire sign = in[WIDTH -1];
wire [WIDTH:0] tmp [CTRL:0];
assign tmp[CTRL] = {in[0], in};
assign out = tmp[0];
genvar i;
generate
for (i = 0; i < CTRL; i = i + 1) begin: mux
assign tmp[i] = shift[i] ? {tmp[i+1][(2**i)-1], {(2**i){sign}}, tmp[i+1][WIDTH-1:(2**i)]} : tmp[i+1];
end
endgenerate
endmodule
module lsr_struct
#(
parameter CTRL=5,
parameter WIDTH=2**CTRL
)
(
input [WIDTH-1:0] in,
input [ CTRL-1:0] shift,
output [WIDTH:0] out
);
wire sign = 1'b0;
wire [WIDTH:0] tmp [CTRL:0];
assign tmp[CTRL] = {in[0], in};
assign out = tmp[0];
genvar i;
generate
for (i = 0; i < CTRL; i = i + 1) begin: mux
assign tmp[i] = shift[i] ? {tmp[i+1][(2**i)-1], {(2**i){sign}}, tmp[i+1][WIDTH-1:(2**i)]} : tmp[i+1];
end
endgenerate
endmodule
module lsl_struct
#(
parameter CTRL=5,
parameter WIDTH=2**CTRL
)
(
input [WIDTH-1:0] in,
input [ CTRL-1:0] shift,
output [WIDTH:0] out
);
wire [WIDTH:0] tmp [CTRL:0];
assign tmp[CTRL] = {in[WIDTH-1], in};
assign out = tmp[0];
genvar i, j;
generate
for (i = 0; i < CTRL; i = i + 1) begin: mux
assign tmp[i] = shift[i] ? {tmp[i+1][WIDTH-(2**i)], tmp[i+1][WIDTH-(2**i)-1:0], {(2**i){1'b0}}} : tmp[i+1];
end
endgenerate
endmodule
|
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt51_kon(
input rst,
input clk,
input cen,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] cur_op,
input [2:0] cur_ch,
input up_keyon,
input csm,
input overflow_A,
output reg keyon_II
);
//reg csm_copy;
reg din;
wire drop;
reg [3:0] cur_op_hot;
always @(posedge clk) if (cen)
keyon_II <= (csm&&overflow_A) || drop;
always @(*) begin
case( cur_op )
2'd0: cur_op_hot = 4'b0001; // S1 / M1
2'd1: cur_op_hot = 4'b0100; // S3 / M2
2'd2: cur_op_hot = 4'b0010; // S2 / C1
2'd3: cur_op_hot = 4'b1000; // S4 / C2
endcase
din = keyon_ch==cur_ch && up_keyon ? |(keyon_op&cur_op_hot) : drop;
end
jt51_sh #(.width(1),.stages(32)) u_konch(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.drop ( drop )
);
endmodule
|
/************************************************
* *
* Derek Prince *
* ECEN 2350: Digital Logic *
* 2n-bit Comparator on the terasiC DE0 board *
* Altera Cyclone 3 EP3C16F484 *
* *
* Date: October 11th, 2016 *
* Last Modified: October 16th, 2016 *
* *
*************************************************
Copyright (c) 2016 Derek Prince
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
// X has priority. Meaning, if greater than is 1: X is greater than Y. Same goes for lt = 1.
module doublencomparator(x0, x1, y0, y1, eqin, gtin, ltin, eqout, gtout, ltout);
input x0, x1, y0, y1; // input bit pairs
input eqin, gtin, ltin; // carry inputs (eq = equal, gt = greater than, lt = less than)
output eqout, gtout, ltout; // outputs
// Equality
// every bit needs to be equal for it to be equal. Astonishing, right?
// This means that if eqin is 0 already, the whole thing is 0.
// Which is good, otherwise the final output might say that 0001 is equal to 1101.
assign eqout = eqin & (x0 ~^ y0) & (x1 ~^ y1);
// COST:
// If we assume the XOR gate is a NAND, AND, & OR gate, each with only two inputs, that means one XOR has a cost of 9.
// I'm choosing not to include the NAND gate as an AND followed by an OR because an AND gate is made by inverting the output of a NAND.
// So the NAND is cheaper and it would be stupid to say a NAND has the cost of a NAND and two NOTs.
// ------------------------------------------------
// Moving on, this gives me a cost of 15 for eqout.
// Greater Than
// I did a few versions of this function that were very short but they would always miss ~100 of 56k possibilities.
// So I just made a kmap of the inputs and the carry in bit.
// Since this does not cover the acse of the previous bits being less than, I AND-ed it with the less than in bit to cover that case.
//
// gx0\x1y0y1 000 001 011 010 100 101 111 110
// ----------------------------------
// 00 | 0 | 0 | 0 | 0 || 1 | 0 | 0 | 0 |
// ----------------------------------
// 01 | 1 | 1 | 0 | 0 || 1 | 1 | 0 | 1 |
// ----------------------------------
// 11 | 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 |
// ----------------------------------
// 10 | 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 |
// ----------------------------------
//
// f = g + y0'x' + x1y0'y1' + x0x1y0y1'
//
// Looking at this, it's clear that each input to the OR gate covers one case where x is greater than y.
// I was hoping for a more condensed version of this but oh well.
assign gtout = (gtin | (x0 & ~y0) | (x1 & ~y0 & ~y1) | (x0 & x1 & y0 & ~y1)) & ~ltin;
// COST:
// This function is by far the most expensive because it has the most cases.
// ltout is easy because it's the default case if eqout and gtout are 0.
// ---------------------------------------------
// Just add the inputs and outputs as normal: 29
// Less Than
// This one is the simplest of all purely because the other two
// are done already and the output can only have one 'state'
// So just check if either of the other outputs are true and
// assign lt true if they are not.
// And remember to carry the input
assign ltout = ltin | ~(eqout | gtout);
// COST:
// --------------------------------------------
// Just add the inputs and outputs as normal: 8
// TOTAL COST:
// 52
// As a side note, ltout is a redundant calculation that isn't required to carry through.
// e.g. If there are 3 states and the output is neither of the first two states, then by default is has to be the third state.
// This would mean that each module could cut off 8 cost.
// Since the same check is performed at the output so that 2's compliment numbers can use the same circuitry,
// this has zero drawbacks and is only included because the assignment specifically requested it.
// Another thing to consider is that a 2-to-1 mux is a much cheaper way of implementing an xor gate
// and is more than likely what the FPGA does at compilation. So the actual cost is cut down even more.
endmodule //doublencomparator
|
//
// Testbench for LandingGearController
// Jenner Hanni <[email protected]>
//
// See the attached 'testcases' document for a description of the test cases
//
module TestBench;
reg Clock, Clear, GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever;
wire RedLED, GrnLED, Valve, Pump, Timer;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
parameter CLOCK_CYCLE = 2;
parameter CLOCK_WIDTH = CLOCK_CYCLE/2;
parameter IDLE_CLOCKS = 1;
LandingGearController TFSM(Clock, Clear,
GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever,
RedLED, GrnLED, Valve, Pump, Timer);
//
// set up monitor
//
initial
begin
$display(" Time Clear | Down Up Taxi TimeUp Lever | RedLED GrnLED Valve Pump Timer\n");
$monitor($time, " %b | %b %b %b %b %b | %b %b %b %b %b",Clear, GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever, RedLED, GrnLED, Valve, Pump, Timer);
end
//
// Create free running clock
//
initial
begin
Clock = FALSE;
forever #CLOCK_WIDTH Clock = ~Clock;
end
//
// Generate Clear signal for two cycles
//
initial
begin
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
end
//
// Generate stimulus after waiting for reset
//
initial
begin
// Case #1 - Testing for regular operation
// TAXI-TUP-TDN-TUP-TAXI-TDN-TAXI-TDN-GOUP-FLYUP-GODN-FLYDN-TAXI
$display("\nCase #1\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #2 - Testing for regular operation
// TAXI-TUP-GOUP-FLYUP-GODN-TAXI
$display("\nCase #2\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #3 - Testing for regular operation
// TAXI-TDN-GOUP-FLYUP-GODN-TAXI
$display("\nCase #3\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #4 - Testing for regular operation
// TAXI-TUP-FLYDN-GOUP-FLYUP-GODN-TAXI
$display("\nCase #4\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #5 - Testing for regular operation
// TAXI-TDN-FLYDN-TAXI
$display("\nCase #5\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #6 - Verify TimeUp and Lever are don't cares when transitioning to TAXI
// TAXI-TUP-TAXI
$display("\nCase #6\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10101;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10110;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10111;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #7 - Verify TimeUp and Lever are don't cares when transitioning to TAXI
// TAXI-TDN-TAXI
$display("\nCase #7\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10101;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10110;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10111;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #8 - Verify TimeUp and Lever are don't cares when transitioning to TAXI
// TAXI-TDN-FLYDN-TAXI
$display("\nCase #8\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10101;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10110;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10111;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #9 - Verify TimeUp and Lever are don't cares when transitioning to TAXI
// TAXI-TUP-GOUP-FLYUP-GODN-TAXI
$display("\nCase #9\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10101;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10110;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10111;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #10 - Verify timer is ignored even if accidentally reset during flight until landing
// TAXI-TUP-TUP-GOUP-GOUP-FLYUP-FLYUP-GODN-GODN-TAXI
$display("\nCase #10\n");
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00001;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
Clear = TRUE;
repeat (IDLE_CLOCKS) @(negedge Clock);
Clear = FALSE;
// Case #11 - Verify pilot lever is ignored during gear extension/retraction
// TAXI-TUP-GOUP-GOUP-FLYUP-GODN-GODN-TAXI
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10000;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b01010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00011;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b00010;
repeat (1) @(negedge Clock); {GearIsDown, GearIsUp, PlaneOnGround, TimeUp, Lever} = 5'b10100;
$stop;
end
endmodule
|
module peripheral_crc_7(clk , rst , d_in , cs , addr , rd , wr, d_out );
//entradas y salidas j1
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
//------------------------------------ regs and wires-------------------------------
//registros modulo peripheral
reg [3:0] s; //selector mux_4 and write registers
reg [16:0] data_in=0;
reg start=0;
wire [6:0] data_out;
wire done;
//------------------------------------ regs and wires-------------------------------
always @(*) begin//------address_decoder------------------------------
case (addr)
//se asignan direcciones
//direcciones de escritura
4'h0:begin s = (cs && wr) ? 4'b0001 : 4'b0000 ;end //data_in
4'h2:begin s = (cs && wr) ? 4'b0010 : 4'b0000 ;end //start
//direcciones de lectura
4'h4:begin s = (cs && rd) ? 4'b0100 : 4'b0000 ;end //done
4'h6:begin s = (cs && rd) ? 4'b1000 : 4'b0000 ;end //data_out
default:begin s = 4'b0000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
data_in = (s[0]) ? d_in : data_in; //Write Registers
start = s[1]; //Write Registers
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s[3:2])
2'b01: d_out[0] = done ;
2'b10: d_out[6:0] = data_out ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_4
crc_7 c_7 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) ); // se instancia modulo crc7
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2017/08/13 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] crc;
wire [61:59] ah = crc[5:3];
wire [61:59] bh = ~crc[4:2];
wire [41:2] al = {crc,crc,crc,crc,crc};
wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]};
reg sel;
wire [61:28] q = ( sel
? func(ah, al)
: func(bh, bl));
function [61:28] func;
input [61:59] inh;
input [41:2] inl;
reg [42:28] func_mid;
reg carry;
begin
carry = &inl[27:2];
func_mid = {1'b0,inl[41:28]} + {14'b0, carry};
func[61:59] = inh + {2'b0, func_mid[42]};
func[58:42] = {17{func_mid[41]}};
func[41:28] = func_mid[41:28];
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
//$write("%d %x\n", cyc, q);
if (cyc!=0) begin
cyc <= cyc + 1;
sel <= ~sel;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
sel <= 1'b1;
crc <= 8'h12;
end
if (cyc==2) if (q!=34'h100000484) $stop;
if (cyc==3) if (q!=34'h37fffeddb) $stop;
if (cyc==4) if (q!=34'h080001212) $stop;
if (cyc==5) if (q!=34'h1fffff7ef) $stop;
if (cyc==6) if (q!=34'h200000848) $stop;
if (cyc==7) if (q!=34'h380001ebd) $stop;
if (cyc==8) if (q!=34'h07fffe161) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N (
Q ,
SET ,
RESET ,
CLK_N ,
D ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input SET ;
input RESET ;
input CLK_N ;
input D ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
package t;
class c;
virtual function create (string name="");
return null; // Error: logic returning a null
endfunction
endclass : c
endpackage
module m;
import t::*;
int idx, idx2;
c carr [0:1][0:3];
class c2;
static c sval;
c val;
c arr [0:1];
task check;
if (sval == null) $display("Empty"); // Okay
if (val == null) $display("Empty"); // Okay
if (arr[0] == null) $display("Empty"); // Okay
endtask
endclass
// An implicit logic return type is given a NULL
function tmp();
return null; // Error: logic returning a null
endfunction
c cls;
logic val;
initial begin
idx = 0;
idx2 = 0;
if (cls == null) $display("Empty"); // Okay
if (carr[0][0] == null) $display("Empty"); // Okay
if (carr[idx][idx2] == null) $display("Empty"); // Okay
if (0 == null) $display("Empty"); // Error: logic comp null
val = 1|null; // Error: logic binop null
val = 1<<null; // Error: logic binop null
val = null<<1; // Error: logic binop null
val = null==null; // Okay
val = null<=1; // Error: null binop logic
val = null<=cls; // Error: not supported
val = !null; // Error: unary null
val = null; // Error: null r-value
val <= null; // Error: null r-value
$display("FAILED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
`define SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
|
module top;
parameter pval = -2;
reg pass = 1'b1;
reg [14:-1] big = 16'h0123;
reg [15:0] big_0 = 16'h0123;
reg signed [15:0] idxs [0:1];
reg signed [15:0] a;
reg [4*8:1] res;
initial begin
/* If this fails it is likely because the index width is less
* than an integer width. */
a = -2;
$sformat(res, "%b", big[a+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 1, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
a = 0;
idxs[0] = -1;
$sformat(res, "%b", big_0[idxs[a]+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 2, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
/* This should work since it is a constant value. */
$sformat(res, "%b", big[pval+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 3, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
/* This should always work since it uses the index directly. */
a = -1;
$sformat(res, "%b", big_0[a+:4]);
if (res !== "011x") begin
$display("Failed: &PV<> check 4, expected 4'b011x, got %s.", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [7:0] in;
reg [3:0] out;
initial begin
pass = 1'b1;
in = 8'b10100101;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dx];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dx:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dx];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is X, expected 4'b000x, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dz];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dz:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dz];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is Z, expected 4'b000x, got %b", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2011 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_system_0.v
//
// *Module Description:
// openMSP430 System 1.
// This core is dedicated to computing and can
// only drive two leds on the board.
// It can also read the switches value.
//
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
`include "openmsp430/openMSP430_defines.v"
module omsp_system_1 (
// Clock & Reset
dco_clk, // Fast oscillator (fast clock)
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
// Data Memory
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
dmem_dout, // Data Memory data output
// Program Memory
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
pmem_dout, // Program Memory data output
// Switches & LEDs
switch, // Input switches
led // LEDs
);
// Clock & Reset
input dco_clk; // Fast oscillator (fast clock)
input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
// Data Memory
input [15:0] dmem_dout; // Data Memory data output
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
// Program Memory
input [15:0] pmem_dout; // Program Memory data output
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// LEDs
input [3:0] switch; // Input switches
output [1:0] led; // LEDs
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
// Clock & Reset
wire mclk;
wire aclk_en;
wire smclk_en;
wire puc_rst;
// Debug interface
wire dbg_freeze;
// Data memory
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
// Program memory
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
// Peripheral bus
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire per_en;
wire [15:0] per_dout;
// Interrupts
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire nmi;
// GPIO
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [15:0] per_dout_gpio;
// Timer A
wire [15:0] per_dout_tA;
//=============================================================================
// 2) OPENMSP430 CORE
//=============================================================================
openMSP430 #(.INST_NR (1),
.TOTAL_NR(1)) openMSP430_0 (
// OUTPUTs
.aclk (), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_uart_txd (), // Debug interface: UART TXD
.dco_enable (), // ASIC ONLY: Fast oscillator enable
.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.dma_dout (), // Direct Memory Access data output
.dma_ready (), // Direct Memory Access is complete
.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_bus), // Maskable interrupts
.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
.dma_addr (15'h0000), // Direct Memory Access address
.dma_din (16'h0000), // Direct Memory Access data input
.dma_en (1'b0), // Direct Memory Access enable (high active)
.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (1'b0), // ASIC ONLY: Scan mode
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
//=============================================================================
// 3) OPENMSP430 PERIPHERALS
//=============================================================================
//
// Digital I/O
//-------------------------------
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(0),
.P4_EN(0),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
// OUTPUTs
.irq_port1 (irq_port1), // Port 1 interrupt
.irq_port2 (irq_port2), // Port 2 interrupt
.p1_dout (p1_dout), // Port 1 data output
.p1_dout_en (p1_dout_en), // Port 1 data output enable
.p1_sel (p1_sel), // Port 1 function select
.p2_dout (p2_dout), // Port 2 data output
.p2_dout_en (p2_dout_en), // Port 2 data output enable
.p2_sel (p2_sel), // Port 2 function select
.p3_dout (), // Port 3 data output
.p3_dout_en (), // Port 3 data output enable
.p3_sel (), // Port 3 function select
.p4_dout (), // Port 4 data output
.p4_dout_en (), // Port 4 data output enable
.p4_sel (), // Port 4 function select
.p5_dout (), // Port 5 data output
.p5_dout_en (), // Port 5 data output enable
.p5_sel (), // Port 5 function select
.p6_dout (), // Port 6 data output
.p6_dout_en (), // Port 6 data output enable
.p6_sel (), // Port 6 function select
.per_dout (per_dout_gpio), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.p1_din (p1_din), // Port 1 data input
.p2_din (p2_din), // Port 2 data input
.p3_din (8'h00), // Port 3 data input
.p4_din (8'h00), // Port 4 data input
.p5_din (8'h00), // Port 5 data input
.p6_din (8'h00), // Port 6 data input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
// Assign LEDs
assign led = p2_dout[1:0] & p2_dout_en[1:0];
// Assign Switches
assign p1_din[7:4] = 4'h0;
assign p1_din[3:0] = switch;
//
// Timer A
//----------------------------------------------
omsp_timerA timerA_0 (
// OUTPUTs
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
.per_dout (per_dout_tA), // Peripheral data output
.ta_out0 (), // Timer A output 0
.ta_out0_en (), // Timer A output 0 enable
.ta_out1 (), // Timer A output 1
.ta_out1_en (), // Timer A output 1 enable
.ta_out2 (), // Timer A output 2
.ta_out2_en (), // Timer A output 2 enable
// INPUTs
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (1'b0), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (1'b0), // Timer A capture 0 input A
.ta_cci0b (1'b0), // Timer A capture 0 input B
.ta_cci1a (1'b0), // Timer A capture 1 input A
.ta_cci1b (1'b0), // Timer A capture 1 input B
.ta_cci2a (1'b0), // Timer A capture 2 input A
.ta_cci2b (1'b0), // Timer A capture 2 input B
.taclk (1'b0) // TACLK external timer clock (SLOW)
);
//
// Combine peripheral data buses
//-------------------------------
assign per_dout = per_dout_gpio |
per_dout_tA;
//
// Assign interrupts
//-------------------------------
assign nmi = 1'b0;
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
1'b0, // Vector 9 (0xFFF2) - Reserved (Timer-A 0 from system 0)
1'b0, // Vector 8 (0xFFF0) - Reserved (Timer-A 1 from system 0)
1'b0, // Vector 7 (0xFFEE) - Reserved (UART RX from system 0)
1'b0, // Vector 6 (0xFFEC) - Reserved (UART TX from system 0)
irq_ta0, // Vector 5 (0xFFEA)
irq_ta1, // Vector 4 (0xFFE8)
1'b0, // Vector 3 (0xFFE6) - Reserved (Port 2 from system 0)
1'b0, // Vector 2 (0xFFE4) - Reserved (Port 1 from system 0)
irq_port2, // Vector 1 (0xFFE2)
irq_port1}; // Vector 0 (0xFFE0)
endmodule // omsp_system_1
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
// surefire lint_off STMINI
// surefire lint_off CSEBEQ
input clk;
reg [7:0] a_to_clk_levm3;
reg [7:0] b_to_clk_levm1;
reg [7:0] c_com_levs10;
reg [7:0] d_to_clk_levm2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v
wire [7:0] n_from_clk_lev2; // From a of t_order_a.v
wire [7:0] o_from_com_levs11; // From a of t_order_a.v
wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v
wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
// End of automatics
reg [7:0] cyc; initial cyc=0;
t_order_a a (
.one (8'h1),
/*AUTOINST*/
// Outputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]),
.n_from_clk_lev2 (n_from_clk_lev2[7:0]),
.o_from_com_levs11 (o_from_com_levs11[7:0]),
.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
// Inputs
.clk (clk),
.a_to_clk_levm3 (a_to_clk_levm3[7:0]),
.b_to_clk_levm1 (b_to_clk_levm1[7:0]),
.c_com_levs10 (c_com_levs10[7:0]),
.d_to_clk_levm2 (d_to_clk_levm2[7:0]));
t_order_b b (
/*AUTOINST*/
// Outputs
.o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]),
// Inputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]));
reg [7:0] o_from_com_levs12;
reg [7:0] o_from_com_levs13;
always @ (/*AS*/o_from_com_levs11) begin
o_from_com_levs12 = o_from_com_levs11 + 8'h1;
o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize
o_from_com_levs13 = o_from_com_levs12;
end
reg sepassign_in;
// verilator lint_off UNOPTFLAT
wire [3:0] sepassign;
// verilator lint_on UNOPTFLAT
// verilator lint_off UNOPT
assign #0.1 sepassign[0] = 0,
sepassign[1] = sepassign[2],
sepassign[2] = sepassign[3],
sepassign[3] = sepassign_in;
wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
// verilator lint_on UNOPT
always @ (posedge clk) begin
cyc <= cyc+8'd1;
sepassign_in <= 0;
if (cyc == 8'd1) begin
a_to_clk_levm3 <= 0;
d_to_clk_levm2 <= 1;
b_to_clk_levm1 <= 1;
c_com_levs10 <= 2;
sepassign_in <= 1;
end
if (cyc == 8'd2) begin
if (sepassign !== 4'b1110) $stop;
end
if (cyc == 8'd3) begin
$display("%d %d %d %d",m_from_clk_lev1_r,
n_from_clk_lev2,
o_from_com_levs11,
o_from_comandclk_levs12);
if (m_from_clk_lev1_r !== 8'h2) $stop;
if (o_subfrom_clk_lev3 !== 8'h2) $stop;
if (n_from_clk_lev2 !== 8'h2) $stop;
if (o_from_com_levs11 !== 8'h3) $stop;
if (o_from_com_levs13 !== 8'h5) $stop;
if (o_from_comandclk_levs12 !== 8'h5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=6,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [31 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [31 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [3 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [5 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(6),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Down-Sizer
// Down-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data, Write Response and Read Data Down-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Down-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_axi4lite_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [64-1:0] s_axi_wdata,
input wire [64/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [64-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [32-1:0] m_axi_wdata,
output wire [32/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [32-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg s_axi_rvalid_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg split_ar ;
reg split_r ;
reg ar_start ;
reg aw_start ;
reg ar_done ;
reg [31:0] rdata_low ;
reg [1:0] rresp_low ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg split_aw ;
reg split_w ;
reg high_aw ;
reg aw_done ;
reg w_done ;
reg [1:0] bresp_low ;
wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
m_axi_rready_i <= 1'b0 ;
split_ar <= 1'b0 ;
split_r <= 1'b0 ;
ar_start <= 1'b0 ;
ar_done <= 1'b0 ;
rdata_low <= 32'b0 ;
rresp_low <= 2'b0 ;
end else begin
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
split_ar <= 1'b0;
split_r <= 1'b0;
ar_start <= 1'b0;
end
end else if (s_axi_arready_i) begin
s_axi_arready_i <= 1'b0; // end single-cycle pulse
s_axi_rvalid_i <= 1'b1;
end else if (ar_done) begin
if (m_axi_rvalid) begin
ar_done <= 1'b0;
if (split_ar & ~split_r) begin
split_r <= 1'b1;
rdata_low <= m_axi_rdata;
rresp_low <= m_axi_rresp;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
m_axi_arvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1; // begin single-cycle pulse
end
end
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ((C_AXI_SUPPORTS_WRITE==0) | (~aw_start))) begin
m_axi_arvalid_i <= 1'b1;
split_ar <= ~s_axi_araddr[2];
ar_start <= 1'b1;
end
end
end
assign s_axi_arready = s_axi_arready_i ;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign m_axi_araddr = m_axaddr;
assign s_axi_rresp = split_r ? ({m_axi_rresp[1], &m_axi_rresp} | {rresp_low[1], &rresp_low}) : m_axi_rresp;
assign s_axi_rdata = split_r ? {m_axi_rdata,rdata_low} : {m_axi_rdata,m_axi_rdata};
assign m_axi_arprot = s_axi_arprot;
end else begin : gen_noread
assign s_axi_arready = 1'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_arvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 64'b0 ;
assign m_axi_arprot = 3'b0 ;
always @ * begin
ar_start = 1'b0;
split_r = 1'b0;
end
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_awready_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_awvalid_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
split_aw <= 1'b0 ;
split_w <= 1'b0 ;
high_aw <= 1'b0 ;
aw_start <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
bresp_low <= 2'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
split_aw <= 1'b0;
split_w <= 1'b0;
high_aw <= 1'b0;
aw_start <= 1'b0 ;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
aw_done <= 1'b0;
w_done <= 1'b0;
if (split_aw & ~split_w) begin
split_w <= 1'b1;
bresp_low <= m_axi_bresp;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
m_axi_awvalid_i <= 1'b1;
m_axi_wvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end
end else begin
if (m_axi_awvalid_i | m_axi_wvalid_i) begin
if (m_axi_awvalid_i & m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
if (m_axi_wvalid_i & m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_awvalid & s_axi_wvalid & ~aw_done & ~w_done & ((C_AXI_SUPPORTS_READ==0) | (~ar_start & ~s_axi_arvalid))) begin
m_axi_awvalid_i <= 1'b1;
m_axi_wvalid_i <= 1'b1;
aw_start <= 1'b1 ;
split_aw <= ~s_axi_awaddr[2] & (|s_axi_wstrb[7:4]) & (|s_axi_wstrb[3:0]);
high_aw <= ~s_axi_awaddr[2] & (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0]);
end
end
end
end
assign s_axi_awready = s_axi_awready_i ;
assign s_axi_wready = s_axi_awready_i ;
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign m_axi_awaddr = m_axaddr;
assign s_axi_bresp = split_w ? ({m_axi_bresp[1], &m_axi_bresp} | {bresp_low[1], &bresp_low}) : m_axi_bresp;
assign m_axi_wdata = (split_w | s_axi_awaddr[2] | (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0])) ? s_axi_wdata[63:32] : s_axi_wdata[31:0];
assign m_axi_wstrb = (split_w | s_axi_awaddr[2] | (|s_axi_wstrb[7:4]) & ~(|s_axi_wstrb[3:0])) ? s_axi_wstrb[7:4] : s_axi_wstrb[3:0];
assign m_axi_awprot = s_axi_awprot;
end else begin : gen_nowrite
assign s_axi_awready = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_awvalid = 1'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign s_axi_bresp = 2'b0 ;
assign m_axi_wdata = 32'b0 ;
assign m_axi_wstrb = 4'b0 ;
assign m_axi_awprot = 3'b0 ;
always @ * begin
aw_start = 1'b0;
split_w = 1'b0;
end
end
if (C_AXI_SUPPORTS_WRITE == 0) begin : gen_ro_addr
assign m_axaddr = split_r ? ({s_axi_araddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axi_araddr;
end else if (C_AXI_SUPPORTS_READ == 0) begin : gen_wo_addr
assign m_axaddr = (split_w | high_aw) ? ({s_axi_awaddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axi_awaddr;
end else begin : gen_rw_addr
assign s_axaddr = ar_start ? s_axi_araddr : s_axi_awaddr;
assign m_axaddr = (split_w | split_r | high_aw) ? ({s_axaddr[C_AXI_ADDR_WIDTH-1:2], 2'b00} | 3'b100) : s_axaddr;
end
endgenerate
endmodule
|
// soc_design.v
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design (
output wire [12:0] dram_addr, // dram.addr
output wire [1:0] dram_ba, // .ba
output wire dram_cas_n, // .cas_n
output wire dram_cke, // .cke
output wire dram_cs_n, // .cs_n
inout wire [15:0] dram_dq, // .dq
output wire [1:0] dram_dqm, // .dqm
output wire dram_ras_n, // .ras_n
output wire dram_we_n, // .we_n
output wire dram_clk_clk, // dram_clk.clk
input wire fpga_reset_n, // fpga.reset_n
output wire ledr0_ledr, // ledr0.ledr
input wire ref_clk, // ref.clk
input wire uart_RXD, // uart.RXD
output wire uart_TXD // .TXD
);
wire system_pll_outclk0_clk; // system_pll:outclk_0 -> [JTAG:clk, SDRAM:clk, SRAM:clk, Sys_Timer:clk, SystemID:clock, Test_PipeLine:clock_clk, UART_COM:clk, convolution_slave:clock_clk, irq_mapper:clk, mm_interconnect_0:system_pll_outclk0_clk, niosII_core:clk, rst_controller:clk]
wire test_pipeline_avm_m0_waitrequest; // mm_interconnect_0:Test_PipeLine_avm_m0_waitrequest -> Test_PipeLine:avm_m0_waitrequest
wire [31:0] test_pipeline_avm_m0_readdata; // mm_interconnect_0:Test_PipeLine_avm_m0_readdata -> Test_PipeLine:avm_m0_readdata
wire [31:0] test_pipeline_avm_m0_address; // Test_PipeLine:avm_m0_address -> mm_interconnect_0:Test_PipeLine_avm_m0_address
wire test_pipeline_avm_m0_read; // Test_PipeLine:avm_m0_read -> mm_interconnect_0:Test_PipeLine_avm_m0_read
wire test_pipeline_avm_m0_readdatavalid; // mm_interconnect_0:Test_PipeLine_avm_m0_readdatavalid -> Test_PipeLine:avm_m0_readdatavalid
wire test_pipeline_avm_m0_write; // Test_PipeLine:avm_m0_write -> mm_interconnect_0:Test_PipeLine_avm_m0_write
wire [31:0] test_pipeline_avm_m0_writedata; // Test_PipeLine:avm_m0_writedata -> mm_interconnect_0:Test_PipeLine_avm_m0_writedata
wire [7:0] test_pipeline_avm_m0_burstcount; // Test_PipeLine:avm_m0_burstcount -> mm_interconnect_0:Test_PipeLine_avm_m0_burstcount
wire [31:0] niosii_core_data_master_readdata; // mm_interconnect_0:niosII_core_data_master_readdata -> niosII_core:d_readdata
wire niosii_core_data_master_waitrequest; // mm_interconnect_0:niosII_core_data_master_waitrequest -> niosII_core:d_waitrequest
wire niosii_core_data_master_debugaccess; // niosII_core:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:niosII_core_data_master_debugaccess
wire [26:0] niosii_core_data_master_address; // niosII_core:d_address -> mm_interconnect_0:niosII_core_data_master_address
wire [3:0] niosii_core_data_master_byteenable; // niosII_core:d_byteenable -> mm_interconnect_0:niosII_core_data_master_byteenable
wire niosii_core_data_master_read; // niosII_core:d_read -> mm_interconnect_0:niosII_core_data_master_read
wire niosii_core_data_master_readdatavalid; // mm_interconnect_0:niosII_core_data_master_readdatavalid -> niosII_core:d_readdatavalid
wire niosii_core_data_master_write; // niosII_core:d_write -> mm_interconnect_0:niosII_core_data_master_write
wire [31:0] niosii_core_data_master_writedata; // niosII_core:d_writedata -> mm_interconnect_0:niosII_core_data_master_writedata
wire [3:0] niosii_core_data_master_burstcount; // niosII_core:d_burstcount -> mm_interconnect_0:niosII_core_data_master_burstcount
wire [31:0] niosii_core_instruction_master_readdata; // mm_interconnect_0:niosII_core_instruction_master_readdata -> niosII_core:i_readdata
wire niosii_core_instruction_master_waitrequest; // mm_interconnect_0:niosII_core_instruction_master_waitrequest -> niosII_core:i_waitrequest
wire [26:0] niosii_core_instruction_master_address; // niosII_core:i_address -> mm_interconnect_0:niosII_core_instruction_master_address
wire niosii_core_instruction_master_read; // niosII_core:i_read -> mm_interconnect_0:niosII_core_instruction_master_read
wire niosii_core_instruction_master_readdatavalid; // mm_interconnect_0:niosII_core_instruction_master_readdatavalid -> niosII_core:i_readdatavalid
wire [3:0] niosii_core_instruction_master_burstcount; // niosII_core:i_burstcount -> mm_interconnect_0:niosII_core_instruction_master_burstcount
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:SDRAM_s1_chipselect -> SDRAM:az_cs
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // SDRAM:za_data -> mm_interconnect_0:SDRAM_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // SDRAM:za_waitrequest -> mm_interconnect_0:SDRAM_s1_waitrequest
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:SDRAM_s1_address -> SDRAM:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:SDRAM_s1_read -> SDRAM:az_rd_n
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:SDRAM_s1_byteenable -> SDRAM:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // SDRAM:za_valid -> mm_interconnect_0:SDRAM_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:SDRAM_s1_write -> SDRAM:az_wr_n
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:SDRAM_s1_writedata -> SDRAM:az_data
wire [31:0] mm_interconnect_0_niosii_core_debug_mem_slave_readdata; // niosII_core:debug_mem_slave_readdata -> mm_interconnect_0:niosII_core_debug_mem_slave_readdata
wire mm_interconnect_0_niosii_core_debug_mem_slave_waitrequest; // niosII_core:debug_mem_slave_waitrequest -> mm_interconnect_0:niosII_core_debug_mem_slave_waitrequest
wire mm_interconnect_0_niosii_core_debug_mem_slave_debugaccess; // mm_interconnect_0:niosII_core_debug_mem_slave_debugaccess -> niosII_core:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_niosii_core_debug_mem_slave_address; // mm_interconnect_0:niosII_core_debug_mem_slave_address -> niosII_core:debug_mem_slave_address
wire mm_interconnect_0_niosii_core_debug_mem_slave_read; // mm_interconnect_0:niosII_core_debug_mem_slave_read -> niosII_core:debug_mem_slave_read
wire [3:0] mm_interconnect_0_niosii_core_debug_mem_slave_byteenable; // mm_interconnect_0:niosII_core_debug_mem_slave_byteenable -> niosII_core:debug_mem_slave_byteenable
wire mm_interconnect_0_niosii_core_debug_mem_slave_write; // mm_interconnect_0:niosII_core_debug_mem_slave_write -> niosII_core:debug_mem_slave_write
wire [31:0] mm_interconnect_0_niosii_core_debug_mem_slave_writedata; // mm_interconnect_0:niosII_core_debug_mem_slave_writedata -> niosII_core:debug_mem_slave_writedata
wire mm_interconnect_0_sram_s1_chipselect; // mm_interconnect_0:SRAM_s1_chipselect -> SRAM:chipselect
wire [31:0] mm_interconnect_0_sram_s1_readdata; // SRAM:readdata -> mm_interconnect_0:SRAM_s1_readdata
wire [14:0] mm_interconnect_0_sram_s1_address; // mm_interconnect_0:SRAM_s1_address -> SRAM:address
wire [3:0] mm_interconnect_0_sram_s1_byteenable; // mm_interconnect_0:SRAM_s1_byteenable -> SRAM:byteenable
wire mm_interconnect_0_sram_s1_write; // mm_interconnect_0:SRAM_s1_write -> SRAM:write
wire [31:0] mm_interconnect_0_sram_s1_writedata; // mm_interconnect_0:SRAM_s1_writedata -> SRAM:writedata
wire mm_interconnect_0_sram_s1_clken; // mm_interconnect_0:SRAM_s1_clken -> SRAM:clken
wire mm_interconnect_0_jtag_avalon_jtag_slave_chipselect; // mm_interconnect_0:JTAG_avalon_jtag_slave_chipselect -> JTAG:av_chipselect
wire [31:0] mm_interconnect_0_jtag_avalon_jtag_slave_readdata; // JTAG:av_readdata -> mm_interconnect_0:JTAG_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest; // JTAG:av_waitrequest -> mm_interconnect_0:JTAG_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_avalon_jtag_slave_address; // mm_interconnect_0:JTAG_avalon_jtag_slave_address -> JTAG:av_address
wire mm_interconnect_0_jtag_avalon_jtag_slave_read; // mm_interconnect_0:JTAG_avalon_jtag_slave_read -> JTAG:av_read_n
wire mm_interconnect_0_jtag_avalon_jtag_slave_write; // mm_interconnect_0:JTAG_avalon_jtag_slave_write -> JTAG:av_write_n
wire [31:0] mm_interconnect_0_jtag_avalon_jtag_slave_writedata; // mm_interconnect_0:JTAG_avalon_jtag_slave_writedata -> JTAG:av_writedata
wire mm_interconnect_0_uart_com_avalon_rs232_slave_chipselect; // mm_interconnect_0:UART_COM_avalon_rs232_slave_chipselect -> UART_COM:chipselect
wire [31:0] mm_interconnect_0_uart_com_avalon_rs232_slave_readdata; // UART_COM:readdata -> mm_interconnect_0:UART_COM_avalon_rs232_slave_readdata
wire [0:0] mm_interconnect_0_uart_com_avalon_rs232_slave_address; // mm_interconnect_0:UART_COM_avalon_rs232_slave_address -> UART_COM:address
wire mm_interconnect_0_uart_com_avalon_rs232_slave_read; // mm_interconnect_0:UART_COM_avalon_rs232_slave_read -> UART_COM:read
wire [3:0] mm_interconnect_0_uart_com_avalon_rs232_slave_byteenable; // mm_interconnect_0:UART_COM_avalon_rs232_slave_byteenable -> UART_COM:byteenable
wire mm_interconnect_0_uart_com_avalon_rs232_slave_write; // mm_interconnect_0:UART_COM_avalon_rs232_slave_write -> UART_COM:write
wire [31:0] mm_interconnect_0_uart_com_avalon_rs232_slave_writedata; // mm_interconnect_0:UART_COM_avalon_rs232_slave_writedata -> UART_COM:writedata
wire [31:0] mm_interconnect_0_convolution_slave_avs_s0_readdata; // convolution_slave:avs_s0_readdata -> mm_interconnect_0:convolution_slave_avs_s0_readdata
wire mm_interconnect_0_convolution_slave_avs_s0_waitrequest; // convolution_slave:avs_s0_waitrequest -> mm_interconnect_0:convolution_slave_avs_s0_waitrequest
wire [8:0] mm_interconnect_0_convolution_slave_avs_s0_address; // mm_interconnect_0:convolution_slave_avs_s0_address -> convolution_slave:avs_s0_address
wire mm_interconnect_0_convolution_slave_avs_s0_read; // mm_interconnect_0:convolution_slave_avs_s0_read -> convolution_slave:avs_s0_read
wire mm_interconnect_0_convolution_slave_avs_s0_write; // mm_interconnect_0:convolution_slave_avs_s0_write -> convolution_slave:avs_s0_write
wire [31:0] mm_interconnect_0_convolution_slave_avs_s0_writedata; // mm_interconnect_0:convolution_slave_avs_s0_writedata -> convolution_slave:avs_s0_writedata
wire [31:0] mm_interconnect_0_test_pipeline_avs_s0_readdata; // Test_PipeLine:avs_s0_readdata -> mm_interconnect_0:Test_PipeLine_avs_s0_readdata
wire mm_interconnect_0_test_pipeline_avs_s0_waitrequest; // Test_PipeLine:avs_s0_waitrequest -> mm_interconnect_0:Test_PipeLine_avs_s0_waitrequest
wire [7:0] mm_interconnect_0_test_pipeline_avs_s0_address; // mm_interconnect_0:Test_PipeLine_avs_s0_address -> Test_PipeLine:avs_s0_address
wire mm_interconnect_0_test_pipeline_avs_s0_read; // mm_interconnect_0:Test_PipeLine_avs_s0_read -> Test_PipeLine:avs_s0_read
wire mm_interconnect_0_test_pipeline_avs_s0_write; // mm_interconnect_0:Test_PipeLine_avs_s0_write -> Test_PipeLine:avs_s0_write
wire [31:0] mm_interconnect_0_test_pipeline_avs_s0_writedata; // mm_interconnect_0:Test_PipeLine_avs_s0_writedata -> Test_PipeLine:avs_s0_writedata
wire [31:0] mm_interconnect_0_systemid_control_slave_readdata; // SystemID:readdata -> mm_interconnect_0:SystemID_control_slave_readdata
wire [0:0] mm_interconnect_0_systemid_control_slave_address; // mm_interconnect_0:SystemID_control_slave_address -> SystemID:address
wire mm_interconnect_0_sys_timer_s1_chipselect; // mm_interconnect_0:Sys_Timer_s1_chipselect -> Sys_Timer:chipselect
wire [15:0] mm_interconnect_0_sys_timer_s1_readdata; // Sys_Timer:readdata -> mm_interconnect_0:Sys_Timer_s1_readdata
wire [2:0] mm_interconnect_0_sys_timer_s1_address; // mm_interconnect_0:Sys_Timer_s1_address -> Sys_Timer:address
wire mm_interconnect_0_sys_timer_s1_write; // mm_interconnect_0:Sys_Timer_s1_write -> Sys_Timer:write_n
wire [15:0] mm_interconnect_0_sys_timer_s1_writedata; // mm_interconnect_0:Sys_Timer_s1_writedata -> Sys_Timer:writedata
wire irq_mapper_receiver0_irq; // UART_COM:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // JTAG:av_irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // Sys_Timer:irq -> irq_mapper:receiver2_irq
wire [31:0] niosii_core_irq_irq; // irq_mapper:sender_irq -> niosII_core:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [JTAG:rst_n, SDRAM:reset_n, SRAM:reset, Sys_Timer:reset_n, SystemID:reset_n, Test_PipeLine:reset_reset, UART_COM:reset, convolution_slave:reset_reset, irq_mapper:reset, mm_interconnect_0:Test_PipeLine_reset_reset_bridge_in_reset_reset, niosII_core:reset_n, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [SRAM:reset_req, niosII_core:reset_req, rst_translator:reset_req_in]
soc_design_JTAG jtag (
.clk (system_pll_outclk0_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
soc_design_SDRAM sdram (
.clk (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (dram_addr), // wire.export
.zs_ba (dram_ba), // .export
.zs_cas_n (dram_cas_n), // .export
.zs_cke (dram_cke), // .export
.zs_cs_n (dram_cs_n), // .export
.zs_dq (dram_dq), // .export
.zs_dqm (dram_dqm), // .export
.zs_ras_n (dram_ras_n), // .export
.zs_we_n (dram_we_n) // .export
);
soc_design_SRAM sram (
.clk (system_pll_outclk0_clk), // clk1.clk
.address (mm_interconnect_0_sram_s1_address), // s1.address
.clken (mm_interconnect_0_sram_s1_clken), // .clken
.chipselect (mm_interconnect_0_sram_s1_chipselect), // .chipselect
.write (mm_interconnect_0_sram_s1_write), // .write
.readdata (mm_interconnect_0_sram_s1_readdata), // .readdata
.writedata (mm_interconnect_0_sram_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_sram_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_design_Sys_Timer sys_timer (
.clk (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sys_timer_s1_address), // s1.address
.writedata (mm_interconnect_0_sys_timer_s1_writedata), // .writedata
.readdata (mm_interconnect_0_sys_timer_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_sys_timer_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_sys_timer_s1_write), // .write_n
.irq (irq_mapper_receiver2_irq) // irq.irq
);
soc_design_SystemID systemid (
.clock (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_systemid_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_systemid_control_slave_address) // .address
);
chris_pipelined test_pipeline (
.avs_s0_address (mm_interconnect_0_test_pipeline_avs_s0_address), // avs_s0.address
.avs_s0_read (mm_interconnect_0_test_pipeline_avs_s0_read), // .read
.avs_s0_readdata (mm_interconnect_0_test_pipeline_avs_s0_readdata), // .readdata
.avs_s0_write (mm_interconnect_0_test_pipeline_avs_s0_write), // .write
.avs_s0_writedata (mm_interconnect_0_test_pipeline_avs_s0_writedata), // .writedata
.avs_s0_waitrequest (mm_interconnect_0_test_pipeline_avs_s0_waitrequest), // .waitrequest
.clock_clk (system_pll_outclk0_clk), // clock.clk
.reset_reset (rst_controller_reset_out_reset), // reset.reset
.avm_m0_address (test_pipeline_avm_m0_address), // avm_m0.address
.avm_m0_read (test_pipeline_avm_m0_read), // .read
.avm_m0_waitrequest (test_pipeline_avm_m0_waitrequest), // .waitrequest
.avm_m0_readdata (test_pipeline_avm_m0_readdata), // .readdata
.avm_m0_readdatavalid (test_pipeline_avm_m0_readdatavalid), // .readdatavalid
.avm_m0_write (test_pipeline_avm_m0_write), // .write
.avm_m0_writedata (test_pipeline_avm_m0_writedata), // .writedata
.avm_m0_burstcount (test_pipeline_avm_m0_burstcount) // .burstcount
);
soc_design_UART_COM uart_com (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.address (mm_interconnect_0_uart_com_avalon_rs232_slave_address), // avalon_rs232_slave.address
.chipselect (mm_interconnect_0_uart_com_avalon_rs232_slave_chipselect), // .chipselect
.byteenable (mm_interconnect_0_uart_com_avalon_rs232_slave_byteenable), // .byteenable
.read (mm_interconnect_0_uart_com_avalon_rs232_slave_read), // .read
.write (mm_interconnect_0_uart_com_avalon_rs232_slave_write), // .write
.writedata (mm_interconnect_0_uart_com_avalon_rs232_slave_writedata), // .writedata
.readdata (mm_interconnect_0_uart_com_avalon_rs232_slave_readdata), // .readdata
.irq (irq_mapper_receiver0_irq), // interrupt.irq
.UART_RXD (uart_RXD), // external_interface.export
.UART_TXD (uart_TXD) // .export
);
chris_slave convolution_slave (
.avs_s0_address (mm_interconnect_0_convolution_slave_avs_s0_address), // avs_s0.address
.avs_s0_read (mm_interconnect_0_convolution_slave_avs_s0_read), // .read
.avs_s0_readdata (mm_interconnect_0_convolution_slave_avs_s0_readdata), // .readdata
.avs_s0_write (mm_interconnect_0_convolution_slave_avs_s0_write), // .write
.avs_s0_writedata (mm_interconnect_0_convolution_slave_avs_s0_writedata), // .writedata
.avs_s0_waitrequest (mm_interconnect_0_convolution_slave_avs_s0_waitrequest), // .waitrequest
.clock_clk (system_pll_outclk0_clk), // clock.clk
.reset_reset (rst_controller_reset_out_reset), // reset.reset
.LEDR (ledr0_ledr) // LEDR.ledr
);
soc_design_niosII_core niosii_core (
.clk (system_pll_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (niosii_core_data_master_address), // data_master.address
.d_byteenable (niosii_core_data_master_byteenable), // .byteenable
.d_read (niosii_core_data_master_read), // .read
.d_readdata (niosii_core_data_master_readdata), // .readdata
.d_waitrequest (niosii_core_data_master_waitrequest), // .waitrequest
.d_write (niosii_core_data_master_write), // .write
.d_writedata (niosii_core_data_master_writedata), // .writedata
.d_burstcount (niosii_core_data_master_burstcount), // .burstcount
.d_readdatavalid (niosii_core_data_master_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (niosii_core_data_master_debugaccess), // .debugaccess
.i_address (niosii_core_instruction_master_address), // instruction_master.address
.i_read (niosii_core_instruction_master_read), // .read
.i_readdata (niosii_core_instruction_master_readdata), // .readdata
.i_waitrequest (niosii_core_instruction_master_waitrequest), // .waitrequest
.i_burstcount (niosii_core_instruction_master_burstcount), // .burstcount
.i_readdatavalid (niosii_core_instruction_master_readdatavalid), // .readdatavalid
.irq (niosii_core_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_niosii_core_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_niosii_core_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_niosii_core_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_niosii_core_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_niosii_core_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_niosii_core_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_niosii_core_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_niosii_core_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
soc_design_system_pll system_pll (
.refclk (ref_clk), // refclk.clk
.rst (~fpga_reset_n), // reset.reset
.outclk_0 (system_pll_outclk0_clk), // outclk0.clk
.outclk_1 (dram_clk_clk), // outclk1.clk
.locked () // (terminated)
);
soc_design_mm_interconnect_0 mm_interconnect_0 (
.system_pll_outclk0_clk (system_pll_outclk0_clk), // system_pll_outclk0.clk
.Test_PipeLine_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Test_PipeLine_reset_reset_bridge_in_reset.reset
.niosII_core_data_master_address (niosii_core_data_master_address), // niosII_core_data_master.address
.niosII_core_data_master_waitrequest (niosii_core_data_master_waitrequest), // .waitrequest
.niosII_core_data_master_burstcount (niosii_core_data_master_burstcount), // .burstcount
.niosII_core_data_master_byteenable (niosii_core_data_master_byteenable), // .byteenable
.niosII_core_data_master_read (niosii_core_data_master_read), // .read
.niosII_core_data_master_readdata (niosii_core_data_master_readdata), // .readdata
.niosII_core_data_master_readdatavalid (niosii_core_data_master_readdatavalid), // .readdatavalid
.niosII_core_data_master_write (niosii_core_data_master_write), // .write
.niosII_core_data_master_writedata (niosii_core_data_master_writedata), // .writedata
.niosII_core_data_master_debugaccess (niosii_core_data_master_debugaccess), // .debugaccess
.niosII_core_instruction_master_address (niosii_core_instruction_master_address), // niosII_core_instruction_master.address
.niosII_core_instruction_master_waitrequest (niosii_core_instruction_master_waitrequest), // .waitrequest
.niosII_core_instruction_master_burstcount (niosii_core_instruction_master_burstcount), // .burstcount
.niosII_core_instruction_master_read (niosii_core_instruction_master_read), // .read
.niosII_core_instruction_master_readdata (niosii_core_instruction_master_readdata), // .readdata
.niosII_core_instruction_master_readdatavalid (niosii_core_instruction_master_readdatavalid), // .readdatavalid
.Test_PipeLine_avm_m0_address (test_pipeline_avm_m0_address), // Test_PipeLine_avm_m0.address
.Test_PipeLine_avm_m0_waitrequest (test_pipeline_avm_m0_waitrequest), // .waitrequest
.Test_PipeLine_avm_m0_burstcount (test_pipeline_avm_m0_burstcount), // .burstcount
.Test_PipeLine_avm_m0_read (test_pipeline_avm_m0_read), // .read
.Test_PipeLine_avm_m0_readdata (test_pipeline_avm_m0_readdata), // .readdata
.Test_PipeLine_avm_m0_readdatavalid (test_pipeline_avm_m0_readdatavalid), // .readdatavalid
.Test_PipeLine_avm_m0_write (test_pipeline_avm_m0_write), // .write
.Test_PipeLine_avm_m0_writedata (test_pipeline_avm_m0_writedata), // .writedata
.convolution_slave_avs_s0_address (mm_interconnect_0_convolution_slave_avs_s0_address), // convolution_slave_avs_s0.address
.convolution_slave_avs_s0_write (mm_interconnect_0_convolution_slave_avs_s0_write), // .write
.convolution_slave_avs_s0_read (mm_interconnect_0_convolution_slave_avs_s0_read), // .read
.convolution_slave_avs_s0_readdata (mm_interconnect_0_convolution_slave_avs_s0_readdata), // .readdata
.convolution_slave_avs_s0_writedata (mm_interconnect_0_convolution_slave_avs_s0_writedata), // .writedata
.convolution_slave_avs_s0_waitrequest (mm_interconnect_0_convolution_slave_avs_s0_waitrequest), // .waitrequest
.JTAG_avalon_jtag_slave_address (mm_interconnect_0_jtag_avalon_jtag_slave_address), // JTAG_avalon_jtag_slave.address
.JTAG_avalon_jtag_slave_write (mm_interconnect_0_jtag_avalon_jtag_slave_write), // .write
.JTAG_avalon_jtag_slave_read (mm_interconnect_0_jtag_avalon_jtag_slave_read), // .read
.JTAG_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_avalon_jtag_slave_readdata), // .readdata
.JTAG_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_avalon_jtag_slave_writedata), // .writedata
.JTAG_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.JTAG_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_avalon_jtag_slave_chipselect), // .chipselect
.niosII_core_debug_mem_slave_address (mm_interconnect_0_niosii_core_debug_mem_slave_address), // niosII_core_debug_mem_slave.address
.niosII_core_debug_mem_slave_write (mm_interconnect_0_niosii_core_debug_mem_slave_write), // .write
.niosII_core_debug_mem_slave_read (mm_interconnect_0_niosii_core_debug_mem_slave_read), // .read
.niosII_core_debug_mem_slave_readdata (mm_interconnect_0_niosii_core_debug_mem_slave_readdata), // .readdata
.niosII_core_debug_mem_slave_writedata (mm_interconnect_0_niosii_core_debug_mem_slave_writedata), // .writedata
.niosII_core_debug_mem_slave_byteenable (mm_interconnect_0_niosii_core_debug_mem_slave_byteenable), // .byteenable
.niosII_core_debug_mem_slave_waitrequest (mm_interconnect_0_niosii_core_debug_mem_slave_waitrequest), // .waitrequest
.niosII_core_debug_mem_slave_debugaccess (mm_interconnect_0_niosii_core_debug_mem_slave_debugaccess), // .debugaccess
.SDRAM_s1_address (mm_interconnect_0_sdram_s1_address), // SDRAM_s1.address
.SDRAM_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.SDRAM_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.SDRAM_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.SDRAM_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.SDRAM_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.SDRAM_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.SDRAM_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.SDRAM_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.SRAM_s1_address (mm_interconnect_0_sram_s1_address), // SRAM_s1.address
.SRAM_s1_write (mm_interconnect_0_sram_s1_write), // .write
.SRAM_s1_readdata (mm_interconnect_0_sram_s1_readdata), // .readdata
.SRAM_s1_writedata (mm_interconnect_0_sram_s1_writedata), // .writedata
.SRAM_s1_byteenable (mm_interconnect_0_sram_s1_byteenable), // .byteenable
.SRAM_s1_chipselect (mm_interconnect_0_sram_s1_chipselect), // .chipselect
.SRAM_s1_clken (mm_interconnect_0_sram_s1_clken), // .clken
.Sys_Timer_s1_address (mm_interconnect_0_sys_timer_s1_address), // Sys_Timer_s1.address
.Sys_Timer_s1_write (mm_interconnect_0_sys_timer_s1_write), // .write
.Sys_Timer_s1_readdata (mm_interconnect_0_sys_timer_s1_readdata), // .readdata
.Sys_Timer_s1_writedata (mm_interconnect_0_sys_timer_s1_writedata), // .writedata
.Sys_Timer_s1_chipselect (mm_interconnect_0_sys_timer_s1_chipselect), // .chipselect
.SystemID_control_slave_address (mm_interconnect_0_systemid_control_slave_address), // SystemID_control_slave.address
.SystemID_control_slave_readdata (mm_interconnect_0_systemid_control_slave_readdata), // .readdata
.Test_PipeLine_avs_s0_address (mm_interconnect_0_test_pipeline_avs_s0_address), // Test_PipeLine_avs_s0.address
.Test_PipeLine_avs_s0_write (mm_interconnect_0_test_pipeline_avs_s0_write), // .write
.Test_PipeLine_avs_s0_read (mm_interconnect_0_test_pipeline_avs_s0_read), // .read
.Test_PipeLine_avs_s0_readdata (mm_interconnect_0_test_pipeline_avs_s0_readdata), // .readdata
.Test_PipeLine_avs_s0_writedata (mm_interconnect_0_test_pipeline_avs_s0_writedata), // .writedata
.Test_PipeLine_avs_s0_waitrequest (mm_interconnect_0_test_pipeline_avs_s0_waitrequest), // .waitrequest
.UART_COM_avalon_rs232_slave_address (mm_interconnect_0_uart_com_avalon_rs232_slave_address), // UART_COM_avalon_rs232_slave.address
.UART_COM_avalon_rs232_slave_write (mm_interconnect_0_uart_com_avalon_rs232_slave_write), // .write
.UART_COM_avalon_rs232_slave_read (mm_interconnect_0_uart_com_avalon_rs232_slave_read), // .read
.UART_COM_avalon_rs232_slave_readdata (mm_interconnect_0_uart_com_avalon_rs232_slave_readdata), // .readdata
.UART_COM_avalon_rs232_slave_writedata (mm_interconnect_0_uart_com_avalon_rs232_slave_writedata), // .writedata
.UART_COM_avalon_rs232_slave_byteenable (mm_interconnect_0_uart_com_avalon_rs232_slave_byteenable), // .byteenable
.UART_COM_avalon_rs232_slave_chipselect (mm_interconnect_0_uart_com_avalon_rs232_slave_chipselect) // .chipselect
);
soc_design_irq_mapper irq_mapper (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (niosii_core_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~fpga_reset_n), // reset_in0.reset
.clk (system_pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
// Double pumped single precision floating point add/sub
// Latency = 9 kernel clocks
//
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_add_sub_dbl_pumped
#(
// Bit width of a single precision float
parameter WIDTH=32
)
(
input clock,
input clock2x,
input enable,
input add_sub,
input [WIDTH-1:0] a1,
input [WIDTH-1:0] b1,
input [WIDTH-1:0] a2,
input [WIDTH-1:0] b2,
output reg [WIDTH-1:0] y1,
output reg [WIDTH-1:0] y2
);
reg [WIDTH-1:0] a1_reg;
reg [WIDTH-1:0] b1_reg;
reg [WIDTH-1:0] a2_reg;
reg [WIDTH-1:0] b2_reg;
reg add_sub_reg;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg clk_90deg, sel2x /* synthesis preserve */;
reg [WIDTH-1:0] fp_add_sub_inp_a;
reg [WIDTH-1:0] fp_add_sub_inp_b;
reg fp_add_sub_inp_add_sub;
wire [WIDTH-1:0] fp_add_sub_res;
reg [WIDTH-1:0] fp_add_sub_res_reg;
reg [WIDTH-1:0] fp_add_sub_res_del1_2x_cycle;
//Register before double pumping
always@(posedge clock)
begin
if (enable) a1_reg <= a1;
if (enable) a2_reg <= a2;
if (enable) b1_reg <= b1;
if (enable) b2_reg <= b2;
if (enable) add_sub_reg <= add_sub;
end
generate
if (WIDTH == 32)
acl_fp_add_sub_fast the_sub(
.add_sub(fp_add_sub_inp_add_sub),
.clk_en(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
else // WIDTH == 64
acl_fp_add_sub_fast_double the_sub(
.add_sub(fp_add_sub_inp_add_sub),
.enable(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
endgenerate
//For testing purposes
//always@(posedge clk2x)
//begin
// fp_sub_res1 <= fp_sub_inp_a + fp_sub_inp_b;
// fp_sub_res <= fp_sub_res1;
//end
always@(posedge clock2x)
begin
if (enable) fp_add_sub_res_del1_2x_cycle <= fp_add_sub_res_reg;
if (enable) fp_add_sub_inp_a <= (!sel2x) ? a1_reg : a2_reg;
if (enable) fp_add_sub_inp_b <= (!sel2x) ? b1_reg : b2_reg;
if (enable) fp_add_sub_inp_add_sub <= add_sub_reg;
if (enable) fp_add_sub_res_reg <= fp_add_sub_res;
end
always@(posedge clock)
begin
if (enable) y1 <= fp_add_sub_res_del1_2x_cycle;
if (enable) y2 <= fp_add_sub_res_reg;
end
//Convert clock to data signal
always@(negedge clock2x)
clk_90deg<=clock;
always@(posedge clock2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clock
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : GTHE3_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE3_CHANNEL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'hF800,
parameter [15:0] ADAPT_CFG1 = 16'h0000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h20F8,
parameter [15:0] CPLL_CFG1 = 16'hA494,
parameter [15:0] CPLL_CFG2 = 16'hF001,
parameter [5:0] CPLL_CFG3 = 6'h00,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [7:0] CPLL_INIT_CFG1 = 8'h00,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DFE_D_X_REL_POS = 1'b0,
parameter [0:0] DFE_VCM_COMP_EN = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h000,
parameter [9:0] ES_PMA_CFG = 10'b0000000000,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] GM_BIAS_SELECT = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [2:0] PCS_RSVD1 = 3'b000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0,
parameter [15:0] PMA_RSV1 = 16'h0000,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0000,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG1 = 16'h0080,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h07E6,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG3 = 16'h0000,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG4 = 16'h0000,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG5 = 16'h0000,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [15:0] RXCFOK_CFG0 = 16'h4000,
parameter [15:0] RXCFOK_CFG1 = 16'h0060,
parameter [15:0] RXCFOK_CFG2 = 16'h000E,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000,
parameter [15:0] RXDFE_CFG0 = 16'h0A00,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h7840,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG0 = 16'h4000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H6_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG0 = 16'h2000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG0 = 16'h2000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h8000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG0 = 16'h8000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0003,
parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0033,
parameter [15:0] RXDLY_CFG = 16'h001F,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "Sigcfg_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h0000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h8000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0002,
parameter [8:0] RXOOB_CFG = 9'b000000110,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h6622,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] RXPI_CFG0 = 2'b00,
parameter [1:0] RXPI_CFG1 = 2'b00,
parameter [1:0] RXPI_CFG2 = 2'b00,
parameter [1:0] RXPI_CFG3 = 2'b00,
parameter [0:0] RXPI_CFG4 = 1'b0,
parameter [0:0] RXPI_CFG5 = 1'b1,
parameter [2:0] RXPI_CFG6 = 3'b000,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b1010,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter [1:0] RX_CM_SEL = 2'b11,
parameter [3:0] RX_CM_TRIM = 4'b0100,
parameter [7:0] RX_CTLE3_LPF = 8'b00000000,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110,
parameter [0:0] RX_DFELPM_CFG1 = 1'b0,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100,
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_HI_LR = 1'b0,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter real RX_PROGDIV_CFG = 4.0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter [1:0] RX_SUM_RES_CTRL = 2'b00,
parameter [3:0] RX_SUM_VCMTUNE = 4'b0000,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b000,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [0:0] RX_WIDEMODE_CDR = 1'b0,
parameter RX_XCLK_SEL = "RXDES",
parameter integer SAS_MAX_COM = 64,
parameter integer SAS_MIN_COM = 36,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter integer SATA_MAX_BURST = 8,
parameter integer SATA_MAX_INIT = 21,
parameter integer SATA_MAX_WAKE = 7,
parameter integer SATA_MIN_BURST = 4,
parameter integer SATA_MIN_INIT = 12,
parameter integer SATA_MIN_WAKE = 4,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0,
parameter SIM_VERSION = "Ver_1",
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATUR_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h001F,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter [3:0] TXDRVBIAS_N = 4'b1010,
parameter [3:0] TXDRVBIAS_P = 4'b1100,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h2020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0001,
parameter [15:0] TXPH_CFG = 16'h0980,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter integer TX_DATA_WIDTH = 20,
parameter [5:0] TX_DCD_CFG = 6'b000010,
parameter [0:0] TX_DCD_EN = 1'b0,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_EML_PHI_TUNE = 1'b0,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [2:0] TX_MODE_SEL = 3'b000,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 4.0,
parameter [0:0] TX_QPI_STATUS_EN = 1'b0,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter [2:0] TX_RXDETECT_REF = 3'b100,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0,
parameter [1:0] WB_MODE = 2'b00
)(
output [2:0] BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output [2:0] BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [16:0] DMONITOROUT,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTHTXN,
output GTHTXP,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [11:0] PCSRSVDOUT,
output PHYSTATUS,
output [7:0] PINRSRVDAS,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output [6:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXQPISENN,
output RXQPISENP,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXQPISENN,
output TXQPISENP,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input EVODDPHICALDONE,
input EVODDPHICALSTART,
input EVODDPHIDRDEN,
input EVODDPHIDWREN,
input EVODDPHIXRDEN,
input EVODDPHIXWREN,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTGREFCLK,
input GTHRXN,
input GTHRXP,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTRESETSEL,
input [15:0] GTRSVD,
input GTRXRESET,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input [2:0] LOOPBACK,
input LPBKRXTXSEREN,
input LPBKTXRXSEREN,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input QPLL0CLK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1REFCLK,
input RESETOVRD,
input RSTCLKENTX,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input [1:0] RXDFEAGCCTRL,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEVSEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input [3:0] RXOSINTCFG,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTOVRDEN,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input RXQPIEN,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [2:0] TXBUFDIFFCTRL,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDEEMPH,
input TXDETECTRX,
input [3:0] TXDIFFCTRL,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXPROGDIVRESET,
input TXQPIBIASEN,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTHE3_CHANNEL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0;
localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1;
localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2;
localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3;
localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1;
localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
localparam [1:0] DDI_CTRL_REG = DDI_CTRL;
localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS;
localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN;
localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
localparam [5:0] ES_CONTROL_REG = ES_CONTROL;
localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG;
localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE;
localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG;
localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT;
localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL;
localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP;
localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0;
localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1;
localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12;
localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3;
localparam [15:0] PMA_RSV1_REG = PMA_RSV1;
localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR;
localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
localparam [40:1] RXBUF_EN_REG = RXBUF_EN;
localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG;
localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG;
localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG;
localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
localparam [4:0] RXOUT_DIV_REG = RXOUT_DIV;
localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
localparam [1:0] RXPI_CFG0_REG = RXPI_CFG0;
localparam [1:0] RXPI_CFG1_REG = RXPI_CFG1;
localparam [1:0] RXPI_CFG2_REG = RXPI_CFG2;
localparam [1:0] RXPI_CFG3_REG = RXPI_CFG3;
localparam [0:0] RXPI_CFG4_REG = RXPI_CFG4;
localparam [0:0] RXPI_CFG5_REG = RXPI_CFG5;
localparam [2:0] RXPI_CFG6_REG = RXPI_CFG6;
localparam [0:0] RXPI_LPM_REG = RXPI_LPM;
localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL;
localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
localparam [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF;
localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
localparam [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
localparam [1:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL;
localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
localparam [0:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM;
localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM;
localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST;
localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT;
localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE;
localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST;
localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT;
localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE;
localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
localparam [56:1] SIM_VERSION_REG = SIM_VERSION;
localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
localparam [3:0] TEMPERATUR_PAR_REG = TEMPERATUR_PAR;
localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
localparam [7:0] TST_RSV0_REG = TST_RSV0;
localparam [7:0] TST_RSV1_REG = TST_RSV1;
localparam [40:1] TXBUF_EN_REG = TXBUF_EN;
localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG;
localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
localparam [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N;
localparam [3:0] TXDRVBIAS_P_REG = TXDRVBIAS_P;
localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
localparam [4:0] TXOUT_DIV_REG = TXOUT_DIV;
localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
localparam [15:0] TXPH_CFG_REG = TXPH_CFG;
localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0;
localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1;
localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2;
localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3;
localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4;
localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5;
localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
localparam [0:0] TXPI_LPM_REG = TXPI_LPM;
localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG;
localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN;
localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE;
localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL;
localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
localparam [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN;
localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
localparam [1:0] WB_MODE_REG = WB_MODE;
`endif
localparam [0:0] AEN_CPLL_REG = 1'b0;
localparam [0:0] AEN_EYESCAN_REG = 1'b1;
localparam [0:0] AEN_LOOPBACK_REG = 1'b0;
localparam [0:0] AEN_MASTER_REG = 1'b0;
localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
localparam [0:0] AEN_POLARITY_REG = 1'b0;
localparam [0:0] AEN_PRBS_REG = 1'b0;
localparam [0:0] AEN_QPI_REG = 1'b0;
localparam [0:0] AEN_RESET_REG = 1'b0;
localparam [0:0] AEN_RXCDR_REG = 1'b0;
localparam [0:0] AEN_RXDFE_REG = 1'b0;
localparam [0:0] AEN_RXDFELPM_REG = 1'b0;
localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXPHDLY_REG = 1'b0;
localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXPHDLY_REG = 1'b0;
localparam [0:0] AEN_TXPI_PPM_REG = 1'b0;
localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
localparam [15:0] AMONITOR_CFG_REG = 16'h0000;
localparam [0:0] A_AFECFOKEN_REG = 1'b0;
localparam [0:0] A_CPLLLOCKEN_REG = 1'b0;
localparam [0:0] A_CPLLPD_REG = 1'b0;
localparam [0:0] A_CPLLRESET_REG = 1'b0;
localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000;
localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000;
localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0;
localparam [0:0] A_DFECFOKHOLD_REG = 1'b0;
localparam [0:0] A_DFECFOKOVREN_REG = 1'b0;
localparam [0:0] A_EYESCANMODE_REG = 1'b0;
localparam [0:0] A_EYESCANRESET_REG = 1'b0;
localparam [0:0] A_GTRESETSEL_REG = 1'b0;
localparam [0:0] A_GTRXRESET_REG = 1'b0;
localparam [0:0] A_GTTXRESET_REG = 1'b0;
localparam [80:1] A_LOOPBACK_REG = "NoLoopBack";
localparam [0:0] A_LPMGCHOLD_REG = 1'b0;
localparam [0:0] A_LPMGCOVREN_REG = 1'b0;
localparam [0:0] A_LPMOSHOLD_REG = 1'b0;
localparam [0:0] A_LPMOSOVREN_REG = 1'b0;
localparam [0:0] A_RXBUFRESET_REG = 1'b0;
localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0;
localparam [0:0] A_RXCDRHOLD_REG = 1'b0;
localparam [0:0] A_RXCDROVRDEN_REG = 1'b0;
localparam [0:0] A_RXCDRRESET_REG = 1'b0;
localparam [1:0] A_RXDFEAGCCTRL_REG = 2'b00;
localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0;
localparam [0:0] A_RXDFELFHOLD_REG = 1'b0;
localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFELPMRESET_REG = 1'b0;
localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVSEN_REG = 1'b0;
localparam [0:0] A_RXDFEXYDEN_REG = 1'b0;
localparam [0:0] A_RXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_RXDLYEN_REG = 1'b0;
localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDLYSRESET_REG = 1'b0;
localparam [0:0] A_RXLPMEN_REG = 1'b0;
localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
localparam [1:0] A_RXMONITORSEL_REG = 2'b00;
localparam [0:0] A_RXOOBRESET_REG = 1'b0;
localparam [0:0] A_RXOSHOLD_REG = 1'b0;
localparam [0:0] A_RXOSOVRDEN_REG = 1'b0;
localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_RXPCSRESET_REG = 1'b0;
localparam [24:1] A_RXPD_REG = "P0";
localparam [0:0] A_RXPHALIGN_REG = 1'b0;
localparam [0:0] A_RXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_RXPHDLYPD_REG = 1'b0;
localparam [0:0] A_RXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_RXPHOVRDEN_REG = 1'b0;
localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_RXPMARESET_REG = 1'b0;
localparam [0:0] A_RXPOLARITY_REG = 1'b0;
localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
localparam [48:1] A_RXPRBSSEL_REG = "PRBS7";
localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
localparam [0:0] A_TXDEEMPH_REG = 1'b0;
localparam [3:0] A_TXDIFFCTRL_REG = 4'b1100;
localparam [0:0] A_TXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_TXDLYEN_REG = 1'b0;
localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_TXDLYSRESET_REG = 1'b0;
localparam [0:0] A_TXELECIDLE_REG = 1'b0;
localparam [0:0] A_TXINHIBIT_REG = 1'b0;
localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
localparam [2:0] A_TXMARGIN_REG = 3'b000;
localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_TXPCSRESET_REG = 1'b0;
localparam [24:1] A_TXPD_REG = "P0";
localparam [0:0] A_TXPHALIGN_REG = 1'b0;
localparam [0:0] A_TXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_TXPHDLYPD_REG = 1'b0;
localparam [0:0] A_TXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_TXPHINIT_REG = 1'b0;
localparam [0:0] A_TXPHOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMPD_REG = 1'b0;
localparam [0:0] A_TXPIPPMSEL_REG = 1'b0;
localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_TXPMARESET_REG = 1'b0;
localparam [0:0] A_TXPOLARITY_REG = 1'b0;
localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
localparam [0:0] A_TXPOSTCURSORINV_REG = 1'b0;
localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
localparam [96:1] A_TXPRBSSEL_REG = "PRBS7";
localparam [4:0] A_TXPRECURSOR_REG = 5'b00000;
localparam [0:0] A_TXPRECURSORINV_REG = 1'b0;
localparam [0:0] A_TXQPIBIASEN_REG = 1'b0;
localparam [0:0] A_TXSWING_REG = 1'b0;
localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [40:1] GEN_RXUSRCLK_REG = "TRUE";
localparam [40:1] GEN_TXUSRCLK_REG = "TRUE";
localparam [0:0] GT_INSTANTIATED_REG = 1'b1;
localparam [40:1] RXPLL_SEL_REG = "CPLL";
localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
wire [63:0] RX_PROGDIV_CFG_BIN;
wire [63:0] TX_PROGDIV_CFG_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTHE3_CHANNEL_dr.v"
`endif
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTHTXN_out;
wire GTHTXP_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXQPISENN_out;
wire RXQPISENP_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXQPISENN_out;
wire TXQPISENP_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [11:0] PCSRSVDOUT_out;
wire [11:0] PMASCANOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DRPDO_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [16:0] DMONITOROUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTCE_out;
wire [2:0] BUFGTRESET_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [6:0] RXMONITOROUT_out;
wire [7:0] PINRSRVDAS_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [8:0] BUFGTDIV_out;
wire CPLLFBCLKLOST_delay;
wire CPLLLOCK_delay;
wire CPLLREFCLKLOST_delay;
wire DRPRDY_delay;
wire EYESCANDATAERROR_delay;
wire GTHTXN_delay;
wire GTHTXP_delay;
wire GTPOWERGOOD_delay;
wire GTREFCLKMONITOR_delay;
wire PCIERATEGEN3_delay;
wire PCIERATEIDLE_delay;
wire PCIESYNCTXSYNCDONE_delay;
wire PCIEUSERGEN3RDY_delay;
wire PCIEUSERPHYSTATUSRST_delay;
wire PCIEUSERRATESTART_delay;
wire PHYSTATUS_delay;
wire RESETEXCEPTION_delay;
wire RXBYTEISALIGNED_delay;
wire RXBYTEREALIGN_delay;
wire RXCDRLOCK_delay;
wire RXCDRPHDONE_delay;
wire RXCHANBONDSEQ_delay;
wire RXCHANISALIGNED_delay;
wire RXCHANREALIGN_delay;
wire RXCOMINITDET_delay;
wire RXCOMMADET_delay;
wire RXCOMSASDET_delay;
wire RXCOMWAKEDET_delay;
wire RXDLYSRESETDONE_delay;
wire RXELECIDLE_delay;
wire RXOSINTDONE_delay;
wire RXOSINTSTARTED_delay;
wire RXOSINTSTROBEDONE_delay;
wire RXOSINTSTROBESTARTED_delay;
wire RXOUTCLKFABRIC_delay;
wire RXOUTCLKPCS_delay;
wire RXOUTCLK_delay;
wire RXPHALIGNDONE_delay;
wire RXPHALIGNERR_delay;
wire RXPMARESETDONE_delay;
wire RXPRBSERR_delay;
wire RXPRBSLOCKED_delay;
wire RXPRGDIVRESETDONE_delay;
wire RXQPISENN_delay;
wire RXQPISENP_delay;
wire RXRATEDONE_delay;
wire RXRECCLKOUT_delay;
wire RXRESETDONE_delay;
wire RXSLIDERDY_delay;
wire RXSLIPDONE_delay;
wire RXSLIPOUTCLKRDY_delay;
wire RXSLIPPMARDY_delay;
wire RXSYNCDONE_delay;
wire RXSYNCOUT_delay;
wire RXVALID_delay;
wire TXCOMFINISH_delay;
wire TXDLYSRESETDONE_delay;
wire TXOUTCLKFABRIC_delay;
wire TXOUTCLKPCS_delay;
wire TXOUTCLK_delay;
wire TXPHALIGNDONE_delay;
wire TXPHINITDONE_delay;
wire TXPMARESETDONE_delay;
wire TXPRGDIVRESETDONE_delay;
wire TXQPISENN_delay;
wire TXQPISENP_delay;
wire TXRATEDONE_delay;
wire TXRESETDONE_delay;
wire TXSYNCDONE_delay;
wire TXSYNCOUT_delay;
wire [11:0] PCSRSVDOUT_delay;
wire [127:0] RXDATA_delay;
wire [15:0] DRPDO_delay;
wire [15:0] RXCTRL0_delay;
wire [15:0] RXCTRL1_delay;
wire [16:0] DMONITOROUT_delay;
wire [1:0] PCIERATEQPLLPD_delay;
wire [1:0] PCIERATEQPLLRESET_delay;
wire [1:0] RXCLKCORCNT_delay;
wire [1:0] RXDATAVALID_delay;
wire [1:0] RXHEADERVALID_delay;
wire [1:0] RXSTARTOFSEQ_delay;
wire [1:0] TXBUFSTATUS_delay;
wire [2:0] BUFGTCEMASK_delay;
wire [2:0] BUFGTCE_delay;
wire [2:0] BUFGTRESET_delay;
wire [2:0] BUFGTRSTMASK_delay;
wire [2:0] RXBUFSTATUS_delay;
wire [2:0] RXSTATUS_delay;
wire [4:0] RXCHBONDO_delay;
wire [5:0] RXHEADER_delay;
wire [6:0] RXMONITOROUT_delay;
wire [7:0] PINRSRVDAS_delay;
wire [7:0] RXCTRL2_delay;
wire [7:0] RXCTRL3_delay;
wire [7:0] RXDATAEXTENDRSVD_delay;
wire [8:0] BUFGTDIV_delay;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire EVODDPHICALDONE_in;
wire EVODDPHICALSTART_in;
wire EVODDPHIDRDEN_in;
wire EVODDPHIDWREN_in;
wire EVODDPHIXRDEN_in;
wire EVODDPHIXWREN_in;
wire EYESCANMODE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire GTGREFCLK_in;
wire GTHRXN_in;
wire GTHRXP_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESET_in;
wire LPBKRXTXSEREN_in;
wire LPBKTXRXSEREN_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RSTCLKENTX_in;
wire RX8B10BEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESETRSV_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCOMMADETEN_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEVSEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSINTEN_in;
wire RXOSINTHOLD_in;
wire RXOSINTOVRDEN_in;
wire RXOSINTSTROBE_in;
wire RXOSINTTESTOVRDEN_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXQPIEN_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDEEMPH_in;
wire TXDETECTRX_in;
wire TXDIFFPD_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPOSTCURSORINV_in;
wire TXPRBSFORCEERR_in;
wire TXPRECURSORINV_in;
wire TXPROGDIVRESET_in;
wire TXQPIBIASEN_in;
wire TXQPISTRONGPDOWN_in;
wire TXQPIWEAKPUP_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [11:0] PMASCANIN_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXDFEAGCCTRL_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXBUFDIFFCTRL_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXOSINTCFG_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXDIFFCTRL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] PCSRSVDIN2_in;
wire [4:0] PMARSVDIN_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [8:0] DRPADDR_in;
wire CFGRESET_delay;
wire CLKRSVD0_delay;
wire CLKRSVD1_delay;
wire CPLLLOCKDETCLK_delay;
wire CPLLLOCKEN_delay;
wire CPLLPD_delay;
wire CPLLRESET_delay;
wire DMONFIFORESET_delay;
wire DMONITORCLK_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire EVODDPHICALDONE_delay;
wire EVODDPHICALSTART_delay;
wire EVODDPHIDRDEN_delay;
wire EVODDPHIDWREN_delay;
wire EVODDPHIXRDEN_delay;
wire EVODDPHIXWREN_delay;
wire EYESCANMODE_delay;
wire EYESCANRESET_delay;
wire EYESCANTRIGGER_delay;
wire GTGREFCLK_delay;
wire GTHRXN_delay;
wire GTHRXP_delay;
wire GTNORTHREFCLK0_delay;
wire GTNORTHREFCLK1_delay;
wire GTREFCLK0_delay;
wire GTREFCLK1_delay;
wire GTRESETSEL_delay;
wire GTRXRESET_delay;
wire GTSOUTHREFCLK0_delay;
wire GTSOUTHREFCLK1_delay;
wire GTTXRESET_delay;
wire LPBKRXTXSEREN_delay;
wire LPBKTXRXSEREN_delay;
wire PCIEEQRXEQADAPTDONE_delay;
wire PCIERSTIDLE_delay;
wire PCIERSTTXSYNCSTART_delay;
wire PCIEUSERRATEDONE_delay;
wire QPLL0CLK_delay;
wire QPLL0REFCLK_delay;
wire QPLL1CLK_delay;
wire QPLL1REFCLK_delay;
wire RESETOVRD_delay;
wire RSTCLKENTX_delay;
wire RX8B10BEN_delay;
wire RXBUFRESET_delay;
wire RXCDRFREQRESET_delay;
wire RXCDRHOLD_delay;
wire RXCDROVRDEN_delay;
wire RXCDRRESETRSV_delay;
wire RXCDRRESET_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCOMMADETEN_delay;
wire RXDFEAGCHOLD_delay;
wire RXDFEAGCOVRDEN_delay;
wire RXDFELFHOLD_delay;
wire RXDFELFOVRDEN_delay;
wire RXDFELPMRESET_delay;
wire RXDFETAP10HOLD_delay;
wire RXDFETAP10OVRDEN_delay;
wire RXDFETAP11HOLD_delay;
wire RXDFETAP11OVRDEN_delay;
wire RXDFETAP12HOLD_delay;
wire RXDFETAP12OVRDEN_delay;
wire RXDFETAP13HOLD_delay;
wire RXDFETAP13OVRDEN_delay;
wire RXDFETAP14HOLD_delay;
wire RXDFETAP14OVRDEN_delay;
wire RXDFETAP15HOLD_delay;
wire RXDFETAP15OVRDEN_delay;
wire RXDFETAP2HOLD_delay;
wire RXDFETAP2OVRDEN_delay;
wire RXDFETAP3HOLD_delay;
wire RXDFETAP3OVRDEN_delay;
wire RXDFETAP4HOLD_delay;
wire RXDFETAP4OVRDEN_delay;
wire RXDFETAP5HOLD_delay;
wire RXDFETAP5OVRDEN_delay;
wire RXDFETAP6HOLD_delay;
wire RXDFETAP6OVRDEN_delay;
wire RXDFETAP7HOLD_delay;
wire RXDFETAP7OVRDEN_delay;
wire RXDFETAP8HOLD_delay;
wire RXDFETAP8OVRDEN_delay;
wire RXDFETAP9HOLD_delay;
wire RXDFETAP9OVRDEN_delay;
wire RXDFEUTHOLD_delay;
wire RXDFEUTOVRDEN_delay;
wire RXDFEVPHOLD_delay;
wire RXDFEVPOVRDEN_delay;
wire RXDFEVSEN_delay;
wire RXDFEXYDEN_delay;
wire RXDLYBYPASS_delay;
wire RXDLYEN_delay;
wire RXDLYOVRDEN_delay;
wire RXDLYSRESET_delay;
wire RXGEARBOXSLIP_delay;
wire RXLATCLK_delay;
wire RXLPMEN_delay;
wire RXLPMGCHOLD_delay;
wire RXLPMGCOVRDEN_delay;
wire RXLPMHFHOLD_delay;
wire RXLPMHFOVRDEN_delay;
wire RXLPMLFHOLD_delay;
wire RXLPMLFKLOVRDEN_delay;
wire RXLPMOSHOLD_delay;
wire RXLPMOSOVRDEN_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXOOBRESET_delay;
wire RXOSCALRESET_delay;
wire RXOSHOLD_delay;
wire RXOSINTEN_delay;
wire RXOSINTHOLD_delay;
wire RXOSINTOVRDEN_delay;
wire RXOSINTSTROBE_delay;
wire RXOSINTTESTOVRDEN_delay;
wire RXOSOVRDEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPCSRESET_delay;
wire RXPHALIGNEN_delay;
wire RXPHALIGN_delay;
wire RXPHDLYPD_delay;
wire RXPHDLYRESET_delay;
wire RXPHOVRDEN_delay;
wire RXPMARESET_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXPROGDIVRESET_delay;
wire RXQPIEN_delay;
wire RXRATEMODE_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXSYNCALLIN_delay;
wire RXSYNCIN_delay;
wire RXSYNCMODE_delay;
wire RXUSERRDY_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire SIGVALIDCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDEEMPH_delay;
wire TXDETECTRX_delay;
wire TXDIFFPD_delay;
wire TXDLYBYPASS_delay;
wire TXDLYEN_delay;
wire TXDLYHOLD_delay;
wire TXDLYOVRDEN_delay;
wire TXDLYSRESET_delay;
wire TXDLYUPDOWN_delay;
wire TXELECIDLE_delay;
wire TXINHIBIT_delay;
wire TXLATCLK_delay;
wire TXPCSRESET_delay;
wire TXPDELECIDLEMODE_delay;
wire TXPHALIGNEN_delay;
wire TXPHALIGN_delay;
wire TXPHDLYPD_delay;
wire TXPHDLYRESET_delay;
wire TXPHDLYTSTCLK_delay;
wire TXPHINIT_delay;
wire TXPHOVRDEN_delay;
wire TXPIPPMEN_delay;
wire TXPIPPMOVRDEN_delay;
wire TXPIPPMPD_delay;
wire TXPIPPMSEL_delay;
wire TXPISOPD_delay;
wire TXPMARESET_delay;
wire TXPOLARITY_delay;
wire TXPOSTCURSORINV_delay;
wire TXPRBSFORCEERR_delay;
wire TXPRECURSORINV_delay;
wire TXPROGDIVRESET_delay;
wire TXQPIBIASEN_delay;
wire TXQPISTRONGPDOWN_delay;
wire TXQPIWEAKPUP_delay;
wire TXRATEMODE_delay;
wire TXSWING_delay;
wire TXSYNCALLIN_delay;
wire TXSYNCIN_delay;
wire TXSYNCMODE_delay;
wire TXUSERRDY_delay;
wire TXUSRCLK2_delay;
wire TXUSRCLK_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] GTRSVD_delay;
wire [15:0] PCSRSVDIN_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [19:0] TSTIN_delay;
wire [1:0] RXDFEAGCCTRL_delay;
wire [1:0] RXELECIDLEMODE_delay;
wire [1:0] RXMONITORSEL_delay;
wire [1:0] RXPD_delay;
wire [1:0] RXPLLCLKSEL_delay;
wire [1:0] RXSYSCLKSEL_delay;
wire [1:0] TXPD_delay;
wire [1:0] TXPLLCLKSEL_delay;
wire [1:0] TXSYSCLKSEL_delay;
wire [2:0] CPLLREFCLKSEL_delay;
wire [2:0] LOOPBACK_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXOUTCLKSEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXBUFDIFFCTRL_delay;
wire [2:0] TXMARGIN_delay;
wire [2:0] TXOUTCLKSEL_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXOSINTCFG_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXDIFFCTRL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] PCSRSVDIN2_delay;
wire [4:0] PMARSVDIN_delay;
wire [4:0] RXCHBONDI_delay;
wire [4:0] TXPIPPMSTEPSIZE_delay;
wire [4:0] TXPOSTCURSOR_delay;
wire [4:0] TXPRECURSOR_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXMAINCURSOR_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [7:0] TXDATAEXTENDRSVD_delay;
wire [8:0] DRPADDR_delay;
assign #(out_delay) BUFGTCE = BUFGTCE_delay;
assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay;
assign #(out_delay) BUFGTDIV = BUFGTDIV_delay;
assign #(out_delay) BUFGTRESET = BUFGTRESET_delay;
assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay;
assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay;
assign #(out_delay) CPLLLOCK = CPLLLOCK_delay;
assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay;
assign #(out_delay) DMONITOROUT = DMONITOROUT_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay;
assign #(out_delay) GTHTXN = GTHTXN_delay;
assign #(out_delay) GTHTXP = GTHTXP_delay;
assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay;
assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay;
assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay;
assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay;
assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay;
assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay;
assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay;
assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay;
assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay;
assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay;
assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay;
assign #(out_delay) PHYSTATUS = PHYSTATUS_delay;
assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay;
assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay;
assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay;
assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay;
assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay;
assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay;
assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay;
assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay;
assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay;
assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay;
assign #(out_delay) RXCHBONDO = RXCHBONDO_delay;
assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay;
assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay;
assign #(out_delay) RXCOMMADET = RXCOMMADET_delay;
assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay;
assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay;
assign #(out_delay) RXCTRL0 = RXCTRL0_delay;
assign #(out_delay) RXCTRL1 = RXCTRL1_delay;
assign #(out_delay) RXCTRL2 = RXCTRL2_delay;
assign #(out_delay) RXCTRL3 = RXCTRL3_delay;
assign #(out_delay) RXDATA = RXDATA_delay;
assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay;
assign #(out_delay) RXDATAVALID = RXDATAVALID_delay;
assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay;
assign #(out_delay) RXELECIDLE = RXELECIDLE_delay;
assign #(out_delay) RXHEADER = RXHEADER_delay;
assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay;
assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay;
assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay;
assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay;
assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay;
assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay;
assign #(out_delay) RXOUTCLK = RXOUTCLK_delay;
assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay;
assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay;
assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay;
assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay;
assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay;
assign #(out_delay) RXPRBSERR = RXPRBSERR_delay;
assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay;
assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay;
assign #(out_delay) RXQPISENN = RXQPISENN_delay;
assign #(out_delay) RXQPISENP = RXQPISENP_delay;
assign #(out_delay) RXRATEDONE = RXRATEDONE_delay;
assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay;
assign #(out_delay) RXRESETDONE = RXRESETDONE_delay;
assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay;
assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay;
assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay;
assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay;
assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay;
assign #(out_delay) RXSTATUS = RXSTATUS_delay;
assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay;
assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay;
assign #(out_delay) RXVALID = RXVALID_delay;
assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay;
assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay;
assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay;
assign #(out_delay) TXOUTCLK = TXOUTCLK_delay;
assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay;
assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay;
assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay;
assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay;
assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay;
assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay;
assign #(out_delay) TXQPISENN = TXQPISENN_delay;
assign #(out_delay) TXQPISENP = TXQPISENP_delay;
assign #(out_delay) TXRATEDONE = TXRATEDONE_delay;
assign #(out_delay) TXRESETDONE = TXRESETDONE_delay;
assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay;
assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2;
assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK;
assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) RX8B10BEN_delay = RX8B10BEN;
assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN;
assign #(in_delay) RXCHBONDI_delay = RXCHBONDI;
assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL;
assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER;
assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE;
assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN;
assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP;
assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN;
assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN;
assign #(in_delay) RXPOLARITY_delay = RXPOLARITY;
assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET;
assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL;
assign #(in_delay) RXRATE_delay = RXRATE;
assign #(in_delay) RXSLIDE_delay = RXSLIDE;
assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK;
assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA;
assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS;
assign #(in_delay) TX8B10BEN_delay = TX8B10BEN;
assign #(in_delay) TXCOMINIT_delay = TXCOMINIT;
assign #(in_delay) TXCOMSAS_delay = TXCOMSAS;
assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE;
assign #(in_delay) TXCTRL0_delay = TXCTRL0;
assign #(in_delay) TXCTRL1_delay = TXCTRL1;
assign #(in_delay) TXCTRL2_delay = TXCTRL2;
assign #(in_delay) TXDATA_delay = TXDATA;
assign #(in_delay) TXDETECTRX_delay = TXDETECTRX;
assign #(in_delay) TXELECIDLE_delay = TXELECIDLE;
assign #(in_delay) TXHEADER_delay = TXHEADER;
assign #(in_delay) TXINHIBIT_delay = TXINHIBIT;
assign #(in_delay) TXPD_delay = TXPD;
assign #(in_delay) TXPOLARITY_delay = TXPOLARITY;
assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR;
assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL;
assign #(in_delay) TXRATE_delay = TXRATE;
assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0;
assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1;
assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK;
assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK;
assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK;
assign #(inclk_delay) RXLATCLK_delay = RXLATCLK;
assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK;
assign #(inclk_delay) TXLATCLK_delay = TXLATCLK;
assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK;
assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK;
assign #(in_delay) CFGRESET_delay = CFGRESET;
assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN;
assign #(in_delay) CPLLPD_delay = CPLLPD;
assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL;
assign #(in_delay) CPLLRESET_delay = CPLLRESET;
assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET;
assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE;
assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART;
assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN;
assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN;
assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN;
assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN;
assign #(in_delay) EYESCANMODE_delay = EYESCANMODE;
assign #(in_delay) EYESCANRESET_delay = EYESCANRESET;
assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER;
assign #(in_delay) GTHRXN_delay = GTHRXN;
assign #(in_delay) GTHRXP_delay = GTHRXP;
assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0;
assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1;
assign #(in_delay) GTREFCLK0_delay = GTREFCLK0;
assign #(in_delay) GTREFCLK1_delay = GTREFCLK1;
assign #(in_delay) GTRESETSEL_delay = GTRESETSEL;
assign #(in_delay) GTRSVD_delay = GTRSVD;
assign #(in_delay) GTRXRESET_delay = GTRXRESET;
assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0;
assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1;
assign #(in_delay) GTTXRESET_delay = GTTXRESET;
assign #(in_delay) LOOPBACK_delay = LOOPBACK;
assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN;
assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN;
assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE;
assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE;
assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART;
assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE;
assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2;
assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN;
assign #(in_delay) PMARSVDIN_delay = PMARSVDIN;
assign #(in_delay) QPLL0CLK_delay = QPLL0CLK;
assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK;
assign #(in_delay) QPLL1CLK_delay = QPLL1CLK;
assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK;
assign #(in_delay) RESETOVRD_delay = RESETOVRD;
assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX;
assign #(in_delay) RXBUFRESET_delay = RXBUFRESET;
assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET;
assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD;
assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN;
assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV;
assign #(in_delay) RXCDRRESET_delay = RXCDRRESET;
assign #(in_delay) RXDFEAGCCTRL_delay = RXDFEAGCCTRL;
assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD;
assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN;
assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD;
assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN;
assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET;
assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD;
assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN;
assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD;
assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN;
assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD;
assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN;
assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD;
assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN;
assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD;
assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN;
assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD;
assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN;
assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD;
assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN;
assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD;
assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN;
assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD;
assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN;
assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD;
assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN;
assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD;
assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN;
assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD;
assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN;
assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD;
assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN;
assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD;
assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN;
assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD;
assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN;
assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD;
assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN;
assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN;
assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN;
assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS;
assign #(in_delay) RXDLYEN_delay = RXDLYEN;
assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN;
assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET;
assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE;
assign #(in_delay) RXLPMEN_delay = RXLPMEN;
assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD;
assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN;
assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD;
assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN;
assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD;
assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN;
assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD;
assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN;
assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL;
assign #(in_delay) RXOOBRESET_delay = RXOOBRESET;
assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET;
assign #(in_delay) RXOSHOLD_delay = RXOSHOLD;
assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG;
assign #(in_delay) RXOSINTEN_delay = RXOSINTEN;
assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD;
assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN;
assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE;
assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN;
assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN;
assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL;
assign #(in_delay) RXPCSRESET_delay = RXPCSRESET;
assign #(in_delay) RXPD_delay = RXPD;
assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN;
assign #(in_delay) RXPHALIGN_delay = RXPHALIGN;
assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD;
assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET;
assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN;
assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL;
assign #(in_delay) RXPMARESET_delay = RXPMARESET;
assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET;
assign #(in_delay) RXQPIEN_delay = RXQPIEN;
assign #(in_delay) RXRATEMODE_delay = RXRATEMODE;
assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN;
assign #(in_delay) RXSYNCIN_delay = RXSYNCIN;
assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE;
assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL;
assign #(in_delay) RXUSERRDY_delay = RXUSERRDY;
assign #(in_delay) TSTIN_delay = TSTIN;
assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL;
assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD;
assign #(in_delay) TXDEEMPH_delay = TXDEEMPH;
assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL;
assign #(in_delay) TXDIFFPD_delay = TXDIFFPD;
assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS;
assign #(in_delay) TXDLYEN_delay = TXDLYEN;
assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD;
assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN;
assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET;
assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN;
assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR;
assign #(in_delay) TXMARGIN_delay = TXMARGIN;
assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL;
assign #(in_delay) TXPCSRESET_delay = TXPCSRESET;
assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE;
assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN;
assign #(in_delay) TXPHALIGN_delay = TXPHALIGN;
assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD;
assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET;
assign #(in_delay) TXPHINIT_delay = TXPHINIT;
assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN;
assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN;
assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN;
assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD;
assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL;
assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE;
assign #(in_delay) TXPISOPD_delay = TXPISOPD;
assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL;
assign #(in_delay) TXPMARESET_delay = TXPMARESET;
assign #(in_delay) TXPOSTCURSORINV_delay = TXPOSTCURSORINV;
assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR;
assign #(in_delay) TXPRECURSORINV_delay = TXPRECURSORINV;
assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR;
assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET;
assign #(in_delay) TXQPIBIASEN_delay = TXQPIBIASEN;
assign #(in_delay) TXQPISTRONGPDOWN_delay = TXQPISTRONGPDOWN;
assign #(in_delay) TXQPIWEAKPUP_delay = TXQPIWEAKPUP;
assign #(in_delay) TXRATEMODE_delay = TXRATEMODE;
assign #(in_delay) TXSWING_delay = TXSWING;
assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN;
assign #(in_delay) TXSYNCIN_delay = TXSYNCIN;
assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE;
assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL;
assign #(in_delay) TXUSERRDY_delay = TXUSERRDY;
assign BUFGTCEMASK_delay = BUFGTCEMASK_out;
assign BUFGTCE_delay = BUFGTCE_out;
assign BUFGTDIV_delay = BUFGTDIV_out;
assign BUFGTRESET_delay = BUFGTRESET_out;
assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out;
assign CPLLLOCK_delay = CPLLLOCK_out;
assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out;
assign DMONITOROUT_delay = DMONITOROUT_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out;
assign GTHTXN_delay = GTHTXN_out;
assign GTHTXP_delay = GTHTXP_out;
assign GTPOWERGOOD_delay = GTPOWERGOOD_out;
assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out;
assign PCIERATEGEN3_delay = PCIERATEGEN3_out;
assign PCIERATEIDLE_delay = PCIERATEIDLE_out;
assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out;
assign PCSRSVDOUT_delay = PCSRSVDOUT_out;
assign PHYSTATUS_delay = PHYSTATUS_out;
assign PINRSRVDAS_delay = PINRSRVDAS_out;
assign RESETEXCEPTION_delay = RESETEXCEPTION_out;
assign RXBUFSTATUS_delay = RXBUFSTATUS_out;
assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out;
assign RXCDRLOCK_delay = RXCDRLOCK_out;
assign RXCDRPHDONE_delay = RXCDRPHDONE_out;
assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out;
assign RXCHANREALIGN_delay = RXCHANREALIGN_out;
assign RXCHBONDO_delay = RXCHBONDO_out;
assign RXCLKCORCNT_delay = RXCLKCORCNT_out;
assign RXCOMINITDET_delay = RXCOMINITDET_out;
assign RXCOMMADET_delay = RXCOMMADET_out;
assign RXCOMSASDET_delay = RXCOMSASDET_out;
assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out;
assign RXCTRL0_delay = RXCTRL0_out;
assign RXCTRL1_delay = RXCTRL1_out;
assign RXCTRL2_delay = RXCTRL2_out;
assign RXCTRL3_delay = RXCTRL3_out;
assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out;
assign RXDATAVALID_delay = RXDATAVALID_out;
assign RXDATA_delay = RXDATA_out;
assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out;
assign RXELECIDLE_delay = RXELECIDLE_out;
assign RXHEADERVALID_delay = RXHEADERVALID_out;
assign RXHEADER_delay = RXHEADER_out;
assign RXMONITOROUT_delay = RXMONITOROUT_out;
assign RXOSINTDONE_delay = RXOSINTDONE_out;
assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out;
assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out;
assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out;
assign RXOUTCLK_delay = RXOUTCLK_out;
assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out;
assign RXPHALIGNERR_delay = RXPHALIGNERR_out;
assign RXPMARESETDONE_delay = RXPMARESETDONE_out;
assign RXPRBSERR_delay = RXPRBSERR_out;
assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out;
assign RXQPISENN_delay = RXQPISENN_out;
assign RXQPISENP_delay = RXQPISENP_out;
assign RXRATEDONE_delay = RXRATEDONE_out;
assign RXRECCLKOUT_delay = RXRECCLKOUT_out;
assign RXRESETDONE_delay = RXRESETDONE_out;
assign RXSLIDERDY_delay = RXSLIDERDY_out;
assign RXSLIPDONE_delay = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out;
assign RXSTATUS_delay = RXSTATUS_out;
assign RXSYNCDONE_delay = RXSYNCDONE_out;
assign RXSYNCOUT_delay = RXSYNCOUT_out;
assign RXVALID_delay = RXVALID_out;
assign TXBUFSTATUS_delay = TXBUFSTATUS_out;
assign TXCOMFINISH_delay = TXCOMFINISH_out;
assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out;
assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out;
assign TXOUTCLK_delay = TXOUTCLK_out;
assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out;
assign TXPHINITDONE_delay = TXPHINITDONE_out;
assign TXPMARESETDONE_delay = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out;
assign TXQPISENN_delay = TXQPISENN_out;
assign TXQPISENP_delay = TXQPISENP_out;
assign TXRATEDONE_delay = TXRATEDONE_out;
assign TXRESETDONE_delay = TXRESETDONE_out;
assign TXSYNCDONE_delay = TXSYNCDONE_out;
assign TXSYNCOUT_delay = TXSYNCOUT_out;
assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET_delay; // rv 0
assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0_delay; // rv 0
assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1_delay; // rv 0
assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK_delay; // rv 0
assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN_delay; // rv 0
assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD_delay; // rv 0
assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL_delay[0]; // rv 1
assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL_delay[1]; // rv 0
assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL_delay[2]; // rv 0
assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET_delay; // rv 0
assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET_delay; // rv 0
assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK_delay; // rv 0
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign EVODDPHICALDONE_in = (EVODDPHICALDONE !== 1'bz) && EVODDPHICALDONE_delay; // rv 0
assign EVODDPHICALSTART_in = (EVODDPHICALSTART !== 1'bz) && EVODDPHICALSTART_delay; // rv 0
assign EVODDPHIDRDEN_in = (EVODDPHIDRDEN !== 1'bz) && EVODDPHIDRDEN_delay; // rv 0
assign EVODDPHIDWREN_in = (EVODDPHIDWREN !== 1'bz) && EVODDPHIDWREN_delay; // rv 0
assign EVODDPHIXRDEN_in = (EVODDPHIXRDEN !== 1'bz) && EVODDPHIXRDEN_delay; // rv 0
assign EVODDPHIXWREN_in = (EVODDPHIXWREN !== 1'bz) && EVODDPHIXWREN_delay; // rv 0
assign EYESCANMODE_in = (EYESCANMODE !== 1'bz) && EYESCANMODE_delay; // rv 0
assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET_delay; // rv 0
assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER_delay; // rv 0
assign GTGREFCLK_in = GTGREFCLK_delay;
assign GTHRXN_in = GTHRXN_delay;
assign GTHRXP_in = GTHRXP_delay;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay;
assign GTREFCLK0_in = GTREFCLK0_delay;
assign GTREFCLK1_in = GTREFCLK1_delay;
assign GTRESETSEL_in = (GTRESETSEL !== 1'bz) && GTRESETSEL_delay; // rv 0
assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD_delay[0]; // rv 0
assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD_delay[10]; // rv 0
assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD_delay[11]; // rv 0
assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD_delay[12]; // rv 0
assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD_delay[13]; // rv 0
assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD_delay[14]; // rv 0
assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD_delay[15]; // rv 0
assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD_delay[1]; // rv 0
assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD_delay[2]; // rv 0
assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD_delay[3]; // rv 0
assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD_delay[4]; // rv 0
assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD_delay[5]; // rv 0
assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD_delay[6]; // rv 0
assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD_delay[7]; // rv 0
assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD_delay[8]; // rv 0
assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD_delay[9]; // rv 0
assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET_delay; // rv 0
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay;
assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET_delay; // rv 0
assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK_delay[0]; // rv 0
assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK_delay[1]; // rv 0
assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK_delay[2]; // rv 0
assign LPBKRXTXSEREN_in = (LPBKRXTXSEREN !== 1'bz) && LPBKRXTXSEREN_delay; // rv 0
assign LPBKTXRXSEREN_in = (LPBKTXRXSEREN !== 1'bz) && LPBKTXRXSEREN_delay; // rv 0
assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE_delay; // rv 0
assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE_delay; // rv 0
assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART_delay; // rv 0
assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE_delay; // rv 0
assign PCSRSVDIN2_in[0] = (PCSRSVDIN2[0] !== 1'bz) && PCSRSVDIN2_delay[0]; // rv 0
assign PCSRSVDIN2_in[1] = (PCSRSVDIN2[1] !== 1'bz) && PCSRSVDIN2_delay[1]; // rv 0
assign PCSRSVDIN2_in[2] = (PCSRSVDIN2[2] !== 1'bz) && PCSRSVDIN2_delay[2]; // rv 0
assign PCSRSVDIN2_in[3] = (PCSRSVDIN2[3] !== 1'bz) && PCSRSVDIN2_delay[3]; // rv 0
assign PCSRSVDIN2_in[4] = (PCSRSVDIN2[4] !== 1'bz) && PCSRSVDIN2_delay[4]; // rv 0
assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] !== 1'bz) && PCSRSVDIN_delay[0]; // rv 0
assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN_delay[10]; // rv 0
assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN_delay[11]; // rv 0
assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN_delay[12]; // rv 0
assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN_delay[13]; // rv 0
assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN_delay[14]; // rv 0
assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN_delay[15]; // rv 0
assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN_delay[1]; // rv 0
assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN_delay[2]; // rv 0
assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN_delay[3]; // rv 0
assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN_delay[4]; // rv 0
assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN_delay[5]; // rv 0
assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN_delay[6]; // rv 0
assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN_delay[7]; // rv 0
assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN_delay[8]; // rv 0
assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN_delay[9]; // rv 0
assign PMARSVDIN_in[0] = (PMARSVDIN[0] !== 1'bz) && PMARSVDIN_delay[0]; // rv 0
assign PMARSVDIN_in[1] = (PMARSVDIN[1] !== 1'bz) && PMARSVDIN_delay[1]; // rv 0
assign PMARSVDIN_in[2] = (PMARSVDIN[2] !== 1'bz) && PMARSVDIN_delay[2]; // rv 0
assign PMARSVDIN_in[3] = (PMARSVDIN[3] !== 1'bz) && PMARSVDIN_delay[3]; // rv 0
assign PMARSVDIN_in[4] = (PMARSVDIN[4] !== 1'bz) && PMARSVDIN_delay[4]; // rv 0
assign QPLL0CLK_in = QPLL0CLK_delay;
assign QPLL0REFCLK_in = QPLL0REFCLK_delay;
assign QPLL1CLK_in = QPLL1CLK_delay;
assign QPLL1REFCLK_in = QPLL1REFCLK_delay;
assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD_delay; // rv 0
assign RSTCLKENTX_in = (RSTCLKENTX !== 1'bz) && RSTCLKENTX_delay; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0
assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET_delay; // rv 0
assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET_delay; // rv 0
assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD_delay; // rv 0
assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN_delay; // rv 0
assign RXCDRRESETRSV_in = (RXCDRRESETRSV !== 1'bz) && RXCDRRESETRSV_delay; // rv 0
assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET_delay; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0
assign RXDFEAGCCTRL_in[0] = (RXDFEAGCCTRL[0] !== 1'bz) && RXDFEAGCCTRL_delay[0]; // rv 0
assign RXDFEAGCCTRL_in[1] = (RXDFEAGCCTRL[1] !== 1'bz) && RXDFEAGCCTRL_delay[1]; // rv 0
assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD_delay; // rv 0
assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN_delay; // rv 0
assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD_delay; // rv 0
assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN_delay; // rv 0
assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET_delay; // rv 0
assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD_delay; // rv 0
assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN_delay; // rv 0
assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD_delay; // rv 0
assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN_delay; // rv 0
assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD_delay; // rv 0
assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN_delay; // rv 0
assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD_delay; // rv 0
assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN_delay; // rv 0
assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD_delay; // rv 0
assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN_delay; // rv 0
assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD_delay; // rv 0
assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN_delay; // rv 0
assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD_delay; // rv 0
assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN_delay; // rv 0
assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD_delay; // rv 0
assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN_delay; // rv 0
assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD_delay; // rv 0
assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN_delay; // rv 0
assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD_delay; // rv 0
assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN_delay; // rv 0
assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD_delay; // rv 0
assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN_delay; // rv 0
assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD_delay; // rv 0
assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN_delay; // rv 0
assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD_delay; // rv 0
assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN_delay; // rv 0
assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD_delay; // rv 0
assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN_delay; // rv 0
assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD_delay; // rv 0
assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN_delay; // rv 0
assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD_delay; // rv 0
assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN_delay; // rv 0
assign RXDFEVSEN_in = (RXDFEVSEN !== 1'bz) && RXDFEVSEN_delay; // rv 0
assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN_delay; // rv 0
assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS_delay; // rv 0
assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN_delay; // rv 0
assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN_delay; // rv 0
assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET_delay; // rv 0
assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE_delay[0]; // rv 0
assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE_delay[1]; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0
assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK_delay; // rv 0
assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN_delay; // rv 0
assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD_delay; // rv 0
assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN_delay; // rv 0
assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD_delay; // rv 0
assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN_delay; // rv 0
assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD_delay; // rv 0
assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN_delay; // rv 0
assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD_delay; // rv 0
assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN_delay; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0
assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL_delay[0]; // rv 0
assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL_delay[1]; // rv 0
assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET_delay; // rv 0
assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET_delay; // rv 0
assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD_delay; // rv 0
assign RXOSINTCFG_in[0] = (RXOSINTCFG[0] !== 1'bz) && RXOSINTCFG_delay[0]; // rv 0
assign RXOSINTCFG_in[1] = (RXOSINTCFG[1] === 1'bz) || RXOSINTCFG_delay[1]; // rv 1
assign RXOSINTCFG_in[2] = (RXOSINTCFG[2] === 1'bz) || RXOSINTCFG_delay[2]; // rv 1
assign RXOSINTCFG_in[3] = (RXOSINTCFG[3] !== 1'bz) && RXOSINTCFG_delay[3]; // rv 0
assign RXOSINTEN_in = (RXOSINTEN === 1'bz) || RXOSINTEN_delay; // rv 1
assign RXOSINTHOLD_in = (RXOSINTHOLD !== 1'bz) && RXOSINTHOLD_delay; // rv 0
assign RXOSINTOVRDEN_in = (RXOSINTOVRDEN !== 1'bz) && RXOSINTOVRDEN_delay; // rv 0
assign RXOSINTSTROBE_in = (RXOSINTSTROBE !== 1'bz) && RXOSINTSTROBE_delay; // rv 0
assign RXOSINTTESTOVRDEN_in = (RXOSINTTESTOVRDEN !== 1'bz) && RXOSINTTESTOVRDEN_delay; // rv 0
assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN_delay; // rv 0
assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL_delay[0]; // rv 0
assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL_delay[1]; // rv 0
assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL_delay[2]; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0
assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET_delay; // rv 0
assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD_delay[0]; // rv 0
assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD_delay[1]; // rv 0
assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN_delay; // rv 0
assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN_delay; // rv 0
assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD_delay; // rv 0
assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET_delay; // rv 0
assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN_delay; // rv 0
assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL_delay[0]; // rv 0
assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL_delay[1]; // rv 0
assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET_delay; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0
assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET_delay; // rv 0
assign RXQPIEN_in = (RXQPIEN !== 1'bz) && RXQPIEN_delay; // rv 0
assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE_delay; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0
assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN_delay; // rv 0
assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN_delay; // rv 0
assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE_delay; // rv 1
assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL_delay[0]; // rv 0
assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL_delay[1]; // rv 0
assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY_delay; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0
assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK_delay; // rv 0
assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN_delay[0]; // rv 0
assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN_delay[10]; // rv 0
assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN_delay[11]; // rv 0
assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN_delay[12]; // rv 0
assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN_delay[13]; // rv 0
assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN_delay[14]; // rv 0
assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN_delay[15]; // rv 0
assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN_delay[16]; // rv 0
assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN_delay[17]; // rv 0
assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN_delay[18]; // rv 0
assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN_delay[19]; // rv 0
assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN_delay[1]; // rv 0
assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN_delay[2]; // rv 0
assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN_delay[3]; // rv 0
assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN_delay[4]; // rv 0
assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN_delay[5]; // rv 0
assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN_delay[6]; // rv 0
assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN_delay[7]; // rv 0
assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN_delay[8]; // rv 0
assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN_delay[9]; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0
assign TXBUFDIFFCTRL_in[0] = (TXBUFDIFFCTRL[0] !== 1'bz) && TXBUFDIFFCTRL_delay[0]; // rv 0
assign TXBUFDIFFCTRL_in[1] = (TXBUFDIFFCTRL[1] !== 1'bz) && TXBUFDIFFCTRL_delay[1]; // rv 0
assign TXBUFDIFFCTRL_in[2] = (TXBUFDIFFCTRL[2] !== 1'bz) && TXBUFDIFFCTRL_delay[2]; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0
assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD_delay[0]; // rv 0
assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD_delay[1]; // rv 0
assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD_delay[2]; // rv 0
assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD_delay[3]; // rv 0
assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD_delay[4]; // rv 0
assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD_delay[5]; // rv 0
assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD_delay[6]; // rv 0
assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD_delay[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0
assign TXDEEMPH_in = (TXDEEMPH !== 1'bz) && TXDEEMPH_delay; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0
assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL_delay[0]; // rv 0
assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL_delay[1]; // rv 0
assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL_delay[2]; // rv 0
assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL_delay[3]; // rv 0
assign TXDIFFPD_in = (TXDIFFPD !== 1'bz) && TXDIFFPD_delay; // rv 0
assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS_delay; // rv 0
assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN_delay; // rv 0
assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD_delay; // rv 0
assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN_delay; // rv 0
assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET_delay; // rv 0
assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN_delay; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0
assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK_delay; // rv 0
assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR_delay[0]; // rv 0
assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR_delay[1]; // rv 0
assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR_delay[2]; // rv 0
assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR_delay[3]; // rv 0
assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR_delay[4]; // rv 0
assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR_delay[5]; // rv 0
assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR_delay[6]; // rv 0
assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN_delay[0]; // rv 0
assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN_delay[1]; // rv 0
assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN_delay[2]; // rv 0
assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL_delay[0]; // rv 0
assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL_delay[1]; // rv 0
assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL_delay[2]; // rv 0
assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET_delay; // rv 0
assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE_delay; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0
assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN_delay; // rv 0
assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN_delay; // rv 0
assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD_delay; // rv 0
assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET_delay; // rv 0
assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK_delay; // rv 0
assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT_delay; // rv 0
assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN_delay; // rv 0
assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN_delay; // rv 0
assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN_delay; // rv 0
assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD_delay; // rv 0
assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL_delay; // rv 0
assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE_delay[0]; // rv 0
assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE_delay[1]; // rv 0
assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE_delay[2]; // rv 0
assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE_delay[3]; // rv 0
assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE_delay[4]; // rv 0
assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD_delay; // rv 0
assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL_delay[0]; // rv 0
assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL_delay[1]; // rv 0
assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET_delay; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0
assign TXPOSTCURSORINV_in = (TXPOSTCURSORINV !== 1'bz) && TXPOSTCURSORINV_delay; // rv 0
assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR_delay[0]; // rv 0
assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR_delay[1]; // rv 0
assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR_delay[2]; // rv 0
assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR_delay[3]; // rv 0
assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR_delay[4]; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0
assign TXPRECURSORINV_in = (TXPRECURSORINV !== 1'bz) && TXPRECURSORINV_delay; // rv 0
assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR_delay[0]; // rv 0
assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR_delay[1]; // rv 0
assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR_delay[2]; // rv 0
assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR_delay[3]; // rv 0
assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR_delay[4]; // rv 0
assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET_delay; // rv 0
assign TXQPIBIASEN_in = (TXQPIBIASEN !== 1'bz) && TXQPIBIASEN_delay; // rv 0
assign TXQPISTRONGPDOWN_in = (TXQPISTRONGPDOWN !== 1'bz) && TXQPISTRONGPDOWN_delay; // rv 0
assign TXQPIWEAKPUP_in = (TXQPIWEAKPUP !== 1'bz) && TXQPIWEAKPUP_delay; // rv 0
assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE_delay; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0
assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING_delay; // rv 0
assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN_delay; // rv 0
assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN_delay; // rv 0
assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE_delay; // rv 1
assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL_delay[0]; // rv 0
assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL_delay[1]; // rv 0
assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY_delay; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0
assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK_delay; // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin
$display("Error: [Unisim %s-276] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin
$display("Error: [Unisim %s-277] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-279] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-303] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin
$display("Error: [Unisim %s-381] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin
$display("Error: [Unisim %s-383] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin
$display("Error: [Unisim %s-485] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-495] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin
$display("Error: [Unisim %s-528] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127))) begin
$display("Error: [Unisim %s-538] SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63))) begin
$display("Error: [Unisim %s-539] SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63))) begin
$display("Error: [Unisim %s-544] SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63))) begin
$display("Error: [Unisim %s-545] SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-546] SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61))) begin
$display("Error: [Unisim %s-547] SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63))) begin
$display("Error: [Unisim %s-548] SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-549] SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-595] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_DEBUG_MODE_REG !== 1'b0) && (ACJTAG_DEBUG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-101] ACJTAG_DEBUG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_DEBUG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_MODE_REG !== 1'b0) && (ACJTAG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] ACJTAG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_RESET_REG !== 1'b0) && (ACJTAG_RESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] ACJTAG_RESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_RESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG0_REG < 16'h0000) || (ADAPT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-104] ADAPT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG1_REG < 16'h0000) || (ADAPT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-105] ADAPT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-128] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_ENABLE_REG < 10'b0000000000) || (ALIGN_COMMA_ENABLE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-129] ALIGN_COMMA_ENABLE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_COMMA_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4))) begin
$display("Error: [Unisim %s-130] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-131] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_MCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-132] ALIGN_MCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-133] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_PCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-134] ALIGN_PCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXOSCALRESET_REG !== 1'b0) && (A_RXOSCALRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-204] A_RXOSCALRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXOSCALRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXPROGDIVRESET_REG !== 1'b0) && (A_RXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-220] A_RXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_TXPROGDIVRESET_REG !== 1'b0) && (A_TXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-254] A_TXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_TXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin
$display("Error: [Unisim %s-258] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CDR_SWAP_MODE_EN_REG !== 1'b0) && (CDR_SWAP_MODE_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-259] CDR_SWAP_MODE_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, CDR_SWAP_MODE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-260] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14))) begin
$display("Error: [Unisim %s-261] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-262] CHAN_BOND_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-263] CHAN_BOND_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-264] CHAN_BOND_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-265] CHAN_BOND_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-266] CHAN_BOND_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-267] CHAN_BOND_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-268] CHAN_BOND_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-269] CHAN_BOND_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-270] CHAN_BOND_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-271] CHAN_BOND_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-272] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-273] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-274] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-275] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-278] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_1_REG < 10'b0000000000) || (CLK_COR_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-280] CLK_COR_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_2_REG < 10'b0000000000) || (CLK_COR_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-281] CLK_COR_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_3_REG < 10'b0000000000) || (CLK_COR_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-282] CLK_COR_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_4_REG < 10'b0000000000) || (CLK_COR_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-283] CLK_COR_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-284] CLK_COR_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_1_REG < 10'b0000000000) || (CLK_COR_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-285] CLK_COR_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_2_REG < 10'b0000000000) || (CLK_COR_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-286] CLK_COR_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_3_REG < 10'b0000000000) || (CLK_COR_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-287] CLK_COR_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_4_REG < 10'b0000000000) || (CLK_COR_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-288] CLK_COR_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-289] CLK_COR_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-290] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-291] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG0_REG < 16'h0000) || (CPLL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-292] CPLL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG1_REG < 16'h0000) || (CPLL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-293] CPLL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG2_REG < 16'h0000) || (CPLL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-294] CPLL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG3_REG < 6'h00) || (CPLL_CFG3_REG > 6'h3F))) begin
$display("Error: [Unisim %s-295] CPLL_CFG3 attribute is set to %h. Legal values for this attribute are 6'h00 to 6'h3F. Instance: %m", MODULE_NAME, CPLL_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5))) begin
$display("Error: [Unisim %s-297] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20))) begin
$display("Error: [Unisim %s-296] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG0_REG < 16'h0000) || (CPLL_INIT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-298] CPLL_INIT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG1_REG < 8'h00) || (CPLL_INIT_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-299] CPLL_INIT_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_LOCK_CFG_REG < 16'h0000) || (CPLL_LOCK_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-300] CPLL_LOCK_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_LOCK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-301] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_CTRL_REG < 2'b00) || (DDI_CTRL_REG > 2'b11))) begin
$display("Error: [Unisim %s-302] DDI_CTRL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, DDI_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-304] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-305] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin
$display("Error: [Unisim %s-306] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_D_X_REL_POS_REG !== 1'b0) && (DFE_D_X_REL_POS_REG !== 1'b1))) begin
$display("Error: [Unisim %s-307] DFE_D_X_REL_POS attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_D_X_REL_POS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_VCM_COMP_EN_REG !== 1'b0) && (DFE_VCM_COMP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-308] DFE_VCM_COMP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_VCM_COMP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG0_REG < 10'h000) || (DMONITOR_CFG0_REG > 10'h3FF))) begin
$display("Error: [Unisim %s-309] DMONITOR_CFG0 attribute is set to %h. Legal values for this attribute are 10'h000 to 10'h3FF. Instance: %m", MODULE_NAME, DMONITOR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG1_REG < 8'h00) || (DMONITOR_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-310] DMONITOR_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, DMONITOR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CLK_PHASE_SEL_REG !== 1'b0) && (ES_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-311] ES_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ES_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CONTROL_REG < 6'b000000) || (ES_CONTROL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-312] ES_CONTROL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, ES_CONTROL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-313] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-314] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_HORZ_OFFSET_REG < 12'h000) || (ES_HORZ_OFFSET_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-315] ES_HORZ_OFFSET attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, ES_HORZ_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PMA_CFG_REG < 10'b0000000000) || (ES_PMA_CFG_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-316] ES_PMA_CFG attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ES_PMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PRESCALE_REG < 5'b00000) || (ES_PRESCALE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-317] ES_PRESCALE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, ES_PRESCALE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER0_REG < 16'h0000) || (ES_QUALIFIER0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-318] ES_QUALIFIER0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER1_REG < 16'h0000) || (ES_QUALIFIER1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-319] ES_QUALIFIER1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER2_REG < 16'h0000) || (ES_QUALIFIER2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-320] ES_QUALIFIER2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER3_REG < 16'h0000) || (ES_QUALIFIER3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-321] ES_QUALIFIER3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER4_REG < 16'h0000) || (ES_QUALIFIER4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-322] ES_QUALIFIER4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK0_REG < 16'h0000) || (ES_QUAL_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-323] ES_QUAL_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK1_REG < 16'h0000) || (ES_QUAL_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-324] ES_QUAL_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK2_REG < 16'h0000) || (ES_QUAL_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-325] ES_QUAL_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK3_REG < 16'h0000) || (ES_QUAL_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-326] ES_QUAL_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK4_REG < 16'h0000) || (ES_QUAL_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-327] ES_QUAL_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK0_REG < 16'h0000) || (ES_SDATA_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-328] ES_SDATA_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK1_REG < 16'h0000) || (ES_SDATA_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-329] ES_SDATA_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK2_REG < 16'h0000) || (ES_SDATA_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-330] ES_SDATA_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK3_REG < 16'h0000) || (ES_SDATA_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-331] ES_SDATA_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK4_REG < 16'h0000) || (ES_SDATA_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-332] ES_SDATA_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EVODD_PHI_CFG_REG < 11'b00000000000) || (EVODD_PHI_CFG_REG > 11'b11111111111))) begin
$display("Error: [Unisim %s-333] EVODD_PHI_CFG attribute is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111. Instance: %m", MODULE_NAME, EVODD_PHI_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EYE_SCAN_SWAP_EN_REG !== 1'b0) && (EYE_SCAN_SWAP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-334] EYE_SCAN_SWAP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, EYE_SCAN_SWAP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_DESKEW_SEQ_ENABLE_REG < 4'b0000) || (FTS_DESKEW_SEQ_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-335] FTS_DESKEW_SEQ_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_DESKEW_SEQ_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_CFG_REG < 4'b0000) || (FTS_LANE_DESKEW_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-336] FTS_LANE_DESKEW_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-337] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GEARBOX_MODE_REG < 5'b00000) || (GEARBOX_MODE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-338] GEARBOX_MODE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, GEARBOX_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GM_BIAS_SELECT_REG !== 1'b0) && (GM_BIAS_SELECT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-341] GM_BIAS_SELECT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, GM_BIAS_SELECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOCAL_MASTER_REG !== 1'b0) && (LOCAL_MASTER_REG !== 1'b1))) begin
$display("Error: [Unisim %s-343] LOCAL_MASTER attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, LOCAL_MASTER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOBDIVCTL_REG < 2'b00) || (OOBDIVCTL_REG > 2'b11))) begin
$display("Error: [Unisim %s-344] OOBDIVCTL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, OOBDIVCTL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOB_PWRUP_REG !== 1'b0) && (OOB_PWRUP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-345] OOB_PWRUP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, OOB_PWRUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin
$display("Error: [Unisim %s-346] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_PIPE_RX_ELECIDLE_REG !== 1'b0) && (PCI3_PIPE_RX_ELECIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-347] PCI3_PIPE_RX_ELECIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_PIPE_RX_ELECIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ASYNC_EBUF_BYPASS_REG < 2'b00) || (PCI3_RX_ASYNC_EBUF_BYPASS_REG > 2'b11))) begin
$display("Error: [Unisim %s-348] PCI3_RX_ASYNC_EBUF_BYPASS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, PCI3_RX_ASYNC_EBUF_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-349] PCI3_RX_ELECIDLE_EI2_ENABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_EI2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_H2L_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-350] PCI3_RX_ELECIDLE_H2L_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_DISABLE_REG < 3'b000) || (PCI3_RX_ELECIDLE_H2L_DISABLE_REG > 3'b111))) begin
$display("Error: [Unisim %s-351] PCI3_RX_ELECIDLE_H2L_DISABLE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_HI_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_HI_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-352] PCI3_RX_ELECIDLE_HI_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_HI_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-353] PCI3_RX_ELECIDLE_LP4_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_LP4_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_FIFO_DISABLE_REG !== 1'b0) && (PCI3_RX_FIFO_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-354] PCI3_RX_FIFO_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_FIFO_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_BUFG_DIV_CTRL_REG < 16'h0000) || (PCIE_BUFG_DIV_CTRL_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-355] PCIE_BUFG_DIV_CTRL attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_BUFG_DIV_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_RXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-356] PCIE_RXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPMA_CFG_REG < 16'h0000) || (PCIE_RXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-357] PCIE_RXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_TXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-358] PCIE_TXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPMA_CFG_REG < 16'h0000) || (PCIE_TXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-359] PCIE_TXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-360] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD0_REG < 16'b0000000000000000) || (PCS_RSVD0_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-361] PCS_RSVD0 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, PCS_RSVD0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD1_REG < 3'b000) || (PCS_RSVD1_REG > 3'b111))) begin
$display("Error: [Unisim %s-362] PCS_RSVD1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCS_RSVD1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_FROM_P2_REG < 12'h000) || (PD_TRANS_TIME_FROM_P2_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-363] PD_TRANS_TIME_FROM_P2 attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_FROM_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_NONE_P2_REG < 8'h00) || (PD_TRANS_TIME_NONE_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-364] PD_TRANS_TIME_NONE_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_NONE_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_TO_P2_REG < 8'h00) || (PD_TRANS_TIME_TO_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-365] PD_TRANS_TIME_TO_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_TO_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN12_REG < 2'h0) || (PLL_SEL_MODE_GEN12_REG > 2'h3))) begin
$display("Error: [Unisim %s-366] PLL_SEL_MODE_GEN12 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN3_REG < 2'h0) || (PLL_SEL_MODE_GEN3_REG > 2'h3))) begin
$display("Error: [Unisim %s-367] PLL_SEL_MODE_GEN3 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PMA_RSV1_REG < 16'h0000) || (PMA_RSV1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-368] PMA_RSV1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PMA_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROCESS_PAR_REG < 3'b000) || (PROCESS_PAR_REG > 3'b111))) begin
$display("Error: [Unisim %s-369] PROCESS_PAR attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PROCESS_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RATE_SW_USE_DRP_REG !== 1'b0) && (RATE_SW_USE_DRP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-370] RATE_SW_USE_DRP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RATE_SW_USE_DRP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RESET_POWERSAVE_DISABLE_REG !== 1'b0) && (RESET_POWERSAVE_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-371] RESET_POWERSAVE_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RESET_POWERSAVE_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUFRESET_TIME_REG < 5'b00000) || (RXBUFRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-372] RXBUFRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXBUFRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST"))) begin
$display("Error: [Unisim %s-373] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_HI_CNT_REG < 4'b0000) || (RXBUF_EIDLE_HI_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-374] RXBUF_EIDLE_HI_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_HI_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_LO_CNT_REG < 4'b0000) || (RXBUF_EIDLE_LO_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-375] RXBUF_EIDLE_LO_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_LO_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-376] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-377] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-378] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-379] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-380] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-382] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRFREQRESET_TIME_REG < 5'b00000) || (RXCDRFREQRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-384] RXCDRFREQRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRFREQRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRPHRESET_TIME_REG < 5'b00000) || (RXCDRPHRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-385] RXCDRPHRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRPHRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_GEN3_REG < 16'h0000) || (RXCDR_CFG0_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-387] RXCDR_CFG0_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_REG < 16'h0000) || (RXCDR_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-386] RXCDR_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_GEN3_REG < 16'h0000) || (RXCDR_CFG1_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-389] RXCDR_CFG1_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_REG < 16'h0000) || (RXCDR_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-388] RXCDR_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_GEN3_REG < 16'h0000) || (RXCDR_CFG2_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-391] RXCDR_CFG2_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_REG < 16'h0000) || (RXCDR_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-390] RXCDR_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_GEN3_REG < 16'h0000) || (RXCDR_CFG3_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-393] RXCDR_CFG3_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_REG < 16'h0000) || (RXCDR_CFG3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-392] RXCDR_CFG3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_GEN3_REG < 16'h0000) || (RXCDR_CFG4_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-395] RXCDR_CFG4_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_REG < 16'h0000) || (RXCDR_CFG4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-394] RXCDR_CFG4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_GEN3_REG < 16'h0000) || (RXCDR_CFG5_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-397] RXCDR_CFG5_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_REG < 16'h0000) || (RXCDR_CFG5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-396] RXCDR_CFG5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-398] RXCDR_FR_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_FR_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_HOLD_DURING_EIDLE_REG !== 1'b0) && (RXCDR_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-399] RXCDR_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG0_REG < 16'h0000) || (RXCDR_LOCK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-400] RXCDR_LOCK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG1_REG < 16'h0000) || (RXCDR_LOCK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-401] RXCDR_LOCK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG2_REG < 16'h0000) || (RXCDR_LOCK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-402] RXCDR_LOCK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-403] RXCDR_PH_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_PH_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG0_REG < 16'h0000) || (RXCFOK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-404] RXCFOK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG1_REG < 16'h0000) || (RXCFOK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-405] RXCFOK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG2_REG < 16'h0000) || (RXCFOK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-406] RXCFOK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPMRESET_TIME_REG < 7'b0000000) || (RXDFELPMRESET_TIME_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-407] RXDFELPMRESET_TIME attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RXDFELPMRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG0_REG < 16'h0000) || (RXDFELPM_KL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-408] RXDFELPM_KL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG1_REG < 16'h0000) || (RXDFELPM_KL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-409] RXDFELPM_KL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG2_REG < 16'h0000) || (RXDFELPM_KL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-410] RXDFELPM_KL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG0_REG < 16'h0000) || (RXDFE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-411] RXDFE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG1_REG < 16'h0000) || (RXDFE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-412] RXDFE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG0_REG < 16'h0000) || (RXDFE_GC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-413] RXDFE_GC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG1_REG < 16'h0000) || (RXDFE_GC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-414] RXDFE_GC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG2_REG < 16'h0000) || (RXDFE_GC_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-415] RXDFE_GC_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG0_REG < 16'h0000) || (RXDFE_H2_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-416] RXDFE_H2_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG1_REG < 16'h0000) || (RXDFE_H2_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-417] RXDFE_H2_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG0_REG < 16'h0000) || (RXDFE_H3_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-418] RXDFE_H3_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG1_REG < 16'h0000) || (RXDFE_H3_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-419] RXDFE_H3_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG0_REG < 16'h0000) || (RXDFE_H4_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-420] RXDFE_H4_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG1_REG < 16'h0000) || (RXDFE_H4_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-421] RXDFE_H4_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG0_REG < 16'h0000) || (RXDFE_H5_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-422] RXDFE_H5_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG1_REG < 16'h0000) || (RXDFE_H5_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-423] RXDFE_H5_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG0_REG < 16'h0000) || (RXDFE_H6_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-424] RXDFE_H6_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG1_REG < 16'h0000) || (RXDFE_H6_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-425] RXDFE_H6_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG0_REG < 16'h0000) || (RXDFE_H7_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-426] RXDFE_H7_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG1_REG < 16'h0000) || (RXDFE_H7_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-427] RXDFE_H7_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG0_REG < 16'h0000) || (RXDFE_H8_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-428] RXDFE_H8_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG1_REG < 16'h0000) || (RXDFE_H8_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-429] RXDFE_H8_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG0_REG < 16'h0000) || (RXDFE_H9_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-430] RXDFE_H9_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG1_REG < 16'h0000) || (RXDFE_H9_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-431] RXDFE_H9_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG0_REG < 16'h0000) || (RXDFE_HA_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-432] RXDFE_HA_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG1_REG < 16'h0000) || (RXDFE_HA_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-433] RXDFE_HA_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG0_REG < 16'h0000) || (RXDFE_HB_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-434] RXDFE_HB_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG1_REG < 16'h0000) || (RXDFE_HB_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-435] RXDFE_HB_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG0_REG < 16'h0000) || (RXDFE_HC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-436] RXDFE_HC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG1_REG < 16'h0000) || (RXDFE_HC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-437] RXDFE_HC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG0_REG < 16'h0000) || (RXDFE_HD_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-438] RXDFE_HD_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG1_REG < 16'h0000) || (RXDFE_HD_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-439] RXDFE_HD_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG0_REG < 16'h0000) || (RXDFE_HE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-440] RXDFE_HE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG1_REG < 16'h0000) || (RXDFE_HE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-441] RXDFE_HE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG0_REG < 16'h0000) || (RXDFE_HF_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-442] RXDFE_HF_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG1_REG < 16'h0000) || (RXDFE_HF_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-443] RXDFE_HF_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG0_REG < 16'h0000) || (RXDFE_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-444] RXDFE_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG1_REG < 16'h0000) || (RXDFE_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-445] RXDFE_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG0_REG < 16'h0000) || (RXDFE_UT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-446] RXDFE_UT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG1_REG < 16'h0000) || (RXDFE_UT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-447] RXDFE_UT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG0_REG < 16'h0000) || (RXDFE_VP_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-448] RXDFE_VP_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG1_REG < 16'h0000) || (RXDFE_VP_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-449] RXDFE_VP_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_CFG_REG < 16'h0000) || (RXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-450] RXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_LCFG_REG < 16'h0000) || (RXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-451] RXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXELECIDLE_CFG_REG != "Sigcfg_4") &&
(RXELECIDLE_CFG_REG != "Sigcfg_1") &&
(RXELECIDLE_CFG_REG != "Sigcfg_2") &&
(RXELECIDLE_CFG_REG != "Sigcfg_3") &&
(RXELECIDLE_CFG_REG != "Sigcfg_6") &&
(RXELECIDLE_CFG_REG != "Sigcfg_8") &&
(RXELECIDLE_CFG_REG != "Sigcfg_12") &&
(RXELECIDLE_CFG_REG != "Sigcfg_16"))) begin
$display("Error: [Unisim %s-452] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are Sigcfg_4, Sigcfg_1, Sigcfg_2, Sigcfg_3, Sigcfg_6, Sigcfg_8, Sigcfg_12 or Sigcfg_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin
$display("Error: [Unisim %s-453] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-454] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXISCANRESET_TIME_REG < 5'b00000) || (RXISCANRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-455] RXISCANRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXISCANRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_CFG_REG < 16'h0000) || (RXLPM_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-456] RXLPM_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_GC_CFG_REG < 16'h0000) || (RXLPM_GC_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-457] RXLPM_GC_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_GC_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG0_REG < 16'h0000) || (RXLPM_KH_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-458] RXLPM_KH_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG1_REG < 16'h0000) || (RXLPM_KH_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-459] RXLPM_KH_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG0_REG < 16'h0000) || (RXLPM_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-460] RXLPM_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG1_REG < 16'h0000) || (RXLPM_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-461] RXLPM_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CFG_REG < 9'b000000000) || (RXOOB_CFG_REG > 9'b111111111))) begin
$display("Error: [Unisim %s-462] RXOOB_CFG attribute is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111. Instance: %m", MODULE_NAME, RXOOB_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC"))) begin
$display("Error: [Unisim %s-463] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOSCALRESET_TIME_REG < 5'b00000) || (RXOSCALRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-464] RXOSCALRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXOSCALRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-465] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, RXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPCSRESET_TIME_REG < 5'b00000) || (RXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-466] RXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHBEACON_CFG_REG < 16'h0000) || (RXPHBEACON_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-467] RXPHBEACON_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHBEACON_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHDLY_CFG_REG < 16'h0000) || (RXPHDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-468] RXPHDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSAMP_CFG_REG < 16'h0000) || (RXPHSAMP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-469] RXPHSAMP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSAMP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSLIP_CFG_REG < 16'h0000) || (RXPHSLIP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-470] RXPHSLIP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSLIP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPH_MONITOR_SEL_REG < 5'b00000) || (RXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-471] RXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG0_REG < 2'b00) || (RXPI_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-472] RXPI_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG1_REG < 2'b00) || (RXPI_CFG1_REG > 2'b11))) begin
$display("Error: [Unisim %s-473] RXPI_CFG1 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG2_REG < 2'b00) || (RXPI_CFG2_REG > 2'b11))) begin
$display("Error: [Unisim %s-474] RXPI_CFG2 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG3_REG < 2'b00) || (RXPI_CFG3_REG > 2'b11))) begin
$display("Error: [Unisim %s-475] RXPI_CFG3 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG4_REG !== 1'b0) && (RXPI_CFG4_REG !== 1'b1))) begin
$display("Error: [Unisim %s-476] RXPI_CFG4 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG5_REG !== 1'b0) && (RXPI_CFG5_REG !== 1'b1))) begin
$display("Error: [Unisim %s-477] RXPI_CFG5 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG6_REG < 3'b000) || (RXPI_CFG6_REG > 3'b111))) begin
$display("Error: [Unisim %s-478] RXPI_CFG6 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RXPI_CFG6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_LPM_REG !== 1'b0) && (RXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-479] RXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_VREFSEL_REG !== 1'b0) && (RXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-480] RXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN"))) begin
$display("Error: [Unisim %s-482] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMARESET_TIME_REG < 5'b00000) || (RXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-483] RXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_ERR_LOOPBACK_REG !== 1'b0) && (RXPRBS_ERR_LOOPBACK_REG !== 1'b1))) begin
$display("Error: [Unisim %s-484] RXPRBS_ERR_LOOPBACK attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPRBS_ERR_LOOPBACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15))) begin
$display("Error: [Unisim %s-486] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA"))) begin
$display("Error: [Unisim %s-487] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_MULTILANE_REG !== 1'b0) && (RXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-488] RXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_OVRD_REG !== 1'b0) && (RXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-489] RXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_SKIP_DA_REG !== 1'b0) && (RXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-490] RXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_AFE_CM_EN_REG !== 1'b0) && (RX_AFE_CM_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-491] RX_AFE_CM_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_AFE_CM_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BIAS_CFG0_REG < 16'h0000) || (RX_BIAS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-492] RX_BIAS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RX_BIAS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BUFFER_CFG_REG < 6'b000000) || (RX_BUFFER_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-493] RX_BUFFER_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_BUFFER_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CAPFF_SARC_ENB_REG !== 1'b0) && (RX_CAPFF_SARC_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-494] RX_CAPFF_SARC_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CAPFF_SARC_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLKMUX_EN_REG !== 1'b0) && (RX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-496] RX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK_SLIP_OVRD_REG < 5'b00000) || (RX_CLK_SLIP_OVRD_REG > 5'b11111))) begin
$display("Error: [Unisim %s-497] RX_CLK_SLIP_OVRD attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_CLK_SLIP_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_CFG_REG < 4'b0000) || (RX_CM_BUF_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-498] RX_CM_BUF_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_CM_BUF_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_PD_REG !== 1'b0) && (RX_CM_BUF_PD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-499] RX_CM_BUF_PD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CM_BUF_PD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_SEL_REG < 2'b00) || (RX_CM_SEL_REG > 2'b11))) begin
$display("Error: [Unisim %s-500] RX_CM_SEL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_TRIM_REG < 4'b0000) || (RX_CM_TRIM_REG > 4'b1111))) begin
$display("Error: [Unisim %s-501] RX_CM_TRIM attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CTLE3_LPF_REG < 8'b00000000) || (RX_CTLE3_LPF_REG > 8'b11111111))) begin
$display("Error: [Unisim %s-502] RX_CTLE3_LPF attribute is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111. Instance: %m", MODULE_NAME, RX_CTLE3_LPF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-503] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DDI_SEL_REG < 6'b000000) || (RX_DDI_SEL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-504] RX_DDI_SEL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_DDI_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-505] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG0_REG < 4'b0000) || (RX_DFELPM_CFG0_REG > 4'b1111))) begin
$display("Error: [Unisim %s-506] RX_DFELPM_CFG0 attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG1_REG !== 1'b0) && (RX_DFELPM_CFG1_REG !== 1'b1))) begin
$display("Error: [Unisim %s-507] RX_DFELPM_CFG1 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b0) && (RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-508] RX_DFELPM_KLKH_AGC_STUP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_KLKH_AGC_STUP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG0_REG < 2'b00) || (RX_DFE_AGC_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-509] RX_DFE_AGC_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG1_REG < 3'b000) || (RX_DFE_AGC_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-510] RX_DFE_AGC_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KH_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-511] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KH_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-512] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KL_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-513] RX_DFE_KL_LPM_KL_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KL_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-514] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-515] RX_DFE_LPM_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFE_LPM_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin
$display("Error: [Unisim %s-516] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DIVRESET_TIME_REG < 5'b00000) || (RX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-517] RX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EN_HI_LR_REG !== 1'b0) && (RX_EN_HI_LR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-518] RX_EN_HI_LR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EN_HI_LR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_CODE_REG < 7'b0000000) || (RX_EYESCAN_VS_CODE_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-519] RX_EYESCAN_VS_CODE attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_CODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_NEG_DIR_REG !== 1'b0) && (RX_EYESCAN_VS_NEG_DIR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-520] RX_EYESCAN_VS_NEG_DIR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_NEG_DIR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_RANGE_REG < 2'b00) || (RX_EYESCAN_VS_RANGE_REG > 2'b11))) begin
$display("Error: [Unisim %s-521] RX_EYESCAN_VS_RANGE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_RANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_UT_SIGN_REG !== 1'b0) && (RX_EYESCAN_VS_UT_SIGN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-522] RX_EYESCAN_VS_UT_SIGN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_UT_SIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (RX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-523] RX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-524] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PMA_POWER_SAVE_REG !== 1'b0) && (RX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-525] RX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SAMPLE_PERIOD_REG < 3'b000) || (RX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-527] RX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_DFETAPREP_EN_REG !== 1'b0) && (RX_SUM_DFETAPREP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-529] RX_SUM_DFETAPREP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_DFETAPREP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_IREF_TUNE_REG < 4'b0000) || (RX_SUM_IREF_TUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-530] RX_SUM_IREF_TUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_IREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_RES_CTRL_REG < 2'b00) || (RX_SUM_RES_CTRL_REG > 2'b11))) begin
$display("Error: [Unisim %s-531] RX_SUM_RES_CTRL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_SUM_RES_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCMTUNE_REG < 4'b0000) || (RX_SUM_VCMTUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-532] RX_SUM_VCMTUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_VCMTUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCM_OVWR_REG !== 1'b0) && (RX_SUM_VCM_OVWR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-533] RX_SUM_VCM_OVWR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_VCM_OVWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VREF_TUNE_REG < 3'b000) || (RX_SUM_VREF_TUNE_REG > 3'b111))) begin
$display("Error: [Unisim %s-534] RX_SUM_VREF_TUNE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SUM_VREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_TUNE_AFE_OS_REG < 2'b00) || (RX_TUNE_AFE_OS_REG > 2'b11))) begin
$display("Error: [Unisim %s-535] RX_TUNE_AFE_OS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_TUNE_AFE_OS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_WIDEMODE_CDR_REG !== 1'b0) && (RX_WIDEMODE_CDR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-536] RX_WIDEMODE_CDR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_WIDEMODE_CDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR"))) begin
$display("Error: [Unisim %s-537] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_SEQ_LEN_REG < 4'b0000) || (SATA_BURST_SEQ_LEN_REG > 4'b1111))) begin
$display("Error: [Unisim %s-540] SATA_BURST_SEQ_LEN attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, SATA_BURST_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_VAL_REG < 3'b000) || (SATA_BURST_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-541] SATA_BURST_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_BURST_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ"))) begin
$display("Error: [Unisim %s-542] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_EIDLE_VAL_REG < 3'b000) || (SATA_EIDLE_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-543] SATA_EIDLE_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_EIDLE_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE"))) begin
$display("Error: [Unisim %s-550] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-551] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE"))) begin
$display("Error: [Unisim %s-552] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b0) && (SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-553] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != "Ver_1") &&
(SIM_VERSION_REG != "Ver_1_1") &&
(SIM_VERSION_REG != "Ver_2"))) begin
$display("Error: [Unisim %s-554] SIM_VERSION attribute is set to %s. Legal values for this attribute are Ver_1, Ver_1_1 or Ver_2. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TAPDLY_SET_TX_REG < 2'h0) || (TAPDLY_SET_TX_REG > 2'h3))) begin
$display("Error: [Unisim %s-555] TAPDLY_SET_TX attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, TAPDLY_SET_TX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TEMPERATUR_PAR_REG < 4'b0000) || (TEMPERATUR_PAR_REG > 4'b1111))) begin
$display("Error: [Unisim %s-556] TEMPERATUR_PAR attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TEMPERATUR_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_CFG_REG < 15'b000000000000000) || (TERM_RCAL_CFG_REG > 15'b111111111111111))) begin
$display("Error: [Unisim %s-557] TERM_RCAL_CFG attribute is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111. Instance: %m", MODULE_NAME, TERM_RCAL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_OVRD_REG < 3'b000) || (TERM_RCAL_OVRD_REG > 3'b111))) begin
$display("Error: [Unisim %s-558] TERM_RCAL_OVRD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TERM_RCAL_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TRANS_TIME_RATE_REG < 8'h00) || (TRANS_TIME_RATE_REG > 8'hFF))) begin
$display("Error: [Unisim %s-559] TRANS_TIME_RATE attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TRANS_TIME_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV0_REG < 8'h00) || (TST_RSV0_REG > 8'hFF))) begin
$display("Error: [Unisim %s-560] TST_RSV0 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV1_REG < 8'h00) || (TST_RSV1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-561] TST_RSV1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-562] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-563] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_CFG_REG < 16'h0000) || (TXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-564] TXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_LCFG_REG < 16'h0000) || (TXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-565] TXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDRVBIAS_N_REG < 4'b0000) || (TXDRVBIAS_N_REG > 4'b1111))) begin
$display("Error: [Unisim %s-566] TXDRVBIAS_N attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TXDRVBIAS_N_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDRVBIAS_P_REG < 4'b0000) || (TXDRVBIAS_P_REG > 4'b1111))) begin
$display("Error: [Unisim %s-567] TXDRVBIAS_P attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TXDRVBIAS_P_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH"))) begin
$display("Error: [Unisim %s-568] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin
$display("Error: [Unisim %s-569] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-570] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-572] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, TXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPCSRESET_TIME_REG < 5'b00000) || (TXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-573] TXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG0_REG < 16'h0000) || (TXPHDLY_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-574] TXPHDLY_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG1_REG < 16'h0000) || (TXPHDLY_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-575] TXPHDLY_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_CFG_REG < 16'h0000) || (TXPH_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-576] TXPH_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPH_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_MONITOR_SEL_REG < 5'b00000) || (TXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-577] TXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG0_REG < 2'b00) || (TXPI_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-578] TXPI_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG1_REG < 2'b00) || (TXPI_CFG1_REG > 2'b11))) begin
$display("Error: [Unisim %s-579] TXPI_CFG1 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG2_REG < 2'b00) || (TXPI_CFG2_REG > 2'b11))) begin
$display("Error: [Unisim %s-580] TXPI_CFG2 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG3_REG !== 1'b0) && (TXPI_CFG3_REG !== 1'b1))) begin
$display("Error: [Unisim %s-581] TXPI_CFG3 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG4_REG !== 1'b0) && (TXPI_CFG4_REG !== 1'b1))) begin
$display("Error: [Unisim %s-582] TXPI_CFG4 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG5_REG < 3'b000) || (TXPI_CFG5_REG > 3'b111))) begin
$display("Error: [Unisim %s-583] TXPI_CFG5 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_GRAY_SEL_REG !== 1'b0) && (TXPI_GRAY_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-584] TXPI_GRAY_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_GRAY_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_INVSTROBE_SEL_REG !== 1'b0) && (TXPI_INVSTROBE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-585] TXPI_INVSTROBE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_INVSTROBE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_LPM_REG !== 1'b0) && (TXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-586] TXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin
$display("Error: [Unisim %s-587] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPM_CFG_REG < 8'b00000000) || (TXPI_PPM_CFG_REG > 8'b11111111))) begin
$display("Error: [Unisim %s-588] TXPI_PPM_CFG attribute is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111. Instance: %m", MODULE_NAME, TXPI_PPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_SYNFREQ_PPM_REG < 3'b000) || (TXPI_SYNFREQ_PPM_REG > 3'b111))) begin
$display("Error: [Unisim %s-589] TXPI_SYNFREQ_PPM attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_SYNFREQ_PPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_VREFSEL_REG !== 1'b0) && (TXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-590] TXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPMARESET_TIME_REG < 5'b00000) || (TXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-591] TXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_MULTILANE_REG !== 1'b0) && (TXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-592] TXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_OVRD_REG !== 1'b0) && (TXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-593] TXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_SKIP_DA_REG !== 1'b0) && (TXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-594] TXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLKMUX_EN_REG !== 1'b0) && (TX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-596] TX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-597] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_CFG_REG < 6'b000000) || (TX_DCD_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-598] TX_DCD_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DCD_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_EN_REG !== 1'b0) && (TX_DCD_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-599] TX_DCD_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_DCD_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH0_REG < 6'b000000) || (TX_DEEMPH0_REG > 6'b111111))) begin
$display("Error: [Unisim %s-600] TX_DEEMPH0 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH1_REG < 6'b000000) || (TX_DEEMPH1_REG > 6'b111111))) begin
$display("Error: [Unisim %s-601] TX_DEEMPH1 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DIVRESET_TIME_REG < 5'b00000) || (TX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-602] TX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin
$display("Error: [Unisim %s-603] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_ASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_ASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-604] TX_EIDLE_ASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_ASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_DEASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_DEASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-605] TX_EIDLE_DEASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_DEASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EML_PHI_TUNE_REG !== 1'b0) && (TX_EML_PHI_TUNE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-606] TX_EML_PHI_TUNE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_EML_PHI_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (TX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-607] TX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_IDLE_DATA_ZERO_REG !== 1'b0) && (TX_IDLE_DATA_ZERO_REG !== 1'b1))) begin
$display("Error: [Unisim %s-608] TX_IDLE_DATA_ZERO attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_IDLE_DATA_ZERO_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-609] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-610] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MAINCURSOR_SEL_REG !== 1'b0) && (TX_MAINCURSOR_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-611] TX_MAINCURSOR_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_MAINCURSOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_0_REG < 7'b0000000) || (TX_MARGIN_FULL_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-612] TX_MARGIN_FULL_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_1_REG < 7'b0000000) || (TX_MARGIN_FULL_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-613] TX_MARGIN_FULL_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_2_REG < 7'b0000000) || (TX_MARGIN_FULL_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-614] TX_MARGIN_FULL_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_3_REG < 7'b0000000) || (TX_MARGIN_FULL_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-615] TX_MARGIN_FULL_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_4_REG < 7'b0000000) || (TX_MARGIN_FULL_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-616] TX_MARGIN_FULL_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_0_REG < 7'b0000000) || (TX_MARGIN_LOW_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-617] TX_MARGIN_LOW_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_1_REG < 7'b0000000) || (TX_MARGIN_LOW_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-618] TX_MARGIN_LOW_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_2_REG < 7'b0000000) || (TX_MARGIN_LOW_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-619] TX_MARGIN_LOW_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_3_REG < 7'b0000000) || (TX_MARGIN_LOW_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-620] TX_MARGIN_LOW_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_4_REG < 7'b0000000) || (TX_MARGIN_LOW_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-621] TX_MARGIN_LOW_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MODE_SEL_REG < 3'b000) || (TX_MODE_SEL_REG > 3'b111))) begin
$display("Error: [Unisim %s-622] TX_MODE_SEL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_MODE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMADATA_OPT_REG !== 1'b0) && (TX_PMADATA_OPT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-623] TX_PMADATA_OPT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMADATA_OPT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMA_POWER_SAVE_REG !== 1'b0) && (TX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-624] TX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI"))) begin
$display("Error: [Unisim %s-625] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_QPI_STATUS_EN_REG !== 1'b0) && (TX_QPI_STATUS_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-627] TX_QPI_STATUS_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_QPI_STATUS_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_CFG_REG < 14'h0000) || (TX_RXDETECT_CFG_REG > 14'h3FFF))) begin
$display("Error: [Unisim %s-628] TX_RXDETECT_CFG attribute is set to %h. Legal values for this attribute are 14'h0000 to 14'h3FFF. Instance: %m", MODULE_NAME, TX_RXDETECT_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_REF_REG < 3'b000) || (TX_RXDETECT_REF_REG > 3'b111))) begin
$display("Error: [Unisim %s-629] TX_RXDETECT_REF attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SAMPLE_PERIOD_REG < 3'b000) || (TX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-630] TX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SARC_LPBK_ENB_REG !== 1'b0) && (TX_SARC_LPBK_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-631] TX_SARC_LPBK_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_SARC_LPBK_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR"))) begin
$display("Error: [Unisim %s-636] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_PCS_CLK_PHASE_SEL_REG !== 1'b0) && (USE_PCS_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-637] USE_PCS_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, USE_PCS_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WB_MODE_REG < 2'b00) || (WB_MODE_REG > 2'b11))) begin
$display("Error: [Unisim %s-638] WB_MODE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, WB_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_CFG_REG != 4.0) &&
(RX_PROGDIV_CFG_REG != 5.0) &&
(RX_PROGDIV_CFG_REG != 8.0) &&
(RX_PROGDIV_CFG_REG != 10.0) &&
(RX_PROGDIV_CFG_REG != 16.0) &&
(RX_PROGDIV_CFG_REG != 16.5) &&
(RX_PROGDIV_CFG_REG != 20.0) &&
(RX_PROGDIV_CFG_REG != 32.0) &&
(RX_PROGDIV_CFG_REG != 33.0) &&
(RX_PROGDIV_CFG_REG != 40.0) &&
(RX_PROGDIV_CFG_REG != 64.0) &&
(RX_PROGDIV_CFG_REG != 66.0))) begin
$display("Error: [Unisim %s-526] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0 or 66.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_CFG_REG != 4.0) &&
(TX_PROGDIV_CFG_REG != 5.0) &&
(TX_PROGDIV_CFG_REG != 8.0) &&
(TX_PROGDIV_CFG_REG != 10.0) &&
(TX_PROGDIV_CFG_REG != 16.0) &&
(TX_PROGDIV_CFG_REG != 16.5) &&
(TX_PROGDIV_CFG_REG != 20.0) &&
(TX_PROGDIV_CFG_REG != 32.0) &&
(TX_PROGDIV_CFG_REG != 33.0) &&
(TX_PROGDIV_CFG_REG != 40.0) &&
(TX_PROGDIV_CFG_REG != 64.0) &&
(TX_PROGDIV_CFG_REG != 66.0))) begin
$display("Error: [Unisim %s-626] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0 or 66.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 12'b111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTHE3_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG),
.SIM_VERSION (SIM_VERSION_REG)
) SIP_GTHE3_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_EYESCAN (AEN_EYESCAN_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_QPI (AEN_QPI_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.A_AFECFOKEN (A_AFECFOKEN_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG),
.A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG),
.A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG),
.A_DFECFOKHOLD (A_DFECFOKHOLD_REG),
.A_DFECFOKOVREN (A_DFECFOKOVREN_REG),
.A_EYESCANMODE (A_EYESCANMODE_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_LPMGCHOLD (A_LPMGCHOLD_REG),
.A_LPMGCOVREN (A_LPMGCOVREN_REG),
.A_LPMOSHOLD (A_LPMOSHOLD_REG),
.A_LPMOSOVREN (A_LPMOSOVREN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEVSEN (A_RXDFEVSEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPOSTCURSORINV (A_TXPOSTCURSORINV_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPRECURSORINV (A_TXPRECURSORINV_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXQPIBIASEN (A_TXQPIBIASEN_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG),
.DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PMA_CFG (ES_PMA_CFG_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.EVODD_PHI_CFG (EVODD_PHI_CFG_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GM_BIAS_SELECT (GM_BIAS_SELECT_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PCS_RSVD1 (PCS_RSVD1_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG),
.PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG),
.PMA_RSV1 (PMA_RSV1_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_CFG0 (RXPI_CFG0_REG),
.RXPI_CFG1 (RXPI_CFG1_REG),
.RXPI_CFG2 (RXPI_CFG2_REG),
.RXPI_CFG3 (RXPI_CFG3_REG),
.RXPI_CFG4 (RXPI_CFG4_REG),
.RXPI_CFG5 (RXPI_CFG5_REG),
.RXPI_CFG6 (RXPI_CFG6_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPLL_SEL (RXPLL_SEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE3_LPF (RX_CTLE3_LPF_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.SAS_MAX_COM (SAS_MAX_COM_REG),
.SAS_MIN_COM (SAS_MIN_COM_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SATA_MAX_BURST (SATA_MAX_BURST_REG),
.SATA_MAX_INIT (SATA_MAX_INIT_REG),
.SATA_MAX_WAKE (SATA_MAX_WAKE_REG),
.SATA_MIN_BURST (SATA_MIN_BURST_REG),
.SATA_MIN_INIT (SATA_MIN_INIT_REG),
.SATA_MIN_WAKE (SATA_MIN_WAKE_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATUR_PAR (TEMPERATUR_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXDRVBIAS_N (TXDRVBIAS_N_REG),
.TXDRVBIAS_P (TXDRVBIAS_P_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCD_CFG (TX_DCD_CFG_REG),
.TX_DCD_EN (TX_DCD_EN_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_MODE_SEL (TX_MODE_SEL_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.WB_MODE (WB_MODE_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.DMONITOROUT (DMONITOROUT_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTHTXN (GTHTXN_out),
.GTHTXP (GTHTXP_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXQPISENN (RXQPISENN_out),
.RXQPISENP (RXQPISENP_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXQPISENN (TXQPISENN_out),
.TXQPISENP (TXQPISENP_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.EVODDPHICALDONE (EVODDPHICALDONE_in),
.EVODDPHICALSTART (EVODDPHICALSTART_in),
.EVODDPHIDRDEN (EVODDPHIDRDEN_in),
.EVODDPHIDWREN (EVODDPHIDWREN_in),
.EVODDPHIXRDEN (EVODDPHIXRDEN_in),
.EVODDPHIXWREN (EVODDPHIXWREN_in),
.EYESCANMODE (EYESCANMODE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.GTGREFCLK (GTGREFCLK_in),
.GTHRXN (GTHRXN_in),
.GTHRXP (GTHRXP_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRESETSEL (GTRESETSEL_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.LOOPBACK (LOOPBACK_in),
.LPBKRXTXSEREN (LPBKRXTXSEREN_in),
.LPBKTXRXSEREN (LPBKTXRXSEREN_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PCSRSVDIN2 (PCSRSVDIN2_in),
.PMARSVDIN (PMARSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RSTCLKENTX (RSTCLKENTX_in),
.RX8B10BEN (RX8B10BEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCDRRESETRSV (RXCDRRESETRSV_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDFEAGCCTRL (RXDFEAGCCTRL_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEVSEN (RXDFEVSEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSINTCFG (RXOSINTCFG_in),
.RXOSINTEN (RXOSINTEN_in),
.RXOSINTHOLD (RXOSINTHOLD_in),
.RXOSINTOVRDEN (RXOSINTOVRDEN_in),
.RXOSINTSTROBE (RXOSINTSTROBE_in),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXQPIEN (RXQPIEN_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDIFFPD (TXDIFFPD_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPOSTCURSORINV (TXPOSTCURSORINV_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPRECURSORINV (TXPRECURSORINV_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXQPIBIASEN (TXQPIBIASEN_in),
.TXQPISTRONGPDOWN (TXQPISTRONGPDOWN_in),
.TXQPIWEAKPUP (TXQPIWEAKPUP_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
specify
(DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[0]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[10]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[11]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[12]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[13]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[14]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[15]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[1]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[2]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[3]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[4]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[5]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[6]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[7]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[8]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
(GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[0]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[1]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[2]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[3]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => PHYSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANBONDSEQ) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMINITDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMMADET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMSASDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMWAKEDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[10]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[11]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[12]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[13]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[14]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[15]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[16]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[17]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[18]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[19]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[20]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[21]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[22]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[23]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[24]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[25]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[26]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[27]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[28]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[29]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[30]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[31]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[32]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[33]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[34]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[35]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[36]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[37]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[38]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[39]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[40]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[41]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[42]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[43]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[44]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[45]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[46]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[47]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[48]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[49]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[50]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[51]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[52]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[53]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[54]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[55]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[56]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[57]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[58]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[59]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[60]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[61]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[62]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[63]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[8]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[9]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSERR) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSLOCKED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRATEDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIDERDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPPMARDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXVALID) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXCOMFINISH) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRATEDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRESETDONE) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:03:00 09/16/2014
// Design Name:
// Module Name: segClkDevider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module segClkDevider(
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 10000;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
module ad_csc_1 (
// data
clk,
sync,
data,
// constants
C1,
C2,
C3,
C4,
// sync is delay matched
csc_sync_1,
csc_data_1);
// parameters
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data
input clk;
input [DW:0] sync;
input [23:0] data;
// constants
input [16:0] C1;
input [16:0] C2;
input [16:0] C3;
input [24:0] C4;
// sync is delay matched
output [DW:0] csc_sync_1;
output [ 7:0] csc_data_1;
// internal wires
wire [24:0] data_1_m_s;
wire [24:0] data_2_m_s;
wire [24:0] data_3_m_s;
wire [DW:0] sync_3_m_s;
// c1*R
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
.clk (clk),
.data_a (C1),
.data_b (data[23:16]),
.data_p (data_1_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c2*G
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
.clk (clk),
.data_a (C2),
.data_b (data[15:8]),
.data_p (data_2_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c3*B
ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
.clk (clk),
.data_a (C3),
.data_b (data[7:0]),
.data_p (data_3_m_s),
.ddata_in (sync),
.ddata_out (sync_3_m_s));
// sum + c4
ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
.clk (clk),
.data_1 (data_1_m_s),
.data_2 (data_2_m_s),
.data_3 (data_3_m_s),
.data_4 (C4),
.data_p (csc_data_1),
.ddata_in (sync_3_m_s),
.ddata_out (csc_sync_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module ampDrive (
input clk,
input feedfwd_en,
input opGate,
input opMode, //0 = sample-by-sample, 1 = constant DAC, 2 = Pulse mean removal //
input [4:0] Ldelay,
input signed [12:0] constDac_val,
input signed [15:0] din,
input DACclkPhase,
input signed [6:0] IIRtapWeight,
output reg oflowDetect = 1'b0,
//output reg signed [12:0] dout = 13'd0,
//output reg DAC_en = 1'b0
(* IOB = "true" *) output reg signed [12:0] dout = 13'd0, //For the sake of Iverilog!!
(* IOB = "true" *) output reg DAC_en = 1'b0 //ditto !
//(* IOB = "true" *) output reg signed [12:0] dout_copy = 13'd0, //For the sake of Iverilog!!
//(* IOB = "true" *) output reg DAC_en_copy = 1'b0 //ditto !
);
//`include "bits_to_fit.v"
//`define COMBINE // NB: Introduces a two-cycle delay
`define SUM_OUTPUT_SMPLS // NB: Introduces a one-cycle delay, or zero-cyle, see in macro-defined code below. PRESENTY ZERO-CYCLE!!
//parameter offset_delay = 4'd8; //minimum latency 5 cycles with respect to store_strb in FF modules (2 from LUT & mult, 1 gain, 2 Ldelay)
//parameter OFFSET_DELAY = 4'd7; //with respect to store_strb at Ldelay entrance (5 from "loop' module, 2 from gain, 1 from RAM_strobes, -2 from internal)
parameter OFFSET_DELAY = 4'd8; //with respect to store_strb at Ldelay entrance (5 from "loop' module, 2 from gain, 1 from RAM_strobes, -2 from internal)
// GENERIC PARAMETER
//parameter OFFSET_DELAY = 4'd10; //with respect to store_strb at Ldelay entrance (5 from "loop' module, 2 from gain, 1 from RAM_strobes, -2 from internal)
// NB: now includes 2 cycle delay from the Combiner Module
//7 is to bring the latency down by one cycle - should be 5 from 'loop' + 2 from gain + 1 from P1_strobe (then minus 1 from the register on opgate)
// gain stage, delay, combi o/p block, o/p filtering, decimate and put out.
(* shreg_extract = "no" *) reg signed [15:0] amp_drive = 16'sd0;
wire signed [15:0] amp_drive_del;
wire opGateDel;
//wire [5:0] strbDel;
reg [5:0] strbDel = 6'd0;
reg delayBypass_a = 1'b1, delayBypass_b = 1'b1;
(* shreg_extract = "no" *) reg [4:0] Ldelay_b = 5'd2;
always @(posedge clk) begin
Ldelay_b <= Ldelay;
(* full_case, parallel_case *)
case (Ldelay)
5'd0: begin
delayBypass_a <= 1'b1;
delayBypass_b <= 1'b0;
strbDel <= Ldelay + (OFFSET_DELAY - 4'd2);
end
5'd1: begin
delayBypass_a <= 1'b0;
delayBypass_b <= 1'b1;
strbDel <= Ldelay + (OFFSET_DELAY - 4'd1);
end
default: begin
delayBypass_a <= 1'b0;
delayBypass_b <= 1'b0;
strbDel <= Ldelay + OFFSET_DELAY;
end
endcase
end
ShiftReg16 #(32) latencyDelay (clk, delayBypass_b, din, Ldelay_b, amp_drive_del);
//assign strbDel = Ldelay + OFFSET_DELAY;
//Delay the store strobe by required amount
StrbShifter #(64) StoreStrbDel (clk, opGate, strbDel, opGateDel);
//combinatorial block for opGate
/*always @(posedge clk) opGate_ctr <= (storeStrbDel) ? opGate_ctr + 1'b1 : 11'd0;
always @(*) begin
if (storeStrbDel) begin
(* full_case, parallel_case *)
case (opGate_ctr)
start_proc: opGate = 1'b1;
end_proc: opGate = 1'b0;
//default: opGate = opGate;
endcase
end else opGate = 1'b0;
end*/
//Combi o/p block
(* equivalent_register_removal = "no", shreg_extract = "no" *) reg feedfwd_en_a = 0, feedfwd_en_b = 0; //PIPELINE REGISTERS
//reg signed [15:0] amp_drive_b = 16'sd0; //PIPELINE REGISTER
wire oflowDet;
always @(posedge clk) begin
oflowDetect <= oflowDet;
feedfwd_en_a <= feedfwd_en;
feedfwd_en_b <= feedfwd_en_a;
//amp_drive_b <= amp_drive;
end
/*always @(*) begin
if (storeStrbDel && (opGate || ~use_strobes))
(* full_case, parallel_case *) //recoded 09/10/14
case (opMode) //Need to include saturation detection here, this will be evident from the filter output - could just look for overflows!
2'd0: amp_drive = amp_drive_del;
2'd1: amp_drive = constDac_val;
default: amp_drive = 13'd0;
endcase
else amp_drive = 13'd0;
end*/
//reg delayBypass;
always @(posedge clk) begin
//delayBypass <= (Ldelay==5'd0); // register the comparator output for timing
if (opGateDel)
(* full_case, parallel_case *) //recoded 09/10/14
case (opMode) //Need to include saturation detection here, this will be evident from the filter output - could just look for overflows!
//2'd0: amp_drive <= amp_drive_del;
1'd0: amp_drive <= (delayBypass_a) ? din : amp_drive_del;
1'd1: amp_drive <= {constDac_val, 3'b000};
// `ifdef COMBINE
// 2'd2: amp_drive <= (delayBypass_a) ? din : amp_drive_del; //Combined mode, as for sample-by-sample
// `endif
default: amp_drive <= 16'd0;
//default: amp_drive <= (delayBypass_a) ? din : amp_drive_del; //Combined mode, as for sample-by-sample
endcase
else amp_drive <= 16'd0;
end
wire signed [15:0] amp_drive_IIRin = amp_drive; // Possibly remove bypass option later!
// Filter here now - input is amp_drive
wire signed [15:0] amp_drive_AD;
`ifdef SUM_OUTPUT_SMPLS
reg signed [15:0] amp_drive_AD_b = 16'sd0;
wire signed [16:0] amp_drive_out = amp_drive_AD + amp_drive_AD_b;
//reg signed [16:0] amp_drive_out = 16'sd0;
`else
wire signed [15:0] amp_drive_out = amp_drive_AD;
`endif
antiDroopIIR_16 #(16) antiDroopIIR_DAC(
.clk(clk),
.trig(opGate),
//.din(amp_drive),
.din(amp_drive_IIRin),
.tapWeight(IIRtapWeight),
.accClr_en(1'b1),
//.oflowClr(),
.oflowDetect(oflowDet),
.dout(amp_drive_AD)
);
//assign amp_drive_out = (~IIRbypass) ? amp_drive_b : amp_drive_AD;
//assign amp_drive_out = amp_drive_AD;
//Decimate and put out
(* shreg_extract = "no" *) reg clk_tog = 1'b0; //1-bit toggle
//(* shreg_extract = "no" *) reg storeStrbDel_a = 1'b0, storeStrbDel_b = 1'b0, storeStrbDel_c = 1'b0, storeStrbDel_d = 1'b0, storeStrbDel_e = 1'b0;
(* shreg_extract = "no" *) reg storeStrbDel_a = 1'b0, storeStrbDel_b = 1'b0, storeStrbDel_c = 1'b0, storeStrbDel_d = 1'b0;//, storeStrbDel_e = 1'b0;
//wire clearDAC;
//wire output_en;
reg clearDAC = 1'b0, output_en = 1'b0;
//assign clearDAC = storeStrbDel_e & ~storeStrbDel_d; //DAC must be cleared at least one cycle after the storeStrDeb goes low to avoi doubloe pulsing the DAC clk
//assign output_en = (~IIRbypass) ? storeStrbDel_a : storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
//assign output_en = storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
always @(posedge clk) begin
storeStrbDel_a <= opGateDel;
storeStrbDel_b <= storeStrbDel_a;
storeStrbDel_c <= storeStrbDel_b;
storeStrbDel_d <= storeStrbDel_c;
//storeStrbDel_e <= storeStrbDel_d;
clearDAC <= (storeStrbDel_d & ~storeStrbDel_c) && feedfwd_en_b;
output_en <= storeStrbDel_b && feedfwd_en_b;
//if (clearDAC && feedfwd_en_b) begin
`ifdef SUM_OUTPUT_SMPLS
amp_drive_AD_b <= amp_drive_AD;
//amp_drive_out <= amp_drive_AD + amp_drive_AD_b;
`endif
if (clearDAC) begin
//if (clearDAC && feedfwd_en) begin
//dout <= dout; //seems a bit dangerous to assume that the amp_drive will be cancelled at the correct time!
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b1;
//DAC_en_copy <= 1'b1;
clk_tog <= clk_tog;
//end else if (storeStrbDel && feedfwd_en_b) begin
//end else if (storeStrbDel && feedfwd_en) begin
//end else if (output_en && feedfwd_en_b) begin
end else if (output_en) begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
//DAC_en_copy <= clk_tog ^ DACclkPhase;
`ifdef SUM_OUTPUT_SMPLS
dout <= (clk_tog) ? dout : amp_drive_out[16:4];
`else
dout <= (clk_tog) ? dout : amp_drive_out[15:3];
`endif
//dout_copy <= (clk_tog) ? dout : amp_drive_out;
end else begin
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b0;
//DAC_en_copy <= 1'b0;
clk_tog <= 1'b0;
end
end
/*always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
storeStrbDel_c <= storeStrbDel_b;
storeStrbDel_d <= storeStrbDel_c;
storeStrbDel_e <= storeStrbDel_d;
if (clearDAC && feedfwd_en_b) begin
//if (clearDAC && feedfwd_en) begin
//dout <= dout; //seems a bit dangerous to assume that the amp_drive will be cancelled at the correct time!
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b1;
//DAC_en_copy <= 1'b1;
clk_tog <= clk_tog;
//end else if (storeStrbDel && feedfwd_en_b) begin
//end else if (storeStrbDel && feedfwd_en) begin
end else if (output_en && feedfwd_en_b) begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
//DAC_en_copy <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive_out[15:3];
//dout_copy <= (clk_tog) ? dout : amp_drive_out;
end else begin
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b0;
//DAC_en_copy <= 1'b0;
clk_tog <= 1'b0;
end
end*/
/*always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
if (clearDAC) begin
dout <= dout;
DAC_en <= 1'b1;
clk_tog <= clk_tog;
end else if (~storeStrbDel) begin
dout <= 13'd0;
DAC_en <= 1'b0;
clk_tog <= 1'b0;
end else begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive;
end
end*/
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title :
//
// File : alt_ddrx_cache.v
//
// Abstract :
///////////////////////////////////////////////////////////////////////////////
module alt_ddrx_cache #
( parameter
// controller settings
MEM_IF_CHIP_BITS = 2,
MEM_IF_CS_WIDTH = 4,
MEM_IF_ROW_WIDTH = 16, // max supported row bits
MEM_IF_BA_WIDTH = 3, // max supported bank bits
MEM_TYPE = "DDR3",
DWIDTH_RATIO = 2, // 2 - fullrate, 4 - halfrate
CLOSE_PAGE_POLICY = 1,
CTL_LOOK_AHEAD_DEPTH = 4,
CTL_CMD_QUEUE_DEPTH = 8
)
(
ctl_clk,
ctl_reset_n,
// state machine inputs
fetch,
// ecc inputs
ecc_fetch_error_addr,
// command queue inputs
cmd_is_valid,
// command inputs
in_cs_all_banks_closed,
in_cs_can_precharge_all,
in_cs_can_refresh,
in_cs_can_self_refresh,
in_cs_can_power_down,
in_cs_can_exit_power_saving_mode,
in_cs_zq_cal_req,
in_cs_power_down_req,
in_cs_refresh_req,
in_cmd_bank_is_open,
in_cmd_row_is_open,
in_cmd_can_write,
in_cmd_can_read,
in_cmd_can_activate,
in_cmd_can_precharge,
// command outputs
out_cs_all_banks_closed,
out_cs_can_precharge_all,
out_cs_can_refresh,
out_cs_can_self_refresh,
out_cs_can_power_down,
out_cs_can_exit_power_saving_mode,
out_cs_zq_cal_req,
out_cs_power_down_req,
out_cs_refresh_req,
out_cmd_bank_is_open,
out_cmd_row_is_open,
out_cmd_can_write,
out_cmd_can_read,
out_cmd_can_activate,
out_cmd_can_precharge,
out_cmd_info_valid
);
input ctl_clk;
input ctl_reset_n;
// state machine inputs
input fetch;
// ecc inputs
input ecc_fetch_error_addr;
// command queue inputs
input [CTL_CMD_QUEUE_DEPTH : 0] cmd_is_valid;
// command inputs
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_all_banks_closed;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_precharge_all;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_refresh;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_self_refresh;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_power_down;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_exit_power_saving_mode;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_zq_cal_req;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_power_down_req;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_refresh_req;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_bank_is_open;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_row_is_open;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_write;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_read;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_activate;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_precharge;
// command outputs
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_all_banks_closed;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_precharge_all;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_refresh;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_self_refresh;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_power_down;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_exit_power_saving_mode;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_zq_cal_req;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_power_down_req;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_refresh_req;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_bank_is_open;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_row_is_open;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_write;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_read;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_activate;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_precharge;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_info_valid;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Registers & Wires
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Cache Logic
------------------------------------------------------------------------------*/
reg cache;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_bank_is_open;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_row_is_open;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_write;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_read;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_activate;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_precharge;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_all_banks_closed;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_precharge_all;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_refresh;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_self_refresh;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_power_down;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_exit_power_saving_mode;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_zq_cal_req;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_power_down_req;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_refresh_req;
/*------------------------------------------------------------------------------
Command Valid Logic
------------------------------------------------------------------------------*/
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_info_valid;
reg [CTL_LOOK_AHEAD_DEPTH : 0] int_cmd_info_valid;
reg int_current_info_valid_r1;
reg fetch_r1;
reg ecc_fetch_error_addr_r1;
/*------------------------------------------------------------------------------
Assignment
------------------------------------------------------------------------------*/
// no changes made to these signals
assign out_cs_all_banks_closed = in_cs_all_banks_closed;
assign out_cs_can_precharge_all = in_cs_can_precharge_all;
assign out_cs_can_refresh = in_cs_can_refresh;
assign out_cs_can_self_refresh = in_cs_can_self_refresh;
assign out_cs_can_power_down = in_cs_can_power_down;
assign out_cs_can_exit_power_saving_mode = in_cs_can_exit_power_saving_mode;
assign out_cs_zq_cal_req = in_cs_zq_cal_req;
assign out_cs_power_down_req = in_cs_power_down_req;
assign out_cs_refresh_req = in_cs_refresh_req;
/*------------------------------------------------------------------------------
[END] Registers & Wires
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Cache Logic
------------------------------------------------------------------------------*/
// Determine when to cache
always @ (*)
begin
if (fetch)
cache = 1'b1;
else
cache = 1'b0;
end
/*------------------------------------------------------------------------------
Cache Logic
------------------------------------------------------------------------------*/
always @ (*)
begin
if (cache)
begin
out_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_write [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_write [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_read [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_read [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = int_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_write [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_read [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH] = 0;
end
else
begin
out_cmd_bank_is_open = in_cmd_bank_is_open;
out_cmd_can_write = in_cmd_can_write;
out_cmd_can_read = in_cmd_can_read;
out_cmd_can_activate = in_cmd_can_activate;
out_cmd_can_precharge = in_cmd_can_precharge;
out_cmd_info_valid = int_cmd_info_valid;
end
end
always @ (*)
begin
if (cache || fetch_r1)
begin
out_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH] = 0;
end
else
begin
out_cmd_row_is_open = in_cmd_row_is_open;
end
end
/*------------------------------------------------------------------------------
[END] Cache Logic
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Command Valid Logic
------------------------------------------------------------------------------*/
// register fetch signals
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
fetch_r1 <= 1'b0;
ecc_fetch_error_addr_r1 <= 1'b0;
end
else
begin
fetch_r1 <= fetch;
ecc_fetch_error_addr_r1 <= ecc_fetch_error_addr;
end
end
// Command valid logic
generate
genvar z_lookahead;
for (z_lookahead = 1; z_lookahead < CTL_LOOK_AHEAD_DEPTH + 1;z_lookahead = z_lookahead + 1)
begin : cmd_valid_logic_per_lookahead
always @ (*)
begin
int_cmd_info_valid [z_lookahead] = cmd_is_valid [z_lookahead];
end
end
endgenerate
// Current valid logic
always @ (*)
begin
if (fetch)
int_cmd_info_valid [0] = 1'b0;
else if (fetch_r1)
int_cmd_info_valid [0] = 1'b1;
//we will need to deassert current info valid signal for 2 clock cycle so that state machine will not capture the wrong information
else if (ecc_fetch_error_addr)
int_cmd_info_valid [0] = 1'b0;
else if (ecc_fetch_error_addr_r1)
int_cmd_info_valid [0] = 1'b1;
else
int_cmd_info_valid [0] = int_current_info_valid_r1;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_current_info_valid_r1 <= 1'b0;
else
int_current_info_valid_r1 <= int_cmd_info_valid [0];
end
/*------------------------------------------------------------------------------
[END] Command Valid Logic
------------------------------------------------------------------------------*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns / 1ps
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [31:0] sum;
wire [8:0] Output;
wire [8:0] Input = crc[8:0];
assigns assigns (/*AUTOINST*/
// Outputs
.Output (Output[8:0]),
// Inputs
.Input (Input[8:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module assigns(Input, Output);
input [8:0] Input;
output [8:0] Output;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8];
end
endgenerate
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_phy_10g_tx
*/
module test_eth_phy_10g_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
reg tx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
xgmii_txd,
xgmii_txc,
tx_prbs31_enable
);
$to_myhdl(
serdes_tx_data,
serdes_tx_hdr
);
// dump file
$dumpfile("test_eth_phy_10g_tx_64.lxt");
$dumpvars(0, test_eth_phy_10g_tx_64);
end
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
UUT (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.1 Date: 14- 4-2017
Version: 1.0 Date: 27-10-2016
*/
module jt51_acc(
input rst,
input clk,
input cen,
input m1_enters,
input m2_enters,
input c1_enters,
input c2_enters,
input op31_acc,
input [1:0] rl_I,
input [2:0] con_I,
input signed [13:0] op_out,
input ne, // noise enable
input signed [11:0] noise_mix,
output signed [15:0] left,
output signed [15:0] right,
output reg signed [15:0] xleft, // exact outputs
output reg signed [15:0] xright
);
reg signed [13:0] op_val;
always @(*) begin
if( ne && op31_acc ) // cambiar a OP 31
op_val = { {2{noise_mix[11]}}, noise_mix };
else
op_val = op_out;
end
reg sum_en;
always @(*) begin
case ( con_I )
3'd0,3'd1,3'd2,3'd3: sum_en = m2_enters;
3'd4: sum_en = m1_enters | m2_enters;
3'd5,3'd6: sum_en = ~c1_enters;
3'd7: sum_en = 1'b1;
default: sum_en = 1'bx;
endcase
end
wire ren = rl_I[1];
wire len = rl_I[0];
reg signed [16:0] pre_left, pre_right;
wire signed [15:0] total;
wire signed [16:0] total_ex = {total[15],total};
reg sum_all;
wire rst_sum = c2_enters;
//wire rst_sum = c1_enters;
//wire rst_sum = m1_enters;
//wire rst_sum = m2_enters;
function signed [15:0] lim16;
input signed [16:0] din;
lim16 = !din[16] && din[15] ? 16'h7fff :
( din[16] && !din[15] ? 16'h8000 : din[15:0] );
endfunction
always @(posedge clk) begin
if( rst ) begin
sum_all <= 1'b0;
end
else if(cen) begin
if( rst_sum ) begin
sum_all <= 1'b1;
if( !sum_all ) begin
pre_right <= ren ? total_ex : 17'd0;
pre_left <= len ? total_ex : 17'd0;
end
else begin
pre_right <= pre_right + (ren ? total_ex : 17'd0);
pre_left <= pre_left + (len ? total_ex : 17'd0);
end
end
if( c1_enters ) begin
sum_all <= 1'b0;
xleft <= lim16(pre_left);
xright <= lim16(pre_right);
end
end
end
reg signed [15:0] opsum;
wire signed [16:0] opsum10 = {{3{op_val[13]}},op_val}+{total[15],total};
always @(*) begin
if( rst_sum )
opsum = sum_en ? { {2{op_val[13]}}, op_val } : 16'd0;
else begin
if( sum_en )
if( opsum10[16]==opsum10[15] )
opsum = opsum10[15:0];
else begin
opsum = opsum10[16] ? 16'h8000 : 16'h7fff;
end
else
opsum = total;
end
end
jt51_sh #(.width(16),.stages(8)) u_acc(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( opsum ),
.drop ( total )
);
wire signed [9:0] left_man, right_man;
wire [2:0] left_exp, right_exp;
jt51_exp2lin left_reconstruct(
.lin( left ),
.man( left_man ),
.exp( left_exp )
);
jt51_exp2lin right_reconstruct(
.lin( right ),
.man( right_man ),
.exp( right_exp )
);
jt51_lin2exp left2exp(
.lin( xleft ),
.man( left_man ),
.exp( left_exp ) );
jt51_lin2exp right2exp(
.lin( xright ),
.man( right_man ),
.exp( right_exp ) );
`ifdef DUMPLEFT
reg skip;
wire signed [15:0] dump = left;
initial skip=1;
always @(posedge clk)
if( c1_enters && (!skip || dump) && cen) begin
$display("%d", dump );
skip <= 0;
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
|
/*
* PC speaker module without any codec
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module speaker (
// Clocks
input clk,
input rst,
// Wishbone slave interface
input [7:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// Timer clock
input timer2,
// Speaker pad signal
output speaker_
);
// Net declarations
wire write;
wire spk;
// Combinatorial logic
// System speaker
assign speaker_ = timer2 & wb_dat_o[1];
// Wishbone signals
assign wb_ack_o = wb_stb_i && wb_cyc_i;
assign write = wb_stb_i && wb_cyc_i && wb_we_i;
// Sequential logic
always @(posedge clk)
wb_dat_o <= rst ? 8'h0 : (write ? wb_dat_i : wb_dat_o);
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This is the tag RAM and data RAM unit. The tag RAM holds both the --
// -- virtual tag and the physical address. The physical address is used to --
// -- avoid translation during clean operations. The cache data RAM is also --
// -- present in this unit. This unit has a dedicated memory interface --
// -- because it can perform global clean and flush by itself without --
// -- depending on the cache controller. Only for FPGA. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
`include "zap_defines.vh"
module zap_cache_tag_ram #(
parameter CACHE_SIZE = 1024, // Bytes.
parameter CACHE_LINE = 8
)(
input wire i_clk,
input wire i_reset,
input wire [31:0] i_address_nxt,
input wire [31:0] i_address,
input wire i_cache_en,
input wire [CACHE_LINE*8-1:0] i_cache_line,
input wire [CACHE_LINE-1:0] i_cache_line_ben,
output wire [CACHE_LINE*8-1:0] o_cache_line,
input wire i_cache_tag_wr_en,
input wire [`CACHE_TAG_WDT-1:0] i_cache_tag,
input wire i_cache_tag_dirty,
output wire [`CACHE_TAG_WDT-1:0] o_cache_tag,
output reg o_cache_tag_valid,
output reg o_cache_tag_dirty,
input wire i_cache_clean_req,
output reg o_cache_clean_done,
input wire i_cache_inv_req,
output reg o_cache_inv_done,
/*
* Cache clean operations occur through these ports.
* Memory access ports, both NXT and FF. Usually you'll be connecting NXT ports
*/
output reg o_wb_cyc_ff, o_wb_cyc_nxt,
output reg o_wb_stb_ff, o_wb_stb_nxt,
output reg [31:0] o_wb_adr_ff, o_wb_adr_nxt,
output reg [31:0] o_wb_dat_ff, o_wb_dat_nxt,
output reg [3:0] o_wb_sel_ff, o_wb_sel_nxt,
output reg o_wb_wen_ff, o_wb_wen_nxt,
output reg [2:0] o_wb_cti_ff, o_wb_cti_nxt, /* Cycle Type Indicator - 010, 111 */
input wire [31:0] i_wb_dat,
input wire i_wb_ack
);
// ----------------------------------------------------------------------------
`include "zap_localparams.vh"
localparam NUMBER_OF_DIRTY_BLOCKS = ((CACHE_SIZE/CACHE_LINE)/16); // Keep cache size > 16 bytes.
// States.
localparam IDLE = 0;
localparam CACHE_CLEAN_GET_ADDRESS = 1;
localparam CACHE_CLEAN_WRITE = 2;
localparam CACHE_INV = 3;
// ----------------------------------------------------------------------------
reg [(CACHE_SIZE/CACHE_LINE)-1:0] dirty;
reg [(CACHE_SIZE/CACHE_LINE)-1:0] valid;
reg [`CACHE_TAG_WDT-1:0] tag_ram_wr_data;
reg tag_ram_wr_en;
reg [$clog2(CACHE_SIZE/CACHE_LINE)-1:0] tag_ram_wr_addr;
reg [$clog2(CACHE_SIZE/CACHE_LINE)-1:0] tag_ram_rd_addr;
reg tag_ram_clear;
reg tag_ram_clean;
reg [1:0] state_ff, state_nxt;
reg [$clog2(NUMBER_OF_DIRTY_BLOCKS):0] blk_ctr_ff, blk_ctr_nxt;
reg [$clog2(CACHE_LINE/4):0] adr_ctr_ff, adr_ctr_nxt;
genvar i;
// ----------------------------------------------------------------------------
for(i=0;i<CACHE_LINE;i=i+1)
begin
zap_ram_simple #(.WIDTH(8), .DEPTH(CACHE_SIZE/CACHE_LINE)) u_zap_ram_simple_data_ram (
.i_clk(i_clk),
.i_wr_en(i_cache_line_ben[i]),
.i_rd_en(1'd1),
.i_wr_data(i_cache_line [i*8+7:i*8]),
.o_rd_data(o_cache_line [i*8+7:i*8]),
.i_wr_addr(tag_ram_wr_addr),
.i_rd_addr(tag_ram_rd_addr)
);
end
zap_ram_simple #(.WIDTH(`CACHE_TAG_WDT), .DEPTH(CACHE_SIZE/CACHE_LINE)) u_zap_ram_simple_tag (
.i_clk(i_clk),
.i_wr_en(tag_ram_wr_en),
.i_rd_en(1'd1),
.i_wr_data(tag_ram_wr_data),
.o_rd_data(o_cache_tag),
.i_wr_addr(tag_ram_wr_addr),
.i_rd_addr(tag_ram_rd_addr)
);
// ----------------------------------------------------------------------------
always @ (posedge i_clk)
begin
o_cache_tag_dirty <= dirty [ tag_ram_rd_addr ];
if ( i_reset )
dirty <= 0;
else if ( tag_ram_wr_en )
dirty [ tag_ram_wr_addr ] <= i_cache_tag_dirty;
else if ( tag_ram_clean )
dirty[tag_ram_rd_addr] <= 1'd0;// BUG FIX dirty_nxt;
end
always @ (posedge i_clk)
begin
o_cache_tag_valid <= valid [ tag_ram_rd_addr ];
if ( tag_ram_clear || !i_cache_en || i_reset )
valid <= 0;
else if ( tag_ram_wr_en )
valid [ tag_ram_wr_addr ] <= 1'd1;
end
// ----------------------------------------------------------------------------
always @ (posedge i_clk)
begin
if ( i_reset )
begin
o_wb_cyc_ff <= 0;
o_wb_stb_ff <= 0;
o_wb_wen_ff <= 0;
o_wb_sel_ff <= 0;
o_wb_dat_ff <= 0;
o_wb_cti_ff <= CTI_CLASSIC;
o_wb_adr_ff <= 0;
adr_ctr_ff <= 0;
blk_ctr_ff <= 0;
state_ff <= IDLE;
end
else
begin
o_wb_cyc_ff <= o_wb_cyc_nxt;
o_wb_stb_ff <= o_wb_stb_nxt;
o_wb_wen_ff <= o_wb_wen_nxt;
o_wb_sel_ff <= o_wb_sel_nxt;
o_wb_dat_ff <= o_wb_dat_nxt;
o_wb_cti_ff <= o_wb_cti_nxt;
o_wb_adr_ff <= o_wb_adr_nxt;
adr_ctr_ff <= adr_ctr_nxt;
blk_ctr_ff <= blk_ctr_nxt;
state_ff <= state_nxt;
end
end
// ----------------------------------------------------------------------------
always @*
begin:blk1
reg [31:0] shamt, data, pa;
shamt = 0;
data = 0;
pa = 0;
// Defaults.
state_nxt = state_ff;
tag_ram_rd_addr = 0;
tag_ram_wr_addr = i_address [`VA__CACHE_INDEX];
tag_ram_wr_en = 0;
tag_ram_clear = 0;
tag_ram_clean = 0;
adr_ctr_nxt = adr_ctr_ff;
blk_ctr_nxt = blk_ctr_ff;
o_cache_clean_done = 0;
o_cache_inv_done = 0;
o_wb_cyc_nxt = o_wb_cyc_ff;
o_wb_stb_nxt = o_wb_stb_ff;
o_wb_adr_nxt = o_wb_adr_ff;
o_wb_dat_nxt = o_wb_dat_ff;
o_wb_sel_nxt = o_wb_sel_ff;
o_wb_wen_nxt = o_wb_wen_ff;
o_wb_cti_nxt = o_wb_cti_ff;
tag_ram_wr_data = 0;
case ( state_ff )
IDLE:
begin: blp9
integer i;
kill_access;
tag_ram_rd_addr = i_address_nxt [`VA__CACHE_INDEX];
tag_ram_wr_addr = i_address [`VA__CACHE_INDEX];
tag_ram_wr_en = i_cache_tag_wr_en;
tag_ram_wr_data = i_cache_tag;
if ( i_cache_clean_req )
begin
tag_ram_wr_en = 0;
blk_ctr_nxt = 0;
state_nxt = CACHE_CLEAN_GET_ADDRESS;
end
else if ( i_cache_inv_req )
begin
tag_ram_wr_en = 0;
state_nxt = CACHE_INV;
end
end
CACHE_CLEAN_GET_ADDRESS:
begin
tag_ram_rd_addr = get_tag_ram_rd_addr (blk_ctr_ff , dirty);
if ( &baggage(dirty, blk_ctr_ff) )
begin
// Move to next block.
blk_ctr_nxt = blk_ctr_ff + 1;
if ( blk_ctr_ff == NUMBER_OF_DIRTY_BLOCKS - 1 )
begin
state_nxt = IDLE;
o_cache_clean_done = 1'd1;
end
end
else
begin
// Go to state.
state_nxt = CACHE_CLEAN_WRITE;
end
adr_ctr_nxt = 0; // Initialize address counter.
end
CACHE_CLEAN_WRITE:
begin
tag_ram_rd_addr = get_tag_ram_rd_addr (blk_ctr_ff , dirty);
adr_ctr_nxt = adr_ctr_ff + (i_wb_ack && o_wb_stb_ff);
if ( adr_ctr_nxt > ((CACHE_LINE/4) - 1) )
begin
// Remove dirty marking. BUG FIX.
tag_ram_clean = 1;
// Kill access.
kill_access;
// Go to new state.
state_nxt = CACHE_CLEAN_GET_ADDRESS;
end
else
begin
shamt = adr_ctr_nxt * 32;
data = o_cache_line >> shamt;
pa = o_cache_tag[`CACHE_TAG__PA] << $clog2(CACHE_LINE);
// Perform a Wishbone write using Physical Address.
wb_prpr_write( data, pa + (adr_ctr_nxt * (32/8)), (adr_ctr_nxt != (CACHE_LINE/4)-1) ? CTI_BURST : CTI_EOB, 4'b1111
);
end
end
CACHE_INV:
begin
tag_ram_clear = 1'd1;
state_nxt = IDLE;
o_cache_inv_done = 1'd1;
end
endcase
end
// -----------------------------------------------------------------------------
// Priority encoder.
function [4:0] pri_enc_1 ( input [15:0] in );
begin: priEncFn
casez ( in )
16'b0000_0000_0000_0001: pri_enc_1 = 4'd0;
16'b0000_0000_0000_001?: pri_enc_1 = 4'd1;
16'b0000_0000_0000_01??: pri_enc_1 = 4'd2;
16'b0000_0000_0000_1???: pri_enc_1 = 4'd3;
16'b0000_0000_0001_????: pri_enc_1 = 4'd4;
16'b0000_0000_001?_????: pri_enc_1 = 4'd5;
16'b0000_0000_01??_????: pri_enc_1 = 4'd6;
16'b0000_0000_1???_????: pri_enc_1 = 4'd7;
16'b0000_0001_????_????: pri_enc_1 = 4'd8;
16'b0000_001?_????_????: pri_enc_1 = 4'd9;
16'b0000_01??_????_????: pri_enc_1 = 4'hA;
16'b0000_1???_????_????: pri_enc_1 = 4'hB;
16'b0001_????_????_????: pri_enc_1 = 4'hC;
16'b001?_????_????_????: pri_enc_1 = 4'hD;
16'b01??_????_????_????: pri_enc_1 = 4'hE;
16'b1???_????_????_????: pri_enc_1 = 4'hF;
default: pri_enc_1 = 5'b11111;
endcase
end
endfunction
// -----------------------------------------------------------------------------
function [31:0] get_tag_ram_rd_addr (
input [$clog2(NUMBER_OF_DIRTY_BLOCKS)-1:0] blk_ctr,
input [CACHE_SIZE/CACHE_LINE-1:0] dirty
);
reg [CACHE_SIZE/CACHE_LINE-1:0] dirty_new;
reg [3:0] enc;
reg [31:0] shamt;
begin
shamt = blk_ctr_ff << 4;
dirty_new = dirty >> shamt;
enc = pri_enc_1(dirty_new);
get_tag_ram_rd_addr = shamt + enc;
end
endfunction
// ----------------------------------------------------------------------------
/* Function to generate Wishbone read signals. */
task wb_prpr_read;
input [31:0] i_address;
input [2:0] i_cti;
begin
o_wb_cyc_nxt = 1'd1;
o_wb_stb_nxt = 1'd1;
o_wb_wen_nxt = 1'd0;
o_wb_sel_nxt = 4'b1111;
o_wb_adr_nxt = i_address;
o_wb_cti_nxt = i_cti;
o_wb_dat_nxt = 0;
end
endtask
// ----------------------------------------------------------------------------
/* Function to generate Wishbone write signals */
task wb_prpr_write;
input [31:0] i_data;
input [31:0] i_address;
input [2:0] i_cti;
input [3:0] i_ben;
begin
o_wb_cyc_nxt = 1'd1;
o_wb_stb_nxt = 1'd1;
o_wb_wen_nxt = 1'd1;
o_wb_sel_nxt = i_ben;
o_wb_adr_nxt = i_address;
o_wb_cti_nxt = i_cti;
o_wb_dat_nxt = i_data;
end
endtask
// ----------------------------------------------------------------------------
/* Disables Wishbone */
task kill_access;
begin
o_wb_cyc_nxt = 0;
o_wb_stb_nxt = 0;
o_wb_wen_nxt = 0;
o_wb_adr_nxt = 0;
o_wb_dat_nxt = 0;
o_wb_sel_nxt = 0;
o_wb_cti_nxt = CTI_CLASSIC;
end
endtask
// ----------------------------------------------------------------------------
function [4:0] baggage (
input [CACHE_SIZE/CACHE_LINE-1:0] dirty,
input [$clog2(NUMBER_OF_DIRTY_BLOCKS)-1:0] blk_ctr_ff
);
reg [31:0] shamt;
begin
shamt = blk_ctr_ff << 4;
baggage = pri_enc_1(dirty >> shamt);
end
endfunction
endmodule // zap_cache_tag_ram.v
`default_nettype wire
// ----------------------------------------------------------------------------
// END OF FILE
// ----------------------------------------------------------------------------
|
module HazardCheckUnit(IDEXMemRead,IDEXRt,IFIDRs,IFIDRt,PCWrite,IFIDWrite,ctrlSetZero,IDEXRd,IDEXRegWrite,opcode,EXMEMRead,EXMEMRt,clk);
input[4:0] IDEXRt,IFIDRt,IFIDRs,IDEXRd,EXMEMRt;
input IDEXMemRead,IDEXRegWrite,EXMEMRead;
input[5:0] opcode;
input clk;
output PCWrite,IFIDWrite,ctrlSetZero;
reg PCWrite,IFIDWrite,ctrlSetZero;
initial
begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
always @(opcode or IDEXMemRead or IDEXRt or IFIDRs or IFIDRt or IDEXRd or IDEXRegWrite or clk) begin
if(opcode==6'b000100)begin
if(IDEXMemRead && ((IDEXRt==IFIDRs) || (IDEXRt==IFIDRt))) begin//beq,lw,stall 2 clks
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else if(IDEXRegWrite && ((IDEXRd==IFIDRs) || (IDEXRd==IFIDRt)))begin//beq,R,stall 1 clk
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
if(EXMEMRead && ((EXMEMRt==IFIDRs) || (EXMEMRt==IFIDRt)))begin
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
end
else begin
if(IDEXMemRead && ((IDEXRt==IFIDRs) || (IDEXRt==IFIDRt))) begin//R,lw,stall 1 clk
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
end
end
endmodule |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:23:09 MST 2015
//Date : Fri Nov 10 02:35:34 2017
//Host : aCentauri running 64-bit Service Pack 1 (build 7601)
//Command : generate_target OpenSSD2_wrapper.bd
//Design : OpenSSD2_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module OpenSSD2_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
IO_NAND_CH0_DQ,
IO_NAND_CH0_DQS_N,
IO_NAND_CH0_DQS_P,
IO_NAND_CH1_DQ,
IO_NAND_CH1_DQS_N,
IO_NAND_CH1_DQS_P,
I_NAND_CH0_RB,
I_NAND_CH1_RB,
O_DEBUG,
O_NAND_CH0_ALE,
O_NAND_CH0_CE,
O_NAND_CH0_CLE,
O_NAND_CH0_RE_N,
O_NAND_CH0_RE_P,
O_NAND_CH0_WE,
O_NAND_CH0_WP,
O_NAND_CH1_ALE,
O_NAND_CH1_CE,
O_NAND_CH1_CLE,
O_NAND_CH1_RE_N,
O_NAND_CH1_RE_P,
O_NAND_CH1_WE,
O_NAND_CH1_WP,
pcie_perst_n,
pcie_ref_clk_n,
pcie_ref_clk_p,
pcie_rx_n,
pcie_rx_p,
pcie_tx_n,
pcie_tx_p);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [7:0]IO_NAND_CH0_DQ;
inout IO_NAND_CH0_DQS_N;
inout IO_NAND_CH0_DQS_P;
inout [7:0]IO_NAND_CH1_DQ;
inout IO_NAND_CH1_DQS_N;
inout IO_NAND_CH1_DQS_P;
input [7:0]I_NAND_CH0_RB;
input [7:0]I_NAND_CH1_RB;
output [31:0]O_DEBUG;
output O_NAND_CH0_ALE;
output [7:0]O_NAND_CH0_CE;
output O_NAND_CH0_CLE;
output O_NAND_CH0_RE_N;
output O_NAND_CH0_RE_P;
output O_NAND_CH0_WE;
output O_NAND_CH0_WP;
output O_NAND_CH1_ALE;
output [7:0]O_NAND_CH1_CE;
output O_NAND_CH1_CLE;
output O_NAND_CH1_RE_N;
output O_NAND_CH1_RE_P;
output O_NAND_CH1_WE;
output O_NAND_CH1_WP;
input pcie_perst_n;
input pcie_ref_clk_n;
input pcie_ref_clk_p;
input [7:0]pcie_rx_n;
input [7:0]pcie_rx_p;
output [7:0]pcie_tx_n;
output [7:0]pcie_tx_p;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [7:0]IO_NAND_CH0_DQ;
wire IO_NAND_CH0_DQS_N;
wire IO_NAND_CH0_DQS_P;
wire [7:0]IO_NAND_CH1_DQ;
wire IO_NAND_CH1_DQS_N;
wire IO_NAND_CH1_DQS_P;
wire [7:0]I_NAND_CH0_RB;
wire [7:0]I_NAND_CH1_RB;
wire [31:0]O_DEBUG;
wire O_NAND_CH0_ALE;
wire [7:0]O_NAND_CH0_CE;
wire O_NAND_CH0_CLE;
wire O_NAND_CH0_RE_N;
wire O_NAND_CH0_RE_P;
wire O_NAND_CH0_WE;
wire O_NAND_CH0_WP;
wire O_NAND_CH1_ALE;
wire [7:0]O_NAND_CH1_CE;
wire O_NAND_CH1_CLE;
wire O_NAND_CH1_RE_N;
wire O_NAND_CH1_RE_P;
wire O_NAND_CH1_WE;
wire O_NAND_CH1_WP;
wire pcie_perst_n;
wire pcie_ref_clk_n;
wire pcie_ref_clk_p;
wire [7:0]pcie_rx_n;
wire [7:0]pcie_rx_p;
wire [7:0]pcie_tx_n;
wire [7:0]pcie_tx_p;
OpenSSD2 OpenSSD2_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IO_NAND_CH0_DQ(IO_NAND_CH0_DQ),
.IO_NAND_CH0_DQS_N(IO_NAND_CH0_DQS_N),
.IO_NAND_CH0_DQS_P(IO_NAND_CH0_DQS_P),
.IO_NAND_CH1_DQ(IO_NAND_CH1_DQ),
.IO_NAND_CH1_DQS_N(IO_NAND_CH1_DQS_N),
.IO_NAND_CH1_DQS_P(IO_NAND_CH1_DQS_P),
.I_NAND_CH0_RB(I_NAND_CH0_RB),
.I_NAND_CH1_RB(I_NAND_CH1_RB),
.O_DEBUG(O_DEBUG),
.O_NAND_CH0_ALE(O_NAND_CH0_ALE),
.O_NAND_CH0_CE(O_NAND_CH0_CE),
.O_NAND_CH0_CLE(O_NAND_CH0_CLE),
.O_NAND_CH0_RE_N(O_NAND_CH0_RE_N),
.O_NAND_CH0_RE_P(O_NAND_CH0_RE_P),
.O_NAND_CH0_WE(O_NAND_CH0_WE),
.O_NAND_CH0_WP(O_NAND_CH0_WP),
.O_NAND_CH1_ALE(O_NAND_CH1_ALE),
.O_NAND_CH1_CE(O_NAND_CH1_CE),
.O_NAND_CH1_CLE(O_NAND_CH1_CLE),
.O_NAND_CH1_RE_N(O_NAND_CH1_RE_N),
.O_NAND_CH1_RE_P(O_NAND_CH1_RE_P),
.O_NAND_CH1_WE(O_NAND_CH1_WE),
.O_NAND_CH1_WP(O_NAND_CH1_WP),
.pcie_perst_n(pcie_perst_n),
.pcie_ref_clk_n(pcie_ref_clk_n),
.pcie_ref_clk_p(pcie_ref_clk_p),
.pcie_rx_n(pcie_rx_n),
.pcie_rx_p(pcie_rx_p),
.pcie_tx_n(pcie_tx_n),
.pcie_tx_p(pcie_tx_p));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_BLACKBOX_V
`define SKY130_FD_SC_LS__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:15:25 09/05/2012
// Design Name:
// Module Name: posted_pkt_scheduler_4radios
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module posted_pkt_scheduler_4radios(
input clk,
input rst,
//interface to PCIe Endpoint Block Plus
input [2:0] max_pay_size,
//interface from/to RX data fifo
input [63:0] RX_FIFO_data,
output RX_FIFO_RDEN,
input RX_FIFO_pempty,
input [31:0] RX_TS_FIFO_data,
output RX_TS_FIFO_RDEN,
input RX_TS_FIFO_empty,
//interface from/to the 2nd RX data fifo
input [63:0] RX_FIFO_2nd_data,
output RX_FIFO_2nd_RDEN,
input RX_FIFO_2nd_pempty,
input [31:0] RX_TS_FIFO_2nd_data,
output RX_TS_FIFO_2nd_RDEN,
input RX_TS_FIFO_2nd_empty,
//interface from/to the 3rd RX data fifo
input [63:0] RX_FIFO_3rd_data,
output RX_FIFO_3rd_RDEN,
input RX_FIFO_3rd_pempty,
input [31:0] RX_TS_FIFO_3rd_data,
output RX_TS_FIFO_3rd_RDEN,
input RX_TS_FIFO_3rd_empty,
//interface from/to the 4th RX data fifo
input [63:0] RX_FIFO_4th_data,
output RX_FIFO_4th_RDEN,
input RX_FIFO_4th_pempty,
input [31:0] RX_TS_FIFO_4th_data,
output RX_TS_FIFO_4th_RDEN,
input RX_TS_FIFO_4th_empty,
//interface from/to dma ctrl wrapper
/// TX descriptor write back
input TX_desc_write_back_req,
output reg TX_desc_write_back_ack,
input [63:0] SourceAddr,
input [31:0] DestAddr,
input [23:0] FrameSize,
input [7:0] FrameControl,
input [63:0] DescAddr,
/// RX control signals
input RXEnable,
input [63:0] RXBuf_1stAddr,
input [31:0] RXBuf_1stSize,
/// RX control signals for the 2nd RX buffer
input RXEnable_2nd,
input [63:0] RXBuf_2ndAddr,
input [31:0] RXBuf_2ndSize,
/// RX control signals for the 3rd RX buffer
input RXEnable_3rd,
input [63:0] RXBuf_3rdAddr,
input [31:0] RXBuf_3rdSize,
/// RX control signals for the 4th RX buffer
input RXEnable_4th,
input [63:0] RXBuf_4thAddr,
input [31:0] RXBuf_4thSize,
//interface from/to dma write data fifo in TX engine
output reg [63:0] dma_write_data_fifo_data,
output reg dma_write_data_fifo_wren,
input dma_write_data_fifo_full,
//interface to posted pkt builder
output reg go,
input ack,
output reg [63:0] dmawad,
output [9:0] length,
//interface from a64_128_distram_p(posted header fifo)
input posted_fifo_full
// debug interface
// output reg [31:0] Debug20RX1,
//// output reg [4:0] Debug22RX3,
// output reg [31:0] Debug24RX5,
// output reg [31:0] Debug26RX7,
// output reg [31:0] Debug27RX8,
// output reg [31:0] Debug28RX9,
// output reg [31:0] Debug29RX10
);
//state machine state definitions for state
localparam IDLE = 5'b00000;
localparam TX_DESC_WRITE_BACK = 5'b00001;
localparam TX_DESC_WRITE_BACK2 = 5'b00010;
localparam TX_DESC_WRITE_BACK3 = 5'b00011;
localparam TX_DESC_WRITE_BACK4 = 5'b00100;
localparam WAIT_FOR_ACK = 5'b00101;
localparam RX_PACKET = 5'b00110;
localparam RX_PACKET2 = 5'b00111;
localparam RX_PACKET3 = 5'b01000;
localparam RX_PACKET4 = 5'b01001;
localparam RX_PACKET5 = 5'b01010;
localparam RX_PACKET6 = 5'b01011;
localparam RX_PACKET_WAIT_FOR_ACK = 5'b01100;
localparam RX_DESC_WAIT = 5'b10011;
localparam RX_DESC = 5'b01101;
localparam RX_DESC2 = 5'b01110;
localparam RX_CLEAR = 5'b10000;
localparam RX_CLEAR2 = 5'b11111;
localparam RX_CLEAR_WAIT_FOR_ACK = 5'b10101;
localparam RX_CLEAR_WAIT = 5'b11100;
reg [4:0] state;
localparam RX_FRAME_SIZE_BYTES = 13'h0070; // data frame size is 112 bytes
localparam TX_DESC_SIZE_BYTES = 13'h0020; // TX descriptor size is 32 bytes
localparam RX_DESC_SIZE_BYTES = 13'h0010; // RX descriptor size is 16 bytes
// Signals for RoundRobin scheduling, two RX paths, pending
// reg Current_Path; // 0: Current path is RX FIFO 1; 1: Current path is RX FIFO 2
// Signals for RoundRobin scheduling, four RX paths
reg [1:0] pathindex_inturn; // 00: path 1; 01: path 2; 10: path 3; 11: path 4
reg RX_FIFO_RDEN_cntl; // read RX FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
// is used to select one of the RX FIFOs
reg RX_TS_FIFO_RDEN_cntl; // read RX TS FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
// is used to select one of the RX FIFOs
wire [31:0] RX_TS_FIFO_data_cntl;
reg [13:0] cnt; // counter for RX data
reg [63:0] fifo_data_pipe; // pipeline data register between RX fifo and
// dma write data fifo, also swap the upper and lower
// DW
reg [12:0] length_byte; // output posted packet length
////////////// RX Path 1 //////////////////////
reg buf_inuse; // whether this RX Buf is in use
reg [31:0] RoundNumber; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_1st, dmawad_now2_1st;
reg [63:0] dmawad_next_1st; // next RX data destination address
// reg [63:0] dmawad_desc; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_1stAddr_r1, RXBuf_1stAddr_r2;
reg [31:0] RXBuf_1stSize_r;
////////////// RX Path 2 //////////////////////
reg buf_inuse_2nd; // whether this RX Buf is in use
reg [31:0] RoundNumber_2nd; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_2nd;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_2nd, dmawad_now2_2nd;
reg [63:0] dmawad_next_2nd; // next RX data destination address
// reg [63:0] dmawad_desc_2nd; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_2ndAddr_r1, RXBuf_2ndAddr_r2;
reg [31:0] RXBuf_2ndSize_r;
////////////// RX Path 3 //////////////////////
reg buf_inuse_3rd; // whether this RX Buf is in use
reg [31:0] RoundNumber_3rd; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_3rd;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_3rd, dmawad_now2_3rd;
reg [63:0] dmawad_next_3rd; // next RX data destination address
// reg [63:0] dmawad_desc_3rd; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_3rdAddr_r1, RXBuf_3rdAddr_r2;
reg [31:0] RXBuf_3rdSize_r;
////////////// RX Path 4 //////////////////////
reg buf_inuse_4th; // whether this RX Buf is in use
reg [31:0] RoundNumber_4th; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_4th;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_4th, dmawad_now2_4th;
reg [63:0] dmawad_next_4th; // next RX data destination address
// reg [63:0] dmawad_desc_4th; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_4thAddr_r1, RXBuf_4thAddr_r2;
reg [31:0] RXBuf_4thSize_r;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// // Debug register
// always@(posedge clk)begin
// Debug20RX1[3:0] <= state[3:0];
// Debug20RX1[7:4] <= {3'b000,buf_inuse};
// Debug20RX1[23:8] <= {3'b000,length_byte[12:0]};
// Debug20RX1[27:24] <= {1'b0,max_pay_size};
// Debug20RX1[31:28] <= {3'b000,posted_fifo_full};
// end
//
//// always@(posedge clk)begin
//// Debug22RX3[3:0] <= {3'b000,dma_write_data_fifo_full};
//// Debug22RX3[4] <= RX_FIFO_pempty;
//// end
//
// always@(posedge clk)begin
// if (rst)
// Debug24RX5[31:0] <= 32'h0000_0000;
// else begin
// if (RX_FIFO_RDEN)
// Debug24RX5 <= Debug24RX5 + 8'h0000_0001;
// else
// Debug24RX5 <= Debug24RX5;
// end
// end
//
// always@(posedge clk)begin
// if(rst)
// Debug26RX7 <= 32'h0000_0000;
// else if (dma_write_data_fifo_wren)
// Debug26RX7 <= Debug26RX7 + 32'h0000_0001;
// else
// Debug26RX7 <= Debug26RX7;
// end
//
// always@(posedge clk)begin
// if (rst)
// Debug27RX8 <= 32'h0000_0000;
// else if (state == RX_PACKET)
// Debug27RX8 <= Debug27RX8 + 32'h0000_0001;
// else
// Debug27RX8 <= Debug27RX8;
// end
//
// always@(posedge clk)begin
// Debug28RX9 <= dmawad[31:0];
// Debug29RX10 <= dmawad[63:32];
// end
// pipeline registers for RX path 1
always@(posedge clk)begin
RXBuf_1stAddr_r1 <= RXBuf_1stAddr;
RXBuf_1stAddr_r2 <= RXBuf_1stAddr;
RXBuf_1stSize_r <= RXBuf_1stSize;
end
// pipeline registers for RX path 2
always@(posedge clk)begin
RXBuf_2ndAddr_r1 <= RXBuf_2ndAddr;
RXBuf_2ndAddr_r2 <= RXBuf_2ndAddr;
RXBuf_2ndSize_r <= RXBuf_2ndSize;
end
// pipeline registers for RX path 3
always@(posedge clk)begin
RXBuf_3rdAddr_r1 <= RXBuf_3rdAddr;
RXBuf_3rdAddr_r2 <= RXBuf_3rdAddr;
RXBuf_3rdSize_r <= RXBuf_3rdSize;
end
// pipeline registers for RX path 4
always@(posedge clk)begin
RXBuf_4thAddr_r1 <= RXBuf_4thAddr;
RXBuf_4thAddr_r2 <= RXBuf_4thAddr;
RXBuf_4thSize_r <= RXBuf_4thSize;
end
wire [12:0] frame_size_bytes; // RX data frame size, min(RX_FRAME_SIZE_BYTES, max_pay_size_bytes)
wire [12:0] max_pay_size_bytes; // max payload size from pcie core
//calculate the max payload size in bytes for ease of calculations
//instead of the encoding as specified
//in the PCI Express Base Specification
assign max_pay_size_bytes =13'h0001<<(max_pay_size+7);
assign frame_size_bytes = (RX_FRAME_SIZE_BYTES <= max_pay_size_bytes) ? RX_FRAME_SIZE_BYTES :
max_pay_size_bytes;
//generate TX_desc_write_back_ack signal
always@(posedge clk) begin
if (rst_reg)
TX_desc_write_back_ack <= 1'b0;
else if (state == TX_DESC_WRITE_BACK)
TX_desc_write_back_ack <= 1'b1;
else
TX_desc_write_back_ack <= 1'b0;
end
/// Jiansong: pipeline data register between RX fifo and
/// dma write data fifo, also swap the upper and lower DW
//always@(posedge clk) fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
// always@(posedge clk) fifo_data_pipe[63:0] <= (~Current_Path) ?
// {RX_FIFO_data[15:0],RX_FIFO_data[31:16],
// RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
// {RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
// RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]};
always@(posedge clk) fifo_data_pipe[63:0] <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
{RX_FIFO_data[15:0],RX_FIFO_data[31:16],
RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
{RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]}
)
: ( (pathindex_inturn[0] == 1'b0) ?
{RX_FIFO_3rd_data[15:0],RX_FIFO_3rd_data[31:16],
RX_FIFO_3rd_data[47:32],RX_FIFO_3rd_data[63:48]} :
{RX_FIFO_4th_data[15:0],RX_FIFO_4th_data[31:16],
RX_FIFO_4th_data[47:32],RX_FIFO_4th_data[63:48]}
);
// assign RX_FIFO_RDEN = Current_Path & RX_FIFO_RDEN_cntl;
// assign RX_FIFO_2nd_RDEN = (~Current_Path) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_FIFO_RDEN_cntl;
assign RX_TS_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_data_cntl[31:0] = (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_data[31:0] : RX_TS_FIFO_2nd_data[31:0] )
: ( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_3rd_data[31:0] : RX_TS_FIFO_4th_data[31:0] );
//main state machine
always@ (posedge clk) begin
if (rst_reg) begin
state <= IDLE;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
go <= 1'b0;
buf_inuse <= 1'b0;
buf_inuse_2nd <= 1'b0;
buf_inuse_3rd <= 1'b0;
buf_inuse_4th <= 1'b0;
pathindex_inturn <= 2'b00;
cnt <= 13'h0000;
end else begin
case (state)
IDLE : begin
cnt <= 13'h0000;
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
// check if need to generate a posted packet
if(~posted_fifo_full & ~dma_write_data_fifo_full) begin
if(TX_desc_write_back_req)
state <= TX_DESC_WRITE_BACK;
else begin
casex({ pathindex_inturn[1:0],
((~RX_FIFO_pempty)&(~RX_TS_FIFO_empty)),
((~RX_FIFO_2nd_pempty)&(~RX_TS_FIFO_2nd_empty)),
((~RX_FIFO_3rd_pempty)&(~RX_TS_FIFO_3rd_empty)),
((~RX_FIFO_4th_pempty)&(~RX_TS_FIFO_4th_empty)) })
6'b00_1xxx, 6'b01_1000, 6'b10_1x00, 6'b11_1xx0: begin // path1's turn
pathindex_inturn <= 2'b00;
buf_inuse <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_01xx, 6'b01_x1xx, 6'b10_0100, 6'b11_01x0: begin // path2's turn
pathindex_inturn <= 2'b01;
buf_inuse_2nd <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_001x, 6'b01_x01x, 6'b10_xx1x, 6'b11_0010: begin // path3's turn
pathindex_inturn <= 2'b10;
buf_inuse_3rd <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_0001, 6'b01_x001, 6'b10_xx01, 6'b11_xxx1: begin // path4's turn
pathindex_inturn <= 2'b11;
buf_inuse_4th <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
default: begin // IDLE state
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= IDLE;
end
endcase
// case({Path_Priority, ~RX_FIFO_pempty, ~RX_FIFO_2nd_pempty})
// 3'b010, 3'b011, 3'b110: begin
// Current_Path <= 1'b0;
// buf_inuse <= 1'b0;
// cnt <= frame_size_bytes;
// state <= RX_CLEAR;
// end
// 3'b101, 3'b111, 3'b001: begin
// Current_Path <= 1'b1;
// buf_inuse_2nd <= 1'b0;
// cnt <= frame_size_bytes;
// state <= RX_CLEAR;
// end
// 3'b000, 3'b100: begin
// state <= IDLE;
// end
// endcase
end
end else
state <= IDLE;
end
// start TX desc write back flow
TX_DESC_WRITE_BACK : begin // write TX descriptor into dma write data fifo
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// TimeStamp(4B), TXStatus(2B), CRC(2B)
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= TX_DESC_WRITE_BACK2;
end
TX_DESC_WRITE_BACK2 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// SourceAddr(8B)
dma_write_data_fifo_data[63:0] <= SourceAddr;
state <= TX_DESC_WRITE_BACK3;
end
TX_DESC_WRITE_BACK3 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// NextDesc(4B), DestAddr(4B)
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,DestAddr};
state <= TX_DESC_WRITE_BACK4;
end
TX_DESC_WRITE_BACK4 : begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// Reserved(4B), FrameControl, FrameSize(3B)
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,FrameControl,FrameSize};
state <= WAIT_FOR_ACK;
end
WAIT_FOR_ACK : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
if(ack) begin
go <= 1'b0;
state <= IDLE;
end else begin
go <= 1'b1;
state <= WAIT_FOR_ACK;
end
end
// start of a clear next desc -> generate RX packet -> write des flow,
// clear RX descriptor of next block
RX_CLEAR : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// clear RX desc
dma_write_data_fifo_data[63:0] <= {64'h0000_0000_0000_0000};
state <= RX_CLEAR2;
end
RX_CLEAR2 : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b1;
dma_write_data_fifo_wren <= 1'b1;
// write round number in RX desc. In case it's the head of RX buffer,
// RoundNumber could be old
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0]+32'h0000_001C,RoundNumber[31:0]};
state <= RX_CLEAR_WAIT_FOR_ACK;
end
RX_CLEAR_WAIT_FOR_ACK : begin
// RX_FIFO_RDEN <= 1'b0; // this is a modification here, previously (in SISO), we read out the first data in IDLE state
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if(ack) begin
go <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
RX_FIFO_RDEN_cntl <= 1'b1;
state <= RX_PACKET;
end else begin
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT;
end
end else begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT_FOR_ACK;
end
end
RX_CLEAR_WAIT : begin
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
RX_FIFO_RDEN_cntl <= 1'b1;
state <= RX_PACKET;
end else begin
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT;
end
end
// start of RX packet generation flow
RX_PACKET : begin
go <= 1'b0;
cnt <= cnt - 13'h0008;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= RX_PACKET2;
end
RX_PACKET2 : begin
go <= 1'b0;
cnt <= cnt - 13'h0008;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
state <= RX_PACKET3;
end
RX_PACKET3 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
if (cnt == 13'h0010) begin
state <= RX_PACKET4;
end else begin
cnt <= cnt - 13'h0008;
state <= RX_PACKET3;
end
end
RX_PACKET4 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET5;
end
RX_PACKET5 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET6;
end
RX_PACKET6 : begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET_WAIT_FOR_ACK;
end
RX_PACKET_WAIT_FOR_ACK : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
if(ack) begin
go <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full)
state <= RX_DESC;
else
state <= RX_DESC_WAIT;
end else begin
go <= 1'b1;
state <= RX_PACKET_WAIT_FOR_ACK;
end
end
RX_DESC_WAIT : begin
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full)
state <= RX_DESC;
else
state <= RX_DESC_WAIT;
end
// start of RX desc flow
RX_DESC : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// data will be swapped later
// dma_write_data_fifo_data[63:0] <= {56'h00_0000_0000_0000,8'h01};
dma_write_data_fifo_data[63:0] <= 64'hFFFF_FFFF_FFFF_FFFF;
state <= RX_DESC2;
end
RX_DESC2 : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b1;
dma_write_data_fifo_wren <= 1'b1;
// dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
// Write Round number in RX desc. It's used as debug info
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0],RoundNumber[31:0]};
state <= WAIT_FOR_ACK;
end
default: begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= IDLE;
end
endcase
end
end
// update dmawad_next_1st and RoundNumber_next for RX path 1
always@(posedge clk) begin
if(~buf_inuse | rst_reg) begin
dmawad_next_1st <= RXBuf_1stAddr_r1;
RoundNumber_next <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b00)) begin
// if end of RX buf is arrived, dmawad_next_1st will return to start address at next cycle
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
dmawad_next_1st <= RXBuf_1stAddr_r1;
RoundNumber_next <= RoundNumber + 32'h0000_0001;
end else begin
dmawad_next_1st <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
RoundNumber_next <= RoundNumber_next;
end
end else begin
dmawad_next_1st <= dmawad_next_1st;
RoundNumber_next <= RoundNumber_next;
end
end
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 2
always@(posedge clk) begin
if(~buf_inuse_2nd | rst_reg) begin
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
RoundNumber_next_2nd <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b01)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
RoundNumber_next_2nd <= RoundNumber_2nd + 32'h0000_0001;
end else begin
dmawad_next_2nd <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
RoundNumber_next_2nd <= RoundNumber_next_2nd;
end
end else begin
dmawad_next_2nd <= dmawad_next_2nd;
RoundNumber_next_2nd <= RoundNumber_next_2nd;
end
end
// update dmawad_next_3rd and RoundNumber_next_3rd for RX path 3
always@(posedge clk) begin
if(~buf_inuse_3rd | rst_reg) begin
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
RoundNumber_next_3rd <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b10)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
RoundNumber_next_3rd <= RoundNumber_3rd + 32'h0000_0001;
end else begin
dmawad_next_3rd <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
RoundNumber_next_3rd <= RoundNumber_next_3rd;
end
end else begin
dmawad_next_3rd <= dmawad_next_3rd;
RoundNumber_next_3rd <= RoundNumber_next_3rd;
end
end
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 4
always@(posedge clk) begin
if(~buf_inuse_4th | rst_reg) begin
dmawad_next_4th <= RXBuf_4thAddr_r1;
RoundNumber_next_4th <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b11)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
dmawad_next_4th <= RXBuf_4thAddr_r1;
RoundNumber_next_4th <= RoundNumber_4th + 32'h0000_0001;
end else begin
dmawad_next_4th <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
RoundNumber_next_4th <= RoundNumber_next_4th;
end
end else begin
dmawad_next_4th <= dmawad_next_4th;
RoundNumber_next_4th <= RoundNumber_next_4th;
end
end
// update dmawad_now for RX path 1
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_1st <= dmawad_next_1st;
dmawad_now2_1st <= dmawad_next_1st;
RoundNumber <= RoundNumber_next;
end else begin
dmawad_now1_1st <= dmawad_now1_1st;
dmawad_now2_1st <= dmawad_now2_1st;
RoundNumber <= RoundNumber;
end
end
// update dmawad_now_2nd for RX path 2
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_2nd <= dmawad_next_2nd;
dmawad_now2_2nd <= dmawad_next_2nd;
RoundNumber_2nd <= RoundNumber_next_2nd;
end else begin
dmawad_now1_2nd <= dmawad_now1_2nd;
dmawad_now2_2nd <= dmawad_now2_2nd;
RoundNumber_2nd <= RoundNumber_2nd;
end
end
// update dmawad_now_3rd for RX path 3
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_3rd <= dmawad_next_3rd;
dmawad_now2_3rd <= dmawad_next_3rd;
RoundNumber_3rd <= RoundNumber_next_3rd;
end else begin
dmawad_now1_3rd <= dmawad_now1_3rd;
dmawad_now2_3rd <= dmawad_now2_3rd;
RoundNumber_3rd <= RoundNumber_3rd;
end
end
// update dmawad_now_4th for RX path 4
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_4th <= dmawad_next_4th;
dmawad_now2_4th <= dmawad_next_4th;
RoundNumber_4th <= RoundNumber_next_4th;
end else begin
dmawad_now1_4th <= dmawad_now1_4th;
dmawad_now2_4th <= dmawad_now2_4th;
RoundNumber_4th <= RoundNumber_4th;
end
end
// dmawad output
always@(posedge clk) begin
if(rst_reg) begin
dmawad <= 64'h0000_0000_0000_0000;
end else if (state == TX_DESC_WRITE_BACK) begin
dmawad <= DescAddr;
end else if (state == RX_CLEAR) begin
if (pathindex_inturn[1] == 1'b0) begin
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b00
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
dmawad <= RXBuf_1stAddr_r1;
end else begin
dmawad <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
end
end else begin // pathindex_inturn == 2'b01
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
dmawad <= RXBuf_2ndAddr_r1;
end else begin
dmawad <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
end
end
end else begin
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b10
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
dmawad <= RXBuf_3rdAddr_r1;
end else begin
dmawad <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
end
end else begin // pathindex_inturn == 2'b11
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
dmawad <= RXBuf_4thAddr_r1;
end else begin
dmawad <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
end
end
end
end else if (state == RX_PACKET) begin // calculation
dmawad <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_1st + 64'h0000_0000_0000_0010 : dmawad_now1_2nd + 64'h0000_0000_0000_0010
)
: ( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_3rd + 64'h0000_0000_0000_0010 : dmawad_now1_4th + 64'h0000_0000_0000_0010
);
end else if (state == RX_DESC) begin
dmawad <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_1st : dmawad_now1_2nd
)
: ( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_3rd : dmawad_now1_4th
);
end else begin
dmawad <= dmawad;
end
end
// length output value from state machine
always@(posedge clk) begin
if(rst_reg)
length_byte[12:0] <= 13'h0000;
else if (state == TX_DESC_WRITE_BACK)
length_byte[12:0] <= TX_DESC_SIZE_BYTES[12:0];
else if (state == RX_CLEAR)
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
else if (state == RX_PACKET)
length_byte[12:0] <= frame_size_bytes[12:0];
else if (state == RX_DESC)
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
else
length_byte <= length_byte;
end
assign length[9:0] = length_byte[11:2];
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:user:KeyboardCtrl:1.0
// IP Revision: 2
(* X_CORE_INFO = "KeyboardCtrl,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "KeyboardCtrl_0,KeyboardCtrl,{}" *)
(* CORE_GENERATION_INFO = "KeyboardCtrl_0,KeyboardCtrl,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=KeyboardCtrl,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,SYSCLK_FREQUENCY_HZ=100000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module KeyboardCtrl_0 (
key_in,
is_extend,
is_break,
valid,
err,
PS2_DATA,
PS2_CLK,
rst,
clk
);
output wire [7 : 0] key_in;
output wire is_extend;
output wire is_break;
output wire valid;
output wire err;
inout wire PS2_DATA;
inout wire PS2_CLK;
input wire rst;
input wire clk;
KeyboardCtrl #(
.SYSCLK_FREQUENCY_HZ(100000000)
) inst (
.key_in(key_in),
.is_extend(is_extend),
.is_break(is_break),
.valid(valid),
.err(err),
.PS2_DATA(PS2_DATA),
.PS2_CLK(PS2_CLK),
.rst(rst),
.clk(clk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_1_V
`define SKY130_FD_SC_HVL__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_1_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
addRecFNToRaw#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input subOp,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [2:0] roundingMode,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig
);
`include "HardFloat_localFuncs.vi"
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam alignDistWidth = clog2(sigWidth);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire effSignB = subOp ? !signB : signB;
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire eqSigns = (signA == effSignB);
wire notEqSigns_signZero = (roundingMode == `round_min) ? 1 : 0;
wire signed [(expWidth + 1):0] sDiffExps = sExpA - sExpB;
wire [(alignDistWidth - 1):0] modNatAlignDist =
(sDiffExps < 0) ? sExpB - sExpA : sDiffExps;
wire isMaxAlign =
(sDiffExps>>>alignDistWidth != 0)
&& ((sDiffExps>>>alignDistWidth != -1)
|| (sDiffExps[(alignDistWidth - 1):0] == 0));
wire [(alignDistWidth - 1):0] alignDist =
isMaxAlign ? (1<<alignDistWidth) - 1 : modNatAlignDist;
wire closeSubMags = !eqSigns && !isMaxAlign && (modNatAlignDist <= 1);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [(sigWidth + 2):0] close_alignedSigA =
((0 <= sDiffExps) && sDiffExps[0] ? sigA<<2 : 0)
| ((0 <= sDiffExps) && !sDiffExps[0] ? sigA<<1 : 0)
| ((sDiffExps < 0) ? sigA : 0);
wire signed [(sigWidth + 2):0] close_sSigSum =
close_alignedSigA - (sigB<<1);
wire [(sigWidth + 1):0] close_sigSum =
(close_sSigSum < 0) ? -close_sSigSum : close_sSigSum;
wire [(sigWidth + 1 + (sigWidth & 1)):0] close_adjustedSigSum =
close_sigSum<<(sigWidth & 1);
wire [(sigWidth + 1)/2:0] close_reduced2SigSum;
compressBy2#(sigWidth + 2 + (sigWidth & 1))
compressBy2_close_sigSum(close_adjustedSigSum, close_reduced2SigSum);
wire [(alignDistWidth - 1):0] close_normDistReduced2;
countLeadingZeros#((sigWidth + 3)/2, alignDistWidth)
countLeadingZeros_close(close_reduced2SigSum, close_normDistReduced2);
wire [(alignDistWidth - 1):0] close_nearNormDist =
close_normDistReduced2<<1;
wire [(sigWidth + 2):0] close_sigOut =
(close_sigSum<<close_nearNormDist)<<1;
wire close_totalCancellation =
!(|close_sigOut[(sigWidth + 2):(sigWidth + 1)]);
wire close_notTotalCancellation_signOut = signA ^ (close_sSigSum < 0);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire far_signOut = (sDiffExps < 0) ? effSignB : signA;
wire [(sigWidth - 1):0] far_sigLarger = (sDiffExps < 0) ? sigB : sigA;
wire [(sigWidth - 1):0] far_sigSmaller = (sDiffExps < 0) ? sigA : sigB;
wire [(sigWidth + 4):0] far_mainAlignedSigSmaller =
{far_sigSmaller, 5'b0}>>alignDist;
wire [(sigWidth + 1)/4:0] far_reduced4SigSmaller;
compressBy4#(sigWidth + 2)
compressBy4_far_sigSmaller(
{far_sigSmaller, 2'b00}, far_reduced4SigSmaller);
wire [(sigWidth + 1)/4:0] far_roundExtraMask;
lowMaskHiLo#(alignDistWidth - 2, (sigWidth + 5)/4, 0)
lowMask_far_roundExtraMask(
alignDist[(alignDistWidth - 1):2], far_roundExtraMask);
wire [(sigWidth + 2):0] far_alignedSigSmaller =
{far_mainAlignedSigSmaller>>3,
(|far_mainAlignedSigSmaller[2:0])
|| (|(far_reduced4SigSmaller & far_roundExtraMask))};
wire far_subMags = !eqSigns;
wire [(sigWidth + 3):0] far_negAlignedSigSmaller =
far_subMags ? {1'b1, ~far_alignedSigSmaller}
: {1'b0, far_alignedSigSmaller};
wire [(sigWidth + 3):0] far_sigSum =
(far_sigLarger<<3) + far_negAlignedSigSmaller + far_subMags;
wire [(sigWidth + 2):0] far_sigOut =
far_subMags ? far_sigSum : far_sigSum>>1 | far_sigSum[0];
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notSigNaN_invalidExc = isInfA && isInfB && !eqSigns;
wire notNaN_isInfOut = isInfA || isInfB;
wire addZeros = isZeroA && isZeroB;
wire notNaN_specialCase = notNaN_isInfOut || addZeros;
wire notNaN_isZeroOut =
addZeros
|| (!notNaN_isInfOut && closeSubMags && close_totalCancellation);
wire notNaN_signOut =
(eqSigns && signA )
|| (isInfA && signA )
|| (isInfB && effSignB )
|| (notNaN_isZeroOut && !eqSigns && notEqSigns_signZero)
|| (!notNaN_specialCase && closeSubMags && !close_totalCancellation
&& close_notTotalCancellation_signOut)
|| (!notNaN_specialCase && !closeSubMags && far_signOut);
wire signed [(expWidth + 1):0] common_sExpOut =
(closeSubMags || (sDiffExps < 0) ? sExpB : sExpA)
- (closeSubMags ? close_nearNormDist : far_subMags);
wire [(sigWidth + 2):0] common_sigOut =
closeSubMags ? close_sigOut : far_sigOut;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign invalidExc = isSigNaNA || isSigNaNB || notSigNaN_invalidExc;
assign out_isInf = notNaN_isInfOut;
assign out_isZero = notNaN_isZeroOut;
assign out_sExp = common_sExpOut;
`ifdef HardFloat_propagateNaNPayloads
assign out_isNaN = isNaNA || isNaNB || notSigNaN_invalidExc;
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_add#(sigWidth)
propagateNaN(
control,
subOp,
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
signNaN,
fractNaN
);
assign out_sign = out_isNaN ? signNaN : notNaN_signOut;
assign out_sig = out_isNaN ? {1'b1, fractNaN, 2'b00} : common_sigOut;
`else
assign out_isNaN = isNaNA || isNaNB;
assign out_sign = notNaN_signOut;
assign out_sig = common_sigOut;
`endif
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
addRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input subOp,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [2:0] roundingMode,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
addRecFNToRaw#(expWidth, sigWidth)
addRecFNToRaw(
control,
subOp,
a,
b,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
roundRawFNToRecFN#(expWidth, sigWidth, `flRoundOpt_subnormsAlwaysExact)
roundRawOut(
control,
invalidExc,
1'b0,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingMode,
out,
exceptionFlags
);
endmodule
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax).
begin end
endtask
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// Internal PCPI Cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
generate if (ENABLE_FAST_MUL) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (ENABLE_MUL) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (ENABLE_DIV) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
ENABLE_PCPI && pcpi_ready: begin
pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
end
(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
ENABLE_DIV && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// Memory Interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // C.LW
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // C.ADDI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // C.LI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // C.LUI
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (COMPRESSED_ISA && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (COMPRESSED_ISA && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// Instruction Decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_uj;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef DEBUGASM
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // C.LW
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // C.SW
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // C.JAL
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // C.LI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // C.LUI
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_uj;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
end
end
// Main State Machine
localparam cpu_state_trap = 8'b10000000;
localparam cpu_state_fetch = 8'b01000000;
localparam cpu_state_ld_rs1 = 8'b00100000;
localparam cpu_state_ld_rs2 = 8'b00010000;
localparam cpu_state_exec = 8'b00001000;
localparam cpu_state_shift = 8'b00000100;
localparam cpu_state_stmem = 8'b00000010;
localparam cpu_state_ldmem = 8'b00000001;
reg [7:0] cpu_state;
reg [1:0] irq_state;
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = COMPRESSED_ISA;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef PICORV32_REGS
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
`PICORV32_REGS cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (WITH_PCPI && CATCH_ILLINSN) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (ENABLE_COUNTERS) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!ENABLE_TRACE)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
if (ENABLE_COUNTERS)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~STACKADDR) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= STACKADDR;
end
cpu_state <= cpu_state_fetch;
end else
(* parallel_case, full_case *)
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
ENABLE_IRQ && irq_state[0]: begin
current_pc = PROGADDR_IRQ;
irq_active <= 1;
mem_do_rinst <= 1;
end
ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (ENABLE_IRQ_QREGS)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
latched_trace <= 1;
if (ENABLE_COUNTERS) begin
count_instr <= count_instr + 1;
if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_uj;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
pcpi_valid <= 1;
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && ENABLE_COUNTERS64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && ENABLE_COUNTERS64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | MASKED_IRQ;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (ENABLE_TRACE)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (!CATCH_MISALIGN) begin
if (COMPRESSED_ISA) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef RISCV_FORMAL
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// Formal Verification
`ifdef FORMAL
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
// This is a simple example implementation of PICORV32_REGS.
// Use the PICORV32_REGS mechanism if you want to use custom
// memory resources to implement the processor register file.
// Note that your implementation must match the requirements of
// the PicoRV32 configuration. (e.g. QREGS, etc)
module picorv32_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:30];
always @(posedge clk)
if (wen) regs[~waddr[4:0]] <= wdata;
assign rdata1 = regs[~raddr1[4:0]];
assign rdata2 = regs[~raddr2[4:0]];
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
parameter STEPS_AT_ONCE = 1,
parameter CARRY_CHAIN = 4
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg pcpi_wait_q;
wire mul_start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_mul <= 0;
instr_mulh <= 0;
instr_mulhsu <= 0;
instr_mulhu <= 0;
if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b000: instr_mul <= 1;
3'b001: instr_mulh <= 1;
3'b010: instr_mulhsu <= 1;
3'b011: instr_mulhu <= 1;
endcase
end
pcpi_wait <= instr_any_mul;
pcpi_wait_q <= pcpi_wait;
end
reg [63:0] rs1, rs2, rd, rdx;
reg [63:0] next_rs1, next_rs2, this_rs2;
reg [63:0] next_rd, next_rdx, next_rdt;
reg [6:0] mul_counter;
reg mul_waiting;
reg mul_finish;
integer i, j;
// carry save accumulator
always @* begin
next_rd = rd;
next_rdx = rdx;
next_rs1 = rs1;
next_rs2 = rs2;
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
this_rs2 = next_rs1[0] ? next_rs2 : 0;
if (CARRY_CHAIN == 0) begin
next_rdt = next_rd ^ next_rdx ^ this_rs2;
next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
next_rd = next_rdt;
end else begin
next_rdt = 0;
for (j = 0; j < 64; j = j + CARRY_CHAIN)
{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
next_rdx = next_rdt << 1;
end
next_rs1 = next_rs1 >> 1;
next_rs2 = next_rs2 << 1;
end
end
always @(posedge clk) begin
mul_finish <= 0;
if (!resetn) begin
mul_waiting <= 1;
end else
if (mul_waiting) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
rd <= 0;
rdx <= 0;
mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
mul_waiting <= !mul_start;
end else begin
rd <= next_rd;
rdx <= next_rdx;
rs1 <= next_rs1;
rs2 <= next_rs2;
mul_counter <= mul_counter - STEPS_AT_ONCE;
if (mul_counter[6]) begin
mul_finish <= 1;
mul_waiting <= 1;
end
end
end
always @(posedge clk) begin
pcpi_wr <= 0;
pcpi_ready <= 0;
if (mul_finish && resetn) begin
pcpi_wr <= 1;
pcpi_ready <= 1;
pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
end
end
endmodule
module picorv32_pcpi_fast_mul #(
parameter EXTRA_MUL_FFS = 0,
parameter EXTRA_INSN_FFS = 0,
parameter MUL_CLKGATE = 0
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output pcpi_wr,
output [31:0] pcpi_rd,
output pcpi_wait,
output pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg shift_out;
reg [3:0] active;
reg [32:0] rs1, rs2, rs1_q, rs2_q;
reg [63:0] rd, rd_q;
wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
reg pcpi_insn_valid_q;
always @* begin
instr_mul = 0;
instr_mulh = 0;
instr_mulhsu = 0;
instr_mulhu = 0;
if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
case (pcpi_insn[14:12])
3'b000: instr_mul = 1;
3'b001: instr_mulh = 1;
3'b010: instr_mulhsu = 1;
3'b011: instr_mulhu = 1;
endcase
end
end
always @(posedge clk) begin
pcpi_insn_valid_q <= pcpi_insn_valid;
if (!MUL_CLKGATE || active[0]) begin
rs1_q <= rs1;
rs2_q <= rs2;
end
if (!MUL_CLKGATE || active[1]) begin
rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
end
if (!MUL_CLKGATE || active[2]) begin
rd_q <= rd;
end
end
always @(posedge clk) begin
if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
active[0] <= 1;
end else begin
active[0] <= 0;
end
active[3:1] <= active;
shift_out <= instr_any_mulh;
if (!resetn)
active <= 0;
end
assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
assign pcpi_wait = 0;
assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
`ifdef RISCV_FORMAL_ALTOPS
assign pcpi_rd =
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
`else
assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
`endif
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_div, instr_divu, instr_rem, instr_remu;
wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
reg pcpi_wait_q;
wire start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_div <= 0;
instr_divu <= 0;
instr_rem <= 0;
instr_remu <= 0;
if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b100: instr_div <= 1;
3'b101: instr_divu <= 1;
3'b110: instr_rem <= 1;
3'b111: instr_remu <= 1;
endcase
end
pcpi_wait <= instr_any_div_rem && resetn;
pcpi_wait_q <= pcpi_wait && resetn;
end
reg [31:0] dividend;
reg [62:0] divisor;
reg [31:0] quotient;
reg [31:0] quotient_msk;
reg running;
reg outsign;
always @(posedge clk) begin
pcpi_ready <= 0;
pcpi_wr <= 0;
pcpi_rd <= 'bx;
if (!resetn) begin
running <= 0;
end else
if (start) begin
running <= 1;
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
quotient <= 0;
quotient_msk <= 1 << 31;
end else
if (!quotient_msk && running) begin
running <= 0;
pcpi_ready <= 1;
pcpi_wr <= 1;
`ifdef RISCV_FORMAL_ALTOPS
case (1)
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
endcase
`else
if (instr_div || instr_divu)
pcpi_rd <= outsign ? -quotient : quotient;
else
pcpi_rd <= outsign ? -dividend : dividend;
`endif
end else begin
if (divisor <= dividend) begin
dividend <= dividend - divisor;
quotient <= quotient | quotient_msk;
end
divisor <= divisor >> 1;
`ifdef RISCV_FORMAL_ALTOPS
quotient_msk <= quotient_msk >> 5;
`else
quotient_msk <= quotient_msk >> 1;
`endif
end
end
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output trap,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_rdata;
picorv32_axi_adapter axi_adapter (
.clk (clk ),
.resetn (resetn ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
input clk, resetn,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Native PicoRV32 memory interface
input mem_valid,
input mem_instr,
output mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
always @(posedge clk) begin
if (!resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_valid && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_valid) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// File : register_bank.v
// Creation date : 16.05.2017
// Creation time : 11:39:39
// Description : Stores registers and the logic needed to access them. In case of multiple simultaenous writes, the one with most priority is done.
// Created by : TermosPullo
// Tool : Kactus2 3.4.106 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:cpu.logic:register_bank:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic/register_bank/1.0/register_bank.1.0.xml
//-----------------------------------------------------------------------------
module register_bank #(
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter REGISTER_ID_WIDTH = 4, // Bits reserved for identification a single register.
parameter REGISTER_COUNT = 8 // How many registers are supported in the core.
) (
// Interface: cpu_clk_sink
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// Interface: cpu_system
input alu_active_i,
input [DATA_WIDTH-1:0] alu_result_i,
input [REGISTER_ID_WIDTH-1:0] choose_register_i1,
input [REGISTER_ID_WIDTH-1:0] choose_register_i2,
input [DATA_WIDTH-1:0] load_value_i,
input mem_read_rdy_i,
input register_active_i,
input [DATA_WIDTH-1:0] register_input,
output reg [DATA_WIDTH-1:0] register_output1,
output reg [DATA_WIDTH-1:0] register_output2
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The registers.
reg [DATA_WIDTH-1:0] registers [REGISTER_COUNT-1:0];
// Iterator for the reset
integer index;
always @* begin
// Select new output when ever registers are activated.
register_output1 <= registers[choose_register_i1];
register_output2 <= registers[choose_register_i2];
end
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
for (index = 0; index < REGISTER_COUNT; index = index + 1) begin
registers[index] <= 0;
end
end
else begin
if (alu_active_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= alu_result_i;
end
else if (mem_read_rdy_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= load_value_i;
end
else if (register_active_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= register_input[DATA_WIDTH-1:0];
end
end
end
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of K580WT57 DMA controller
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wt57.v
//
// Warning: This realization is not fully operational.
module k580wt57(
input clk,
input ce,
input reset,
input[3:0] iaddr,
input[7:0] idata,
input[3:0] drq,
input iwe_n,
input ird_n,
input hlda,
output hrq,
output reg[3:0] dack,
output[7:0] odata,
output[15:0] oaddr,
output owe_n,
output ord_n,
output oiowe_n,
output oiord_n );
parameter ST_IDLE = 3'b000;
parameter ST_WAIT = 3'b001;
parameter ST_T1 = 3'b010;
parameter ST_T2 = 3'b011;
parameter ST_T3 = 3'b100;
parameter ST_T4 = 3'b101;
parameter ST_T5 = 3'b110;
parameter ST_T6 = 3'b111;
reg[2:0] state;
reg[1:0] channel;
reg[7:0] mode;
reg[4:0] chstate;
reg[15:0] chaddr[3:0];
reg[15:0] chtcnt[3:0];
reg ff,exiwe_n;
assign hrq = state!=ST_IDLE;
assign odata = {3'b0,chstate};
assign oaddr = chaddr[channel];
assign owe_n = chtcnt[channel][14]==0 || state!=ST_T2;
assign ord_n = chtcnt[channel][15]==0 || (state!=ST_T1 && state!=ST_T2);
assign oiowe_n = chtcnt[channel][15]==0 || state!=ST_T2;
assign oiord_n = chtcnt[channel][14]==0 || (state!=ST_T1 && state!=ST_T2);
wire[3:0] mdrq = drq & mode[3:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; ff <= 0; mode <= 0; exiwe_n <= 1'b1;
chstate <= 0; dack <= 0;
end else begin
exiwe_n <= iwe_n;
if (iwe_n && ~exiwe_n) begin
ff <= ~(ff|iaddr[3]);
if (ff) begin
if(iaddr==4'b0000) chaddr[0][15:8] <= idata;
if(iaddr==4'b0001) chtcnt[0][15:8] <= idata;
if(iaddr==4'b0010) chaddr[1][15:8] <= idata;
if(iaddr==4'b0011) chtcnt[1][15:8] <= idata;
if(iaddr==4'b0100) chaddr[2][15:8] <= idata;
if(iaddr==4'b0101) chtcnt[2][15:8] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][15:8] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][15:8] <= idata;
end else begin
if(iaddr==4'b0000) chaddr[0][7:0] <= idata;
if(iaddr==4'b0001) chtcnt[0][7:0] <= idata;
if(iaddr==4'b0010) chaddr[1][7:0] <= idata;
if(iaddr==4'b0011) chtcnt[1][7:0] <= idata;
if(iaddr==4'b0100) chaddr[2][7:0] <= idata;
if(iaddr==4'b0101) chtcnt[2][7:0] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][7:0] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][7:0] <= idata;
end
if (iaddr[3]) mode <= idata;
end
if (ce) begin
case (state)
ST_IDLE: begin
if (|mdrq) state <= ST_WAIT;
end
ST_WAIT: begin
if (hlda) state <= ST_T1;
casex (mdrq[3:1])
3'b1xx: channel <= 2'b11;
3'b01x: channel <= 2'b10;
3'b001: channel <= 2'b01;
3'b000: channel <= 2'b00;
endcase
end
ST_T1: begin
state <= ST_T2;
dack[channel] <= 1'b1;
end
ST_T2: begin
if (mdrq[channel]==0) begin
dack[channel] <= 0;
if (chtcnt[channel][13:0]==0) begin
chstate[channel] <= 1'b1;
if (mode[7]==1'b1 && channel==2'b10) begin
chaddr[channel] <= chaddr[2'b11];
chtcnt[channel][13:0] <= chtcnt[2'b11][13:0];
end
end else begin
chaddr[channel] <= chaddr[channel]+1'b1;
chtcnt[channel][13:0] <= chtcnt[channel][13:0]+14'h3FFF;
end
state <= ST_T3;
end
end
ST_T3: begin
state <= |mdrq ? ST_WAIT : ST_IDLE;
end
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_SYMBOL_V
`define SKY130_FD_SC_HD__O2111A_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_SYMBOL_V
|
`timescale 1 ps / 1 ps
//altera message_off 10230
module alt_mem_ddrx_csr #
( parameter
DWIDTH_RATIO = 2,
CTL_CSR_ENABLED = 1,
CTL_ECC_CSR_ENABLED = 1,
CTL_CSR_READ_ONLY = 0,
CTL_ECC_CSR_READ_ONLY = 0,
CFG_AVALON_ADDR_WIDTH = 8,
CFG_AVALON_DATA_WIDTH = 32,
MEM_IF_CLK_PAIR_COUNT = 1,
MEM_IF_DQS_WIDTH = 72,
CFG_CS_ADDR_WIDTH = 1, // same as MEM_IF_CHIP
CFG_ROW_ADDR_WIDTH = 13, // max supported row bits
CFG_COL_ADDR_WIDTH = 10, // max supported column bits
CFG_BANK_ADDR_WIDTH = 3, // max supported bank bits
CFG_ENABLE_ECC = 1,
CFG_ENABLE_AUTO_CORR = 1,
CFG_REGDIMM_ENABLE = 0,
// timing parameter width
CAS_WR_LAT_BUS_WIDTH = 4, // max will be 8 in DDR3
ADD_LAT_BUS_WIDTH = 3, // max will be 6 in DDR2
TCL_BUS_WIDTH = 4, // max will be 11 in DDR3
BL_BUS_WIDTH = 5, //
TRRD_BUS_WIDTH = 4, // 2 - 8
TFAW_BUS_WIDTH = 6, // 6 - 32
TRFC_BUS_WIDTH = 8, // 12 - 140?
TREFI_BUS_WIDTH = 13, // 780 - 6240
TRCD_BUS_WIDTH = 4, // 2 - 11
TRP_BUS_WIDTH = 4, // 2 - 11
TWR_BUS_WIDTH = 4, // 2 - 12
TWTR_BUS_WIDTH = 4, // 1 - 10
TRTP_BUS_WIDTH = 4, // 2 - 8
TRAS_BUS_WIDTH = 5, // 4 - 29
TRC_BUS_WIDTH = 6, // 8 - 40
AUTO_PD_BUS_WIDTH = 16, // same as CSR interface
STARVE_LIMIT_BUS_WIDTH = 8,
// timing parameter
CFG_CAS_WR_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_ADD_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_TCL = 0, // these timing parameter must be set properly for controller to work
CFG_BURST_LENGTH = 0, // these timing parameter must be set properly for controller to work
CFG_TRRD = 0, // these timing parameter must be set properly for controller to work
CFG_TFAW = 0, // these timing parameter must be set properly for controller to work
CFG_TRFC = 0, // these timing parameter must be set properly for controller to work
CFG_TREFI = 0, // these timing parameter must be set properly for controller to work
CFG_TRCD = 0, // these timing parameter must be set properly for controller to work
CFG_TRP = 0, // these timing parameter must be set properly for controller to work
CFG_TWR = 0, // these timing parameter must be set properly for controller to work
CFG_TWTR = 0, // these timing parameter must be set properly for controller to work
CFG_TRTP = 0, // these timing parameter must be set properly for controller to work
CFG_TRAS = 0, // these timing parameter must be set properly for controller to work
CFG_TRC = 0, // these timing parameter must be set properly for controller to work
CFG_AUTO_PD_CYCLES = 0, // these timing parameter must be set properly for controller to work
// parameters used by input interface
CFG_ADDR_ORDER = 1, // normally we will use '1' for chip, bank, row, column arrangement
CFG_REORDER_DATA = 0,
CFG_STARVE_LIMIT = 0,
MEM_IF_CSR_COL_WIDTH = 5,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 3,
MEM_IF_CSR_CS_WIDTH = 3
)
(
ctl_clk,
ctl_rst_n,
// csr interface (Avalon)
avalon_mm_addr,
avalon_mm_be,
avalon_mm_write,
avalon_mm_wdata,
avalon_mm_read,
avalon_mm_rdata,
avalon_mm_rdata_valid,
avalon_mm_waitrequest,
// input from PHY
sts_cal_success,
sts_cal_fail,
// input from state machine
local_power_down_ack,
local_self_rfsh_ack,
// input from ecc
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
// output to PHY
cfg_cal_req,
cfg_clock_off,
ctl_cal_byte_lane_sel_n,
// output to timer
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_burst_length,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_auto_pd_cycles,
// output to input interface
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// output to ecc
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// output to others
cfg_regdimm_enable,
cfg_reorder_data,
cfg_starve_limit
);
localparam integer CFG_MEM_IF_CS_WIDTH = (2**CFG_CS_ADDR_WIDTH);
input ctl_clk;
input ctl_rst_n;
input avalon_mm_write;
input avalon_mm_read;
input [CFG_AVALON_ADDR_WIDTH - 1 : 0] avalon_mm_addr;
input [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_wdata;
input [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] avalon_mm_be;
output avalon_mm_waitrequest;
output avalon_mm_rdata_valid;
output [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
// input from AFI
input sts_cal_success;
input sts_cal_fail;
// input from state machine
input local_power_down_ack;
input local_self_rfsh_ack;
// input from ecc
input sts_sbe_error;
input sts_dbe_error;
input sts_corr_dropped;
input [7 : 0] sts_sbe_count;
input [7 : 0] sts_dbe_count;
input [7 : 0] sts_corr_dropped_count;
input [31 : 0] sts_err_addr;
input [31 : 0] sts_corr_dropped_addr;
// output to PHY
output cfg_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
output [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
output [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
output [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
output [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
output [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
output [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
output [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
output [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
output [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
output [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
output [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
output [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
output [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
output [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
output [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
output [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
output [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
output [1 : 0] cfg_addr_order;
output cfg_reorder_data;
output [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
output [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
output [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
output [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
output [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
output cfg_enable_ecc;
output cfg_enable_auto_corr;
output cfg_gen_sbe;
output cfg_gen_dbe;
output cfg_enable_intr;
output cfg_mask_sbe_intr;
output cfg_mask_dbe_intr;
output cfg_mask_corr_dropped_intr;
output cfg_clr_intr;
output cfg_regdimm_enable;
wire avalon_mm_waitrequest;
wire avalon_mm_rdata_valid;
wire [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
reg int_write_req;
reg int_read_req;
reg int_rdata_valid;
reg [8 - 1 : 0] int_addr; // hard-coded to only 8 bits
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_wdata;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_rdata;
reg [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] int_be;
reg int_mask_avalon_mm_write;
reg int_mask_avalon_mm_read;
reg int_mask_ecc_avalon_mm_write;
reg int_mask_ecc_avalon_mm_read;
// output to PHY
wire cfg_cal_req;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
wire [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
wire [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
wire [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
wire [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
wire [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
wire [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
wire [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
wire [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
wire [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
wire [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
wire [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
wire [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
wire [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
wire [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
wire [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
wire [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
wire [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
wire [1 : 0] cfg_addr_order;
wire cfg_reorder_data;
wire [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
wire [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
wire [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
wire [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_mask_corr_dropped_intr;
wire cfg_clr_intr;
// output to others
wire cfg_regdimm_enable;
// CSR read registers
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_100;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_110;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_120;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_121;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_122;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_123;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_124;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_125;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_126;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_130;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_131;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_132;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_133;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_134;
/*------------------------------------------------------------------------------
CSR Interface
------------------------------------------------------------------------------*/
// Assign waitrequest signal to '0'
assign avalon_mm_waitrequest = 1'b0;
generate
if (!CTL_CSR_ENABLED && !CTL_ECC_CSR_ENABLED)
begin
// when both csr and ecc csr is disabled
assign avalon_mm_rdata = 0;
assign avalon_mm_rdata_valid = 0;
end
else
begin
// register all inputs
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_write_req <= 0;
int_read_req <= 0;
int_addr <= 0;
int_wdata <= 0;
int_be <= 0;
end
else
begin
int_addr <= avalon_mm_addr [7 : 0]; // we only need the bottom 8 bits
int_wdata <= avalon_mm_wdata;
int_be <= avalon_mm_be;
if (avalon_mm_write)
int_write_req <= 1'b1;
else
int_write_req <= 1'b0;
if (avalon_mm_read)
int_read_req <= 1'b1;
else
int_read_req <= 1'b0;
end
end
// Write and read request mask
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
if (CTL_CSR_READ_ONLY)
begin
int_mask_avalon_mm_write <= 1'b1;
int_mask_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
end
if (CTL_ECC_CSR_READ_ONLY)
begin
int_mask_ecc_avalon_mm_write <= 1'b1;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Read Interface
------------------------------------------------------------------------------*/
assign avalon_mm_rdata = int_rdata;
assign avalon_mm_rdata_valid = int_rdata_valid;
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_rdata <= 0;
int_rdata_valid <= 0;
end
else
begin
if (int_read_req)
begin
if (int_addr == 8'h00)
int_rdata <= read_csr_register_100;
else if (int_addr == 8'h10)
int_rdata <= read_csr_register_110;
else if (int_addr == 8'h20)
int_rdata <= read_csr_register_120;
else if (int_addr == 8'h21)
int_rdata <= read_csr_register_121;
else if (int_addr == 8'h22)
int_rdata <= read_csr_register_122;
else if (int_addr == 8'h23)
int_rdata <= read_csr_register_123;
else if (int_addr == 8'h24)
int_rdata <= read_csr_register_124;
else if (int_addr == 8'h25)
int_rdata <= read_csr_register_125;
else if (int_addr == 8'h26)
int_rdata <= read_csr_register_126;
else if (int_addr == 8'h30)
int_rdata <= read_csr_register_130;
else if (int_addr == 8'h31)
int_rdata <= read_csr_register_131;
else if (int_addr == 8'h32)
int_rdata <= read_csr_register_132;
else if (int_addr == 8'h33)
int_rdata <= read_csr_register_133;
else if (int_addr == 8'h34)
int_rdata <= read_csr_register_134;
end
if (int_read_req)
int_rdata_valid <= 1'b1;
else
int_rdata_valid <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
CSR Registers
------------------------------------------------------------------------------*/
generate
genvar i;
if (!CTL_CSR_ENABLED) // when csr is disabled
begin
// assigning values to the top
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_cs_addr_width = CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_cal_req = 0;
assign cfg_clock_off = 0;
assign ctl_cal_byte_lane_sel_n = 0;
assign cfg_regdimm_enable = 1'b1; // udimm or rdimm determined by parameter CFG_REGDIMM_ENABLE
end
else
begin
/*------------------------------------------------------------------------------
0x100 ALTMEPHY Status and Control Register
------------------------------------------------------------------------------*/
reg csr_cal_success;
reg csr_cal_fail;
reg csr_cal_req;
reg [5 : 0] csr_clock_off;
// assign value back to top
assign cfg_cal_req = csr_cal_req;
assign cfg_clock_off = csr_clock_off [MEM_IF_CLK_PAIR_COUNT - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_req <= 0;
csr_clock_off <= 0;
end
else
begin
// write request
if (int_write_req && int_addr == 8'h00)
begin
if (int_be [0])
begin
csr_cal_req <= int_wdata [2] ;
end
if (int_be [1])
begin
csr_clock_off <= int_wdata [13 : 8];
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_success <= 0;
csr_cal_fail <= 0;
end
else
begin
csr_cal_success <= sts_cal_success;
csr_cal_fail <= sts_cal_fail;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_100 = 0;
// then we set individual bits
read_csr_register_100 [0] = csr_cal_success;
read_csr_register_100 [1] = csr_cal_fail;
read_csr_register_100 [2] = csr_cal_req;
read_csr_register_100 [13 : 8] = csr_clock_off;
end
/*------------------------------------------------------------------------------
0x110 Controller Status and Control Register
------------------------------------------------------------------------------*/
reg [15 : 0] csr_auto_pd_cycles;
reg csr_auto_pd_ack;
reg csr_self_rfsh; // yyong: remember to handle this
reg csr_self_rfsh_ack;
reg csr_ganged_arf; // yyong: remember to handle this
reg [1 : 0] csr_addr_order;
reg csr_reg_dimm; // yyong: remember to handle this
reg [1 : 0] csr_drate;
// assign value back to top
assign cfg_auto_pd_cycles = csr_auto_pd_cycles;
assign cfg_addr_order = csr_addr_order;
assign cfg_regdimm_enable = csr_reg_dimm;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_cycles <= CFG_AUTO_PD_CYCLES; // reset to default value
csr_self_rfsh <= 0;
csr_ganged_arf <= 0;
csr_addr_order <= CFG_ADDR_ORDER; // reset to default value
csr_reg_dimm <= CFG_REGDIMM_ENABLE; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h10)
begin
if (int_be [0])
begin
csr_auto_pd_cycles [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_auto_pd_cycles [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_self_rfsh <= int_wdata [17] ;
csr_ganged_arf <= int_wdata [19] ;
csr_addr_order <= int_wdata [21 : 20];
csr_reg_dimm <= int_wdata [22] ;
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_ack <= 0;
csr_self_rfsh_ack <= 0;
csr_drate <= 0;
end
else
begin
csr_auto_pd_ack <= local_power_down_ack;
csr_self_rfsh_ack <= local_self_rfsh_ack;
csr_drate <= (DWIDTH_RATIO == 2) ? 2'b00 : 2'b01; // Fullrate - 00, Halfrate - 01
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_110 = 0;
// then we set individual bits
read_csr_register_110 [15 : 0 ] = csr_auto_pd_cycles;
read_csr_register_110 [16] = csr_auto_pd_ack;
read_csr_register_110 [17] = csr_self_rfsh;
read_csr_register_110 [18] = csr_self_rfsh_ack;
read_csr_register_110 [19] = csr_ganged_arf;
read_csr_register_110 [21 : 20] = csr_addr_order;
read_csr_register_110 [22] = csr_reg_dimm;
read_csr_register_110 [24 : 23] = csr_drate;
end
/*------------------------------------------------------------------------------
0x120 Memory Address Sizes 0
------------------------------------------------------------------------------*/
reg [7 : 0] csr_col_width;
reg [7 : 0] csr_row_width;
reg [3 : 0] csr_bank_width;
reg [3 : 0] csr_chip_width;
// assign value back to top
assign cfg_cs_addr_width = csr_chip_width [MEM_IF_CSR_CS_WIDTH - 1 : 0];
assign cfg_bank_addr_width = csr_bank_width [MEM_IF_CSR_BANK_WIDTH - 1 : 0];
assign cfg_row_addr_width = csr_row_width [MEM_IF_CSR_ROW_WIDTH - 1 : 0];
assign cfg_col_addr_width = csr_col_width [MEM_IF_CSR_COL_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_col_width <= CFG_COL_ADDR_WIDTH; // reset to default value
csr_row_width <= CFG_ROW_ADDR_WIDTH; // reset to default value
csr_bank_width <= CFG_BANK_ADDR_WIDTH; // reset to default value
csr_chip_width <= CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h20)
begin
if (int_be [0])
begin
if (int_wdata [7 : 0] <= CFG_COL_ADDR_WIDTH)
begin
csr_col_width <= int_wdata [7 : 0 ];
end
end
if (int_be [1])
begin
if (int_wdata [15 : 8] <= CFG_ROW_ADDR_WIDTH)
begin
csr_row_width <= int_wdata [15 : 8 ];
end
end
if (int_be [2])
begin
if (int_wdata [19 : 16] <= CFG_BANK_ADDR_WIDTH)
begin
csr_bank_width <= int_wdata [19 : 16];
end
if (int_wdata [23 : 20] <= (CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0))
begin
csr_chip_width <= int_wdata [23 : 20];
end
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_120 = 0;
// then we set individual bits
read_csr_register_120 [7 : 0 ] = csr_col_width;
read_csr_register_120 [15 : 8 ] = csr_row_width;
read_csr_register_120 [19 : 16] = csr_bank_width;
read_csr_register_120 [23 : 20] = csr_chip_width;
end
/*------------------------------------------------------------------------------
0x121 Memory Address Sizes 1
------------------------------------------------------------------------------*/
reg [31 : 0] csr_data_binary_representation;
reg [7 : 0] csr_chip_binary_representation;
reg [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] cal_byte_lane;
// assign value back to top
assign ctl_cal_byte_lane_sel_n = ~cal_byte_lane;
// determine cal_byte_lane base on csr data
for (i = 0;i < CFG_MEM_IF_CS_WIDTH;i = i + 1)
begin : ctl_cal_byte_lane_per_chip
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= {MEM_IF_DQS_WIDTH{1'b1}}; // setting to all ones
else
begin
if (csr_chip_binary_representation[i])
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= csr_data_binary_representation [MEM_IF_DQS_WIDTH - 1 : 0];
else
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= 0;
end
end
end
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_data_binary_representation <= {MEM_IF_DQS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h21)
begin
if (int_be [0])
begin
csr_data_binary_representation [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_data_binary_representation [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_data_binary_representation [23 : 16] <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_data_binary_representation [31 : 24] <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_121 = 0;
// then we set individual bits
read_csr_register_121 [31 : 0 ] = csr_data_binary_representation;
end
/*------------------------------------------------------------------------------
0x122 Memory Address Sizes 2
------------------------------------------------------------------------------*/
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_chip_binary_representation <= {CFG_MEM_IF_CS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h22)
begin
if (int_be [0])
begin
csr_chip_binary_representation [ 7 : 0] <= int_wdata [7 : 0 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_122 = 0;
// then we set individual bits
read_csr_register_122 [7 : 0 ] = csr_chip_binary_representation;
end
/*------------------------------------------------------------------------------
0x123 Memory Timing Parameters Registers 0
------------------------------------------------------------------------------*/
reg [3 : 0] csr_trcd;
reg [3 : 0] csr_trrd;
reg [3 : 0] csr_trp;
reg [3 : 0] csr_tmrd; // yyong: might remove this
reg [7 : 0] csr_tras;
reg [7 : 0] csr_trc;
// assign value back to top
assign cfg_trcd = csr_trcd [TRCD_BUS_WIDTH - 1 : 0];
assign cfg_trrd = csr_trrd [TRRD_BUS_WIDTH - 1 : 0];
assign cfg_trp = csr_trp [TRP_BUS_WIDTH - 1 : 0];
assign cfg_tras = csr_tras [TRAS_BUS_WIDTH - 1 : 0];
assign cfg_trc = csr_trc [TRC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trcd <= CFG_TRCD; // reset to default value
csr_trrd <= CFG_TRRD; // reset to default value
csr_trp <= CFG_TRP; // reset to default value
csr_tmrd <= 0; // yyong: might remove this
csr_tras <= CFG_TRAS; // reset to default value
csr_trc <= CFG_TRC; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h23)
begin
if (int_be [0])
begin
csr_trcd <= int_wdata [3 : 0 ];
csr_trrd <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_trp <= int_wdata [11 : 8 ];
csr_tmrd <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_tras <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_trc <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_123 = 0;
// then we set individual bits
read_csr_register_123 [3 : 0 ] = csr_trcd;
read_csr_register_123 [7 : 4 ] = csr_trrd;
read_csr_register_123 [11 : 8 ] = csr_trp;
read_csr_register_123 [15 : 12] = csr_tmrd;
read_csr_register_123 [23 : 16] = csr_tras;
read_csr_register_123 [31 : 24] = csr_trc;
end
/*------------------------------------------------------------------------------
0x124 Memory Timing Parameters Registers 1
------------------------------------------------------------------------------*/
reg [3 : 0] csr_twtr;
reg [3 : 0] csr_trtp;
reg [5 : 0] csr_tfaw;
// assign value back to top
assign cfg_twtr = csr_twtr [TWTR_BUS_WIDTH - 1 : 0];
assign cfg_trtp = csr_trtp [TRTP_BUS_WIDTH - 1 : 0];
assign cfg_tfaw = csr_tfaw [TFAW_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_twtr <= CFG_TWTR;
csr_trtp <= CFG_TRTP;
csr_tfaw <= CFG_TFAW;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h24)
begin
if (int_be [0])
begin
csr_twtr <= int_wdata [3 : 0 ];
csr_trtp <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_tfaw <= int_wdata [13 : 8 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_124 = 0;
// then we set individual bits
read_csr_register_124 [3 : 0 ] = csr_twtr;
read_csr_register_124 [7 : 4 ] = csr_trtp;
read_csr_register_124 [15 : 8 ] = csr_tfaw;
end
/*------------------------------------------------------------------------------
0x125 Memory Timing Parameters Registers 2
------------------------------------------------------------------------------*/
reg [15 : 0] csr_trefi;
reg [7 : 0] csr_trfc;
// assign value back to top
assign cfg_trefi = csr_trefi [TREFI_BUS_WIDTH - 1 : 0];
assign cfg_trfc = csr_trfc [TRFC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trefi <= CFG_TREFI;
csr_trfc <= CFG_TRFC;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h25)
begin
if (int_be [0])
begin
csr_trefi [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_trefi [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_trfc <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_125 = 0;
// then we set individual bits
read_csr_register_125 [15 : 0 ] = csr_trefi;
read_csr_register_125 [23 : 16] = csr_trfc;
end
/*------------------------------------------------------------------------------
0x126 Memory Timing Parameters Registers 3
------------------------------------------------------------------------------*/
reg [3 : 0] csr_tcl;
reg [3 : 0] csr_al;
reg [3 : 0] csr_cwl;
reg [3 : 0] csr_twr;
reg [7 : 0] csr_bl;
// assign value back to top
assign cfg_tcl = csr_tcl [TCL_BUS_WIDTH - 1 : 0];
assign cfg_add_lat = csr_al [ADD_LAT_BUS_WIDTH - 1 : 0];
assign cfg_cas_wr_lat = csr_cwl [CAS_WR_LAT_BUS_WIDTH - 1 : 0];
assign cfg_twr = csr_twr [TWR_BUS_WIDTH - 1 : 0];
assign cfg_burst_length = csr_bl [BL_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_tcl <= CFG_TCL;
csr_al <= CFG_ADD_LAT;
csr_cwl <= CFG_CAS_WR_LAT;
csr_twr <= CFG_TWR;
csr_bl <= CFG_BURST_LENGTH;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h26)
begin
if (int_be [0])
begin
csr_tcl <= int_wdata [3 : 0 ];
csr_al <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_cwl <= int_wdata [11 : 8 ];
csr_twr <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_bl <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_126 = 0;
// then we set individual bits
read_csr_register_126 [3 : 0 ] = csr_tcl;
read_csr_register_126 [7 : 4 ] = csr_al;
read_csr_register_126 [11 : 8 ] = csr_cwl;
read_csr_register_126 [15 : 12] = csr_twr;
read_csr_register_126 [23 : 16] = csr_bl;
end
end
if (!CTL_ECC_CSR_ENABLED)
begin
assign cfg_enable_ecc = 1'b1; // default value
assign cfg_enable_auto_corr = 1'b1; // default value
assign cfg_gen_sbe = 0;
assign cfg_gen_dbe = 0;
assign cfg_enable_intr = 1'b1; // default value
assign cfg_mask_sbe_intr = 0;
assign cfg_mask_dbe_intr = 0;
assign cfg_clr_intr = 0;
assign cfg_mask_corr_dropped_intr=0;
end
else
begin
/*------------------------------------------------------------------------------
0x130 ECC Control Register
------------------------------------------------------------------------------*/
reg csr_enable_ecc;
reg csr_enable_auto_corr;
reg csr_gen_sbe;
reg csr_gen_dbe;
reg csr_enable_intr;
reg csr_mask_sbe_intr;
reg csr_mask_dbe_intr;
reg csr_ecc_clear;
reg csr_mask_corr_dropped_intr;
// assign value back to top
assign cfg_enable_ecc = csr_enable_ecc;
assign cfg_enable_auto_corr = csr_enable_auto_corr;
assign cfg_gen_sbe = csr_gen_sbe;
assign cfg_gen_dbe = csr_gen_dbe;
assign cfg_enable_intr = csr_enable_intr;
assign cfg_mask_sbe_intr = csr_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_mask_dbe_intr;
assign cfg_clr_intr = csr_ecc_clear;
assign cfg_mask_corr_dropped_intr = csr_mask_corr_dropped_intr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_enable_ecc <= CFG_ENABLE_ECC;
csr_enable_auto_corr <= CFG_ENABLE_AUTO_CORR;
csr_gen_sbe <= 0;
csr_gen_dbe <= 0;
csr_enable_intr <= 1'b1;
csr_mask_sbe_intr <= 0;
csr_mask_dbe_intr <= 0;
csr_ecc_clear <= 0;
csr_mask_corr_dropped_intr <= 0;
end
else
begin
// write request
if (!int_mask_ecc_avalon_mm_write && int_write_req && int_addr == 8'h30)
begin
if (int_be [0])
begin
csr_enable_ecc <= int_wdata [0];
csr_enable_auto_corr <= int_wdata [1];
csr_gen_sbe <= int_wdata [2];
csr_gen_dbe <= int_wdata [3];
csr_enable_intr <= int_wdata [4];
csr_mask_sbe_intr <= int_wdata [5];
csr_mask_dbe_intr <= int_wdata [6];
csr_ecc_clear <= int_wdata [7];
end
if (int_be [1])
begin
csr_mask_corr_dropped_intr <= int_wdata [8];
end
end
// set csr_clear to zero after one clock cycle
if (csr_ecc_clear)
csr_ecc_clear <= 1'b0;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_130 = 0;
// then we set individual bits
read_csr_register_130 [0] = csr_enable_ecc;
read_csr_register_130 [1] = csr_enable_auto_corr;
read_csr_register_130 [2] = csr_gen_sbe;
read_csr_register_130 [3] = csr_gen_dbe;
read_csr_register_130 [4] = csr_enable_intr;
read_csr_register_130 [5] = csr_mask_sbe_intr;
read_csr_register_130 [6] = csr_mask_dbe_intr;
read_csr_register_130 [7] = csr_ecc_clear;
read_csr_register_130 [8] = csr_mask_corr_dropped_intr;
end
/*------------------------------------------------------------------------------
0x131 ECC Status Register (Read Only)
------------------------------------------------------------------------------*/
reg csr_sbe_error;
reg csr_dbe_error;
reg csr_corr_dropped;
reg [7 : 0] csr_sbe_count;
reg [7 : 0] csr_dbe_count;
reg [7 : 0] csr_corr_dropped_count;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
csr_sbe_error <= sts_sbe_error;
csr_dbe_error <= sts_dbe_error;
csr_sbe_count <= sts_sbe_count;
csr_dbe_count <= sts_dbe_count;
csr_corr_dropped <= sts_corr_dropped;
csr_corr_dropped_count <= sts_corr_dropped_count;
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_131 = 0;
// then we set individual bits
read_csr_register_131 [0 ] = csr_sbe_error;
read_csr_register_131 [1 ] = csr_dbe_error;
read_csr_register_131 [2 ] = csr_corr_dropped;
read_csr_register_131 [15 : 8 ] = csr_sbe_count;
read_csr_register_131 [23 : 16] = csr_dbe_count;
read_csr_register_131 [31 : 24] = csr_corr_dropped_count;
end
/*------------------------------------------------------------------------------
0x132 ECC Error Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_error_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_error_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_error_addr <= 0;
else
csr_error_addr <= sts_err_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_132 = csr_error_addr;
end
/*------------------------------------------------------------------------------
0x133 ECC Correction Dropped Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_corr_dropped_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_corr_dropped_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_corr_dropped_addr <= 0;
else
csr_corr_dropped_addr <= sts_corr_dropped_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_133 = csr_corr_dropped_addr;
end
/*------------------------------------------------------------------------------
0x134 Controller Status and Control Register - Advanced Features
------------------------------------------------------------------------------*/
reg csr_reorder_data;
reg [7 : 0] csr_starve_limit;
// assign value back to top
assign cfg_reorder_data = csr_reorder_data;
assign cfg_starve_limit = csr_starve_limit;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_reorder_data <= CFG_REORDER_DATA;
csr_starve_limit <= CFG_STARVE_LIMIT; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h34)
begin
if (int_be [0])
begin
csr_reorder_data <= int_wdata [ 0];
end
if (int_be [2])
begin
csr_starve_limit <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_134 = 0;
// then we set individual bits
read_csr_register_134 [ 0 ] = csr_reorder_data;
read_csr_register_134 [ 23 : 16 ] = csr_starve_limit;
end
end
endgenerate
endmodule
|
// -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer with Packet FIFO
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_w_upsizer_pktfifo #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter C_CLK_CONV = 1'b0,
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1,
// Log2 of Up-Sizing ratio for data.
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Global Signals
input wire S_AXI_ACLK,
input wire M_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire M_AXI_ARESETN,
// Command Interface
input wire [C_AXI_ADDR_WIDTH-1:0] cmd_si_addr,
input wire [8-1:0] cmd_si_len,
input wire [3-1:0] cmd_si_size,
input wire [2-1:0] cmd_si_burst,
output wire cmd_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWREGION,
input wire [4-1:0] S_AXI_AWQOS,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [8-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWREGION,
output wire [4-1:0] M_AXI_AWQOS,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE
);
localparam integer P_SI_BYTES = C_S_AXI_DATA_WIDTH / 8;
localparam integer P_MI_BYTES = C_M_AXI_DATA_WIDTH / 8;
localparam integer P_MAX_BYTES = 1024 / 8;
localparam integer P_SI_SIZE = f_ceil_log2(P_SI_BYTES);
localparam integer P_MI_SIZE = f_ceil_log2(P_MI_BYTES);
localparam integer P_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer P_RATIO_LOG = f_ceil_log2(P_RATIO);
localparam integer P_NUM_BUF = (P_RATIO > 16) ? 32 : (P_RATIO * 2);
localparam integer P_NUM_BUF_LOG = f_ceil_log2(P_NUM_BUF);
localparam integer P_AWFIFO_TRESHOLD = P_NUM_BUF - 2;
localparam integer P_M_WBUFFER_WIDTH = P_MI_BYTES * 9;
localparam integer P_M_WBUFFER_DEPTH = 512;
localparam integer P_M_WBUFFER_DEPTH_LOG = 9;
localparam integer P_M_WBUFFER_WORDS = P_M_WBUFFER_DEPTH / P_NUM_BUF;
localparam integer P_M_WBUFFER_WORDS_LOG = f_ceil_log2(P_M_WBUFFER_WORDS);
localparam integer P_MAX_RBUFFER_BYTES_LOG = f_ceil_log2((P_M_WBUFFER_DEPTH / 4) * P_MAX_BYTES);
localparam [1:0] P_INCR = 2'b01, P_WRAP = 2'b10, P_FIXED = 2'b00;
localparam [1:0] S_IDLE = 2'b00, S_WRITING = 2'b01, S_AWFULL = 2'b11;
localparam [2:0] M_IDLE = 3'b000, M_ISSUE1 = 3'b001, M_WRITING1 = 3'b011, M_AW_STALL = 3'b010, M_AW_DONE1 = 3'b110, M_ISSUE2 = 3'b111, M_WRITING2 = 3'b101, M_AW_DONE2 = 3'b100;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_AWFIFO_WIDTH = 29 + C_AXI_ADDR_WIDTH + P_MI_SIZE;
localparam integer P_COMMON_CLOCK = (C_CLK_CONV & C_AXI_IS_ACLK_ASYNC) ? 0 : 1;
reg S_AXI_WREADY_i;
reg M_AXI_AWVALID_i;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR_i;
wire [7:0] M_AXI_AWLEN_i;
wire [2:0] M_AXI_AWSIZE_i;
wire [1:0] M_AXI_AWBURST_i;
wire M_AXI_AWLOCK_i;
reg M_AXI_WVALID_i;
reg M_AXI_WLAST_i;
wire S_AXI_AWLOCK_i;
reg aw_push;
wire push_ready;
wire aw_ready;
reg load_si_ptr;
reg [1:0] si_state;
reg [1:0] si_state_ns;
reg S_AXI_WREADY_ns;
reg aw_pop;
reg aw_pop_extend;
wire aw_pop_event;
wire aw_pop_resync;
reg cmd_ready_i;
wire si_buf_en;
reg [P_NUM_BUF_LOG-1:0] si_buf;
reg [P_NUM_BUF_LOG-1:0] buf_cnt;
reg [P_M_WBUFFER_WORDS_LOG-1:0] si_ptr;
reg [1:0] si_burst;
reg [2:0] si_size;
reg [P_SI_BYTES-1:0] si_be;
wire [P_MI_BYTES-1:0] si_we;
reg [P_SI_BYTES-1:0] si_wrap_be_next;
reg [P_MI_SIZE-P_SI_SIZE-1:0] si_word;
reg [P_MI_SIZE-P_SI_SIZE-1:0] si_wrap_word_next;
reg [3:0] si_wrap_cnt;
reg [2:0] mi_state;
reg [2:0] mi_state_ns;
reg M_AXI_AWVALID_ns;
reg M_AXI_WVALID_ns;
reg load_mi_ptr;
reg load_mi_next;
reg load_mi_d1;
reg load_mi_d2;
reg first_load_mi_d1;
wire mi_w_done;
reg mi_last;
reg mi_last_d1;
reg next_valid;
reg [P_NUM_BUF_LOG-1:0] mi_buf;
reg [P_M_WBUFFER_WORDS_LOG-1:0] mi_ptr;
reg [7:0] mi_wcnt;
wire mi_buf_en;
wire mi_awvalid;
reg [1:0] mi_burst;
reg [2:0] mi_size;
reg [P_MI_BYTES-1:0] mi_be;
reg [P_MI_BYTES-1:0] mi_be_d1;
reg [P_MI_BYTES-1:0] mi_wstrb_mask_d2;
reg [P_MI_BYTES-1:0] mi_wrap_be_next;
reg [P_MI_SIZE-1:0] mi_addr;
reg [P_MI_SIZE-1:0] mi_addr_d1;
wire [P_MI_SIZE-1:0] si_last_index;
wire [P_MI_SIZE-1:0] si_last_index_reg;
wire [P_MI_SIZE-1:0] mi_last_index_reg;
reg [P_MI_SIZE-1:0] mi_last_index_reg_d0;
reg [P_MI_SIZE-1:0] mi_last_index_reg_d1;
reg [P_MI_SIZE-1:0] next_mi_last_index_reg;
reg mi_first;
reg mi_first_d1;
reg [3:0] mi_wrap_cnt;
reg [7:0] next_mi_len;
reg [1:0] next_mi_burst;
reg [2:0] next_mi_size;
reg [P_MI_SIZE+4-1:0] next_mi_addr;
wire [P_M_WBUFFER_WIDTH-1:0] si_wpayload;
wire [P_M_WBUFFER_WIDTH-1:0] mi_wpayload;
wire [P_M_WBUFFER_DEPTH_LOG-1:0] si_buf_addr;
wire [P_M_WBUFFER_DEPTH_LOG-1:0] mi_buf_addr;
wire s_awvalid_reg;
wire s_awready_reg;
wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr_reg;
wire [7:0] s_awlen_reg;
wire [2:0] s_awsize_reg;
wire [1:0] s_awburst_reg;
wire s_awlock_reg;
wire [3:0] s_awcache_reg;
wire [2:0] s_awprot_reg;
wire [3:0] s_awqos_reg;
wire [3:0] s_awregion_reg;
wire m_aclk;
wire m_aresetn;
wire s_aresetn;
wire aw_fifo_s_aclk;
wire aw_fifo_m_aclk;
wire aw_fifo_aresetn;
wire awpop_reset;
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire fast_aclk;
reg fast_aresetn_r;
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Byte-enable pattern, for a full SI data-width transfer, at the given starting address.
function [P_SI_BYTES-1:0] f_si_be_init
(
input [P_SI_SIZE-1:0] addr,
input [2:0] size
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_SI_BYTES; i=i+1) begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_be_init[i] = addr_i[ 1 : 0] == i[ 1 : 0];
2'h1: f_si_be_init[i] = addr_i[ 1 : 1] == i[ 1 : 1];
default: f_si_be_init[i] = 1'b1;
endcase
3: case (size[1:0])
2'h0: f_si_be_init[i] = addr_i[ 2 : 0] == i[ 2 : 0];
2'h1: f_si_be_init[i] = addr_i[ 2 : 1] == i[ 2 : 1];
2'h2: f_si_be_init[i] = addr_i[ 2 : 2] == i[ 2 : 2];
default: f_si_be_init[i] = 1'b1;
endcase
4: case (size)
3'h0: f_si_be_init[i] = addr_i[ 3 : 0] == i[ 3 : 0];
3'h1: f_si_be_init[i] = addr_i[ 3 : 1] == i[ 3 : 1];
3'h2: f_si_be_init[i] = addr_i[ 3 : 2] == i[ 3 : 2];
3'h3: f_si_be_init[i] = addr_i[ 3 : 3] == i[ 3 : 3];
default: f_si_be_init[i] = 1'b1;
endcase
5: case (size)
3'h0: f_si_be_init[i] = addr_i[ 4 : 0] == i[ 4 : 0];
3'h1: f_si_be_init[i] = addr_i[ 4 : 1] == i[ 4 : 1];
3'h2: f_si_be_init[i] = addr_i[ 4 : 2] == i[ 4 : 2];
3'h3: f_si_be_init[i] = addr_i[ 4 : 3] == i[ 4 : 3];
3'h4: f_si_be_init[i] = addr_i[ 4 : 4] == i[ 4 : 4];
default: f_si_be_init[i] = 1'b1;
endcase
6: case (size)
3'h0: f_si_be_init[i] = addr_i[ 5 : 0] == i[ 5 : 0];
3'h1: f_si_be_init[i] = addr_i[ 5 : 1] == i[ 5 : 1];
3'h2: f_si_be_init[i] = addr_i[ 5 : 2] == i[ 5 : 2];
3'h3: f_si_be_init[i] = addr_i[ 5 : 3] == i[ 5 : 3];
3'h4: f_si_be_init[i] = addr_i[ 5 : 4] == i[ 5 : 4];
3'h5: f_si_be_init[i] = addr_i[ 5 : 5] == i[ 5 : 5];
default: f_si_be_init[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable pattern, for a full MI data-width transfer, at the given starting address.
function [P_MI_BYTES-1:0] f_mi_be_init
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_MI_BYTES; i=i+1) begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 2 : 0] == i[ 2 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 2 : 1] == i[ 2 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 2 : 2] == i[ 2 : 2];
default: f_mi_be_init[i] = 1'b1; // Fully-packed
endcase
4: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 3 : 0] == i[ 3 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 3 : 1] == i[ 3 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 3 : 2] == i[ 3 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 3 : 3] == i[ 3 : 3];
default: f_mi_be_init[i] = 1'b1;
endcase
5: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 4 : 0] == i[ 4 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 4 : 1] == i[ 4 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 4 : 2] == i[ 4 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 4 : 3] == i[ 4 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 4 : 4] == i[ 4 : 4];
default: f_mi_be_init[i] = 1'b1;
endcase
6: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 5 : 0] == i[ 5 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 5 : 1] == i[ 5 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 5 : 2] == i[ 5 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 5 : 3] == i[ 5 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 5 : 4] == i[ 5 : 4];
3'h5: f_mi_be_init[i] = addr_i[ 5 : 5] == i[ 5 : 5];
default: f_mi_be_init[i] = 1'b1;
endcase
7: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 6 : 0] == i[ 6 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 6 : 1] == i[ 6 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 6 : 2] == i[ 6 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 6 : 3] == i[ 6 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 6 : 4] == i[ 6 : 4];
3'h5: f_mi_be_init[i] = addr_i[ 6 : 5] == i[ 6 : 5];
3'h6: f_mi_be_init[i] = addr_i[ 6 : 6] == i[ 6 : 6];
default: f_mi_be_init[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable mask for the first fully-packed MI transfer (mask off ragged-head burst).
function [P_MI_BYTES-1:0] f_mi_be_first_mask
(
input [P_MI_SIZE-1:0] addr
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_mi_be_first_mask[i] = (i >= {1'b0, addr});
end
end
endfunction
// Index of last byte written in last MI transfer.
function [P_MI_SIZE-1:0] f_mi_be_last_index
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len,
input [1:0] burst
);
reg [P_MI_SIZE-1:0] bytes;
reg [P_MI_SIZE-1:0] mask;
begin
case (P_SI_SIZE)
2: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
endcase
3: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
endcase
4: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
endcase
5: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
3'h5: begin bytes = {len, 5'b0}; mask = {5{1'b1}}; end
endcase
6: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
3'h5: begin bytes = {len, 5'b0}; mask = {5{1'b1}}; end
3'h6: begin bytes = {len, 6'b0}; mask = {6{1'b1}}; end
endcase
endcase
case (burst)
P_INCR:
f_mi_be_last_index = (addr + bytes) | mask;
P_WRAP:
f_mi_be_last_index = addr | bytes | mask;
P_FIXED:
f_mi_be_last_index = {P_MI_SIZE{1'b1}};
endcase
end
endfunction
// Byte-enable mask for the last fully-packed MI transfer (mask off ragged-tail burst).
function [P_MI_BYTES-1:0] f_mi_be_last_mask
(
input [P_MI_SIZE-1:0] index
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_mi_be_last_mask[i] = (i <= {1'b0, index});
end
end
endfunction
// Byte-enable pattern, within the SI data-width, of the transfer at the wrap boundary.
function [P_SI_BYTES-1:0] f_si_wrap_be
(
input [P_SI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_SI_BYTES; i=i+1) begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[1:0]) : ({addr_i[1:1], 1'b0} == i[1:0]);
2'h1: f_si_wrap_be[i] = ( 1'b0 == i[1:1]);
default: f_si_wrap_be[i] = 1'b1;
endcase
3: case (size[1:0])
2'h0: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[2:0]) : len[1] ? ({addr_i[2:2], 2'b0} == i[2:0]) : ({addr_i[2:1], 1'b0} == i[2:0]);
2'h1: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[2:1]) : ({addr_i[2:2], 1'b0} == i[2:1]);
2'h2: f_si_wrap_be[i] = ( 1'b0 == i[2:2]);
default: f_si_wrap_be[i] = 1'b1;
endcase
4: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[3:0]) : len[2] ? ({addr_i[3:3], 3'b0} == i[3:0]) : len[1] ? ({addr_i[3:2], 2'b0} == i[3:0]) : ({addr_i[3:1], 1'b0} == i[3:0]);
3'h1: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[3:1]) : len[1] ? ({addr_i[3:3], 2'b0} == i[3:1]) : ({addr_i[3:2], 1'b0} == i[3:1]);
3'h2: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[3:2]) : ({addr_i[3:3], 1'b0} == i[3:2]);
3'h3: f_si_wrap_be[i] = ( 1'b0 == i[3:3]);
default: f_si_wrap_be[i] = 1'b1;
endcase
5: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ({addr_i[4:4], 4'b0} == i[4:0]) : len[2] ? ({addr_i[4:3], 3'b0} == i[4:0]) : len[1] ? ({addr_i[4:2], 2'b0} == i[4:0]) : ({addr_i[4:1], 1'b0} == i[4:0]);
3'h1: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[4:1]) : len[2] ? ({addr_i[4:4], 3'b0} == i[4:1]) : len[1] ? ({addr_i[4:3], 2'b0} == i[4:1]) : ({addr_i[4:2], 1'b0} == i[4:1]);
3'h2: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[4:2]) : len[1] ? ({addr_i[4:4], 2'b0} == i[4:2]) : ({addr_i[4:3], 1'b0} == i[4:2]);
3'h3: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[4:3]) : ({addr_i[4:4], 1'b0} == i[4:3]);
3'h4: f_si_wrap_be[i] = ( 1'b0 == i[4:4]);
default: f_si_wrap_be[i] = 1'b1;
endcase
6: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ({addr_i[5:4], 4'b0} == i[5:0]) : len[2] ? ({addr_i[5:3], 3'b0} == i[5:0]) : len[1] ? ({addr_i[5:2], 2'b0} == i[5:0]) : ({addr_i[5:1], 1'b0} == i[5:0]);
3'h1: f_si_wrap_be[i] = len[3] ? ({addr_i[5:5], 4'b0} == i[5:1]) : len[2] ? ({addr_i[5:4], 3'b0} == i[5:1]) : len[1] ? ({addr_i[5:3], 2'b0} == i[5:1]) : ({addr_i[5:2], 1'b0} == i[5:1]);
3'h2: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[5:2]) : len[2] ? ({addr_i[5:5], 3'b0} == i[5:2]) : len[1] ? ({addr_i[5:4], 2'b0} == i[5:2]) : ({addr_i[5:3], 1'b0} == i[5:2]);
3'h3: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[5:3]) : len[1] ? ({addr_i[5:5], 2'b0} == i[5:3]) : ({addr_i[5:4], 1'b0} == i[5:3]);
3'h4: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[5:4]) : ({addr_i[5:5], 1'b0} == i[5:4]);
3'h5: f_si_wrap_be[i] = ( 1'b0 == i[5:5]);
default: f_si_wrap_be[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable pattern, within the MI data-width, of the transfer at the wrap boundary.
function [P_MI_BYTES-1:0] f_mi_wrap_be
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_MI_BYTES; i=i+1) begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[2:0]) : len[1] ? ({addr_i[2:2], 2'b0} == i[2:0]) : ({addr_i[2:1], 1'b0} == i[2:0]);
3'h1: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[2:1]) : ({addr_i[2:2], 1'b0} == i[2:1]);
3'h2: f_mi_wrap_be[i] = ( 1'b0 == i[2:2]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
4: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[3:0]) : len[2] ? ({addr_i[3:3], 3'b0} == i[3:0]) : len[1] ? ({addr_i[3:2], 2'b0} == i[3:0]) : ({addr_i[3:1], 1'b0} == i[3:0]);
3'h1: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[3:1]) : len[1] ? ({addr_i[3:3], 2'b0} == i[3:1]) : ({addr_i[3:2], 1'b0} == i[3:1]);
3'h2: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[3:2]) : ({addr_i[3:3], 1'b0} == i[3:2]);
3'h3: f_mi_wrap_be[i] = ( 1'b0 == i[3:3]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
5: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[4:4], 4'b0} == i[4:0]) : len[2] ? ({addr_i[4:3], 3'b0} == i[4:0]) : len[1] ? ({addr_i[4:2], 2'b0} == i[4:0]) : ({addr_i[4:1], 1'b0} == i[4:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[4:1]) : len[2] ? ({addr_i[4:4], 3'b0} == i[4:1]) : len[1] ? ({addr_i[4:3], 2'b0} == i[4:1]) : ({addr_i[4:2], 1'b0} == i[4:1]);
3'h2: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[4:2]) : len[1] ? ({addr_i[4:4], 2'b0} == i[4:2]) : ({addr_i[4:3], 1'b0} == i[4:2]);
3'h3: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[4:3]) : ({addr_i[4:4], 1'b0} == i[4:3]);
3'h4: f_mi_wrap_be[i] = ( 1'b0 == i[4:4]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
6: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[5:4], 4'b0} == i[5:0]) : len[2] ? ({addr_i[5:3], 3'b0} == i[5:0]) : len[1] ? ({addr_i[5:2], 2'b0} == i[5:0]) : ({addr_i[5:1], 1'b0} == i[5:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ({addr_i[5:5], 4'b0} == i[5:1]) : len[2] ? ({addr_i[5:4], 3'b0} == i[5:1]) : len[1] ? ({addr_i[5:3], 2'b0} == i[5:1]) : ({addr_i[5:2], 1'b0} == i[5:1]);
3'h2: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[5:2]) : len[2] ? ({addr_i[5:5], 3'b0} == i[5:2]) : len[1] ? ({addr_i[5:4], 2'b0} == i[5:2]) : ({addr_i[5:3], 1'b0} == i[5:2]);
3'h3: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[5:3]) : len[1] ? ({addr_i[5:5], 2'b0} == i[5:3]) : ({addr_i[5:4], 1'b0} == i[5:3]);
3'h4: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[5:4]) : ({addr_i[5:5], 1'b0} == i[5:4]);
3'h5: f_mi_wrap_be[i] = ( 1'b0 == i[5:5]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
7: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:4], 4'b0} == i[6:0]) : len[2] ? ({addr_i[6:3], 3'b0} == i[6:0]) : len[1] ? ({addr_i[6:2], 2'b0} == i[6:0]) : ({addr_i[6:1], 1'b0} == i[6:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:5], 4'b0} == i[6:1]) : len[2] ? ({addr_i[6:4], 3'b0} == i[6:1]) : len[1] ? ({addr_i[6:3], 2'b0} == i[6:1]) : ({addr_i[6:2], 1'b0} == i[6:1]);
3'h2: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:6], 4'b0} == i[6:2]) : len[2] ? ({addr_i[6:5], 3'b0} == i[6:2]) : len[1] ? ({addr_i[6:4], 2'b0} == i[6:2]) : ({addr_i[6:3], 1'b0} == i[6:2]);
3'h3: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[6:3]) : len[2] ? ({addr_i[6:6], 3'b0} == i[6:3]) : len[1] ? ({addr_i[6:5], 2'b0} == i[6:3]) : ({addr_i[6:4], 1'b0} == i[6:3]);
3'h4: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[6:4]) : len[1] ? ({addr_i[6:6], 2'b0} == i[6:4]) : ({addr_i[6:5], 1'b0} == i[6:4]);
3'h5: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[6:5]) : ({addr_i[6:6], 1'b0} == i[6:5]);
3'h6: f_mi_wrap_be[i] = ( 1'b0 == i[6:6]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Number of SI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_si_wrap_cnt
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
default: start = addr_i[ 2 +: 4];
endcase
3: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
2'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
endcase
f_si_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Number of MI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_mi_wrap_cnt
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
7: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
3'h6: start = addr_i[ 6 +: 4];
default: start = addr_i[ 7 +: 4];
endcase
endcase
f_mi_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Mask of address bits used to point to buffer line (MI data-width) of first SI wrap transfer.
function [2:0] f_si_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_RATIO_LOG)
1: case (P_SI_SIZE)
6: case (size)
3'h6: f_si_wrap_mask = len[3:1];
3'h5: f_si_wrap_mask = len[3:2];
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_si_wrap_mask = len[3:1];
3'h4: f_si_wrap_mask = len[3:2];
3'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_si_wrap_mask = len[3:1];
3'h3: f_si_wrap_mask = len[3:2];
3'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:1];
2'h2: f_si_wrap_mask = len[3:2];
2'h1: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:1];
2'h1: f_si_wrap_mask = len[3:2];
default: f_si_wrap_mask = len[3:3];
endcase
endcase
2: case (P_SI_SIZE)
5: case (size)
3'h5: f_si_wrap_mask = len[3:2];
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_si_wrap_mask = len[3:2];
3'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:2];
2'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:2];
2'h1: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
endcase
3: case (P_SI_SIZE)
4: case (size)
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
endcase
default: f_si_wrap_mask = 0 ;
endcase
end
endfunction
// Mask of address bits used to point to buffer line of first MI wrap transfer.
function [2:0] f_mi_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_RATIO_LOG)
1: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h6: f_mi_wrap_mask = len[3:1];
3'h5: f_mi_wrap_mask = len[3:2];
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h5: f_mi_wrap_mask = len[3:1];
3'h4: f_mi_wrap_mask = len[3:2];
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h4: f_mi_wrap_mask = len[3:1];
3'h3: f_mi_wrap_mask = len[3:2];
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h3: f_mi_wrap_mask = len[3:1];
3'h2: f_mi_wrap_mask = len[3:2];
3'h1: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_mi_wrap_mask = {len[2:1], 1'b1};
2'h2: f_mi_wrap_mask = len[3:1];
2'h1: f_mi_wrap_mask = len[3:2];
default: f_mi_wrap_mask = len[3:3];
endcase
endcase
2: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h5: f_mi_wrap_mask = len[3:2];
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h4: f_mi_wrap_mask = len[3:2];
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h3: f_mi_wrap_mask = len[3:2];
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h2: f_mi_wrap_mask = len[3:2];
3'h1: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
endcase
3: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = 1'b1;
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = 1'b1;
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = 1'b1;
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
endcase
default: f_mi_wrap_mask = 0 ;
endcase
end
endfunction
// Index of SI transfer within buffer line following wrap
function [P_MI_SIZE-P_SI_SIZE-1:0] f_si_wrap_word
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_MI_SIZE-P_SI_SIZE-1:0] mask;
begin
case (P_SI_SIZE)
2: case (size[1:0])
3'h2: mask = {len[3:1], {1{1'b1}}};
3'h1: mask = len[3:1];
default: mask = len[3:2];
endcase
3: case (size)
3'h3: mask = {len[3:1], {1{1'b1}}};
3'h2: mask = len[3:1];
3'h1: mask = len[3:2];
default: mask = len[3:3];
endcase
4: case (size)
3'h4: mask = {len[3:1], {1{1'b1}}};
3'h3: mask = len[3:1];
3'h2: mask = len[3:2];
3'h1: mask = len[3:3];
default: mask = 0;
endcase
5: case (size)
3'h5: mask = {len[3:1], {1{1'b1}}};
3'h4: mask = len[3:1];
3'h3: mask = len[3:2];
3'h2: mask = len[3:3];
default: mask = 0;
endcase
6: case (size)
3'h6: mask = {len[3:1], {1{1'b1}}};
3'h5: mask = len[3:1];
3'h4: mask = len[3:2];
3'h3: mask = len[3:3];
default: mask = 0;
endcase
endcase
f_si_wrap_word = addr[P_MI_SIZE-1 : P_SI_SIZE] & ~mask;
end
endfunction
// Complete byte-enable pattern for writing SI data word to buffer (MI data-width).
function [P_MI_BYTES-1:0] f_si_we
(
input [P_RATIO_LOG-1:0] word, // Index of SI transfer within buffer line
input [P_SI_BYTES-1:0] be // Byte-enable pattern within SI transfer (SI data-width)
);
integer i;
begin
for (i=0; i<P_RATIO; i=i+1) begin
f_si_we[i*P_SI_BYTES +: P_SI_BYTES] = (i == word) ? be : 0;
end
end
endfunction
// Rotate byte-enable mask around SI-width boundary.
function [P_SI_BYTES-1:0] f_si_be_rot
(
input [P_SI_BYTES-1:0] be, // Byte-enable pattern within SI transfer (SI data-width)
input [2:0] size
);
reg [63:0] be_i;
begin
be_i = be;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_be_rot = {be_i[0 +: ( 4 - 1)], be_i[ 3 -: 1]};
2'h1: f_si_be_rot = {be_i[0 +: ( 4 - 2)], be_i[ 3 -: 2]};
default: f_si_be_rot = {4{1'b1}};
endcase
3: case (size[1:0])
2'h0: f_si_be_rot = {be_i[0 +: ( 8 - 1)], be_i[ 7 -: 1]};
2'h1: f_si_be_rot = {be_i[0 +: ( 8 - 2)], be_i[ 7 -: 2]};
2'h2: f_si_be_rot = {be_i[0 +: ( 8 - 4)], be_i[ 7 -: 4]};
default: f_si_be_rot = {8{1'b1}};
endcase
4: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (16 - 1)], be_i[15 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (16 - 2)], be_i[15 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (16 - 4)], be_i[15 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (16 - 8)], be_i[15 -: 8]};
default: f_si_be_rot = {16{1'b1}};
endcase
5: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (32 - 1)], be_i[31 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (32 - 2)], be_i[31 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (32 - 4)], be_i[31 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (32 - 8)], be_i[31 -: 8]};
3'h4: f_si_be_rot = {be_i[0 +: (32 - 16)], be_i[31 -: 16]};
default: f_si_be_rot = {32{1'b1}};
endcase
6: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (64 - 1)], be_i[63 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (64 - 2)], be_i[63 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (64 - 4)], be_i[63 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (64 - 8)], be_i[63 -: 8]};
3'h4: f_si_be_rot = {be_i[0 +: (64 - 16)], be_i[63 -: 16]};
3'h5: f_si_be_rot = {be_i[0 +: (64 - 32)], be_i[63 -: 32]};
default: f_si_be_rot = {64{1'b1}};
endcase
endcase
end
endfunction
// Rotate byte-enable mask around MI-width boundary.
function [P_MI_BYTES-1:0] f_mi_be_rot
(
input [P_MI_BYTES-1:0] be, // Byte-enable pattern within MI transfer
input [2:0] size
);
reg [127:0] be_i;
begin
be_i = be;
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 8 - 1)], be_i[ 7 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 8 - 2)], be_i[ 7 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 8 - 4)], be_i[ 7 -: 4]};
default: f_mi_be_rot = {8{1'b1}};
endcase
4: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 16 - 1)], be_i[ 15 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 16 - 2)], be_i[ 15 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 16 - 4)], be_i[ 15 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 16 - 8)], be_i[ 15 -: 8]};
default: f_mi_be_rot = {16{1'b1}};
endcase
5: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 32 - 1)], be_i[ 31 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 32 - 2)], be_i[ 31 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 32 - 4)], be_i[ 31 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 32 - 8)], be_i[ 31 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: ( 32 - 16)], be_i[ 31 -: 16]};
default: f_mi_be_rot = {32{1'b1}};
endcase
6: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 64 - 1)], be_i[ 63 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 64 - 2)], be_i[ 63 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 64 - 4)], be_i[ 63 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 64 - 8)], be_i[ 63 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: ( 64 - 16)], be_i[ 63 -: 16]};
3'h5: f_mi_be_rot = {be_i[0 +: ( 64 - 32)], be_i[ 63 -: 32]};
default: f_mi_be_rot = {64{1'b1}};
endcase
7: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: (128 - 1)], be_i[127 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: (128 - 2)], be_i[127 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: (128 - 4)], be_i[127 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: (128 - 8)], be_i[127 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: (128 - 16)], be_i[127 -: 16]};
3'h5: f_mi_be_rot = {be_i[0 +: (128 - 32)], be_i[127 -: 32]};
3'h6: f_mi_be_rot = {be_i[0 +: (128 - 64)], be_i[127 -: 64]};
default: f_mi_be_rot = {128{1'b1}};
endcase
endcase
end
endfunction
function [P_SI_BYTES*9-1:0] f_wpayload
(
input [C_S_AXI_DATA_WIDTH-1:0] wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb
);
integer i;
begin
for (i=0; i<P_SI_BYTES; i=i+1) begin
f_wpayload[i*9 +: 9] = {wstrb[i], wdata[i*8 +: 8]};
end
end
endfunction
function [C_M_AXI_DATA_WIDTH-1:0] f_wdata
(
input [P_MI_BYTES*9-1:0] wpayload
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_wdata[i*8 +: 8] = wpayload[i*9 +: 8];
end
end
endfunction
function [C_M_AXI_DATA_WIDTH/8-1:0] f_wstrb
(
input [P_MI_BYTES*9-1:0] wpayload
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_wstrb[i] = wpayload[i*9+8];
end
end
endfunction
generate
if (C_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = M_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign aw_fifo_s_aclk = S_AXI_ACLK;
assign aw_fifo_m_aclk = M_AXI_ACLK;
assign aw_fifo_aresetn = S_AXI_ARESETN & M_AXI_ARESETN;
assign awpop_reset = ~S_AXI_ARESETN | ~M_AXI_ARESETN;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end else begin : gen_sync_conv
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = M_AXI_ACLK;
end else begin : gen_fastclk_si
assign fast_aclk = S_AXI_ACLK;
end
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = fast_aresetn_r;
assign s_aresetn = fast_aresetn_r;
assign aw_fifo_s_aclk = fast_aclk;
assign aw_fifo_m_aclk = 1'b0;
assign aw_fifo_aresetn = fast_aresetn_r;
assign s_sample_cycle_early = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign s_sample_cycle = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE;
assign m_sample_cycle_early = P_SI_LT_MI ? SAMPLE_CYCLE_EARLY : 1'b1;
assign m_sample_cycle = P_SI_LT_MI ? SAMPLE_CYCLE : 1'b1;
always @(posedge fast_aclk) begin
if (~S_AXI_ARESETN | ~M_AXI_ARESETN) begin
fast_aresetn_r <= 1'b0;
end else if (S_AXI_ARESETN & M_AXI_ARESETN & SAMPLE_CYCLE_EARLY) begin
fast_aresetn_r <= 1'b1;
end
end
end
end else begin : gen_no_clk_conv
assign m_aclk = S_AXI_ACLK;
assign m_aresetn = S_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign aw_fifo_s_aclk = S_AXI_ACLK;
assign aw_fifo_m_aclk = 1'b0;
assign aw_fifo_aresetn = S_AXI_ARESETN;
assign fast_aclk = S_AXI_ACLK;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end
assign S_AXI_WREADY = S_AXI_WREADY_i;
assign S_AXI_AWLOCK_i = S_AXI_AWLOCK[0];
assign si_buf_en = S_AXI_WVALID & S_AXI_WREADY_i;
assign cmd_ready = cmd_ready_i;
assign s_awready_reg = aw_push;
assign si_last_index = f_mi_be_last_index(cmd_si_addr[0 +: P_MI_SIZE], cmd_si_size, cmd_si_len, cmd_si_burst);
assign push_ready = s_awvalid_reg & aw_ready & (buf_cnt != P_AWFIFO_TRESHOLD);
always @ * begin
aw_push = 1'b0;
load_si_ptr = 1'b0;
si_state_ns = si_state;
S_AXI_WREADY_ns = S_AXI_WREADY_i;
case (si_state)
S_IDLE: begin
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
S_AXI_WREADY_ns = 1'b1;
si_state_ns = S_WRITING;
end
end
S_WRITING: begin
if (S_AXI_WVALID & S_AXI_WREADY_i & S_AXI_WLAST) begin
if (push_ready) begin
aw_push = m_sample_cycle; // Sample strobe when AW FIFO is on faster M_AXI_ACLK.
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for new AW command
si_state_ns = S_IDLE;
end
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for AW FIFO push
si_state_ns = S_AWFULL;
end
end
end
S_AWFULL: begin
if (push_ready) begin
aw_push = m_sample_cycle; // Sample strobe when AW FIFO is on faster M_AXI_ACLK.
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
S_AXI_WREADY_ns = 1'b1;
si_state_ns = S_WRITING;
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for new AW command
si_state_ns = S_IDLE;
end
end
end
default: si_state_ns = S_IDLE;
endcase
end
always @ (posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
si_state <= S_IDLE;
S_AXI_WREADY_i <= 1'b0;
si_buf <= 0;
buf_cnt <= 0;
cmd_ready_i <= 1'b0;
end else begin
si_state <= si_state_ns;
S_AXI_WREADY_i <= S_AXI_WREADY_ns;
cmd_ready_i <= aw_pop_resync;
if (aw_push) begin
si_buf <= si_buf + 1;
end
if (aw_push & ~aw_pop_resync) begin
buf_cnt <= buf_cnt + 1;
end else if (~aw_push & aw_pop_resync & |buf_cnt) begin
buf_cnt <= buf_cnt - 1;
end
end
end
always @ (posedge S_AXI_ACLK) begin
if (load_si_ptr) begin
if (cmd_si_burst == P_WRAP) begin
si_ptr <= cmd_si_addr[P_MI_SIZE +: 3] & f_si_wrap_mask(cmd_si_size, cmd_si_len);
end else begin
si_ptr <= 0;
end
si_burst <= cmd_si_burst;
si_size <= cmd_si_size;
si_be <= f_si_be_init(cmd_si_addr[0 +: P_SI_SIZE], cmd_si_size);
si_word <= cmd_si_addr[P_MI_SIZE-1 : P_SI_SIZE];
si_wrap_cnt <= f_si_wrap_cnt(cmd_si_addr[0 +: (P_MI_SIZE + 4)], cmd_si_size, cmd_si_len);
si_wrap_be_next <= f_si_wrap_be(cmd_si_addr[0 +: P_SI_SIZE], cmd_si_size, cmd_si_len);
si_wrap_word_next <= f_si_wrap_word(cmd_si_addr[0 +: (P_MI_SIZE + 4)], cmd_si_size, cmd_si_len);
end else if (si_buf_en) begin
if (si_burst == P_FIXED) begin
si_ptr <= si_ptr + 1;
end else if ((si_burst == P_WRAP) && (si_wrap_cnt == 0)) begin
si_ptr <= 0;
si_be <= si_wrap_be_next;
si_word <= si_wrap_word_next;
end else begin
if (si_be[P_SI_BYTES-1]) begin
if (&si_word) begin
si_ptr <= si_ptr + 1; // Wrap long INCR bursts around end of buffer
end
si_word <= si_word + 1;
end
si_be <= f_si_be_rot(si_be, si_size);
end
si_wrap_cnt <= si_wrap_cnt - 1;
end
end
always @ * begin
mi_state_ns = mi_state;
M_AXI_AWVALID_ns = M_AXI_AWVALID_i;
M_AXI_WVALID_ns = M_AXI_WVALID_i;
aw_pop = 1'b0;
load_mi_ptr = 1'b0;
load_mi_next = 1'b0;
case (mi_state)
M_IDLE: begin // mi_state = 0
M_AXI_AWVALID_ns = 1'b0;
M_AXI_WVALID_ns = 1'b0;
if (mi_awvalid) begin
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end
end
M_ISSUE1: begin // mi_state = 1
M_AXI_AWVALID_ns = 1'b1;
mi_state_ns = M_WRITING1;
end
M_WRITING1: begin // mi_state = 3
M_AXI_WVALID_ns = 1'b1;
if (M_AXI_AWREADY) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
M_AXI_AWVALID_ns = 1'b0;
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end else begin
mi_state_ns = M_AW_DONE1;
end
end else if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_AW_STALL;
end
end
M_AW_STALL: begin // mi_state = 2
if (M_AXI_AWREADY) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
M_AXI_AWVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end
end
M_AW_DONE1: begin // mi_state = 6
if (mi_awvalid) begin
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end else if (~mi_last & ~mi_last_d1 & ~M_AXI_WLAST_i) begin
load_mi_next = 1'b1;
mi_state_ns = M_ISSUE2;
end
end else if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end
end
M_ISSUE2: begin // mi_state = 7
M_AXI_AWVALID_ns = 1'b1;
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end else begin
mi_state_ns = M_WRITING2;
end
end
M_WRITING2: begin // mi_state = 5
if (M_AXI_AWREADY) begin
M_AXI_AWVALID_ns = 1'b0;
if (mi_w_done) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
mi_state_ns = M_AW_DONE1;
end else begin
mi_state_ns = M_AW_DONE2;
end
end else if (mi_w_done) begin
mi_state_ns = M_WRITING1;
end
end
M_AW_DONE2: begin // mi_state = 4
if (mi_w_done) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
mi_state_ns = M_AW_DONE1;
end
end
default: mi_state_ns = M_IDLE;
endcase
end
always @ (posedge m_aclk) begin
if (~m_aresetn) begin
mi_state <= M_IDLE;
mi_buf <= 0;
M_AXI_AWVALID_i <= 1'b0;
M_AXI_WVALID_i <= 1'b0;
mi_last <= 1'b0;
mi_last_d1 <= 1'b0;
M_AXI_WLAST_i <= 1'b0;
mi_wstrb_mask_d2 <= {P_MI_BYTES{1'b1}};
first_load_mi_d1 <= 1'b0;
next_valid <= 1'b0;
end else begin
mi_state <= mi_state_ns;
M_AXI_AWVALID_i <= M_AXI_AWVALID_ns;
M_AXI_WVALID_i <= M_AXI_WVALID_ns;
if (mi_buf_en & mi_last) begin
mi_buf <= mi_buf + 1;
end
if (load_mi_ptr) begin
mi_last <= (M_AXI_AWLEN_i == 0);
M_AXI_WLAST_i <= 1'b0;
end else if (mi_buf_en) begin
M_AXI_WLAST_i <= mi_last_d1;
mi_last_d1 <= mi_last;
if (first_load_mi_d1) begin
mi_wstrb_mask_d2 <= mi_be_d1 &
(mi_first_d1 ? f_mi_be_first_mask(mi_addr_d1) : {P_MI_BYTES{1'b1}}) &
(mi_last_d1 ? f_mi_be_last_mask(mi_last_index_reg_d1) : {P_MI_BYTES{1'b1}});
end
if (mi_last) begin
mi_last <= next_valid & (next_mi_len == 0);
end else begin
mi_last <= (mi_wcnt == 1);
end
end
if (load_mi_d1) begin
first_load_mi_d1 <= 1'b1; // forever
end
if (mi_last & mi_buf_en) begin
next_valid <= 1'b0;
end else if (load_mi_next) begin
next_valid <= 1'b1;
end
if (m_sample_cycle) begin
aw_pop_extend <= 1'b0;
end else if (aw_pop) begin
aw_pop_extend <= 1'b1;
end
end
end
assign mi_buf_en = (M_AXI_WVALID_i & M_AXI_WREADY) | load_mi_d1 | load_mi_d2;
assign mi_w_done = M_AXI_WVALID_i & M_AXI_WREADY & M_AXI_WLAST_i;
always @ (posedge m_aclk) begin
load_mi_d2 <= load_mi_d1;
load_mi_d1 <= load_mi_ptr;
if (load_mi_ptr) begin
if (M_AXI_AWBURST_i == P_WRAP) begin
mi_ptr <= M_AXI_AWADDR_i[P_MI_SIZE +: 3] & f_mi_wrap_mask(M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
end else begin
mi_ptr <= 0;
end
mi_wcnt <= M_AXI_AWLEN_i;
mi_burst <= M_AXI_AWBURST_i;
mi_size <= M_AXI_AWSIZE_i;
mi_be <= f_mi_be_init(M_AXI_AWADDR_i[0 +: P_MI_SIZE], M_AXI_AWSIZE_i);
mi_wrap_cnt <= f_mi_wrap_cnt(M_AXI_AWADDR_i[0 +: (P_MI_SIZE + 4)], M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
mi_wrap_be_next <= f_mi_wrap_be(M_AXI_AWADDR_i[0 +: P_MI_SIZE], M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
mi_first <= 1'b1;
mi_addr <= M_AXI_AWADDR_i[0 +: P_MI_SIZE];
mi_last_index_reg_d0 <= mi_last_index_reg;
end else if (mi_buf_en) begin
mi_be_d1 <= mi_be;
mi_first_d1 <= mi_first;
mi_last_index_reg_d1 <= mi_last_index_reg_d0;
mi_addr_d1 <= mi_addr;
if (mi_last) begin
if (next_mi_burst == P_WRAP) begin
mi_ptr <= next_mi_addr[P_MI_SIZE +: 3] & f_mi_wrap_mask(next_mi_size, next_mi_len);
end else begin
mi_ptr <= 0;
end
if (next_valid) begin
mi_wcnt <= next_mi_len;
mi_addr <= next_mi_addr[0 +: P_MI_SIZE];
mi_last_index_reg_d0 <= next_mi_last_index_reg;
end
mi_burst <= next_mi_burst;
mi_size <= next_mi_size;
mi_be <= f_mi_be_init(next_mi_addr[0 +: P_MI_SIZE], next_mi_size);
mi_wrap_cnt <= f_mi_wrap_cnt(next_mi_addr, next_mi_size, next_mi_len);
mi_wrap_be_next <= f_mi_wrap_be(next_mi_addr[0 +: P_MI_SIZE], next_mi_size, next_mi_len);
mi_first <= 1'b1;
end else begin
mi_first <= 1'b0;
if (mi_burst == P_FIXED) begin
mi_ptr <= mi_ptr + 1;
end else if ((mi_burst == P_WRAP) && (mi_wrap_cnt == 0)) begin
mi_ptr <= 0;
mi_be <= mi_wrap_be_next;
end else begin
if (mi_be[P_MI_BYTES-1]) begin
mi_ptr <= (mi_ptr + 1); // Wrap long INCR bursts around end of buffer
end
mi_be <= f_mi_be_rot(mi_be, mi_size);
end
mi_wcnt <= mi_wcnt - 1;
mi_wrap_cnt <= mi_wrap_cnt - 1;
end
end
if (load_mi_next) begin
next_mi_len <= M_AXI_AWLEN_i;
next_mi_burst <= M_AXI_AWBURST_i;
next_mi_size <= M_AXI_AWSIZE_i;
next_mi_addr <= M_AXI_AWADDR_i[0 +: (P_MI_SIZE + 4)];
next_mi_last_index_reg <= mi_last_index_reg;
end
end
assign si_wpayload = {P_RATIO{f_wpayload(S_AXI_WDATA,S_AXI_WSTRB)}};
assign M_AXI_WDATA = f_wdata(mi_wpayload);
assign M_AXI_WSTRB = f_wstrb(mi_wpayload) & mi_wstrb_mask_d2 & {P_MI_BYTES{M_AXI_WVALID_i}};
assign M_AXI_WVALID = M_AXI_WVALID_i;
assign M_AXI_WLAST = M_AXI_WLAST_i;
assign M_AXI_AWVALID = M_AXI_AWVALID_i;
assign M_AXI_AWADDR = M_AXI_AWADDR_i;
assign M_AXI_AWLEN = M_AXI_AWLEN_i;
assign M_AXI_AWSIZE = M_AXI_AWSIZE_i;
assign M_AXI_AWBURST = M_AXI_AWBURST_i;
assign M_AXI_AWLOCK = {1'b0,M_AXI_AWLOCK_i};
assign si_buf_addr = {si_buf, si_ptr};
assign mi_buf_addr = {mi_buf, mi_ptr};
assign si_we = f_si_we(si_word, si_be);
blk_mem_gen_v8_2 #(
.C_FAMILY(C_FAMILY),
.C_XDEVICEFAMILY(C_FAMILY),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("BlankString"),
.C_INIT_FILE("BlankString"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(P_MI_BYTES),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(P_M_WBUFFER_WIDTH),
.C_READ_WIDTH_A(P_M_WBUFFER_WIDTH),
.C_WRITE_DEPTH_A(P_M_WBUFFER_DEPTH),
.C_READ_DEPTH_A(P_M_WBUFFER_DEPTH),
.C_ADDRA_WIDTH(P_M_WBUFFER_DEPTH_LOG),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(P_MI_BYTES),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(P_M_WBUFFER_WIDTH),
.C_READ_WIDTH_B(P_M_WBUFFER_WIDTH),
.C_WRITE_DEPTH_B(P_M_WBUFFER_DEPTH),
.C_READ_DEPTH_B(P_M_WBUFFER_DEPTH),
.C_ADDRB_WIDTH(P_M_WBUFFER_DEPTH_LOG),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("GENERATE_X_ONLY"),
.C_COMMON_CLK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_USE_BRAM_BLOCK(0)
) w_buffer (
.clka(S_AXI_ACLK),
.rsta(1'b0),
.ena(si_buf_en),
.regcea(1'b1),
.wea(si_we),
.addra(si_buf_addr),
.dina(si_wpayload),
.douta(),
.clkb(m_aclk),
.rstb(1'b0),
.enb(mi_buf_en),
.regceb(1'b1),
.web({P_MI_BYTES{1'b0}}),
.addrb(mi_buf_addr),
.dinb({P_M_WBUFFER_WIDTH{1'b0}}),
.doutb(mi_wpayload),
.injectsbiterr(1'b0),
.injectdbiterr(1'b0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wdata({P_M_WBUFFER_WIDTH{1'b0}}),
.s_axi_wstrb({P_MI_BYTES{1'b0}}),
.s_axi_wlast(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_injectdbiterr(1'b0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc(),
.sleep(1'b0),
.eccpipece(1'b0)
);
fifo_generator_v12_0 #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_MEMORY_TYPE(1),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_AXIS_TYPE(0),
.C_HAS_AXI_ID(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_DIN_WIDTH_WACH(P_AWFIFO_WIDTH),
.C_DIN_WIDTH_WDCH(37),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(P_AWFIFO_WIDTH),
.C_DIN_WIDTH_RDCH(35),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(P_MI_SIZE),
.C_AXI_AWUSER_WIDTH(P_MI_SIZE),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(2),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_WDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_WRCH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_APPLICATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0)
) dw_fifogen_aw (
.s_aclk(aw_fifo_s_aclk),
.m_aclk(aw_fifo_m_aclk),
.s_aresetn(aw_fifo_aresetn),
.s_axi_awid (1'b0),
.s_axi_awaddr (s_awaddr_reg),
.s_axi_awlen (s_awlen_reg),
.s_axi_awsize (s_awsize_reg),
.s_axi_awburst (s_awburst_reg),
.s_axi_awlock (s_awlock_reg),
.s_axi_awcache (s_awcache_reg),
.s_axi_awprot (s_awprot_reg),
.s_axi_awqos (s_awqos_reg),
.s_axi_awregion (s_awregion_reg),
.s_axi_awuser (si_last_index_reg),
.s_axi_awvalid (aw_push),
.s_axi_awready (aw_ready),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr (M_AXI_AWADDR_i),
.m_axi_awlen (M_AXI_AWLEN_i),
.m_axi_awsize (M_AXI_AWSIZE_i),
.m_axi_awburst (M_AXI_AWBURST_i),
.m_axi_awlock (M_AXI_AWLOCK_i),
.m_axi_awcache (M_AXI_AWCACHE),
.m_axi_awprot (M_AXI_AWPROT),
.m_axi_awqos (M_AXI_AWQOS),
.m_axi_awregion (M_AXI_AWREGION),
.m_axi_awuser (mi_last_index_reg),
.m_axi_awvalid (mi_awvalid),
.m_axi_awready (aw_pop),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(1'b0),
.s_axi_araddr({C_AXI_ADDR_WIDTH{1'b0}}),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser({P_MI_SIZE{1'b0}}),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY(C_FAMILY),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(1),
.C_AXI_AWUSER_WIDTH(P_MI_SIZE),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(0),
.C_REG_CONFIG_B(0),
.C_REG_CONFIG_AR(0),
.C_REG_CONFIG_R(0)
) s_aw_reg (
.aclk(S_AXI_ACLK),
.aresetn(s_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr (S_AXI_AWADDR),
.s_axi_awlen (S_AXI_AWLEN),
.s_axi_awsize (S_AXI_AWSIZE),
.s_axi_awburst (S_AXI_AWBURST),
.s_axi_awlock (S_AXI_AWLOCK_i),
.s_axi_awcache (S_AXI_AWCACHE),
.s_axi_awprot (S_AXI_AWPROT),
.s_axi_awregion(S_AXI_AWREGION),
.s_axi_awqos (S_AXI_AWQOS),
.s_axi_awuser (si_last_index),
.s_axi_awvalid (S_AXI_AWVALID),
.s_axi_awready (S_AXI_AWREADY),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b00),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_buser(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.s_axi_arid(1'b0),
.s_axi_araddr({C_AXI_ADDR_WIDTH{1'B0}}),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arregion(4'b0),
.s_axi_arqos(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_ruser(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_awid(),
.m_axi_awaddr (s_awaddr_reg),
.m_axi_awlen (s_awlen_reg),
.m_axi_awsize (s_awsize_reg),
.m_axi_awburst (s_awburst_reg),
.m_axi_awlock (s_awlock_reg),
.m_axi_awcache (s_awcache_reg),
.m_axi_awprot (s_awprot_reg),
.m_axi_awregion(s_awregion_reg),
.m_axi_awqos (s_awqos_reg),
.m_axi_awuser (si_last_index_reg),
.m_axi_awvalid (s_awvalid_reg),
.m_axi_awready (s_awready_reg),
.m_axi_wid(),
.m_axi_wuser(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.m_axi_arid(),
.m_axi_aruser(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready()
);
if (C_CLK_CONV && C_AXI_IS_ACLK_ASYNC) begin : gen_awpop_fifo
fifo_generator_v12_0 #(
.C_DIN_WIDTH(1),
.C_DOUT_WIDTH(1),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) dw_fifogen_awpop (
.clk(1'b0),
.wr_clk(M_AXI_ACLK),
.rd_clk(S_AXI_ACLK),
.rst(awpop_reset),
.wr_rst(1'b0),
.rd_rst(1'b0),
.srst(1'b0),
.din(1'b0),
.dout(),
.full(),
.empty(aw_pop_event),
.wr_en(aw_pop),
.rd_en(aw_pop_resync),
.backup(1'b0),
.backup_marker(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
assign aw_pop_resync = ~aw_pop_event;
end else begin : gen_no_awpop_fifo
assign aw_pop_resync = aw_pop | aw_pop_extend;
end
endgenerate
endmodule
|
module ExampMain
#(parameter P)
(input i, output o, inout io);
endmodule
module ExampStub (/*AUTOARG*/
// Outputs
o,
// Inouts
io,
// Inputs
i
);
/*AUTOINOUTPARAM("ExampMain")*/
// Beginning of automatic parameters (from specific module)
parameter P;
// End of automatics
/*AUTOINOUTMODULE("ExampMain")*/
// Beginning of automatic in/out/inouts (from specific module)
output o;
inout io;
input i;
// End of automatics
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o = 1'h0;
// End of automatics
// verilator lint_off UNUSED
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
// Beginning of automatic unused inputs
i,
io,
// End of automatics
1'b0};
// verilator lint_on UNUSED
endmodule
// Local Variables:
// indent-tabs-mode: nil
// End:
|
//////////////////////////////////////////////////////////////////////////////
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//////////////////////////////////////////////////////////////////////////////
// Filename: ps2_reg.v
//
// Description: PS/2 memory mapped registers
//////////////////////////////////////////////////////////////////////////////
// Structure:
//
//////////////////////////////////////////////////////////////////////////////
//
// History:
// wph 10/10/01
//
//////////////////////////////////////////////////////////////////////////////
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// Rst signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>
//////////////////////////////////////////////////////////////////////////////
module ps2_reg(
//global signal
Clk, // I system clock
Rst, // I system reset
//IPIF Signals
Bus2IP_RegCE, // I [0:7]
Bus2IP_Data, // I [0:7]
Bus2IP_RdReq, // I
Bus2IP_WrReq, // I
IP2Bus_Data, // O [0:7]
IP2Bus_Error, // O
IP2Bus_RdAck, // O
IP2Bus_Retry, // O
IP2Bus_ToutSup, // O
IP2Bus_WrAck, // O
IP2Bus_Intr, // O
//interface signal for memory mapped registers
srst, // O global rest + software reset, send to ps2_sie
rx_full_sta, // O
rx_full_set, // I
rx_err_set, // I
rx_ovf_set, // I
tx_full_sta, // O
tx_full_clr, // I
tx_ack_set, // I
tx_noack_set, // I
wdt_tout_set, // I
tx_data, // O [0:7]
rx_data // I [0:7]
);
///////////////////////////////////////////////////////////////////////////////
//ports
///////////////////////////////////////////////////////////////////////////////
input Clk; // I system clock
input Rst; // I system reset
//IPIF Signals
input [0:7] Bus2IP_RegCE; // I [0:7]
input [0:7] Bus2IP_Data; // I [0:7]
input Bus2IP_RdReq; // I
input Bus2IP_WrReq; // I
output [0:7] IP2Bus_Data; // O [0:7]
output IP2Bus_Error; // O
output IP2Bus_RdAck; // O
output IP2Bus_Retry; // O
output IP2Bus_ToutSup; // O
output IP2Bus_WrAck; // O
output IP2Bus_Intr; // O
//interface signal for memory mapped registers
output srst; // O global rest + software reset, send to ps2_sie
output rx_full_sta; // O
input rx_full_set; // I
input rx_err_set; // I
input rx_ovf_set; // I
output tx_full_sta; // O
input tx_full_clr; // I
input tx_ack_set; // I
input tx_noack_set; // I
input wdt_tout_set; // I
output [0:7] tx_data; // O [0:7]
input [0:7] rx_data; // I [0:7]
///////////////////////////////////////////////////////////////////////////////
//wires
///////////////////////////////////////////////////////////////////////////////
wire srst_ce;
wire sta_ce;
wire tx_data_ce;
wire rx_data_ce;
wire ints_ce;
wire intc_ce ;
wire intms_ce ;
wire intmc_ce ;
wire Bus2IP_Data_srst_d;
wire Bus2IP_Data_wdt_tout;
wire Bus2IP_Data_tx_noack;
wire Bus2IP_Data_tx_ack;
wire Bus2IP_Data_rx_ovf;
wire Bus2IP_Data_rx_err;
wire Bus2IP_Data_rx_full;
reg Bus2IP_RdReq_d1;
reg Bus2IP_WrReq_d1;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg srst_q;
reg [0:7] tx_data_q;
reg [0:7] rx_data_q;
wire rx_full_sta;
wire int_rx_full_q;
wire int_rx_err_q;
wire int_rx_ovf_q;
wire int_tx_ack_q;
wire int_tx_noack_q;
wire int_wdt_tout_q;
wire intm_rx_full_q;
wire intm_rx_err_q;
wire intm_rx_ovf_q;
wire intm_tx_ack_q;
wire intm_tx_noack_q;
wire intm_wdt_tout_q;
///////////////////////////////////////////////////////////////////////////////
//begin
///////////////////////////////////////////////////////////////////////////////
assign srst_ce = Bus2IP_RegCE[0]; // 00 R/W SRST (Soft Reset) bit7
assign sta_ce = Bus2IP_RegCE[1]; // 04 R/W STR (Status Register) bit6:7
assign rx_data_ce = Bus2IP_RegCE[2]; // 08 R/(W) RXR (RX Register bit) bit0:7
assign tx_data_ce = Bus2IP_RegCE[3]; // 0c R/W TXR (TX Register) bit0:7
assign ints_ce = Bus2IP_RegCE[4]; // 10 R INTSTA (Interrupt Status) bit2:7
assign intc_ce = Bus2IP_RegCE[5]; // 14 R/W INTCLR (Interrupt Clear) bit2:7
assign intms_ce = Bus2IP_RegCE[6]; // 18 R/W INTMSET(Interrupt Mask Set) bit2:7
assign intmc_ce = Bus2IP_RegCE[7]; // 1c R/W INTMCLR(Interrupt Mask Clr) bit2:7
assign Bus2IP_Data_srst_d = Bus2IP_Data[7];
// Interrupt bits
// rx_full, rx_err, rx_ovf, tx_ack, tx_noack, wdt_tout
// 2 3 4 5 6 7
assign Bus2IP_Data_wdt_tout = Bus2IP_Data[7];
assign Bus2IP_Data_tx_noack = Bus2IP_Data[6];
assign Bus2IP_Data_tx_ack = Bus2IP_Data[5];
assign Bus2IP_Data_rx_ovf = Bus2IP_Data[4];
assign Bus2IP_Data_rx_err = Bus2IP_Data[3];
assign Bus2IP_Data_rx_full = Bus2IP_Data[2];
assign IP2Bus_Data = (srst_ce) ? {7'h0, srst_q} :
(sta_ce) ? {6'h0, tx_full_sta, rx_full_sta} :
(rx_data_ce) ? rx_data_q:
(tx_data_ce) ? tx_data_q:
(ints_ce | intc_ce) ? {2'h0,int_rx_full_q, int_rx_err_q,
int_rx_ovf_q, int_tx_ack_q,
int_tx_noack_q, int_wdt_tout_q}:
(intms_ce |intmc_ce) ? {2'h0,intm_rx_full_q, intm_rx_err_q,
intm_rx_ovf_q, intm_tx_ack_q,
intm_tx_noack_q,intm_wdt_tout_q}:
8'h00;
//Generate Ack signal after Req edge is detect
always @ (posedge Clk)
begin
if (Rst) begin Bus2IP_RdReq_d1 <= 0;
Bus2IP_WrReq_d1 <= 0;
end
else begin Bus2IP_RdReq_d1 <= Bus2IP_RdReq;
Bus2IP_WrReq_d1 <= Bus2IP_WrReq;
end
end
always @ (posedge Clk)
begin
if (Rst) begin IP2Bus_RdAck <= 0;
IP2Bus_WrAck <= 0;
end
else begin IP2Bus_RdAck <= (Bus2IP_RdReq & (~ Bus2IP_RdReq_d1) );
IP2Bus_WrAck <= (Bus2IP_WrReq & (~ Bus2IP_WrReq_d1) );
end
end
//------------------------------------------
//Signals not used
//------------------------------------------
assign IP2Bus_Error = 1'b0;
assign IP2Bus_Retry = 1'b0;
assign IP2Bus_ToutSup = 1'b0;
//------------------------------------------
//SRST
//Software Reset
//------------------------------------------
always @ (posedge Clk)
begin
if (Rst) srst_q <= 0;
else if (srst_ce && Bus2IP_WrReq) srst_q <= Bus2IP_Data_srst_d;
end
assign srst = srst_q || Rst;
//------------------------------------------
//TX_DATA
//TX data register and full
//------------------------------------------
//tx_data
//write by Host
always @ (posedge Clk)
begin
if (Rst) tx_data_q <= 0;
else if (tx_data_ce && Bus2IP_WrReq) tx_data_q <= Bus2IP_Data;
end
assign tx_data = tx_data_q;
//could be memory mapped, but read-only
//tx_data full register
//set when host writes into TX_DATA register
//Cleared by ps2_sie when finished transmission
FDRE tx_data_fl_reg (
.C (Clk),
.R (srst || tx_full_clr),
.CE (tx_data_ce && Bus2IP_WrReq),
.D (1'b1),
.Q (tx_full_sta)
);
//------------------------------------------
//RX_DATA
//RX data register and full register
//------------------------------------------
//Written by ps2_sie after receiving a byte packet
//Or Written by Host if it wants (rare)
always @ (posedge Clk)
begin
if (Rst) rx_data_q <= 0;
else if (rx_full_set) rx_data_q <= rx_data;
else if (rx_data_ce && Bus2IP_WrReq) rx_data_q <= Bus2IP_Data;
end
//could be memory mapped, but read-only
//rx_data full register
//set when ps2_sie (host write into RX_DATA register won't change it!)
//cleared by when host reads RX_DATA
FDRE rx_data_fl_reg (
.C (Clk),
.R (srst || (rx_data_ce && Bus2IP_RdReq)),
//.CE (rx_full_set || (rx_data_ce && Bus2IP_WrReq)),
.CE (rx_full_set),
.D (1'b1),
.Q (rx_full_sta)
);
//------------------------------------------
//Interrupt Register (Set and Clear)
//rx_full, rx_err, rx_ovf, tx_ack, tx_noack, wdt_tout
//mask=1 interrupt enabled
//mask=0 interrupt disabled (PowerOn)
//------------------------------------------
FDRE int_rx_full_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_full)),
.CE (rx_full_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_rx_full)),
.D (1'b1),
.Q (int_rx_full_q)
);
FDRE int_rx_err_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_err)),
.CE (rx_err_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_rx_err)),
.D (1'b1),
.Q (int_rx_err_q)
);
FDRE int_rx_ovf_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_ovf)),
.CE (rx_ovf_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_rx_ovf)),
.D (1'b1),
.Q (int_rx_ovf_q)
);
FDRE int_tx_ack_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_tx_ack)),
.CE (tx_ack_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_tx_ack)),
.D (1'b1),
.Q (int_tx_ack_q)
);
FDRE int_tx_noack_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_tx_noack)),
.CE (tx_noack_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_tx_noack)),
.D (1'b1),
.Q (int_tx_noack_q)
);
FDRE int_wdt_tout_reg (
.C (Clk),
.R (srst || (intc_ce && Bus2IP_WrReq && Bus2IP_Data_wdt_tout)),
.CE (wdt_tout_set||(ints_ce && Bus2IP_WrReq && Bus2IP_Data_wdt_tout)),
.D (1'b1),
.Q (int_wdt_tout_q)
);
//------------------------------------------
//Interrupt Mask Register (Set and Clear)
//rx_full, rx_err, rx_ovf, tx_ack, tx_noack, wdt_tout
//mask=1 interrupt enabled
//mask=0 interrupt disabled (PowerOn)
//------------------------------------------
FDRE intm_rx_full_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_full)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_rx_full),
.D (1'b1),
.Q (intm_rx_full_q)
);
FDRE intm_rx_err_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_err)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_rx_err),
.D (1'b1),
.Q (intm_rx_err_q)
);
FDRE intm_rx_ovf_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_rx_ovf)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_rx_ovf),
.D (1'b1),
.Q (intm_rx_ovf_q)
);
FDRE intm_tx_ack_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_tx_ack)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_tx_ack),
.D (1'b1),
.Q (intm_tx_ack_q)
);
FDRE intm_tx_noack_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_tx_noack)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_tx_noack),
.D (1'b1),
.Q (intm_tx_noack_q)
);
FDRE intm_wdt_tout_reg (
.C (Clk),
.R (Rst || (intmc_ce && Bus2IP_WrReq && Bus2IP_Data_wdt_tout)),
.CE (intms_ce && Bus2IP_WrReq && Bus2IP_Data_wdt_tout),
.D (1'b1),
.Q (intm_wdt_tout_q)
);
//------------------------------------------
//Interrupt signal
//rx_full, rx_err, rx_ovf, tx_ack, tx_noack, wdt_tout
//mask=1 interrupt enabled
//mask=0 interrupt disabled (PowerOn)
//------------------------------------------
assign IP2Bus_Intr =
(int_rx_full_q & intm_rx_full_q ) |
(int_rx_err_q & intm_rx_err_q ) |
(int_rx_ovf_q & intm_rx_ovf_q ) |
(int_tx_ack_q & intm_tx_ack_q ) |
(int_tx_noack_q & intm_tx_noack_q ) |
(int_wdt_tout_q & intm_wdt_tout_q );
endmodule
|
`timescale 1ns / 1ps
// KCP53002 Furcula to Wishbone bus bridge
//
// Note that Furcula is, in reality, a slight modification of Wishbone.
// Since these two interconnects share so many signals in common, the
// interface to the bridge is kept very small.
module bridge(
// FURCULA BUS
input f_signed_i,
input [1:0] f_siz_i,
input [2:0] f_adr_i,
input [63:0] f_dat_i,
output [63:0] f_dat_o,
// WISHBONE BUS
output [7:0] wb_sel_o,
output [63:0] wb_dat_o,
input [63:0] wb_dat_i
);
// Wishbone SEL_O signal generation.
wire size_byte = (f_siz_i == 2'b00);
wire size_hword = (f_siz_i == 2'b01);
wire size_word = (f_siz_i == 2'b10);
wire size_dword = (f_siz_i == 2'b11);
wire ab7 = f_adr_i[2:0] == 3'b111;
wire ab6 = f_adr_i[2:0] == 3'b110;
wire ab5 = f_adr_i[2:0] == 3'b101;
wire ab4 = f_adr_i[2:0] == 3'b100;
wire ab3 = f_adr_i[2:0] == 3'b011;
wire ab2 = f_adr_i[2:0] == 3'b010;
wire ab1 = f_adr_i[2:0] == 3'b001;
wire ab0 = f_adr_i[2:0] == 3'b000;
wire ah3 = f_adr_i[2:1] == 2'b11;
wire ah2 = f_adr_i[2:1] == 2'b10;
wire ah1 = f_adr_i[2:1] == 2'b01;
wire ah0 = f_adr_i[2:1] == 2'b00;
wire aw1 = f_adr_i[2] == 1'b1;
wire aw0 = f_adr_i[2] == 1'b0;
wire den = size_dword;
wire wen1 = size_word & aw1;
wire wen0 = size_word & aw0;
wire hen3 = size_hword & ah3;
wire hen2 = size_hword & ah2;
wire hen1 = size_hword & ah1;
wire hen0 = size_hword & ah0;
wire ben7 = size_byte & ab7;
wire ben6 = size_byte & ab6;
wire ben5 = size_byte & ab5;
wire ben4 = size_byte & ab4;
wire ben3 = size_byte & ab3;
wire ben2 = size_byte & ab2;
wire ben1 = size_byte & ab1;
wire ben0 = size_byte & ab0;
wire sel7 = den | wen1 | hen3 | ben7;
wire sel6 = den | wen1 | hen3 | ben6;
wire sel5 = den | wen1 | hen2 | ben5;
wire sel4 = den | wen1 | hen2 | ben4;
wire sel3 = den | wen0 | hen1 | ben3;
wire sel2 = den | wen0 | hen1 | ben2;
wire sel1 = den | wen0 | hen0 | ben1;
wire sel0 = den | wen0 | hen0 | ben0;
assign wb_sel_o = {sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0};
// Furcula-to-Wishbone Data Routing
wire [7:0] od7 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[63:56] : 0);
wire [7:0] od6 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[55:48] : 0);
wire [7:0] od5 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[47:40] : 0);
wire [7:0] od4 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[7:0] : 0) |
(size_dword ? f_dat_i[39:32] : 0);
wire [7:0] od3 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[31:24] : 0);
wire [7:0] od2 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[23:16] : 0);
wire [7:0] od1 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[15:8] : 0);
wire [7:0] od0 = f_dat_i[7:0];
assign wb_dat_o = {od7, od6, od5, od4, od3, od2, od1, od0};
// Wishbone to Furcula Data Routing
wire [31:0] id2 =
(wen1 ? wb_dat_i[63:32] : 0) |
(wen0 ? wb_dat_i[31:0] : 0);
wire [15:0] id1 =
(hen3 ? wb_dat_i[63:48] : 0) |
(hen2 ? wb_dat_i[47:32] : 0) |
(hen1 ? wb_dat_i[31:16] : 0) |
(hen0 ? wb_dat_i[15:0] : 0);
wire [7:0] id0 =
(ben7 ? wb_dat_i[63:56] : 0) |
(ben6 ? wb_dat_i[55:48] : 0) |
(ben5 ? wb_dat_i[47:40] : 0) |
(ben4 ? wb_dat_i[39:32] : 0) |
(ben3 ? wb_dat_i[31:24] : 0) |
(ben2 ? wb_dat_i[23:16] : 0) |
(ben1 ? wb_dat_i[15:8] : 0) |
(ben0 ? wb_dat_i[7:0] : 0);
wire [63:32] id2s = (f_signed_i ? {32{id2[31]}} : 32'd0);
wire [63:16] id1s = (f_signed_i ? {48{id1[15]}} : 48'd0);
wire [63:8] id0s = (f_signed_i ? {56{id0[7]}} : 56'd0);
assign f_dat_o =
(size_dword ? wb_dat_i : 0) |
(size_word ? {id2s, id2} : 0) |
(size_hword ? {id1s, id1} : 0) |
(size_byte ? {id0s, id0} : 0);
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
//Date : Wed Jul 20 13:44:49 2016
//Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
//Command : generate_target block_design.bd
//Design : block_design
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=6,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "block_design.hwdef" *)
module block_design
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
leds,
pbs,
sws);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [3:0]leds;
input [3:0]pbs;
input [3:0]sws;
wire [0:0]ARESETN_1;
wire [0:0]S00_ARESETN_1;
wire [3:0]axi_gpio_io_gpio_io_o;
wire axi_gpio_io_ip2intc_irpt;
wire [31:0]axi_interconnect_0_M00_AXI_ARADDR;
wire axi_interconnect_0_M00_AXI_ARREADY;
wire axi_interconnect_0_M00_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M00_AXI_AWADDR;
wire axi_interconnect_0_M00_AXI_AWREADY;
wire axi_interconnect_0_M00_AXI_AWVALID;
wire axi_interconnect_0_M00_AXI_BREADY;
wire [1:0]axi_interconnect_0_M00_AXI_BRESP;
wire axi_interconnect_0_M00_AXI_BVALID;
wire [31:0]axi_interconnect_0_M00_AXI_RDATA;
wire axi_interconnect_0_M00_AXI_RREADY;
wire [1:0]axi_interconnect_0_M00_AXI_RRESP;
wire axi_interconnect_0_M00_AXI_RVALID;
wire [31:0]axi_interconnect_0_M00_AXI_WDATA;
wire axi_interconnect_0_M00_AXI_WREADY;
wire [3:0]axi_interconnect_0_M00_AXI_WSTRB;
wire axi_interconnect_0_M00_AXI_WVALID;
wire [3:0]pbs_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [3:0]sws_1;
wire [8:0]xlconcat_0_dout;
wire [0:0]xlconstant_0_dout;
assign leds[3:0] = axi_gpio_io_gpio_io_o;
assign pbs_1 = pbs[3:0];
assign sws_1 = sws[3:0];
block_design_axi_gpio_0_0 axi_gpio_io
(.gpio2_io_i(xlconcat_0_dout),
.gpio_io_o(axi_gpio_io_gpio_io_o),
.ip2intc_irpt(axi_gpio_io_ip2intc_irpt),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_interconnect_0_M00_AXI_ARADDR[8:0]),
.s_axi_aresetn(S00_ARESETN_1),
.s_axi_arready(axi_interconnect_0_M00_AXI_ARREADY),
.s_axi_arvalid(axi_interconnect_0_M00_AXI_ARVALID),
.s_axi_awaddr(axi_interconnect_0_M00_AXI_AWADDR[8:0]),
.s_axi_awready(axi_interconnect_0_M00_AXI_AWREADY),
.s_axi_awvalid(axi_interconnect_0_M00_AXI_AWVALID),
.s_axi_bready(axi_interconnect_0_M00_AXI_BREADY),
.s_axi_bresp(axi_interconnect_0_M00_AXI_BRESP),
.s_axi_bvalid(axi_interconnect_0_M00_AXI_BVALID),
.s_axi_rdata(axi_interconnect_0_M00_AXI_RDATA),
.s_axi_rready(axi_interconnect_0_M00_AXI_RREADY),
.s_axi_rresp(axi_interconnect_0_M00_AXI_RRESP),
.s_axi_rvalid(axi_interconnect_0_M00_AXI_RVALID),
.s_axi_wdata(axi_interconnect_0_M00_AXI_WDATA),
.s_axi_wready(axi_interconnect_0_M00_AXI_WREADY),
.s_axi_wstrb(axi_interconnect_0_M00_AXI_WSTRB),
.s_axi_wvalid(axi_interconnect_0_M00_AXI_WVALID));
block_design_axi_interconnect_0_0 axi_interconnect_0
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(ARESETN_1),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(S00_ARESETN_1),
.M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),
.M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),
.M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),
.M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),
.M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),
.M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),
.M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),
.M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),
.M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),
.M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),
.M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),
.M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(S00_ARESETN_1),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
block_design_proc_sys_reset_0_0 proc_sys_reset_0
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(ARESETN_1),
.mb_debug_sys_rst(1'b0),
.peripheral_aresetn(S00_ARESETN_1),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
block_design_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.IRQ_F2P(axi_gpio_io_ip2intc_irpt),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
block_design_xlconcat_0_0 xlconcat_0
(.In0(pbs_1),
.In1(sws_1),
.In2(xlconstant_0_dout),
.dout(xlconcat_0_dout));
block_design_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
endmodule
module block_design_axi_interconnect_0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_interconnect_0_ACLK_net;
wire [0:0]axi_interconnect_0_ARESETN_net;
wire [31:0]axi_interconnect_0_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_ARID;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;
wire axi_interconnect_0_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;
wire axi_interconnect_0_to_s00_couplers_ARVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_AWID;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;
wire axi_interconnect_0_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;
wire axi_interconnect_0_to_s00_couplers_AWVALID;
wire [11:0]axi_interconnect_0_to_s00_couplers_BID;
wire axi_interconnect_0_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;
wire axi_interconnect_0_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_RDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_RID;
wire axi_interconnect_0_to_s00_couplers_RLAST;
wire axi_interconnect_0_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;
wire axi_interconnect_0_to_s00_couplers_RVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_WDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_WID;
wire axi_interconnect_0_to_s00_couplers_WLAST;
wire axi_interconnect_0_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_0_to_s00_couplers_WSTRB;
wire axi_interconnect_0_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_axi_interconnect_0_ARADDR;
wire s00_couplers_to_axi_interconnect_0_ARREADY;
wire s00_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]s00_couplers_to_axi_interconnect_0_AWADDR;
wire s00_couplers_to_axi_interconnect_0_AWREADY;
wire s00_couplers_to_axi_interconnect_0_AWVALID;
wire s00_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]s00_couplers_to_axi_interconnect_0_BRESP;
wire s00_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]s00_couplers_to_axi_interconnect_0_RDATA;
wire s00_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]s00_couplers_to_axi_interconnect_0_RRESP;
wire s00_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]s00_couplers_to_axi_interconnect_0_WDATA;
wire s00_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]s00_couplers_to_axi_interconnect_0_WSTRB;
wire s00_couplers_to_axi_interconnect_0_WVALID;
assign M00_AXI_araddr[31:0] = s00_couplers_to_axi_interconnect_0_ARADDR;
assign M00_AXI_arvalid = s00_couplers_to_axi_interconnect_0_ARVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_axi_interconnect_0_AWADDR;
assign M00_AXI_awvalid = s00_couplers_to_axi_interconnect_0_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_interconnect_0_BREADY;
assign M00_AXI_rready = s00_couplers_to_axi_interconnect_0_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_axi_interconnect_0_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_axi_interconnect_0_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_interconnect_0_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_interconnect_0_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_interconnect_0_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_interconnect_0_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;
assign axi_interconnect_0_ACLK_net = M00_ACLK;
assign axi_interconnect_0_ARESETN_net = M00_ARESETN[0];
assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_0_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;
assign s00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;
s00_couplers_imp_1RQO0KS s00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arready(s00_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(s00_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(s00_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awready(s00_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(s00_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(s00_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(s00_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(s00_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(s00_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(s00_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(s00_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(s00_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),
.S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),
.S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),
.S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),
.S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),
.S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),
.S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),
.S_AXI_wid(axi_interconnect_0_to_s00_couplers_WID),
.S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));
endmodule
module s00_couplers_imp_1RQO0KS
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
block_design_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_bCMDMux for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_bCMDMux
// Module Name: NPCG_Toggle_bCMDMux
// File Name: NPCG_Toggle_bCMDMux.v
//
// Version: v1.0.0
//
// Description: NFC PCG layer command multiplexor
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_bCMDMux
#
(
// Multiplexing by ibCMDReadySet[10:0]
// not support parallel primitive command execution
// [11]: MNC_getFT, get features (100101)
// [10]: SCC_N_poe, NAND Power-ON Event (111110)
// [ 9]: SCC_PI_reset, PHY. reset: PI (110010)
// [ 8]: SCC_PO_reset, PHY. reset: PO (110000)
// [ 7]: MNC_N_init, reset: NAND initializing (101100)
// [ 6]: MNC_readST, read status (DDR) (101001)
// [ 5]: MNC_readID, read ID (101011 + length[7:0](option, 00h/40h))
// [ 4]: MNC_setFT, set features (SDR/DDR) (100000/100001 + length[7:0](option, 01h/02h/10h/30h))
// [ 3]: BNC_B_erase, block erase: address write, execute (D0h) (001000)
// [ 2]: BNC_P_program, page program: address write, data transfer (10h) (000100 + length[15:0](length, word))
// [ 1]: BNC_P_read_DT00h, page read (DT): data transfer after read status (00h) (000011 + length[15:0](length, word))
// [ 0]: BNC_P_read_AW30h, page read (AW): address write (30h) (000000)
parameter NumofbCMD = 12, // number of blocking commands
parameter NumberOfWays = 4
)
(
ibCMDReadySet ,
iIDLE_WriteReady ,
iIDLE_ReadData ,
iIDLE_ReadLast ,
iIDLE_ReadValid ,
iIDLE_PM_PCommand ,
iIDLE_PM_PCommandOption ,
iIDLE_PM_TargetWay ,
iIDLE_PM_NumOfData ,
iIDLE_PM_CASelect ,
iIDLE_PM_CAData ,
iIDLE_PM_WriteData ,
iIDLE_PM_WriteLast ,
iIDLE_PM_WriteValid ,
iIDLE_PM_ReadReady ,
iMNC_getFT_ReadData ,
iMNC_getFT_ReadLast ,
iMNC_getFT_ReadValid ,
iMNC_getFT_PM_PCommand ,
iMNC_getFT_PM_PCommandOption ,
iMNC_getFT_PM_TargetWay ,
iMNC_getFT_PM_NumOfData ,
iMNC_getFT_PM_CASelect ,
iMNC_getFT_PM_CAData ,
iMNC_getFT_PM_ReadReady ,
iSCC_N_poe_PM_PCommand ,
iSCC_N_poe_PM_PCommandOption ,
iSCC_N_poe_PM_NumOfData ,
iSCC_PI_reset_PM_PCommand ,
iSCC_PO_reset_PM_PCommand ,
iMNC_N_init_PM_PCommand ,
iMNC_N_init_PM_PCommandOption ,
iMNC_N_init_PM_TargetWay ,
iMNC_N_init_PM_NumOfData ,
iMNC_N_init_PM_CASelect ,
iMNC_N_init_PM_CAData ,
iMNC_readST_ReadData ,
iMNC_readST_ReadLast ,
iMNC_readST_ReadValid ,
iMNC_readST_PM_PCommand ,
iMNC_readST_PM_PCommandOption ,
iMNC_readST_PM_TargetWay ,
iMNC_readST_PM_NumOfData ,
iMNC_readST_PM_CASelect ,
iMNC_readST_PM_CAData ,
iMNC_readST_PM_ReadReady ,
iMNC_setFT_WriteReady ,
iMNC_setFT_PM_PCommand ,
iMNC_setFT_PM_PCommandOption ,
iMNC_setFT_PM_TargetWay ,
iMNC_setFT_PM_NumOfData ,
iMNC_setFT_PM_CASelect ,
iMNC_setFT_PM_CAData ,
iMNC_setFT_PM_WriteData ,
iMNC_setFT_PM_WriteLast ,
iMNC_setFT_PM_WriteValid ,
iBNC_B_erase_PM_PCommand ,
iBNC_B_erase_PM_PCommandOption ,
iBNC_B_erase_PM_TargetWay ,
iBNC_B_erase_PM_NumOfData ,
iBNC_B_erase_PM_CASelect ,
iBNC_B_erase_PM_CAData ,
iBNC_P_prog_WriteReady ,
iBNC_P_prog_PM_PCommand ,
iBNC_P_prog_PM_PCommandOption ,
iBNC_P_prog_PM_TargetWay ,
iBNC_P_prog_PM_NumOfData ,
iBNC_P_prog_PM_CASelect ,
iBNC_P_prog_PM_CAData ,
iBNC_P_prog_PM_WriteData ,
iBNC_P_prog_PM_WriteLast ,
iBNC_P_prog_PM_WriteValid ,
iBNC_P_read_DT00h_ReadData ,
iBNC_P_read_DT00h_ReadLast ,
iBNC_P_read_DT00h_ReadValid ,
iBNC_P_read_DT00h_PM_PCommand ,
iBNC_P_read_DT00h_PM_PCommandOption ,
iBNC_P_read_DT00h_PM_TargetWay ,
iBNC_P_read_DT00h_PM_NumOfData ,
iBNC_P_read_DT00h_PM_CASelect ,
iBNC_P_read_DT00h_PM_CAData ,
iBNC_P_read_DT00h_PM_ReadReady ,
iBNC_P_read_AW30h_PM_PCommand ,
iBNC_P_read_AW30h_PM_PCommandOption ,
iBNC_P_read_AW30h_PM_TargetWay ,
iBNC_P_read_AW30h_PM_NumOfData ,
iBNC_P_read_AW30h_PM_CASelect ,
iBNC_P_read_AW30h_PM_CAData ,
oWriteReady ,
oReadData ,
oReadLast ,
oReadValid ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData ,
oPM_WriteData ,
oPM_WriteLast ,
oPM_WriteValid ,
oPM_ReadReady
);
input [NumofbCMD-1:0] ibCMDReadySet ;
input iIDLE_WriteReady ;
input [31:0] iIDLE_ReadData ;
input iIDLE_ReadLast ;
input iIDLE_ReadValid ;
input [7:0] iIDLE_PM_PCommand ;
input [2:0] iIDLE_PM_PCommandOption ;
input [NumberOfWays - 1:0] iIDLE_PM_TargetWay ;
input [15:0] iIDLE_PM_NumOfData ;
input iIDLE_PM_CASelect ;
input [7:0] iIDLE_PM_CAData ;
input [31:0] iIDLE_PM_WriteData ;
input iIDLE_PM_WriteLast ;
input iIDLE_PM_WriteValid ;
input iIDLE_PM_ReadReady ;
input [31:0] iMNC_getFT_ReadData ;
input iMNC_getFT_ReadLast ;
input iMNC_getFT_ReadValid ;
input [7:0] iMNC_getFT_PM_PCommand ;
input [2:0] iMNC_getFT_PM_PCommandOption ;
input [NumberOfWays - 1:0] iMNC_getFT_PM_TargetWay ;
input [15:0] iMNC_getFT_PM_NumOfData ;
input iMNC_getFT_PM_CASelect ;
input [7:0] iMNC_getFT_PM_CAData ;
input iMNC_getFT_PM_ReadReady ;
input [7:0] iSCC_N_poe_PM_PCommand ;
input [2:0] iSCC_N_poe_PM_PCommandOption ;
input [15:0] iSCC_N_poe_PM_NumOfData ;
input [7:0] iSCC_PI_reset_PM_PCommand ;
input [7:0] iSCC_PO_reset_PM_PCommand ;
input [7:0] iMNC_N_init_PM_PCommand ;
input [2:0] iMNC_N_init_PM_PCommandOption ;
input [NumberOfWays - 1:0] iMNC_N_init_PM_TargetWay ;
input [15:0] iMNC_N_init_PM_NumOfData ;
input iMNC_N_init_PM_CASelect ;
input [7:0] iMNC_N_init_PM_CAData ;
input [31:0] iMNC_readST_ReadData ;
input iMNC_readST_ReadLast ;
input iMNC_readST_ReadValid ;
input [7:0] iMNC_readST_PM_PCommand ;
input [2:0] iMNC_readST_PM_PCommandOption ;
input [NumberOfWays - 1:0] iMNC_readST_PM_TargetWay ;
input [15:0] iMNC_readST_PM_NumOfData ;
input iMNC_readST_PM_CASelect ;
input [7:0] iMNC_readST_PM_CAData ;
input iMNC_readST_PM_ReadReady ;
input iMNC_setFT_WriteReady ;
input [7:0] iMNC_setFT_PM_PCommand ;
input [2:0] iMNC_setFT_PM_PCommandOption ;
input [NumberOfWays - 1:0] iMNC_setFT_PM_TargetWay ;
input [15:0] iMNC_setFT_PM_NumOfData ;
input iMNC_setFT_PM_CASelect ;
input [7:0] iMNC_setFT_PM_CAData ;
input [31:0] iMNC_setFT_PM_WriteData ;
input iMNC_setFT_PM_WriteLast ;
input iMNC_setFT_PM_WriteValid ;
input [7:0] iBNC_B_erase_PM_PCommand ;
input [2:0] iBNC_B_erase_PM_PCommandOption ;
input [NumberOfWays - 1:0] iBNC_B_erase_PM_TargetWay ;
input [15:0] iBNC_B_erase_PM_NumOfData ;
input iBNC_B_erase_PM_CASelect ;
input [7:0] iBNC_B_erase_PM_CAData ;
input iBNC_P_prog_WriteReady ;
input [7:0] iBNC_P_prog_PM_PCommand ;
input [2:0] iBNC_P_prog_PM_PCommandOption ;
input [NumberOfWays - 1:0] iBNC_P_prog_PM_TargetWay ;
input [15:0] iBNC_P_prog_PM_NumOfData ;
input iBNC_P_prog_PM_CASelect ;
input [7:0] iBNC_P_prog_PM_CAData ;
input [31:0] iBNC_P_prog_PM_WriteData ;
input iBNC_P_prog_PM_WriteLast ;
input iBNC_P_prog_PM_WriteValid ;
input [31:0] iBNC_P_read_DT00h_ReadData ;
input iBNC_P_read_DT00h_ReadLast ;
input iBNC_P_read_DT00h_ReadValid ;
input [7:0] iBNC_P_read_DT00h_PM_PCommand ;
input [2:0] iBNC_P_read_DT00h_PM_PCommandOption ;
input [NumberOfWays - 1:0] iBNC_P_read_DT00h_PM_TargetWay ;
input [15:0] iBNC_P_read_DT00h_PM_NumOfData ;
input iBNC_P_read_DT00h_PM_CASelect ;
input [7:0] iBNC_P_read_DT00h_PM_CAData ;
input iBNC_P_read_DT00h_PM_ReadReady ;
input [7:0] iBNC_P_read_AW30h_PM_PCommand ;
input [2:0] iBNC_P_read_AW30h_PM_PCommandOption ;
input [NumberOfWays - 1:0] iBNC_P_read_AW30h_PM_TargetWay ;
input [15:0] iBNC_P_read_AW30h_PM_NumOfData ;
input iBNC_P_read_AW30h_PM_CASelect ;
input [7:0] iBNC_P_read_AW30h_PM_CAData ;
output oWriteReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
output [31:0] oPM_WriteData ;
output oPM_WriteLast ;
output oPM_WriteValid ;
output oPM_ReadReady ;
// Internal Wires/Regs
wire [NumofbCMD-1:0] ibCMDActive ;
//wire wbCMD_idle ;
// - Dispatcher Interface
// - Data Write Channel
reg rWriteReady ;
// - Data Read Channel
reg [31:0] rReadData ;
reg rReadLast ;
reg rReadValid ;
// - NPCG_Toggle Interface
reg [7:0] rPM_PCommand ;
reg [2:0] rPM_PCommandOption ;
reg [NumberOfWays - 1:0] rPM_TargetWay ;
reg [15:0] rPM_NumOfData ;
reg rPM_CASelect ;
reg [7:0] rPM_CAData ;
reg [31:0] rPM_WriteData ;
reg rPM_WriteLast ;
reg rPM_WriteValid ;
reg rPM_ReadReady ;
// Control Signals
//assign wbCMD_idle = ~( &(ibCMDReadySet[NumofbCMD-1:0]) );
assign ibCMDActive[NumofbCMD-1:0] = ~ibCMDReadySet[NumofbCMD-1:0];
// Mux
// Dispatcher Interface
// - Data Write Channel
// rWriteReady
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
//end else if (ibCMDActive[11]) begin // MNC_getFT
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
//end else if (ibCMDActive[ 6]) begin // MNC_readST
//end else if (ibCMDActive[ 5]) begin // MNC_readID
if (ibCMDActive[ 4]) begin // MNC_setFT
rWriteReady <= iMNC_setFT_WriteReady;
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rWriteReady <= iBNC_P_prog_WriteReady;
//end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rWriteReady <= iIDLE_WriteReady;
end
end
// - Data Read Channel
// rReadData[31:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rReadData[31:0] <= iMNC_getFT_ReadData[31:0];
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
end else if (ibCMDActive[ 6]) begin // MNC_readST
rReadData[31:0] <= iMNC_readST_ReadData[31:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
//end else if (ibCMDActive[ 4]) begin // MNC_setFT
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
//end else if (ibCMDActive[ 2]) begin // BNC_P_program
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rReadData[31:0] <= iBNC_P_read_DT00h_ReadData[31:0];
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rReadData[31:0] <= iIDLE_ReadData[31:0];
end
end
// rReadLast
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rReadLast <= iMNC_getFT_ReadLast;
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
end else if (ibCMDActive[ 6]) begin // MNC_readST
rReadLast <= iMNC_readST_ReadLast;
//end else if (ibCMDActive[ 5]) begin // MNC_readID
//end else if (ibCMDActive[ 4]) begin // MNC_setFT
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
//end else if (ibCMDActive[ 2]) begin // BNC_P_program
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rReadLast <= iBNC_P_read_DT00h_ReadLast;
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rReadLast <= iIDLE_ReadLast;
end
end
// rReadValid
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rReadValid <= iMNC_getFT_ReadValid;
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
end else if (ibCMDActive[ 6]) begin // MNC_readST
rReadValid <= iMNC_readST_ReadValid;
//end else if (ibCMDActive[ 5]) begin // MNC_readID
//end else if (ibCMDActive[ 4]) begin // MNC_setFT
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
//end else if (ibCMDActive[ 2]) begin // BNC_P_program
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rReadValid <= iBNC_P_read_DT00h_ReadValid;
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rReadValid <= iIDLE_ReadValid;
end
end
// NPCG_Toggle Interface
// rPM_PCommand[7:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_PCommand[7:0] <= iMNC_getFT_PM_PCommand[7:0];
end else if (ibCMDActive[10]) begin // SCC_N_poe
rPM_PCommand[7:0] <= iSCC_N_poe_PM_PCommand[7:0];
end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
rPM_PCommand[7:0] <= iSCC_PI_reset_PM_PCommand[7:0];
end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
rPM_PCommand[7:0] <= iSCC_PO_reset_PM_PCommand[7:0];
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_PCommand[7:0] <= iMNC_N_init_PM_PCommand[7:0];
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_PCommand[7:0] <= iMNC_readST_PM_PCommand[7:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_PCommand[7:0] <= iMNC_setFT_PM_PCommand[7:0];
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_PCommand[7:0] <= iBNC_B_erase_PM_PCommand[7:0];
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_PCommand[7:0] <= iBNC_P_prog_PM_PCommand[7:0];
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_PCommand[7:0] <= iBNC_P_read_DT00h_PM_PCommand[7:0];
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_PCommand[7:0] <= iBNC_P_read_AW30h_PM_PCommand[7:0];
end else begin // default
rPM_PCommand[7:0] <= iIDLE_PM_PCommand[7:0];
end
end
// rPM_PCommandOption[2:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_PCommandOption[2:0] <= iMNC_getFT_PM_PCommandOption[2:0];
end else if (ibCMDActive[10]) begin // SCC_N_poe
rPM_PCommandOption[2:0] <= iSCC_N_poe_PM_PCommandOption[2:0];
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_PCommandOption[2:0] <= iMNC_N_init_PM_PCommandOption[2:0];
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_PCommandOption[2:0] <= iMNC_readST_PM_PCommandOption[2:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_PCommandOption[2:0] <= iMNC_setFT_PM_PCommandOption[2:0];
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_PCommandOption[2:0] <= iBNC_B_erase_PM_PCommandOption[2:0];
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_PCommandOption[2:0] <= iBNC_P_prog_PM_PCommandOption[2:0];
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_PCommandOption[2:0] <= iBNC_P_read_DT00h_PM_PCommandOption[2:0];
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_PCommandOption[2:0] <= iBNC_P_read_AW30h_PM_PCommandOption[2:0];
end else begin // default
rPM_PCommandOption[2:0] <= iIDLE_PM_PCommandOption[2:0];
end
end
// rPM_TargetWay[NumberOfWays - 1:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_TargetWay[NumberOfWays - 1:0] <= iMNC_getFT_PM_TargetWay[NumberOfWays - 1:0];
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_TargetWay[NumberOfWays - 1:0] <= iMNC_N_init_PM_TargetWay[NumberOfWays - 1:0];
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_TargetWay[NumberOfWays - 1:0] <= iMNC_readST_PM_TargetWay[NumberOfWays - 1:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_TargetWay[NumberOfWays - 1:0] <= iMNC_setFT_PM_TargetWay[NumberOfWays - 1:0];
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_TargetWay[NumberOfWays - 1:0] <= iBNC_B_erase_PM_TargetWay[NumberOfWays - 1:0];
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_TargetWay[NumberOfWays - 1:0] <= iBNC_P_prog_PM_TargetWay[NumberOfWays - 1:0];
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_TargetWay[NumberOfWays - 1:0] <= iBNC_P_read_DT00h_PM_TargetWay[NumberOfWays - 1:0];
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_TargetWay[NumberOfWays - 1:0] <= iBNC_P_read_AW30h_PM_TargetWay[NumberOfWays - 1:0];
end else begin // default
rPM_TargetWay[NumberOfWays - 1:0] <= iIDLE_PM_TargetWay[NumberOfWays - 1:0];
end
end
// rPM_NumOfData[15:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_NumOfData[15:0] <= iMNC_getFT_PM_NumOfData[15:0];
end else if (ibCMDActive[10]) begin // SCC_N_poe
rPM_NumOfData[15:0] <= iSCC_N_poe_PM_NumOfData[15:0];
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_NumOfData[15:0] <= iMNC_N_init_PM_NumOfData[15:0];
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_NumOfData[15:0] <= iMNC_readST_PM_NumOfData[15:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_NumOfData[15:0] <= iMNC_setFT_PM_NumOfData[15:0];
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_NumOfData[15:0] <= iBNC_B_erase_PM_NumOfData[15:0];
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_NumOfData[15:0] <= iBNC_P_prog_PM_NumOfData[15:0];
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_NumOfData[15:0] <= iBNC_P_read_DT00h_PM_NumOfData[15:0];
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_NumOfData[15:0] <= iBNC_P_read_AW30h_PM_NumOfData[15:0];
end else begin // default
rPM_NumOfData[15:0] <= iIDLE_PM_NumOfData[15:0];
end
end
// rPM_CASelect
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_CASelect <= iMNC_getFT_PM_CASelect;
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_CASelect <= iMNC_N_init_PM_CASelect;
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_CASelect <= iMNC_readST_PM_CASelect;
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_CASelect <= iMNC_setFT_PM_CASelect;
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_CASelect <= iBNC_B_erase_PM_CASelect;
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_CASelect <= iBNC_P_prog_PM_CASelect;
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_CASelect <= iBNC_P_read_DT00h_PM_CASelect;
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_CASelect <= iBNC_P_read_AW30h_PM_CASelect;
end else begin // default
rPM_CASelect <= iIDLE_PM_CASelect;
end
end
// rPM_CAData[7:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_CAData[7:0] <= iMNC_getFT_PM_CAData[7:0];
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
end else if (ibCMDActive[ 7]) begin // MNC_N_init
rPM_CAData[7:0] <= iMNC_N_init_PM_CAData[7:0];
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_CAData[7:0] <= iMNC_readST_PM_CAData[7:0];
//end else if (ibCMDActive[ 5]) begin // MNC_readID
end else if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_CAData[7:0] <= iMNC_setFT_PM_CAData[7:0];
end else if (ibCMDActive[ 3]) begin // BNC_B_erase
rPM_CAData[7:0] <= iBNC_B_erase_PM_CAData[7:0];
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_CAData[7:0] <= iBNC_P_prog_PM_CAData[7:0];
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_CAData[7:0] <= iBNC_P_read_DT00h_PM_CAData[7:0];
end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
rPM_CAData[7:0] <= iBNC_P_read_AW30h_PM_CAData[7:0];
end else begin // default
rPM_CAData[7:0] <= iIDLE_PM_CAData[7:0];
end
end
// rPM_WriteData[31:0]
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
//end else if (ibCMDActive[11]) begin // MNC_getFT
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
//end else if (ibCMDActive[ 6]) begin // MNC_readST
//end else if (ibCMDActive[ 5]) begin // MNC_readID
if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_WriteData[31:0] <= iMNC_setFT_PM_WriteData[31:0];
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_WriteData[31:0] <= iBNC_P_prog_PM_WriteData[31:0];
//end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rPM_WriteData[31:0] <= iIDLE_PM_WriteData[31:0];
end
end
// rPM_WriteLast
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
//end else if (ibCMDActive[11]) begin // MNC_getFT
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
//end else if (ibCMDActive[ 6]) begin // MNC_readST
//end else if (ibCMDActive[ 5]) begin // MNC_readID
if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_WriteLast <= iMNC_setFT_PM_WriteLast;
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_WriteLast <= iBNC_P_prog_PM_WriteLast;
//end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rPM_WriteLast <= iIDLE_PM_WriteLast;
end
end
// rPM_WriteValid
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
//end else if (ibCMDActive[11]) begin // MNC_getFT
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
//end else if (ibCMDActive[ 6]) begin // MNC_readST
//end else if (ibCMDActive[ 5]) begin // MNC_readID
if (ibCMDActive[ 4]) begin // MNC_setFT
rPM_WriteValid <= iMNC_setFT_PM_WriteValid;
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
end else if (ibCMDActive[ 2]) begin // BNC_P_program
rPM_WriteValid <= iBNC_P_prog_PM_WriteValid;
//end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rPM_WriteValid <= iIDLE_PM_WriteValid;
end
end
// rPM_ReadReady
always @ (*) begin
//if (wbCMD_idle) begin // All blocking command machines are in inactive state.
if (ibCMDActive[11]) begin // MNC_getFT
rPM_ReadReady <= iMNC_getFT_PM_ReadReady;
//end else if (ibCMDActive[10]) begin // SCC_N_poe
//end else if (ibCMDActive[ 9]) begin // SCC_PI_reset
//end else if (ibCMDActive[ 8]) begin // SCC_PO_reset
//end else if (ibCMDActive[ 7]) begin // MNC_N_init
end else if (ibCMDActive[ 6]) begin // MNC_readST
rPM_ReadReady <= iMNC_readST_PM_ReadReady;
//end else if (ibCMDActive[ 5]) begin // MNC_readID
//end else if (ibCMDActive[ 4]) begin // MNC_setFT
//end else if (ibCMDActive[ 3]) begin // BNC_B_erase
//end else if (ibCMDActive[ 2]) begin // BNC_P_program
end else if (ibCMDActive[ 1]) begin // BNC_P_read_DT00h
rPM_ReadReady <= iBNC_P_read_DT00h_PM_ReadReady;
//end else if (ibCMDActive[ 0]) begin // BNC_P_read_AW30h
end else begin // default
rPM_ReadReady <= iIDLE_PM_ReadReady;
end
end
// Wire Connections
// - Dispatcher Interface
// - Data Write Channel
assign oWriteReady = rWriteReady;
// - Data Read Channel
assign oReadData[31:0] = rReadData[31:0];
assign oReadLast = rReadLast;
assign oReadValid = rReadValid;
// - NPCG_Toggle Interface
assign oPM_PCommand[7:0] = rPM_PCommand[7:0];
assign oPM_PCommandOption[2:0] = rPM_PCommandOption[2:0];
assign oPM_TargetWay[NumberOfWays - 1:0] = rPM_TargetWay[NumberOfWays - 1:0];
assign oPM_NumOfData[15:0] = rPM_NumOfData[15:0];
assign oPM_CASelect = rPM_CASelect;
assign oPM_CAData[7:0] = rPM_CAData[7:0];
assign oPM_WriteData[31:0] = rPM_WriteData[31:0];
assign oPM_WriteLast = rPM_WriteLast;
assign oPM_WriteValid = rPM_WriteValid;
assign oPM_ReadReady = rPM_ReadReady;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_wrlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
// 3. ODT not supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_wrlvl #
(
parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 2,
parameter DRAM_WIDTH = 8,
parameter RANKS = 1,
parameter nCK_PER_CLK = 4,
parameter CLK_PERIOD = 4,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
input phy_ctl_ready,
input wr_level_start,
input wl_sm_start,
input wrlvl_final,
input wrlvl_byte_redo,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
input early1_data,
input early2_data,
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
input oclkdelay_calib_done,
input [(DQ_WIDTH)-1:0] rd_data_rise0,
output reg wrlvl_byte_done,
output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,
output phy_ctl_rdy_dly,
output reg wr_level_done /* synthesis syn_maxfan = 2 */,
// to phy_init for cs logic
output wrlvl_rank_done,
output done_dqs_tap_inc,
output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,
// Fine delay line used only during write leveling
// Inc/dec Phaser_Out fine delay line
output reg dqs_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_po_en_stg2_f,
// Coarse delay line used during write leveling
// only if 64 taps of fine delay line were not
// sufficient to detect a 0->1 transition
// Inc Phaser_Out coarse delay line
output reg dqs_wl_po_stg2_c_incdec,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_wl_po_en_stg2_c,
// Read Phaser_Out delay value
input [8:0] po_counter_read_val,
// output reg dqs_wl_po_stg2_load,
// output reg [8:0] dqs_wl_po_stg2_reg_l,
// CK edge undetected
output reg wrlvl_err,
output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
// Debug ports
output [5:0] dbg_wl_tap_cnt,
output dbg_wl_edge_detect_valid,
output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,
output [DQS_CNT_WIDTH:0] dbg_dqs_count,
output [4:0] dbg_wl_state,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl
);
localparam WL_IDLE = 5'h0;
localparam WL_INIT = 5'h1;
localparam WL_INIT_FINE_INC = 5'h2;
localparam WL_INIT_FINE_INC_WAIT1= 5'h3;
localparam WL_INIT_FINE_INC_WAIT = 5'h4;
localparam WL_INIT_FINE_DEC = 5'h5;
localparam WL_INIT_FINE_DEC_WAIT = 5'h6;
localparam WL_FINE_INC = 5'h7;
localparam WL_WAIT = 5'h8;
localparam WL_EDGE_CHECK = 5'h9;
localparam WL_DQS_CHECK = 5'hA;
localparam WL_DQS_CNT = 5'hB;
localparam WL_2RANK_TAP_DEC = 5'hC;
localparam WL_2RANK_DQS_CNT = 5'hD;
localparam WL_FINE_DEC = 5'hE;
localparam WL_FINE_DEC_WAIT = 5'hF;
localparam WL_CORSE_INC = 5'h10;
localparam WL_CORSE_INC_WAIT = 5'h11;
localparam WL_CORSE_INC_WAIT1 = 5'h12;
localparam WL_CORSE_INC_WAIT2 = 5'h13;
localparam WL_CORSE_DEC = 5'h14;
localparam WL_CORSE_DEC_WAIT = 5'h15;
localparam WL_CORSE_DEC_WAIT1 = 5'h16;
localparam WL_FINE_INC_WAIT = 5'h17;
localparam WL_2RANK_FINAL_TAP = 5'h18;
localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;
localparam WL_FINE_DEC_WAIT1 = 5'h1A;
localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;
localparam COARSE_TAPS = 7;
localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;
localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;
localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;
integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;
reg phy_ctl_ready_r1;
reg phy_ctl_ready_r2;
reg phy_ctl_ready_r3;
reg phy_ctl_ready_r4;
reg phy_ctl_ready_r5;
reg phy_ctl_ready_r6;
(* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;
reg [1:0] rank_cnt_r;
reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;
reg [DQS_WIDTH-1:0] rd_data_previous_r;
reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;
reg wr_level_done_r;
reg wrlvl_rank_done_r;
reg wr_level_start_r;
reg [4:0] wl_state_r, wl_state_r1;
reg inhibit_edge_detect_r;
reg wl_edge_detect_valid_r;
reg [5:0] wl_tap_count_r;
reg [5:0] fine_dec_cnt;
reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each
reg [2:0] corse_dec[0:DQS_WIDTH-1];
reg [2:0] corse_inc[0:DQS_WIDTH-1];
reg dq_cnt_inc;
reg [3:0] stable_cnt;
reg flag_ck_negedge;
//reg past_negedge;
reg flag_init;
reg [2:0] corse_cnt[0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;
reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];
//reg [3*DQS_WIDTH-1:0] coarse_tap_inc;
reg [2:0] final_coarse_tap[0:DQS_WIDTH-1];
reg [5:0] add_smallest[0:DQS_WIDTH-1];
reg [5:0] add_largest[0:DQS_WIDTH-1];
//reg [6*DQS_WIDTH-1:0] fine_tap_inc;
//reg [6*DQS_WIDTH-1:0] fine_tap_dec;
reg wr_level_done_r1;
reg wr_level_done_r2;
reg wr_level_done_r3;
reg wr_level_done_r4;
reg wr_level_done_r5;
reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];
reg [5:0] smallest[0:DQS_WIDTH-1];
reg [5:0] largest[0:DQS_WIDTH-1];
reg [5:0] final_val[0:DQS_WIDTH-1];
reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];
reg done_dqs_dec;
reg [8:0] po_rdval_cnt;
reg po_cnt_dec;
reg po_dec_done;
reg dual_rnk_dec;
wire [DQS_CNT_WIDTH+2:0] dqs_count_w;
reg [5:0] fast_cal_fine_cnt;
reg [2:0] fast_cal_coarse_cnt;
reg wrlvl_byte_redo_r;
reg [2:0] wrlvl_redo_corse_inc;
reg wrlvl_final_r;
reg final_corse_dec;
wire [DQS_CNT_WIDTH+2:0] oclk_count_w;
reg wrlvl_tap_done_r ;
reg [3:0] wait_cnt;
reg [3:0] incdec_wait_cnt;
// Debug ports
assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;
assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;
assign dbg_wl_tap_cnt = wl_tap_count_r;
assign dbg_dqs_count = dqs_count_r;
assign dbg_wl_state = wl_state_r;
assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt;
assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;
always @(*) begin
for (v = 0; v < DQS_WIDTH; v = v + 1)
corse_cnt_dbg[3*v+:3] = corse_cnt[v];
end
assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg;
assign dbg_phy_wrlvl[27+:5] = wl_state_r;
assign dbg_phy_wrlvl[32+:4] = dqs_count_r;
assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;
assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;
assign dbg_phy_wrlvl[54+:4] = stable_cnt;
assign dbg_phy_wrlvl[58] = 'd0;
assign dbg_phy_wrlvl[59] = flag_ck_negedge;
assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;
//**************************************************************************
// DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay
//**************************************************************************
assign po_stg2_wl_cnt = dqs_count_r;
assign wrlvl_rank_done = wrlvl_rank_done_r;
assign done_dqs_tap_inc = done_dqs_dec;
assign phy_ctl_rdy_dly = phy_ctl_ready_r6;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;
wrlvl_final_r <= #TCQ wrlvl_final;
if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
wr_level_done <= #TCQ 1'b0;
else
wr_level_done <= #TCQ done_dqs_dec;
end
// Status signal that will be asserted once the first
// pass of write leveling is done.
always @(posedge clk) begin
if(rst) begin
wrlvl_tap_done_r <= #TCQ 1'b0 ;
end else begin
if(wrlvl_tap_done_r == 1'b0) begin
if(oclkdelay_calib_done) begin
wrlvl_tap_done_r <= #TCQ 1'b1 ;
end
end
end
end
always @(posedge clk) begin
if (rst || po_cnt_dec)
wait_cnt <= #TCQ 'd8;
else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (po_rdval_cnt == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
po_dec_done <= #TCQ 1'b0;
else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
po_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
dqs_po_dec_done <= #TCQ po_dec_done;
wr_level_done_r1 <= #TCQ wr_level_done_r;
wr_level_done_r2 <= #TCQ wr_level_done_r1;
wr_level_done_r3 <= #TCQ wr_level_done_r2;
wr_level_done_r4 <= #TCQ wr_level_done_r3;
wr_level_done_r5 <= #TCQ wr_level_done_r4;
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];
if ((RANKS == 1) || ~oclkdelay_calib_done)
wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];
else
wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];
end
end
generate
if (RANKS == 2) begin: dual_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))
done_dqs_dec <= #TCQ 1'b1;
end
end else begin: single_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if (~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r3 && ~wr_level_done_r4)
done_dqs_dec <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk)
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))
wrlvl_byte_done <= #TCQ 1'b0;
else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)
wrlvl_byte_done <= #TCQ 1'b1;
// Storing DQS tap values at the end of each DQS write leveling
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop
for (n = 0; n < DQS_WIDTH; n = n + 1) begin
wl_corse_cnt[k][n] <= #TCQ 'b0;
wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;
end
end
end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |
(wl_state_r == WL_FINE_DEC_WAIT1) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;
wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r];
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin
for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt
wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;
wl_corse_cnt[p][q] <= #TCQ corse_cnt[0];
end
end
end
end
// Convert coarse delay to fine taps in case of unequal number of coarse
// taps between ranks. Assuming a difference of 1 coarse tap counts
// between ranks. A common fine and coarse tap value must be used for both ranks
// because Phaser_Out has only one rank register.
// Coarse tap1 = period(ps)*93/360 = 34 fine taps
// Other coarse taps = period(ps)*103/360 = 38 fine taps
generate
genvar cnt;
if (RANKS == 2) begin // Dual rank
for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt
always @(posedge clk) begin
if (rst) begin
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ 'd0;
end else if (wr_level_done_r1 & ~wr_level_done_r2) begin
if (~oclkdelay_calib_done) begin
for(y = 0 ; y < DQS_WIDTH; y = y+1) begin
final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y];
add_smallest[y] <= #TCQ 'd0;
add_largest[y] <= #TCQ 'd0;
end
end else
if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin
// Both ranks have use the same number of coarse delay taps.
// No conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin
// Rank 0 uses fewer coarse delay taps than rank1.
// conversion of coarse tap to fine taps required for rank1.
// The final coarse count will the smaller value.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1;
if (|wl_corse_cnt[0][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd34;
end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin
// This may be an unlikely scenario in a real system.
// Rank 0 uses more coarse delay taps than rank1.
// conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
if (|wl_corse_cnt[1][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'smallest' value in final_val
// computation
add_smallest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'smallest' value in
// final_val computation
add_smallest[cnt] <= #TCQ 'd34;
end
end
end
end
end else begin
// Single rank
always @(posedge clk) begin
//coarse_tap_inc <= #TCQ 'd0;
for(w = 0; w < DQS_WIDTH; w = w + 1) begin
final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];
add_smallest[w] <= #TCQ 'd0;
add_largest[w] <= #TCQ 'd0;
end
end
end
endgenerate
// Determine delay value for DQS in multirank system
// Assuming delay value is the smallest for rank 0 DQS
// and largest delay value for rank 4 DQS
// Set to smallest + ((largest-smallest)/2)
always @(posedge clk) begin
if (rst) begin
for(x = 0; x < DQS_WIDTH; x = x +1) begin
smallest[x] <= #TCQ 'b0;
largest[x] <= #TCQ 'b0;
end
end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
end else if ((wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];
end else if (((SIM_CAL_OPTION == "FAST_CAL") |
(~oclkdelay_calib_done & ~wrlvl_byte_redo)) &
wr_level_done_r1 & ~wr_level_done_r2) begin
for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs
smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
largest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
end
end
end
// final_val to be used for all DQSs in all ranks
genvar wr_i;
generate
for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap
always @(posedge clk) begin
if (rst)
final_val[wr_i] <= #TCQ 'b0;
else if (wr_level_done_r2 && ~wr_level_done_r3) begin
if (~oclkdelay_calib_done)
final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]);
else if ((smallest[wr_i] + add_smallest[wr_i]) <
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +
(((largest[wr_i] + add_largest[wr_i]) -
(smallest[wr_i] + add_smallest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) >
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +
(((smallest[wr_i] + add_smallest[wr_i]) -
(largest[wr_i] + add_largest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) ==
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);
end
end
end
endgenerate
// // fine tap inc/dec value for all DQSs in all ranks
// genvar dqs_i;
// generate
// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap
// always @(posedge clk) begin
// if (rst)
// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// else if (wr_level_done_r3 && ~wr_level_done_r4) begin
// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// end
// end
// endgenerate
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
// Fine delay line used only during write leveling
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
// Dec Phaser_Out fine delay (1)before write leveling,
// (2)if no 0 to 1 transition detected with 63 fine delay taps, or
// (3)dual rank case where fine taps for the first rank need to be 0
end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||
(wl_state_r == WL_FINE_DEC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b1;
// Inc Phaser_Out fine delay during write leveling
end else if ((wl_state_r == WL_INIT_FINE_INC) ||
(wl_state_r == WL_FINE_INC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b1;
dqs_po_en_stg2_f <= #TCQ 1'b1;
end else begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
end
end
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write leveling
// only if no 0->1 transition undetected with 64
// fine delay line taps
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end else if (wl_state_r == WL_CORSE_INC) begin
// Inc Phaser_Out coarse delay during write leveling
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end
end
// only storing the rise data for checking. The data comming back during
// write leveling will be a static value. Just checking for rise data is
// enough.
genvar rd_i;
generate
for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd
always @(posedge clk)
rd_data_rise_wl_r[rd_i] <=
#TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];
end
endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||
//(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))
rd_data_previous_r <= #TCQ rd_data_rise_wl_r;
end
// changed stable count from 3 to 7 because of fine tap resolution
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC) |
(wl_state_r == WL_FINE_DEC) |
(rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |
(wl_state_r1 == WL_INIT_FINE_DEC))
stable_cnt <= #TCQ 'd0;
else if ((wl_tap_count_r > 6'd0) &
(((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 'd14))
stable_cnt <= #TCQ stable_cnt + 1;
end
end
// Signal to ensure that flag_ck_negedge does not incorrectly assert
// when DQS is very close to CK rising edge
//always @(posedge clk) begin
// if (rst | (wl_state_r == WL_DQS_CNT) |
// (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
// past_negedge <= #TCQ 1'b0;
// else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
// (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
// (wl_state_r == WL_CORSE_INC_WAIT2)))
// past_negedge <= #TCQ 1'b1;
//end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r |
(wl_state_r1 == WL_INIT_FINE_DEC))
flag_ck_negedge <= #TCQ 1'd0;
else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |
(wl_state_r == WL_CORSE_INC))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
// Flag to inhibit rd_data_edge_detect_r before stable DQ
always @(posedge clk) begin
if (rst)
flag_init <= #TCQ 1'b1;
else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) ||
(wl_state_r1 == WL_INIT_FINE_DEC_WAIT)))
flag_init <= #TCQ 1'b0;
end
//checking for transition from 0 to 1
always @(posedge clk)begin
if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) |
inhibit_edge_detect_r)
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin
if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);
end
// registring the write level start signal
always@(posedge clk) begin
wr_level_start_r <= #TCQ wr_level_start;
end
// Assign dqs_count_r to dqs_count_w to perform the shift operation
// instead of multiply operation
assign dqs_count_w = {2'b00, dqs_count_r};
assign oclk_count_w = {2'b00, oclkdelay_calib_cnt};
always @(posedge clk) begin
if (rst)
incdec_wait_cnt <= #TCQ 'd0;
else if ((wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_INIT_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC_WAIT_TMP))
incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1;
else
incdec_wait_cnt <= #TCQ 'd0;
end
// state machine to initiate the write leveling sequence
// The state machine operates on one byte at a time.
// It will increment the delays to the DQS OSERDES
// and sample the DQ from the memory. When it detects
// a transition from 1 to 0 then the write leveling is considered
// done.
always @(posedge clk) begin
if(rst)begin
wrlvl_err <= #TCQ 1'b0;
wr_level_done_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
dq_cnt_inc <= #TCQ 1'b1;
rank_cnt_r <= #TCQ 2'b00;
wl_state_r <= #TCQ WL_IDLE;
wl_state_r1 <= #TCQ WL_IDLE;
inhibit_edge_detect_r <= #TCQ 1'b1;
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 6'd0;
fine_dec_cnt <= #TCQ 6'd0;
for (r = 0; r < DQS_WIDTH; r = r + 1) begin
fine_inc[r] <= #TCQ 6'b0;
corse_dec[r] <= #TCQ 3'b0;
corse_inc[r] <= #TCQ 3'b0;
corse_cnt[r] <= #TCQ 3'b0;
end
dual_rnk_dec <= #TCQ 1'b0;
fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE;
fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE;
final_corse_dec <= #TCQ 1'b0;
//zero_tran_r <= #TCQ 1'b0;
wrlvl_redo_corse_inc <= #TCQ 'd0;
end else begin
wl_state_r1 <= #TCQ wl_state_r;
case (wl_state_r)
WL_IDLE: begin
wrlvl_rank_done_r <= #TCQ 1'd0;
inhibit_edge_detect_r <= #TCQ 1'b1;
if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ wrcal_cnt;
corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt];
wl_tap_count_r <= #TCQ smallest[wrcal_cnt];
if (early1_data &&
(((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) ||
((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500))))
wrlvl_redo_corse_inc <= #TCQ REDO_COARSE;
else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2))
wrlvl_redo_corse_inc <= #TCQ 3'd6;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if (wrlvl_final && ~wrlvl_final_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ 'd0;
end
// verilint STARC-2.2.3.3 off
if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin
if (SIM_CAL_OPTION == "FAST_CAL")
wl_state_r <= #TCQ WL_FINE_INC;
else
wl_state_r <= #TCQ WL_INIT;
end
end
// verilint STARC-2.2.3.3 on
WL_INIT: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
inhibit_edge_detect_r <= #TCQ 1'b1;
wrlvl_rank_done_r <= #TCQ 1'd0;
//zero_tran_r <= #TCQ 1'b0;
if (wrlvl_final)
corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ];
if (wrlvl_byte_redo) begin
if (|wl_tap_count_r) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if(wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
end
// Initially Phaser_Out fine delay taps incremented
// until stable_cnt=14. A stable_cnt of 14 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 14 fine
// tap increments. This is done to inhibit false 0->1
// edge detection when DQS is initially aligned to the
// negedge of CK
WL_INIT_FINE_INC: begin
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
final_corse_dec <= #TCQ 1'b0;
end
WL_INIT_FINE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT;
end
// Case1: stable value of rd_data_previous_r=0 then
// proceed to 0->1 edge detection.
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_INC_WAIT: begin
if (wl_sm_start) begin
if (stable_cnt < 'd14)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
else if (~rd_data_previous_r[dqs_count_r]) begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end else begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end
end
end
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_DEC: begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_INIT_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT;
end
WL_INIT_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0) begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end
end
// Inc DQS Phaser_Out Stage2 Fine Delay line
WL_FINE_INC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL") begin
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (fast_cal_fine_cnt > 'd0)
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1;
else
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt;
end else if (wr_level_done_r5) begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (|fine_inc[dqs_count_w])
fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
end
end
WL_FINE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_fine_cnt > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
WL_FINE_DEC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_FINE_DEC_WAIT;
end
WL_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0)
wl_state_r <= #TCQ WL_FINE_DEC;
//else if (zero_tran_r)
// wl_state_r <= #TCQ WL_DQS_CNT;
else if (dual_rnk_dec) begin
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else
wl_state_r <= #TCQ WL_CORSE_INC;
end
WL_CORSE_DEC: begin
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;
dual_rnk_dec <= #TCQ 1'b0;
if (|corse_dec[dqs_count_r])
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1;
else
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r];
end
WL_CORSE_DEC_WAIT: begin
if (wl_sm_start) begin
//if (|corse_dec[dqs_count_r])
// wl_state_r <= #TCQ WL_CORSE_DEC;
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end
end
WL_CORSE_DEC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_DEC;
end
WL_CORSE_INC: begin
wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP;
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1;
else
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt;
end else if (wrlvl_byte_redo) begin
corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1;
if (|wrlvl_redo_corse_inc)
wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1;
end else if (~wr_level_done_r5)
corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1;
else if (|corse_inc[dqs_count_w])
corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1;
end
WL_CORSE_INC_WAIT_TMP: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT;
end
WL_CORSE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if (|wrlvl_redo_corse_inc)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_INIT_FINE_INC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end
end else if (~wr_level_done_r5 && wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;
else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
end
WL_CORSE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;
end
WL_CORSE_INC_WAIT2: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_WAIT;
end
WL_WAIT: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK;
end
WL_EDGE_CHECK: begin // Look for the edge
if (wl_edge_detect_valid_r == 1'b0) begin
wl_state_r <= #TCQ WL_WAIT;
wl_edge_detect_valid_r <= #TCQ 1'b1;
end
// 0->1 transition detected with DQS
else if(rd_data_edge_detect_r[dqs_count_r] &&
wl_edge_detect_valid_r)
begin
wl_tap_count_r <= #TCQ wl_tap_count_r;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) ||
~oclkdelay_calib_done)
wl_state_r <= #TCQ WL_DQS_CNT;
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// For initial writes check only upto 56 taps. Reserving the
// remaining taps for OCLK calibration.
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin
if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end else begin
if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal
wl_state_r <= #TCQ WL_FINE_INC;
else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end
end
WL_2RANK_TAP_DEC: begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
for (m = 0; m < DQS_WIDTH; m = m + 1)
corse_dec[m] <= #TCQ corse_cnt[m];
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b1;
end
WL_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1)) ||
wrlvl_byte_redo) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
end
WL_2RANK_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b0;
end
WL_DQS_CHECK: begin // check if all DQS have been calibrated
wl_tap_count_r <= #TCQ 'd0;
if (dq_cnt_inc == 1'b0)begin
wrlvl_rank_done_r <= #TCQ 1'd1;
for (t = 0; t < DQS_WIDTH; t = t + 1)
corse_cnt[t] <= #TCQ 3'b0;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin
wl_state_r <= #TCQ WL_IDLE;
if (wrlvl_byte_redo)
dqs_count_r <= #TCQ dqs_count_r;
else
dqs_count_r <= #TCQ 'd0;
end else if (rank_cnt_r == RANKS-1) begin
dqs_count_r <= #TCQ dqs_count_r;
if (RANKS > 1)
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
else
wl_state_r <= #TCQ WL_IDLE;
end else begin
wl_state_r <= #TCQ WL_INIT;
dqs_count_r <= #TCQ 'd0;
end
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(rank_cnt_r == RANKS-1)) begin
wr_level_done_r <= #TCQ 1'd1;
rank_cnt_r <= #TCQ 2'b00;
end else begin
wr_level_done_r <= #TCQ 1'd0;
rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;
end
end else
wl_state_r <= #TCQ WL_INIT;
end
WL_2RANK_FINAL_TAP: begin
if (wr_level_done_r4 && ~wr_level_done_r5) begin
for(u = 0; u < DQS_WIDTH; u = u + 1) begin
corse_inc[u] <= #TCQ final_coarse_tap[u];
fine_inc[u] <= #TCQ final_val[u];
end
dqs_count_r <= #TCQ 'd0;
end else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
end
end
endcase
end
end // always @ (posedge clk)
endmodule
|
module fifo # (parameter abits = 10, dbits = 8)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count-1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=1;
end
end
else dffw1<=0;
end
always @ (posedge clock)
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1-1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=1;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_SYMBOL_V
|
`define bsg_buf_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_250_BUFX8_b``bits buf_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_250_BUFX8_horiz_b``bits buf_gate (.i0(i),.o);\
end
module bsg_buf #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_buf_macro(89) else
`bsg_buf_macro(88) else
`bsg_buf_macro(87) else
`bsg_buf_macro(86) else
`bsg_buf_macro(85) else
`bsg_buf_macro(84) else
`bsg_buf_macro(83) else
`bsg_buf_macro(82) else
`bsg_buf_macro(81) else
`bsg_buf_macro(80) else
`bsg_buf_macro(79) else
`bsg_buf_macro(78) else
`bsg_buf_macro(77) else
`bsg_buf_macro(76) else
`bsg_buf_macro(75) else
`bsg_buf_macro(74) else
`bsg_buf_macro(73) else
`bsg_buf_macro(72) else
`bsg_buf_macro(71) else
`bsg_buf_macro(70) else
`bsg_buf_macro(69) else
`bsg_buf_macro(68) else
`bsg_buf_macro(67) else
`bsg_buf_macro(66) else
`bsg_buf_macro(65) else
`bsg_buf_macro(64) else
`bsg_buf_macro(63) else
`bsg_buf_macro(62) else
`bsg_buf_macro(61) else
`bsg_buf_macro(60) else
`bsg_buf_macro(59) else
`bsg_buf_macro(58) else
`bsg_buf_macro(57) else
`bsg_buf_macro(56) else
`bsg_buf_macro(55) else
`bsg_buf_macro(54) else
`bsg_buf_macro(53) else
`bsg_buf_macro(52) else
`bsg_buf_macro(51) else
`bsg_buf_macro(50) else
`bsg_buf_macro(49) else
`bsg_buf_macro(48) else
`bsg_buf_macro(47) else
`bsg_buf_macro(46) else
`bsg_buf_macro(45) else
`bsg_buf_macro(44) else
`bsg_buf_macro(43) else
`bsg_buf_macro(42) else
`bsg_buf_macro(41) else
`bsg_buf_macro(40) else
`bsg_buf_macro(39) else
`bsg_buf_macro(38) else
`bsg_buf_macro(37) else
`bsg_buf_macro(36) else
`bsg_buf_macro(35) else
`bsg_buf_macro(34) else
`bsg_buf_macro(33) else
`bsg_buf_macro(32) else
`bsg_buf_macro(31) else
`bsg_buf_macro(30) else
`bsg_buf_macro(29) else
`bsg_buf_macro(28) else
`bsg_buf_macro(27) else
`bsg_buf_macro(26) else
`bsg_buf_macro(25) else
`bsg_buf_macro(24) else
`bsg_buf_macro(23) else
`bsg_buf_macro(22) else
`bsg_buf_macro(21) else
`bsg_buf_macro(20) else
`bsg_buf_macro(19) else
`bsg_buf_macro(18) else
`bsg_buf_macro(17) else
`bsg_buf_macro(16) else
`bsg_buf_macro(15) else
`bsg_buf_macro(14) else
`bsg_buf_macro(13) else
`bsg_buf_macro(12) else
`bsg_buf_macro(11) else
`bsg_buf_macro(10) else
`bsg_buf_macro(9) else
`bsg_buf_macro(8) else
`bsg_buf_macro(7) else
`bsg_buf_macro(6) else
`bsg_buf_macro(5) else
`bsg_buf_macro(4) else
`bsg_buf_macro(3) else
`bsg_buf_macro(2) else
`bsg_buf_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_buf)
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:44:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_rst_ps7_0_49M_0_stub.v
// Design : gcd_zynq_snick_rst_ps7_0_49M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
`include "defines.v"
module age_incr(
input `control_w control0_in,
input `control_w control1_in,
input `control_w control2_in,
input `control_w control3_in,
input `control_w control4_in,
input control4_ready,
input clk,
output reg `control_w control0_out,
output reg `control_w control1_out,
output reg `control_w control2_out,
output reg `control_w control3_out,
output reg `control_w control4_out);
wire [`age_f] age0, age1, age2, age3, age4;
// Update the age
assign age0 = control0_in[`age_f] + 1;
assign age1 = control1_in[`age_f] + 1;
assign age2 = control2_in[`age_f] + 1;
assign age3 = control3_in[`age_f] + 1;
assign age4 = control4_in[`age_f] + 1;
always @(posedge clk) begin
control0_out <= {control0_in[`control_n-1:`age_n], age0};
control1_out <= {control1_in[`control_n-1:`age_n], age1};
control2_out <= {control2_in[`control_n-1:`age_n], age2};
control3_out <= {control3_in[`control_n-1:`age_n], age3};
// We need to be able to kill the resource if it is not valid
if (control4_ready == 1'b0) begin
control4_out <= {1'b0, control4_in[`control_n-2:`age_n], age4};
end else begin
control4_out <= {control4_in[`control_n-1:`age_n], age4};
end
end
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
Section Foo.
Variable X : Type.
Polymorphic Section Bar.
Variable A : Type.
Definition id (a:A) := a.
End Bar.
Check id@{_}.
End Foo.
Check id@{_}.
Polymorphic Section Foo.
Variable A : Type.
Section Bar.
Variable B : Type.
Inductive prod := Prod : A -> B -> prod.
End Bar.
Check prod@{_}.
End Foo.
Check prod@{_ _}.
Section Foo.
Universe K.
Inductive bla := Bla : Type@{K} -> bla.
Polymorphic Definition bli@{j} := Type@{j} -> bla.
Definition bloo := bli@{_}.
Polymorphic Universe i.
Fail Definition x := Type.
Fail Inductive x : Type := .
Polymorphic Definition x := Type.
Polymorphic Inductive y : x := .
Variable A : Type. (* adds a mono univ for the Type, which is unrelated to the others *)
Fail Variable B : (y : Type@{i}).
(* not allowed: mono constraint (about a fresh univ for y) regarding
poly univ i *)
Polymorphic Variable B : Type. (* new polymorphic stuff always OK *)
Variable C : Type@{i}. (* no new univs so no problems *)
Polymorphic Definition thing := bloo -> y -> A -> B.
End Foo.
Check bli@{_}.
Check bloo@{}.
Check thing@{_ _ _}.
Section Foo.
Polymorphic Universes i k.
Universe j.
Fail Constraint i < j.
Fail Constraint i < k.
(* referring to mono univs in poly constraints is OK. *)
Polymorphic Constraint i < j. Polymorphic Constraint j < k.
Polymorphic Definition foo := Type@{j}.
End Foo.
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* DDR2 memory controller block
*/
module ddr2 #(
parameter P0_MASK_SIZE = 4,
parameter P0_DATA_PORT_SIZE = 32,
parameter P1_MASK_SIZE = 4,
parameter P1_DATA_PORT_SIZE = 32,
parameter MEMCLK_PERIOD = 3200,
// Memory data transfer clock period
parameter CALIB_SOFT_IP = "TRUE",
// # = TRUE, Enables the soft calibration logic,
// # = FALSE, Disables the soft calibration logic.
parameter SIMULATION = "FALSE",
// # = TRUE, Simulating the design. Useful to reduce the simulation time,
// # = FALSE, Implementing the design.
parameter MEM_ADDR_ORDER = "ROW_BANK_COLUMN",
// The order in which user address is provided to the memory controller,
// ROW_BANK_COLUMN or BANK_ROW_COLUMN
parameter NUM_DQ_PINS = 16,
// External memory data width
parameter MEM_ADDR_WIDTH = 13,
// External memory address width
parameter MEM_BANKADDR_WIDTH = 3
// External memory bank address width
)
(
// clock and reset
input wire async_rst,
input wire mcb_clk_0,
input wire mcb_clk_180,
input wire mcb_drp_clk,
input wire mcb_clk_locked,
// Calibration status
output wire calib_done,
// DDR2 DRAM connection
output wire [MEM_ADDR_WIDTH-1:0] mcbx_dram_a,
output wire [MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba,
output wire mcbx_dram_ras_n,
output wire mcbx_dram_cas_n,
output wire mcbx_dram_we_n,
output wire mcbx_dram_cke,
output wire mcbx_dram_ck,
output wire mcbx_dram_ck_n,
inout wire [NUM_DQ_PINS-1:0] mcbx_dram_dq,
inout wire mcbx_dram_dqs,
inout wire mcbx_dram_dqs_n,
inout wire mcbx_dram_udqs,
inout wire mcbx_dram_udqs_n,
output wire mcbx_dram_udm,
output wire mcbx_dram_dm,
output wire mcbx_dram_odt,
inout wire mcbx_rzq,
inout wire mcbx_zio,
// MCB ports
// port 0
input wire p0_cmd_clk,
input wire p0_cmd_en,
input wire [2:0] p0_cmd_instr,
input wire [5:0] p0_cmd_bl,
input wire [29:0] p0_cmd_byte_addr,
output wire p0_cmd_empty,
output wire p0_cmd_full,
input wire p0_wr_clk,
input wire p0_wr_en,
input wire [P0_MASK_SIZE-1:0] p0_wr_mask,
input wire [P0_DATA_PORT_SIZE-1:0] p0_wr_data,
output wire p0_wr_empty,
output wire p0_wr_full,
output wire p0_wr_underrun,
output wire [6:0] p0_wr_count,
output wire p0_wr_error,
input wire p0_rd_clk,
input wire p0_rd_en,
output wire [P0_DATA_PORT_SIZE-1:0] p0_rd_data,
output wire p0_rd_empty,
output wire p0_rd_full,
output wire p0_rd_overflow,
output wire [6:0] p0_rd_count,
output wire p0_rd_error,
// port 1
input wire p1_cmd_clk,
input wire p1_cmd_en,
input wire [2:0] p1_cmd_instr,
input wire [5:0] p1_cmd_bl,
input wire [29:0] p1_cmd_byte_addr,
output wire p1_cmd_empty,
output wire p1_cmd_full,
input wire p1_wr_clk,
input wire p1_wr_en,
input wire [P1_MASK_SIZE-1:0] p1_wr_mask,
input wire [P1_DATA_PORT_SIZE-1:0] p1_wr_data,
output wire p1_wr_empty,
output wire p1_wr_full,
output wire p1_wr_underrun,
output wire [6:0] p1_wr_count,
output wire p1_wr_error,
input wire p1_rd_clk,
input wire p1_rd_en,
output wire [P1_DATA_PORT_SIZE-1:0] p1_rd_data,
output wire p1_rd_empty,
output wire p1_rd_full,
output wire p1_rd_overflow,
output wire [6:0] p1_rd_count,
output wire p1_rd_error,
// port 2
input wire p2_cmd_clk,
input wire p2_cmd_en,
input wire [2:0] p2_cmd_instr,
input wire [5:0] p2_cmd_bl,
input wire [29:0] p2_cmd_byte_addr,
output wire p2_cmd_empty,
output wire p2_cmd_full,
input wire p2_rd_clk,
input wire p2_rd_en,
output wire [31:0] p2_rd_data,
output wire p2_rd_empty,
output wire p2_rd_full,
output wire p2_rd_overflow,
output wire [6:0] p2_rd_count,
output wire p2_rd_error,
// port 3
input wire p3_cmd_clk,
input wire p3_cmd_en,
input wire [2:0] p3_cmd_instr,
input wire [5:0] p3_cmd_bl,
input wire [29:0] p3_cmd_byte_addr,
output wire p3_cmd_empty,
output wire p3_cmd_full,
input wire p3_rd_clk,
input wire p3_rd_en,
output wire [31:0] p3_rd_data,
output wire p3_rd_empty,
output wire p3_rd_full,
output wire p3_rd_overflow,
output wire [6:0] p3_rd_count,
output wire p3_rd_error,
// port 4
input wire p4_cmd_clk,
input wire p4_cmd_en,
input wire [2:0] p4_cmd_instr,
input wire [5:0] p4_cmd_bl,
input wire [29:0] p4_cmd_byte_addr,
output wire p4_cmd_empty,
output wire p4_cmd_full,
input wire p4_rd_clk,
input wire p4_rd_en,
output wire [31:0] p4_rd_data,
output wire p4_rd_empty,
output wire p4_rd_full,
output wire p4_rd_overflow,
output wire [6:0] p4_rd_count,
output wire p4_rd_error,
// port 5
input wire p5_cmd_clk,
input wire p5_cmd_en,
input wire [2:0] p5_cmd_instr,
input wire [5:0] p5_cmd_bl,
input wire [29:0] p5_cmd_byte_addr,
output wire p5_cmd_empty,
output wire p5_cmd_full,
input wire p5_rd_clk,
input wire p5_rd_en,
output wire [31:0] p5_rd_data,
output wire p5_rd_empty,
output wire p5_rd_full,
output wire p5_rd_overflow,
output wire [6:0] p5_rd_count,
output wire p5_rd_error
);
// The parameter CX_PORT_ENABLE shows all the active user ports in the design.
// For example, the value 6'b111100 tells that only port-2, port-3, port-4
// and port-5 are enabled. The other two ports are inactive. An inactive port
// can be a disabled port or an invisible logical port. Few examples to the
// invisible logical port are port-4 and port-5 in the user port configuration,
// Config-2: Four 32-bit bi-directional ports and the ports port-2 through
// port-5 in Config-4: Two 64-bit bi-directional ports. Please look into the
// Chapter-2 of ug388.pdf in the /docs directory for further details.
localparam PORT_ENABLE = 6'b111111;
localparam PORT_CONFIG = "B32_B32_R32_R32_R32_R32";
localparam ARB_ALGORITHM = 0;
localparam ARB_NUM_TIME_SLOTS = 12;
localparam ARB_TIME_SLOT_0 = 18'o012345;
localparam ARB_TIME_SLOT_1 = 18'o123450;
localparam ARB_TIME_SLOT_2 = 18'o234501;
localparam ARB_TIME_SLOT_3 = 18'o345012;
localparam ARB_TIME_SLOT_4 = 18'o450123;
localparam ARB_TIME_SLOT_5 = 18'o501234;
localparam ARB_TIME_SLOT_6 = 18'o012345;
localparam ARB_TIME_SLOT_7 = 18'o123450;
localparam ARB_TIME_SLOT_8 = 18'o234501;
localparam ARB_TIME_SLOT_9 = 18'o345012;
localparam ARB_TIME_SLOT_10 = 18'o450123;
localparam ARB_TIME_SLOT_11 = 18'o501234;
localparam MEM_TRAS = 42500;
localparam MEM_TRCD = 12500;
localparam MEM_TREFI = 7800000;
localparam MEM_TRFC = 127500;
localparam MEM_TRP = 12500;
localparam MEM_TWR = 15000;
localparam MEM_TRTP = 7500;
localparam MEM_TWTR = 7500;
localparam MEM_TYPE = "DDR2";
localparam MEM_DENSITY = "1Gb";
localparam MEM_BURST_LEN = 4;
localparam MEM_CAS_LATENCY = 5;
localparam MEM_NUM_COL_BITS = 10;
localparam MEM_DDR1_2_ODS = "FULL";
localparam MEM_DDR2_RTT = "50OHMS";
localparam MEM_DDR2_DIFF_DQS_EN = "YES";
localparam MEM_DDR2_3_PA_SR = "FULL";
localparam MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
localparam MEM_DDR3_CAS_LATENCY = 6;
localparam MEM_DDR3_ODS = "DIV6";
localparam MEM_DDR3_RTT = "DIV2";
localparam MEM_DDR3_CAS_WR_LATENCY = 5;
localparam MEM_DDR3_AUTO_SR = "ENABLED";
localparam MEM_MOBILE_PA_SR = "FULL";
localparam MEM_MDDR_ODS = "FULL";
localparam MC_CALIB_BYPASS = "NO";
localparam MC_CALIBRATION_MODE = "CALIBRATION";
localparam MC_CALIBRATION_DELAY = "HALF";
localparam SKIP_IN_TERM_CAL = 0;
localparam SKIP_DYNAMIC_CAL = 0;
localparam LDQSP_TAP_DELAY_VAL = 0;
localparam LDQSN_TAP_DELAY_VAL = 0;
localparam UDQSP_TAP_DELAY_VAL = 0;
localparam UDQSN_TAP_DELAY_VAL = 0;
localparam DQ0_TAP_DELAY_VAL = 0;
localparam DQ1_TAP_DELAY_VAL = 0;
localparam DQ2_TAP_DELAY_VAL = 0;
localparam DQ3_TAP_DELAY_VAL = 0;
localparam DQ4_TAP_DELAY_VAL = 0;
localparam DQ5_TAP_DELAY_VAL = 0;
localparam DQ6_TAP_DELAY_VAL = 0;
localparam DQ7_TAP_DELAY_VAL = 0;
localparam DQ8_TAP_DELAY_VAL = 0;
localparam DQ9_TAP_DELAY_VAL = 0;
localparam DQ10_TAP_DELAY_VAL = 0;
localparam DQ11_TAP_DELAY_VAL = 0;
localparam DQ12_TAP_DELAY_VAL = 0;
localparam DQ13_TAP_DELAY_VAL = 0;
localparam DQ14_TAP_DELAY_VAL = 0;
localparam DQ15_TAP_DELAY_VAL = 0;
localparam ARB_TIME0_SLOT = {ARB_TIME_SLOT_0[17:15], ARB_TIME_SLOT_0[14:12], ARB_TIME_SLOT_0[11:9], ARB_TIME_SLOT_0[8:6], ARB_TIME_SLOT_0[5:3], ARB_TIME_SLOT_0[2:0]};
localparam ARB_TIME1_SLOT = {ARB_TIME_SLOT_1[17:15], ARB_TIME_SLOT_1[14:12], ARB_TIME_SLOT_1[11:9], ARB_TIME_SLOT_1[8:6], ARB_TIME_SLOT_1[5:3], ARB_TIME_SLOT_1[2:0]};
localparam ARB_TIME2_SLOT = {ARB_TIME_SLOT_2[17:15], ARB_TIME_SLOT_2[14:12], ARB_TIME_SLOT_2[11:9], ARB_TIME_SLOT_2[8:6], ARB_TIME_SLOT_2[5:3], ARB_TIME_SLOT_2[2:0]};
localparam ARB_TIME3_SLOT = {ARB_TIME_SLOT_3[17:15], ARB_TIME_SLOT_3[14:12], ARB_TIME_SLOT_3[11:9], ARB_TIME_SLOT_3[8:6], ARB_TIME_SLOT_3[5:3], ARB_TIME_SLOT_3[2:0]};
localparam ARB_TIME4_SLOT = {ARB_TIME_SLOT_4[17:15], ARB_TIME_SLOT_4[14:12], ARB_TIME_SLOT_4[11:9], ARB_TIME_SLOT_4[8:6], ARB_TIME_SLOT_4[5:3], ARB_TIME_SLOT_4[2:0]};
localparam ARB_TIME5_SLOT = {ARB_TIME_SLOT_5[17:15], ARB_TIME_SLOT_5[14:12], ARB_TIME_SLOT_5[11:9], ARB_TIME_SLOT_5[8:6], ARB_TIME_SLOT_5[5:3], ARB_TIME_SLOT_5[2:0]};
localparam ARB_TIME6_SLOT = {ARB_TIME_SLOT_6[17:15], ARB_TIME_SLOT_6[14:12], ARB_TIME_SLOT_6[11:9], ARB_TIME_SLOT_6[8:6], ARB_TIME_SLOT_6[5:3], ARB_TIME_SLOT_6[2:0]};
localparam ARB_TIME7_SLOT = {ARB_TIME_SLOT_7[17:15], ARB_TIME_SLOT_7[14:12], ARB_TIME_SLOT_7[11:9], ARB_TIME_SLOT_7[8:6], ARB_TIME_SLOT_7[5:3], ARB_TIME_SLOT_7[2:0]};
localparam ARB_TIME8_SLOT = {ARB_TIME_SLOT_8[17:15], ARB_TIME_SLOT_8[14:12], ARB_TIME_SLOT_8[11:9], ARB_TIME_SLOT_8[8:6], ARB_TIME_SLOT_8[5:3], ARB_TIME_SLOT_8[2:0]};
localparam ARB_TIME9_SLOT = {ARB_TIME_SLOT_9[17:15], ARB_TIME_SLOT_9[14:12], ARB_TIME_SLOT_9[11:9], ARB_TIME_SLOT_9[8:6], ARB_TIME_SLOT_9[5:3], ARB_TIME_SLOT_9[2:0]};
localparam ARB_TIME10_SLOT = {ARB_TIME_SLOT_10[17:15], ARB_TIME_SLOT_10[14:12], ARB_TIME_SLOT_10[11:9], ARB_TIME_SLOT_10[8:6], ARB_TIME_SLOT_10[5:3], ARB_TIME_SLOT_10[2:0]};
localparam ARB_TIME11_SLOT = {ARB_TIME_SLOT_11[17:15], ARB_TIME_SLOT_11[14:12], ARB_TIME_SLOT_11[11:9], ARB_TIME_SLOT_11[8:6], ARB_TIME_SLOT_11[5:3], ARB_TIME_SLOT_11[2:0]};
// Unused signals
wire p2_wr_clk;
wire p2_wr_en;
wire [3:0] p2_wr_mask;
wire [31:0] p2_wr_data;
wire p2_wr_full;
wire p2_wr_empty;
wire [6:0] p2_wr_count;
wire p2_wr_underrun;
wire p2_wr_error;
wire p3_wr_clk;
wire p3_wr_en;
wire [3:0] p3_wr_mask;
wire [31:0] p3_wr_data;
wire p3_wr_full;
wire p3_wr_empty;
wire [6:0] p3_wr_count;
wire p3_wr_underrun;
wire p3_wr_error;
wire p4_wr_clk;
wire p4_wr_en;
wire [3:0] p4_wr_mask;
wire [31:0] p4_wr_data;
wire p4_wr_full;
wire p4_wr_empty;
wire [6:0] p4_wr_count;
wire p4_wr_underrun;
wire p4_wr_error;
wire p5_wr_clk;
wire p5_wr_en;
wire [3:0] p5_wr_mask;
wire [31:0] p5_wr_data;
wire p5_wr_full;
wire p5_wr_empty;
wire [6:0] p5_wr_count;
wire p5_wr_underrun;
wire p5_wr_error;
// BUFPLL_MCB to supply clock to MCB
wire sysclk_2x;
wire sysclk_2x_180;
wire pll_ce_0;
wire pll_ce_90;
wire pll_lock;
BUFPLL_MCB
bufpll_mcb_inst
(
.GCLK (mcb_drp_clk),
.PLLIN0 (mcb_clk_0),
.PLLIN1 (mcb_clk_180),
.LOCKED (mcb_clk_locked),
.IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.LOCK (pll_lock)
);
wire async_rst_int;
reset_stretch #(.N(4)) rst_inst (
.clk(mcb_drp_clk),
.rst_in(async_rst | ~pll_lock),
.rst_out(async_rst_int)
);
// MCB wrapper
memc_wrapper #
(
.C_MEMCLK_PERIOD (MEMCLK_PERIOD),
.C_CALIB_SOFT_IP (CALIB_SOFT_IP),
//synthesis translate_off
.C_SIMULATION (SIMULATION),
//synthesis translate_on
.C_ARB_NUM_TIME_SLOTS (ARB_NUM_TIME_SLOTS),
.C_ARB_TIME_SLOT_0 (ARB_TIME0_SLOT),
.C_ARB_TIME_SLOT_1 (ARB_TIME1_SLOT),
.C_ARB_TIME_SLOT_2 (ARB_TIME2_SLOT),
.C_ARB_TIME_SLOT_3 (ARB_TIME3_SLOT),
.C_ARB_TIME_SLOT_4 (ARB_TIME4_SLOT),
.C_ARB_TIME_SLOT_5 (ARB_TIME5_SLOT),
.C_ARB_TIME_SLOT_6 (ARB_TIME6_SLOT),
.C_ARB_TIME_SLOT_7 (ARB_TIME7_SLOT),
.C_ARB_TIME_SLOT_8 (ARB_TIME8_SLOT),
.C_ARB_TIME_SLOT_9 (ARB_TIME9_SLOT),
.C_ARB_TIME_SLOT_10 (ARB_TIME10_SLOT),
.C_ARB_TIME_SLOT_11 (ARB_TIME11_SLOT),
.C_ARB_ALGORITHM (ARB_ALGORITHM),
.C_PORT_ENABLE (PORT_ENABLE),
.C_PORT_CONFIG (PORT_CONFIG),
.C_MEM_TRAS (MEM_TRAS),
.C_MEM_TRCD (MEM_TRCD),
.C_MEM_TREFI (MEM_TREFI),
.C_MEM_TRFC (MEM_TRFC),
.C_MEM_TRP (MEM_TRP),
.C_MEM_TWR (MEM_TWR),
.C_MEM_TRTP (MEM_TRTP),
.C_MEM_TWTR (MEM_TWTR),
.C_MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.C_NUM_DQ_PINS (NUM_DQ_PINS),
.C_MEM_TYPE (MEM_TYPE),
.C_MEM_DENSITY (MEM_DENSITY),
.C_MEM_BURST_LEN (MEM_BURST_LEN),
.C_MEM_CAS_LATENCY (MEM_CAS_LATENCY),
.C_MEM_ADDR_WIDTH (MEM_ADDR_WIDTH),
.C_MEM_BANKADDR_WIDTH (MEM_BANKADDR_WIDTH),
.C_MEM_NUM_COL_BITS (MEM_NUM_COL_BITS),
.C_MEM_DDR1_2_ODS (MEM_DDR1_2_ODS),
.C_MEM_DDR2_RTT (MEM_DDR2_RTT),
.C_MEM_DDR2_DIFF_DQS_EN (MEM_DDR2_DIFF_DQS_EN),
.C_MEM_DDR2_3_PA_SR (MEM_DDR2_3_PA_SR),
.C_MEM_DDR2_3_HIGH_TEMP_SR (MEM_DDR2_3_HIGH_TEMP_SR),
.C_MEM_DDR3_CAS_LATENCY (MEM_DDR3_CAS_LATENCY),
.C_MEM_DDR3_ODS (MEM_DDR3_ODS),
.C_MEM_DDR3_RTT (MEM_DDR3_RTT),
.C_MEM_DDR3_CAS_WR_LATENCY (MEM_DDR3_CAS_WR_LATENCY),
.C_MEM_DDR3_AUTO_SR (MEM_DDR3_AUTO_SR),
.C_MEM_MOBILE_PA_SR (MEM_MOBILE_PA_SR),
.C_MEM_MDDR_ODS (MEM_MDDR_ODS),
.C_MC_CALIB_BYPASS (MC_CALIB_BYPASS),
.C_MC_CALIBRATION_MODE (MC_CALIBRATION_MODE),
.C_MC_CALIBRATION_DELAY (MC_CALIBRATION_DELAY),
.C_SKIP_IN_TERM_CAL (SKIP_IN_TERM_CAL),
.C_SKIP_DYNAMIC_CAL (SKIP_DYNAMIC_CAL),
.LDQSP_TAP_DELAY_VAL (LDQSP_TAP_DELAY_VAL),
.UDQSP_TAP_DELAY_VAL (UDQSP_TAP_DELAY_VAL),
.LDQSN_TAP_DELAY_VAL (LDQSN_TAP_DELAY_VAL),
.UDQSN_TAP_DELAY_VAL (UDQSN_TAP_DELAY_VAL),
.DQ0_TAP_DELAY_VAL (DQ0_TAP_DELAY_VAL),
.DQ1_TAP_DELAY_VAL (DQ1_TAP_DELAY_VAL),
.DQ2_TAP_DELAY_VAL (DQ2_TAP_DELAY_VAL),
.DQ3_TAP_DELAY_VAL (DQ3_TAP_DELAY_VAL),
.DQ4_TAP_DELAY_VAL (DQ4_TAP_DELAY_VAL),
.DQ5_TAP_DELAY_VAL (DQ5_TAP_DELAY_VAL),
.DQ6_TAP_DELAY_VAL (DQ6_TAP_DELAY_VAL),
.DQ7_TAP_DELAY_VAL (DQ7_TAP_DELAY_VAL),
.DQ8_TAP_DELAY_VAL (DQ8_TAP_DELAY_VAL),
.DQ9_TAP_DELAY_VAL (DQ9_TAP_DELAY_VAL),
.DQ10_TAP_DELAY_VAL (DQ10_TAP_DELAY_VAL),
.DQ11_TAP_DELAY_VAL (DQ11_TAP_DELAY_VAL),
.DQ12_TAP_DELAY_VAL (DQ12_TAP_DELAY_VAL),
.DQ13_TAP_DELAY_VAL (DQ13_TAP_DELAY_VAL),
.DQ14_TAP_DELAY_VAL (DQ14_TAP_DELAY_VAL),
.DQ15_TAP_DELAY_VAL (DQ15_TAP_DELAY_VAL),
.C_P0_MASK_SIZE (P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (P1_DATA_PORT_SIZE)
)
memc_wrapper_inst
(
.async_rst (async_rst_int),
.calib_done (calib_done),
.sysclk_2x (sysclk_2x),
.sysclk_2x_180 (sysclk_2x_180),
.pll_ce_0 (pll_ce_0),
.pll_ce_90 (pll_ce_90),
.pll_lock (pll_lock),
.mcb_drp_clk (mcb_drp_clk),
.mcbx_dram_addr (mcbx_dram_a),
.mcbx_dram_ba (mcbx_dram_ba),
.mcbx_dram_ras_n (mcbx_dram_ras_n),
.mcbx_dram_cas_n (mcbx_dram_cas_n),
.mcbx_dram_we_n (mcbx_dram_we_n),
.mcbx_dram_cke (mcbx_dram_cke),
.mcbx_dram_clk (mcbx_dram_ck),
.mcbx_dram_clk_n (mcbx_dram_ck_n),
.mcbx_dram_dq (mcbx_dram_dq),
.mcbx_dram_dqs (mcbx_dram_dqs),
.mcbx_dram_dqs_n (mcbx_dram_dqs_n),
.mcbx_dram_udqs (mcbx_dram_udqs),
.mcbx_dram_udqs_n (mcbx_dram_udqs_n),
.mcbx_dram_udm (mcbx_dram_udm),
.mcbx_dram_ldm (mcbx_dram_dm),
.mcbx_dram_odt (mcbx_dram_odt),
.mcbx_dram_ddr3_rst ( ),
.mcbx_rzq (mcbx_rzq),
.mcbx_zio (mcbx_zio),
// The following port map shows all the six logical user ports. However, all
// of them may not be active in this design. A port should be enabled to
// validate its port map. If it is not,the complete port is going to float
// by getting disconnected from the lower level MCB modules. The port enable
// information of a controller can be obtained from the corresponding local
// parameter CX_PORT_ENABLE. In such a case, we can simply ignore its port map.
// The following comments will explain when a port is going to be active.
// Config-1: Two 32-bit bi-directional and four 32-bit unidirectional ports
// Config-2: Four 32-bit bi-directional ports
// Config-3: One 64-bit bi-directional and two 32-bit bi-directional ports
// Config-4: Two 64-bit bi-directional ports
// Config-5: One 128-bit bi-directional port
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_cmd_clk (p0_cmd_clk),
.p0_cmd_en (p0_cmd_en),
.p0_cmd_instr (p0_cmd_instr),
.p0_cmd_bl (p0_cmd_bl),
.p0_cmd_byte_addr (p0_cmd_byte_addr),
.p0_cmd_full (p0_cmd_full),
.p0_cmd_empty (p0_cmd_empty),
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_wr_clk (p0_wr_clk),
.p0_wr_en (p0_wr_en),
.p0_wr_mask (p0_wr_mask),
.p0_wr_data (p0_wr_data),
.p0_wr_full (p0_wr_full),
.p0_wr_count (p0_wr_count),
.p0_wr_empty (p0_wr_empty),
.p0_wr_underrun (p0_wr_underrun),
.p0_wr_error (p0_wr_error),
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_rd_clk (p0_rd_clk),
.p0_rd_en (p0_rd_en),
.p0_rd_data (p0_rd_data),
.p0_rd_empty (p0_rd_empty),
.p0_rd_count (p0_rd_count),
.p0_rd_full (p0_rd_full),
.p0_rd_overflow (p0_rd_overflow),
.p0_rd_error (p0_rd_error),
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_cmd_clk (p1_cmd_clk),
.p1_cmd_en (p1_cmd_en),
.p1_cmd_instr (p1_cmd_instr),
.p1_cmd_bl (p1_cmd_bl),
.p1_cmd_byte_addr (p1_cmd_byte_addr),
.p1_cmd_full (p1_cmd_full),
.p1_cmd_empty (p1_cmd_empty),
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_wr_clk (p1_wr_clk),
.p1_wr_en (p1_wr_en),
.p1_wr_mask (p1_wr_mask),
.p1_wr_data (p1_wr_data),
.p1_wr_full (p1_wr_full),
.p1_wr_count (p1_wr_count),
.p1_wr_empty (p1_wr_empty),
.p1_wr_underrun (p1_wr_underrun),
.p1_wr_error (p1_wr_error),
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_rd_clk (p1_rd_clk),
.p1_rd_en (p1_rd_en),
.p1_rd_data (p1_rd_data),
.p1_rd_empty (p1_rd_empty),
.p1_rd_count (p1_rd_count),
.p1_rd_full (p1_rd_full),
.p1_rd_overflow (p1_rd_overflow),
.p1_rd_error (p1_rd_error),
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
.p2_cmd_clk (p2_cmd_clk),
.p2_cmd_en (p2_cmd_en),
.p2_cmd_instr (p2_cmd_instr),
.p2_cmd_bl (p2_cmd_bl),
.p2_cmd_byte_addr (p2_cmd_byte_addr),
.p2_cmd_full (p2_cmd_full),
.p2_cmd_empty (p2_cmd_empty),
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
.p2_wr_clk (p2_wr_clk),
.p2_wr_en (p2_wr_en),
.p2_wr_mask (p2_wr_mask),
.p2_wr_data (p2_wr_data),
.p2_wr_full (p2_wr_full),
.p2_wr_count (p2_wr_count),
.p2_wr_empty (p2_wr_empty),
.p2_wr_underrun (p2_wr_underrun),
.p2_wr_error (p2_wr_error),
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
.p2_rd_clk (p2_rd_clk),
.p2_rd_en (p2_rd_en),
.p2_rd_data (p2_rd_data),
.p2_rd_empty (p2_rd_empty),
.p2_rd_count (p2_rd_count),
.p2_rd_full (p2_rd_full),
.p2_rd_overflow (p2_rd_overflow),
.p2_rd_error (p2_rd_error),
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
.p3_cmd_clk (p3_cmd_clk),
.p3_cmd_en (p3_cmd_en),
.p3_cmd_instr (p3_cmd_instr),
.p3_cmd_bl (p3_cmd_bl),
.p3_cmd_byte_addr (p3_cmd_byte_addr),
.p3_cmd_full (p3_cmd_full),
.p3_cmd_empty (p3_cmd_empty),
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
.p3_wr_clk (p3_wr_clk),
.p3_wr_en (p3_wr_en),
.p3_wr_mask (p3_wr_mask),
.p3_wr_data (p3_wr_data),
.p3_wr_full (p3_wr_full),
.p3_wr_count (p3_wr_count),
.p3_wr_empty (p3_wr_empty),
.p3_wr_underrun (p3_wr_underrun),
.p3_wr_error (p3_wr_error),
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
.p3_rd_clk (p3_rd_clk),
.p3_rd_en (p3_rd_en),
.p3_rd_data (p3_rd_data),
.p3_rd_empty (p3_rd_empty),
.p3_rd_count (p3_rd_count),
.p3_rd_full (p3_rd_full),
.p3_rd_overflow (p3_rd_overflow),
.p3_rd_error (p3_rd_error),
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p4_cmd_clk (p4_cmd_clk),
.p4_cmd_en (p4_cmd_en),
.p4_cmd_instr (p4_cmd_instr),
.p4_cmd_bl (p4_cmd_bl),
.p4_cmd_byte_addr (p4_cmd_byte_addr),
.p4_cmd_full (p4_cmd_full),
.p4_cmd_empty (p4_cmd_empty),
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p4_wr_clk (p4_wr_clk),
.p4_wr_en (p4_wr_en),
.p4_wr_mask (p4_wr_mask),
.p4_wr_data (p4_wr_data),
.p4_wr_full (p4_wr_full),
.p4_wr_count (p4_wr_count),
.p4_wr_empty (p4_wr_empty),
.p4_wr_underrun (p4_wr_underrun),
.p4_wr_error (p4_wr_error),
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p4_rd_clk (p4_rd_clk),
.p4_rd_en (p4_rd_en),
.p4_rd_data (p4_rd_data),
.p4_rd_empty (p4_rd_empty),
.p4_rd_count (p4_rd_count),
.p4_rd_full (p4_rd_full),
.p4_rd_overflow (p4_rd_overflow),
.p4_rd_error (p4_rd_error),
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p5_cmd_clk (p5_cmd_clk),
.p5_cmd_en (p5_cmd_en),
.p5_cmd_instr (p5_cmd_instr),
.p5_cmd_bl (p5_cmd_bl),
.p5_cmd_byte_addr (p5_cmd_byte_addr),
.p5_cmd_full (p5_cmd_full),
.p5_cmd_empty (p5_cmd_empty),
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p5_wr_clk (p5_wr_clk),
.p5_wr_en (p5_wr_en),
.p5_wr_mask (p5_wr_mask),
.p5_wr_data (p5_wr_data),
.p5_wr_full (p5_wr_full),
.p5_wr_count (p5_wr_count),
.p5_wr_empty (p5_wr_empty),
.p5_wr_underrun (p5_wr_underrun),
.p5_wr_error (p5_wr_error),
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p5_rd_clk (p5_rd_clk),
.p5_rd_en (p5_rd_en),
.p5_rd_data (p5_rd_data),
.p5_rd_empty (p5_rd_empty),
.p5_rd_count (p5_rd_count),
.p5_rd_full (p5_rd_full),
.p5_rd_overflow (p5_rd_overflow),
.p5_rd_error (p5_rd_error),
.selfrefresh_enter (1'b0),
.selfrefresh_mode (selfrefresh_mode)
);
endmodule
|
/*!
* <b>Module:</b>GTXE2_GPL
* @file GTXE2_GPL.v
* @date 2015-09-08
* @author Alexey
*
* @brief emulates GTXE2_CHANNEL primitive behaviour.
* The file is gathered from multiple files
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GTXE2_GPL.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
/**
* Original unisims primitive's interfaces, according to xilinx's user guide:
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
* referenced as ug476 or UG476
*
* Due to lack of functionality of gtxe2_gpl project as compared to the xilinx's primitive,
* not all of the inputs are used and not all of the outputs are driven.
**/
// cpll reference clock mux
module gtxe2_chnl_cpll_inmux(
input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0,
input wire GTREFCLK1,
input wire GTNORTHREFCLK0,
input wire GTNORTHREFCLK1,
input wire GTSOUTHREFCLK0,
input wire GTSOUTHREFCLK1,
input wire GTGREFCLK,
output wire CPLL_MUX_CLK_OUT
);
// clock multiplexer - pre-syntesis simulation only
assign CPLL_MUX_CLK_OUT = CPLLREFCLKSEL == 3'b000 ? 1'b0 // reserved
: CPLLREFCLKSEL == 3'b001 ? GTREFCLK0
: CPLLREFCLKSEL == 3'b010 ? GTREFCLK1
: CPLLREFCLKSEL == 3'b011 ? GTNORTHREFCLK0
: CPLLREFCLKSEL == 3'b100 ? GTNORTHREFCLK1
: CPLLREFCLKSEL == 3'b101 ? GTSOUTHREFCLK0
: CPLLREFCLKSEL == 3'b110 ? GTSOUTHREFCLK1
: /*CPLLREFCLKSEL == 3'b111 ?*/ GTGREFCLK;
endmodule
module gtxe2_chnl_outclk_mux(
input wire TXPLLREFCLK_DIV1,
input wire TXPLLREFCLK_DIV2,
input wire TXOUTCLKPMA,
input wire TXOUTCLKPCS,
input wire [2:0] TXOUTCLKSEL,
input wire TXDLYBYPASS,
output wire TXOUTCLK
);
assign TXOUTCLK = TXOUTCLKSEL == 3'b001 ? TXOUTCLKPCS
: TXOUTCLKSEL == 3'b010 ? TXOUTCLKPMA
: TXOUTCLKSEL == 3'b011 ? TXPLLREFCLK_DIV1
: TXOUTCLKSEL == 3'b100 ? TXPLLREFCLK_DIV2
: /* 3'b000 */ 1'b1;
endmodule
`timescale 1ps/1ps
`define GTXE2_CHNL_CPLL_LOCK_TIME 60
module gtxe2_chnl_cpll(
// top-level interfaces
input wire CPLLLOCKDETCLK,
input wire CPLLLOCKEN,
input wire CPLLPD,
input wire CPLLRESET, // active high
output wire CPLLFBCLKLOST,
output wire CPLLLOCK,
output wire CPLLREFCLKLOST,
input wire [15:0] GTRSVD,
input wire [15:0] PCSRSVDIN,
input wire [4:0] PCSRSVDIN2,
input wire [4:0] PMARSVDIN,
input wire [4:0] PMARSVDIN2,
input wire [19:0] TSTIN,
output wire [9:0] TSTOUT,
// internal
input wire ref_clk,
output wire clk_out,
output wire pll_locked // equals CPLLLOCK
);
parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
parameter integer CPLL_REFCLK_DIV = 1;
parameter integer RXOUT_DIV = 2;
parameter integer TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter [1:0] PMA_RSV3 = 1;
localparam multiplier = CPLL_FBDIV * CPLL_FBDIV_45;
localparam divider = CPLL_REFCLK_DIV;
assign pll_locked = locked;
assign CPLLLOCK = pll_locked;
wire fb_clk_out;
wire reset;
reg mult_clk;
reg mult_dev_clk;
assign clk_out = mult_dev_clk;
// generate internal async reset
assign reset = CPLLPD | CPLLRESET;
// apply multipliers
time last_edge; // reference clock edge's absolute time
time period; // reference clock's period
integer locked_f;
reg locked;
initial
begin
last_edge = 0;
period = 0;
forever @ (posedge ref_clk or posedge reset)
begin
period = reset ? 0 : $time - (last_edge == 0 ? $time : last_edge);
last_edge = reset ? 0 : $time;
end
end
reg tmp = 0;
initial
begin
@ (posedge reset);
forever @ (posedge ref_clk)
begin
tmp = ~tmp;
if (period > 0)
begin
locked_f = 1;
mult_clk = 1'b1;
repeat (multiplier * 2 - 1)
begin
#(period/multiplier/2)
mult_clk = ~mult_clk;
end
end
else
locked_f = 0;
end
end
// apply dividers
initial
begin
mult_dev_clk = 1'b1;
forever
begin
repeat (divider)
@ (mult_clk);
mult_dev_clk = ~mult_dev_clk;
end
end
// show if 'pll' is locked
reg [31:0] counter;
always @ (posedge ref_clk or posedge reset)
counter <= reset | locked_f == 0 ? 0 : counter == `GTXE2_CHNL_CPLL_LOCK_TIME ? counter : counter + 1;
always @ (posedge ref_clk)
locked <= counter == `GTXE2_CHNL_CPLL_LOCK_TIME;
/*
always @ (posedge ref_clk or posedge reset)
begin
if (locked_f == 1 && ~reset)
begin
repeat (`GTXE2_CHNL_CPLL_LOCK_TIME) @ (posedge ref_clk);
locked <= 1'b1;
end
else
locked <= 1'b0;
end*/
endmodule
/**
* Divides input clock either by input 'div' or by parameter 'divide_by' if divide_by_param
* was set to 1
**/
`ifndef CLOCK_DIVIDER_V
`define CLOCK_DIVIDER_V
// non synthesisable!
module clock_divider(
input wire clk_in,
output reg clk_out,
input wire [31:0] div
);
parameter divide_by = 1;
parameter divide_by_param = 1;
reg [31:0] cnt = 0;
reg [31:0] div_r;
initial
begin
cnt = 0;
clk_out = 1'b1;
forever
begin
if (divide_by_param == 0)
begin
if (div > 32'h0)
div_r = div;
else
div_r = 1;
repeat (div_r)
@ (clk_in);
end
else
begin
repeat (divide_by)
@ (clk_in);
end
clk_out = ~clk_out;
end
end
endmodule
`endif
module gtxe2_chnl_clocking(
// top-level interfaces
input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0,
input wire GTREFCLK1,
input wire GTNORTHREFCLK0,
input wire GTNORTHREFCLK1,
input wire GTSOUTHREFCLK0,
input wire GTSOUTHREFCLK1,
input wire GTGREFCLK,
input wire QPLLCLK,
input wire QPLLREFCLK,
input wire [1:0] RXSYSCLKSEL,
input wire [1:0] TXSYSCLKSEL,
input wire [2:0] TXOUTCLKSEL,
input wire [2:0] RXOUTCLKSEL,
input wire TXDLYBYPASS,
input wire RXDLYBYPASS,
output wire GTREFCLKMONITOR,
input wire CPLLLOCKDETCLK,
input wire CPLLLOCKEN,
input wire CPLLPD,
input wire CPLLRESET,
output wire CPLLFBCLKLOST,
output wire CPLLLOCK,
output wire CPLLREFCLKLOST,
input wire [2:0] TXRATE,
input wire [2:0] RXRATE,
// phy-level interfaces
output wire TXOUTCLKPMA,
output wire TXOUTCLKPCS,
output wire TXOUTCLK,
output wire TXOUTCLKFABRIC,
output wire tx_serial_clk,
output wire tx_piso_clk,
output wire RXOUTCLKPMA,
output wire RXOUTCLKPCS,
output wire RXOUTCLK,
output wire RXOUTCLKFABRIC,
output wire rx_serial_clk,
output wire rx_sipo_clk,
// additional ports to cpll
output [9:0] TSTOUT,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input [4:0] PMARSVDIN2,
input [19:0] TSTIN
);
// CPLL
parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
parameter integer CPLL_REFCLK_DIV = 1;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter [1:0] PMA_RSV3 = 1;
parameter TXOUT_DIV = 2;
//parameter TXRATE = 3'b000;
parameter RXOUT_DIV = 2;
//parameter RXRATE = 3'b000;
parameter TX_INT_DATAWIDTH = 0;
parameter TX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter RX_DATA_WIDTH = 20;
/*
localparam tx_serial_divider = TXRATE == 3'b001 ? 1
: TXRATE == 3'b010 ? 2
: TXRATE == 3'b011 ? 4
: TXRATE == 3'b100 ? 8
: TXRATE == 3'b101 ? 16 : TXOUT_DIV ;
localparam rx_serial_divider = RXRATE == 3'b001 ? 1
: RXRATE == 3'b010 ? 2
: RXRATE == 3'b011 ? 4
: RXRATE == 3'b100 ? 8
: RXRATE == 3'b101 ? 16 : RXOUT_DIV ;
*/
localparam tx_pma_divider1 = TX_INT_DATAWIDTH == 1 ? 4 : 2;
localparam tx_pcs_divider1 = tx_pma_divider1;
localparam tx_pma_divider2 = TX_DATA_WIDTH == 20 | TX_DATA_WIDTH == 40 | TX_DATA_WIDTH == 80 ? 5 : 4;
localparam tx_pcs_divider2 = tx_pma_divider2;
localparam rx_pma_divider1 = RX_INT_DATAWIDTH == 1 ? 4 : 2;
localparam rx_pma_divider2 = RX_DATA_WIDTH == 20 | RX_DATA_WIDTH == 40 | RX_DATA_WIDTH == 80 ? 5 : 4;
wire clk_mux_out;
wire cpll_clk_out;
wire tx_phy_clk;
wire rx_phy_clk;
wire TXPLLREFCLK_DIV1;
wire TXPLLREFCLK_DIV2;
wire RXPLLREFCLK_DIV1;
wire RXPLLREFCLK_DIV2;
assign tx_phy_clk = TXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
assign TXPLLREFCLK_DIV1 = TXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out;
assign rx_phy_clk = RXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
assign RXPLLREFCLK_DIV1 = RXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out;
assign tx_serial_clk = tx_phy_clk;
assign rx_serial_clk = rx_phy_clk;
// piso and sipo clocks
// are not used in the design - no need to use ddr mode during simulation. much easier just multi serial clk by 2
wire [31:0] tx_serial_divider;
wire [31:0] rx_serial_divider;
assign tx_serial_divider = TXRATE == 3'b001 ? 1
: TXRATE == 3'b010 ? 2
: TXRATE == 3'b011 ? 4
: TXRATE == 3'b100 ? 8
: TXRATE == 3'b101 ? 16 : TXOUT_DIV ;
assign rx_serial_divider = RXRATE == 3'b001 ? 1
: RXRATE == 3'b010 ? 2
: RXRATE == 3'b011 ? 4
: RXRATE == 3'b100 ? 8
: RXRATE == 3'b101 ? 16 : RXOUT_DIV ;
clock_divider #(
// .divide_by (tx_serial_divider),
.divide_by_param (0)
)
tx_toserialclk_div(
.clk_in (tx_phy_clk),
.clk_out (tx_piso_clk),
.div (tx_serial_divider)
);
clock_divider #(
// .divide_by (rx_serial_divider),
.divide_by_param (0)
)
rx_toserialclk_div(
.clk_in (rx_phy_clk),
.clk_out (rx_sipo_clk),
.div (rx_serial_divider)
);
// TXOUTCLKPCS/TXOUTCLKPMA generation
wire tx_pma_div1_clk;
assign TXOUTCLKPCS = TXOUTCLKPMA;
clock_divider #(
.divide_by (tx_pma_divider1)
)
tx_pma_div1(
.div (1),
.clk_in (tx_piso_clk),
.clk_out (tx_pma_div1_clk)
);
clock_divider #(
.divide_by (tx_pma_divider2)
)
tx_pma_div2(
.div (1),
.clk_in (tx_pma_div1_clk),
.clk_out (TXOUTCLKPMA)
);
// RXOUTCLKPCS/RXOUTCLKPMA generation
wire rx_pma_div1_clk;
assign RXOUTCLKPCS = RXOUTCLKPMA;
clock_divider #(
.divide_by (rx_pma_divider1)
)
rx_pma_div1(
.div (1),
.clk_in (rx_sipo_clk),
.clk_out (rx_pma_div1_clk)
);
clock_divider #(
.divide_by (rx_pma_divider2)
)
rx_pma_div2(
.div (1),
.clk_in (rx_pma_div1_clk),
.clk_out (RXOUTCLKPMA)
);
//
clock_divider #(
.divide_by (2)
)
txpllrefclk_div2(
.div (1),
.clk_in (TXPLLREFCLK_DIV1),
.clk_out (TXPLLREFCLK_DIV2)
);
clock_divider #(
.divide_by (2)
)
rxpllrefclk_div2(
.div (1),
.clk_in (RXPLLREFCLK_DIV1),
.clk_out (RXPLLREFCLK_DIV2)
);
gtxe2_chnl_outclk_mux tx_out_mux(
.TXPLLREFCLK_DIV1 (TXPLLREFCLK_DIV1),
.TXPLLREFCLK_DIV2 (TXPLLREFCLK_DIV2),
.TXOUTCLKPMA (TXOUTCLKPMA),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLKSEL (TXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.TXOUTCLK (TXOUTCLK)
);
gtxe2_chnl_outclk_mux rx_out_mux(
.TXPLLREFCLK_DIV1 (RXPLLREFCLK_DIV1),
.TXPLLREFCLK_DIV2 (RXPLLREFCLK_DIV2),
.TXOUTCLKPMA (RXOUTCLKPMA),
.TXOUTCLKPCS (RXOUTCLKPCS),
.TXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (RXDLYBYPASS),
.TXOUTCLK (RXOUTCLK)
);
gtxe2_chnl_cpll_inmux clk_mux(
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.CPLL_MUX_CLK_OUT (clk_mux_out)
);
gtxe2_chnl_cpll #(
.CPLL_FBDIV (4),
.CPLL_FBDIV_45 (5),
.CPLL_REFCLK_DIV (1)
)
cpll(
.CPLLLOCKDETCLK (CPLLLOCKDETCLK),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.PCSRSVDIN2 (PCSRSVDIN2),
.PMARSVDIN (PMARSVDIN),
.PMARSVDIN2 (PMARSVDIN2),
.TSTIN (TSTIN),
.TSTOUT (TSTOUT),
.ref_clk (clk_mux_out),
.clk_out (cpll_clk_out),
.pll_locked ()
);
endmodule
// simplified resynchronisation fifo, could cause metastability
// because of that shall not be syntesisable
// TODO add shift registers and gray code to fix that
`ifndef RESYNC_FIFO_NOSYNT_V
`define RESYNC_FIFO_NOSYNT_V
module resync_fifo_nonsynt #(
parameter [31:0] width = 20,
//parameter [31:0] depth = 7
parameter [31:0] log_depth = 3
)
(
input wire rst_rd,
input wire rst_wr,
input wire clk_wr,
input wire val_wr,
input wire [width - 1:0] data_wr,
input wire clk_rd,
input wire val_rd,
output wire [width - 1:0] data_rd,
output wire empty_rd,
output wire almost_empty_rd,
output wire full_wr
);
/*
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
localparam log_depth = clogb2(depth);
*/
localparam depth = 1 << log_depth;
reg [width -1:0] fifo [depth - 1:0];
// wr_clk domain
reg [log_depth - 1:0] cnt_wr;
// rd_clk domain
reg [log_depth - 1:0] cnt_rd;
assign data_rd = fifo[cnt_rd];
assign empty_rd = cnt_wr == cnt_rd;
assign full_wr = (cnt_wr + 1'b1) == cnt_rd;
assign almost_empty_rd = (cnt_rd + 1'b1) == cnt_wr;
always @ (posedge clk_wr)
fifo[cnt_wr] <= val_wr ? data_wr : fifo[cnt_wr];
always @ (posedge clk_wr)
cnt_wr <= rst_wr ? 0 : val_wr ? cnt_wr + 1'b1 : cnt_wr;
always @ (posedge clk_rd)
cnt_rd <= rst_rd ? 0 : val_rd ? cnt_rd + 1'b1 : cnt_rd;
endmodule
`endif
module gtxe2_chnl_tx_ser #(
parameter [31:0] width = 20
)
(
input wire reset,
input wire trim,
input wire inclk,
input wire outclk,
input wire [width - 1:0] indata,
input wire idle_in,
output wire outdata,
output wire idle_out
);
localparam trimmed_width = width * 4 / 5;
reg [31:0] bitcounter;
wire [width - 1:0] data_resynced;
wire almost_empty_rd;
wire empty_rd;
wire full_wr;
wire val_rd;
wire bitcounter_limit;
assign bitcounter_limit = trim ? bitcounter == (trimmed_width - 1) : bitcounter == (width - 1);
always @ (posedge outclk)
bitcounter <= reset | bitcounter_limit ? 32'h0 : bitcounter + 1'b1;
assign outdata = data_resynced[bitcounter];
assign val_rd = ~almost_empty_rd & ~empty_rd & bitcounter_limit;
resync_fifo_nonsynt #(
.width (width + 1), // +1 is for a flag of an idle line (both TXP and TXN = 0)
.log_depth (3)
)
fifo(
.rst_rd (reset),
.rst_wr (reset),
.clk_wr (inclk),
.val_wr (1'b1),
.data_wr ({idle_in, indata}),
.clk_rd (outclk),
.val_rd (val_rd),
.data_rd ({idle_out, data_resynced}),
.empty_rd (empty_rd),
.full_wr (full_wr),
.almost_empty_rd (almost_empty_rd)
);
endmodule
// for some reason overall trasmitted disparity is tracked at the top level
module gtxe2_chnl_tx_8x10enc #(
parameter iwidth = 16,
parameter iskwidth = 2,
parameter owidth = 20
)
(
input wire [iskwidth - 1:0] TX8B10BBYPASS,
input wire TX8B10BEN,
input wire [iskwidth - 1:0] TXCHARDISPMODE,
input wire [iskwidth - 1:0] TXCHARDISPVAL,
input wire [iskwidth - 1:0] TXCHARISK,
input wire disparity,
input wire [iwidth - 1:0] data_in,
output wire [owidth - 1:0] data_out,
output wire next_disparity
);
wire [owidth - 1:0] enc_data_out;
wire [owidth - 1:0] bp_data_out;
assign data_out = TX8B10BEN ? enc_data_out : bp_data_out;
// only full 8/10 encoding and width=20 case is implemented
localparam word_count = owidth / 10;
wire [word_count - 1:0] word_disparity;
wire [word_count - 1:0] interm_disparity;
wire [5:0] six [word_count - 1:0];
wire [3:0] four [word_count - 1:0];
wire [9:0] oword [word_count - 1:0];
wire [iwidth - 1:0] iword [word_count - 1:0];
wire [word_count - 1:0] is_control;
// typical approach: 8x10 = 5x6 + 3x4
// word disparity[i] = calculated disparity for the i-th 8-bit word
// interm_disparity[i] - disparity after 5x6 encoding for the i-th word
genvar ii;
generate
for (ii = 0; ii < 2; ii = ii + 1)
begin: encode_by_word
assign is_control[ii] = TXCHARISK[ii];
assign iword[ii] = data_in[ii*8 + 7:ii*8];
assign interm_disparity[ii]= ^six[ii] ? word_disparity[ii] : ~word_disparity[ii];
assign word_disparity[ii] = (ii == 0) ? disparity :
(^oword[ii - 1] ? word_disparity[ii - 1] : ~word_disparity[ii - 1]); // if there're 5 '1's - do no change the disparity, 6 or 4 - change
assign six[ii] = iword[ii][4:0] == 5'b00000 ? (~word_disparity[ii] ? 6'b100111 : 6'b011000)
: iword[ii][4:0] == 5'b00001 ? (~word_disparity[ii] ? 6'b011101 : 6'b100010)
: iword[ii][4:0] == 5'b00010 ? (~word_disparity[ii] ? 6'b101101 : 6'b010010)
: iword[ii][4:0] == 5'b00011 ? (~word_disparity[ii] ? 6'b110001 : 6'b110001)
: iword[ii][4:0] == 5'b00100 ? (~word_disparity[ii] ? 6'b110101 : 6'b001010)
: iword[ii][4:0] == 5'b00101 ? (~word_disparity[ii] ? 6'b101001 : 6'b101001)
: iword[ii][4:0] == 5'b00110 ? (~word_disparity[ii] ? 6'b011001 : 6'b011001)
: iword[ii][4:0] == 5'b00111 ? (~word_disparity[ii] ? 6'b111000 : 6'b000111)
: iword[ii][4:0] == 5'b01000 ? (~word_disparity[ii] ? 6'b111001 : 6'b000110)
: iword[ii][4:0] == 5'b01001 ? (~word_disparity[ii] ? 6'b100101 : 6'b100101)
: iword[ii][4:0] == 5'b01010 ? (~word_disparity[ii] ? 6'b010101 : 6'b010101)
: iword[ii][4:0] == 5'b01011 ? (~word_disparity[ii] ? 6'b110100 : 6'b110100)
: iword[ii][4:0] == 5'b01100 ? (~word_disparity[ii] ? 6'b001101 : 6'b001101)
: iword[ii][4:0] == 5'b01101 ? (~word_disparity[ii] ? 6'b101100 : 6'b101100)
: iword[ii][4:0] == 5'b01110 ? (~word_disparity[ii] ? 6'b011100 : 6'b011100)
: iword[ii][4:0] == 5'b01111 ? (~word_disparity[ii] ? 6'b010111 : 6'b101000)
: iword[ii][4:0] == 5'b10000 ? (~word_disparity[ii] ? 6'b011011 : 6'b100100)
: iword[ii][4:0] == 5'b10001 ? (~word_disparity[ii] ? 6'b100011 : 6'b100011)
: iword[ii][4:0] == 5'b10010 ? (~word_disparity[ii] ? 6'b010011 : 6'b010011)
: iword[ii][4:0] == 5'b10011 ? (~word_disparity[ii] ? 6'b110010 : 6'b110010)
: iword[ii][4:0] == 5'b10100 ? (~word_disparity[ii] ? 6'b001011 : 6'b001011)
: iword[ii][4:0] == 5'b10101 ? (~word_disparity[ii] ? 6'b101010 : 6'b101010)
: iword[ii][4:0] == 5'b10110 ? (~word_disparity[ii] ? 6'b011010 : 6'b011010)
: iword[ii][4:0] == 5'b10111 ? (~word_disparity[ii] ? 6'b111010 : 6'b000101)
: iword[ii][4:0] == 5'b11000 ? (~word_disparity[ii] ? 6'b110011 : 6'b001100)
: iword[ii][4:0] == 5'b11001 ? (~word_disparity[ii] ? 6'b100110 : 6'b100110)
: iword[ii][4:0] == 5'b11010 ? (~word_disparity[ii] ? 6'b010110 : 6'b010110)
: iword[ii][4:0] == 5'b11011 ? (~word_disparity[ii] ? 6'b110110 : 6'b001001)
: iword[ii][4:0] == 5'b11100 ? (~word_disparity[ii] ? 6'b001110 : 6'b001110)
: iword[ii][4:0] == 5'b11101 ? (~word_disparity[ii] ? 6'b101110 : 6'b010001)
: iword[ii][4:0] == 5'b11110 ? (~word_disparity[ii] ? 6'b011110 : 6'b100001)
:/*iword[ii][4:0] == 5'b11111*/(~word_disparity[ii] ? 6'b101011 : 6'b010100);
assign four[ii] = iword[ii][7:5] == 3'd0 ? (~interm_disparity[ii] ? 4'b1011 : 4'b0100)
: iword[ii][7:5] == 3'd1 ? (~interm_disparity[ii] ? 4'b1001 : 4'b1001)
: iword[ii][7:5] == 3'd2 ? (~interm_disparity[ii] ? 4'b0101 : 4'b0101)
: iword[ii][7:5] == 3'd3 ? (~interm_disparity[ii] ? 4'b1100 : 4'b0011)
: iword[ii][7:5] == 3'd4 ? (~interm_disparity[ii] ? 4'b1101 : 4'b0010)
: iword[ii][7:5] == 3'd5 ? (~interm_disparity[ii] ? 4'b1010 : 4'b1010)
: iword[ii][7:5] == 3'd6 ? (~interm_disparity[ii] ? 4'b0110 : 4'b0110)
:/*iword[ii][7:5] == 3'd7*/(~interm_disparity[ii] ? (six[ii][1:0] == 2'b11 ? 4'b0111 : 4'b1110)
: (six[ii][1:0] == 2'b00 ? 4'b1000 : 4'b0001));
assign oword[ii] = ~is_control[ii] ? {six[ii], four[ii]}
: iword[ii][7:0] == 8'b00011100 ? (~word_disparity[ii] ? 10'b0011110100 : 10'b1100001011)
: iword[ii][7:0] == 8'b00111100 ? (~word_disparity[ii] ? 10'b0011111001 : 10'b1100000110)
: iword[ii][7:0] == 8'b01011100 ? (~word_disparity[ii] ? 10'b0011110101 : 10'b1100001010)
: iword[ii][7:0] == 8'b01111100 ? (~word_disparity[ii] ? 10'b0011110011 : 10'b1100001100)
: iword[ii][7:0] == 8'b10011100 ? (~word_disparity[ii] ? 10'b0011110010 : 10'b1100001101)
: iword[ii][7:0] == 8'b10111100 ? (~word_disparity[ii] ? 10'b0011111010 : 10'b1100000101)
: iword[ii][7:0] == 8'b11011100 ? (~word_disparity[ii] ? 10'b0011110110 : 10'b1100001001)
: iword[ii][7:0] == 8'b11111100 ? (~word_disparity[ii] ? 10'b0011111000 : 10'b1100000111)
: iword[ii][7:0] == 8'b11110111 ? (~word_disparity[ii] ? 10'b1110101000 : 10'b0001010111)
: iword[ii][7:0] == 8'b11111011 ? (~word_disparity[ii] ? 10'b1101101000 : 10'b0010010111)
: iword[ii][7:0] == 8'b11111101 ? (~word_disparity[ii] ? 10'b1011101000 : 10'b0100010111)
:/*iword[ii][7:0] == 8'b11111110*/(~word_disparity[ii] ? 10'b0111101000 : 10'b1000010111);
assign enc_data_out[ii*10 + 9:ii * 10] = oword[ii];
// case of a disabled encoder
assign bp_data_out[ii*10 + 9:ii*10] = {TXCHARDISPMODE[ii], TXCHARDISPVAL[ii], data_in[ii*8 + 7:ii*8]};
end
endgenerate
assign next_disparity = ^oword[word_count - 1] ? word_disparity[word_count - 1] : ~word_disparity[word_count - 1];
endmodule
module gtxe2_chnl_tx_oob #(
parameter width = 20
)
(
// top-level ifaces
input wire TXCOMINIT,
input wire TXCOMWAKE,
output wire TXCOMFINISH,
// internal ifaces
input wire clk,
input wire reset,
input wire disparity,
output wire [width - 1:0] outdata,
output wire outval
);
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b0101;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
localparam burst_len_mult = SATA_CPLL_CFG == "VCO_3000MHZ" ? 2 // assuming each usrclk cycle == 20 sata serial clk cycles
: SATA_CPLL_CFG == "VCO_1500MHZ" ? 4
: /* VCO_6000MHZ */ 1;
localparam burst_len = /*burst_len_mult * 8*/ 32; // = 106.7ns; each burst contains 16 SATA Gen1 words
localparam quiet_len_init = burst_len * 3; // = 320ns
localparam quiet_len_wake = burst_len; // = 106.7ns
localparam init_bursts_cnt = SATA_BURST_SEQ_LEN;//3;
localparam wake_bursts_cnt = SATA_BURST_SEQ_LEN;//5;
reg [31:0] bursts_cnt;
reg [31:0] stopwatch;
wire stopwatch_clr;
wire bursts_cnt_inc;
wire bursts_cnt_clr;
wire [31:0] quiet_len;
// FSM Declarations
reg state_burst;
reg state_quiet;
wire state_idle;
wire set_burst;
wire set_quiet;
wire clr_burst;
wire clr_quiet;
// remember what command was issued
reg issued_init;
reg issued_wake;
always @ (posedge clk)
begin
issued_init <= reset | TXCOMFINISH | issued_wake ? 1'b0 : TXCOMINIT ? 1'b1 : state_idle ? 1'b0 : issued_init;
issued_wake <= reset | TXCOMFINISH | issued_init ? 1'b0 : TXCOMWAKE ? 1'b1 : state_idle ? 1'b0 : issued_wake;
end
wire [31:0] bursts_cnt_togo;
assign bursts_cnt_togo = issued_wake ? wake_bursts_cnt : init_bursts_cnt ;
// FSM
assign state_idle = ~state_burst & ~state_quiet;
always @ (posedge clk)
begin
state_burst <= (state_burst | set_burst) & ~reset & ~clr_burst;
state_quiet <= (state_quiet | set_quiet) & ~reset & ~clr_quiet;
end
assign set_burst = state_idle & (TXCOMINIT | TXCOMWAKE) | state_quiet & clr_quiet & ~TXCOMFINISH;
assign set_quiet = state_burst & (bursts_cnt < bursts_cnt_togo - 1) & clr_burst;
assign clr_burst = state_burst & stopwatch == (burst_len - burst_len_mult);
assign clr_quiet = state_quiet & stopwatch == (quiet_len - burst_len_mult);
// bursts timing
assign quiet_len = issued_wake ? quiet_len_wake : quiet_len_init;
assign stopwatch_clr = set_burst | set_quiet | state_idle;
always @ (posedge clk)
stopwatch <= reset | stopwatch_clr ? 0 : stopwatch + burst_len_mult;
// total bursts count
assign bursts_cnt_clr = state_idle;
assign bursts_cnt_inc = state_burst & clr_burst;
always @ (posedge clk)
bursts_cnt <= reset | bursts_cnt_clr ? 0 : bursts_cnt_inc ? bursts_cnt + 1 : bursts_cnt;
// data to serializer
// only datawidth = 20 is supported for now
wire [width - 1:0] outdata_pos;
wire [width - 1:0] outdata_neg;
// outdata = {Align2 + Align1}, disparity always flips
assign outdata_pos = stopwatch[0] == 1'b0 ? {10'b0101010101, 10'b1100000101}
: {10'b1101100011, 10'b0101010101};
assign outdata_neg = stopwatch[0] == 1'b0 ? {10'b0101010101, 10'b0011111010}
: {10'b0010011100, 10'b0101010101};
assign outdata = disparity ? outdata_pos : outdata_neg;
assign outval = state_burst;
assign TXCOMFINISH = bursts_cnt_clr & bursts_cnt == bursts_cnt_togo;
endmodule
/*
* According to the doc, p110
* If TX_INT_DATAWIDTH, the inner width = 32 bits, otherwise 16.
*/
module gtxe2_chnl_tx_dataiface #(
parameter internal_data_width = 16,
parameter interface_data_width = 32,
parameter internal_isk_width = 2,
parameter interface_isk_width = 4
)
(
input wire usrclk,
input wire usrclk2,
input wire reset,
output wire [internal_data_width - 1:0] outdata,
output wire [internal_isk_width - 1:0] outisk,
input wire [interface_data_width - 1:0] indata,
input wire [interface_isk_width - 1:0] inisk
);
localparam div = interface_data_width / internal_data_width;
wire [interface_data_width + interface_isk_width - 1:0] data_resynced;
reg [31:0] wordcounter;
wire almost_empty_rd;
wire empty_rd;
wire full_wr;
wire val_rd;
always @ (posedge usrclk)
wordcounter <= reset | wordcounter == (div - 1) ? 32'h0 : wordcounter + 1'b1;
assign outdata = data_resynced[(wordcounter + 1) * internal_data_width - 1 -: internal_data_width];
assign outisk = data_resynced[(wordcounter + 1) * internal_isk_width + internal_data_width * div - 1 -: internal_isk_width];
assign val_rd = ~almost_empty_rd & ~empty_rd & wordcounter == (div - 1);
resync_fifo_nonsynt #(
.width (interface_data_width + interface_isk_width),
.log_depth (3)
)
fifo(
.rst_rd (reset),
.rst_wr (reset),
.clk_wr (usrclk2),
.val_wr (1'b1),
.data_wr ({inisk, indata}),
.clk_rd (usrclk),
.val_rd (val_rd),
.data_rd ({data_resynced}),
.empty_rd (empty_rd),
.full_wr (full_wr),
.almost_empty_rd (almost_empty_rd)
);
endmodule
module gtxe2_chnl_tx(
input wire reset,
output wire TXP,
output wire TXN,
input wire [63:0] TXDATA,
input wire TXUSRCLK,
input wire TXUSRCLK2,
// 8/10 encoder
input wire [7:0] TX8B10BBYPASS,
input wire TX8B10BEN,
input wire [7:0] TXCHARDISPMODE,
input wire [7:0] TXCHARDISPVAL,
input wire [7:0] TXCHARISK,
// TX Buffer
output wire [1:0] TXBUFSTATUS,
// TX Polarity
input wire TXPOLARITY,
// TX Fabric Clock Control
input wire [2:0] TXRATE,
output wire TXRATEDONE,
// TX OOB
input wire TXCOMINIT,
input wire TXCOMWAKE,
output wire TXCOMFINISH,
// TX Driver Control
input wire TXELECIDLE,
// internal
input wire serial_clk
);
parameter TX_DATA_WIDTH = 20;
parameter TX_INT_DATAWIDTH = 0;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
function integer calc_idw;
input TX8B10BEN;
// input TX_INT_DATAWIDTH;
// input TX_DATA_WIDTH;
begin
// if (TX8B10BEN == 1)
calc_idw = TX_INT_DATAWIDTH == 1 ? 40 : 20;
/* else
begin
if (TX_INT_DATAWIDTH == 1)
calc_idw = TX_DATA_WIDTH == 32 ? 32
: TX_DATA_WIDTH == 40 ? 40
: TX_DATA_WIDTH == 64 ? 32 : 40;
else
calc_idw = TX_DATA_WIDTH == 16 ? 16
: TX_DATA_WIDTH == 20 ? 20
: TX_DATA_WIDTH == 32 ? 16 : 20;
end*/
end
endfunction
function integer calc_ifdw;
input TX8B10BEN;
begin
// if (TX8B10BEN == 1)
calc_ifdw = TX_DATA_WIDTH == 16 ? 20 :
TX_DATA_WIDTH == 32 ? 40 :
TX_DATA_WIDTH == 64 ? 80 : TX_DATA_WIDTH;
/* else
begin
if (TX_INT_DATAWIDTH == 1)
calc_ifdw = TX_DATA_WIDTH == 32 ? 32
: TX_DATA_WIDTH == 40 ? 40
: TX_DATA_WIDTH == 64 ? 64 : 80;
else
calc_ifdw = TX_DATA_WIDTH == 16 ? 16
: TX_DATA_WIDTH == 20 ? 20
: TX_DATA_WIDTH == 32 ? 16 : 20;
end*/
end
endfunction
// can be 20 or 40, if it shall be 16 or 32, extra bits wont be used
localparam internal_data_width = calc_idw(1);//PTX8B10BEN);//, TX_INT_DATAWIDTH, TX_DATA_WIDTH);
localparam interface_data_width = calc_ifdw(1);
localparam internal_isk_width = internal_data_width / 10;
localparam interface_isk_width = interface_data_width / 10;
// used in case of TX8B10BEN = 0
localparam data_width_odd = TX_DATA_WIDTH == 16 | TX_DATA_WIDTH == 32 | TX_DATA_WIDTH == 64;
// TX PMA
// serializer
wire serial_data;
wire line_idle;
wire line_idle_pcs; // line_idle in pcs clock domain
wire [internal_data_width - 1:0] ser_input;
wire oob_active;
reg oob_in_process;
always @ (posedge TXUSRCLK)
oob_in_process <= reset | TXCOMFINISH ? 1'b0 : TXCOMINIT | TXCOMWAKE ? 1'b1 : oob_in_process;
assign TXP = ~line_idle ? serial_data : 1'bz;
assign TXN = ~line_idle ? ~serial_data : 1'bz;
assign line_idle_pcs = (TXELECIDLE | oob_in_process) & ~oob_active | reset;
// Serializer
wire [internal_data_width - 1:0] parallel_data;
wire [internal_data_width - 1:0] inv_parallel_data;
gtxe2_chnl_tx_ser #(
.width (internal_data_width)
)
ser(
.reset (reset),
.trim (data_width_odd & ~TX8B10BEN),
.inclk (TXUSRCLK),
.outclk (serial_clk),
.indata (inv_parallel_data),
.idle_in (line_idle_pcs),
.outdata (serial_data),
.idle_out (line_idle)
);
// TX PCS
// fit data width
localparam iface_databus_width = interface_data_width * 8 / 10;
localparam intern_databus_width = internal_data_width * 8 / 10;
wire [intern_databus_width - 1:0] internal_data;
wire [internal_isk_width - 1:0] internal_isk;
wire [internal_isk_width - 1:0] internal_dispval;
wire [internal_isk_width - 1:0] internal_dispmode;
wire [internal_data_width - 1:0] dataiface_data_out;
wire [interface_data_width - 1:0] dataiface_data_in;
//assign dataiface_data_in = {TXCHARDISPMODE[interface_isk_width - 1:0], TXCHARDISPVAL[interface_isk_width - 1:0], TXDATA[iface_databus_width - 1:0]};
genvar ii;
localparam outdiv = interface_data_width / internal_data_width;
generate
for (ii = 1; ii < (outdiv + 1); ii = ii + 1)
begin: asdadfdsf
assign dataiface_data_in[ii*internal_data_width - 1-:internal_data_width] = {TXCHARDISPMODE[ii*interface_isk_width - 1-:interface_isk_width],
TXCHARDISPVAL[ii*interface_isk_width - 1-:interface_isk_width],
TXDATA[ii*intern_databus_width - 1-:intern_databus_width]
};
end
endgenerate
assign internal_dispmode = dataiface_data_out[intern_databus_width + internal_isk_width + internal_isk_width - 1-:internal_isk_width];
assign internal_dispval = dataiface_data_out[intern_databus_width + internal_isk_width - 1-:internal_isk_width];
assign internal_data = dataiface_data_out[intern_databus_width - 1:0];
gtxe2_chnl_tx_dataiface #(
.internal_data_width (internal_data_width),
.interface_data_width (interface_data_width),
.internal_isk_width (internal_isk_width),
.interface_isk_width (interface_isk_width)
)
dataiface
(
.usrclk (TXUSRCLK),
.usrclk2 (TXUSRCLK2),
.reset (reset),
.outdata (dataiface_data_out),
.outisk (internal_isk),
.indata (dataiface_data_in),
.inisk (TXCHARISK[interface_isk_width - 1:0])
);
wire [internal_data_width - 1:0] polarized_data;
// invert data (get words as [abdceifghj] after 8/10, each word shall be transmitter in a reverse bit order)
genvar jj;
generate
for (ii = 0; ii < internal_data_width; ii = ii + 10)
begin: select_each_word
for (jj = 0; jj < 10; jj = jj + 1)
begin: reverse_bits
assign inv_parallel_data[ii + jj] = TX8B10BEN ? polarized_data[ii + 9 - jj] : polarized_data[ii + jj];
end
end
endgenerate
// Polarity:
assign ser_input = polarized_data;
generate
for (ii = 0; ii < internal_data_width; ii = ii + 1)
begin: invert_dataword
assign polarized_data[ii] = TXPOLARITY == 1'b1 ? ~parallel_data[ii] : parallel_data[ii];
end
endgenerate
// SATA OOB
reg disparity;
wire [internal_data_width - 1:0] oob_data;
wire oob_val;
assign oob_active = oob_val;
gtxe2_chnl_tx_oob #(
.width (internal_data_width),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_CPLL_CFG (SATA_CPLL_CFG)
)
tx_oob(
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.clk (TXUSRCLK),
.reset (reset),
.disparity (disparity),
.outdata (oob_data),
.outval (oob_val)
);
// Disparity control
wire next_disparity;
always @ (posedge TXUSRCLK)
disparity <= reset | line_idle_pcs? 1'b0 : oob_val ? ~disparity : next_disparity;
// 8/10 endoding
wire [internal_data_width - 1:0] encoded_data;
gtxe2_chnl_tx_8x10enc #(
.iwidth (intern_databus_width),//TX_DATA_WIDTH),
.iskwidth (internal_isk_width),
.owidth (internal_data_width)
// .oddwidth (data_width_odd)
)
encoder_8x10(
.TX8B10BBYPASS (TX8B10BBYPASS[internal_isk_width - 1:0]),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (internal_dispmode),
.TXCHARDISPVAL (internal_dispval),
.TXCHARISK (internal_isk),
.disparity (disparity),
.data_in (internal_data),
.data_out (encoded_data),
.next_disparity (next_disparity)
);
// OOB-OrdinaryData Arbiter
assign parallel_data = oob_val ? oob_data : encoded_data;
endmodule
/**
* For now contains only deserializer, oob, 10x8 decoder, aligner and polarity invertor blocks
**/
// TODO resync all output signals
// simplified resynchronisation fifo, could cause metastability
// because of that shall not be syntesisable
// TODO add shift registers and gray code to fix that
`ifndef RESYNC_FIFO_NOSYNT_V
`define RESYNC_FIFO_NOSYNT_V
module resync_fifo_nonsynt #(
parameter [31:0] width = 20,
//parameter [31:0] depth = 7
parameter [31:0] log_depth = 3
)
(
input wire rst_rd,
input wire rst_wr,
input wire clk_wr,
input wire val_wr,
input wire [width - 1:0] data_wr,
input wire clk_rd,
input wire val_rd,
output wire [width - 1:0] data_rd,
output wire empty_rd,
output wire almost_empty_rd,
output wire full_wr
);
/*
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
localparam log_depth = clogb2(depth);
*/
localparam depth = 1 << log_depth;
reg [width -1:0] fifo [depth - 1:0];
// wr_clk domain
reg [log_depth - 1:0] cnt_wr;
// rd_clk domain
reg [log_depth - 1:0] cnt_rd;
assign data_rd = fifo[cnt_rd];
assign empty_rd = cnt_wr == cnt_rd;
assign full_wr = (cnt_wr + 1'b1) == cnt_rd;
assign almost_empty_rd = (cnt_rd + 1'b1) == cnt_wr;
always @ (posedge clk_wr)
fifo[cnt_wr] <= val_wr ? data_wr : fifo[cnt_wr];
always @ (posedge clk_wr)
cnt_wr <= rst_wr ? 0 : val_wr ? cnt_wr + 1'b1 : cnt_wr;
always @ (posedge clk_rd)
cnt_rd <= rst_rd ? 0 : val_rd ? cnt_rd + 1'b1 : cnt_rd;
endmodule
`endif
module gtxe2_chnl_rx_des #(
parameter [31:0] width = 20
)
(
input wire reset,
input wire trim,
input wire inclk,
input wire outclk,
input wire indata,
output wire [width - 1:0] outdata
);
localparam trimmed_width = width * 4 / 5;
reg [31:0] bitcounter;
reg [width - 1:0] inbuffer;
wire empty_rd;
wire full_wr;
wire val_wr;
wire val_rd;
wire bitcounter_limit;
wire almost_empty_rd;
reg need_reset = 1;
assign bitcounter_limit = trim ? bitcounter == (trimmed_width - 1) : bitcounter == (width - 1);
always @ (posedge inclk)
bitcounter <= reset | bitcounter_limit ? 32'h0 : bitcounter + 1'b1;
genvar ii;
generate
for (ii = 0; ii < width; ii = ii + 1)
begin: splicing
always @ (posedge inclk)
if ((ii >= trimmed_width) & trim)
inbuffer[ii] <= 1'bx;
else
inbuffer[ii] <= reset ? 1'b0 : (bitcounter == ii) ? indata : inbuffer[ii];
end
endgenerate
assign val_rd = ~empty_rd & ~almost_empty_rd;
assign val_wr = ~full_wr & bitcounter == (width - 1);
always @ (posedge inclk) begin
if (reset) need_reset <= 0;
else if (full_wr && !need_reset) begin
$display("1:FIFO in %m is full, that is not an appropriate behaviour - needs reset @%time", $time);
bitcounter <= 'bx;
need_reset <= 1'b1;
// $finish;
end
end
resync_fifo_nonsynt #(
.width (width),
.log_depth (3)
)
fifo(
.rst_rd (reset),
.rst_wr (reset),
.clk_wr (inclk),
.val_wr (val_wr),
.data_wr ({indata, inbuffer[width - 2:0]}),
.clk_rd (outclk),
.val_rd (val_rd),
.data_rd (outdata),
.empty_rd (empty_rd),
.full_wr (full_wr),
.almost_empty_rd (almost_empty_rd)
);
endmodule
// doesnt support global parameters for now. instead uses localparams
// in case global parameters are needed, have to translate them in terms of localparams
module gtxe2_chnl_rx_oob #(
parameter width = 20,
// parameters are not used for now
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter SATA_MIN_INIT = 12,
parameter SATA_MIN_WAKE = 4,
parameter SATA_MAX_BURST = 8,
parameter SATA_MIN_BURST = 4,
parameter SATA_MAX_INIT = 21,
parameter SATA_MAX_WAKE = 7
)
(
input wire reset,
input wire clk,
input wire usrclk2,
input wire RXN,
input wire RXP,
input wire [1:0] RXELECIDLEMODE,
output wire RXELECIDLE,
output wire RXCOMINITDET,
output wire RXCOMWAKEDET
);
localparam burst_min_len = 150;
localparam burst_max_len = 340;
localparam wake_idle_min_len = 150;
localparam wake_idle_max_len = 340;
localparam init_idle_min_len = 450;
localparam init_idle_max_len = 990;
localparam wake_bursts_cnt = SATA_BURST_VAL;
localparam init_bursts_cnt = SATA_BURST_VAL;
wire idle;
assign idle = (RXN == RXP) | (RXP === 1'bx) | (RXP === 1'bz);
wire state_notrans;
wire state_error; //nostrans substate
wire state_done; //notrans substate
reg state_idle;
reg state_burst;
wire set_notrans;
wire set_done;
wire set_error;
wire set_idle;
wire set_burst;
wire clr_idle;
wire clr_burst;
assign state_notrans = ~state_idle & ~state_burst;
always @ (posedge clk)
begin
state_idle <= (state_idle | set_idle) & ~reset & ~clr_idle;
state_burst <= (state_burst | set_burst) & ~reset & ~clr_burst;
end
assign set_notrans = set_done | set_error;
assign set_idle = state_burst & clr_burst & idle;
assign set_burst = state_notrans & ~idle | state_idle & clr_idle & ~idle;
assign clr_idle = ~idle | set_notrans;
assign clr_burst = idle | set_notrans;
reg [31:0] burst_len;
reg [31:0] idle_len;
reg [31:0] bursts_cnt;
always @ (posedge clk)
begin
burst_len <= reset | ~state_burst ? 0 : burst_len + 1;
idle_len <= reset | ~state_idle ? 0 : idle_len + 1;
bursts_cnt <= reset | state_notrans ? 0 : state_burst & clr_burst ? bursts_cnt + 1 : bursts_cnt;
end
wire burst_len_violation;
wire idle_len_violation;
wire wake_idle_violation;
wire init_idle_violation;
//reg burst_len_ok;
reg wake_idle_ok;
reg init_idle_ok;
reg burst_len_curr_ok;
reg init_idle_curr_ok;
reg wake_idle_curr_ok;
wire done_wake;
wire done_init;
always @ (posedge clk)
begin
wake_idle_ok <= reset | state_notrans ? 1'b1 : wake_idle_violation ? 1'b0 : wake_idle_ok;
init_idle_ok <= reset | state_notrans ? 1'b1 : init_idle_violation ? 1'b0 : init_idle_ok;
// burst_len_ok <= reset | state_notrans ? 1'b1 : burst_len_violation ? 1'b0 : burst_len_ok;
wake_idle_curr_ok <= reset | ~state_idle ? 1'b0 : idle_len == wake_idle_min_len ? 1'b1 : wake_idle_curr_ok;
init_idle_curr_ok <= reset | ~state_idle ? 1'b0 : idle_len == init_idle_min_len ? 1'b1 : init_idle_curr_ok;
burst_len_curr_ok <= reset | ~state_burst? 1'b0 : burst_len == burst_min_len ? 1'b1 : burst_len_curr_ok;
end
assign burst_len_violation = state_burst & set_idle & ~burst_len_curr_ok | state_burst & burst_len == burst_max_len;
assign wake_idle_violation = state_idle & set_burst & ~wake_idle_curr_ok | state_idle & idle_len == wake_idle_max_len;
assign init_idle_violation = state_idle & set_burst & ~init_idle_curr_ok | state_idle & idle_len == init_idle_max_len;
assign idle_len_violation = (~wake_idle_ok | wake_idle_violation) & init_idle_violation | wake_idle_violation & (~init_idle_ok | init_idle_violation);
assign done_wake = state_burst & ~idle & bursts_cnt == (wake_bursts_cnt - 1) & wake_idle_ok;
assign done_init = state_burst & ~idle & bursts_cnt == (init_bursts_cnt - 1)& init_idle_ok;
assign set_error = idle_len_violation | burst_len_violation;
assign set_done = ~set_error & (done_wake | done_init);
// just to rxcominit(wake)det be synchronous to usrclk2
reg rxcominitdet_clk = 1'b0;
reg rxcominitdet_usrclk2 = 1'b0;
reg rxcomwakedet_clk = 1'b0;
reg rxcomwakedet_usrclk2 = 1'b0;
always @ (posedge clk)
begin
rxcominitdet_clk <= reset ? 1'b0 : done_init | rxcominitdet_clk & ~rxcominitdet_usrclk2;
rxcomwakedet_clk <= reset ? 1'b0 : done_wake | rxcomwakedet_clk & ~rxcomwakedet_usrclk2;
end
always @ (posedge usrclk2)
begin
rxcominitdet_usrclk2 <= reset ? 1'b0 : rxcominitdet_clk & ~rxcominitdet_usrclk2;
rxcomwakedet_usrclk2 <= reset ? 1'b0 : rxcomwakedet_clk & ~rxcomwakedet_usrclk2;
end
assign RXCOMINITDET = rxcominitdet_usrclk2;
assign RXCOMWAKEDET = rxcomwakedet_usrclk2;
assign RXELECIDLE = RXP === 1'bz ? 1'b1 : RXP === 1'bx ? 1'b1 : RXP == RXN;
endmodule
// always enabled, wasnt tested with width parameters, disctinct from 20
module gtxe2_chnl_rx_10x8dec #(
parameter iwidth = 20,
parameter iskwidth = 2,
parameter owidth = 20,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE"
)
(
input wire clk,
input wire rst,
input wire [iwidth - 1:0] indata,
input wire RX8B10BEN,
input wire data_width_odd,
output wire [iskwidth - 1:0] rxchariscomma,
output wire [iskwidth - 1:0] rxcharisk,
output wire [iskwidth - 1:0] rxdisperr,
output wire [iskwidth - 1:0] rxnotintable,
output wire [owidth - 1:0] outdata
);
wire [iskwidth - 1:0] rxcharisk_dec;
wire [iskwidth - 1:0] rxdisperr_dec;
wire [owidth - 1:0] outdata_dec;
localparam word_count = iwidth / 10;
localparam add_2out_bits = owidth == 20 | owidth == 40 | owidth == 80 ? "TRUE" : "FALSE";
wire [iwidth - 2 * word_count - 1:0] pure_data;
wire [iwidth - 1:0] data;
wire [word_count - 1:0] disp; //consecutive disparity calculations;
wire [word_count - 1:0] disp_word; // 0 - negative, 1 - positive
wire [word_count - 1:0] no_disp_word; // ignore disp_word, '1's and '0's have equal count
wire [word_count - 1:0] disp_err;
reg disp_init; // disparity after last clock's portion of data
always @ (posedge clk)
disp_init <= rst ? 1'b0 : disp[word_count - 1];
genvar ii;
generate
for (ii = 0; ii < word_count; ii = ii + 1)
begin: asdf
//data = {1'(is in table) + 3'(decoded 4/3) + 1'(is in table) + 5'(decoded 6/5)}
//6/5 decoding
assign data[ii*10+5:ii*10] = rxcharisk_dec[ii] ? (
indata[ii*10 + 9:ii*10] == 10'b0010111100 | indata[ii*10 + 9:ii*10] == 10'b1101000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b1001111100 | indata[ii*10 + 9:ii*10] == 10'b0110000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b1010111100 | indata[ii*10 + 9:ii*10] == 10'b0101000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b1100111100 | indata[ii*10 + 9:ii*10] == 10'b0011000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b0100111100 | indata[ii*10 + 9:ii*10] == 10'b1011000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b0101111100 | indata[ii*10 + 9:ii*10] == 10'b1010000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b0110111100 | indata[ii*10 + 9:ii*10] == 10'b1001000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b0001111100 | indata[ii*10 + 9:ii*10] == 10'b1110000011 ? 6'b011100 :
indata[ii*10 + 9:ii*10] == 10'b0001010111 | indata[ii*10 + 9:ii*10] == 10'b1110101000 ? 6'b010111 :
indata[ii*10 + 9:ii*10] == 10'b0001011011 | indata[ii*10 + 9:ii*10] == 10'b1110100100 ? 6'b011011 :
indata[ii*10 + 9:ii*10] == 10'b0001011101 | indata[ii*10 + 9:ii*10] == 10'b1110100010 ? 6'b011101 :
indata[ii*10 + 9:ii*10] == 10'b0001011110 | indata[ii*10 + 9:ii*10] == 10'b1110100001 ? 6'b011110 :
6'b100000)
:
(indata[ii*10 + 5:ii*10] == 6'b111001 | indata[ii*10 + 5:ii*10] == 6'b000110 ? 6'b000000 :// Data VVV
indata[ii*10 + 5:ii*10] == 6'b101110 | indata[ii*10 + 5:ii*10] == 6'b010001 ? 6'b000001 :
indata[ii*10 + 5:ii*10] == 6'b101101 | indata[ii*10 + 5:ii*10] == 6'b010010 ? 6'b000010 :
indata[ii*10 + 5:ii*10] == 6'b100011 | indata[ii*10 + 5:ii*10] == 6'b100011 ? 6'b000011 :
indata[ii*10 + 5:ii*10] == 6'b101011 | indata[ii*10 + 5:ii*10] == 6'b010100 ? 6'b000100 :
indata[ii*10 + 5:ii*10] == 6'b100101 | indata[ii*10 + 5:ii*10] == 6'b100101 ? 6'b000101 :
indata[ii*10 + 5:ii*10] == 6'b100110 | indata[ii*10 + 5:ii*10] == 6'b100110 ? 6'b000110 :
indata[ii*10 + 5:ii*10] == 6'b000111 | indata[ii*10 + 5:ii*10] == 6'b111000 ? 6'b000111 :
indata[ii*10 + 5:ii*10] == 6'b100111 | indata[ii*10 + 5:ii*10] == 6'b011000 ? 6'b001000 :
indata[ii*10 + 5:ii*10] == 6'b101001 | indata[ii*10 + 5:ii*10] == 6'b101001 ? 6'b001001 :
indata[ii*10 + 5:ii*10] == 6'b101010 | indata[ii*10 + 5:ii*10] == 6'b101010 ? 6'b001010 :
indata[ii*10 + 5:ii*10] == 6'b001011 | indata[ii*10 + 5:ii*10] == 6'b001011 ? 6'b001011 :
indata[ii*10 + 5:ii*10] == 6'b101100 | indata[ii*10 + 5:ii*10] == 6'b101100 ? 6'b001100 :
indata[ii*10 + 5:ii*10] == 6'b001101 | indata[ii*10 + 5:ii*10] == 6'b001101 ? 6'b001101 :
indata[ii*10 + 5:ii*10] == 6'b001110 | indata[ii*10 + 5:ii*10] == 6'b001110 ? 6'b001110 :
indata[ii*10 + 5:ii*10] == 6'b111010 | indata[ii*10 + 5:ii*10] == 6'b000101 ? 6'b001111 :
indata[ii*10 + 5:ii*10] == 6'b110110 | indata[ii*10 + 5:ii*10] == 6'b001001 ? 6'b010000 :
indata[ii*10 + 5:ii*10] == 6'b110001 | indata[ii*10 + 5:ii*10] == 6'b110001 ? 6'b010001 :
indata[ii*10 + 5:ii*10] == 6'b110010 | indata[ii*10 + 5:ii*10] == 6'b110010 ? 6'b010010 :
indata[ii*10 + 5:ii*10] == 6'b010011 | indata[ii*10 + 5:ii*10] == 6'b010011 ? 6'b010011 :
indata[ii*10 + 5:ii*10] == 6'b110100 | indata[ii*10 + 5:ii*10] == 6'b110100 ? 6'b010100 :
indata[ii*10 + 5:ii*10] == 6'b010101 | indata[ii*10 + 5:ii*10] == 6'b010101 ? 6'b010101 :
indata[ii*10 + 5:ii*10] == 6'b010110 | indata[ii*10 + 5:ii*10] == 6'b010110 ? 6'b010110 :
indata[ii*10 + 5:ii*10] == 6'b010111 | indata[ii*10 + 5:ii*10] == 6'b101000 ? 6'b010111 :
indata[ii*10 + 5:ii*10] == 6'b110011 | indata[ii*10 + 5:ii*10] == 6'b001100 ? 6'b011000 :
indata[ii*10 + 5:ii*10] == 6'b011001 | indata[ii*10 + 5:ii*10] == 6'b011001 ? 6'b011001 :
indata[ii*10 + 5:ii*10] == 6'b011010 | indata[ii*10 + 5:ii*10] == 6'b011010 ? 6'b011010 :
indata[ii*10 + 5:ii*10] == 6'b011011 | indata[ii*10 + 5:ii*10] == 6'b100100 ? 6'b011011 :
indata[ii*10 + 5:ii*10] == 6'b011100 | indata[ii*10 + 5:ii*10] == 6'b011100 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b011101 | indata[ii*10 + 5:ii*10] == 6'b100010 ? 6'b011101 :
indata[ii*10 + 5:ii*10] == 6'b011110 | indata[ii*10 + 5:ii*10] == 6'b100001 ? 6'b011110 :
indata[ii*10 + 5:ii*10] == 6'b110101 | indata[ii*10 + 5:ii*10] == 6'b001010 ? 6'b011111 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :// Controls VVV
/* indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b111100 | indata[ii*10 + 5:ii*10] == 6'b000011 ? 6'b011100 :
indata[ii*10 + 5:ii*10] == 6'b010111 | indata[ii*10 + 5:ii*10] == 6'b101000 ? 6'b010111 :
indata[ii*10 + 5:ii*10] == 6'b011011 | indata[ii*10 + 5:ii*10] == 6'b100100 ? 6'b011011 :
indata[ii*10 + 5:ii*10] == 6'b011101 | indata[ii*10 + 5:ii*10] == 6'b100010 ? 6'b011101 :
indata[ii*10 + 5:ii*10] == 6'b011110 | indata[ii*10 + 5:ii*10] == 6'b100001 ? 6'b011110 :*/
6'b100000); // not in a table
//4/3 decoding
assign data[ii*10+ 9:ii*10+ 6] = rxcharisk_dec[ii] ? (
indata[ii*10 + 9:ii*10] == 10'b0010111100 | indata[ii*10 + 9:ii*10] == 10'b1101000011 ? 4'b0000 :
indata[ii*10 + 9:ii*10] == 10'b1001111100 | indata[ii*10 + 9:ii*10] == 10'b0110000011 ? 4'b0001 :
indata[ii*10 + 9:ii*10] == 10'b1010111100 | indata[ii*10 + 9:ii*10] == 10'b0101000011 ? 4'b0010 :
indata[ii*10 + 9:ii*10] == 10'b1100111100 | indata[ii*10 + 9:ii*10] == 10'b0011000011 ? 4'b0011 :
indata[ii*10 + 9:ii*10] == 10'b0100111100 | indata[ii*10 + 9:ii*10] == 10'b1011000011 ? 4'b0100 :
indata[ii*10 + 9:ii*10] == 10'b0101111100 | indata[ii*10 + 9:ii*10] == 10'b1010000011 ? 4'b0101 :
indata[ii*10 + 9:ii*10] == 10'b0110111100 | indata[ii*10 + 9:ii*10] == 10'b1001000011 ? 4'b0110 :
indata[ii*10 + 9:ii*10] == 10'b0001111100 | indata[ii*10 + 9:ii*10] == 10'b1110000011 ? 4'b0111 :
indata[ii*10 + 9:ii*10] == 10'b0001010111 | indata[ii*10 + 9:ii*10] == 10'b1110101000 ? 4'b0111 :
indata[ii*10 + 9:ii*10] == 10'b0001011011 | indata[ii*10 + 9:ii*10] == 10'b1110100100 ? 4'b0111 :
indata[ii*10 + 9:ii*10] == 10'b0001011101 | indata[ii*10 + 9:ii*10] == 10'b1110100010 ? 4'b0111 :
indata[ii*10 + 9:ii*10] == 10'b0001011110 | indata[ii*10 + 9:ii*10] == 10'b1110100001 ? 4'b0111 :
4'b1000)
:
(indata[ii*10 + 9:ii*10 + 6] == 4'b1101 | indata[ii*10 + 9:ii*10 + 6] == 4'b0010 ? 4'b0000 : // Data VVV
indata[ii*10 + 9:ii*10 + 6] == 4'b1001 | indata[ii*10 + 9:ii*10 + 6] == 4'b1001 ? 4'b0001 :
indata[ii*10 + 9:ii*10 + 6] == 4'b1010 | indata[ii*10 + 9:ii*10 + 6] == 4'b1010 ? 4'b0010 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0011 | indata[ii*10 + 9:ii*10 + 6] == 4'b1100 ? 4'b0011 :
indata[ii*10 + 9:ii*10 + 6] == 4'b1011 | indata[ii*10 + 9:ii*10 + 6] == 4'b0100 ? 4'b0100 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0101 | indata[ii*10 + 9:ii*10 + 6] == 4'b0101 ? 4'b0101 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0110 | indata[ii*10 + 9:ii*10 + 6] == 4'b0110 ? 4'b0110 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0111 | indata[ii*10 + 9:ii*10 + 6] == 4'b1110 ? 4'b0111 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0001 | indata[ii*10 + 9:ii*10 + 6] == 4'b1000 ? 4'b0111 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0010 | indata[ii*10 + 9:ii*10 + 6] == 4'b1101 ? 4'b0000 : // Control VVV
/* indata[ii*10 + 9:ii*10 + 6] == 4'b1001 | indata[ii*10 + 9:ii*10 + 6] == 4'b0110 ? 4'b0001 :
indata[ii*10 + 9:ii*10 + 6] == 4'b1010 | indata[ii*10 + 9:ii*10 + 6] == 4'b0101 ? 4'b0010 :
indata[ii*10 + 9:ii*10 + 6] == 4'b1100 | indata[ii*10 + 9:ii*10 + 6] == 4'b0011 ? 4'b0011 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0100 | indata[ii*10 + 9:ii*10 + 6] == 4'b1011 ? 4'b0100 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0101 | indata[ii*10 + 9:ii*10 + 6] == 4'b1010 ? 4'b0101 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0110 | indata[ii*10 + 9:ii*10 + 6] == 4'b1001 ? 4'b0110 :
indata[ii*10 + 9:ii*10 + 6] == 4'b0001 | indata[ii*10 + 9:ii*10 + 6] == 4'b1110 ? 4'b0111 :*/
4'b1000); // not in a table
assign disp_word[ii] = (4'd0 + indata[ii*10] + indata[ii*10 + 1] + indata[ii*10 + 2] + indata[ii*10 + 3] + indata[ii*10 + 4]
+ indata[ii*10 + 5] + indata[ii*10 + 6] + indata[ii*10 + 7] + indata[ii*10 + 8] + indata[ii*10 + 9]) > 5;
assign no_disp_word[ii]= (4'd0 + indata[ii*10] + indata[ii*10 + 1] + indata[ii*10 + 2] + indata[ii*10 + 3] + indata[ii*10 + 4]
+ indata[ii*10 + 5] + indata[ii*10 + 6] + indata[ii*10 + 7] + indata[ii*10 + 8] + indata[ii*10 + 9]) == 5;
assign pure_data[ii*8 + 7:ii*8] = {data[ii*10 + 8:ii*10 + 6], data[ii*10 + 4:ii*10]};
assign outdata_dec[ii*8 + 7:ii*8] = pure_data[ii*8 + 7:ii*8];
assign outdata[ii*8 + 7:ii*8] = RX8B10BEN ? outdata_dec[ii*8 + 7:ii*8] : ~data_width_odd ? indata[ii*10 + 7:ii*10] : indata[ii*8 + 7:ii*8];
assign rxcharisk[ii] = RX8B10BEN ? rxcharisk_dec[ii] : ~data_width_odd ? indata[ii*10 + 8] : 1'bx;
assign rxdisperr[ii] = RX8B10BEN ? rxdisperr_dec[ii] : ~data_width_odd ? indata[ii*10 + 9] : 1'bx;
/* if (RX8B10BEN) begin
end
else
if (data_width_odd) begin
assign outdata[ii*8 + 7:ii*8] = indata[ii*8 + 7:ii*8];
assign rxcharisk[ii] = 1'bx;
assign rxdisperr[ii] = 1'bx;
end
else begin
assign outdata[ii*8 + 7:ii*8] = indata[ii*10 + 7:ii*10];
assign rxcharisk[ii] = indata[ii*10 + 8];
assign rxdisperr[ii] = indata[ii*10 + 9];
end*/
end
endgenerate
assign disp_err = ~no_disp_word & (~disp_word ^ {disp[word_count - 2:0], disp_init});
assign disp = ~no_disp_word & disp_word | no_disp_word & {disp[word_count - 2:0], disp_init};
generate
for (ii = 0; ii < word_count; ii = ii + 1)
begin:dfsga
assign rxnotintable[ii] = ii >= word_count ? 1'b0 : data[ii*10 + 9] | data[ii*10 + 5];
assign rxdisperr_dec[ii] = ii >= word_count ? 1'b0 : disp_err[ii];
assign rxcharisk_dec[ii] = ii >= word_count ? 1'b0 :
indata[ii*10 + 9:ii*10] == 10'b0010111100 | indata[ii*10 + 9:ii*10] == 10'b1101000011 |
indata[ii*10 + 9:ii*10] == 10'b1001111100 | indata[ii*10 + 9:ii*10] == 10'b0110000011 |
indata[ii*10 + 9:ii*10] == 10'b1010111100 | indata[ii*10 + 9:ii*10] == 10'b0101000011 |
indata[ii*10 + 9:ii*10] == 10'b1100111100 | indata[ii*10 + 9:ii*10] == 10'b0011000011 |
indata[ii*10 + 9:ii*10] == 10'b0100111100 | indata[ii*10 + 9:ii*10] == 10'b1011000011 |
indata[ii*10 + 9:ii*10] == 10'b0101111100 | indata[ii*10 + 9:ii*10] == 10'b1010000011 |
indata[ii*10 + 9:ii*10] == 10'b0110111100 | indata[ii*10 + 9:ii*10] == 10'b1001000011 |
indata[ii*10 + 9:ii*10] == 10'b0001111100 | indata[ii*10 + 9:ii*10] == 10'b1110000011 |
indata[ii*10 + 9:ii*10] == 10'b0001010111 | indata[ii*10 + 9:ii*10] == 10'b1110101000 |
indata[ii*10 + 9:ii*10] == 10'b0001011011 | indata[ii*10 + 9:ii*10] == 10'b1110100100 |
indata[ii*10 + 9:ii*10] == 10'b0001011101 | indata[ii*10 + 9:ii*10] == 10'b1110100010 |
indata[ii*10 + 9:ii*10] == 10'b0001011110 | indata[ii*10 + 9:ii*10] == 10'b1110100001;
assign rxchariscomma[ii] = ii >= word_count ? 1'b0 :
(indata[ii*10 + 9:ii*10] == 10'b1001111100 |
indata[ii*10 + 9:ii*10] == 10'b0101111100 |
indata[ii*10 + 9:ii*10] == 10'b0001111100) & DEC_PCOMMA_DETECT |
(indata[ii*10 + 9:ii*10] == 10'b0110000011 |
indata[ii*10 + 9:ii*10] == 10'b1010000011 |
indata[ii*10 + 9:ii*10] == 10'b1110000011) & DEC_MCOMMA_DETECT;
end
endgenerate
endmodule
module gtxe2_chnl_rx_align #(
parameter width = 20,
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b1111111111,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter ALIGN_COMMA_WORD = 1
)
(
input wire clk,
input wire rst,
input wire [width - 1:0] indata,
output wire [width - 1:0] outdata,
input wire rxelecidle,
output wire RXBYTEISALIGNED,
output wire RXBYTEREALIGN,
output wire RXCOMMADET,
input wire RXCOMMADETEN,
input wire RXPCOMMAALIGNEN,
input wire RXMCOMMAALIGNEN
);
localparam comma_width = ALIGN_COMMA_DOUBLE == "FALSE" ? 10 : 20;
localparam window_size = width;//comma_width + width;
// prepare a buffer to be scanned on comma matches
reg [width - 1:0] indata_r;
wire [width*2 - 1:0] data;
// looking for matches in all related bit history - in 'data'
assign data = {indata, indata_r};//{indata_r, indata};
always @ (posedge clk)
indata_r <= indata;
// finding matches
wire [comma_width - 1:0] comma_window [window_size - 1:0];
//initial
// for (idx = 0; idx < window_size; idx = idx + 1) $dumpvars(0, comma_width[idx]);
wire [window_size - 1:0] comma_match; // shows all matches
wire [window_size - 1:0] comma_pos; // shows the first match
wire [window_size - 1:0] pcomma_match;
wire [window_size - 1:0] mcomma_match;
genvar ii;
generate
for (ii = 0; ii < window_size; ii = ii + 1)
begin: filter
assign comma_window[ii] = data[comma_width + ii - 1:ii];
assign pcomma_match[ii] = (comma_window[ii] & ALIGN_COMMA_ENABLE) == (ALIGN_PCOMMA_VALUE & ALIGN_COMMA_ENABLE);
assign mcomma_match[ii] = (comma_window[ii] & ALIGN_COMMA_ENABLE) == (ALIGN_MCOMMA_VALUE & ALIGN_COMMA_ENABLE);
assign comma_match[ii] = pcomma_match[ii] & RXPCOMMAALIGNEN | mcomma_match[ii] & RXMCOMMAALIGNEN;
end
endgenerate
// so, comma_match indicates bits, from whose comma/doublecomma (or commas) occurs in the window buffer
// all we need from now is to get one of these bits, [x], and say [x+width-1:x] is an aligned data
// doing it in a hard way
generate
for (ii = 1; ii < window_size; ii = ii + 1)
begin: filter_comma_pos
assign comma_pos[ii] = comma_match[ii] & ~|comma_match[ii - 1:0];
end
endgenerate
assign comma_pos[0] = comma_match[0];
// so, comma_pos's '1' indicates the first comma occurence. there is only one '1' in the vector
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
function integer powerof2;
input [31:0] value;
begin
value = 1 << value;
end
endfunction
localparam pwidth = clogb2(width * 2 -1);
// decoding (finding an index, representing '1' in comma_pos)
wire [pwidth - 1:0] pointer;
reg [pwidth - 1:0] pointer_latched;
wire pointer_set;
wire [window_size - 1:0] pbits [pwidth - 1:0];
genvar jj;
generate
for (ii = 0; ii < pwidth; ii = ii + 1)
begin: for_each_pointers_bit
for (jj = 0; jj < window_size; jj = jj + 1)
begin: calculate_encoder_mask
assign pbits[ii][jj] = jj[ii];
end
assign pointer[ii] = |(pbits[ii] & comma_pos);
end
endgenerate
//here we are: pointer = index of a beginning of the required output data
reg is_aligned;
assign outdata = ~RXCOMMADETEN ? indata : pointer_set ? data[pointer + width - 1 -:width] : data[pointer_latched + width - 1 -:width];
assign pointer_set = |comma_pos;
assign RXCOMMADET = RXCOMMADETEN & pointer_set & (|pcomma_match & ALIGN_PCOMMA_DET == "TRUE" | |mcomma_match & ALIGN_MCOMMA_DET == "TRUE");
assign RXBYTEISALIGNED = RXCOMMADETEN & is_aligned;
assign RXBYTEREALIGN = RXCOMMADETEN & is_aligned & pointer_set;
always @ (posedge clk)
begin
is_aligned <= rst | pointer_set === 1'bx | rxelecidle ? 1'b0 : ~is_aligned & pointer_set | is_aligned;
pointer_latched <= rst ? {pwidth{1'b0}} : pointer_set ? pointer : pointer_latched;
end
endmodule
/*
* According to the doc, p110
* If RX_INT_DATAWIDTH, the inner width = 32 bits, otherwise 16.
*/
module gtxe2_chnl_rx_dataiface #(
parameter internal_data_width = 16,
parameter interface_data_width = 32,
parameter internal_isk_width = 2,
parameter interface_isk_width = 4
)
(
input wire usrclk,
input wire usrclk2,
input wire reset,
output wire [interface_data_width - 1:0] outdata,
output wire [interface_isk_width - 1:0] outisk,
input wire [internal_data_width - 1:0] indata,
input wire [internal_isk_width - 1:0] inisk,
input wire realign
);
localparam div = interface_data_width / internal_data_width;
localparam internal_total_width = internal_data_width + internal_isk_width;
localparam interface_total_width = interface_data_width + interface_isk_width;
reg [interface_data_width - 1:0] inbuffer_data;
reg [interface_isk_width - 1:0] inbuffer_isk;
reg [31:0] wordcounter;
wire empty_rd;
wire full_wr;
wire val_wr;
wire val_rd;
wire almost_empty_rd;
reg need_reset = 1;
always @ (posedge usrclk)
wordcounter <= reset ? 32'h0 : realign & ~(div == 0) ? 32'd1 : wordcounter == (div - 1) ? 32'h0 : wordcounter + 1'b1;
genvar ii;
generate
for (ii = 0; ii < div; ii = ii + 1)
begin: splicing
always @ (posedge usrclk)
inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width] <= reset ? {internal_data_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? indata : inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width];
end
endgenerate
generate
for (ii = 0; ii < div; ii = ii + 1)
begin: splicing2
always @ (posedge usrclk)
inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width] <= reset ? {internal_isk_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? inisk : inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width];
end
endgenerate
assign val_rd = ~empty_rd & ~almost_empty_rd;
assign val_wr = ~full_wr & wordcounter == (div - 1);
always @ (posedge usrclk)
if (reset) need_reset <= 0;
else if (full_wr && !need_reset) begin
$display("2:FIFO in %m is full, that is not an appropriate behaviour, needs reset @%time", $time);
wordcounter = 'bx;
need_reset <= 1;
// $finish;
end
wire [interface_total_width - 1:0] resync;
assign outdata = resync[interface_data_width - 1:0];
assign outisk = resync[interface_data_width + interface_isk_width - 1:interface_data_width];
wire [interface_total_width - 1:0] data_wr;
generate
if (interface_data_width > internal_data_width)
assign data_wr = {inisk, inbuffer_isk[interface_isk_width - internal_isk_width - 1 : 0], indata, inbuffer_data[interface_data_width - internal_data_width - 1 : 0]};
else
assign data_wr = {inisk, indata};
endgenerate
resync_fifo_nonsynt #(
.width (interface_total_width),
.log_depth (3)
)
fifo(
.rst_rd (reset),
.rst_wr (reset),
.clk_wr (usrclk),
.val_wr (val_wr),
.data_wr (data_wr),
.clk_rd (usrclk2),
.val_rd (val_rd),
.data_rd (resync),
.empty_rd (empty_rd),
.full_wr (full_wr),
.almost_empty_rd (almost_empty_rd)
);
endmodule
module gtxe2_chnl_rx(
input wire reset,
input wire RXP,
input wire RXN,
input wire RXUSRCLK,
input wire RXUSRCLK2,
output wire [63:0] RXDATA,
// oob
input wire [1:0] RXELECIDLEMODE,
output wire RXELECIDLE,
output wire RXCOMINITDET,
output wire RXCOMWAKEDET,
// polarity
input wire RXPOLARITY,
// aligner
output wire RXBYTEISALIGNED,
output wire RXBYTEREALIGN,
output wire RXCOMMADET,
input wire RXCOMMADETEN,
input wire RXPCOMMAALIGNEN,
input wire RXMCOMMAALIGNEN,
// 10/8 decoder
input wire RX8B10BEN,
output wire [7:0] RXCHARISCOMMA,
output wire [7:0] RXCHARISK,
output wire [7:0] RXDISPERR,
output wire [7:0] RXNOTINTABLE,
// internal
input wire serial_clk
);
parameter integer RX_DATA_WIDTH = 20;
parameter integer RX_INT_DATAWIDTH = 0;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
function integer calc_idw;
input dummy;
begin
calc_idw = RX_INT_DATAWIDTH == 1 ? 40 : 20;
end
endfunction
function integer calc_ifdw;
input dummy;
begin
calc_ifdw = RX_DATA_WIDTH == 16 ? 20 :
RX_DATA_WIDTH == 32 ? 40 :
RX_DATA_WIDTH == 64 ? 80 : RX_DATA_WIDTH;
end
endfunction
// can be 20 or 40, if it shall be 16 or 32, extra bits wont be used
localparam internal_data_width = calc_idw(1);
localparam interface_data_width = calc_ifdw(1);
localparam internal_isk_width = internal_data_width / 10;
localparam interface_isk_width = interface_data_width / 10;
// used in case of TX8B10BEN = 0
localparam data_width_odd = RX_DATA_WIDTH == 16 | RX_DATA_WIDTH == 32 | RX_DATA_WIDTH == 64;
// OOB
gtxe2_chnl_rx_oob #(
.width (internal_data_width)
)
rx_oob(
.reset (reset),
.clk (serial_clk),
.usrclk2 (RXUSRCLK2),
.RXN (RXN),
.RXP (RXP),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET)
);
// Polarity
// no need to invert data after a deserializer, no need to resync or make a buffer trigger for simulation
wire indata_ser;
assign indata_ser = RXPOLARITY ^ RXP;
// due to non-syntasisable usage, CDR is missing
// deserializer
wire [internal_data_width - 1:0] parallel_data; // in trimmed case highest bites shall be 'x'
gtxe2_chnl_rx_des #(
.width (internal_data_width)
)
des(
.reset (reset),
.trim (data_width_odd & ~RX8B10BEN),
.inclk (serial_clk),
.outclk (RXUSRCLK),
.indata (indata_ser),
.outdata (parallel_data)
);
// aligner
wire [internal_data_width - 1:0] aligned_data;
gtxe2_chnl_rx_align #(
.width (internal_data_width),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE)
)
aligner(
.clk (RXUSRCLK),
.rst (reset),
.indata (parallel_data),
.outdata (aligned_data),
.rxelecidle (RXELECIDLE),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN)
);
localparam iface_databus_width = interface_data_width * 8 / 10;
localparam intern_databus_width = internal_data_width * 8 / 10;
wire [intern_databus_width - 1:0] internal_data;
wire [internal_isk_width - 1:0] internal_isk;
wire [internal_isk_width - 1:0] internal_chariscomma;
wire [internal_isk_width - 1:0] internal_notintable;
wire [internal_isk_width - 1:0] internal_disperr;
// 10x8 decoder
gtxe2_chnl_rx_10x8dec #(
.iwidth (internal_data_width),
.iskwidth (internal_isk_width),
.owidth (intern_databus_width),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT)
)
decoder_10x8(
.clk (RXUSRCLK),
.rst (reset),
.indata (aligned_data),
.RX8B10BEN (RX8B10BEN),
.data_width_odd (data_width_odd),
.rxchariscomma (internal_chariscomma),
.rxcharisk (internal_isk),
.rxdisperr (internal_disperr),
.rxnotintable (internal_notintable),
.outdata (internal_data)
);
// fit data width
localparam outdiv = interface_data_width / internal_data_width;
// if something is written into dataiface_data_in _except_ internal_data and internal_isk => count all extra bits in this parameter
localparam internal_data_extra = 4;
localparam interface_data_extra = outdiv * internal_data_extra;
wire [interface_data_width - 1 + interface_data_extra:0] dataiface_data_out;
wire [internal_data_width - 1 + internal_data_extra:0] dataiface_data_in;
assign dataiface_data_in = {internal_notintable, internal_chariscomma, internal_disperr, internal_isk, internal_data};
genvar ii;
generate
for (ii = 1; ii < (outdiv + 1); ii = ii + 1)
begin: asdadfdsf
assign RXDATA[ii*intern_databus_width - 1 -: intern_databus_width] = dataiface_data_out[(ii-1)*(internal_data_width + internal_data_extra) + intern_databus_width - 1 -: intern_databus_width];
assign RXCHARISK[ii*internal_isk_width - 1 -: internal_isk_width] = dataiface_data_out[(ii-1)*(internal_data_width + internal_data_extra) + intern_databus_width - 1 + internal_isk_width -: internal_isk_width];
assign RXDISPERR[ii*internal_isk_width - 1 -: internal_isk_width] = dataiface_data_out[(ii-1)*(internal_data_width + internal_data_extra) + intern_databus_width - 1 + internal_isk_width*2 -: internal_isk_width];
assign RXCHARISCOMMA[ii*internal_isk_width - 1 -: internal_isk_width] = dataiface_data_out[(ii-1)*(internal_data_width + internal_data_extra) + intern_databus_width - 1 + internal_isk_width*3 -: internal_isk_width];
assign RXNOTINTABLE[ii*internal_isk_width - 1 -: internal_isk_width] = dataiface_data_out[(ii-1)*(internal_data_width + internal_data_extra) + intern_databus_width - 1 + internal_isk_width*4 -: internal_isk_width];
end
endgenerate
assign RXDATA[63:iface_databus_width] = {64 - iface_databus_width{1'bx}};
assign RXDISPERR[7:interface_isk_width] = {8 - interface_isk_width{1'bx}};
assign RXCHARISK[7:interface_isk_width] = {8 - interface_isk_width{1'bx}};
assign RXCHARISCOMMA[7:interface_isk_width] = {8 - interface_isk_width{1'bx}};
assign RXNOTINTABLE[7:interface_isk_width] = {8 - interface_isk_width{1'bx}};
gtxe2_chnl_rx_dataiface #(
.internal_data_width (internal_data_width + internal_data_extra),
.interface_data_width (interface_data_width + interface_data_extra),
.internal_isk_width (internal_isk_width),
.interface_isk_width (interface_isk_width)
)
dataiface
(
.usrclk (RXUSRCLK),
.usrclk2 (RXUSRCLK2),
.reset (reset),
.indata (dataiface_data_in),
.inisk (internal_isk), // not used actually
.outdata (dataiface_data_out),
.outisk (),
.realign (RXBYTEREALIGN === 1'bx ? 1'b0 : RXBYTEREALIGN)
);
endmodule
module gtxe2_chnl(
input wire reset,
/*
* TX
*/
output wire TXP,
output wire TXN,
input wire [63:0] TXDATA,
input wire TXUSRCLK,
input wire TXUSRCLK2,
// 8/10 encoder
input wire [7:0] TX8B10BBYPASS,
input wire TX8B10BEN,
input wire [7:0] TXCHARDISPMODE,
input wire [7:0] TXCHARDISPVAL,
input wire [7:0] TXCHARISK,
// TX Buffer
output wire [1:0] TXBUFSTATUS,
// TX Polarity
input wire TXPOLARITY,
// TX Fabric Clock Control
input wire [2:0] TXRATE,
output wire TXRATEDONE,
// TX OOB
input wire TXCOMINIT,
input wire TXCOMWAKE,
output wire TXCOMFINISH,
// TX Driver Control
input wire TXELECIDLE,
/*
* RX
*/
input wire RXP,
input wire RXN,
input wire RXUSRCLK,
input wire RXUSRCLK2,
output wire [63:0] RXDATA,
input wire [2:0] RXRATE,
// oob
input wire [1:0] RXELECIDLEMODE,
output wire RXELECIDLE,
output wire RXCOMINITDET,
output wire RXCOMWAKEDET,
// polarity
input wire RXPOLARITY,
// aligner
output wire RXBYTEISALIGNED,
output wire RXBYTEREALIGN,
output wire RXCOMMADET,
input wire RXCOMMADETEN,
input wire RXPCOMMAALIGNEN,
input wire RXMCOMMAALIGNEN,
// 10/8 decoder
input wire RX8B10BEN,
output wire [7:0] RXCHARISCOMMA,
output wire [7:0] RXCHARISK,
output wire [7:0] RXDISPERR,
output wire [7:0] RXNOTINTABLE,
/*
* Clocking
*/
// top-level interfaces
input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0,
input wire GTREFCLK1,
input wire GTNORTHREFCLK0,
input wire GTNORTHREFCLK1,
input wire GTSOUTHREFCLK0,
input wire GTSOUTHREFCLK1,
input wire GTGREFCLK,
input wire QPLLCLK,
input wire QPLLREFCLK,
input wire [1:0] RXSYSCLKSEL,
input wire [1:0] TXSYSCLKSEL,
input wire [2:0] TXOUTCLKSEL,
input wire [2:0] RXOUTCLKSEL,
input wire TXDLYBYPASS,
input wire RXDLYBYPASS,
output wire GTREFCLKMONITOR,
input wire CPLLLOCKDETCLK,
input wire CPLLLOCKEN,
input wire CPLLPD,
input wire CPLLRESET,
output wire CPLLFBCLKLOST,
output wire CPLLLOCK,
output wire CPLLREFCLKLOST,
// phy-level interfaces
output wire TXOUTCLKPMA,
output wire TXOUTCLKPCS,
output wire TXOUTCLK,
output wire TXOUTCLKFABRIC,
output wire tx_serial_clk,
output wire RXOUTCLKPMA,
output wire RXOUTCLKPCS,
output wire RXOUTCLK,
output wire RXOUTCLKFABRIC,
output wire rx_serial_clk,
// additional ports to pll
output [9:0] TSTOUT,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input [4:0] PMARSVDIN2,
input [19:0] TSTIN
);
parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
parameter integer CPLL_REFCLK_DIV = 1;
parameter [1:0] PMA_RSV3 = 1;
parameter TXOUT_DIV = 2;
//parameter TXRATE = 3'b000;
parameter RXOUT_DIV = 2;
//parameter RXRATE = 3'b000;
parameter integer TX_INT_DATAWIDTH = 0;
parameter integer TX_DATA_WIDTH = 20;
parameter integer RX_DATA_WIDTH = 20;
parameter integer RX_INT_DATAWIDTH = 0;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
gtxe2_chnl_tx #(
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_CPLL_CFG (SATA_CPLL_CFG)
)
tx(
.reset (reset),
.TXP (TXP),
.TXN (TXN),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXBUFSTATUS (TXBUFSTATUS),
.TXPOLARITY (TXPOLARITY),
.TXRATE (TXRATE),
.TXRATEDONE (TXRATEDONE),
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.TXELECIDLE (TXELECIDLE),
.serial_clk (tx_serial_clk)
);
gtxe2_chnl_rx #(
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE)
)
rx(
.reset (reset),
.RXP (RXP),
.RXN (RXN),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.RXDATA (RXDATA),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXPOLARITY (RXPOLARITY),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.serial_clk (rx_serial_clk)
);
gtxe2_chnl_clocking #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH)
)
clocking(
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK ),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.TXOUTCLKSEL (TXOUTCLKSEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.RXDLYBYPASS (RXDLYBYPASS),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TXRATE (TXRATE),
.RXRATE (RXRATE),
.TXOUTCLKPMA (TXOUTCLKPMA),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (tx_serial_clk),
.tx_piso_clk (),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.PCSRSVDIN2 (PCSRSVDIN2),
.PMARSVDIN (PMARSVDIN),
.PMARSVDIN2 (PMARSVDIN2),
.TSTIN (TSTIN),
.TSTOUT (TSTOUT),
.RXOUTCLKPMA (RXOUTCLKPMA),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (rx_serial_clk),
.rx_sipo_clk ()
);
endmodule
module GTXE2_GPL(
// clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input [1:0] RXSYSCLKSEL,
input [1:0] TXSYSCLKSEL,
output GTREFCLKMONITOR,
// CPLL Ports, UG476 p.48
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input CPLLRESET,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [9:0] TSTOUT,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input [4:0] PMARSVDIN2,
input [19:0] TSTIN,
// Reset Mode ports, ug476 p.62
input GTRESETSEL,
input RESETOVRD,
// TX Reset ports, ug476 p.65
input CFGRESET,
input GTTXRESET,
input TXPCSRESET,
input TXPMARESET,
output TXRESETDONE,
input TXUSERRDY,
output [15:0] PCSRSVDOUT,
// RX Reset ports, UG476 p.73
input GTRXRESET,
input RXPMARESET,
input RXCDRRESET,
input RXCDRFREQRESET,
input RXDFELPMRESET,
input EYESCANRESET,
input RXPCSRESET,
input RXBUFRESET,
input RXUSERRDY,
output RXRESETDONE,
input RXOOBRESET,
// Power Down ports, ug476 p.88
input [1:0] RXPD,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHDLYPD,
input RXPHDLYPD,
// Loopback ports, ug476 p.91
input [2:0] LOOPBACK,
// Dynamic Reconfiguration Port, ug476 p.92
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
output [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
// Digital Monitor Ports, ug476 p.95
input [3:0] CLKRSVD,
output [7:0] DMONITOROUT,
// TX Interface Ports, ug476 p.110
input [7:0] TXCHARDISPMODE,
input [7:0] TXCHARDISPVAL,
input [63:0] TXDATA,
input TXUSRCLK,
input TXUSRCLK2,
// TX 8B/10B encoder ports, ug476 p.118
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [7:0] TXCHARISK,
// TX Gearbox ports, ug476 p.122
output TXGEARBOXREADY,
input [2:0] TXHEADER,
input [6:0] TXSEQUENCE,
input TXSTARTSEQ,
// TX BUffer Ports, ug476 p.134
output [1:0] TXBUFSTATUS,
// TX Buffer Bypass Ports, ug476 p.136
input TXDLYSRESET,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHINIT,
input TXPHOVRDEN,
input TXPHDLYRESET,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYOVRDEN,
input TXPHDLYTSTCLK,
input TXDLYHOLD,
input TXDLYUPDOWN,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXDLYSRESETDONE,
/* input TXSYNCMODE,
input TXSYNCALLIN,
input TXSYNCIN,
output TXSYNCOUT,
output TXSYNCDONE,*/
// TX Pattern Generator, ug476 p.147
input [2:0] TXPRBSSEL,
input TXPRBSFORCEERR,
// TX Polarity Control Ports, ug476 p.149
input TXPOLARITY,
// TX Fabric Clock Output Control Ports, ug476 p.152
input [2:0] TXOUTCLKSEL,
input [2:0] TXRATE,
output TXOUTCLKFABRIC,
output TXOUTCLK,
output TXOUTCLKPCS,
output TXRATEDONE,
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
// GTH only
/* input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMSEL,
input TXPIPPMPD,
input [4:0] TXPIPPMSTEPSIZE,*/
// TX Configurable Driver Ports, ug476 p.156
input [2:0] TXBUFDIFFCTRL,
input TXDEEMPH,
input [3:0] TXDIFFCTRL,
input TXELECIDLE,
input TXINHIBIT,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXQPIBIASEN,
output TXQPISENN,
output TXQPISENP,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXSWING,
input TXDIFFPD,
input TXPISOPD,
// TX Receiver Detection Ports, ug476 p.165
input TXDETECTRX,
output PHYSTATUS,
output [2:0] RXSTATUS,
// TX OOB Signaling Ports, ug476 p.166
output TXCOMFINISH,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
// RX AFE Ports, ug476 p.171
output RXQPISENN,
output RXQPISENP,
input RXQPIEN,
// RX OOB Signaling Ports, ug476 p.178
input [1:0] RXELECIDLEMODE,
output RXELECIDLE,
output RXCOMINITDET,
output RXCOMSASDET,
output RXCOMWAKEDET,
// RX Equalizer Ports, ug476 p.189
input RXLPMEN,
input RXOSHOLD,
input RXOSOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFECM1EN,
input RXDFEXYDHOLD,
input RXDFEXYDOVRDEN,
input RXDFEXYDEN,
input [1:0] RXMONITORSEL,
output [6:0] RXMONITOROUT,
// CDR Ports, ug476 p.202
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESETRSV,
input [2:0] RXRATE,
output RXCDRLOCK,
// RX Fabric Clock Output Control Ports, ug476 p.213
input [2:0] RXOUTCLKSEL,
output RXOUTCLKFABRIC,
output RXOUTCLK,
output RXOUTCLKPCS,
output RXRATEDONE,
input RXDLYBYPASS,
// RX Margin Analysis Ports, ug476 p.220
output EYESCANDATAERROR,
input EYESCANTRIGGER,
input EYESCANMODE,
// RX Polarity Control Ports, ug476 p.224
input RXPOLARITY,
// Pattern Checker Ports, ug476 p.225
input RXPRBSCNTRESET,
input [2:0] RXPRBSSEL,
output RXPRBSERR,
// RX Byte and Word Alignment Ports, ug476 p.233
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCOMMADET,
input RXCOMMADETEN,
input RXPCOMMAALIGNEN,
input RXMCOMMAALIGNEN,
input RXSLIDE,
// RX 8B/10B Decoder Ports, ug476 p.241
input RX8B10BEN,
output [7:0] RXCHARISCOMMA,
output [7:0] RXCHARISK,
output [7:0] RXDISPERR,
output [7:0] RXNOTINTABLE,
input SETERRSTATUS,
// RX Buffer Bypass Ports, ug476 p.244
input RXPHDLYRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHOVRDEN,
input RXDLYSRESET,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDDIEN,
output RXPHALIGNDONE,
output [4:0] RXPHMONITOR,
output [4:0] RXPHSLIPMONITOR,
output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259
output [2:0] RXBUFSTATUS,
// RX Clock Correction Ports, ug476 p.263
output [1:0] RXCLKCORCNT,
// RX Channel Bonding Ports, ug476 p.274
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
input [4:0] RXCHBONDI,
output [4:0] RXCHBONDO,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCHBONDEN,
// RX Gearbox Ports, ug476 p.285
output RXDATAVALID,
input RXGEARBOXSLIP,
output [2:0] RXHEADER,
output RXHEADERVALID,
output RXSTARTOFSEQ,
// FPGA RX Interface Ports, ug476 p.299
output [63:0] RXDATA,
input RXUSRCLK,
input RXUSRCLK2,
// ug476, p.323
output RXVALID,
// for correct clocking scheme in case of multilane structure
input QPLLCLK,
input QPLLREFCLK,
// dunno
input RXDFEVSEN,
// Diffpairs
input GTXRXP,
input GTXRXN,
output GTXTXN,
output GTXTXP
);
// simulation common attributes, UG476 p.28
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
// Clocking Atributes, UG476 p.38
parameter OUTREFCLK_SEL_INV = 1'b0;
// CPLL Attributes, UG476 p.49
parameter CPLL_CFG = 24'h0;
parameter CPLL_FBDIV = 4;
parameter CPLL_FBDIV_45 = 5;
parameter CPLL_INIT_CFG = 24'h0;
parameter CPLL_LOCK_CFG = 16'h0;
parameter CPLL_REFCLK_DIV = 1;
parameter RXOUT_DIV = 2;
parameter TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter PMA_RSV3 = 2'b00;
// TX Initialization and Reset Attributes, ug476 p.66
parameter TXPCSRESET_TIME = 5'b00001;
parameter TXPMARESET_TIME = 5'b00001;
// RX Initialization and Reset Attributes, UG476 p.75
parameter RXPMARESET_TIME = 5'h0;
parameter RXCDRPHRESET_TIME = 5'h0;
parameter RXCDRFREQRESET_TIME = 5'h0;
parameter RXDFELPMRESET_TIME = 7'h0;
parameter RXISCANRESET_TIME = 7'h0;
parameter RXPCSRESET_TIME = 5'h0;
parameter RXBUFRESET_TIME = 5'h0;
// Power Down attributes, ug476 p.88
parameter PD_TRANS_TIME_FROM_P2 = 12'h0;
parameter PD_TRANS_TIME_NONE_P2 = 8'h0;
parameter PD_TRANS_TIME_TO_P2 = 8'h0;
parameter TRANS_TIME_RATE = 8'h0;
parameter RX_CLKMUX_PD = 1'b0;
parameter TX_CLKMUX_PD = 1'b0;
// GTX Digital Monitor Attributes, ug476 p.96
parameter DMONITOR_CFG = 24'h008101;
// TX Interface attributes, ug476 p.111
parameter TX_DATA_WIDTH = 20;
parameter TX_INT_DATAWIDTH = 0;
// TX Gearbox Attributes, ug476 p.121
parameter GEARBOX_MODE = 3'h0;
parameter TXGEARBOX_EN = "FALSE";
// TX BUffer Attributes, ug476 p.134
parameter TXBUF_EN = "TRUE";
// TX Bypass buffer, ug476 p.138
parameter TX_XCLK_SEL = "TXOUT";
parameter TXPH_CFG = 16'h0;
parameter TXPH_MONITOR_SEL = 5'h0;
parameter TXPHDLY_CFG = 24'h0;
parameter TXDLY_CFG = 16'h0;
parameter TXDLY_LCFG = 9'h0;
parameter TXDLY_TAP_CFG = 16'h0;
parameter TXSYNC_MULTILANE = 1'b0;
parameter TXSYNC_SKIP_DA = 1'b0;
parameter TXSYNC_OVRD = 1'b1;
parameter LOOPBACK_CFG = 1'b0;
// TX Pattern Generator, ug476 p.147
parameter RXPRBS_ERR_LOOPBACK = 1'b0;
// TX Fabric Clock Output Control Attributes, ug476 p. 153
parameter TXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
// GTH only
/*parameter TXPI_SYNCFREQ_PPM = 3'b001;
parameter TXPI_PPM_CFG = 8'd0;
parameter TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_GREY_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "12345";*/
// TX Configurable Driver Attributes, ug476 p.162
parameter TX_DEEMPH0 = 5'b10100;
parameter TX_DEEMPH1 = 5'b01101;
parameter TX_DRIVE_MODE = "DIRECT";
parameter TX_MAINCURSOR_SEL = 1'b0;
parameter TX_MARGIN_FULL_0 = 7'b0;
parameter TX_MARGIN_FULL_1 = 7'b0;
parameter TX_MARGIN_FULL_2 = 7'b0;
parameter TX_MARGIN_FULL_3 = 7'b0;
parameter TX_MARGIN_FULL_4 = 7'b0;
parameter TX_MARGIN_LOW_0 = 7'b0;
parameter TX_MARGIN_LOW_1 = 7'b0;
parameter TX_MARGIN_LOW_2 = 7'b0;
parameter TX_MARGIN_LOW_3 = 7'b0;
parameter TX_MARGIN_LOW_4 = 7'b0;
parameter TX_PREDRIVER_MODE = 1'b0;
parameter TX_QPI_STATUS_EN = 1'b0;
parameter TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
// TX Receiver Detection Attributes, ug476 p.165
parameter TX_RXDETECT_CFG = 14'h0;
parameter TX_RXDETECT_REF = 3'h0;
// TX OOB Signaling Attributes
parameter SATA_BURST_SEQ_LEN = 4'b0101;
// RX AFE Attributes, ug476 p.171
parameter RX_CM_SEL = 2'b11;
parameter TERM_RCAL_CFG = 5'b0;
parameter TERM_RCAL_OVRD = 1'b0;
parameter RX_CM_TRIM = 3'b010;
// RX OOB Signaling Attributes, ug476 p.179
parameter PCS_RSVD_ATTR = 48'h0100; // oob is up
parameter RXOOB_CFG = 7'b0000110;
parameter SATA_BURST_VAL = 3'b110;
parameter SATA_EIDLE_VAL = 3'b110;
parameter SAS_MIN_COM = 36;
parameter SATA_MIN_INIT = 12;
parameter SATA_MIN_WAKE = 4;
parameter SATA_MAX_BURST = 8;
parameter SATA_MIN_BURST = 4;
parameter SAS_MAX_COM = 64;
parameter SATA_MAX_INIT = 21;
parameter SATA_MAX_WAKE = 7;
// RX Equalizer Attributes, ug476 p.193
parameter RX_OS_CFG = 13'h0080;
parameter RXLPM_LF_CFG = 14'h00f0;
parameter RXLPM_HF_CFG = 14'h00f0;
parameter RX_DFE_LPM_CFG = 16'h0;
parameter RX_DFE_GAIN_CFG = 23'h020FEA;
parameter RX_DFE_H2_CFG = 12'h0;
parameter RX_DFE_H3_CFG = 12'h040;
parameter RX_DFE_H4_CFG = 11'h0e0;
parameter RX_DFE_H5_CFG = 11'h0e0;
parameter PMA_RSV = 32'h00018480;
parameter RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter RX_DFE_XYD_CFG = 13'h0;
parameter PMA_RSV4 = 32'h0;
parameter PMA_RSV2 = 16'h0;
parameter RX_BIAS_CFG = 12'h040;
parameter RX_DEBUG_CFG = 12'h0;
parameter RX_DFE_KL_CFG = 13'h0;
parameter RX_DFE_KL_CFG2 = 32'h0;
parameter RX_DFE_UT_CFG = 17'h11e00;
parameter RX_DFE_VP_CFG = 17'h03f03;
// CDR Attributes, ug476 p.203
parameter RXCDR_CFG = 72'h0;
parameter RXCDR_LOCK_CFG = 6'h0;
parameter RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_PH_RESET_ON_EIDLE = 1'b0;
// RX Fabric Clock Output Control Attributes
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// RX Margin Analysis Attributes
parameter ES_VERT_OFFSET = 9'h0;
parameter ES_HORZ_OFFSET = 12'h0;
parameter ES_PRESCALE = 5'h0;
parameter ES_SDATA_MASK = 80'h0;
parameter ES_QUALIFIER = 80'h0;
parameter ES_QUAL_MASK = 80'h0;
parameter ES_EYE_SCAN_EN = 1'b1;
parameter ES_ERRDET_EN = 1'b0;
parameter ES_CONTROL = 6'h0;
parameter es_control_status = 4'b000;
parameter es_rdata = 80'h0;
parameter es_sdata = 80'h0;
parameter es_error_count = 16'h0;
parameter es_sample_count = 16'h0;
parameter RX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter ES_PMA_CFG = 10'h0;
// Pattern Checker Attributes, ug476 p.226
parameter RX_PRBS_ERR_CNT = 16'h15c;
// RX Byte and Word Alignment Attributes, ug476 p.235
parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_MODE = "OFF";
parameter RXSLIDE_AUTO_WAIT = 7;
parameter RX_SIG_VALID_DLY = 10;
parameter COMMA_ALIGN_LATENCY = 9'h14e;
// RX 8B/10B Decoder Attributes, ug476 p.242
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "FALSE";
parameter UCODEER_CLR = 1'b0;
// RX Buffer Bypass Attributes, ug476 p.247
parameter RXBUF_EN = "TRUE";
parameter RX_XCLK_SEL = "RXREC";
parameter RXPH_CFG = 24'h0;
parameter RXPH_MONITOR_SEL = 5'h0;
parameter RXPHDLY_CFG = 24'h0;
parameter RXDLY_CFG = 16'h0;
parameter RXDLY_LCFG = 9'h0;
parameter RXDLY_TAP_CFG = 16'h0;
parameter RX_DDI_SEL = 6'h0;
parameter TST_RSV = 32'h0;
// RX Buffer Attributes, ug476 p.259
parameter RX_BUFFER_CFG = 6'b0;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RXBUF_ADDR_MODE = "FAST";
parameter RXBUF_EIDLE_HI_CNT = 4'b0;
parameter RXBUF_EIDLE_LO_CNT = 4'b0;
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_THRESH_OVFLW = 0;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter RXBUF_THRESH_UNDFLW = 0;
// RX Clock Correction Attributes, ug476 p.265
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter CLK_COR_MAX_LAT = 9;
parameter CLK_COR_MIN_LAT = 7;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter CLK_COR_REPEAT_WAIT = 0;
parameter CLK_COR_SEQ_LEN = 1;
parameter CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_1_1 = 10'b0;
parameter CLK_COR_SEQ_1_2 = 10'b0;
parameter CLK_COR_SEQ_1_3 = 10'b0;
parameter CLK_COR_SEQ_1_4 = 10'b0;
parameter CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_1 = 10'b0;
parameter CLK_COR_SEQ_2_2 = 10'b0;
parameter CLK_COR_SEQ_2_3 = 10'b0;
parameter CLK_COR_SEQ_2_4 = 10'b0;
// RX Channel Bonding Attributes, ug476 p.276
parameter CHAN_BOND_MAX_SKEW = 1;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_SEQ_1_1 = 10'b0;
parameter CHAN_BOND_SEQ_1_2 = 10'b0;
parameter CHAN_BOND_SEQ_1_3 = 10'b0;
parameter CHAN_BOND_SEQ_1_4 = 10'b0;
parameter CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_1 = 10'b0;
parameter CHAN_BOND_SEQ_2_2 = 10'b0;
parameter CHAN_BOND_SEQ_2_3 = 10'b0;
parameter CHAN_BOND_SEQ_2_4 = 10'b0;
parameter CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter PCS_PCIE_EN = "FALSE";
// RX Gearbox Attributes, ug476 p.287
parameter RXGEARBOX_EN = "FALSE";
// ug476 table p.326 - undocumented parameters
parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6;
// clocking reset ( + TX PMA)
//wire clk_reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXDLYSRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
wire clk_reset = EYESCANRESET | RXCDRFREQRESET | RXCDRRESET | RXCDRRESETRSV | RXPRBSCNTRESET | RXBUFRESET | RXPHDLYRESET | RXDFELPMRESET | GTRXRESET | RXOOBRESET | RXPCSRESET | RXPMARESET | CFGRESET | GTTXRESET | GTRESETSEL | RESETOVRD | TXDLYSRESET | TXPHDLYRESET | TXPCSRESET | TXPMARESET;
// have to wait before an external pll (mmcm) locks with usrclk, after that PCS can be resetted. Actually, we reset PMA also, because why not
reg reset;
reg [31:0] reset_timer = 0;
always @ (posedge TXUSRCLK)
reset_timer <= ~TXUSERRDY ? 32'h0 : reset_timer == 32'hffffffff ? reset_timer : reset_timer + 1'b1;
always @ (posedge TXUSRCLK)
reset <= ~TXUSERRDY ? 1'b0 : reset_timer < 32'd20 ? 1'b1 : 1'b0;
reg rx_rst_done = 1'b0;
reg tx_rst_done = 1'b0;
reg rxcdrlock = 1'b0;
reg rxdlysresetdone = 1'b0;
reg rxphaligndone = 1'b0;
assign RXRESETDONE = rx_rst_done;
assign TXRESETDONE = tx_rst_done;
assign RXCDRLOCK = rxcdrlock;
assign RXDLYSRESETDONE = rxdlysresetdone;
assign RXPHALIGNDONE = rxphaligndone;
localparam DRP_LATENCY = 5;
integer drp_latency_counter;
reg drp_rdy_r;
reg [15:0] drp_ram[0:511];
reg [ 8:0] drp_raddr;
assign DRPDO = drp_rdy_r ? drp_ram[drp_raddr] : 16'bz;
assign DRPRDY = drp_rdy_r;
always @ (posedge DRPCLK) begin
if (DRPEN) drp_latency_counter <= DRP_LATENCY;
else if (drp_latency_counter != 0) drp_latency_counter <= drp_latency_counter - 1;
if (DRPEN && DRPWE) drp_ram[DRPADDR] <= DRPDI;
drp_rdy_r <= (drp_latency_counter == 1);
if (DRPEN) drp_raddr <= DRPADDR;
end
wire reset_or_GTRXRESET = reset || GTRXRESET;
initial
forever @ (posedge reset_or_GTRXRESET)
begin
tx_rst_done <= 1'b0;
@ (negedge reset_or_GTRXRESET);
repeat (80)
@ (posedge GTREFCLK0);
tx_rst_done <= 1'b1;
end
initial
forever @ (posedge reset_or_GTRXRESET)
begin
rx_rst_done <= 1'b0;
@ (negedge reset_or_GTRXRESET);
repeat (100)
@ (posedge GTREFCLK0);
rx_rst_done <= 1'b1;
end
localparam RXCDRLOCK_DELAY = 10; // Refclk periods
localparam RXDLYSRESET_MIN_DURATION = 50; // ns
localparam RXDLYSRESETDONE_DELAY = 10;
localparam RXDLYSRESETDONE_DURATION = 7; // 100ns
localparam RXPHALIGNDONE_DELAY1 = 15; // 0.45 usec from the end of reset (measured)
localparam RXPHALIGNDONE_DURATION1 = 7;
localparam RXPHALIGNDONE_DELAY2 = 311; // 4.9 usec from the end of reset (measured)
initial forever @ (posedge (reset || RXELECIDLE)) begin
rxcdrlock <= 1'b0;
@ (negedge (reset || RXELECIDLE));
repeat (RXCDRLOCK_DELAY) @ (posedge GTREFCLK0);
rxcdrlock <= 1'b1;
end
initial forever @ (posedge RXDLYSRESET) begin
rxdlysresetdone <= 1'b0;
rxphaligndone <= 1'b0;
# (RXDLYSRESET_MIN_DURATION);
if (!RXDLYSRESET) begin
$display ("%m: RXDLYSRESET is too short - minimal duration is 50 nsec");
end else begin
@ (negedge RXDLYSRESET);
// if (!RXELECIDLE && rxcdrlock) begin
if (!RXELECIDLE) begin // removed that condition - rxcdrlock seems to go up/down (SS?)
repeat (RXDLYSRESETDONE_DELAY) @ (posedge GTREFCLK0);
rxdlysresetdone <= 1'b1;
repeat (RXDLYSRESETDONE_DURATION) @ (posedge GTREFCLK0);
rxdlysresetdone <= 1'b0;
repeat (RXPHALIGNDONE_DELAY1) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b1;
repeat (RXPHALIGNDONE_DURATION1) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b0;
repeat (RXPHALIGNDONE_DELAY2) @ (posedge GTREFCLK0);
rxphaligndone <= 1'b1;
end else $display ("%m: RXELECIDLE in active or rxcdrlock is inactive when applying RXDLYSRESET");
end
end
//RXELECIDLE
gtxe2_chnl #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN)
)
channel(
.reset (reset),
.TXP (GTXTXP),
.TXN (GTXTXN),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXBUFSTATUS (TXBUFSTATUS),
.TXPOLARITY (TXPOLARITY),
.TXRATE (TXRATE),
.RXRATE (RXRATE),
.TXRATEDONE (TXRATEDONE),
.TXCOMINIT (TXCOMINIT),
.TXCOMWAKE (TXCOMWAKE),
.TXCOMFINISH (TXCOMFINISH),
.TXELECIDLE (TXELECIDLE),
.RXP (GTXRXP),
.RXN (GTXRXN),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.RXDATA (RXDATA),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXPOLARITY (RXPOLARITY),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.GTGREFCLK (GTGREFCLK),
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.TXOUTCLKSEL (TXOUTCLKSEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.TXDLYBYPASS (TXDLYBYPASS),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK ),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.PCSRSVDIN2 (PCSRSVDIN2),
.PMARSVDIN (PMARSVDIN),
.PMARSVDIN2 (PMARSVDIN2),
.TSTIN (TSTIN),
.TSTOUT (TSTOUT),
.TXOUTCLKPMA (),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (),
.RXOUTCLKPMA (),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (),
.RXDLYBYPASS (RXDLYBYPASS)
);
endmodule
|
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
// verilator lint_off PINMISSING
`ifdef T_GEN_MISSING_BAD
foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
`elsif T_GEN_MISSING
foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
`else
`error "Bad Test"
`endif
endmodule
module foobar
#( parameter
FOO_START = 0,
FOO_NUM = 2,
FOO_TYPE = 1
)
(
input wire[FOO_NUM-1:0] foo,
output wire[FOO_NUM-1:0] bar);
generate
begin: g
genvar j;
for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
begin: foo_inst;
if (FOO_TYPE == 0)
begin: foo_0
// instatiate foo0
foo0 i_foo(.x(foo[j]), .y(bar[j]));
end
if (FOO_TYPE == 1)
begin: foo_1
// instatiate foo1
foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
end
end
end
endgenerate
endmodule
module foo0(input wire x, output wire y);
assign y = ~x;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter ID = 0;
parameter CR_CB_N = 0;
parameter DEVICE_TYPE = 0;
parameter EMBEDDED_SYNC = 0;
/* 0 = Launch on rising edge, 1 = Launch on falling edge */
parameter OUT_CLK_POLARITY = 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
localparam ALTERA_5SERIES = 16;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_rst;
// internal signals
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
// hdmi output clock
generate
if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
if (DEVICE_TYPE == ALTERA_5SERIES) begin
altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.outclocken (1'b1),
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
.outclock (hdmi_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
if (DEVICE_TYPE == XILINX_7SERIES) begin
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_LP2_V
`define SKY130_FD_SC_LP__DLXTP_LP2_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp2 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp2 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_LP2_V
|
module basic_checker
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(mem_size_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter cache_pkt_width_lp= `bsg_cache_pkt_width(addr_width_p,data_width_p)
)
(
input clk_i
, input reset_i
, input en_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_i
, input ready_o
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
localparam lg_data_size_in_bytes_lp = `BSG_SAFE_CLOG2(data_width_p/8);
localparam lg_data_size_in_half_lp = `BSG_SAFE_CLOG2(data_width_p/16);
localparam lg_data_size_in_words_lp = `BSG_SAFE_CLOG2(data_width_p/32);
localparam lg_data_size_in_dwords_lp = `BSG_SAFE_CLOG2(data_width_p/64);
bsg_cache_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0];
logic [data_width_p-1:0] result [*];
wire [addr_width_p-1:0] cache_pkt_word_addr = cache_pkt.addr[addr_width_p-1:lg_data_size_in_bytes_lp];
// store logic
logic [data_width_p-1:0] load_data, load_data_final;
logic [data_width_p-1:0] store_pre_data;
logic [data_width_p-1:0] store_data;
logic [data_mask_width_lp-1:0] store_mask;
always_comb begin
case (cache_pkt.opcode)
// Arithmetic ops need to be applied to individual segments
AMOADD_W: begin
store_pre_data = cache_pkt.data[0+:32] + load_data_final[0+:32];
end
AMOADD_D: begin
store_pre_data = cache_pkt.data[0+:64] + load_data_final[0+:64];
end
AMOMIN_W: begin
store_pre_data = (cache_pkt.data[0+:32] < load_data_final[0+:32])
? cache_pkt.data[0+:32]
: load_data_final[0+:32];
end
AMOMIN_D: begin
store_pre_data = (cache_pkt.data[0+:64] < load_data_final[0+:64])
? cache_pkt.data[0+:64]
: load_data_final[0+:64];
end
AMOMAX_W: begin
store_pre_data = (cache_pkt.data[0+:32] > load_data_final[0+:32])
? cache_pkt.data[0+:32]
: load_data_final[0+:32];
end
AMOMAX_D: begin
store_pre_data = (cache_pkt.data[0+:64] > load_data_final[0+:64])
? cache_pkt.data[0+:64]
: load_data_final[0+:64];
end
AMOMINU_W: begin
store_pre_data = ($unsigned(cache_pkt.data[0+:32]) < $unsigned(load_data_final[0+:32]))
? cache_pkt.data[0+:32]
: load_data_final[0+:32];
end
AMOMINU_D: begin
store_pre_data = ($unsigned(cache_pkt.data[0+:64]) < $unsigned(load_data_final[0+:64]))
? cache_pkt.data[0+:64]
: load_data_final[0+:64];
end
AMOMAXU_W: begin
store_pre_data = ($unsigned(cache_pkt.data[0+:32]) > $unsigned(load_data_final[0+:32]))
? cache_pkt.data[0+:32]
: load_data_final[0+:32];
end
AMOMAXU_D: begin
store_pre_data = ($unsigned(cache_pkt.data[0+:64]) > $unsigned(load_data_final[0+:64]))
? cache_pkt.data[0+:64]
: load_data_final[0+:64];
end
AMOXOR_W, AMOXOR_D: begin
store_pre_data = cache_pkt.data ^ load_data_final;
end
AMOAND_W, AMOAND_D: begin
store_pre_data = cache_pkt.data & load_data_final;
end
AMOOR_W, AMOOR_D: begin
store_pre_data = cache_pkt.data | load_data_final;
end
default: begin
store_pre_data = cache_pkt.data;
end
endcase
end
always_comb begin
case (cache_pkt.opcode)
SD, AMOSWAP_D, AMOADD_D, AMOXOR_D
,AMOAND_D, AMOOR_D, AMOMIN_D
,AMOMAX_D, AMOMINU_D, AMOMAXU_D: begin
store_data = {(data_width_p/64){store_pre_data[63:0]}};
if (data_width_p > 64)
store_mask = 8'b1111_1111 << (cache_pkt.addr[3+:lg_data_size_in_dwords_lp]*8);
else
store_mask = 8'b1111_1111;
end
SW, AMOSWAP_W, AMOADD_W, AMOXOR_W
,AMOAND_W, AMOOR_W, AMOMIN_W
,AMOMAX_W, AMOMINU_W, AMOMAXU_W: begin
store_data = {(data_width_p/32){store_pre_data[31:0]}};
store_mask = 4'b1111 << (cache_pkt.addr[2+:lg_data_size_in_words_lp]*4);
end
SH: begin
store_data = {(data_width_p/16){store_pre_data[15:0]}};
store_mask = 2'b11 << (cache_pkt.addr[1+:lg_data_size_in_half_lp]*2);
end
SB: begin
store_data = {(data_width_p/8){store_pre_data[7:0]}};
store_mask = 1'b1 << cache_pkt.addr[0+:lg_data_size_in_bytes_lp];
end
SM: begin
store_data = store_pre_data;
store_mask = cache_pkt.mask;
end
default: begin
store_data = '0;
store_mask = '0;
end
endcase
end
// load logic
logic [7:0] byte_sel;
logic [15:0] half_sel;
logic [31:0] word_sel;
logic [63:0] dword_sel;
assign load_data = shadow_mem[cache_pkt_word_addr];
bsg_mux #(
.els_p(data_width_p/8)
,.width_p(8)
) byte_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[0+:lg_data_size_in_bytes_lp])
,.data_o(byte_sel)
);
bsg_mux #(
.els_p(data_width_p/16)
,.width_p(16)
) half_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1+:lg_data_size_in_half_lp])
,.data_o(half_sel)
);
bsg_mux #(
.els_p(data_width_p/32)
,.width_p(32)
) word_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[2+:lg_data_size_in_words_lp])
,.data_o(word_sel)
);
bsg_mux #(
.els_p(data_width_p/64)
,.width_p(64)
) dword_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[3+:lg_data_size_in_dwords_lp])
,.data_o(dword_sel)
);
always_comb begin
case (cache_pkt.opcode)
LD, AMOSWAP_D, AMOADD_D, AMOXOR_D
,AMOAND_D, AMOOR_D, AMOMIN_D
,AMOMAX_D, AMOMINU_D, AMOMAXU_D: load_data_final = {{(data_width_p-64){dword_sel[63]}}, dword_sel};
LW, AMOSWAP_W, AMOADD_W, AMOXOR_W
,AMOAND_W, AMOOR_W, AMOMIN_W
,AMOMAX_W, AMOMINU_W, AMOMAXU_W: load_data_final = {{(data_width_p-32){word_sel[31]}}, word_sel};
LH: load_data_final = {{(data_width_p-16){half_sel[15]}}, half_sel};
LB: load_data_final = {{(data_width_p-8){byte_sel[7]}}, byte_sel};
LWU: load_data_final = {{(data_width_p-32){1'b0}}, word_sel};
LHU: load_data_final = {{(data_width_p-16){1'b0}}, half_sel};
LBU: load_data_final = {{(data_width_p-8){1'b0}}, byte_sel};
LM: begin
for (integer i = 0; i < data_mask_width_lp; i++)
if (cache_pkt.mask[i])
load_data_final[8*i+:8] = load_data[8*i+:8];
else
load_data_final[8*i+:8] = 8'h0;
end
default: load_data_final = '0;
endcase
end
integer send_id, recv_id;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
send_id <= '0;
recv_id <= '0;
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] = '0;
end
else begin
if (en_i) begin
// input recorder
if (v_i & ready_o) begin
case (cache_pkt.opcode)
TAGST: begin
result[send_id] = '0;
send_id++;
end
LM, LD, LW, LH, LB, LWU, LHU, LBU: begin
result[send_id] = load_data_final;
send_id++;
end
SM, SD, SW, SH, SB: begin
result[send_id] = '0;
send_id++;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
AMOSWAP_W, AMOADD_W, AMOXOR_W,
AMOAND_W, AMOOR_W, AMOMIN_W,
AMOMAX_W, AMOMINU_W, AMOMAXU_W,
AMOSWAP_D, AMOADD_D, AMOXOR_D,
AMOAND_D, AMOOR_D, AMOMIN_D,
AMOMAX_D, AMOMINU_D, AMOMAXU_D: begin
result[send_id] = load_data_final;
send_id++;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
ALOCK, AUNLOCK, TAGFL, AFLINV: begin
result[send_id] = '0;
send_id++;
end
endcase
end
// output checker
if (v_o & yumi_i) begin
assert(result[recv_id] == data_o)
else $fatal("[BSG_FATAL] output does not match expected result. Id=%d, Expected: %x. Actual: %x.",
recv_id, result[recv_id], data_o);
recv_id++;
end
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(basic_checker)
|
//
// (c) 2017 ReconfigureIO
//
// <COPYRIGHT TERMS>
//
//
// Provides a 'stub' implementation of the kernel action logic with single AXI
// shared memory interface.
//
`timescale 1ns/1ps
// Can be redefined on the synthesis command line.
`define AXI_MASTER_ADDR_WIDTH 64
// Can be redefined on the synthesis command line.
`define AXI_MASTER_DATA_WIDTH 64
// Can be redefined on the synthesis command line.
`define AXI_MASTER_ID_WIDTH 1
// Can be redefined on the synthesis command line.
`define AXI_MASTER_USER_WIDTH 1
// The module name is common for different kernel action toplevel entities.
// verilator lint_off DECLFILENAME
module teak__action__top__gmem
(go_0Ready, go_0Stop, done_0Ready, done_0Stop, s_axi_araddr, s_axi_arcache, s_axi_arprot,
s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid,
s_axi_rready, s_axi_awaddr, s_axi_awcache, s_axi_awprot, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, m_axi_gmem_awaddr, m_axi_gmem_awlen,
m_axi_gmem_awsize, m_axi_gmem_awburst, m_axi_gmem_awlock, m_axi_gmem_awcache,
m_axi_gmem_awprot, m_axi_gmem_awqos, m_axi_gmem_awregion, m_axi_gmem_awuser,
m_axi_gmem_awid, m_axi_gmem_awvalid, m_axi_gmem_awready, m_axi_gmem_wdata,
m_axi_gmem_wstrb, m_axi_gmem_wlast, m_axi_gmem_wuser,
m_axi_gmem_wvalid, m_axi_gmem_wready, m_axi_gmem_bresp, m_axi_gmem_buser,
m_axi_gmem_bid, m_axi_gmem_bvalid, m_axi_gmem_bready, m_axi_gmem_araddr,
m_axi_gmem_arlen, m_axi_gmem_arsize, m_axi_gmem_arburst, m_axi_gmem_arlock,
m_axi_gmem_arcache, m_axi_gmem_arprot, m_axi_gmem_arqos, m_axi_gmem_arregion,
m_axi_gmem_aruser, m_axi_gmem_arid, m_axi_gmem_arvalid, m_axi_gmem_arready,
m_axi_gmem_rdata, m_axi_gmem_rresp, m_axi_gmem_rlast, m_axi_gmem_ruser,
m_axi_gmem_rid, m_axi_gmem_rvalid, m_axi_gmem_rready, paramaddr_0Ready,
paramaddr_0Data, paramaddr_0Stop, paramdata_0Ready, paramdata_0Data, paramdata_0Stop,
clk, reset);
// verilator lint_on DECLFILENAME
// Action control signals.
input go_0Ready;
output go_0Stop;
output done_0Ready;
input done_0Stop;
// Parameter data access signals. Provides a SELF channel output for address
// values and a SELF channel input for the corresponding data items read from
// the parameter register file.
// verilator lint_off UNUSED
output paramaddr_0Ready;
output [31:0] paramaddr_0Data;
input paramaddr_0Stop;
input paramdata_0Ready;
input [31:0] paramdata_0Data;
output paramdata_0Stop;
// verilator lint_on UNUSED
// AXI interface signals are not used in the stub implementation.
// verilator lint_off UNUSED
// Specifies the AXI slave bus signals.
input [31:0] s_axi_araddr;
input [3:0] s_axi_arcache;
input [2:0] s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0] s_axi_rdata;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [31:0] s_axi_awaddr;
input [3:0] s_axi_awcache;
input [2:0] s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0] s_axi_wdata;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
// Specifies the AXI master write address signals.
output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_awaddr;
output [7:0] m_axi_gmem_awlen;
output [2:0] m_axi_gmem_awsize;
output [1:0] m_axi_gmem_awburst;
output m_axi_gmem_awlock;
output [3:0] m_axi_gmem_awcache;
output [2:0] m_axi_gmem_awprot;
output [3:0] m_axi_gmem_awqos;
output [3:0] m_axi_gmem_awregion;
output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_awuser;
output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_awid;
output m_axi_gmem_awvalid;
input m_axi_gmem_awready;
// Specifies the AXI master write data signals.
output [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_wdata;
output [`AXI_MASTER_DATA_WIDTH/8-1:0] m_axi_gmem_wstrb;
output m_axi_gmem_wlast;
output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_wuser;
output m_axi_gmem_wvalid;
input m_axi_gmem_wready;
// Specifies the AXI master write response signals.
input [1:0] m_axi_gmem_bresp;
input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_buser;
input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_bid;
input m_axi_gmem_bvalid;
output m_axi_gmem_bready;
// Specifies the AXI master read address signals.
output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_araddr;
output [7:0] m_axi_gmem_arlen;
output [2:0] m_axi_gmem_arsize;
output [1:0] m_axi_gmem_arburst;
output m_axi_gmem_arlock;
output [3:0] m_axi_gmem_arcache;
output [2:0] m_axi_gmem_arprot;
output [3:0] m_axi_gmem_arqos;
output [3:0] m_axi_gmem_arregion;
output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_aruser;
output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_arid;
output m_axi_gmem_arvalid;
input m_axi_gmem_arready;
// Specifies the AXI master read data signals.
input [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_rdata;
input [1:0] m_axi_gmem_rresp;
input m_axi_gmem_rlast;
input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_ruser;
input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_rid;
input m_axi_gmem_rvalid;
output m_axi_gmem_rready;
// verilator lint_on UNUSED
// System level signals.
input clk;
input reset;
// Action start loopback signals.
reg action_done_q;
// AXI slave loopback signals.
reg s_axi_read_ready_q;
reg s_axi_read_complete_q;
reg s_axi_write_ready_q;
reg s_axi_write_complete_q;
// Implement action start loopback signals.
always @(posedge clk)
begin
if (reset)
begin
action_done_q <= 1'b0;
end
else if (action_done_q)
begin
action_done_q <= done_0Stop;
end
else if (go_0Ready)
begin
action_done_q <= 1'b1;
end
end
assign go_0Stop = action_done_q;
assign done_0Ready = action_done_q;
// Implement AXI read control loopback.
always @(posedge clk)
begin
if (reset)
begin
s_axi_read_ready_q <= 1'b0;
s_axi_read_complete_q <= 1'b0;
end
else if (s_axi_read_complete_q)
begin
s_axi_read_complete_q <= ~s_axi_rready;
end
else if (s_axi_read_ready_q)
begin
s_axi_read_ready_q <= 1'b0;
s_axi_read_complete_q <= 1'b1;
end
else
begin
s_axi_read_ready_q <= s_axi_arvalid;
end
end
assign s_axi_arready = s_axi_read_ready_q;
assign s_axi_rdata = 32'b0;
assign s_axi_rresp = 2'b0;
assign s_axi_rvalid = s_axi_read_complete_q;
// Implement AXI write control loopback.
always @(posedge clk)
begin
if (reset)
begin
s_axi_write_ready_q <= 1'b0;
s_axi_write_complete_q <= 1'b0;
end
else if (s_axi_write_complete_q)
begin
s_axi_write_complete_q <= ~s_axi_bready;
end
else if (s_axi_write_ready_q)
begin
s_axi_write_ready_q <= 1'b0;
s_axi_write_complete_q <= 1'b1;
end
else
begin
s_axi_write_ready_q <= s_axi_awvalid & s_axi_wvalid;
end
end
assign s_axi_awready = s_axi_write_ready_q;
assign s_axi_wready = s_axi_write_ready_q;
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = s_axi_write_complete_q;
// Tie off unused parameter access signals.
assign paramaddr_0Ready = 1'b0;
assign paramaddr_0Data = 32'b0;
assign paramdata_0Stop = 1'b0;
// Tie of unused AXI memory access signals.
assign m_axi_gmem_awaddr = `AXI_MASTER_ADDR_WIDTH'b0;
assign m_axi_gmem_awlen = 8'b0;
assign m_axi_gmem_awsize = 3'b0;
assign m_axi_gmem_awburst = 2'b0;
assign m_axi_gmem_awlock = 1'b0;
assign m_axi_gmem_awcache = 4'b0;
assign m_axi_gmem_awprot = 3'b0;
assign m_axi_gmem_awqos = 4'b0;
assign m_axi_gmem_awregion = 4'b0;
assign m_axi_gmem_awuser = `AXI_MASTER_USER_WIDTH'b0;
assign m_axi_gmem_awid = `AXI_MASTER_ID_WIDTH'b0;
assign m_axi_gmem_awvalid = 1'b0;
assign m_axi_gmem_wdata = `AXI_MASTER_DATA_WIDTH'b0;
assign m_axi_gmem_wstrb = `AXI_MASTER_DATA_WIDTH/8'b0;
assign m_axi_gmem_wlast = 1'b0;
assign m_axi_gmem_wuser = `AXI_MASTER_USER_WIDTH'b0;
assign m_axi_gmem_wvalid = 1'b0;
assign m_axi_gmem_bready = 1'b0;
assign m_axi_gmem_araddr = `AXI_MASTER_ADDR_WIDTH'b0;
assign m_axi_gmem_arlen = 8'b0;
assign m_axi_gmem_arsize = 3'b0;
assign m_axi_gmem_arburst = 2'b0;
assign m_axi_gmem_arlock = 1'b0;
assign m_axi_gmem_arcache = 4'b0;
assign m_axi_gmem_arprot = 3'b0;
assign m_axi_gmem_arqos = 4'b0;
assign m_axi_gmem_arregion = 4'b0;
assign m_axi_gmem_aruser = `AXI_MASTER_USER_WIDTH'b0;
assign m_axi_gmem_arid = `AXI_MASTER_ID_WIDTH'b0;
assign m_axi_gmem_arvalid = 1'b0;
assign m_axi_gmem_rready = 1'b0;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "decoder_8b10b.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { [email protected], [email protected] } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Section 36.2.4 which is available from : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// ////
//// and the 8B/10B coding scheme from the 1993 IBM publication ////
//// "DC-Balanced, Partitioned-Block, 8B/10B Transmission Code" ////
//// by A.X. Widmer and P.A. Franasze" see doc/01-581v1.pdf ////
//// ////
//// and US patent #4,486,739 "BYTE ORIENTED DC BALANCED ////
//// (0,4) 8B/10B PARTITIONED BLOCK TRANSMISSION CODE "; see : ////
//// ////
//// doc/US4486739.pdf ////
//// ////
//// http://en.wikipedia.org/wiki/8b/10b_encoding ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module decoder_8b10b (
// --- Resets ---
input reset,
// --- Clocks ---
input RBYTECLK,
// --- TBI (Ten Bit Interface) input bus
input [9:0] tbi,
// --- Control (K)
output reg K_out,
// -- Eight bit output bus
output reg [7:0] ebi,
// --- 8B/10B RX coding error ---
output reg coding_err,
// --- 8B/10B RX disparity ---
output reg disparity,
// --- 8B/10B RX disparity error ---
output disparity_err
);
`ifdef MODEL_TECH
// ModelSim debugging only
wire [4:0] decoder_8b_X; wire [2:0] decoder_8b_Y;
assign decoder_8b_X = ebi[4:0];
assign decoder_8b_Y = ebi[7:5];
`endif
wire a,b,c,d,e,i,f,g,h,j; // 10 Bit inputs
assign {a,b,c,d,e,i,f,g,h,j} = tbi[9:0];
// ******************************************************************************
// Figure 10 - Decoder: 6b - Signals
// ******************************************************************************
wire AEQB, CEQD, P22, P13, P31;
// ******************************************************************************
// Figure 11 - Decoder: K - Signals
// ******************************************************************************
wire eeqi, c_d_e_i, cn_dn_en_in;
wire P22_a_c_eeqi, P22_an_cn_eeqi;
wire P22_b_c_eeqi, P22_bn_cn_eeqi, an_bn_en_in;
wire a_b_e_i, P13_d_e_i, P13_in, P13_en, P31_i;
// ******************************************************************************
// Figure 12 - Decoder: 5B - Signals
// ******************************************************************************
wire OR12_1, OR12_2, OR12_3, OR12_4, OR12_5, OR12_6, OR12_7;
wire A, B, C, D, E;
// ******************************************************************************
// Figure 13 - Decoder: 3B - Signals
// ******************************************************************************
wire K, F, G, H, K28p, KA, KB, KC;
// ******************************************************************************
// Figure 10 - Decoder: 6b Input Function
// ******************************************************************************
assign AEQB = (a & b) | (!a & !b) ;
assign CEQD = (c & d) | (!c & !d) ;
assign P22 = (a & b & !c & !d) | (c & d & !a & !b) | ( !AEQB & !CEQD) ;
assign P13 = ( !AEQB & !c & !d) | ( !CEQD & !a & !b) ;
assign P31 = ( !AEQB & c & d) | ( !CEQD & a & b) ;
// ******************************************************************************
// Figure 11 - Decoder: K
// ******************************************************************************
assign eeqi = (e == i);
assign P22_a_c_eeqi = P22 & a & c & eeqi;
assign P22_an_cn_eeqi = P22 & !a & !c & eeqi;
assign cn_dn_en_in = (!c & !d & !e & !i);
assign c_d_e_i = (c & d & e & i);
assign KA = c_d_e_i | cn_dn_en_in;
assign KB = P13 & (!e & i & g & h & j);
assign KC = P31 & (e & !i & !g & !h & !j);
assign K = KA | KB | KC;
assign P22_b_c_eeqi = P22 & b & c & eeqi;
assign P22_bn_cn_eeqi = P22 & !b & !c & eeqi;
assign an_bn_en_in = !a & !b & !e & !i;
assign a_b_e_i = a & b & e & i;
assign P13_d_e_i = P13 & d & e & i;
assign P13_in = P13 & !i;
assign P13_en = P13 & !e;
assign P31_i = P31 & i;
// ******************************************************************************
// Figure 12 - Decoder: 5B/6B
// ******************************************************************************
assign OR12_1 = P22_an_cn_eeqi | P13_en;
assign OR12_2 = a_b_e_i | cn_dn_en_in | P31_i;
assign OR12_3 = P31_i | P22_b_c_eeqi | P13_d_e_i;
assign OR12_4 = P22_a_c_eeqi | P13_en;
assign OR12_5 = P13_en | cn_dn_en_in | an_bn_en_in;
assign OR12_6 = P22_an_cn_eeqi | P13_in;
assign OR12_7 = P13_d_e_i | P22_bn_cn_eeqi;
assign A = a ^ (OR12_7 | OR12_1 | OR12_2);
assign B = b ^ (OR12_2 | OR12_3 | OR12_4);
assign C = c ^ (OR12_1 | OR12_3 | OR12_5);
assign D = d ^ (OR12_2 | OR12_4 | OR12_7);
assign E = e ^ (OR12_5 | OR12_6 | OR12_7);
// ******************************************************************************
// Figure 13 - Decoder: 3B/4B
// ******************************************************************************
// K28 with positive disp into fghi - .1, .2, .5, and .6 specal cases
assign K28p = ! (c | d | e | i) ;
assign F = (j & !f & (h | !g | K28p)) | (f & !j & (!h | g | !K28p)) | (K28p & g & h) | (!K28p & !g & !h) ;
assign G = (j & !f & (h | !g | !K28p)) | (f & !j & (!h | g |K28p)) | (!K28p & g & h) | (K28p & !g & !h) ;
assign H = ((j ^ h) & ! ((!f & g & !h & j & !K28p) | (!f & g & h & !j & K28p) |
(f & !g & !h & j & !K28p) | (f & !g & h & !j & K28p))) | (!f & g & h & j) | (f & !g & !h & !j) ;
// ******************************************************************************
// Registered 8B output
// ******************************************************************************
always @(posedge RBYTECLK or posedge reset)
if (reset)
begin
K_out <= 0; ebi[7:0] <= 8'b0;
end
else
begin
K_out <= K; ebi[7:0] <= { H, G, F, E, D, C, B, A } ;
end
// ******************************************************************************
// Disparity
// ******************************************************************************
wire heqj, fghjP13, fghjP31, fghj22;
wire DISPARITY6p, DISPARITY6n, DISPARITY4p, DISPARITY4n;
wire DISPARITY6b, DISPARITY6a2, DISPARITY6a0;
assign feqg = (f & g) | (!f & !g);
assign heqj = (h & j) | (!h & !j);
assign fghjP13 = ( !feqg & !h & !j) | ( !heqj & !f & !g) ;
assign fghjP31 = ( (!feqg) & h & j) | ( !heqj & f & g) ;
assign fghj22 = (f & g & !h & !j) | (!f & !g & h & j) | ( !feqg & !heqj) ;
assign DISPARITY6p = (P31 & (e | i)) | (P22 & e & i) ;
assign DISPARITY6n = (P13 & ! (e & i)) | (P22 & !e & !i);
assign DISPARITY4p = fghjP31 ;
assign DISPARITY4n = fghjP13 ;
assign DISPARITY6a = P31 | (P22 & disparity); // pos disp if P22 and was pos, or P31.
assign DISPARITY6a2 = P31 & disparity; // disp is ++ after 4 bts
assign DISPARITY6a0 = P13 & ! disparity; // -- disp after 4 bts
assign DISPARITY6b = (e & i & ! DISPARITY6a0) | (DISPARITY6a & (e | i)) | DISPARITY6a2;
// ******************************************************************************
// Disparity errors
// ******************************************************************************
wire derr1,derr2,derr3,derr4,derr5,derr6,derr7,derr8;
assign derr1 = (disparity & DISPARITY6p) | (DISPARITY6n & !disparity);
assign derr2 = (disparity & !DISPARITY6n & f & g);
assign derr3 = (disparity & a & b & c);
assign derr4 = (disparity & !DISPARITY6n & DISPARITY4p);
assign derr5 = (!disparity & !DISPARITY6p & !f & !g);
assign derr6 = (!disparity & !a & !b & !c);
assign derr7 = (!disparity & !DISPARITY6p & DISPARITY4n);
assign derr8 = (DISPARITY6p & DISPARITY4p) | (DISPARITY6n & DISPARITY4n);
// ******************************************************************************
// Register disparity and disparity_err output
// ******************************************************************************
reg derr12, derr34, derr56, derr78;
always @(posedge RBYTECLK or posedge reset)
if (reset)
begin
disparity <= 1'b0;
derr12 <= 1;
derr34 <= 1;
derr56 <= 1;
derr78 <= 1;
end
else
begin
disparity <= fghjP31 | (DISPARITY6b & fghj22) ;
derr12 <= derr1 | derr2;
derr34 <= derr3 | derr4;
derr56 <= derr5 | derr6;
derr78 <= derr7 | derr8;
end
assign disparity_err = derr12|derr34|derr56|derr78;
// ******************************************************************************
// Coding errors as defined in patent - page 447
// ******************************************************************************
wire cerr1, cerr2, cerr3, cerr4, cerr5, cerr6, cerr7, cerr8, cerr9;
assign cerr1 = (a & b & c & d) | (!a & !b & !c & !d);
assign cerr2 = (P13 & !e & !i);
assign cerr3 = (P31 & e & i);
assign cerr4 = (f & g & h & j) | (!f & !g & !h & !j);
assign cerr5 = (e & i & f & g & h) | (!e & !i & !f & !g & !h);
assign cerr6 = (e & !i & g & h & j) | (!e & i & !g & !h & !j);
assign cerr7 = (((e & i & !g & !h & !j) | (!e & !i & g & h & j)) & !((c & d & e) | (!c & !d & !e)));
assign cerr8 = (!P31 & e & !i & !g & !h & !j);
assign cerr9 = (!P13 & !e & i & g & h & j);
reg cerr;
always @(posedge RBYTECLK or posedge reset)
if (reset)
cerr <= 0;
else
cerr <= cerr1|cerr2|cerr3|cerr4|cerr5|cerr6|cerr7|cerr8|cerr9;
// ******************************************************************************
// Disparity coding errors curtosy of http://asics.chuckbenz.com/decode.v
// ******************************************************************************
wire zerr1, zerr2, zerr3;
assign zerr1 = (DISPARITY6p & DISPARITY4p) | (DISPARITY6n & DISPARITY4n);
assign zerr2 = (f & g & !h & !j & DISPARITY6p);
assign zerr3 = (!f & !g & h & j & DISPARITY6n);
reg zerr;
always @(posedge RBYTECLK or posedge reset)
if (reset)
zerr <= 0;
else
zerr <= zerr1|zerr2|zerr3;
// ******************************************************************************
// Extra coding errors - again from http://asics.chuckbenz.com/decode.v
// ******************************************************************************
wire xerr1, xerr2, xerr3, xerr4;
reg xerr;
assign xerr1 = (a & b & c & !e & !i & ((!f & !g) | fghjP13));
assign xerr2 =(!a & !b & !c & e & i & ((f & g) | fghjP31));
assign xerr3 = (c & d & e & i & !f & !g & !h);
assign xerr4 = (!c & !d & !e & !i & f & g & h);
always @(posedge RBYTECLK or posedge reset)
if (reset)
xerr <= 0;
else
xerr <= xerr1|xerr2|xerr3|xerr4;
// ******************************************************************************
// Registered Coding error output
// ******************************************************************************
always @(posedge RBYTECLK or posedge reset)
if (reset)
coding_err <= 1'b1;
else
coding_err <= cerr | zerr | xerr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_V |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
module
compareRecF16 (
input [16:0] a,
input [16:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN#(5, 11)
compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);
endmodule
module
compareRecF32 (
input [32:0] a,
input [32:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN#(8, 24)
compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);
endmodule
module
compareRecF64 (
input [64:0] a,
input [64:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN#(11, 53)
compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);
endmodule
module
compareRecF128 (
input [128:0] a,
input [128:0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
compareRecFN#(15, 113)
compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);
endmodule
|
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