text
stringlengths 992
1.04M
|
|---|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y}, (forall (x: X), f x = g x) -> f = g) ->
forall m a Q,
{{fun st => Q st /\ st X = m}}
X ::= a
{{fun st => Q (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality v a Q.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* FILL IN HERE *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
{{P}} WHILE b DO c END {{P}}.
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
{{P}} WHILE b DO c END {{P /\ ~b}}
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Review *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
#1 $finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
#1 $finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V |
// soc_design_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0 (
input wire system_pll_outclk0_clk, // system_pll_outclk0.clk
input wire niosII_core_reset_reset_bridge_in_reset_reset, // niosII_core_reset_reset_bridge_in_reset.reset
input wire [26:0] niosII_core_data_master_address, // niosII_core_data_master.address
output wire niosII_core_data_master_waitrequest, // .waitrequest
input wire [3:0] niosII_core_data_master_burstcount, // .burstcount
input wire [3:0] niosII_core_data_master_byteenable, // .byteenable
input wire niosII_core_data_master_read, // .read
output wire [31:0] niosII_core_data_master_readdata, // .readdata
output wire niosII_core_data_master_readdatavalid, // .readdatavalid
input wire niosII_core_data_master_write, // .write
input wire [31:0] niosII_core_data_master_writedata, // .writedata
input wire niosII_core_data_master_debugaccess, // .debugaccess
input wire [26:0] niosII_core_instruction_master_address, // niosII_core_instruction_master.address
output wire niosII_core_instruction_master_waitrequest, // .waitrequest
input wire [3:0] niosII_core_instruction_master_burstcount, // .burstcount
input wire niosII_core_instruction_master_read, // .read
output wire [31:0] niosII_core_instruction_master_readdata, // .readdata
output wire niosII_core_instruction_master_readdatavalid, // .readdatavalid
output wire [8:0] convolution_slave_avs_s0_address, // convolution_slave_avs_s0.address
output wire convolution_slave_avs_s0_write, // .write
output wire convolution_slave_avs_s0_read, // .read
input wire [31:0] convolution_slave_avs_s0_readdata, // .readdata
output wire [31:0] convolution_slave_avs_s0_writedata, // .writedata
input wire convolution_slave_avs_s0_waitrequest, // .waitrequest
output wire [0:0] JTAG_avalon_jtag_slave_address, // JTAG_avalon_jtag_slave.address
output wire JTAG_avalon_jtag_slave_write, // .write
output wire JTAG_avalon_jtag_slave_read, // .read
input wire [31:0] JTAG_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] JTAG_avalon_jtag_slave_writedata, // .writedata
input wire JTAG_avalon_jtag_slave_waitrequest, // .waitrequest
output wire JTAG_avalon_jtag_slave_chipselect, // .chipselect
output wire [8:0] niosII_core_debug_mem_slave_address, // niosII_core_debug_mem_slave.address
output wire niosII_core_debug_mem_slave_write, // .write
output wire niosII_core_debug_mem_slave_read, // .read
input wire [31:0] niosII_core_debug_mem_slave_readdata, // .readdata
output wire [31:0] niosII_core_debug_mem_slave_writedata, // .writedata
output wire [3:0] niosII_core_debug_mem_slave_byteenable, // .byteenable
input wire niosII_core_debug_mem_slave_waitrequest, // .waitrequest
output wire niosII_core_debug_mem_slave_debugaccess, // .debugaccess
output wire [24:0] SDRAM_s1_address, // SDRAM_s1.address
output wire SDRAM_s1_write, // .write
output wire SDRAM_s1_read, // .read
input wire [15:0] SDRAM_s1_readdata, // .readdata
output wire [15:0] SDRAM_s1_writedata, // .writedata
output wire [1:0] SDRAM_s1_byteenable, // .byteenable
input wire SDRAM_s1_readdatavalid, // .readdatavalid
input wire SDRAM_s1_waitrequest, // .waitrequest
output wire SDRAM_s1_chipselect, // .chipselect
output wire [14:0] SRAM_s1_address, // SRAM_s1.address
output wire SRAM_s1_write, // .write
input wire [31:0] SRAM_s1_readdata, // .readdata
output wire [31:0] SRAM_s1_writedata, // .writedata
output wire [3:0] SRAM_s1_byteenable, // .byteenable
output wire SRAM_s1_chipselect, // .chipselect
output wire SRAM_s1_clken, // .clken
output wire [2:0] Sys_Timer_s1_address, // Sys_Timer_s1.address
output wire Sys_Timer_s1_write, // .write
input wire [15:0] Sys_Timer_s1_readdata, // .readdata
output wire [15:0] Sys_Timer_s1_writedata, // .writedata
output wire Sys_Timer_s1_chipselect, // .chipselect
output wire [0:0] SystemID_control_slave_address, // SystemID_control_slave.address
input wire [31:0] SystemID_control_slave_readdata // .readdata
);
wire niosii_core_data_master_translator_avalon_universal_master_0_waitrequest; // niosII_core_data_master_agent:av_waitrequest -> niosII_core_data_master_translator:uav_waitrequest
wire [31:0] niosii_core_data_master_translator_avalon_universal_master_0_readdata; // niosII_core_data_master_agent:av_readdata -> niosII_core_data_master_translator:uav_readdata
wire niosii_core_data_master_translator_avalon_universal_master_0_debugaccess; // niosII_core_data_master_translator:uav_debugaccess -> niosII_core_data_master_agent:av_debugaccess
wire [26:0] niosii_core_data_master_translator_avalon_universal_master_0_address; // niosII_core_data_master_translator:uav_address -> niosII_core_data_master_agent:av_address
wire niosii_core_data_master_translator_avalon_universal_master_0_read; // niosII_core_data_master_translator:uav_read -> niosII_core_data_master_agent:av_read
wire [3:0] niosii_core_data_master_translator_avalon_universal_master_0_byteenable; // niosII_core_data_master_translator:uav_byteenable -> niosII_core_data_master_agent:av_byteenable
wire niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid; // niosII_core_data_master_agent:av_readdatavalid -> niosII_core_data_master_translator:uav_readdatavalid
wire niosii_core_data_master_translator_avalon_universal_master_0_lock; // niosII_core_data_master_translator:uav_lock -> niosII_core_data_master_agent:av_lock
wire niosii_core_data_master_translator_avalon_universal_master_0_write; // niosII_core_data_master_translator:uav_write -> niosII_core_data_master_agent:av_write
wire [31:0] niosii_core_data_master_translator_avalon_universal_master_0_writedata; // niosII_core_data_master_translator:uav_writedata -> niosII_core_data_master_agent:av_writedata
wire [5:0] niosii_core_data_master_translator_avalon_universal_master_0_burstcount; // niosII_core_data_master_translator:uav_burstcount -> niosII_core_data_master_agent:av_burstcount
wire niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest; // niosII_core_instruction_master_agent:av_waitrequest -> niosII_core_instruction_master_translator:uav_waitrequest
wire [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_readdata; // niosII_core_instruction_master_agent:av_readdata -> niosII_core_instruction_master_translator:uav_readdata
wire niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess; // niosII_core_instruction_master_translator:uav_debugaccess -> niosII_core_instruction_master_agent:av_debugaccess
wire [26:0] niosii_core_instruction_master_translator_avalon_universal_master_0_address; // niosII_core_instruction_master_translator:uav_address -> niosII_core_instruction_master_agent:av_address
wire niosii_core_instruction_master_translator_avalon_universal_master_0_read; // niosII_core_instruction_master_translator:uav_read -> niosII_core_instruction_master_agent:av_read
wire [3:0] niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable; // niosII_core_instruction_master_translator:uav_byteenable -> niosII_core_instruction_master_agent:av_byteenable
wire niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid; // niosII_core_instruction_master_agent:av_readdatavalid -> niosII_core_instruction_master_translator:uav_readdatavalid
wire niosii_core_instruction_master_translator_avalon_universal_master_0_lock; // niosII_core_instruction_master_translator:uav_lock -> niosII_core_instruction_master_agent:av_lock
wire niosii_core_instruction_master_translator_avalon_universal_master_0_write; // niosII_core_instruction_master_translator:uav_write -> niosII_core_instruction_master_agent:av_write
wire [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_writedata; // niosII_core_instruction_master_translator:uav_writedata -> niosII_core_instruction_master_agent:av_writedata
wire [5:0] niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount; // niosII_core_instruction_master_translator:uav_burstcount -> niosII_core_instruction_master_agent:av_burstcount
wire [31:0] jtag_avalon_jtag_slave_agent_m0_readdata; // JTAG_avalon_jtag_slave_translator:uav_readdata -> JTAG_avalon_jtag_slave_agent:m0_readdata
wire jtag_avalon_jtag_slave_agent_m0_waitrequest; // JTAG_avalon_jtag_slave_translator:uav_waitrequest -> JTAG_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_avalon_jtag_slave_agent_m0_debugaccess; // JTAG_avalon_jtag_slave_agent:m0_debugaccess -> JTAG_avalon_jtag_slave_translator:uav_debugaccess
wire [26:0] jtag_avalon_jtag_slave_agent_m0_address; // JTAG_avalon_jtag_slave_agent:m0_address -> JTAG_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_avalon_jtag_slave_agent_m0_byteenable; // JTAG_avalon_jtag_slave_agent:m0_byteenable -> JTAG_avalon_jtag_slave_translator:uav_byteenable
wire jtag_avalon_jtag_slave_agent_m0_read; // JTAG_avalon_jtag_slave_agent:m0_read -> JTAG_avalon_jtag_slave_translator:uav_read
wire jtag_avalon_jtag_slave_agent_m0_readdatavalid; // JTAG_avalon_jtag_slave_translator:uav_readdatavalid -> JTAG_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_avalon_jtag_slave_agent_m0_lock; // JTAG_avalon_jtag_slave_agent:m0_lock -> JTAG_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_avalon_jtag_slave_agent_m0_writedata; // JTAG_avalon_jtag_slave_agent:m0_writedata -> JTAG_avalon_jtag_slave_translator:uav_writedata
wire jtag_avalon_jtag_slave_agent_m0_write; // JTAG_avalon_jtag_slave_agent:m0_write -> JTAG_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_avalon_jtag_slave_agent_m0_burstcount; // JTAG_avalon_jtag_slave_agent:m0_burstcount -> JTAG_avalon_jtag_slave_translator:uav_burstcount
wire jtag_avalon_jtag_slave_agent_rf_source_valid; // JTAG_avalon_jtag_slave_agent:rf_source_valid -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [109:0] jtag_avalon_jtag_slave_agent_rf_source_data; // JTAG_avalon_jtag_slave_agent:rf_source_data -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rf_source_ready; // JTAG_avalon_jtag_slave_agent_rsp_fifo:in_ready -> JTAG_avalon_jtag_slave_agent:rf_source_ready
wire jtag_avalon_jtag_slave_agent_rf_source_startofpacket; // JTAG_avalon_jtag_slave_agent:rf_source_startofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_avalon_jtag_slave_agent_rf_source_endofpacket; // JTAG_avalon_jtag_slave_agent:rf_source_endofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_valid -> JTAG_avalon_jtag_slave_agent:rf_sink_valid
wire [109:0] jtag_avalon_jtag_slave_agent_rsp_fifo_out_data; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_data -> JTAG_avalon_jtag_slave_agent:rf_sink_data
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready; // JTAG_avalon_jtag_slave_agent:rf_sink_ready -> JTAG_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_endofpacket
wire [31:0] convolution_slave_avs_s0_agent_m0_readdata; // convolution_slave_avs_s0_translator:uav_readdata -> convolution_slave_avs_s0_agent:m0_readdata
wire convolution_slave_avs_s0_agent_m0_waitrequest; // convolution_slave_avs_s0_translator:uav_waitrequest -> convolution_slave_avs_s0_agent:m0_waitrequest
wire convolution_slave_avs_s0_agent_m0_debugaccess; // convolution_slave_avs_s0_agent:m0_debugaccess -> convolution_slave_avs_s0_translator:uav_debugaccess
wire [26:0] convolution_slave_avs_s0_agent_m0_address; // convolution_slave_avs_s0_agent:m0_address -> convolution_slave_avs_s0_translator:uav_address
wire [3:0] convolution_slave_avs_s0_agent_m0_byteenable; // convolution_slave_avs_s0_agent:m0_byteenable -> convolution_slave_avs_s0_translator:uav_byteenable
wire convolution_slave_avs_s0_agent_m0_read; // convolution_slave_avs_s0_agent:m0_read -> convolution_slave_avs_s0_translator:uav_read
wire convolution_slave_avs_s0_agent_m0_readdatavalid; // convolution_slave_avs_s0_translator:uav_readdatavalid -> convolution_slave_avs_s0_agent:m0_readdatavalid
wire convolution_slave_avs_s0_agent_m0_lock; // convolution_slave_avs_s0_agent:m0_lock -> convolution_slave_avs_s0_translator:uav_lock
wire [31:0] convolution_slave_avs_s0_agent_m0_writedata; // convolution_slave_avs_s0_agent:m0_writedata -> convolution_slave_avs_s0_translator:uav_writedata
wire convolution_slave_avs_s0_agent_m0_write; // convolution_slave_avs_s0_agent:m0_write -> convolution_slave_avs_s0_translator:uav_write
wire [2:0] convolution_slave_avs_s0_agent_m0_burstcount; // convolution_slave_avs_s0_agent:m0_burstcount -> convolution_slave_avs_s0_translator:uav_burstcount
wire convolution_slave_avs_s0_agent_rf_source_valid; // convolution_slave_avs_s0_agent:rf_source_valid -> convolution_slave_avs_s0_agent_rsp_fifo:in_valid
wire [109:0] convolution_slave_avs_s0_agent_rf_source_data; // convolution_slave_avs_s0_agent:rf_source_data -> convolution_slave_avs_s0_agent_rsp_fifo:in_data
wire convolution_slave_avs_s0_agent_rf_source_ready; // convolution_slave_avs_s0_agent_rsp_fifo:in_ready -> convolution_slave_avs_s0_agent:rf_source_ready
wire convolution_slave_avs_s0_agent_rf_source_startofpacket; // convolution_slave_avs_s0_agent:rf_source_startofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_startofpacket
wire convolution_slave_avs_s0_agent_rf_source_endofpacket; // convolution_slave_avs_s0_agent:rf_source_endofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_endofpacket
wire convolution_slave_avs_s0_agent_rsp_fifo_out_valid; // convolution_slave_avs_s0_agent_rsp_fifo:out_valid -> convolution_slave_avs_s0_agent:rf_sink_valid
wire [109:0] convolution_slave_avs_s0_agent_rsp_fifo_out_data; // convolution_slave_avs_s0_agent_rsp_fifo:out_data -> convolution_slave_avs_s0_agent:rf_sink_data
wire convolution_slave_avs_s0_agent_rsp_fifo_out_ready; // convolution_slave_avs_s0_agent:rf_sink_ready -> convolution_slave_avs_s0_agent_rsp_fifo:out_ready
wire convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket; // convolution_slave_avs_s0_agent_rsp_fifo:out_startofpacket -> convolution_slave_avs_s0_agent:rf_sink_startofpacket
wire convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket; // convolution_slave_avs_s0_agent_rsp_fifo:out_endofpacket -> convolution_slave_avs_s0_agent:rf_sink_endofpacket
wire [31:0] systemid_control_slave_agent_m0_readdata; // SystemID_control_slave_translator:uav_readdata -> SystemID_control_slave_agent:m0_readdata
wire systemid_control_slave_agent_m0_waitrequest; // SystemID_control_slave_translator:uav_waitrequest -> SystemID_control_slave_agent:m0_waitrequest
wire systemid_control_slave_agent_m0_debugaccess; // SystemID_control_slave_agent:m0_debugaccess -> SystemID_control_slave_translator:uav_debugaccess
wire [26:0] systemid_control_slave_agent_m0_address; // SystemID_control_slave_agent:m0_address -> SystemID_control_slave_translator:uav_address
wire [3:0] systemid_control_slave_agent_m0_byteenable; // SystemID_control_slave_agent:m0_byteenable -> SystemID_control_slave_translator:uav_byteenable
wire systemid_control_slave_agent_m0_read; // SystemID_control_slave_agent:m0_read -> SystemID_control_slave_translator:uav_read
wire systemid_control_slave_agent_m0_readdatavalid; // SystemID_control_slave_translator:uav_readdatavalid -> SystemID_control_slave_agent:m0_readdatavalid
wire systemid_control_slave_agent_m0_lock; // SystemID_control_slave_agent:m0_lock -> SystemID_control_slave_translator:uav_lock
wire [31:0] systemid_control_slave_agent_m0_writedata; // SystemID_control_slave_agent:m0_writedata -> SystemID_control_slave_translator:uav_writedata
wire systemid_control_slave_agent_m0_write; // SystemID_control_slave_agent:m0_write -> SystemID_control_slave_translator:uav_write
wire [2:0] systemid_control_slave_agent_m0_burstcount; // SystemID_control_slave_agent:m0_burstcount -> SystemID_control_slave_translator:uav_burstcount
wire systemid_control_slave_agent_rf_source_valid; // SystemID_control_slave_agent:rf_source_valid -> SystemID_control_slave_agent_rsp_fifo:in_valid
wire [109:0] systemid_control_slave_agent_rf_source_data; // SystemID_control_slave_agent:rf_source_data -> SystemID_control_slave_agent_rsp_fifo:in_data
wire systemid_control_slave_agent_rf_source_ready; // SystemID_control_slave_agent_rsp_fifo:in_ready -> SystemID_control_slave_agent:rf_source_ready
wire systemid_control_slave_agent_rf_source_startofpacket; // SystemID_control_slave_agent:rf_source_startofpacket -> SystemID_control_slave_agent_rsp_fifo:in_startofpacket
wire systemid_control_slave_agent_rf_source_endofpacket; // SystemID_control_slave_agent:rf_source_endofpacket -> SystemID_control_slave_agent_rsp_fifo:in_endofpacket
wire systemid_control_slave_agent_rsp_fifo_out_valid; // SystemID_control_slave_agent_rsp_fifo:out_valid -> SystemID_control_slave_agent:rf_sink_valid
wire [109:0] systemid_control_slave_agent_rsp_fifo_out_data; // SystemID_control_slave_agent_rsp_fifo:out_data -> SystemID_control_slave_agent:rf_sink_data
wire systemid_control_slave_agent_rsp_fifo_out_ready; // SystemID_control_slave_agent:rf_sink_ready -> SystemID_control_slave_agent_rsp_fifo:out_ready
wire systemid_control_slave_agent_rsp_fifo_out_startofpacket; // SystemID_control_slave_agent_rsp_fifo:out_startofpacket -> SystemID_control_slave_agent:rf_sink_startofpacket
wire systemid_control_slave_agent_rsp_fifo_out_endofpacket; // SystemID_control_slave_agent_rsp_fifo:out_endofpacket -> SystemID_control_slave_agent:rf_sink_endofpacket
wire [31:0] niosii_core_debug_mem_slave_agent_m0_readdata; // niosII_core_debug_mem_slave_translator:uav_readdata -> niosII_core_debug_mem_slave_agent:m0_readdata
wire niosii_core_debug_mem_slave_agent_m0_waitrequest; // niosII_core_debug_mem_slave_translator:uav_waitrequest -> niosII_core_debug_mem_slave_agent:m0_waitrequest
wire niosii_core_debug_mem_slave_agent_m0_debugaccess; // niosII_core_debug_mem_slave_agent:m0_debugaccess -> niosII_core_debug_mem_slave_translator:uav_debugaccess
wire [26:0] niosii_core_debug_mem_slave_agent_m0_address; // niosII_core_debug_mem_slave_agent:m0_address -> niosII_core_debug_mem_slave_translator:uav_address
wire [3:0] niosii_core_debug_mem_slave_agent_m0_byteenable; // niosII_core_debug_mem_slave_agent:m0_byteenable -> niosII_core_debug_mem_slave_translator:uav_byteenable
wire niosii_core_debug_mem_slave_agent_m0_read; // niosII_core_debug_mem_slave_agent:m0_read -> niosII_core_debug_mem_slave_translator:uav_read
wire niosii_core_debug_mem_slave_agent_m0_readdatavalid; // niosII_core_debug_mem_slave_translator:uav_readdatavalid -> niosII_core_debug_mem_slave_agent:m0_readdatavalid
wire niosii_core_debug_mem_slave_agent_m0_lock; // niosII_core_debug_mem_slave_agent:m0_lock -> niosII_core_debug_mem_slave_translator:uav_lock
wire [31:0] niosii_core_debug_mem_slave_agent_m0_writedata; // niosII_core_debug_mem_slave_agent:m0_writedata -> niosII_core_debug_mem_slave_translator:uav_writedata
wire niosii_core_debug_mem_slave_agent_m0_write; // niosII_core_debug_mem_slave_agent:m0_write -> niosII_core_debug_mem_slave_translator:uav_write
wire [2:0] niosii_core_debug_mem_slave_agent_m0_burstcount; // niosII_core_debug_mem_slave_agent:m0_burstcount -> niosII_core_debug_mem_slave_translator:uav_burstcount
wire niosii_core_debug_mem_slave_agent_rf_source_valid; // niosII_core_debug_mem_slave_agent:rf_source_valid -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_valid
wire [109:0] niosii_core_debug_mem_slave_agent_rf_source_data; // niosII_core_debug_mem_slave_agent:rf_source_data -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_data
wire niosii_core_debug_mem_slave_agent_rf_source_ready; // niosII_core_debug_mem_slave_agent_rsp_fifo:in_ready -> niosII_core_debug_mem_slave_agent:rf_source_ready
wire niosii_core_debug_mem_slave_agent_rf_source_startofpacket; // niosII_core_debug_mem_slave_agent:rf_source_startofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire niosii_core_debug_mem_slave_agent_rf_source_endofpacket; // niosII_core_debug_mem_slave_agent:rf_source_endofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_valid -> niosII_core_debug_mem_slave_agent:rf_sink_valid
wire [109:0] niosii_core_debug_mem_slave_agent_rsp_fifo_out_data; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_data -> niosII_core_debug_mem_slave_agent:rf_sink_data
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready; // niosII_core_debug_mem_slave_agent:rf_sink_ready -> niosII_core_debug_mem_slave_agent_rsp_fifo:out_ready
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_startofpacket
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_endofpacket
wire [31:0] sram_s1_agent_m0_readdata; // SRAM_s1_translator:uav_readdata -> SRAM_s1_agent:m0_readdata
wire sram_s1_agent_m0_waitrequest; // SRAM_s1_translator:uav_waitrequest -> SRAM_s1_agent:m0_waitrequest
wire sram_s1_agent_m0_debugaccess; // SRAM_s1_agent:m0_debugaccess -> SRAM_s1_translator:uav_debugaccess
wire [26:0] sram_s1_agent_m0_address; // SRAM_s1_agent:m0_address -> SRAM_s1_translator:uav_address
wire [3:0] sram_s1_agent_m0_byteenable; // SRAM_s1_agent:m0_byteenable -> SRAM_s1_translator:uav_byteenable
wire sram_s1_agent_m0_read; // SRAM_s1_agent:m0_read -> SRAM_s1_translator:uav_read
wire sram_s1_agent_m0_readdatavalid; // SRAM_s1_translator:uav_readdatavalid -> SRAM_s1_agent:m0_readdatavalid
wire sram_s1_agent_m0_lock; // SRAM_s1_agent:m0_lock -> SRAM_s1_translator:uav_lock
wire [31:0] sram_s1_agent_m0_writedata; // SRAM_s1_agent:m0_writedata -> SRAM_s1_translator:uav_writedata
wire sram_s1_agent_m0_write; // SRAM_s1_agent:m0_write -> SRAM_s1_translator:uav_write
wire [2:0] sram_s1_agent_m0_burstcount; // SRAM_s1_agent:m0_burstcount -> SRAM_s1_translator:uav_burstcount
wire sram_s1_agent_rf_source_valid; // SRAM_s1_agent:rf_source_valid -> SRAM_s1_agent_rsp_fifo:in_valid
wire [109:0] sram_s1_agent_rf_source_data; // SRAM_s1_agent:rf_source_data -> SRAM_s1_agent_rsp_fifo:in_data
wire sram_s1_agent_rf_source_ready; // SRAM_s1_agent_rsp_fifo:in_ready -> SRAM_s1_agent:rf_source_ready
wire sram_s1_agent_rf_source_startofpacket; // SRAM_s1_agent:rf_source_startofpacket -> SRAM_s1_agent_rsp_fifo:in_startofpacket
wire sram_s1_agent_rf_source_endofpacket; // SRAM_s1_agent:rf_source_endofpacket -> SRAM_s1_agent_rsp_fifo:in_endofpacket
wire sram_s1_agent_rsp_fifo_out_valid; // SRAM_s1_agent_rsp_fifo:out_valid -> SRAM_s1_agent:rf_sink_valid
wire [109:0] sram_s1_agent_rsp_fifo_out_data; // SRAM_s1_agent_rsp_fifo:out_data -> SRAM_s1_agent:rf_sink_data
wire sram_s1_agent_rsp_fifo_out_ready; // SRAM_s1_agent:rf_sink_ready -> SRAM_s1_agent_rsp_fifo:out_ready
wire sram_s1_agent_rsp_fifo_out_startofpacket; // SRAM_s1_agent_rsp_fifo:out_startofpacket -> SRAM_s1_agent:rf_sink_startofpacket
wire sram_s1_agent_rsp_fifo_out_endofpacket; // SRAM_s1_agent_rsp_fifo:out_endofpacket -> SRAM_s1_agent:rf_sink_endofpacket
wire [31:0] sys_timer_s1_agent_m0_readdata; // Sys_Timer_s1_translator:uav_readdata -> Sys_Timer_s1_agent:m0_readdata
wire sys_timer_s1_agent_m0_waitrequest; // Sys_Timer_s1_translator:uav_waitrequest -> Sys_Timer_s1_agent:m0_waitrequest
wire sys_timer_s1_agent_m0_debugaccess; // Sys_Timer_s1_agent:m0_debugaccess -> Sys_Timer_s1_translator:uav_debugaccess
wire [26:0] sys_timer_s1_agent_m0_address; // Sys_Timer_s1_agent:m0_address -> Sys_Timer_s1_translator:uav_address
wire [3:0] sys_timer_s1_agent_m0_byteenable; // Sys_Timer_s1_agent:m0_byteenable -> Sys_Timer_s1_translator:uav_byteenable
wire sys_timer_s1_agent_m0_read; // Sys_Timer_s1_agent:m0_read -> Sys_Timer_s1_translator:uav_read
wire sys_timer_s1_agent_m0_readdatavalid; // Sys_Timer_s1_translator:uav_readdatavalid -> Sys_Timer_s1_agent:m0_readdatavalid
wire sys_timer_s1_agent_m0_lock; // Sys_Timer_s1_agent:m0_lock -> Sys_Timer_s1_translator:uav_lock
wire [31:0] sys_timer_s1_agent_m0_writedata; // Sys_Timer_s1_agent:m0_writedata -> Sys_Timer_s1_translator:uav_writedata
wire sys_timer_s1_agent_m0_write; // Sys_Timer_s1_agent:m0_write -> Sys_Timer_s1_translator:uav_write
wire [2:0] sys_timer_s1_agent_m0_burstcount; // Sys_Timer_s1_agent:m0_burstcount -> Sys_Timer_s1_translator:uav_burstcount
wire sys_timer_s1_agent_rf_source_valid; // Sys_Timer_s1_agent:rf_source_valid -> Sys_Timer_s1_agent_rsp_fifo:in_valid
wire [109:0] sys_timer_s1_agent_rf_source_data; // Sys_Timer_s1_agent:rf_source_data -> Sys_Timer_s1_agent_rsp_fifo:in_data
wire sys_timer_s1_agent_rf_source_ready; // Sys_Timer_s1_agent_rsp_fifo:in_ready -> Sys_Timer_s1_agent:rf_source_ready
wire sys_timer_s1_agent_rf_source_startofpacket; // Sys_Timer_s1_agent:rf_source_startofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_startofpacket
wire sys_timer_s1_agent_rf_source_endofpacket; // Sys_Timer_s1_agent:rf_source_endofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_endofpacket
wire sys_timer_s1_agent_rsp_fifo_out_valid; // Sys_Timer_s1_agent_rsp_fifo:out_valid -> Sys_Timer_s1_agent:rf_sink_valid
wire [109:0] sys_timer_s1_agent_rsp_fifo_out_data; // Sys_Timer_s1_agent_rsp_fifo:out_data -> Sys_Timer_s1_agent:rf_sink_data
wire sys_timer_s1_agent_rsp_fifo_out_ready; // Sys_Timer_s1_agent:rf_sink_ready -> Sys_Timer_s1_agent_rsp_fifo:out_ready
wire sys_timer_s1_agent_rsp_fifo_out_startofpacket; // Sys_Timer_s1_agent_rsp_fifo:out_startofpacket -> Sys_Timer_s1_agent:rf_sink_startofpacket
wire sys_timer_s1_agent_rsp_fifo_out_endofpacket; // Sys_Timer_s1_agent_rsp_fifo:out_endofpacket -> Sys_Timer_s1_agent:rf_sink_endofpacket
wire [15:0] sdram_s1_agent_m0_readdata; // SDRAM_s1_translator:uav_readdata -> SDRAM_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // SDRAM_s1_translator:uav_waitrequest -> SDRAM_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // SDRAM_s1_agent:m0_debugaccess -> SDRAM_s1_translator:uav_debugaccess
wire [26:0] sdram_s1_agent_m0_address; // SDRAM_s1_agent:m0_address -> SDRAM_s1_translator:uav_address
wire [1:0] sdram_s1_agent_m0_byteenable; // SDRAM_s1_agent:m0_byteenable -> SDRAM_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // SDRAM_s1_agent:m0_read -> SDRAM_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // SDRAM_s1_translator:uav_readdatavalid -> SDRAM_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // SDRAM_s1_agent:m0_lock -> SDRAM_s1_translator:uav_lock
wire [15:0] sdram_s1_agent_m0_writedata; // SDRAM_s1_agent:m0_writedata -> SDRAM_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // SDRAM_s1_agent:m0_write -> SDRAM_s1_translator:uav_write
wire [1:0] sdram_s1_agent_m0_burstcount; // SDRAM_s1_agent:m0_burstcount -> SDRAM_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // SDRAM_s1_agent:rf_source_valid -> SDRAM_s1_agent_rsp_fifo:in_valid
wire [91:0] sdram_s1_agent_rf_source_data; // SDRAM_s1_agent:rf_source_data -> SDRAM_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // SDRAM_s1_agent_rsp_fifo:in_ready -> SDRAM_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // SDRAM_s1_agent:rf_source_startofpacket -> SDRAM_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // SDRAM_s1_agent:rf_source_endofpacket -> SDRAM_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // SDRAM_s1_agent_rsp_fifo:out_valid -> SDRAM_s1_agent:rf_sink_valid
wire [91:0] sdram_s1_agent_rsp_fifo_out_data; // SDRAM_s1_agent_rsp_fifo:out_data -> SDRAM_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // SDRAM_s1_agent:rf_sink_ready -> SDRAM_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // SDRAM_s1_agent_rsp_fifo:out_startofpacket -> SDRAM_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // SDRAM_s1_agent_rsp_fifo:out_endofpacket -> SDRAM_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // SDRAM_s1_agent:rdata_fifo_src_valid -> SDRAM_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_s1_agent_rdata_fifo_src_data; // SDRAM_s1_agent:rdata_fifo_src_data -> SDRAM_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // SDRAM_s1_agent_rdata_fifo:in_ready -> SDRAM_s1_agent:rdata_fifo_src_ready
wire niosii_core_data_master_agent_cp_valid; // niosII_core_data_master_agent:cp_valid -> router:sink_valid
wire [108:0] niosii_core_data_master_agent_cp_data; // niosII_core_data_master_agent:cp_data -> router:sink_data
wire niosii_core_data_master_agent_cp_ready; // router:sink_ready -> niosII_core_data_master_agent:cp_ready
wire niosii_core_data_master_agent_cp_startofpacket; // niosII_core_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire niosii_core_data_master_agent_cp_endofpacket; // niosII_core_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire niosii_core_instruction_master_agent_cp_valid; // niosII_core_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [108:0] niosii_core_instruction_master_agent_cp_data; // niosII_core_instruction_master_agent:cp_data -> router_001:sink_data
wire niosii_core_instruction_master_agent_cp_ready; // router_001:sink_ready -> niosII_core_instruction_master_agent:cp_ready
wire niosii_core_instruction_master_agent_cp_startofpacket; // niosII_core_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire niosii_core_instruction_master_agent_cp_endofpacket; // niosII_core_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rp_valid; // JTAG_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [108:0] jtag_avalon_jtag_slave_agent_rp_data; // JTAG_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> JTAG_avalon_jtag_slave_agent:rp_ready
wire jtag_avalon_jtag_slave_agent_rp_startofpacket; // JTAG_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rp_endofpacket; // JTAG_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [108:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [6:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire convolution_slave_avs_s0_agent_rp_valid; // convolution_slave_avs_s0_agent:rp_valid -> router_003:sink_valid
wire [108:0] convolution_slave_avs_s0_agent_rp_data; // convolution_slave_avs_s0_agent:rp_data -> router_003:sink_data
wire convolution_slave_avs_s0_agent_rp_ready; // router_003:sink_ready -> convolution_slave_avs_s0_agent:rp_ready
wire convolution_slave_avs_s0_agent_rp_startofpacket; // convolution_slave_avs_s0_agent:rp_startofpacket -> router_003:sink_startofpacket
wire convolution_slave_avs_s0_agent_rp_endofpacket; // convolution_slave_avs_s0_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [108:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [6:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire systemid_control_slave_agent_rp_valid; // SystemID_control_slave_agent:rp_valid -> router_004:sink_valid
wire [108:0] systemid_control_slave_agent_rp_data; // SystemID_control_slave_agent:rp_data -> router_004:sink_data
wire systemid_control_slave_agent_rp_ready; // router_004:sink_ready -> SystemID_control_slave_agent:rp_ready
wire systemid_control_slave_agent_rp_startofpacket; // SystemID_control_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire systemid_control_slave_agent_rp_endofpacket; // SystemID_control_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [108:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [6:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire niosii_core_debug_mem_slave_agent_rp_valid; // niosII_core_debug_mem_slave_agent:rp_valid -> router_005:sink_valid
wire [108:0] niosii_core_debug_mem_slave_agent_rp_data; // niosII_core_debug_mem_slave_agent:rp_data -> router_005:sink_data
wire niosii_core_debug_mem_slave_agent_rp_ready; // router_005:sink_ready -> niosII_core_debug_mem_slave_agent:rp_ready
wire niosii_core_debug_mem_slave_agent_rp_startofpacket; // niosII_core_debug_mem_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire niosii_core_debug_mem_slave_agent_rp_endofpacket; // niosII_core_debug_mem_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [108:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire sram_s1_agent_rp_valid; // SRAM_s1_agent:rp_valid -> router_006:sink_valid
wire [108:0] sram_s1_agent_rp_data; // SRAM_s1_agent:rp_data -> router_006:sink_data
wire sram_s1_agent_rp_ready; // router_006:sink_ready -> SRAM_s1_agent:rp_ready
wire sram_s1_agent_rp_startofpacket; // SRAM_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sram_s1_agent_rp_endofpacket; // SRAM_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [108:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sys_timer_s1_agent_rp_valid; // Sys_Timer_s1_agent:rp_valid -> router_007:sink_valid
wire [108:0] sys_timer_s1_agent_rp_data; // Sys_Timer_s1_agent:rp_data -> router_007:sink_data
wire sys_timer_s1_agent_rp_ready; // router_007:sink_ready -> Sys_Timer_s1_agent:rp_ready
wire sys_timer_s1_agent_rp_startofpacket; // Sys_Timer_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sys_timer_s1_agent_rp_endofpacket; // Sys_Timer_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [108:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire sdram_s1_agent_rp_valid; // SDRAM_s1_agent:rp_valid -> router_008:sink_valid
wire [90:0] sdram_s1_agent_rp_data; // SDRAM_s1_agent:rp_data -> router_008:sink_data
wire sdram_s1_agent_rp_ready; // router_008:sink_ready -> SDRAM_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // SDRAM_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // SDRAM_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_src_valid; // router:src_valid -> niosII_core_data_master_limiter:cmd_sink_valid
wire [108:0] router_src_data; // router:src_data -> niosII_core_data_master_limiter:cmd_sink_data
wire router_src_ready; // niosII_core_data_master_limiter:cmd_sink_ready -> router:src_ready
wire [6:0] router_src_channel; // router:src_channel -> niosII_core_data_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> niosII_core_data_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> niosII_core_data_master_limiter:cmd_sink_endofpacket
wire [108:0] niosii_core_data_master_limiter_cmd_src_data; // niosII_core_data_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire niosii_core_data_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> niosII_core_data_master_limiter:cmd_src_ready
wire [6:0] niosii_core_data_master_limiter_cmd_src_channel; // niosII_core_data_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire niosii_core_data_master_limiter_cmd_src_startofpacket; // niosII_core_data_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire niosii_core_data_master_limiter_cmd_src_endofpacket; // niosII_core_data_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> niosII_core_data_master_limiter:rsp_sink_valid
wire [108:0] rsp_mux_src_data; // rsp_mux:src_data -> niosII_core_data_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // niosII_core_data_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> niosII_core_data_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> niosII_core_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> niosII_core_data_master_limiter:rsp_sink_endofpacket
wire niosii_core_data_master_limiter_rsp_src_valid; // niosII_core_data_master_limiter:rsp_src_valid -> niosII_core_data_master_agent:rp_valid
wire [108:0] niosii_core_data_master_limiter_rsp_src_data; // niosII_core_data_master_limiter:rsp_src_data -> niosII_core_data_master_agent:rp_data
wire niosii_core_data_master_limiter_rsp_src_ready; // niosII_core_data_master_agent:rp_ready -> niosII_core_data_master_limiter:rsp_src_ready
wire [6:0] niosii_core_data_master_limiter_rsp_src_channel; // niosII_core_data_master_limiter:rsp_src_channel -> niosII_core_data_master_agent:rp_channel
wire niosii_core_data_master_limiter_rsp_src_startofpacket; // niosII_core_data_master_limiter:rsp_src_startofpacket -> niosII_core_data_master_agent:rp_startofpacket
wire niosii_core_data_master_limiter_rsp_src_endofpacket; // niosII_core_data_master_limiter:rsp_src_endofpacket -> niosII_core_data_master_agent:rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> niosII_core_instruction_master_limiter:cmd_sink_valid
wire [108:0] router_001_src_data; // router_001:src_data -> niosII_core_instruction_master_limiter:cmd_sink_data
wire router_001_src_ready; // niosII_core_instruction_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [6:0] router_001_src_channel; // router_001:src_channel -> niosII_core_instruction_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> niosII_core_instruction_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> niosII_core_instruction_master_limiter:cmd_sink_endofpacket
wire [108:0] niosii_core_instruction_master_limiter_cmd_src_data; // niosII_core_instruction_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire niosii_core_instruction_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> niosII_core_instruction_master_limiter:cmd_src_ready
wire [6:0] niosii_core_instruction_master_limiter_cmd_src_channel; // niosII_core_instruction_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire niosii_core_instruction_master_limiter_cmd_src_startofpacket; // niosII_core_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire niosii_core_instruction_master_limiter_cmd_src_endofpacket; // niosII_core_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> niosII_core_instruction_master_limiter:rsp_sink_valid
wire [108:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> niosII_core_instruction_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // niosII_core_instruction_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [6:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> niosII_core_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> niosII_core_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> niosII_core_instruction_master_limiter:rsp_sink_endofpacket
wire niosii_core_instruction_master_limiter_rsp_src_valid; // niosII_core_instruction_master_limiter:rsp_src_valid -> niosII_core_instruction_master_agent:rp_valid
wire [108:0] niosii_core_instruction_master_limiter_rsp_src_data; // niosII_core_instruction_master_limiter:rsp_src_data -> niosII_core_instruction_master_agent:rp_data
wire niosii_core_instruction_master_limiter_rsp_src_ready; // niosII_core_instruction_master_agent:rp_ready -> niosII_core_instruction_master_limiter:rsp_src_ready
wire [6:0] niosii_core_instruction_master_limiter_rsp_src_channel; // niosII_core_instruction_master_limiter:rsp_src_channel -> niosII_core_instruction_master_agent:rp_channel
wire niosii_core_instruction_master_limiter_rsp_src_startofpacket; // niosII_core_instruction_master_limiter:rsp_src_startofpacket -> niosII_core_instruction_master_agent:rp_startofpacket
wire niosii_core_instruction_master_limiter_rsp_src_endofpacket; // niosII_core_instruction_master_limiter:rsp_src_endofpacket -> niosII_core_instruction_master_agent:rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> JTAG_avalon_jtag_slave_burst_adapter:sink0_valid
wire [108:0] cmd_mux_src_data; // cmd_mux:src_data -> JTAG_avalon_jtag_slave_burst_adapter:sink0_data
wire cmd_mux_src_ready; // JTAG_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> JTAG_avalon_jtag_slave_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_endofpacket
wire jtag_avalon_jtag_slave_burst_adapter_source0_valid; // JTAG_avalon_jtag_slave_burst_adapter:source0_valid -> JTAG_avalon_jtag_slave_agent:cp_valid
wire [108:0] jtag_avalon_jtag_slave_burst_adapter_source0_data; // JTAG_avalon_jtag_slave_burst_adapter:source0_data -> JTAG_avalon_jtag_slave_agent:cp_data
wire jtag_avalon_jtag_slave_burst_adapter_source0_ready; // JTAG_avalon_jtag_slave_agent:cp_ready -> JTAG_avalon_jtag_slave_burst_adapter:source0_ready
wire [6:0] jtag_avalon_jtag_slave_burst_adapter_source0_channel; // JTAG_avalon_jtag_slave_burst_adapter:source0_channel -> JTAG_avalon_jtag_slave_agent:cp_channel
wire jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket; // JTAG_avalon_jtag_slave_burst_adapter:source0_startofpacket -> JTAG_avalon_jtag_slave_agent:cp_startofpacket
wire jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket; // JTAG_avalon_jtag_slave_burst_adapter:source0_endofpacket -> JTAG_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> convolution_slave_avs_s0_burst_adapter:sink0_valid
wire [108:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> convolution_slave_avs_s0_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // convolution_slave_avs_s0_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> convolution_slave_avs_s0_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_endofpacket
wire convolution_slave_avs_s0_burst_adapter_source0_valid; // convolution_slave_avs_s0_burst_adapter:source0_valid -> convolution_slave_avs_s0_agent:cp_valid
wire [108:0] convolution_slave_avs_s0_burst_adapter_source0_data; // convolution_slave_avs_s0_burst_adapter:source0_data -> convolution_slave_avs_s0_agent:cp_data
wire convolution_slave_avs_s0_burst_adapter_source0_ready; // convolution_slave_avs_s0_agent:cp_ready -> convolution_slave_avs_s0_burst_adapter:source0_ready
wire [6:0] convolution_slave_avs_s0_burst_adapter_source0_channel; // convolution_slave_avs_s0_burst_adapter:source0_channel -> convolution_slave_avs_s0_agent:cp_channel
wire convolution_slave_avs_s0_burst_adapter_source0_startofpacket; // convolution_slave_avs_s0_burst_adapter:source0_startofpacket -> convolution_slave_avs_s0_agent:cp_startofpacket
wire convolution_slave_avs_s0_burst_adapter_source0_endofpacket; // convolution_slave_avs_s0_burst_adapter:source0_endofpacket -> convolution_slave_avs_s0_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> SystemID_control_slave_burst_adapter:sink0_valid
wire [108:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> SystemID_control_slave_burst_adapter:sink0_data
wire cmd_mux_002_src_ready; // SystemID_control_slave_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> SystemID_control_slave_burst_adapter:sink0_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> SystemID_control_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> SystemID_control_slave_burst_adapter:sink0_endofpacket
wire systemid_control_slave_burst_adapter_source0_valid; // SystemID_control_slave_burst_adapter:source0_valid -> SystemID_control_slave_agent:cp_valid
wire [108:0] systemid_control_slave_burst_adapter_source0_data; // SystemID_control_slave_burst_adapter:source0_data -> SystemID_control_slave_agent:cp_data
wire systemid_control_slave_burst_adapter_source0_ready; // SystemID_control_slave_agent:cp_ready -> SystemID_control_slave_burst_adapter:source0_ready
wire [6:0] systemid_control_slave_burst_adapter_source0_channel; // SystemID_control_slave_burst_adapter:source0_channel -> SystemID_control_slave_agent:cp_channel
wire systemid_control_slave_burst_adapter_source0_startofpacket; // SystemID_control_slave_burst_adapter:source0_startofpacket -> SystemID_control_slave_agent:cp_startofpacket
wire systemid_control_slave_burst_adapter_source0_endofpacket; // SystemID_control_slave_burst_adapter:source0_endofpacket -> SystemID_control_slave_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> niosII_core_debug_mem_slave_burst_adapter:sink0_valid
wire [108:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> niosII_core_debug_mem_slave_burst_adapter:sink0_data
wire cmd_mux_003_src_ready; // niosII_core_debug_mem_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> niosII_core_debug_mem_slave_burst_adapter:sink0_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_endofpacket
wire niosii_core_debug_mem_slave_burst_adapter_source0_valid; // niosII_core_debug_mem_slave_burst_adapter:source0_valid -> niosII_core_debug_mem_slave_agent:cp_valid
wire [108:0] niosii_core_debug_mem_slave_burst_adapter_source0_data; // niosII_core_debug_mem_slave_burst_adapter:source0_data -> niosII_core_debug_mem_slave_agent:cp_data
wire niosii_core_debug_mem_slave_burst_adapter_source0_ready; // niosII_core_debug_mem_slave_agent:cp_ready -> niosII_core_debug_mem_slave_burst_adapter:source0_ready
wire [6:0] niosii_core_debug_mem_slave_burst_adapter_source0_channel; // niosII_core_debug_mem_slave_burst_adapter:source0_channel -> niosII_core_debug_mem_slave_agent:cp_channel
wire niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket; // niosII_core_debug_mem_slave_burst_adapter:source0_startofpacket -> niosII_core_debug_mem_slave_agent:cp_startofpacket
wire niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket; // niosII_core_debug_mem_slave_burst_adapter:source0_endofpacket -> niosII_core_debug_mem_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> SRAM_s1_burst_adapter:sink0_valid
wire [108:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> SRAM_s1_burst_adapter:sink0_data
wire cmd_mux_004_src_ready; // SRAM_s1_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> SRAM_s1_burst_adapter:sink0_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> SRAM_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> SRAM_s1_burst_adapter:sink0_endofpacket
wire sram_s1_burst_adapter_source0_valid; // SRAM_s1_burst_adapter:source0_valid -> SRAM_s1_agent:cp_valid
wire [108:0] sram_s1_burst_adapter_source0_data; // SRAM_s1_burst_adapter:source0_data -> SRAM_s1_agent:cp_data
wire sram_s1_burst_adapter_source0_ready; // SRAM_s1_agent:cp_ready -> SRAM_s1_burst_adapter:source0_ready
wire [6:0] sram_s1_burst_adapter_source0_channel; // SRAM_s1_burst_adapter:source0_channel -> SRAM_s1_agent:cp_channel
wire sram_s1_burst_adapter_source0_startofpacket; // SRAM_s1_burst_adapter:source0_startofpacket -> SRAM_s1_agent:cp_startofpacket
wire sram_s1_burst_adapter_source0_endofpacket; // SRAM_s1_burst_adapter:source0_endofpacket -> SRAM_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> Sys_Timer_s1_burst_adapter:sink0_valid
wire [108:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> Sys_Timer_s1_burst_adapter:sink0_data
wire cmd_mux_005_src_ready; // Sys_Timer_s1_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> Sys_Timer_s1_burst_adapter:sink0_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> Sys_Timer_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> Sys_Timer_s1_burst_adapter:sink0_endofpacket
wire sys_timer_s1_burst_adapter_source0_valid; // Sys_Timer_s1_burst_adapter:source0_valid -> Sys_Timer_s1_agent:cp_valid
wire [108:0] sys_timer_s1_burst_adapter_source0_data; // Sys_Timer_s1_burst_adapter:source0_data -> Sys_Timer_s1_agent:cp_data
wire sys_timer_s1_burst_adapter_source0_ready; // Sys_Timer_s1_agent:cp_ready -> Sys_Timer_s1_burst_adapter:source0_ready
wire [6:0] sys_timer_s1_burst_adapter_source0_channel; // Sys_Timer_s1_burst_adapter:source0_channel -> Sys_Timer_s1_agent:cp_channel
wire sys_timer_s1_burst_adapter_source0_startofpacket; // Sys_Timer_s1_burst_adapter:source0_startofpacket -> Sys_Timer_s1_agent:cp_startofpacket
wire sys_timer_s1_burst_adapter_source0_endofpacket; // Sys_Timer_s1_burst_adapter:source0_endofpacket -> Sys_Timer_s1_agent:cp_endofpacket
wire sdram_s1_burst_adapter_source0_valid; // SDRAM_s1_burst_adapter:source0_valid -> SDRAM_s1_agent:cp_valid
wire [90:0] sdram_s1_burst_adapter_source0_data; // SDRAM_s1_burst_adapter:source0_data -> SDRAM_s1_agent:cp_data
wire sdram_s1_burst_adapter_source0_ready; // SDRAM_s1_agent:cp_ready -> SDRAM_s1_burst_adapter:source0_ready
wire [6:0] sdram_s1_burst_adapter_source0_channel; // SDRAM_s1_burst_adapter:source0_channel -> SDRAM_s1_agent:cp_channel
wire sdram_s1_burst_adapter_source0_startofpacket; // SDRAM_s1_burst_adapter:source0_startofpacket -> SDRAM_s1_agent:cp_startofpacket
wire sdram_s1_burst_adapter_source0_endofpacket; // SDRAM_s1_burst_adapter:source0_endofpacket -> SDRAM_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [108:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [108:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [108:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [108:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [108:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [108:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [108:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_003:sink1_valid
wire [108:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src0_ready
wire [6:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_004:sink1_valid
wire [108:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_004:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_004:sink1_ready -> cmd_demux_001:src1_ready
wire [6:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_004:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_004:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_004:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_006:sink1_valid
wire [108:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_006:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_006:sink1_ready -> cmd_demux_001:src2_ready
wire [6:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_006:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [108:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [108:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [108:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [108:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink0_valid
wire [108:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_003:src1_ready
wire [6:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [108:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_001:sink1_valid
wire [108:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_004_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_004:src1_ready
wire [6:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [108:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [108:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_001:sink2_valid
wire [108:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_006_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_006:src1_ready
wire [6:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_008_src_valid; // router_008:src_valid -> SDRAM_s1_rsp_width_adapter:in_valid
wire [90:0] router_008_src_data; // router_008:src_data -> SDRAM_s1_rsp_width_adapter:in_data
wire router_008_src_ready; // SDRAM_s1_rsp_width_adapter:in_ready -> router_008:src_ready
wire [6:0] router_008_src_channel; // router_008:src_channel -> SDRAM_s1_rsp_width_adapter:in_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> SDRAM_s1_rsp_width_adapter:in_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> SDRAM_s1_rsp_width_adapter:in_endofpacket
wire sdram_s1_rsp_width_adapter_src_valid; // SDRAM_s1_rsp_width_adapter:out_valid -> rsp_demux_006:sink_valid
wire [108:0] sdram_s1_rsp_width_adapter_src_data; // SDRAM_s1_rsp_width_adapter:out_data -> rsp_demux_006:sink_data
wire sdram_s1_rsp_width_adapter_src_ready; // rsp_demux_006:sink_ready -> SDRAM_s1_rsp_width_adapter:out_ready
wire [6:0] sdram_s1_rsp_width_adapter_src_channel; // SDRAM_s1_rsp_width_adapter:out_channel -> rsp_demux_006:sink_channel
wire sdram_s1_rsp_width_adapter_src_startofpacket; // SDRAM_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_006:sink_startofpacket
wire sdram_s1_rsp_width_adapter_src_endofpacket; // SDRAM_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_006:sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> SDRAM_s1_cmd_width_adapter:in_valid
wire [108:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> SDRAM_s1_cmd_width_adapter:in_data
wire cmd_mux_006_src_ready; // SDRAM_s1_cmd_width_adapter:in_ready -> cmd_mux_006:src_ready
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> SDRAM_s1_cmd_width_adapter:in_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> SDRAM_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> SDRAM_s1_cmd_width_adapter:in_endofpacket
wire sdram_s1_cmd_width_adapter_src_valid; // SDRAM_s1_cmd_width_adapter:out_valid -> SDRAM_s1_burst_adapter:sink0_valid
wire [90:0] sdram_s1_cmd_width_adapter_src_data; // SDRAM_s1_cmd_width_adapter:out_data -> SDRAM_s1_burst_adapter:sink0_data
wire sdram_s1_cmd_width_adapter_src_ready; // SDRAM_s1_burst_adapter:sink0_ready -> SDRAM_s1_cmd_width_adapter:out_ready
wire [6:0] sdram_s1_cmd_width_adapter_src_channel; // SDRAM_s1_cmd_width_adapter:out_channel -> SDRAM_s1_burst_adapter:sink0_channel
wire sdram_s1_cmd_width_adapter_src_startofpacket; // SDRAM_s1_cmd_width_adapter:out_startofpacket -> SDRAM_s1_burst_adapter:sink0_startofpacket
wire sdram_s1_cmd_width_adapter_src_endofpacket; // SDRAM_s1_cmd_width_adapter:out_endofpacket -> SDRAM_s1_burst_adapter:sink0_endofpacket
wire [6:0] niosii_core_data_master_limiter_cmd_valid_data; // niosII_core_data_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [6:0] niosii_core_instruction_master_limiter_cmd_valid_data; // niosII_core_instruction_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid; // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_src_data; // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> JTAG_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire convolution_slave_avs_s0_agent_rdata_fifo_src_valid; // convolution_slave_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] convolution_slave_avs_s0_agent_rdata_fifo_src_data; // convolution_slave_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire convolution_slave_avs_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> convolution_slave_avs_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> convolution_slave_avs_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> convolution_slave_avs_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // convolution_slave_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> convolution_slave_avs_s0_agent:rdata_fifo_sink_error
wire systemid_control_slave_agent_rdata_fifo_src_valid; // SystemID_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] systemid_control_slave_agent_rdata_fifo_src_data; // SystemID_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire systemid_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> SystemID_control_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> SystemID_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> SystemID_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // SystemID_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> SystemID_control_slave_agent:rdata_fifo_sink_error
wire niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid; // niosII_core_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] niosii_core_debug_mem_slave_agent_rdata_fifo_src_data; // niosII_core_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> niosII_core_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // niosII_core_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_error
wire sram_s1_agent_rdata_fifo_src_valid; // SRAM_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] sram_s1_agent_rdata_fifo_src_data; // SRAM_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire sram_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> SRAM_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> SRAM_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> SRAM_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // SRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> SRAM_s1_agent:rdata_fifo_sink_error
wire sys_timer_s1_agent_rdata_fifo_src_valid; // Sys_Timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] sys_timer_s1_agent_rdata_fifo_src_data; // Sys_Timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire sys_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> Sys_Timer_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> Sys_Timer_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> Sys_Timer_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // Sys_Timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> Sys_Timer_s1_agent:rdata_fifo_sink_error
wire sdram_s1_agent_rdata_fifo_out_valid; // SDRAM_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
wire [17:0] sdram_s1_agent_rdata_fifo_out_data; // SDRAM_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
wire sdram_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter_006:in_0_ready -> SDRAM_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> SDRAM_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> SDRAM_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // SDRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> SDRAM_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) niosii_core_data_master_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (niosii_core_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (niosii_core_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (niosii_core_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (niosii_core_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (niosii_core_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (niosii_core_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (niosII_core_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (niosII_core_data_master_waitrequest), // .waitrequest
.av_burstcount (niosII_core_data_master_burstcount), // .burstcount
.av_byteenable (niosII_core_data_master_byteenable), // .byteenable
.av_read (niosII_core_data_master_read), // .read
.av_readdata (niosII_core_data_master_readdata), // .readdata
.av_readdatavalid (niosII_core_data_master_readdatavalid), // .readdatavalid
.av_write (niosII_core_data_master_write), // .write
.av_writedata (niosII_core_data_master_writedata), // .writedata
.av_debugaccess (niosII_core_data_master_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) niosii_core_instruction_master_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (niosii_core_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (niosii_core_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (niosii_core_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (niosII_core_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (niosII_core_instruction_master_waitrequest), // .waitrequest
.av_burstcount (niosII_core_instruction_master_burstcount), // .burstcount
.av_read (niosII_core_instruction_master_read), // .read
.av_readdata (niosII_core_instruction_master_readdata), // .readdata
.av_readdatavalid (niosII_core_instruction_master_readdatavalid), // .readdatavalid
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_avalon_jtag_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (JTAG_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (JTAG_avalon_jtag_slave_write), // .write
.av_read (JTAG_avalon_jtag_slave_read), // .read
.av_readdata (JTAG_avalon_jtag_slave_readdata), // .readdata
.av_writedata (JTAG_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (JTAG_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (JTAG_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) convolution_slave_avs_s0_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (convolution_slave_avs_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (convolution_slave_avs_s0_agent_m0_burstcount), // .burstcount
.uav_read (convolution_slave_avs_s0_agent_m0_read), // .read
.uav_write (convolution_slave_avs_s0_agent_m0_write), // .write
.uav_waitrequest (convolution_slave_avs_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (convolution_slave_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (convolution_slave_avs_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (convolution_slave_avs_s0_agent_m0_readdata), // .readdata
.uav_writedata (convolution_slave_avs_s0_agent_m0_writedata), // .writedata
.uav_lock (convolution_slave_avs_s0_agent_m0_lock), // .lock
.uav_debugaccess (convolution_slave_avs_s0_agent_m0_debugaccess), // .debugaccess
.av_address (convolution_slave_avs_s0_address), // avalon_anti_slave_0.address
.av_write (convolution_slave_avs_s0_write), // .write
.av_read (convolution_slave_avs_s0_read), // .read
.av_readdata (convolution_slave_avs_s0_readdata), // .readdata
.av_writedata (convolution_slave_avs_s0_writedata), // .writedata
.av_waitrequest (convolution_slave_avs_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) systemid_control_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (systemid_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (systemid_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (systemid_control_slave_agent_m0_read), // .read
.uav_write (systemid_control_slave_agent_m0_write), // .write
.uav_waitrequest (systemid_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (systemid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (systemid_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (systemid_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (systemid_control_slave_agent_m0_writedata), // .writedata
.uav_lock (systemid_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (systemid_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (SystemID_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (SystemID_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) niosii_core_debug_mem_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (niosii_core_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (niosii_core_debug_mem_slave_agent_m0_read), // .read
.uav_write (niosii_core_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (niosii_core_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (niosii_core_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (niosii_core_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (niosii_core_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (niosii_core_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (niosII_core_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (niosII_core_debug_mem_slave_write), // .write
.av_read (niosII_core_debug_mem_slave_read), // .read
.av_readdata (niosII_core_debug_mem_slave_readdata), // .readdata
.av_writedata (niosII_core_debug_mem_slave_writedata), // .writedata
.av_byteenable (niosII_core_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (niosII_core_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (niosII_core_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_s1_agent_m0_read), // .read
.uav_write (sram_s1_agent_m0_write), // .write
.uav_waitrequest (sram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SRAM_s1_address), // avalon_anti_slave_0.address
.av_write (SRAM_s1_write), // .write
.av_readdata (SRAM_s1_readdata), // .readdata
.av_writedata (SRAM_s1_writedata), // .writedata
.av_byteenable (SRAM_s1_byteenable), // .byteenable
.av_chipselect (SRAM_s1_chipselect), // .chipselect
.av_clken (SRAM_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_timer_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_timer_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_timer_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_timer_s1_agent_m0_read), // .read
.uav_write (sys_timer_s1_agent_m0_write), // .write
.uav_waitrequest (sys_timer_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_timer_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_timer_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_timer_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_timer_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_timer_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_timer_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Sys_Timer_s1_address), // avalon_anti_slave_0.address
.av_write (Sys_Timer_s1_write), // .write
.av_readdata (Sys_Timer_s1_readdata), // .readdata
.av_writedata (Sys_Timer_s1_writedata), // .writedata
.av_chipselect (Sys_Timer_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SDRAM_s1_address), // avalon_anti_slave_0.address
.av_write (SDRAM_s1_write), // .write
.av_read (SDRAM_s1_read), // .read
.av_readdata (SDRAM_s1_readdata), // .readdata
.av_writedata (SDRAM_s1_writedata), // .writedata
.av_byteenable (SDRAM_s1_byteenable), // .byteenable
.av_readdatavalid (SDRAM_s1_readdatavalid), // .readdatavalid
.av_waitrequest (SDRAM_s1_waitrequest), // .waitrequest
.av_chipselect (SDRAM_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_QOS_H (89),
.PKT_QOS_L (89),
.PKT_DATA_SIDEBAND_H (87),
.PKT_DATA_SIDEBAND_L (87),
.PKT_ADDR_SIDEBAND_H (86),
.PKT_ADDR_SIDEBAND_L (86),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_CACHE_H (103),
.PKT_CACHE_L (100),
.PKT_THREAD_ID_H (96),
.PKT_THREAD_ID_L (96),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (63),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) niosii_core_data_master_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (niosii_core_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (niosii_core_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (niosii_core_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (niosii_core_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (niosii_core_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (niosii_core_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (niosii_core_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (niosii_core_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (niosii_core_data_master_agent_cp_valid), // cp.valid
.cp_data (niosii_core_data_master_agent_cp_data), // .data
.cp_startofpacket (niosii_core_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (niosii_core_data_master_agent_cp_ready), // .ready
.rp_valid (niosii_core_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (niosii_core_data_master_limiter_rsp_src_data), // .data
.rp_channel (niosii_core_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (niosii_core_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (niosii_core_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (niosii_core_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_QOS_H (89),
.PKT_QOS_L (89),
.PKT_DATA_SIDEBAND_H (87),
.PKT_DATA_SIDEBAND_L (87),
.PKT_ADDR_SIDEBAND_H (86),
.PKT_ADDR_SIDEBAND_L (86),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_CACHE_H (103),
.PKT_CACHE_L (100),
.PKT_THREAD_ID_H (96),
.PKT_THREAD_ID_L (96),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (31),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) niosii_core_instruction_master_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (niosii_core_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (niosii_core_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (niosii_core_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (niosii_core_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (niosii_core_instruction_master_agent_cp_valid), // cp.valid
.cp_data (niosii_core_instruction_master_agent_cp_data), // .data
.cp_startofpacket (niosii_core_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (niosii_core_instruction_master_agent_cp_ready), // .ready
.rp_valid (niosii_core_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (niosii_core_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (niosii_core_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (niosii_core_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (niosii_core_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (niosii_core_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_avalon_jtag_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (jtag_avalon_jtag_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (jtag_avalon_jtag_slave_burst_adapter_source0_valid), // .valid
.cp_data (jtag_avalon_jtag_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (jtag_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) convolution_slave_avs_s0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (convolution_slave_avs_s0_agent_m0_address), // m0.address
.m0_burstcount (convolution_slave_avs_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (convolution_slave_avs_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (convolution_slave_avs_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (convolution_slave_avs_s0_agent_m0_lock), // .lock
.m0_readdata (convolution_slave_avs_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (convolution_slave_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (convolution_slave_avs_s0_agent_m0_read), // .read
.m0_waitrequest (convolution_slave_avs_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (convolution_slave_avs_s0_agent_m0_writedata), // .writedata
.m0_write (convolution_slave_avs_s0_agent_m0_write), // .write
.rp_endofpacket (convolution_slave_avs_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (convolution_slave_avs_s0_agent_rp_ready), // .ready
.rp_valid (convolution_slave_avs_s0_agent_rp_valid), // .valid
.rp_data (convolution_slave_avs_s0_agent_rp_data), // .data
.rp_startofpacket (convolution_slave_avs_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (convolution_slave_avs_s0_burst_adapter_source0_ready), // cp.ready
.cp_valid (convolution_slave_avs_s0_burst_adapter_source0_valid), // .valid
.cp_data (convolution_slave_avs_s0_burst_adapter_source0_data), // .data
.cp_startofpacket (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (convolution_slave_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (convolution_slave_avs_s0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (convolution_slave_avs_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (convolution_slave_avs_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (convolution_slave_avs_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (convolution_slave_avs_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (convolution_slave_avs_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (convolution_slave_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (convolution_slave_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (convolution_slave_avs_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (convolution_slave_avs_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (convolution_slave_avs_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (convolution_slave_avs_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) convolution_slave_avs_s0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (convolution_slave_avs_s0_agent_rf_source_data), // in.data
.in_valid (convolution_slave_avs_s0_agent_rf_source_valid), // .valid
.in_ready (convolution_slave_avs_s0_agent_rf_source_ready), // .ready
.in_startofpacket (convolution_slave_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (convolution_slave_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (convolution_slave_avs_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (convolution_slave_avs_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (convolution_slave_avs_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) systemid_control_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (systemid_control_slave_agent_m0_address), // m0.address
.m0_burstcount (systemid_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (systemid_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (systemid_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (systemid_control_slave_agent_m0_lock), // .lock
.m0_readdata (systemid_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (systemid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (systemid_control_slave_agent_m0_read), // .read
.m0_waitrequest (systemid_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (systemid_control_slave_agent_m0_writedata), // .writedata
.m0_write (systemid_control_slave_agent_m0_write), // .write
.rp_endofpacket (systemid_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (systemid_control_slave_agent_rp_ready), // .ready
.rp_valid (systemid_control_slave_agent_rp_valid), // .valid
.rp_data (systemid_control_slave_agent_rp_data), // .data
.rp_startofpacket (systemid_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (systemid_control_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (systemid_control_slave_burst_adapter_source0_valid), // .valid
.cp_data (systemid_control_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (systemid_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (systemid_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (systemid_control_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (systemid_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (systemid_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (systemid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (systemid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (systemid_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (systemid_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (systemid_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (systemid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (systemid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (systemid_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (systemid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (systemid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (systemid_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) systemid_control_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (systemid_control_slave_agent_rf_source_data), // in.data
.in_valid (systemid_control_slave_agent_rf_source_valid), // .valid
.in_ready (systemid_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (systemid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (systemid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (systemid_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (systemid_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (systemid_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (systemid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (systemid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) niosii_core_debug_mem_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (niosii_core_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (niosii_core_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (niosii_core_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (niosii_core_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (niosii_core_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (niosii_core_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (niosii_core_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (niosii_core_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (niosii_core_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (niosii_core_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (niosii_core_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (niosii_core_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (niosii_core_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (niosii_core_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (niosii_core_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (niosii_core_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (niosii_core_debug_mem_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (niosii_core_debug_mem_slave_burst_adapter_source0_valid), // .valid
.cp_data (niosii_core_debug_mem_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (niosii_core_debug_mem_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (niosii_core_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (niosii_core_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (niosii_core_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (niosii_core_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (niosii_core_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) niosii_core_debug_mem_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (niosii_core_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (niosii_core_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (niosii_core_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (niosii_core_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (niosii_core_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sram_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_s1_agent_m0_lock), // .lock
.m0_readdata (sram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_s1_agent_m0_read), // .read
.m0_waitrequest (sram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_s1_agent_m0_writedata), // .writedata
.m0_write (sram_s1_agent_m0_write), // .write
.rp_endofpacket (sram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_s1_agent_rp_ready), // .ready
.rp_valid (sram_s1_agent_rp_valid), // .valid
.rp_data (sram_s1_agent_rp_data), // .data
.rp_startofpacket (sram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (sram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_s1_agent_rf_source_data), // in.data
.in_valid (sram_s1_agent_rf_source_valid), // .valid
.in_ready (sram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (88),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sys_timer_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_timer_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_timer_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_timer_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_timer_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_timer_s1_agent_m0_lock), // .lock
.m0_readdata (sys_timer_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_timer_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_timer_s1_agent_m0_read), // .read
.m0_waitrequest (sys_timer_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_timer_s1_agent_m0_writedata), // .writedata
.m0_write (sys_timer_s1_agent_m0_write), // .write
.rp_endofpacket (sys_timer_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_timer_s1_agent_rp_ready), // .ready
.rp_valid (sys_timer_s1_agent_rp_valid), // .valid
.rp_data (sys_timer_s1_agent_rp_data), // .data
.rp_startofpacket (sys_timer_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_timer_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sys_timer_s1_burst_adapter_source0_valid), // .valid
.cp_data (sys_timer_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sys_timer_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sys_timer_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sys_timer_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sys_timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_timer_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_timer_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_timer_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_timer_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_timer_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_timer_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_timer_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (sys_timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_timer_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_timer_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_timer_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_timer_s1_agent_rf_source_data), // in.data
.in_valid (sys_timer_s1_agent_rf_source_valid), // .valid
.in_ready (sys_timer_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_timer_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_timer_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_timer_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_timer_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_timer_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (90),
.PKT_ORI_BURST_SIZE_L (88),
.PKT_RESPONSE_STATUS_H (87),
.PKT_RESPONSE_STATUS_L (86),
.PKT_BURST_SIZE_H (65),
.PKT_BURST_SIZE_L (63),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (70),
.PKT_PROTECTION_H (81),
.PKT_PROTECTION_L (79),
.PKT_BURSTWRAP_H (62),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (72),
.PKT_DEST_ID_H (77),
.PKT_DEST_ID_L (75),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sdram_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_design_mm_interconnect_0_router router (
.sink_ready (niosii_core_data_master_agent_cp_ready), // sink.ready
.sink_valid (niosii_core_data_master_agent_cp_valid), // .valid
.sink_data (niosii_core_data_master_agent_cp_data), // .data
.sink_startofpacket (niosii_core_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_data_master_agent_cp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_001 router_001 (
.sink_ready (niosii_core_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (niosii_core_instruction_master_agent_cp_valid), // .valid
.sink_data (niosii_core_instruction_master_agent_cp_data), // .data
.sink_startofpacket (niosii_core_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_002 router_003 (
.sink_ready (convolution_slave_avs_s0_agent_rp_ready), // sink.ready
.sink_valid (convolution_slave_avs_s0_agent_rp_valid), // .valid
.sink_data (convolution_slave_avs_s0_agent_rp_data), // .data
.sink_startofpacket (convolution_slave_avs_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (convolution_slave_avs_s0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_002 router_004 (
.sink_ready (systemid_control_slave_agent_rp_ready), // sink.ready
.sink_valid (systemid_control_slave_agent_rp_valid), // .valid
.sink_data (systemid_control_slave_agent_rp_data), // .data
.sink_startofpacket (systemid_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (systemid_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_005 router_005 (
.sink_ready (niosii_core_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (niosii_core_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (niosii_core_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (niosii_core_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_005 router_006 (
.sink_ready (sram_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_s1_agent_rp_valid), // .valid
.sink_data (sram_s1_agent_rp_data), // .data
.sink_startofpacket (sram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_002 router_007 (
.sink_ready (sys_timer_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_timer_s1_agent_rp_valid), // .valid
.sink_data (sys_timer_s1_agent_rp_data), // .data
.sink_startofpacket (sys_timer_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_timer_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_008 router_008 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) niosii_core_data_master_limiter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (niosii_core_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (niosii_core_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (niosii_core_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (niosii_core_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (niosii_core_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (niosii_core_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (niosii_core_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (niosii_core_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (niosii_core_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (niosii_core_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (niosii_core_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (niosii_core_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (93),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (90),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) niosii_core_instruction_master_limiter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (niosii_core_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (niosii_core_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (niosii_core_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (niosii_core_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (niosii_core_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (niosii_core_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (niosii_core_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (niosii_core_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (niosii_core_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (niosii_core_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (niosii_core_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (niosii_core_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) jtag_avalon_jtag_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (jtag_avalon_jtag_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (jtag_avalon_jtag_slave_burst_adapter_source0_data), // .data
.source0_channel (jtag_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (jtag_avalon_jtag_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) convolution_slave_avs_s0_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (convolution_slave_avs_s0_burst_adapter_source0_valid), // source0.valid
.source0_data (convolution_slave_avs_s0_burst_adapter_source0_data), // .data
.source0_channel (convolution_slave_avs_s0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (convolution_slave_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (convolution_slave_avs_s0_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) systemid_control_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (systemid_control_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (systemid_control_slave_burst_adapter_source0_data), // .data
.source0_channel (systemid_control_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (systemid_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (systemid_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (systemid_control_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) niosii_core_debug_mem_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_mux_003_src_data), // .data
.sink0_channel (cmd_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_003_src_ready), // .ready
.source0_valid (niosii_core_debug_mem_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (niosii_core_debug_mem_slave_burst_adapter_source0_data), // .data
.source0_channel (niosii_core_debug_mem_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (niosii_core_debug_mem_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) sram_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_004_src_valid), // sink0.valid
.sink0_data (cmd_mux_004_src_data), // .data
.sink0_channel (cmd_mux_004_src_channel), // .channel
.sink0_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_004_src_ready), // .ready
.source0_valid (sram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sram_s1_burst_adapter_source0_data), // .data
.source0_channel (sram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sram_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (88),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (83),
.PKT_BURST_SIZE_L (81),
.PKT_BURST_TYPE_H (85),
.PKT_BURST_TYPE_L (84),
.PKT_BURSTWRAP_H (80),
.PKT_BURSTWRAP_L (75),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (71),
.OUT_BURSTWRAP_H (80),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) sys_timer_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_005_src_valid), // sink0.valid
.sink0_data (cmd_mux_005_src_data), // .data
.sink0_channel (cmd_mux_005_src_channel), // .channel
.sink0_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_005_src_ready), // .ready
.source0_valid (sys_timer_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sys_timer_s1_burst_adapter_source0_data), // .data
.source0_channel (sys_timer_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sys_timer_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sys_timer_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sys_timer_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (70),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (65),
.PKT_BURST_SIZE_L (63),
.PKT_BURST_TYPE_H (67),
.PKT_BURST_TYPE_L (66),
.PKT_BURSTWRAP_H (62),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (91),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (62),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) sdram_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_s1_burst_adapter_source0_ready) // .ready
);
soc_design_mm_interconnect_0_cmd_demux cmd_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (niosii_core_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (niosii_core_data_master_limiter_cmd_src_channel), // .channel
.sink_data (niosii_core_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (niosii_core_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (niosii_core_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (niosii_core_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (niosii_core_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (niosii_core_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (niosii_core_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (niosii_core_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux cmd_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_004 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_006 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux rsp_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux_003 rsp_demux_003 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux_003 rsp_demux_004 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_demux_004_src1_valid), // .valid
.src1_data (rsp_demux_004_src1_data), // .data
.src1_channel (rsp_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_004_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux_003 rsp_demux_006 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_mux rsp_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_003_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_003_src1_valid), // .valid
.sink0_channel (rsp_demux_003_src1_channel), // .channel
.sink0_data (rsp_demux_003_src1_data), // .data
.sink0_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_004_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_004_src1_valid), // .valid
.sink1_channel (rsp_demux_004_src1_channel), // .channel
.sink1_data (rsp_demux_004_src1_data), // .data
.sink1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_006_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_006_src1_valid), // .valid
.sink2_channel (rsp_demux_006_src1_channel), // .channel
.sink2_data (rsp_demux_006_src1_data), // .data
.sink2_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (62),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (65),
.IN_PKT_BURST_SIZE_L (63),
.IN_PKT_RESPONSE_STATUS_H (87),
.IN_PKT_RESPONSE_STATUS_L (86),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (67),
.IN_PKT_BURST_TYPE_L (66),
.IN_PKT_ORI_BURST_SIZE_L (88),
.IN_PKT_ORI_BURST_SIZE_H (90),
.IN_ST_DATA_W (91),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (83),
.OUT_PKT_BURST_SIZE_L (81),
.OUT_PKT_RESPONSE_STATUS_H (105),
.OUT_PKT_RESPONSE_STATUS_L (104),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (85),
.OUT_PKT_BURST_TYPE_L (84),
.OUT_PKT_ORI_BURST_SIZE_L (106),
.OUT_PKT_ORI_BURST_SIZE_H (108),
.OUT_ST_DATA_W (109),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_rsp_width_adapter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_008_src_valid), // sink.valid
.in_channel (router_008_src_channel), // .channel
.in_startofpacket (router_008_src_startofpacket), // .startofpacket
.in_endofpacket (router_008_src_endofpacket), // .endofpacket
.in_ready (router_008_src_ready), // .ready
.in_data (router_008_src_data), // .data
.out_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (80),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (83),
.IN_PKT_BURST_SIZE_L (81),
.IN_PKT_RESPONSE_STATUS_H (105),
.IN_PKT_RESPONSE_STATUS_L (104),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (85),
.IN_PKT_BURST_TYPE_L (84),
.IN_PKT_ORI_BURST_SIZE_L (106),
.IN_PKT_ORI_BURST_SIZE_H (108),
.IN_ST_DATA_W (109),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (65),
.OUT_PKT_BURST_SIZE_L (63),
.OUT_PKT_RESPONSE_STATUS_H (87),
.OUT_PKT_RESPONSE_STATUS_L (86),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (67),
.OUT_PKT_BURST_TYPE_L (66),
.OUT_PKT_ORI_BURST_SIZE_L (88),
.OUT_PKT_ORI_BURST_SIZE_H (90),
.OUT_ST_DATA_W (91),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_cmd_width_adapter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (niosII_core_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_006_src_valid), // sink.valid
.in_channel (cmd_mux_006_src_channel), // .channel
.in_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_006_src_ready), // .ready
.in_data (cmd_mux_006_src_data), // .data
.out_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (convolution_slave_avs_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (convolution_slave_avs_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (convolution_slave_avs_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (systemid_control_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (systemid_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (systemid_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sram_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sram_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sram_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sys_timer_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sys_timer_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sys_timer_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_006 #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (niosII_core_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sdram_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package pkga;
int pvar;
class MyClass;
int member;
function int getpvar(); return pvar; endfunction
endclass
endpackage
package pkgb;
int pvar;
class MyClass;
int member;
function int getpvar(); return pvar; endfunction
function int getavar(); return pkga::pvar; endfunction
endclass
endpackage
module t (/*AUTOARG*/);
initial begin
pkga::MyClass a;
pkgb::MyClass b;
pkga::pvar = 100;
pkgb::pvar = 200;
if (pkga::pvar != 100) $stop;
if (pkgb::pvar != 200) $stop;
a = new;
b = new;
a.member = 10;
b.member = 20;
if (a.member != 10) $stop;
if (b.member != 20) $stop;
if (a.getpvar() != 100) $stop;
if (b.getpvar() != 200) $stop;
if (b.getavar() != 100) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Thu Mar 31 18:01:07 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(AXI_En,
En,
FrameSize,
M_AXIS_tdata,
M_AXIS_tlast,
M_AXIS_tready,
M_AXIS_tstrb,
M_AXIS_tvalid,
S_AXIS_tdata,
S_AXIS_tlast,
S_AXIS_tready,
S_AXIS_tstrb,
S_AXIS_tvalid,
m_axis_aclk,
m_axis_aresetn);
input AXI_En;
input En;
input [7:0]FrameSize;
output [31:0]M_AXIS_tdata;
output M_AXIS_tlast;
input M_AXIS_tready;
output [3:0]M_AXIS_tstrb;
output M_AXIS_tvalid;
input [31:0]S_AXIS_tdata;
input S_AXIS_tlast;
output S_AXIS_tready;
input [3:0]S_AXIS_tstrb;
input S_AXIS_tvalid;
input m_axis_aclk;
input m_axis_aresetn;
wire AXI_En_1;
wire En_1;
wire [7:0]FrameSize_1;
wire [31:0]S_AXIS_1_TDATA;
wire S_AXIS_1_TLAST;
wire S_AXIS_1_TREADY;
wire [3:0]S_AXIS_1_TSTRB;
wire S_AXIS_1_TVALID;
wire m_axis_aclk_1;
wire m_axis_aresetn_1;
wire [31:0]sample_generator_0_M_AXIS_TDATA;
wire sample_generator_0_M_AXIS_TLAST;
wire sample_generator_0_M_AXIS_TREADY;
wire [3:0]sample_generator_0_M_AXIS_TSTRB;
wire sample_generator_0_M_AXIS_TVALID;
assign AXI_En_1 = AXI_En;
assign En_1 = En;
assign FrameSize_1 = FrameSize[7:0];
assign M_AXIS_tdata[31:0] = sample_generator_0_M_AXIS_TDATA;
assign M_AXIS_tlast = sample_generator_0_M_AXIS_TLAST;
assign M_AXIS_tstrb[3:0] = sample_generator_0_M_AXIS_TSTRB;
assign M_AXIS_tvalid = sample_generator_0_M_AXIS_TVALID;
assign S_AXIS_1_TDATA = S_AXIS_tdata[31:0];
assign S_AXIS_1_TLAST = S_AXIS_tlast;
assign S_AXIS_1_TSTRB = S_AXIS_tstrb[3:0];
assign S_AXIS_1_TVALID = S_AXIS_tvalid;
assign S_AXIS_tready = S_AXIS_1_TREADY;
assign m_axis_aclk_1 = m_axis_aclk;
assign m_axis_aresetn_1 = m_axis_aresetn;
assign sample_generator_0_M_AXIS_TREADY = M_AXIS_tready;
design_1_sample_generator_0_0 sample_generator_0
(.AXI_En(AXI_En_1),
.En(En_1),
.FrameSize(FrameSize_1),
.m_axis_aclk(m_axis_aclk_1),
.m_axis_aresetn(m_axis_aresetn_1),
.m_axis_tdata(sample_generator_0_M_AXIS_TDATA),
.m_axis_tlast(sample_generator_0_M_AXIS_TLAST),
.m_axis_tready(sample_generator_0_M_AXIS_TREADY),
.m_axis_tstrb(sample_generator_0_M_AXIS_TSTRB),
.m_axis_tvalid(sample_generator_0_M_AXIS_TVALID),
.s_axis_aclk(m_axis_aclk_1),
.s_axis_aresetn(m_axis_aresetn_1),
.s_axis_tdata(S_AXIS_1_TDATA),
.s_axis_tlast(S_AXIS_1_TLAST),
.s_axis_tready(S_AXIS_1_TREADY),
.s_axis_tstrb(S_AXIS_1_TSTRB),
.s_axis_tvalid(S_AXIS_1_TVALID));
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004,2007 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_mcode
(/*AUTOARG*/
// Outputs
MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
// Inputs
IR, ISet, MCycle, F, NMICycle, IntCycle
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input [7:0] IR;
input [1:0] ISet ;
input [6:0] MCycle ;
input [7:0] F ;
input NMICycle ;
input IntCycle ;
output [2:0] MCycles ;
output [2:0] TStates ;
output [1:0] Prefix ; // None,BC,ED,DD/FD
output Inc_PC ;
output Inc_WZ ;
output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
output Read_To_Reg ;
output Read_To_Acc ;
output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
output [3:0] ALU_Op ;
output Save_ALU ;
output PreserveC ;
output Arith16 ;
output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
output IORQ ;
output Jump ;
output JumpE ;
output JumpXY ;
output Call ;
output RstP ;
output LDZ ;
output LDW ;
output LDSPHL ;
output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
output ExchangeDH ;
output ExchangeRp ;
output ExchangeAF ;
output ExchangeRS ;
output I_DJNZ ;
output I_CPL ;
output I_CCF ;
output I_SCF ;
output I_RETN ;
output I_BT ;
output I_BC ;
output I_BTR ;
output I_RLD ;
output I_RRD ;
output I_INRC ;
output SetDI ;
output SetEI ;
output [1:0] IMode ;
output Halt ;
output NoRead ;
output Write ;
// regs
reg [2:0] MCycles ;
reg [2:0] TStates ;
reg [1:0] Prefix ; // None,BC,ED,DD/FD
reg Inc_PC ;
reg Inc_WZ ;
reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
reg Read_To_Reg ;
reg Read_To_Acc ;
reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
reg [3:0] ALU_Op ;
reg Save_ALU ;
reg PreserveC ;
reg Arith16 ;
reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
reg IORQ ;
reg Jump ;
reg JumpE ;
reg JumpXY ;
reg Call ;
reg RstP ;
reg LDZ ;
reg LDW ;
reg LDSPHL ;
reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
reg ExchangeDH ;
reg ExchangeRp ;
reg ExchangeAF ;
reg ExchangeRS ;
reg I_DJNZ ;
reg I_CPL ;
reg I_CCF ;
reg I_SCF ;
reg I_RETN ;
reg I_BT ;
reg I_BC ;
reg I_BTR ;
reg I_RLD ;
reg I_RRD ;
reg I_INRC ;
reg SetDI ;
reg SetEI ;
reg [1:0] IMode ;
reg Halt ;
reg NoRead ;
reg Write ;
parameter aNone = 3'b111;
parameter aBC = 3'b000;
parameter aDE = 3'b001;
parameter aXY = 3'b010;
parameter aIOA = 3'b100;
parameter aSP = 3'b101;
parameter aZI = 3'b110;
// constant aNone : std_logic_vector[2:0] = 3'b000;
// constant aXY : std_logic_vector[2:0] = 3'b001;
// constant aIOA : std_logic_vector[2:0] = 3'b010;
// constant aSP : std_logic_vector[2:0] = 3'b011;
// constant aBC : std_logic_vector[2:0] = 3'b100;
// constant aDE : std_logic_vector[2:0] = 3'b101;
// constant aZI : std_logic_vector[2:0] = 3'b110;
function is_cc_true;
input [7:0] FF;
input [2:0] cc;
begin
if (Mode == 3 )
begin
case (cc)
3'b000 : is_cc_true = FF[7] == 1'b0; // NZ
3'b001 : is_cc_true = FF[7] == 1'b1; // Z
3'b010 : is_cc_true = FF[4] == 1'b0; // NC
3'b011 : is_cc_true = FF[4] == 1'b1; // C
3'b100 : is_cc_true = 0;
3'b101 : is_cc_true = 0;
3'b110 : is_cc_true = 0;
3'b111 : is_cc_true = 0;
endcase
end
else
begin
case (cc)
3'b000 : is_cc_true = FF[6] == 1'b0; // NZ
3'b001 : is_cc_true = FF[6] == 1'b1; // Z
3'b010 : is_cc_true = FF[0] == 1'b0; // NC
3'b011 : is_cc_true = FF[0] == 1'b1; // C
3'b100 : is_cc_true = FF[2] == 1'b0; // PO
3'b101 : is_cc_true = FF[2] == 1'b1; // PE
3'b110 : is_cc_true = FF[7] == 1'b0; // P
3'b111 : is_cc_true = FF[7] == 1'b1; // M
endcase
end
end
endfunction // is_cc_true
reg [2:0] DDD;
reg [2:0] SSS;
reg [1:0] DPAIR;
always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
or NMICycle)
begin
DDD = IR[5:3];
SSS = IR[2:0];
DPAIR = IR[5:4];
MCycles = 3'b001;
if (MCycle[0] )
begin
TStates = 3'b100;
end
else
begin
TStates = 3'b011;
end
Prefix = 2'b00;
Inc_PC = 1'b0;
Inc_WZ = 1'b0;
IncDec_16 = 4'b0000;
Read_To_Acc = 1'b0;
Read_To_Reg = 1'b0;
Set_BusB_To = 4'b0000;
Set_BusA_To = 4'b0000;
ALU_Op = { 1'b0, IR[5:3] };
Save_ALU = 1'b0;
PreserveC = 1'b0;
Arith16 = 1'b0;
IORQ = 1'b0;
Set_Addr_To = aNone;
Jump = 1'b0;
JumpE = 1'b0;
JumpXY = 1'b0;
Call = 1'b0;
RstP = 1'b0;
LDZ = 1'b0;
LDW = 1'b0;
LDSPHL = 1'b0;
Special_LD = 3'b000;
ExchangeDH = 1'b0;
ExchangeRp = 1'b0;
ExchangeAF = 1'b0;
ExchangeRS = 1'b0;
I_DJNZ = 1'b0;
I_CPL = 1'b0;
I_CCF = 1'b0;
I_SCF = 1'b0;
I_RETN = 1'b0;
I_BT = 1'b0;
I_BC = 1'b0;
I_BTR = 1'b0;
I_RLD = 1'b0;
I_RRD = 1'b0;
I_INRC = 1'b0;
SetDI = 1'b0;
SetEI = 1'b0;
IMode = 2'b11;
Halt = 1'b0;
NoRead = 1'b0;
Write = 1'b0;
case (ISet)
2'b00 :
begin
//----------------------------------------------------------------------------
//
// Unprefixed instructions
//
//----------------------------------------------------------------------------
casez (IR)
// 8 BIT LOAD GROUP
8'b01zzzzzz :
begin
if (IR[5:0] == 6'b110110)
Halt = 1'b1;
else if (IR[2:0] == 3'b110)
begin
// LD r,(HL)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end // if (IR[2:0] == 3'b110)
else if (IR[5:3] == 3'b110)
begin
// LD (HL),r
MCycles = 3'b010;
if (MCycle[0])
begin
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[1])
Write = 1'b1;
end // if (IR[5:3] == 3'b110)
else
begin
Set_BusB_To[2:0] = SSS;
ExchangeRp = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end // else: !if(IR[5:3] == 3'b110)
end // case: 8'b01zzzzzz
8'b00zzz110 :
begin
if (IR[5:3] == 3'b110)
begin
// LD (HL),n
MCycles = 3'b011;
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_Addr_To = aXY;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (MCycle[2])
Write = 1'b1;
end // if (IR[5:3] == 3'b110)
else
begin
// LD r,n
MCycles = 3'b010;
if (MCycle[1])
begin
Inc_PC = 1'b1;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end
end
end
8'b00001010 :
begin
// LD A,(BC)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aBC;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00001010
8'b00011010 :
begin
// LD A,(DE)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aDE;
if (MCycle[1])
Read_To_Acc = 1'b1;
end // case: 8'b00011010
8'b00111010 :
begin
if (Mode == 3 )
begin
// LDD A,(HL)
MCycles = 3'b010;
if (MCycle[0])
Set_Addr_To = aXY;
if (MCycle[1])
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b1110;
end
end
else
begin
// LD A,(nn)
MCycles = 3'b100;
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
if (MCycle[2])
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
if (MCycle[3])
begin
Read_To_Acc = 1'b1;
end
end // else: !if(Mode == 3 )
end // case: 8'b00111010
8'b00000010 :
begin
// LD (BC),A
MCycles = 3'b010;
if (MCycle[0])
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
if (MCycle[1])
begin
Write = 1'b1;
end
end // case: 8'b00000010
8'b00010010 :
begin
// LD (DE),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aDE;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00010010
8'b00110010 :
begin
if (Mode == 3 )
begin
// LDD (HL),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1110;
end
default :;
endcase // case(MCycle)
end
else
begin
// LD (nn),A
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
Set_BusB_To = 4'b0111;
end
MCycle[3] :
begin
Write = 1'b1;
end
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00110010
// 16 BIT LOAD GROUP
8'b00000001,8'b00010001,8'b00100001,8'b00110001 :
begin
// LD dd,nn
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1000;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b1;
end
end // case: 2
MCycle[2] :
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1001;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b0;
end
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
8'b00101010 :
begin
if (Mode == 3 )
begin
// LDI A,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IncDec_16 = 4'b0110;
end
default :;
endcase
end
else
begin
// LD HL,(nn)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
end
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00101010
8'b00100010 :
begin
if (Mode == 3 )
begin
// LDI (HL),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b0110;
end
default :;
endcase
end
else
begin
// LD (nn),HL
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
Set_BusB_To = 4'b0101; // L
end
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
Set_BusB_To = 4'b0100; // H
end
MCycle[4] :
Write = 1'b1;
default :;
endcase
end // else: !if(Mode == 3 )
end // case: 8'b00100010
8'b11111001 :
begin
// LD SP,HL
TStates = 3'b110;
LDSPHL = 1'b1;
end
8'b11zz0101 :
begin
// PUSH qq
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
if (DPAIR == 2'b11 )
begin
Set_BusB_To = 4'b0111;
end
else
begin
Set_BusB_To[2:1] = DPAIR;
Set_BusB_To[0] = 1'b0;
Set_BusB_To[3] = 1'b0;
end
end // case: 1
MCycle[1] :
begin
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
if (DPAIR == 2'b11 )
begin
Set_BusB_To = 4'b1011;
end
else
begin
Set_BusB_To[2:1] = DPAIR;
Set_BusB_To[0] = 1'b1;
Set_BusB_To[3] = 1'b0;
end
Write = 1'b1;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
8'b11zz0001 :
begin
// POP qq
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b1011;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b1;
end
end // case: 2
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Read_To_Reg = 1'b1;
if (DPAIR == 2'b11 )
begin
Set_BusA_To[3:0] = 4'b0111;
end
else
begin
Set_BusA_To[2:1] = DPAIR;
Set_BusA_To[0] = 1'b0;
end
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
8'b11101011 :
begin
if (Mode != 3 )
begin
// EX DE,HL
ExchangeDH = 1'b1;
end
end
8'b00001000 :
begin
if (Mode == 3 )
begin
// LD (nn),SP
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
Set_BusB_To = 4'b1000;
end
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
Set_BusB_To = 4'b1001;
end
MCycle[4] :
Write = 1'b1;
default :;
endcase
end
else if (Mode < 2 )
begin
// EX AF,AF'
ExchangeAF = 1'b1;
end
end // case: 8'b00001000
8'b11011001 :
begin
if (Mode == 3 )
begin
// RETI
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
I_RETN = 1'b1;
SetEI = 1'b1;
end
default :;
endcase
end
else if (Mode < 2 )
begin
// EXX
ExchangeRS = 1'b1;
end
end // case: 8'b11011001
8'b11100011 :
begin
if (Mode != 3 )
begin
// EX (SP),HL
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0101;
Set_BusB_To = 4'b0101;
Set_Addr_To = aSP;
end
MCycle[2] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
TStates = 3'b100;
Write = 1'b1;
end
MCycle[3] :
begin
Read_To_Reg = 1'b1;
Set_BusA_To = 4'b0100;
Set_BusB_To = 4'b0100;
Set_Addr_To = aSP;
end
MCycle[4] :
begin
IncDec_16 = 4'b1111;
TStates = 3'b101;
Write = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11100011
// 8 BIT ARITHMETIC AND LOGICAL GROUP
8'b10zzzzzz :
begin
if (IR[2:0] == 3'b110)
begin
// ADD A,(HL)
// ADC A,(HL)
// SUB A,(HL)
// SBC A,(HL)
// AND A,(HL)
// OR A,(HL)
// XOR A,(HL)
// CP A,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
end
default :;
endcase // case(MCycle)
end // if (IR[2:0] == 3'b110)
else
begin
// ADD A,r
// ADC A,r
// SUB A,r
// SBC A,r
// AND A,r
// OR A,r
// XOR A,r
// CP A,r
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end // else: !if(IR[2:0] == 3'b110)
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
8'b11zzz110 :
begin
// ADD A,n
// ADC A,n
// SUB A,n
// SBC A,n
// AND A,n
// OR A,n
// XOR A,n
// CP A,n
MCycles = 3'b010;
if (MCycle[1] )
begin
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusB_To[2:0] = SSS;
Set_BusA_To[2:0] = 3'b111;
end
end
8'b00zzz100 :
begin
if (IR[5:3] == 3'b110)
begin
// INC (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0000;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00110100
else
begin
// INC r
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0000;
end
end
8'b00zzz101 :
begin
if (IR[5:3] == 3'b110)
begin
// DEC (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aXY;
MCycle[1] :
begin
TStates = 3'b100;
Set_Addr_To = aXY;
ALU_Op = 4'b0010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
end // case: 2
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end
else
begin
// DEC r
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
PreserveC = 1'b1;
ALU_Op = 4'b0010;
end
end
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
8'b00100111 :
begin
// DAA
Set_BusA_To[2:0] = 3'b111;
Read_To_Reg = 1'b1;
ALU_Op = 4'b1100;
Save_ALU = 1'b1;
end
8'b00101111 :
// CPL
I_CPL = 1'b1;
8'b00111111 :
// CCF
I_CCF = 1'b1;
8'b00110111 :
// SCF
I_SCF = 1'b1;
8'b00000000 :
begin
if (NMICycle == 1'b1 )
begin
// NMI
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end
else if (IntCycle == 1'b1 )
begin
// INT (IM 2)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[0] :
begin
LDZ = 1'b1;
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
TStates = 3'b100;
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
TStates = 3'b100;
Write = 1'b1;
end
MCycle[3] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[4] :
Jump = 1'b1;
default :;
endcase
end
end // case: 8'b00000000
8'b11110011 :
// DI
SetDI = 1'b1;
8'b11111011 :
// EI
SetEI = 1'b1;
// 16 BIT ARITHMETIC GROUP
8'b00zz1001 :
begin
// ADD HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase // case(IR[5:4])
TStates = 3'b100;
Arith16 = 1'b1;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
Set_BusB_To[2:1] = IR[5:4];
default :
Set_BusB_To = 4'b1001;
endcase
Arith16 = 1'b1;
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001
8'b00zz0011 :
begin
// INC ss
TStates = 3'b110;
IncDec_16[3:2] = 2'b01;
IncDec_16[1:0] = DPAIR;
end
8'b00zz1011 :
begin
// DEC ss
TStates = 3'b110;
IncDec_16[3:2] = 2'b11;
IncDec_16[1:0] = DPAIR;
end
// ROTATE AND SHIFT GROUP
8'b00000111,
// RLCA
8'b00010111,
// RLA
8'b00001111,
// RRCA
8'b00011111 :
// RRA
begin
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end // case: 8'b00000111,...
// JUMP GROUP
8'b11000011 :
begin
// JP nn
MCycles = 3'b011;
if (MCycle[1])
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
if (MCycle[2])
begin
Inc_PC = 1'b1;
Jump = 1'b1;
end
end // case: 8'b11000011
8'b11zzz010 :
begin
if (IR[5] == 1'b1 && Mode == 3 )
begin
case (IR[4:3])
2'b00 :
begin
// LD ($FF00+C),A
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b0111;
end
MCycle[1] :
begin
Write = 1'b1;
IORQ = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 2'b00
2'b01 :
begin
// LD (nn),A
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
Set_BusB_To = 4'b0111;
end
MCycle[3] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: default :...
2'b10 :
begin
// LD A,($FF00+C)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
MCycle[1] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 2'b10
2'b11 :
begin
// LD A,(nn)
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
end
MCycle[3] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
end
endcase
end
else
begin
// JP cc,nn
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Inc_PC = 1'b1;
if (is_cc_true(F, IR[5:3]) )
begin
Jump = 1'b1;
end
end
default :;
endcase
end // else: !if(DPAIR == 2'b11 )
end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
8'b00011000 :
begin
if (Mode != 2 )
begin
// JR e
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
Inc_PC = 1'b1;
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'b101;
end
default :;
endcase
end // if (Mode != 2 )
end // case: 8'b00011000
// Conditional relative jumps (JR [C/NC/Z/NZ], e)
8'b001zz000 :
begin
if (Mode != 2 )
begin
MCycles = 3'd3;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
case (IR[4:3])
0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3;
1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3;
2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3;
3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3;
endcase
end
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'd5;
end
default :;
endcase
end // if (Mode != 2 )
end // case: 8'b00111000
8'b11101001 :
// JP (HL)
JumpXY = 1'b1;
8'b00010000 :
begin
if (Mode == 3 )
begin
I_DJNZ = 1'b1;
end
else if (Mode < 2 )
begin
// DJNZ,e
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
I_DJNZ = 1'b1;
Set_BusB_To = 4'b1010;
Set_BusA_To[2:0] = 3'b000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
I_DJNZ = 1'b1;
Inc_PC = 1'b1;
end
MCycle[2] :
begin
NoRead = 1'b1;
JumpE = 1'b1;
TStates = 3'b101;
end
default :;
endcase
end // if (Mode < 2 )
end // case: 8'b00010000
// CALL AND RETURN GROUP
8'b11001101 :
begin
// CALL nn
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
IncDec_16 = 4'b1111;
Inc_PC = 1'b1;
TStates = 3'b100;
Set_Addr_To = aSP;
LDW = 1'b1;
Set_BusB_To = 4'b1101;
end
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b11001101
8'b11zzz100 :
begin
if (IR[5] == 1'b0 || Mode != 3 )
begin
// CALL cc,nn
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Inc_PC = 1'b1;
LDW = 1'b1;
if (is_cc_true(F, IR[5:3]) )
begin
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
TStates = 3'b100;
Set_BusB_To = 4'b1101;
end
else
begin
MCycles = 3'b011;
end // else: !if(is_cc_true(F, IR[5:3]) )
end // case: 3
MCycle[3] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[4] :
begin
Write = 1'b1;
Call = 1'b1;
end
default :;
endcase
end // if (IR[5] == 1'b0 || Mode != 3 )
end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
8'b11001001 :
begin
// RET
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aSP;
end
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
end
default :;
endcase // case(MCycle)
end // case: 8'b11001001
8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 :
begin
if (IR[5] == 1'b1 && Mode == 3 )
begin
case (IR[4:3])
2'b00 :
begin
// LD ($FF00+nn),A
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
Set_BusB_To = 4'b0111;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 2'b00
2'b01 :
begin
// ADD SP,n
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
ALU_Op = 4'b0000;
Inc_PC = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To = 4'b1000;
Set_BusB_To = 4'b0110;
end
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To = 4'b1001;
Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
end
default :;
endcase // case(MCycle)
end // case: 2'b01
2'b10 :
begin
// LD A,($FF00+nn)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
MCycle[2] :
Read_To_Acc = 1'b1;
default :;
endcase // case(MCycle)
end // case: 2'b10
2'b11 :
begin
// LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Set_BusA_To[2:0] = 3'b101; // L
Read_To_Reg = 1'b1;
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end
MCycle[4] :
begin
Set_BusA_To[2:0] = 3'b100; // H
Read_To_Reg = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 2'b11
endcase // case(IR[4:3])
end
else
begin
// RET cc
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
if (is_cc_true(F, IR[5:3]) )
begin
Set_Addr_To = aSP;
end
else
begin
MCycles = 3'b001;
end
TStates = 3'b101;
end // case: 1
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
end
default :;
endcase
end // else: !if(IR[5] == 1'b1 && Mode == 3 )
end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 :
begin
// RST p
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1101;
end
MCycle[1] :
begin
Write = 1'b1;
IncDec_16 = 4'b1111;
Set_Addr_To = aSP;
Set_BusB_To = 4'b1100;
end
MCycle[2] :
begin
Write = 1'b1;
RstP = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
// INPUT AND OUTPUT GROUP
8'b11011011 :
begin
if (Mode != 3 )
begin
// IN A,(n)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
end
MCycle[2] :
begin
Read_To_Acc = 1'b1;
IORQ = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11011011
8'b11010011 :
begin
if (Mode != 3 )
begin
// OUT (n),A
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
Set_Addr_To = aIOA;
Set_BusB_To = 4'b0111;
end
MCycle[2] :
begin
Write = 1'b1;
IORQ = 1'b1;
end
default :;
endcase
end // if (Mode != 3 )
end // case: 8'b11010011
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// MULTIBYTE INSTRUCTIONS
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
8'b11001011 :
begin
if (Mode != 2 )
begin
Prefix = 2'b01;
end
end
8'b11101101 :
begin
if (Mode < 2 )
begin
Prefix = 2'b10;
end
end
8'b11011101,8'b11111101 :
begin
if (Mode < 2 )
begin
Prefix = 2'b11;
end
end
endcase // case(IR)
end // case: 2'b00
2'b01 :
begin
//----------------------------------------------------------------------------
//
// CB prefixed instructions
//
//----------------------------------------------------------------------------
Set_BusA_To[2:0] = IR[2:0];
Set_BusB_To[2:0] = IR[2:0];
casez (IR)
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
begin
// RLC r
// RL r
// RRC r
// RR r
// SLA r
// SRA r
// SRL r
// SLL r (Undocumented) / SWAP r
if (MCycle[0] ) begin
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
8'b00zzz110 :
begin
// RLC (HL)
// RL (HL)
// RRC (HL)
// RR (HL)
// SRA (HL)
// SRL (HL)
// SLA (HL)
// SLL (HL) (Undocumented) / SWAP (HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
begin
// BIT b,r
if (MCycle[0] )
begin
Set_BusB_To[2:0] = IR[2:0];
ALU_Op = 4'b1001;
end
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 :
begin
// BIT b,(HL)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1001;
TStates = 3'b100;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
begin
// SET b,r
if (MCycle[0] )
begin
ALU_Op = 4'b1010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
begin
// SET b,(HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1010;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
begin
// RES b,r
if (MCycle[0] )
begin
ALU_Op = 4'b1011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
end
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
begin
// RES b,(HL)
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0], MCycle[6] :
Set_Addr_To = aXY;
MCycle[1] :
begin
ALU_Op = 4'b1011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_Addr_To = aXY;
TStates = 3'b100;
end
MCycle[2] :
Write = 1'b1;
default :;
endcase // case(MCycle)
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
endcase // case(IR)
end // case: 2'b01
default :
begin : default_ed_block
//----------------------------------------------------------------------------
//
// ED prefixed instructions
//
//----------------------------------------------------------------------------
casez (IR)
/*
* Undocumented NOP instructions commented out to reduce size of mcode
*
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
, 8'b10100100,8'b10100101,8'b10100110,8'b10100111
, 8'b10101100,8'b10101101,8'b10101110,8'b10101111
, 8'b10110100,8'b10110101,8'b10110110,8'b10110111
, 8'b10111100,8'b10111101,8'b10111110,8'b10111111
,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
; // NOP, undocumented
8'b01111110,8'b01111111 :
// NOP, undocumented
;
*/
// 8 BIT LOAD GROUP
8'b01010111 :
begin
// LD A,I
Special_LD = 3'b100;
TStates = 3'b101;
end
8'b01011111 :
begin
// LD A,R
Special_LD = 3'b101;
TStates = 3'b101;
end
8'b01000111 :
begin
// LD I,A
Special_LD = 3'b110;
TStates = 3'b101;
end
8'b01001111 :
begin
// LD R,A
Special_LD = 3'b111;
TStates = 3'b101;
end
// 16 BIT LOAD GROUP
8'b01001011,8'b01011011,8'b01101011,8'b01111011 :
begin
// LD dd,(nn)
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
end
MCycle[3] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusA_To = 4'b1000;
end
else
begin
Set_BusA_To[2:1] = IR[5:4];
Set_BusA_To[0] = 1'b1;
end
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
end // case: 4
MCycle[4] :
begin
Read_To_Reg = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusA_To = 4'b1001;
end
else
begin
Set_BusA_To[2:1] = IR[5:4];
Set_BusA_To[0] = 1'b0;
end
end // case: 5
default :;
endcase // case(MCycle)
end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
8'b01000011,8'b01010011,8'b01100011,8'b01110011 :
begin
// LD (nn),dd
MCycles = 3'b101;
case (1'b1) // MCycle
MCycle[1] :
begin
Inc_PC = 1'b1;
LDZ = 1'b1;
end
MCycle[2] :
begin
Set_Addr_To = aZI;
Inc_PC = 1'b1;
LDW = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusB_To = 4'b1000;
end
else
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
Set_BusB_To[3] = 1'b0;
end
end // case: 3
MCycle[3] :
begin
Inc_WZ = 1'b1;
Set_Addr_To = aZI;
Write = 1'b1;
if (IR[5:4] == 2'b11 )
begin
Set_BusB_To = 4'b1001;
end
else
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b0;
Set_BusB_To[3] = 1'b0;
end
end // case: 4
MCycle[4] :
begin
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 :
begin
// LDI, LDD, LDIR, LDDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b0000;
Set_Addr_To = aDE;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110; // IX
end
else
begin
IncDec_16 = 4'b1110;
end
end // case: 2
MCycle[2] :
begin
I_BT = 1'b1;
TStates = 3'b101;
Write = 1'b1;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0101; // DE
end
else
begin
IncDec_16 = 4'b1101;
end
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 :
begin
// CPI, CPD, CPIR, CPDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aXY;
IncDec_16 = 4'b1100; // BC
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b0111;
Save_ALU = 1'b1;
PreserveC = 1'b1;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
I_BC = 1'b1;
TStates = 3'b101;
end
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 :
begin
// NEG
ALU_Op = 4'b0010;
Set_BusB_To = 4'b0111;
Set_BusA_To = 4'b1010;
Read_To_Acc = 1'b1;
Save_ALU = 1'b1;
end
8'b01000110,8'b01001110,8'b01100110,8'b01101110 :
begin
// IM 0
IMode = 2'b00;
end
8'b01010110,8'b01110110 :
// IM 1
IMode = 2'b01;
8'b01011110,8'b01110111 :
// IM 2
IMode = 2'b10;
// 16 bit arithmetic
8'b01001010,8'b01011010,8'b01101010,8'b01111010 :
begin
// ADC HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0001;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase
TStates = 3'b100;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0001;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b0;
end
default :
Set_BusB_To = 4'b1001;
endcase // case(IR[5:4])
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
8'b01000010,8'b01010010,8'b01100010,8'b01110010 :
begin
// SBC HL,ss
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b101;
case (IR[5:4])
0,1,2 :
begin
Set_BusB_To[2:1] = IR[5:4];
Set_BusB_To[0] = 1'b1;
end
default :
Set_BusB_To = 4'b1000;
endcase
TStates = 3'b100;
end // case: 2
MCycle[2] :
begin
NoRead = 1'b1;
ALU_Op = 4'b0011;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
Set_BusA_To[2:0] = 3'b100;
case (IR[5:4])
0,1,2 :
Set_BusB_To[2:1] = IR[5:4];
default :
Set_BusB_To = 4'b1001;
endcase
end // case: 3
default :;
endcase // case(MCycle)
end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
8'b01101111 :
begin
// RLD
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
begin
NoRead = 1'b1;
Set_Addr_To = aXY;
end
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1101;
TStates = 3'b100;
Set_Addr_To = aXY;
Save_ALU = 1'b1;
end
MCycle[3] :
begin
I_RLD = 1'b1;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01101111
8'b01100111 :
begin
// RRD
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[1] :
Set_Addr_To = aXY;
MCycle[2] :
begin
Read_To_Reg = 1'b1;
Set_BusB_To[2:0] = 3'b110;
Set_BusA_To[2:0] = 3'b111;
ALU_Op = 4'b1110;
TStates = 3'b100;
Set_Addr_To = aXY;
Save_ALU = 1'b1;
end
MCycle[3] :
begin
I_RRD = 1'b1;
Write = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01100111
8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 :
begin
// RETI, RETN
MCycles = 3'b011;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aSP;
MCycle[1] :
begin
IncDec_16 = 4'b0111;
Set_Addr_To = aSP;
LDZ = 1'b1;
end
MCycle[2] :
begin
Jump = 1'b1;
IncDec_16 = 4'b0111;
I_RETN = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 :
begin
// IN r,(C)
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
Set_Addr_To = aBC;
MCycle[1] :
begin
IORQ = 1'b1;
if (IR[5:3] != 3'b110 )
begin
Read_To_Reg = 1'b1;
Set_BusA_To[2:0] = IR[5:3];
end
I_INRC = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 :
begin
// OUT (C),r
// OUT (C),0
MCycles = 3'b010;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To[2:0] = IR[5:3];
if (IR[5:3] == 3'b110 )
begin
Set_BusB_To[3] = 1'b1;
end
end
MCycle[1] :
begin
Write = 1'b1;
IORQ = 1'b1;
end
default :;
endcase // case(MCycle)
end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 :
begin
// INI, IND, INIR, INDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
Set_Addr_To = aBC;
Set_BusB_To = 4'b1010;
Set_BusA_To = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
IORQ = 1'b1;
Set_BusB_To = 4'b0110;
Set_Addr_To = aXY;
end
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
TStates = 3'b100;
Write = 1'b1;
I_BTR = 1'b1;
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 :
begin
// OUTI, OUTD, OTIR, OTDR
MCycles = 3'b100;
case (1'b1) // MCycle
MCycle[0] :
begin
TStates = 3'b101;
Set_Addr_To = aXY;
Set_BusB_To = 4'b1010;
Set_BusA_To = 4'b0000;
Read_To_Reg = 1'b1;
Save_ALU = 1'b1;
ALU_Op = 4'b0010;
end
MCycle[1] :
begin
Set_BusB_To = 4'b0110;
Set_Addr_To = aBC;
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0110;
end
else
begin
IncDec_16 = 4'b1110;
end
end
MCycle[2] :
begin
if (IR[3] == 1'b0 )
begin
IncDec_16 = 4'b0010;
end
else
begin
IncDec_16 = 4'b1010;
end
IORQ = 1'b1;
Write = 1'b1;
I_BTR = 1'b1;
end // case: 3
MCycle[3] :
begin
NoRead = 1'b1;
TStates = 3'b101;
end
default :;
endcase // case(MCycle)
end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
default : ;
endcase // case(IR)
end // block: default_ed_block
endcase // case(ISet)
if (Mode == 1 )
begin
if (MCycle[0] )
begin
//TStates = 3'b100;
end
else
begin
TStates = 3'b011;
end
end
if (Mode == 3 )
begin
if (MCycle[0] )
begin
//TStates = 3'b100;
end
else
begin
TStates = 3'b100;
end
end
if (Mode < 2 )
begin
if (MCycle[5] )
begin
Inc_PC = 1'b1;
if (Mode == 1 )
begin
Set_Addr_To = aXY;
TStates = 3'b100;
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
end
if (IR == 8'b00110110 || IR == 8'b11001011 )
begin
Set_Addr_To = aNone;
end
end
if (MCycle[6] )
begin
if (Mode == 0 )
begin
TStates = 3'b101;
end
if (ISet != 2'b01 )
begin
Set_Addr_To = aXY;
end
Set_BusB_To[2:0] = SSS;
Set_BusB_To[3] = 1'b0;
if (IR == 8'b00110110 || ISet == 2'b01 )
begin
// LD (HL),n
Inc_PC = 1'b1;
end
else
begin
NoRead = 1'b1;
end
end
end // if (Mode < 2 )
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
endmodule // T80_MCode
|
/*
module flag_cdc(
clkA, FlagIn_clkA,
clkB, FlagOut_clkB,rst_n);
// clkA domain signals
input clkA, FlagIn_clkA;
input rst_n;
// clkB domain signals
input clkB;
output FlagOut_clkB;
reg FlagToggle_clkA;
reg [2:0] SyncA_clkB;
// this changes level when a flag is seen
always @(posedge clkA)
begin : cdc_clk_a
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end
else if(FlagIn_clkA == 1'b1) begin
FlagToggle_clkA <= ~FlagToggle_clkA;
end
end
// which can then be sync-ed to clkB
always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
// and recreate the flag from the level change
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule
*/
module flag_cdc(
input clkA,
input FlagIn_clkA,
input clkB,
output FlagOut_clkB,
input rst_n
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA = 1'b0;
always @(posedge clkA or negedge rst_n)
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end else begin
FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;
end
// which can then be sync-ed to clkB
reg [2:0] SyncA_clkB = 3'b0;
always @(posedge clkB or negedge rst_n)
if (rst_n == 1'b0) begin
SyncA_clkB <= 3'b0;
end else begin
SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
end
// and recreate the flag in clkB
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_TB_V
`define SKY130_FD_SC_LS__NAND4B_TB_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ls__nand4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
c <= a | b;
// verilator lint_on COMBDLY
end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
parameter CONSTANT = 1;
always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
f = e;
end
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
a <= 32'hfeed0000;
b <= 32'h0000face;
end
if (cyc==2) begin
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
if (g != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_axis_uart:1.0
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_axis_uart_0_1 (
RST_N,
CLK,
S_AXI_AWADDR,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_BRESP,
S_AXI_ARADDR,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_RREADY,
RXD,
TXD,
GPIO_I,
GPIO_O,
GPIO_OT,
INTERRUPT
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [15 : 0] S_AXI_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] S_AXI_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] S_AXI_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire S_AXI_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire S_AXI_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] S_AXI_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] S_AXI_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire S_AXI_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire S_AXI_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire S_AXI_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire S_AXI_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] S_AXI_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [15 : 0] S_AXI_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] S_AXI_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] S_AXI_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire S_AXI_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire S_AXI_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] S_AXI_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] S_AXI_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire S_AXI_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire S_AXI_RREADY;
(* X_INTERFACE_INFO = "user.org:user:UART:1.0 UART RX" *)
input wire RXD;
(* X_INTERFACE_INFO = "user.org:user:UART:1.0 UART TX" *)
output wire TXD;
(* X_INTERFACE_INFO = "user.org:user:GPIO:1.0 GPIO I" *)
input wire [31 : 0] GPIO_I;
(* X_INTERFACE_INFO = "user.org:user:GPIO:1.0 GPIO O" *)
output wire [31 : 0] GPIO_O;
(* X_INTERFACE_INFO = "user.org:user:GPIO:1.0 GPIO OT" *)
output wire [31 : 0] GPIO_OT;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *)
output wire INTERRUPT;
fmrv32im_axis_uart inst (
.RST_N(RST_N),
.CLK(CLK),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.RXD(RXD),
.TXD(TXD),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_OT(GPIO_OT),
.INTERRUPT(INTERRUPT)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Decoder for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Decoder
// Module Name: Decoder
// File Name: Decoder.v
//
// Version: v1.0.0
//
// Description: General purpose decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Decoder
#
(
parameter OutputWidth = 4
)
(
I,
O
);
input [$clog2(OutputWidth) - 1:0] I;
output [OutputWidth - 1:0] O;
reg [OutputWidth - 1:0] rO;
genvar c;
generate
for (c = 0; c < OutputWidth; c = c + 1)
begin: DecodeBits
always @ (*)
begin
if (I == c)
rO[c] <= 1'b1;
else
rO[c] <= 1'b0;
end
end
endgenerate
assign O = rO;
endmodule |
`timescale 1 ns / 1 ps
module axis_packetizer #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32,
parameter CONTINUOUS = "FALSE",
parameter ALWAYS_READY = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_enbl_reg, int_enbl_next;
wire int_comp_wire, int_tvalid_wire, int_tlast_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
end
end
assign int_comp_wire = int_cntr_reg < cfg_data;
assign int_tvalid_wire = int_enbl_reg & s_axis_tvalid;
assign int_tlast_wire = ~int_comp_wire;
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
end
end
else
begin : STOP
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_enbl_next = 1'b0;
end
end
end
endgenerate
generate
if(ALWAYS_READY == "TRUE")
begin : READY
assign s_axis_tready = 1'b1;
end
else
begin : BLOCKING
assign s_axis_tready = int_enbl_reg & m_axis_tready;
end
endgenerate
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tvalid = int_tvalid_wire;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_lim #
(parameter TAPCNTRWIDTH = 7,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 9,
parameter TCQ = 100,
parameter TAPSPERKCLK = 56,
parameter TDQSS_DEGREES = 60,
parameter BYPASS_COMPLEX_OCAL = "FALSE")
(/*AUTOARG*/
// Outputs
lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
// Inputs
clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
prech_done, oclkdelay_calib_cnt
);
function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
end
endfunction // mod_sub
input clk;
input rst;
input lim_start;
input po_rdy;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
input [5:0] oclkdelay_init_val;
input [5:0] wl_po_fine_cnt;
input [5:0] simp_stg3_final_sel;
input oclkdelay_calib_done;
input poc2lim_detect_done;
input prech_done;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
output lim2init_write_request;
output lim2init_prech_req;
output lim2poc_rdy;
output lim2poc_ktap_right; // I think this can be defaulted.
output lim2stg3_inc;
output lim2stg3_dec;
output lim2stg2_inc;
output lim2stg2_dec;
output lim_done;
output [5:0] lim2ocal_stg3_right_lim;
output [5:0] lim2ocal_stg3_left_lim;
output [255:0] dbg_ocd_lim;
// Stage 3 taps can move an additional + or - 60 degrees from the write level position
// Convert 60 degrees to MMCM taps. 360/60=6.
//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam DIV_FACTOR = 360/TDQSS_DEGREES;
localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam WAIT_CNT = 15;
localparam IDLE = 14'b00_0000_0000_0001;
localparam INIT = 14'b00_0000_0000_0010;
localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;
localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;
localparam WAIT_STG3 = 14'b00_0000_0001_0000;
localparam STAGE3_INC = 14'b00_0000_0010_0000;
localparam STAGE3_DEC = 14'b00_0000_0100_0000;
localparam STAGE2_INC = 14'b00_0000_1000_0000;
localparam STAGE2_DEC = 14'b00_0001_0000_0000;
localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;
localparam PRECH_REQUEST = 14'b01_0000_0000_0000;
localparam LIMIT_DONE = 14'b10_0000_0000_0000;
// Flip-flops
reg [5:0] stg3_init_val;
reg [13:0] lim_state;
reg lim_start_r;
reg ktap_right_r;
reg write_request_r;
reg prech_req_r;
reg poc_ready_r;
reg wait_cnt_en_r;
reg wait_cnt_done;
reg [3:0] wait_cnt_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg2_tap_cnt;
reg [5:0] stg3_left_lim;
reg [5:0] stg3_right_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
reg [5:0] stg3_dec_val;
reg [5:0] stg3_inc_val;
reg detect_done_r;
reg stg3_dec_r;
reg stg2_inc_r;
reg stg3_inc2init_val_r;
reg stg3_inc2init_val_r1;
reg stg3_dec2init_val_r;
reg stg3_dec2init_val_r1;
reg stg3_dec_req_r;
reg stg3_inc_req_r;
reg stg2_dec_req_r;
reg stg2_inc_req_r;
reg stg3_init_dec_r;
reg [TAPCNTRWIDTH:0] mmcm_current;
reg [TAPCNTRWIDTH:0] mmcm_init_trail;
reg [TAPCNTRWIDTH:0] mmcm_init_lead;
reg done_r;
reg [13:0] lim_nxt_state;
reg ktap_right;
reg write_request;
reg prech_req;
reg poc_ready;
reg stg3_dec;
reg stg2_inc;
reg stg3_inc2init_val;
reg stg3_dec2init_val;
reg stg3_dec_req;
reg stg3_inc_req;
reg stg2_dec_req;
reg stg2_inc_req;
reg stg3_init_dec;
reg done;
reg oclkdelay_calib_done_r;
wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
/***************************************************************************/
// Debug signals
/***************************************************************************/
assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[255:108] = 'd0;
assign lim2init_write_request = write_request_r;
assign lim2init_prech_req = prech_req_r;
assign lim2poc_ktap_right = ktap_right_r;
assign lim2poc_rdy = poc_ready_r;
assign lim2ocal_stg3_left_lim = stg3_left_lim;
assign lim2ocal_stg3_right_lim = stg3_right_lim;
assign lim2stg3_dec = stg3_dec_req_r;
assign lim2stg3_inc = stg3_inc_req_r;
assign lim2stg2_dec = stg2_dec_req_r;
assign lim2stg2_inc = stg2_inc_req_r;
assign lim_done = done_r;
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if ((lim_state == WAIT_WR_REQ) ||
(lim_state == WAIT_STG3) ||
(lim_state == INIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
end
// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
wait_cnt_done <= #TCQ 1'b0;
end else begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b1;
end
end
end
/**************************Wait Counter End***********************************/
// Flip-flops
always @(posedge clk) begin
if (rst)
oclkdelay_calib_done_r <= #TCQ 1'b0;
else
oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
end
always @(posedge clk) begin
if (rst)
stg3_init_val <= #TCQ oclkdelay_init_val;
else if (oclkdelay_calib_done)
stg3_init_val <= #TCQ simp_stg3_final_sel;
else
stg3_init_val <= #TCQ oclkdelay_init_val;
end
always @(posedge clk) begin
if (rst) begin
lim_state <= #TCQ IDLE;
lim_start_r <= #TCQ 1'b0;
ktap_right_r <= #TCQ 1'b0;
write_request_r <= #TCQ 1'b0;
prech_req_r <= #TCQ 1'b0;
poc_ready_r <= #TCQ 1'b0;
detect_done_r <= #TCQ 1'b0;
stg3_dec_r <= #TCQ 1'b0;
stg2_inc_r <= #TCQ 1'b0;
stg3_inc2init_val_r <= #TCQ 1'b0;
stg3_inc2init_val_r1<= #TCQ 1'b0;
stg3_dec2init_val_r <= #TCQ 1'b0;
stg3_dec2init_val_r1<= #TCQ 1'b0;
stg3_dec_req_r <= #TCQ 1'b0;
stg3_inc_req_r <= #TCQ 1'b0;
stg2_dec_req_r <= #TCQ 1'b0;
stg2_inc_req_r <= #TCQ 1'b0;
done_r <= #TCQ 1'b0;
stg3_dec_val <= #TCQ 'd0;
stg3_inc_val <= #TCQ 'd0;
stg3_init_dec_r <= #TCQ 1'b0;
end else begin
lim_state <= #TCQ lim_nxt_state;
lim_start_r <= #TCQ lim_start;
ktap_right_r <= #TCQ ktap_right;
write_request_r <= #TCQ write_request;
prech_req_r <= #TCQ prech_req;
poc_ready_r <= #TCQ poc_ready;
detect_done_r <= #TCQ poc2lim_detect_done;
stg3_dec_r <= #TCQ stg3_dec;
stg2_inc_r <= #TCQ stg2_inc;
stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
stg3_dec_req_r <= #TCQ stg3_dec_req;
stg3_inc_req_r <= #TCQ stg3_inc_req;
stg2_dec_req_r <= #TCQ stg2_dec_req;
stg2_inc_req_r <= #TCQ stg2_inc_req;
stg3_init_dec_r <= #TCQ stg3_init_dec;
done_r <= #TCQ done;
if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
else
stg3_dec_val <= #TCQ 'd0;
if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
else
stg3_inc_val <= #TCQ 'd63;
end
end
// Keeping track of stage 3 tap count
always @(posedge clk) begin
if (rst)
stg3_tap_cnt <= #TCQ stg3_init_val;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg3_tap_cnt <= #TCQ stg3_init_val;
else if (lim_state == STAGE3_INC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
else if (lim_state == STAGE3_DEC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
end
// Keeping track of stage 2 tap count
always @(posedge clk) begin
if (rst)
stg2_tap_cnt <= #TCQ 'd0;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
else if (lim_state == STAGE2_INC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
else if (lim_state == STAGE2_DEC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
end
// Keeping track of MMCM tap count
always @(posedge clk) begin
if (rst) begin
mmcm_init_trail <= #TCQ 'd0;
mmcm_init_lead <= #TCQ 'd0;
end else if (poc2lim_detect_done && !detect_done_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
if (stg3_tap_cnt == stg3_inc_val)
mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;
end
end
always @(posedge clk) begin
if (rst) begin
mmcm_current <= #TCQ 'd0;
end else if (stg3_dec_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_current <= #TCQ mmcm_init_trail;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
end else begin
if (stg3_tap_cnt == stg3_inc_val)
mmcm_current <= #TCQ mmcm_init_lead;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
end
end
// Record Stage3 Left Limit
always @(posedge clk) begin
if (rst) begin
stg3_left_lim <= #TCQ 'd0;
simp_stg3_left_lim <= #TCQ 'd0;
cmplx_stg3_left_lim <= #TCQ 'd0;
end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
stg3_left_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_left_lim <= #TCQ 'd0;
end
// Record Stage3 Right Limit
always @(posedge clk) begin
if (rst) begin
stg3_right_lim <= #TCQ 'd0;
cmplx_stg3_right_lim <= #TCQ 'd0;
simp_stg3_right_lim <= #TCQ 'd0;
end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
stg3_right_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_right_lim <= #TCQ 'd0;
end
always @(*) begin
lim_nxt_state = lim_state;
ktap_right = ktap_right_r;
write_request = write_request_r;
prech_req = prech_req_r;
poc_ready = poc_ready_r;
stg3_dec = stg3_dec_r;
stg2_inc = stg2_inc_r;
stg3_inc2init_val = stg3_inc2init_val_r;
stg3_dec2init_val = stg3_dec2init_val_r;
stg3_dec_req = stg3_dec_req_r;
stg3_inc_req = stg3_inc_req_r;
stg2_inc_req = stg2_inc_req_r;
stg2_dec_req = stg2_dec_req_r;
stg3_init_dec = stg3_init_dec_r;
done = done_r;
case(lim_state)
IDLE: begin
if (lim_start && !lim_start_r) begin
lim_nxt_state = INIT;
stg3_dec = 1'b1;
stg2_inc = 1'b1;
stg3_init_dec = 1'b1;
done = 1'b0;
end
//New start of limit module for complex oclkdelay calib
else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
done = 1'b0;
end
end
INIT: begin
ktap_right = 1'b1;
// Initial stage 2 increment to 63 for left limit
if (wait_cnt_done)
lim_nxt_state = STAGE2_TAP_CHK;
end
// Wait for DQS to toggle before asserting poc_ready
WAIT_WR_REQ: begin
write_request = 1'b1;
if (wait_cnt_done) begin
poc_ready = 1'b1;
lim_nxt_state = WAIT_POC_DONE;
end
end
// Wait for POC detect done signal
WAIT_POC_DONE: begin
if (poc2lim_detect_done) begin
write_request = 1'b0;
poc_ready = 1'b0;
lim_nxt_state = WAIT_STG3;
end
end
// Wait for DQS to stop toggling before stage3 inc/dec
WAIT_STG3: begin
if (wait_cnt_done) begin
if (stg3_dec_r) begin
// Check for Stage 3 underflow and MMCM tap limit
if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_DEC;
else begin
stg3_dec = 1'b0;
stg3_inc2init_val = 1'b1;
lim_nxt_state = STAGE3_INC;
end
end else begin // Stage 3 being incremented
// Check for Stage 3 overflow and MMCM tap limit
if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_INC;
else begin
stg3_dec2init_val = 1'b1;
lim_nxt_state = STAGE3_DEC;
end
end
end
end
STAGE3_INC: begin
stg3_inc_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
STAGE3_DEC: begin
stg3_dec_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG3_INCDEC_WAIT: begin
stg3_dec_req = 1'b0;
stg3_inc_req = 1'b0;
if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
if (stg3_init_dec_r) begin
// Initial decrement of stage 3
if (stg3_tap_cnt > stg3_dec_val)
lim_nxt_state = STAGE3_DEC;
else begin
lim_nxt_state = WAIT_WR_REQ;
stg3_init_dec = 1'b0;
end
end else if (stg3_dec2init_val_r) begin
if (stg3_tap_cnt > stg3_init_val)
lim_nxt_state = STAGE3_DEC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else if (stg3_inc2init_val_r) begin
if (stg3_tap_cnt < stg3_inc_val)
lim_nxt_state = STAGE3_INC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else begin
lim_nxt_state = WAIT_WR_REQ;
end
end
end
// Check for overflow and underflow of stage2 taps
STAGE2_TAP_CHK: begin
if (stg3_dec2init_val_r) begin
// Increment stage 2 to write level tap value at the end of limit detection
if (stg2_tap_cnt < wl_po_fine_cnt)
lim_nxt_state = STAGE2_INC;
else begin
lim_nxt_state = PRECH_REQUEST;
end
end else if (stg3_inc2init_val_r) begin
// Decrement stage 2 to '0' to determine right limit
if (stg2_tap_cnt > 'd0)
lim_nxt_state = STAGE2_DEC;
else begin
lim_nxt_state = PRECH_REQUEST;
stg3_inc2init_val = 1'b0;
end
end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
// Initial increment to 63
lim_nxt_state = STAGE2_INC;
end else begin
lim_nxt_state = STG3_INCDEC_WAIT;
stg2_inc = 1'b0;
end
end
STAGE2_INC: begin
stg2_inc_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
STAGE2_DEC: begin
stg2_dec_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG2_INCDEC_WAIT: begin
stg2_inc_req = 1'b0;
stg2_dec_req = 1'b0;
if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
lim_nxt_state = STAGE2_TAP_CHK;
end
PRECH_REQUEST: begin
prech_req = 1'b1;
if (prech_done) begin
prech_req = 1'b0;
if (stg3_dec2init_val_r)
lim_nxt_state = LIMIT_DONE;
else
lim_nxt_state = WAIT_WR_REQ;
end
end
LIMIT_DONE: begin
done = 1'b1;
ktap_right = 1'b0;
stg3_dec2init_val = 1'b0;
lim_nxt_state = IDLE;
end
default: begin
lim_nxt_state = IDLE;
end
endcase
end
endmodule //mig_7_series_v2_3_ddr_phy_ocd_lim
|
module chan_fifo_reader
(reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and tx_q
input wire [31:0] adc_time ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is ready
output reg rdreq ; //actually an ack to the current fifodata
output reg skip ; //finish reading current packet
output reg [15:0] tx_q ; //top 16 bit output of fifodata
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
output reg underrun ;
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
output wire [14:0] debug;
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
`define JITTER 5
//Samples format
// 16 bits interleaved complex samples
`define QI16 4'b0
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter TIMESTAMP = 3'd2;
parameter WAIT = 3'd3;
parameter WAITSTROBE = 3'd4;
parameter SEND = 3'd5;
// Header format
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
/* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
always @(posedge tx_clock)
begin
if (reset)
begin
reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
end
else
begin
case (reader_state)
IDLE:
begin
/*
* reset all the variables and wait for a tx_strobe
* it is assumed that the ram connected to this fifo_reader
* is a short hand fifo meaning that the header to the next packet
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
/* Process header */
HEADER:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
begin
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 1;
reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
end
// Decide if we wait, send or discard samples
WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
// Outdated
if ((timestamp < adc_time) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
reader_state <= IDLE;
skip <= 1;
end
// Let's send it
else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
begin
trash <= 0;
reader_state <= WAITSTROBE;
end
else
reader_state <= WAIT;
end
else
reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
reader_state <= IDLE;
skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
case(samples_format)
`QI16:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
endcase
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_sqrt(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 11;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] datain;
wire is_fifo_in_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(datain), .valid_in(i_datain_valid),
.valid_out( is_fifo_in_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_in_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_stall) | !(is_fifo_in_valid);
acl_fp_sqrt_s5 sqrt_unit(
.enable(~is_stalled), .clock(clock), .dataa(datain), .result(o_dataout));
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
/*
File: axi_master.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_master (/*AUTOARG*/
// Outputs
awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
awvalid, wid, wdata, wstrb, wlast, wvalid, bready, arid, araddr,
arlen, arsize, arburst, arlock, arcache, arprot, arvalid, rready,
emesh_access_inb, emesh_write_inb, emesh_datamode_inb,
emesh_ctrlmode_inb, emesh_dstaddr_inb, emesh_srcaddr_inb,
emesh_data_inb, emesh_wr_wait_inb, emesh_rd_wait_inb, awqos, arqos,
// Inputs
aclk, eclk, reset, awready, wready, bid, bresp, bvalid, arready,
rid, rdata, rresp, rlast, rvalid, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
emesh_wr_wait_outb
);
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter STW = 8; //Number of strobes
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Write address channel
//########################
input awready; //write address ready
//########################
//# Write data channel
//########################
input wready; //write ready
//#########################
//# Write response channel
//#########################
input [MIDW-1:0] bid; //response ID tag
input [1:0] bresp; //write response
input bvalid;//write response valid
//########################
//# Read address channel
//########################
input arready;//read address ready
//########################
//# Read data channel
//########################
input [MIDW-1:0] rid; //read ID tag
input [MDW-1:0] rdata; //read data
input [1:0] rresp; //read response
input rlast; //read last, indicates the last transfer in burst
input rvalid;//read valid
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Write address channel
//########################
output [MIDW-1:0] awid; //write address ID
output [MAW-1:0] awaddr; //write address
output [3:0] awlen; //burst lenght (the number of data transfers)
output [2:0] awsize; //burst size (the size of each transfer)
output [1:0] awburst; //burst type
output [1:0] awlock; //lock type (atomic characteristics)
output [3:0] awcache; //memory type
output [2:0] awprot; //protection type
output awvalid; //write address valid
//########################
//# Write data channel
//########################
output [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
output [MDW-1:0] wdata; //write data
output [STW-1:0] wstrb; //write strobes
output wlast; //write last, indicates the last transfer in burst
output wvalid;//write valid
//########################
// Write response channel
//########################
output bready;//response ready
//########################
//# Read address channel
//########################
output [MIDW-1:0] arid; //read address ID
output [MAW-1:0] araddr; //read address
output [3:0] arlen; //burst lenght (the number of data transfers)
output [2:0] arsize; //burst size (the size of each transfer)
output [1:0] arburst; //burst type
output [1:0] arlock; //lock type (atomic characteristics)
output [3:0] arcache; //memory type
output [2:0] arprot; //protection type
output arvalid; //write address valid
//########################
//# Read data channel
//########################
output rready; //read ready
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//#######################################################################
//# The following features are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
// input buser; //user signal (AXI4 only)
// input ruser; //user signal (AXI4 only)
output [3:0] awqos; //quality of service (AXI4 only) default 4'b0000
// output [3:0] awregion;//region identifier (AXI4 only)
// output awuser; //user signal (AXI4 only)
// output wuser; //user signal (AXI4 only)
output [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
// output [3:0] arregion;//region identifier (AXI4 only)
// output aruser; //user signal (AXI4 only)
/*AUTOINPUT*/
/*AUTOWIRE*/
//############
//# Wires
//############
wire [MIDW-1:0] awid; //write address ID
wire [MAW-1:0] awaddr; //write address
wire [3:0] awlen; //burst lenght (the number of data transfers)
wire [2:0] awsize; //burst size (the size of each transfer)
wire [1:0] awburst; //burst type
wire [1:0] awlock; //lock type (atomic characteristics)
wire [3:0] awcache; //memory type
wire [2:0] awprot; //protection type
wire awvalid; //write address valid
wire [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
wire [MDW-1:0] wdata; //write data
wire [STW-1:0] wstrb; //write strobes
wire wlast; //write last, indicates the last transfer in burst
wire wvalid; //write valid
wire bready; //response ready
wire [MIDW-1:0] arid; //read address ID
wire [MAW-1:0] araddr; //read address
wire [3:0] arlen; //burst lenght (the number of data transfers)
wire [2:0] arsize; //burst size (the size of each transfer)
wire [1:0] arburst; //burst type
wire [1:0] arlock; //lock type (atomic characteristics)
wire [3:0] arcache; //memory type
wire [2:0] arprot; //protection type
wire arvalid; //write address valid
wire rready; //read ready
wire emesh_access_inb;
wire emesh_write_inb;
wire [1:0] emesh_datamode_inb;
wire [3:0] emesh_ctrlmode_inb;
wire [31:0] emesh_dstaddr_inb;
wire [31:0] emesh_srcaddr_inb;
wire [31:0] emesh_data_inb;
wire emesh_wr_wait_inb;
wire emesh_rd_wait_inb;
//#######################
//# Defaults
//#######################
assign awqos[3:0] = 4'b0000;
assign arqos[3:0] = 4'b0000;
//##################################
//# Master Write Port Instantiation
//##################################
axi_master_wr axi_master_wr(/*AUTOINST*/
// Outputs
.awid (awid[MIDW-1:0]),
.awaddr (awaddr[MAW-1:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[MIDW-1:0]),
.wdata (wdata[MDW-1:0]),
.wstrb (wstrb[STW-1:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.emesh_wr_wait_inb(emesh_wr_wait_inb),
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.awready (awready),
.wready (wready),
.bid (bid[MIDW-1:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.emesh_access_outb(emesh_access_outb),
.emesh_write_outb(emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]));
//##################################
//# Master Read Port Instantiation
//##################################
axi_master_rd axi_master_rd(/*AUTOINST*/
// Outputs
.arid (arid[MIDW-1:0]),
.araddr (araddr[MAW-1:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arburst (arburst[1:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.emesh_access_inb(emesh_access_inb),
.emesh_write_inb (emesh_write_inb),
.emesh_datamode_inb(emesh_datamode_inb[1:0]),
.emesh_ctrlmode_inb(emesh_ctrlmode_inb[3:0]),
.emesh_dstaddr_inb(emesh_dstaddr_inb[31:0]),
.emesh_srcaddr_inb(emesh_srcaddr_inb[31:0]),
.emesh_data_inb (emesh_data_inb[31:0]),
.emesh_rd_wait_inb(emesh_rd_wait_inb),
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.arready (arready),
.rid (rid[MIDW-1:0]),
.rdata (rdata[MDW-1:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
.emesh_access_outb(emesh_access_outb),
.emesh_write_outb(emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]),
.emesh_wr_wait_outb(emesh_wr_wait_outb));
endmodule // axi_master
|
`timescale 1ns / 1ps
module Altera_UP_PS2_Command_Out (
// Inputs
clk,
reset,
the_command,
send_command,
ps2_clk_posedge,
ps2_clk_negedge,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
command_was_sent,
error_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_101US = 5050;
parameter NUMBER_OF_BITS_FOR_101US = 13;
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001;
//parameter CLOCK_CYCLES_FOR_101US = 50;
//parameter NUMBER_OF_BITS_FOR_101US = 6;
//parameter COUNTER_INCREMENT_FOR_101US = 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter NUMBER_OF_BITS_FOR_15MS = 20;
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 100000;
parameter NUMBER_OF_BITS_FOR_2MS = 17;
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [7:0] the_command;
input send_command;
input ps2_clk_posedge;
input ps2_clk_negedge;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output reg command_was_sent;
output reg error_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [3:0] cur_bit;
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
// State Machine Registers
reg [2:0] ns_ps2_transmitter;
reg [2:0] s_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_transmitter <= PS2_STATE_0_IDLE;
else
s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
// Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1)
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
ps2_command <= 9'h000;
else if (s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else
begin
if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if (transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
cur_bit <= 4'h0;
else if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_was_sent <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if (send_command == 1'b0)
command_was_sent <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
error_communication_timed_out <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if (send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK =
(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
1'b0 :
1'bz;
assign PS2_DAT =
(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:13:12 02/27/2016
// Design Name: dataMemory
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab4/test_dataMem.v
// Project Name: lab4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: dataMemory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_dataMem;
// Inputs
reg clock_in;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg memRead;
// Outputs
wire [31:0] readData;
parameter PERIOD = 200;
// Instantiate the Unit Under Test (UUT)
dataMemory uut (
.clock_in(clock_in),
.address(address),
.writeData(writeData),
.readData(readData),
.memWrite(memWrite),
.memRead(memRead)
);
always #(PERIOD/2) clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
address = 0;
writeData = 0;
memWrite = 0;
memRead = 0;
// Wait 100 ns for global reset to finish
#185;
memWrite = 'b1;
address = 32'b00000000000000000000000000000111;
writeData = 32'b01111111111111111111111111111111;
// Add stimulus here
#250;
memRead = 'b1;
memWrite = 'b0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Table Based Fog
// File : de3d_tfog.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// The fog table generator consists of 3 pipeline stages which
// consist of the actual fog table lookups, the differencer,
// the fractional multiplier, and the final adder.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
/************************************************************************/
/************************************************************************/
module de3d_tfog
(
input de_clk, // Drawing engine clock
input hb_csn, // Chip select for fog unit
input hb_tfog_en, // Fog unit selector for HBI
input hb_wstrb, // Write strobe to access table
input [6:2] hb_addr, // Address to access the fog table
input [7:0] hb_ben, // Byte enables for the fog table
input [31:0] hb_din, // Data to the fog table
input [13:0] zvalue, // Z to be indexed, upper 16 bits
input pc_busy,
output [31:0] hb_dout, // Host data from the fog table
output [7:0] fog_factor // Fog factor to the fogging unit
);
reg [8:0] z_diff_d; /* pipeline delayed diff value */
reg [7:0] low_factor_d, low_factor_dd;
reg [7:0] fog_factor;
reg [7:0] zvalue_d; /* re-registered lower 10 bits of z */
reg [8:0] z_add_d; /* Value of Z to go into * */
wire [5:0] z_low, z_hi; /* Low and high Z values for table look ups */
wire [8:0] z_diff; /* 2's complement difference between */
/* Table z values */
wire [18:0] z_add; /* Value of Z to go into * */
wire [8:0] fog_factor_s; /* signed fog factor (sign always 0) */
wire [7:0] low_factor, /* Lower fog factor */
high_factor; /* High fog factor */
wire [7:0] fog64; /* Final fog entry in the table */
wire [7:0] high_factor_add;/* Take either the high_factor or fog64 */
/************************************************************************/
/* Pipeline Registers */
/************************************************************************/
always @(posedge de_clk) begin
if (!busy3) fog_factor = fog_factor_s[7:0];
if (!busy2) begin
z_add_d = z_add[18:10];
low_factor_dd = low_factor_d;
end
if (!pc_busy) begin
z_diff_d = z_diff;
low_factor_d = low_factor;
zvalue_d = zvalue[7:0];
end
end
/************************************************************************/
/* Calculate the high and low indices */
/************************************************************************/
assign z_low = zvalue[13:8]; // Low value is always the incoming z value
assign z_hi = z_low + 1; // High value is the incoming value + 1
// except when the incoming value is
// The largest table entry
assign high_factor_add = (&z_low) ? fog64 : high_factor;
/************************************************************************/
/* Fog table is the actual latch based cache which stores the fog values*/
/************************************************************************/
DED_FOG_TABLE FOG_TABLE
(
(~hb_csn && hb_tfog_en),
hb_wstrb,
hb_addr,
hb_ben,
hb_din,
z_low,
z_hi,
hb_dout,
low_factor,
high_factor,
fog64
);
/************************************************************************/
/* take the difference between low and high fog factors */
/************************************************************************/
assign z_diff = high_factor_add - low_factor;
/************************************************************************/
/* Multiply values together */
/************************************************************************/
MULT9SX10U MULT9sx10u (z_add, z_diff_d, {zvalue_d,2'b0});
/************************************************************************/
/* Find the final fog factor */
/************************************************************************/
assign fog_factor_s = {1'b0,low_factor_dd} + z_add_d;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_SYMBOL_V
`define SKY130_FD_SC_MS__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_SYMBOL_V
|
// $Id: c_err_rpt.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// error reporting module
//==============================================================================
module c_err_rpt
(clk, reset, active, errors_in, errors_out);
`include "c_constants.v"
// number of error inputs
parameter num_errors = 1;
// select mode of operation
parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// raw error inputs
input [0:num_errors-1] errors_in;
// registered and potentially held error outputs
output [0:num_errors-1] errors_out;
wire [0:num_errors-1] errors_out;
generate
if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_errors-1] errors_s, errors_q;
case(capture_mode)
`ERROR_CAPTURE_MODE_NO_HOLD:
begin
assign errors_s = errors_in;
end
`ERROR_CAPTURE_MODE_HOLD_FIRST:
begin
assign errors_s = ~|errors_q ? errors_in : errors_q;
end
`ERROR_CAPTURE_MODE_HOLD_ALL:
begin
assign errors_s = errors_q | errors_in;
end
endcase
c_dff
#(.width(num_errors),
.reset_type(reset_type))
errorsq
(.clk(clk),
.reset(reset),
.active(active),
.d(errors_s),
.q(errors_q));
assign errors_out = errors_q;
end
else
assign errors_out = {num_errors{1'b0}};
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off SHORTREAL
integer i;
reg [63:0] b;
shortreal r, r2;
integer cyc = 0;
realtime uninit;
initial if (uninit != 0.0) $stop;
initial begin
if (1_00_0.0_1 != 1000.01) $stop;
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
r = $bitstoshortreal($shortrealtobits(1.414));
if (r != 1.414) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
bit global_bit;
module t (clk);
input clk;
integer cyc=0;
typedef struct packed {
bit b1;
bit b0;
} strp_t;
typedef struct packed {
strp_t x1;
strp_t x0;
} strp_strp_t;
typedef union packed {
strp_t x1;
strp_t x0;
} unip_strp_t;
typedef bit [2:1] arrp_t;
typedef arrp_t [4:3] arrp_arrp_t;
typedef strp_t [4:3] arrp_strp_t;
typedef bit arru_t [2:1];
typedef arru_t arru_arru_t [4:3];
typedef arrp_t arru_arrp_t [4:3];
typedef strp_t arru_strp_t [4:3];
strp_t v_strp;
strp_strp_t v_strp_strp;
unip_strp_t v_unip_strp;
arrp_t v_arrp;
arrp_arrp_t v_arrp_arrp;
arrp_strp_t v_arrp_strp;
arru_t v_arru;
arru_arru_t v_arru_arru;
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
real v_real;
real v_arr_real [2];
string v_string;
typedef struct packed {
logic [31:0] data;
} str32_t;
str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
initial v_str32x2[0] = 32'hff;
initial v_str32x2[1] = 0;
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
v_strp <= ~v_strp;
v_strp_strp <= ~v_strp_strp;
v_unip_strp <= ~v_unip_strp;
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
v_real <= v_real + 0.1;
v_string <= "foo";
v_arr_real[0] <= v_arr_real[0] + 0.2;
v_arr_real[1] <= v_arr_real[1] + 0.3;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
v_arru_arrp[b] <= ~v_arru_arrp[b];
for (integer a=3; a<=4; a++) begin
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
v_str32x2[0] <= v_str32x2[0] - 1;
v_str32x2[1] <= v_str32x2[1] + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module p;
parameter PARAM = 1;
initial global_bit = 1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
for (i = 16; i > 0; i--)
if (mem0[i] !== i) begin
$write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i);
status = 1;
end
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_rx.v
// Version : 3.2
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
PCIeGen2x8If128_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
PCIeGen2x8If128_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter N = 1;
parameter AW = 32; // address width
parameter NMIO = 8; // IO data width
parameter DEF_CFG = 18'h1070; // for 104 bits
parameter DEF_CLK = 7;
localparam PW = 2*AW + 40; // standard packet
//clock, reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transactoin
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//########################################
//# BODY
//########################################
//wires
wire reg_access_in;
wire [PW-1:0] reg_packet_in;
wire reg_wait_in;
wire edma_access_in;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire irq; // From edma of edma.v
wire reg_access_out; // From edma of edma.v
wire [PW-1:0] reg_packet_out; // From edma of edma.v
wire reg_wait_out; // From edma of edma.v
// End of automatics
assign dut_active = 1'b1;
assign clkout = clk1;
//########################################
//# DECODE (SPLITTING CTRL+DATA)
//########################################
//hack: send to regfile if addr[31:20] is zero
assign edma_access_in = access_in & |packet_in[39:28];
assign reg_access_in = access_in & ~(|packet_in[39:28]);
assign reg_packet_in = packet_in;
assign reg_wait_in = wait_in;
//########################################
//# DUT: EDMA
//########################################
/*edma AUTO_TEMPLATE (
.clk (clk1),
.access_in (edma_access_in),
);
*/
edma #(.AW(AW))
edma (/*AUTOINST*/
// Outputs
.irq (irq),
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
.reg_wait_out (reg_wait_out),
.reg_access_out (reg_access_out),
.reg_packet_out (reg_packet_out[PW-1:0]),
// Inputs
.clk (clk1), // Templated
.nreset (nreset),
.access_in (edma_access_in), // Templated
.packet_in (packet_in[PW-1:0]),
.wait_in (wait_in),
.reg_access_in (reg_access_in),
.reg_packet_in (reg_packet_in[PW-1:0]),
.reg_wait_in (reg_wait_in));
endmodule // dut
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../common/hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
(** * Hoare: Hoare Logic *)
(* $Date: 2012-05-12 10:20:28 -0400 (Sat, 12 May 2012) $ *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the optional chapter
[Equiv]).
If we stopped here, we would still have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of
them are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively
obvious can sometimes be quite subtle -- or, in some cases,
actually even wrong!
We'll return to this theme later in the course when we discuss
_types_ and _type soundness_.
- We saw a couple of examples of _program verification_ -- using
the precise definition of Imp to prove formally that certain
particular programs (e.g., factorial and slow subtraction)
satisfied particular specifications of their behavior. *)
(** In this chapter, we'll take this last idea further. We'll
develop a reasoning system called _Floyd-Hoare Logic_ -- commonly
shortened to just _Hoare Logic_ -- in which each of the syntactic
constructs of Imp is equipped with a single, generic "proof rule"
that can be used to reason about programs involving this
construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a huge variety of tools that are now being
used to specify and verify real software systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that these specifications are met --
where by "compositional" we mean that the structure of proofs
directly mirrors the structure of the programs that they are
about. *)
(* ####################################################### *)
(** ** Assertions *)
(** If we're going to talk about specifications of programs, the
first thing we'll want is a way of making _assertions_ about
properties that hold at particular points during a program's
execution -- i.e., properties that may or may not be true of a
given state of the memory. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star (assertions) *)
(** Paraphrase the following assertions in English.
1) fun st => st X = 3
2) fun st => st X = x
3) fun st => st X <= st Y
4) fun st => st X = 3 \/ st X <= st Y
5) fun st => st Z * st Z <= x /\ ~ (((S (st Z)) * (S (st Z))) <= x)
6) fun st => True
7) fun st => False
*)
(* FILL IN HERE *)
(** [] *)
(** This way of writing assertions is formally correct -- it
precisely captures what we mean, and it is exactly what we will
use in Coq proofs. We'll also want a lighter, less formal
notation for discussing examples, since this one is a bit
heavy: (1) every single assertion that we ever write is going to
begin with [fun st => ]; and (2) this state [st] is the only one that
we ever use to look up variables (we will never need to talk about
two different memory states at the same time). So, when writing down
assertions informally, we'll make some simplifications:
drop the initial [fun st =>], and write just [X] instead of [st X]. *)
(** Informally, instead of writing
fun st => (st Z) * (st Z) <= x /\ ~ ((S (st Z)) * (S (st Z)) <= x)
we'll write just
Z * Z <= x /\ ~((S Z) * (S Z) <= x).
*)
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of specifying -- making claims about -- the
behavior of commands. *)
(** Since we've defined assertions as a way of making claims about the
properties of states, and since the behavior of a command is to
transform one state to another, it is natural to express claims
about commands in the following way:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates, then the final state is
guaranteed to satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the _postcondition_
of [c]. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (Traditionally, Hoare triples are written [{P} c {Q}], but single
braces are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
Open Scope hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context. The first notation -- with missing postcondition -- will
not actually be used for a while; it's just a placeholder for a
notation that we'll want to define later, when we discuss
decorated programs.) *)
(** **** Exercise: 1 star (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = x}} c {{X = x + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = x}}
c
{{Y = real_fact x}}.
6) {{True}}
c
{{(Z * Z) <= x /\ ~ (((S Z) * (S Z)) <= x)}}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 1 star (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability. We'll continue
doing so throughout the chapter.) *)
(** To get us warmed up, here are two simple facts about Hoare
triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Weakest Preconditions *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: it is perfectly valid, but it tells us
nothing useful. Since the precondition isn't satisfied by any
state, it doesn't describe any situations where we can use the
command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if
- [{{P}} c {{Q}}], and
- whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we
have [P' st] implies [P st] for all states [st]. *)
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** The second of the conditions above is essentially a form of
logical implication at the level of assertions. Because of the
frequency of its occurrence, it is useful to define a little
notation: *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
(** We will write [P ~~> Q] (in ASCII, [P ~][~> Q]) for [assert_implies
P Q]. *)
Notation "P ~~> Q" := (assert_implies P Q) (at level 80).
Notation "P <~~> Q" := (P ~~> Q /\ Q ~~> P) (at level 80).
(** **** Exercise: 1 star (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ ? }} SKIP {{ X = 5 }}
2) {{ ? }} X ::= Y + Z {{ X = 5 }}
3) {{ ? }} X ::= Y {{ X = Y }}
4) {{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ ? }}
X ::= 5
{{ X = 0 }}
6) {{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (is_wp_formal) *)
(** Weakest preconditions can be defined formally as follows: *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (forall st, P' st -> P st).
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
Even more generally, [a] is _any_ arithmetic expression and [Q] is
_any_ property of numbers, then
{{ Q(a) }} X ::= a {{ Q(X) }}
is a valid Hoare triple.
Rephrasing this a bit gives us the general Hoare rule for
assignment:
{{ Q where a is substituted for X }} X ::= a {{ Q }}
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) where X + 1 is substituted for X
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) where 3 is substituted for X
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) where 3 is substituted for X
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we begin with the notion of "substitution
in an assertion": *)
Definition assn_sub X a Q : Assertion :=
fun (st : state) =>
Q (update st X (aeval st a)).
(** We ask that [Q] holds for the state obtained by assigning [a] to
[X], i.e. the updated state in which [X] is bound to the result of
evaluating [a]. Since we've chosen to represent assertions using
Coq propositions, this is the only way we can "substitute" a
variable inside an assertion. *)
(** Now the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{assn_sub X a Q}} X::=a {{Q}}
*)
Theorem hoare_asgn : forall Q X a,
{{assn_sub X a Q}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{assn_sub X (ANum 3) (fun st => st X = 3)}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
{{ assn_sub X (X + 1) (X <= 5) }} X ::= X + 1 {{ X <= 5 }}
{{ assn_sub X 3 (0 <= X /\ X <= 5) }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [x] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => Q st /\ st X = x}}
X ::= a
{{fun st => Q st' /\ st X = aeval st' a }}
(where st' = update st X x)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y}, (forall (x: X), f x = g x) -> f = g) ->
forall x a Q,
{{fun st => Q st /\ st X = x}}
X ::= a
{{fun st => Q (update st X x) /\ st X = aeval (update st X x) a }}.
Proof.
intros functional_extensionality v a Q.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall P X a Q,
{{P}} (X ::= a) {{Q}} ->
P ~~> assn_sub X a Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{assn_sub X 3 (X = 3)}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is also valid, but it is not an instance of
[hoare_asgn] because [True] and [assn_sub X 3 (X = 3)] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We could capture this observation with the
following rule:
{{P'}} c {{Q}}
P <~~> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Generalizing this line of thought a bit further, if we can derive
[{{P}} c {{Q}}], it is valid to change [P] to [P'] as long as [P']
is strong enough to imply [P], and change [Q] to [Q'] as long as
[Q] implies [Q']. This observation is captured by two _Rules of
Consequence_.
{{P'}} c {{Q}}
P ~~> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ~~> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ~~> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ~~> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} =>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := assn_sub X (ANum 1) (fun st => st X = 1)).
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ~~> P'
Q' ~~> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ~~> P' ->
Q' ~~> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
intros st st' Hc HP.
apply HQ'Q. apply (Hht st st'). assumption.
apply HPP'. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] above, to make sure that all of the
metavariables in the premises to the [hoare_consequence_pre] rule
would be set to specific values; since [P'] doesn't appear in the
conclusion of [hoare_consequence_pre], the process of unifying the
conclusion with the current goal doesn't constrain [P'] to a
specific assertion.
This is a little annoying, both because the assertion is a bit
long and also because the very next thing we are going to do --
applying the [hoare_asgn] rule -- will tell us exactly what it
should be! We can use [eapply] instead of [apply] to tell Coq,
essentially, "Be patient: The missing part is going to be filled
in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H]
except that, instead of failing if unifying the goal with the
conclusion of [H] does not determine how to instantiate all
of the variables appearing in the premises of [H], [eapply H]
will replace these variables with _existential variables_
(written [?nnn]) as placeholders for expressions that will be
determined (by further unification) later in the proof.
In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq will
(rightfully) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP. Admitted.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
Trying to finish the proof with [Qed] instead of [Admitted] gives
an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>>
*)
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (normal) variables that did not
exist at the time the existential variable was created. *)
Lemma silly2 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP']. Admitted.
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Lemma silly2_fixed : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this decorated program into a formal proof:
{{ True }} =>
{{ 1 = 1 }}
X ::= 1;
{{ X = 1 }} =>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1); Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}} (X ::= (ANum 3); Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{True}}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches.
But, actually, we can say something more precise. In the "then"
branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule
gives us more information to work with when reasoning about the
behavior of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]).
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression, which
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies. simpl. intros st [_ H].
symmetry in H; apply beq_nat_eq in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies; simpl; intros st _. omega.
Qed.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars, recommended (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** We first extend the syntax of commands, and introduce the usual
notations. We use a separate module to prevent polluting the
global name space. *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** We now extend the evaluation relation to accommodate [IF1]
branches. What rule(s) need to be added to [ceval] to evaluate
one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** We repeat the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Now state and prove a theorem, [hoare_if1], that expresses an
appropriate Hoare logic proof rule for one-sided conditionals. Try
to come up with a rule that is both sound and as precise as
possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. Suppose
we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write
{{P}} WHILE b DO c END {{P}}.
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
{{P}} WHILE b DO c END {{P /\ ~b}}
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_.
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on He, because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just c *)
remember (WHILE b DO c END) as wcom.
ceval_cases (induction He) Case; try (inversion Heqwcom); subst.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption. Qed.
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. remember (ble_nat (st X) 2) as le. destruct le.
apply ex_falso_quodlibet. apply Hb; reflexivity.
symmetry in Heqle. apply ble_nat_false in Heqle. omega.
Qed.
(** We can also use the while rule to prove the following Hoare
triple, which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Actually, this result shouldn't be surprising. If we look back at
the definition of [hoare_triple], we can see that it asserts
something meaningful _only_ when the command terminates. *)
Print hoare_triple.
(** If the command doesn't terminate, we can prove anything we like
about the post-condition. Here's a more direct proof of the same
fact: *)
Theorem always_loop_hoare' : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
unfold hoare_triple. intros P Q st st' contra.
apply loop_never_stops in contra. inversion contra.
Qed.
(** Hoare rules that only talk about terminating commands are often
said to describe a logic of "partial" correctness. It is also
possible to give Hoare rules for "total" correctness, which build
in the fact that the commands terminate. However, in this course
we will focus only on partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state || update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following _valid_ Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
(** Like in the [hoare_asgn_weakest] exercise above, show that your
[havoc_pre] returns the weakest precondition. *)
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ~~> havoc_pre X Q.
Proof.
(* FILL IN HERE *) Admitted.
(* /SOLUTION *)
End Himp.
(** [] *)
(* ####################################################### *)
(** * Review of Hoare Logic *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{assn_sub X a Q}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ~~> P'
Q' ~~> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ -- the
structure of proofs exactly follows the structure of programs.
This fact suggests that we could record the essential ideas of
a proof informally (leaving out some low-level calculational
details) by decorating programs with appropriate assertions around
each statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} =>
{{ x = x }}
X ::= x;
{{ X = x }} =>
{{ X = x /\ z = z }}
Z ::= z;
{{ X = x /\ Z = z }} =>
{{ Z - X = z - x }}
WHILE X <> 0 DO
{{ Z - X = z - x /\ X <> 0 }} =>
{{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
{{ Z - (X - 1) = z - x }}
X ::= X - 1
{{ Z - X = z - x }}
END;
{{ Z - X = z - x /\ ~ (X <> 0) }} =>
{{ Z = z - x }} =>
{{ Z + 1 = z - x + 1 }}
Z ::= Z + 1
{{ Z = z - x + 1 }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally_ consistent with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
- The sequential composition of commands [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P where a is substituted for X }}
X ::= a
{{ P }}
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P/\b] and [P/\~b] and if its "then"
branch is locally consistent (with respect to [P/\b] and [Q])
and its "else" branch is locally consistent (with respect to
[P/\~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
- A while loop is locally consistent if its postcondition is
[P/\~b] (where [P] is its precondition) and if the pre- and
postconditions of its body are exactly [P/\b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
- A pair of assertions separated by [=>] is locally consistent if
the first implies the second (in all states):
{{ P }} =>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if the
decorations are correct is not fully mechanical and syntactic,
but it involves logical and maybe arithmetic reasoning.
*)
(* ####################################################### *)
(** * Sample Hoare Logic Proofs *)
(* ####################################################### *)
(** ** Example: Slow Subtraction *)
(** We've seen an Imp program for subtracting one number from another by
repeatedly subtracting one from each number until the one being
subtracted reaches zero.
Here is a full proof -- presented as a decorated program -- that this
program meets a natural specification:
(1) {{ X = x /\ Z = z }} =>
(2) {{ Z - X = z - x }}
WHILE X <> 0 DO
(3) {{ Z - X = z - x /\ X <> 0 }} =>
(4) {{ (Z - 1) - (X - 1) = z - x }}
Z ::= Z - 1;
(5) {{ Z - (X - 1) = z - x }}
X ::= X - 1
(6) {{ Z - X = z - x }}
END
(7) {{ Z - X = z - x /\ ~ (X <> 0) }} =>
(8) {{ Z = z - x }}
The decorations were constructed as follows:
- Begin with the undecorated program (the unnumbered lines).
- Add the specification -- i.e., the outer precondition (1) and
postcondition (8).
- Write down the invariant of the loop (6).
- Following the format dictated by the [hoare_while] rule, add
the final use of the rule of consequence -- the assertion in
line (7) and the check that (7) implies (8).
- Check that the loop invariant _is_ an invariant of the loop
body by using the assignment rule twice to push the invariant
backwards from the end of the loop body to the
beginning (line (5) and then line (4)), and then filling in
the rule of consequence asserting that the invariant plus the
fact that the loop guard is true (line (3)) implies line (4).
- Check that the invariant is established at the beginning of
the loop verifying that line (2) is implied by line (1).
As in most Hoare Logic proofs, the only challenging part of this
process is finding the right loop invariant. There is no
foolproof procedure for this, but a helpful heuristic is to begin
by assumimng that the loop invariant is exactly the desired
postcondition (i.e., that lines (6) and (8) are the same) and then
calculating a bit to find out why this assertion is _not_ an
invariant of the loop body.
In this case, it quickly becomes clear that assertion (8) is not
an invariant of the loop body because the loop body changes the
variable [Z], but (obviously) not the global constants [x] and
[z]. So we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. *)
(** From this informal proof, it is now easy to read off a formal
proof in terms of the Hoare rules: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= AMinus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
Definition subtract_slowly_invariant x z :=
fun st => minus (st Z) (st X) = minus z x.
Theorem subtract_slowly_correct : forall x z,
{{fun st => st X = x /\ st Z = z}}
subtract_slowly
{{fun st => st Z = minus z x}}.
Proof.
(* Note that we do NOT unfold the definition of hoare_triple
anywhere in this proof! The goal is to use only the Hoare
rules. Your proofs should do the same. *)
intros x z. unfold subtract_slowly.
(* First we need to transform the pre and postconditions so
that hoare_while will apply. In particular, the
precondition should be the loop invariant. *)
eapply hoare_consequence with (P' := subtract_slowly_invariant x z).
apply hoare_while.
Case "Loop body preserves invariant".
(* Split up the two assignments with hoare_seq - using eapply
lets us solve the second one immediately with hoare_asgn *)
eapply hoare_seq. apply hoare_asgn.
(* Now for the first assignment, transform the precondition
so we can use hoare_asgn *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Finally, we need to justify the implication generated by
hoare_consequence_pre (this bit of reasoning is elided in the
informal proof) *)
unfold subtract_slowly_invariant, assn_sub, update, bassn. simpl.
intros st [Inv GuardTrue].
(* Could alternatively do case analysis on
negb (beq_nat (st X) 0) here;
but SearchAbout reveals some nice lemmas *)
SearchAbout [negb true]. rewrite negb_true_iff in GuardTrue.
SearchAbout [beq_nat false]. apply beq_nat_false in GuardTrue.
omega. (* slow but effective! *)
(* Faster variant: rewrite <- Inv. clear Inv. omega. *)
Case "Initial state satisfies invariant".
(* This is the subgoal generated by the precondition part of our
first use of hoare_consequence. It's the first implication
written in the decorated program (though we elided the actual
proof there). *)
unfold subtract_slowly_invariant.
intros st [HX HZ]. omega.
Case "Invariant and negated guard imply postcondition".
(* This is the subgoal generated by the postcondition part of
out first use of hoare_consequence. This implication is
the one written after the while loop in the informal proof. *)
intros st [Inv GuardFalse].
unfold subtract_slowly_invariant in Inv.
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps again to find the right lemmas *)
SearchAbout [not true]. rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false]. rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true]. apply beq_nat_true in GuardFalse.
omega. Qed.
(* ####################################################### *)
(** ** Exercise: Reduce to Zero *)
(** **** Exercise: 2 stars (reduce_to_zero_correct) *)
(** Here is a while loop that is so simple it needs no invariant:
{{ True }}
WHILE X <> 0 DO
{{ True /\ X <> 0 }} =>
{{ True }}
X ::= X - 1
{{ True }}
END
{{ True /\ X = 0 }} =>
{{ X = 0 }}
Your job is to translate this proof to Coq. Refer to the
[slow_subtraction] example for ideas.
*)
Definition reduce_to_zero : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct :
{{fun st => True}}
reduce_to_zero
{{fun st => st X = 0}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z. *)
Definition add_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
Z ::= APlus (AId Z) (ANum 1);
X ::= AMinus (AId X) (ANum 1)
END.
(** **** Exercise: 3 stars (add_slowly_decoration) *)
(** Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (add_slowly_formal) *)
(** Now write down your specification of [add_slowly] formally, as a
Coq [Hoare_triple], and prove it valid. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here's another, slightly trickier example. Make sure you
understand the decorated program completely. You may find it
instructive to start with the bare program and try to fill in the
decorations yourself. Notice exactly where the condition [X<=x]
comes up. *)
(**
{{ X = x }} =>
{{ X = x /\ 0 = 0 }}
Y ::= 0;
{{ X = x /\ Y = 0 }} =>
{{ (Y=0 <-> ev (x-X)) /\ X<=x }}
WHILE X <> 0 DO
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ X<>0 }} =>
{{ (1-Y)=0 <-> ev (x-(X-1)) /\ X-1<=x }}
Y ::= 1 - Y;
{{ Y=0 <-> ev (x-(X-1)) /\ X-1<=x }}
X ::= X - 1
{{ Y=0 <-> ev (x-X) /\ X<=x }}
END
{{ (Y=0 <-> ev (x-X)) /\ X<=x /\ ~(X<>0) }} =>
{{ Y=0 <-> ev x }}
*)
(** And here is the formal version of this proof. Skim them,
but you do not need to understand every detail (though the details
are not actually very hard), since all the important ideas are
already in the informal version. *)
Definition find_parity : com :=
Y ::= (ANum 0);
WHILE (BNot (BEq (AId X) (ANum 0))) DO
Y ::= AMinus (ANum 1) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END.
Definition find_parity_invariant x :=
fun st =>
st X <= x /\ ((st Y = 0 /\ ev (x - st X))
\/ (st Y = 1 /\ ~ev (x - st X))).
(** We'll need the following lemma... *)
Lemma not_ev_ev_S_gen: forall n,
(~ ev n -> ev (S n)) /\
(~ ev (S n) -> ev (S (S n))).
Proof.
induction n as [| n'].
Case "n = 0".
split; intros H.
SCase "->".
apply ex_falso_quodlibet. apply H. apply ev_0.
SCase "<-".
apply ev_SS. apply ev_0.
Case "n = S n'".
inversion IHn' as [Hn HSn]. split; intros H.
SCase "->".
apply HSn. apply H.
SCase "<-".
apply ev_SS. apply Hn. intros contra.
apply H. apply ev_SS. apply contra. Qed.
Lemma not_ev_ev_S : forall n,
~ ev n -> ev (S n).
Proof.
intros n.
destruct (not_ev_ev_S_gen n) as [H _].
apply H.
Qed.
Theorem find_parity_correct : forall x,
{{fun st => st X = x}}
find_parity
{{fun st => st Y = 0 <-> ev x}}.
Proof.
intros x. unfold find_parity.
apply hoare_seq with (Q := find_parity_invariant x).
eapply hoare_consequence.
apply hoare_while with (P := find_parity_invariant x).
Case "Loop body preserves invariant".
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st [[Inv1 Inv2] GuardTrue].
unfold find_parity_invariant, bassn, assn_sub, aeval in *.
rewrite update_eq.
rewrite (update_neq Y X).
rewrite (update_neq X Y).
rewrite update_eq.
simpl in GuardTrue. destruct (st X).
inversion GuardTrue. simpl.
split. omega.
inversion Inv2 as [[H1 H2] | [H1 H2]]; rewrite H1;
[right|left]; (split; simpl; [omega |]).
apply ev_not_ev_S in H2.
replace (S (x - S n)) with (x-n) in H2 by omega.
rewrite <- minus_n_O. assumption.
apply not_ev_ev_S in H2.
replace (S (x - S n)) with (x - n) in H2 by omega.
rewrite <- minus_n_O. assumption.
reflexivity. reflexivity.
Case "Precondition implies invariant".
intros st H. assumption.
Case "Invariant implies postcondition".
unfold bassn, find_parity_invariant. simpl.
intros st [[Inv1 Inv2] GuardFalse].
destruct (st X).
split; intro.
inversion Inv2.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
assumption.
inversion H0 as [H0' _]. rewrite H in H0'. inversion H0'.
inversion Inv2.
inversion H0. assumption.
inversion H0 as [_ H1]. replace (x-0) with x in H1 by omega.
apply ex_falso_quodlibet. apply H1. assumption.
apply ex_falso_quodlibet. apply GuardFalse. reflexivity.
Case "invariant established before loop".
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H.
unfold assn_sub, find_parity_invariant, update. simpl.
subst.
split.
omega.
replace (st X - st X) with 0 by omega.
left. split. reflexivity.
apply ev_0. Qed.
(** **** Exercise: 2 stars (wrong_find_parity_invariant) *)
(** A plausible first attempt at stating an invariant for [find_parity]
is the following. *)
Definition find_parity_invariant' x :=
fun st =>
(st Y) = 0 <-> ev (x - st X).
(** Why doesn't this work? (Hint: Don't waste time trying to answer
this exercise by attempting a formal proof and seeing where it
goes wrong. Just think about whether the loop body actually
preserves the property.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** Here's another example, starting with the formal version this
time. *)
Definition sqrt_loop : com :=
WHILE BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X) DO
Z ::= APlus (ANum 1) (AId Z)
END.
Definition sqrt_com : com :=
Z ::= ANum 0;
sqrt_loop.
Definition sqrt_spec (x : nat) : Assertion :=
fun st =>
((st Z) * (st Z)) <= x
/\ ~ (((S (st Z)) * (S (st Z))) <= x).
Definition sqrt_inv (x : nat) : Assertion :=
fun st =>
st X = x
/\ ((st Z) * (st Z)) <= x.
Theorem random_fact_1 : forall st,
(S (st Z)) * (S (st Z)) <= st X ->
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st.
Proof.
intros st Hle. unfold bassn. simpl.
destruct (st X) as [|x'].
Case "st X = 0".
inversion Hle.
Case "st X = S x'".
simpl in Hle. apply le_S_n in Hle.
remember (ble_nat (plus (st Z)
((st Z) * (S (st Z)))) x')
as ble.
destruct ble. reflexivity.
symmetry in Heqble. apply ble_nat_false in Heqble.
unfold not in Heqble. apply Heqble in Hle. inversion Hle.
Qed.
Theorem random_fact_2 : forall st,
bassn (BLe (AMult (APlus (ANum 1) (AId Z))
(APlus (ANum 1) (AId Z)))
(AId X)) st ->
aeval st (APlus (ANum 1) (AId Z))
* aeval st (APlus (ANum 1) (AId Z))
<= st X.
Proof.
intros st Hble. unfold bassn in Hble. simpl in *.
destruct (st X) as [| x'].
Case "st X = 0".
inversion Hble.
Case "st X = S x'".
apply ble_nat_true in Hble. omega. Qed.
Theorem sqrt_com_correct : forall x,
{{fun st => True}} (X ::= ANum x; sqrt_com) {{sqrt_spec x}}.
Proof.
intros x.
apply hoare_seq with (Q := fun st => st X = x).
Case "sqrt_com".
unfold sqrt_com.
apply hoare_seq with (Q := fun st => st X = x
/\ st Z = 0).
SCase "sqrt_loop".
unfold sqrt_loop.
eapply hoare_consequence.
apply hoare_while with (P := sqrt_inv x).
SSCase "loop preserves invariant".
eapply hoare_consequence_pre.
apply hoare_asgn. intros st H.
unfold assn_sub. unfold sqrt_inv in *.
inversion H as [[HX HZ] HP]. split.
SSSCase "X is preserved".
rewrite update_neq; try assumption; try reflexivity.
SSSCase "Z is updated correctly".
rewrite (update_eq (aeval st (APlus (ANum 1) (AId Z))) Z st).
subst. apply random_fact_2. assumption.
SSCase "invariant is true initially".
intros st H. inversion H as [HX HZ].
unfold sqrt_inv. split. assumption.
rewrite HZ. simpl. omega.
SSCase "after loop, spec is satisfied".
intros st H. unfold sqrt_spec.
inversion H as [HX HP].
unfold sqrt_inv in HX. inversion HX as [HX' Harith].
split. assumption.
intros contra. apply HP. clear HP.
simpl. simpl in contra.
apply random_fact_1. subst x. assumption.
SCase "Z set to 0".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st HX.
unfold assn_sub. split.
rewrite update_neq. assumption. reflexivity.
rewrite update_eq. reflexivity.
Case "assignment of X".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H.
unfold assn_sub. rewrite update_eq. reflexivity. Qed.
(** **** Exercise: 3 stars (sqrt_informal) *)
(** Write an informal decorated program corresponding to this formal
correctness proof. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
Module Factorial.
(** Recall the mathematical factorial function... *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** ... and the Imp program that we wrote to calculate factorials: *)
Definition fact_body : com :=
Y ::= AMult (AId Y) (AId Z);
Z ::= AMinus (AId Z) (ANum 1).
Definition fact_loop : com :=
WHILE BNot (BEq (AId Z) (ANum 0)) DO
fact_body
END.
Definition fact_com : com :=
Z ::= (AId X);
Y ::= ANum 1;
fact_loop.
(** **** Exercise: 3 stars, optional (fact_informal) *)
(** Decorate the [fact_com] program to show that it satisfies the
specification given by the pre and postconditions below. As
usual, feel free to elide the algebraic reasoning about
arithmetic, the less-than relation, etc., that is formally
required by the rule of consequence:
(* FILL IN HERE *)
{{ X = x }}
Z ::= X;
Y ::= 1;
WHILE Z <> 0 DO
Y ::= Y * Z;
Z ::= Z - 1
END
{{ Y = real_fact x }}
*)
(** [] *)
(** **** Exercise: 4 stars, optional (fact_formal) *)
(** Prove formally that fact_com satisfies this specification,
using your informal proof as a guide. You may want to state
the loop invariant separately (as we did in the examples). *)
Theorem fact_com_correct : forall x,
{{fun st => st X = x}} fact_com
{{fun st => st Y = real_fact x}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Factorial.
(* ####################################################### *)
(** * Formalizing Decorated Programs (Optional) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others.
In this optional section, we show that this informal presentation
style can actually be made completely formal. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'=>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '=>' {{ P }}"
:= (DCPost d P)
(at level 91, right associativity) : dcom_scope.
Notation " d ; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [=>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ ~bassn (BNot (BEq (AId X) (ANum 0))) st}} =>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** We can define a similar function that extracts the "initial
precondition" from a decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]).
Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs.
(Strictly speaking, we need to massage the informal rules a little
bit to add some uses of the rule of consequence, but the
correspondence should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ~~> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ~~> assn_sub X a Q)
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ~~> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ~~> P2)
/\ (Q = post d1) /\ (Q = post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ~~> post d)
/\ (Pbody = (fun st => post d st /\ bassn b st))
/\ (Ppost = (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ~~> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ~~> Q)
end.
(** And now, the key theorem, which captures the claim that the
[verification_conditions] function does its job correctly. Not
surprisingly, we need all of the Hoare Logic rules in the
proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [Hd1 [Hd2 [HThen HElse]]]]]; clear H.
subst.
apply hoare_if.
eapply hoare_consequence_pre. apply IHd1. eassumption. assumption.
rewrite Hd2.
eapply hoare_consequence_pre. apply IHd2. eassumption. assumption.
Case "While".
inversion H as [Hpre [Hbody [Hpost Hd]]]; subst; clear H.
eapply hoare_consequence_pre.
apply hoare_while with (P := post d).
apply IHd. apply Hd.
assumption.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(* ====>
= (((fun _ : state => True) ~~> (fun _ : state => True)) /\
((fun _ : state => True) ~~> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ~~>
assn_sub X (AMinus (AId X) (ANum 1)) (fun _ : state => True)) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ~~>
(fun st : state => st X = 0) *)
(** We can certainly work with them using just the tactics we have so
far, but we can make things much smoother with a bit of
automation. We first define a custom [verify] tactic that applies
splitting repeatedly to turn all the conjunctions into separate
subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| reflexivity]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (x:nat) (z:nat) : dcom := (
{{ fun st => st X = x /\ st Z = z }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = z - x
/\ bassn (BNot (BEq (AId X) (ANum 0))) st }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = z - x }} ;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = z - x }}
END
{{ fun st => st Z
- st X
= z - x
/\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st }}
=>
{{ fun st => st Z = z - x }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall x z,
dec_correct (subtract_slowly_dec x z).
Proof. intros x z. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, optional (slow_assignment_dec) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until it
hits [0], incrementing [Y] at each step.
Here is an informal decorated program that implements this idea
given a parameter [x]: *)
(**
{{ True }}
X ::= x
{{ X = x }} ;
Y ::= 0
{{ X = x /\ Y = 0 }} ;
WHILE X <> 0 DO
{{ X + Y = x /\ X > 0 }}
X ::= X - 1
{{ Y + X + 1 = x }} ;
Y ::= Y + 1
{{ Y + X = x }}
END
{{ Y = x /\ X = 0 }}
*)
(** Write a corresponding formal decorated program (parametrized by x)
and prove it correct. *)
Example slow_assignment_dec (x:nat) : dcom :=
(* FILL IN HERE *) admit.
Theorem slow_assignment_dec_correct : forall x,
dec_correct (slow_assignment_dec x).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
Imp program that implements the factorial function, and prove it
correct. *)
(* FILL IN HERE *)
(** [] *)
Definition div_mod_dec (a b : nat) : dcom := (
{{ fun st => True }} =>
{{ fun st => b * 0 + a = a }}
X ::= ANum a
{{ fun st => b * 0 + st X = a }};
Y ::= ANum 0
{{ fun st => b * st Y + st X = a }};
WHILE (BLe (ANum b) (AId X)) DO
{{ fun st => b * st Y + st X = a /\ (bassn (BLe (ANum b) (AId X)) st) }} =>
{{ fun st => b * (st Y + 1) + (st X - b) = a }}
X ::= AMinus (AId X) (ANum b)
{{ fun st => b * (st Y + 1) + st X = a }};
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => b * st Y + st X = a }}
END
{{ fun st => b * st Y + st X = a /\ ~(bassn (BLe (ANum b) (AId X)) st) }} =>
{{ fun st => b * st Y + st X = a /\ (st X < b) }}
)%dcom.
Theorem div_mod_dec_correct : forall a b,
dec_correct (div_mod_dec a b).
Proof.
intros a b. verify.
Case "1". apply ble_nat_true in H0. rewrite mult_plus_distr_l. omega.
Case "2". apply ble_nat_false in H0. omega.
(* more automation would help here *)
Qed.
|
// This VGA renderer is currently configured to display 800x640@65Hz, given a 32.4MHz pixel clock
// These specs are, I think, good to drive the 5" display from Adafruit @ http://www.adafruit.com/products/2110
// Current DAC resistors are: 220+22, 510+22, 1K+68, 1.5K+680, 3.5K+560+100, 6.8K+1.5K+220, 15K+2.2K, 33K+1K+180
// These values require VCCIO bank setting of 3.3V LVTTL; be sure to change the I/O standard for these pins!
// Pin configuration is currently:
// HSYNC - E9 - GPIO_023 - GPIO-0 pin 28 connects to VGA pin 13
// VSYNC - F8 - GPIO_021 - GPIO-0 pin 26 connects to VGA pin 14
// GND - GPIO-0 pin 30 connects to VGA pins 5, 6, 7, 8, and 10.
// RED 0..7 (3.3V LVTTL)
// D3, C3, A3, B4, B5, A2, B3, A4
// GPIO_00, GPIO_01, GPIO_03, GPIO_05, GPIO_07, GPIO_02, GPIO_04, GPIO_06
// GPIO-0 pins 2, 4, 6, 8, 10, 5, 7, 9
// GREEN 0..7 (3.3V LVTTL)
// D5, A6, D6, C6, E6, B7, A7, C8
// GPIO_09, GPIO_011, GPIO_013, GPIO_015, GPIO_017, GPIO_012, GPIO_014, GPIO_016
// GPIO-0 pins 14, 16, 18, 20, 22, 17, 19, 21
// BLUE 0..7 (3.3V LVTTL)
// D9, E10, B11, D11, B12, C11, A12, D12
// GPIO_025, GPIO_027, GPIO_029, GPIO_031, GPIO_033, GPIO_028, GPIO_030, GPIO_032
// GPIO-0 pins 32, 34, 36, 38, 40, 35, 37, 39
//
module vga_renderer
#(parameter WIDTH = 800, // Visible horizontal pixels
H_FRONT_PORCH = 32, // hsync timing
H_SYNC = 120, // ..
H_BACK_PORCH = 32, // ..
HEIGHT = 480, // Visible vertical pixels
V_FRONT_PORCH = 8, // vsync timing
V_SYNC = 5, // ..
V_BACK_PORCH = 13) // ..
(
// vga_clk needs to match your monitor and timing specifications
input vga_clk,
// active low reset
input reset_n,
// 8 bit color digital inputs
input [7:0] red,
input [7:0] green,
input [7:0] blue,
// 8 bit color digital outputs
output [7:0] vga_red,
output [7:0] vga_green,
output [7:0] vga_blue,
// vga sync signals
output vga_hsync,
output vga_vsync,
// framebuffer signal - fb_vblank goes high when vsync starts and should be used to setup the frame buffer for the next render pass
// and the next pixel should be available every vga_clk when not in blanking (hblank or vblank)
// so you have (PIXELS_PER_LINE*(V_BACK_PORCH+V_SYNC+V_FRONT_PORCH)) vga clock cycles to prepare your framebuffer for reading
output fb_hblank,
output fb_vblank
);
localparam PIXELS_PER_LINE = WIDTH + H_BACK_PORCH + H_SYNC + H_FRONT_PORCH;
localparam LINES_PER_FRAME = HEIGHT + V_BACK_PORCH + V_SYNC + V_FRONT_PORCH;
localparam XBITS = $clog2(PIXELS_PER_LINE);
localparam YBITS = $clog2(LINES_PER_FRAME);
reg [XBITS-1:0] x_pos;
wire x_max = (x_pos == (PIXELS_PER_LINE - 1));
reg [YBITS-1:0] y_pos;
wire y_max = (y_pos == (LINES_PER_FRAME - 1));
reg hsync;
assign vga_hsync = ~hsync;
reg vsync;
assign vga_vsync = ~vsync;
assign fb_vblank = (y_pos >= HEIGHT);
assign fb_hblank = (x_pos >= WIDTH);
always @ (posedge vga_clk or negedge reset_n) begin
if(~reset_n) begin
x_pos <= 0;
y_pos <= 0;
hsync <= 1'b0;
vsync <= 1'b0;
end else begin
if(x_max) begin
x_pos <= 0;
if(y_max) begin
y_pos <= 0;
end else begin
y_pos <= y_pos + 1;
end
end else begin
x_pos <= x_pos + 1;
end
if(x_pos == ((WIDTH + H_FRONT_PORCH) - 1)) hsync <= 1'b1;
else if(x_pos == ((WIDTH + H_FRONT_PORCH + H_SYNC) - 1)) hsync <= 1'b0;
if(y_pos == ((HEIGHT + V_FRONT_PORCH) - 1)) vsync <= 1'b1;
else if(y_pos == ((HEIGHT + V_FRONT_PORCH + V_SYNC) - 1)) vsync <= 1'b0;
end
end
assign vga_red = (x_pos < WIDTH && y_pos < HEIGHT) ? red : 8'b0;
assign vga_green = (x_pos < WIDTH && y_pos < HEIGHT) ? green : 8'b0;
assign vga_blue = (x_pos < WIDTH && y_pos < HEIGHT) ? blue : 8'b0;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "wb_master32.v" ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Miha Dolenc ([email protected]) ////
//// ////
//// All additional information is available in the README.pdf ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
// Revision 1.1 2002/07/29 11:25:20 mihad
// Adding test bench for memory interface
//
// Revision 1.1 2002/02/01 13:39:43 mihad
// Initial testbench import. Still under development
//
//
`include "wb_model_defines.v"
`include "timescale.v"
module WB_MASTER32
(
CLK_I,
RST_I,
TAG_I,
TAG_O,
ACK_I,
ADR_O,
CYC_O,
DAT_I,
DAT_O,
ERR_I,
RTY_I,
SEL_O,
STB_O,
WE_O,
CAB_O
);
input CLK_I;
input RST_I;
input `WB_TAG_TYPE TAG_I;
output `WB_TAG_TYPE TAG_O;
input ACK_I;
output `WB_ADDR_TYPE ADR_O;
output CYC_O;
input `WB_DATA_TYPE DAT_I;
output `WB_DATA_TYPE DAT_O;
input ERR_I;
input RTY_I;
output `WB_SEL_TYPE SEL_O;
output STB_O;
output WE_O;
output CAB_O ;
// period length
real Tp ;
reg `WB_ADDR_TYPE ADR_O;
reg `WB_SEL_TYPE SEL_O;
reg `WB_TAG_TYPE TAG_O;
reg CYC_O;
reg WE_O;
reg `WB_DATA_TYPE DAT_O;
reg CAB_O ;
reg STB_O ;
// variable used for indication on whether cycle was already started
reg in_use ;
// because of non-blocking assignments CYC_O is not sufficient indicator for cycle starting - this var is used in its place
reg cycle_in_progress ;
// same goes for CAB_O signal
reg cab ;
reg we ;
task start_cycle ;
input is_cab ;
input write ;
output ok ; // ok indicates to the caller that cycle was started succesfully - if not, caller must take appropriate action
begin:main
ok = 1 ;
// just check if valid value is provided for CAB_O signal (no x's or z's allowed)
if ( (is_cab !== 1'b0) && (is_cab !== 1'b1) )
begin
$display("*E, invalid CAB value for cycle! Requested CAB_O value = %b, Time %t ", is_cab, $time) ;
ok = 0 ;
disable main ;
end
if ( (cycle_in_progress === 1) || (CYC_O === 1))
begin
// cycle was previously started - allow cycle to continue if CAB and WE values match
$display("*W, cycle already in progress when start_cycle routine was called! Time %t ", $time) ;
if ((CAB_O !== is_cab) || (WE_O !== write) )
begin
ok = 0 ;
if ( is_cab === 1 )
$display("*E, cab cycle start attempted when non-cab cycle was in progress! Time %t", $time) ;
else
$display("*E, non-cab cycle start attempted when cab cycle was in progress! Time %t", $time) ;
if ( we === 1 )
$display("*E, write cycle start attempted when read cycle was in progress! Time %t", $time) ;
else
$display("*E, read cycle start attempted when write cycle was in progress! Time %t", $time) ;
disable main ;
end
end
CYC_O <= #(Tp - `Tsetup) 1'b1 ;
CAB_O <= #(Tp - `Tsetup) is_cab ;
WE_O <= #(Tp - `Tsetup) write ;
// this non-blocking assignments are made to internal variables, so read and write tasks can be called immediately after cycle start task
cycle_in_progress = 1'b1 ;
cab = is_cab ;
we = write ;
end
endtask //start_cycle
task end_cycle ;
begin
if ( CYC_O !== 1'b1 )
$display("*W, end_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;
CYC_O <= #`Thold 1'b0 ;
CAB_O <= #`Thold 1'b0 ;
cycle_in_progress = 1'b0 ;
end
endtask //end_cycle
task modify_cycle ;
begin
if ( CYC_O !== 1'b1 )
$display("*W, modify_cycle routine called when CYC_O value was %b! Time %t ", CYC_O, $time) ;
we = ~we ;
WE_O <= #(Tp - `Tsetup) we ;
end
endtask //modify_cycle
task wbm_read ;
input `READ_STIM_TYPE input_data ;
inout `READ_RETURN_TYPE output_data ;
reg `WB_ADDR_TYPE address ;
reg `WB_DATA_TYPE data ;
reg `WB_SEL_TYPE sel ;
reg `WB_TAG_TYPE tag ;
integer num_of_cyc ;
begin:main
output_data`TB_ERROR_BIT = 1'b0 ;
// check if task was called before previous call to read or write finished
if ( in_use === 1 )
begin
$display("*E, wbm_read routine re-entered or called concurently with write routine! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
if ( cycle_in_progress !== 1 )
begin
$display("*E, wbm_read routine called without start_cycle routine being called first! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
if ( we !== 0 )
begin
$display("*E, wbm_read routine called after write cycle was started! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
// this branch contains timing controls - claim the use of WISHBONE
in_use = 1 ;
num_of_cyc = `WAIT_FOR_RESPONSE ;
// assign data outputs
ADR_O <= #(Tp - `Tsetup) input_data`READ_ADDRESS ;
SEL_O <= #(Tp - `Tsetup) input_data`READ_SEL ;
TAG_O <= #(Tp - `Tsetup) input_data`READ_TAG_STIM ;
// assign control output
STB_O <= #(Tp - `Tsetup) 1'b1 ;
output_data`CYC_ACK = 0 ;
output_data`CYC_RTY = 0 ;
output_data`CYC_ERR = 0 ;
@(posedge CLK_I) ;
output_data`CYC_ACK = ACK_I ;
output_data`CYC_RTY = RTY_I ;
output_data`CYC_ERR = ERR_I ;
while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
begin
@(posedge CLK_I) ;
output_data`CYC_ACK = ACK_I ;
output_data`CYC_RTY = RTY_I ;
output_data`CYC_ERR = ERR_I ;
num_of_cyc = num_of_cyc - 1 ;
end
output_data`READ_DATA = DAT_I ;
output_data`READ_TAG_RET = TAG_I ;
if ( output_data`CYC_RESPONSE === 0 )
begin
$display("*W, Terminating read cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
end
if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;
STB_O <= #`Thold 1'b0 ;
ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;
in_use = 0 ;
end
endtask // wbm_read
task wbm_write ;
input `WRITE_STIM_TYPE input_data ;
inout `WRITE_RETURN_TYPE output_data ;
reg `WB_ADDR_TYPE address ;
reg `WB_DATA_TYPE data ;
reg `WB_SEL_TYPE sel ;
reg `WB_TAG_TYPE tag ;
integer num_of_cyc ;
begin:main
output_data`TB_ERROR_BIT = 1'b0 ;
// check if task was called before previous call to read or write finished
if ( in_use === 1 )
begin
$display("*E, wbm_write routine re-entered or called concurently with read routine! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
if ( cycle_in_progress !== 1 )
begin
$display("*E, wbm_write routine called without start_cycle routine being called first! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
if ( we !== 1 )
begin
$display("*E, wbm_write routine after read cycle was started! Time %t ", $time) ;
output_data`TB_ERROR_BIT = 1'b1 ;
disable main ;
end
// this branch contains timing controls - claim the use of WISHBONE
in_use = 1 ;
num_of_cyc = `WAIT_FOR_RESPONSE ;
ADR_O <= #(Tp - `Tsetup) input_data`WRITE_ADDRESS ;
DAT_O <= #(Tp - `Tsetup) input_data`WRITE_DATA ;
SEL_O <= #(Tp - `Tsetup) input_data`WRITE_SEL ;
TAG_O <= #(Tp - `Tsetup) input_data`WRITE_TAG_STIM ;
STB_O <= #(Tp - `Tsetup) 1'b1 ;
output_data`CYC_ACK = 0 ;
output_data`CYC_RTY = 0 ;
output_data`CYC_ERR = 0 ;
@(posedge CLK_I) ;
output_data`CYC_ACK = ACK_I ;
output_data`CYC_RTY = RTY_I ;
output_data`CYC_ERR = ERR_I ;
while ( (num_of_cyc > 0) && (output_data`CYC_RESPONSE === 0) )
begin
@(posedge CLK_I) ;
output_data`CYC_ACK = ACK_I ;
output_data`CYC_RTY = RTY_I ;
output_data`CYC_ERR = ERR_I ;
num_of_cyc = num_of_cyc - 1 ;
end
output_data`WRITE_TAG_RET = TAG_I ;
if ( output_data`CYC_RESPONSE === 0 )
begin
$display("*W, Terminating write cycle because no response was received in %d cycles! Time %t ", `WAIT_FOR_RESPONSE, $time) ;
end
if ( output_data`CYC_ACK === 1 && output_data`CYC_RTY === 0 && output_data`CYC_ERR === 0 )
output_data`CYC_ACTUAL_TRANSFER = output_data`CYC_ACTUAL_TRANSFER + 1 ;
ADR_O <= #`Thold {`WB_ADDR_WIDTH{1'bx}} ;
DAT_O <= #`Thold {`WB_DATA_WIDTH{1'bx}} ;
SEL_O <= #`Thold {`WB_SEL_WIDTH{1'bx}} ;
TAG_O <= #`Thold {`WB_TAG_WIDTH{1'bx}} ;
STB_O <= #`Thold 1'b0 ;
in_use = 0 ;
end
endtask //wbm_write
initial
begin
Tp = 1 / `WB_FREQ ;
in_use = 0 ;
cycle_in_progress = 0 ;
cab = 0 ;
ADR_O <= {`WB_ADDR_WIDTH{1'bx}} ;
DAT_O <= {`WB_DATA_WIDTH{1'bx}} ;
SEL_O <= {`WB_SEL_WIDTH{1'bx}} ;
TAG_O <= {`WB_TAG_WIDTH{1'bx}} ;
CYC_O <= 1'b0 ;
STB_O <= 1'b0 ;
CAB_O <= 1'b0 ;
WE_O <= 1'b0 ;
if ( `Tsetup > Tp || `Thold >= Tp )
begin
$display("Either Tsetup or Thold values for WISHBONE BFMs are too large!") ;
$stop ;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file generates the Incremental Compilation Wrapper that is used for simulation and synthesis
//*/
module pcie_4243_hip_s4gx_gen2_x8_128_icm (
// inputs:
app_int_sts_icm,
cal_blk_clk,
clk250_in,
cpl_err_icm,
cpl_pending_icm,
gxb_powerdown,
msi_stream_data0,
msi_stream_valid0,
npor,
pex_msi_num_icm,
phystatus_ext,
pipe_mode,
pll_powerdown,
pme_to_cr,
reconfig_clk,
reconfig_togxb,
refclk,
rstn,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rx_in4,
rx_in5,
rx_in6,
rx_in7,
rx_stream_mask0,
rx_stream_ready0,
rxdata0_ext,
rxdata1_ext,
rxdata2_ext,
rxdata3_ext,
rxdata4_ext,
rxdata5_ext,
rxdata6_ext,
rxdata7_ext,
rxdatak0_ext,
rxdatak1_ext,
rxdatak2_ext,
rxdatak3_ext,
rxdatak4_ext,
rxdatak5_ext,
rxdatak6_ext,
rxdatak7_ext,
rxelecidle0_ext,
rxelecidle1_ext,
rxelecidle2_ext,
rxelecidle3_ext,
rxelecidle4_ext,
rxelecidle5_ext,
rxelecidle6_ext,
rxelecidle7_ext,
rxstatus0_ext,
rxstatus1_ext,
rxstatus2_ext,
rxstatus3_ext,
rxstatus4_ext,
rxstatus5_ext,
rxstatus6_ext,
rxstatus7_ext,
rxvalid0_ext,
rxvalid1_ext,
rxvalid2_ext,
rxvalid3_ext,
rxvalid4_ext,
rxvalid5_ext,
rxvalid6_ext,
rxvalid7_ext,
test_in,
tx_stream_data0,
tx_stream_valid0,
// outputs:
app_int_sts_ack_icm,
cfg_busdev_icm,
cfg_devcsr_icm,
cfg_linkcsr_icm,
cfg_msicsr_icm,
cfg_prmcsr_icm,
clk250_out,
dlup_exit,
hotrst_exit,
l2_exit,
lane_width_code,
msi_stream_ready0,
phy_sel_code,
pme_to_sr,
powerdown_ext,
reconfig_fromgxb,
ref_clk_sel_code,
rx_stream_data0,
rx_stream_valid0,
rxpolarity0_ext,
rxpolarity1_ext,
rxpolarity2_ext,
rxpolarity3_ext,
rxpolarity4_ext,
rxpolarity5_ext,
rxpolarity6_ext,
rxpolarity7_ext,
test_out_icm,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
tx_out4,
tx_out5,
tx_out6,
tx_out7,
tx_stream_cred0,
tx_stream_mask0,
tx_stream_ready0,
txcompl0_ext,
txcompl1_ext,
txcompl2_ext,
txcompl3_ext,
txcompl4_ext,
txcompl5_ext,
txcompl6_ext,
txcompl7_ext,
txdata0_ext,
txdata1_ext,
txdata2_ext,
txdata3_ext,
txdata4_ext,
txdata5_ext,
txdata6_ext,
txdata7_ext,
txdatak0_ext,
txdatak1_ext,
txdatak2_ext,
txdatak3_ext,
txdatak4_ext,
txdatak5_ext,
txdatak6_ext,
txdatak7_ext,
txdetectrx_ext,
txelecidle0_ext,
txelecidle1_ext,
txelecidle2_ext,
txelecidle3_ext,
txelecidle4_ext,
txelecidle5_ext,
txelecidle6_ext,
txelecidle7_ext
)
;
output app_int_sts_ack_icm;
output [ 12: 0] cfg_busdev_icm;
output [ 31: 0] cfg_devcsr_icm;
output [ 31: 0] cfg_linkcsr_icm;
output [ 15: 0] cfg_msicsr_icm;
output [ 31: 0] cfg_prmcsr_icm;
output clk250_out;
output dlup_exit;
output hotrst_exit;
output l2_exit;
output [ 3: 0] lane_width_code;
output msi_stream_ready0;
output [ 3: 0] phy_sel_code;
output pme_to_sr;
output [ 1: 0] powerdown_ext;
output [ 33: 0] reconfig_fromgxb;
output [ 3: 0] ref_clk_sel_code;
output [ 81: 0] rx_stream_data0;
output rx_stream_valid0;
output rxpolarity0_ext;
output rxpolarity1_ext;
output rxpolarity2_ext;
output rxpolarity3_ext;
output rxpolarity4_ext;
output rxpolarity5_ext;
output rxpolarity6_ext;
output rxpolarity7_ext;
output [ 8: 0] test_out_icm;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output tx_out4;
output tx_out5;
output tx_out6;
output tx_out7;
output [ 65: 0] tx_stream_cred0;
output tx_stream_mask0;
output tx_stream_ready0;
output txcompl0_ext;
output txcompl1_ext;
output txcompl2_ext;
output txcompl3_ext;
output txcompl4_ext;
output txcompl5_ext;
output txcompl6_ext;
output txcompl7_ext;
output [ 7: 0] txdata0_ext;
output [ 7: 0] txdata1_ext;
output [ 7: 0] txdata2_ext;
output [ 7: 0] txdata3_ext;
output [ 7: 0] txdata4_ext;
output [ 7: 0] txdata5_ext;
output [ 7: 0] txdata6_ext;
output [ 7: 0] txdata7_ext;
output txdatak0_ext;
output txdatak1_ext;
output txdatak2_ext;
output txdatak3_ext;
output txdatak4_ext;
output txdatak5_ext;
output txdatak6_ext;
output txdatak7_ext;
output txdetectrx_ext;
output txelecidle0_ext;
output txelecidle1_ext;
output txelecidle2_ext;
output txelecidle3_ext;
output txelecidle4_ext;
output txelecidle5_ext;
output txelecidle6_ext;
output txelecidle7_ext;
input app_int_sts_icm;
input cal_blk_clk;
input clk250_in;
input [ 6: 0] cpl_err_icm;
input cpl_pending_icm;
input gxb_powerdown;
input [ 7: 0] msi_stream_data0;
input msi_stream_valid0;
input npor;
input [ 4: 0] pex_msi_num_icm;
input phystatus_ext;
input pipe_mode;
input pll_powerdown;
input pme_to_cr;
input reconfig_clk;
input [ 3: 0] reconfig_togxb;
input refclk;
input rstn;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input rx_in4;
input rx_in5;
input rx_in6;
input rx_in7;
input rx_stream_mask0;
input rx_stream_ready0;
input [ 7: 0] rxdata0_ext;
input [ 7: 0] rxdata1_ext;
input [ 7: 0] rxdata2_ext;
input [ 7: 0] rxdata3_ext;
input [ 7: 0] rxdata4_ext;
input [ 7: 0] rxdata5_ext;
input [ 7: 0] rxdata6_ext;
input [ 7: 0] rxdata7_ext;
input rxdatak0_ext;
input rxdatak1_ext;
input rxdatak2_ext;
input rxdatak3_ext;
input rxdatak4_ext;
input rxdatak5_ext;
input rxdatak6_ext;
input rxdatak7_ext;
input rxelecidle0_ext;
input rxelecidle1_ext;
input rxelecidle2_ext;
input rxelecidle3_ext;
input rxelecidle4_ext;
input rxelecidle5_ext;
input rxelecidle6_ext;
input rxelecidle7_ext;
input [ 2: 0] rxstatus0_ext;
input [ 2: 0] rxstatus1_ext;
input [ 2: 0] rxstatus2_ext;
input [ 2: 0] rxstatus3_ext;
input [ 2: 0] rxstatus4_ext;
input [ 2: 0] rxstatus5_ext;
input [ 2: 0] rxstatus6_ext;
input [ 2: 0] rxstatus7_ext;
input rxvalid0_ext;
input rxvalid1_ext;
input rxvalid2_ext;
input rxvalid3_ext;
input rxvalid4_ext;
input rxvalid5_ext;
input rxvalid6_ext;
input rxvalid7_ext;
input [ 31: 0] test_in;
input [ 74: 0] tx_stream_data0;
input tx_stream_valid0;
wire app_int_ack;
wire app_int_sts;
wire app_int_sts_ack_icm;
wire app_msi_ack;
wire [ 4: 0] app_msi_num;
wire app_msi_req;
wire [ 2: 0] app_msi_tc;
wire [ 12: 0] cfg_busdev;
wire [ 12: 0] cfg_busdev_icm;
wire [ 31: 0] cfg_devcsr;
wire [ 31: 0] cfg_devcsr_icm;
wire [ 31: 0] cfg_linkcsr;
wire [ 31: 0] cfg_linkcsr_icm;
wire [ 15: 0] cfg_msicsr;
wire [ 15: 0] cfg_msicsr_icm;
wire [ 31: 0] cfg_prmcsr;
wire [ 31: 0] cfg_prmcsr_icm;
wire [ 23: 0] cfg_tcvcmap;
wire clk250_out;
wire [ 6: 0] cpl_err;
wire [ 2: 0] cpl_err_icm_int;
wire [ 2: 0] cpl_err_int;
wire cpl_pending;
wire dlup_exit;
wire hotrst_exit;
wire l2_exit;
wire [ 3: 0] lane_width_code;
wire msi_stream_ready0;
wire [ 7: 0] one_rx_be0;
wire [ 31: 0] open_cfg_pmcsr;
wire [ 23: 0] open_cfg_tcvcmap_icm;
wire [ 19: 0] open_ko_cpl_spc_vc0;
wire open_tx_err0;
wire [ 4: 0] pex_msi_num;
wire [ 3: 0] phy_sel_code;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire [ 33: 0] reconfig_fromgxb;
wire [ 3: 0] ref_clk_sel_code;
wire rx_abort0;
wire rx_ack0;
wire [ 63: 0] rx_data0;
wire [135: 0] rx_desc0;
wire rx_dfr0;
wire rx_dv0;
wire rx_mask0;
wire rx_req0;
wire rx_retry0;
wire [ 81: 0] rx_stream_data0;
wire rx_stream_valid0;
wire rx_ws0;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire rxpolarity4_ext;
wire rxpolarity5_ext;
wire rxpolarity6_ext;
wire rxpolarity7_ext;
wire [ 31: 0] test_in_int;
wire [ 8: 0] test_out_icm;
wire [ 63: 0] test_out_int;
wire [ 8: 0] test_out_wire;
wire tx_ack0;
wire [ 65: 0] tx_cred0_int;
wire [ 63: 0] tx_data0;
wire [127: 0] tx_desc0;
wire tx_dfr0;
wire tx_dv0;
wire [ 11: 0] tx_npcredd0;
wire tx_npcredd_inf0;
wire [ 7: 0] tx_npcredh0;
wire tx_npcredh_inf0;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire tx_out4;
wire tx_out5;
wire tx_out6;
wire tx_out7;
wire tx_req0;
wire [ 65: 0] tx_stream_cred0;
wire tx_stream_mask0;
wire tx_stream_ready0;
wire tx_ws0;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire txcompl4_ext;
wire txcompl5_ext;
wire txcompl6_ext;
wire txcompl7_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire [ 7: 0] txdata4_ext;
wire [ 7: 0] txdata5_ext;
wire [ 7: 0] txdata6_ext;
wire [ 7: 0] txdata7_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdatak4_ext;
wire txdatak5_ext;
wire txdatak6_ext;
wire txdatak7_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
wire txelecidle4_ext;
wire txelecidle5_ext;
wire txelecidle6_ext;
wire txelecidle7_ext;
assign ref_clk_sel_code = 0;
assign lane_width_code = 3;
assign phy_sel_code = 6;
assign test_out_wire = {test_out_int[91 : 88],test_out_int[4 : 0]};
assign test_in_int = {23'h000000,test_in[8 : 5],1'b0,test_in[3],2'b00,test_in[0]};
assign cpl_err = {cpl_err_int,4'h0};
assign cpl_err_icm_int = cpl_err_icm[2 : 0];
assign tx_npcredh0 = tx_cred0_int[27 : 20];
assign tx_npcredd0 = tx_cred0_int[39 : 28];
assign tx_npcredh_inf0 = tx_cred0_int[62];
assign tx_npcredd_inf0 = tx_cred0_int[63];
assign one_rx_be0 = 8'hff;
pcie_4243_hip_s4gx_gen2_x8_128 epmap
(
.app_int_ack (app_int_ack),
.app_int_sts (app_int_sts),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.cal_blk_clk (cal_blk_clk),
.cfg_busdev (cfg_busdev),
.cfg_devcsr (cfg_devcsr),
.cfg_linkcsr (cfg_linkcsr),
.cfg_msicsr (cfg_msicsr),
.cfg_pmcsr (open_cfg_pmcsr),
.cfg_prmcsr (cfg_prmcsr),
.cfg_tcvcmap (cfg_tcvcmap),
.clk250_in (clk250_in),
.clk250_out (clk250_out),
.cpl_err (cpl_err),
.cpl_pending (cpl_pending),
.dlup_exit (dlup_exit),
.gxb_powerdown (gxb_powerdown),
.hotrst_exit (hotrst_exit),
.ko_cpl_spc_vc0 (open_ko_cpl_spc_vc0),
.l2_exit (l2_exit),
.npor (npor),
.pex_msi_num (pex_msi_num),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pll_powerdown (pll_powerdown),
.pme_to_cr (pme_to_cr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (reconfig_togxb),
.refclk (refclk),
.rstn (rstn),
.rx_abort0 (rx_abort0),
.rx_ack0 (rx_ack0),
.rx_data0 (rx_data0),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_in4 (rx_in4),
.rx_in5 (rx_in5),
.rx_in6 (rx_in6),
.rx_in7 (rx_in7),
.rx_mask0 (rx_mask0),
.rx_req0 (rx_req0),
.rx_retry0 (rx_retry0),
.rx_ws0 (rx_ws0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdata4_ext (rxdata4_ext),
.rxdata5_ext (rxdata5_ext),
.rxdata6_ext (rxdata6_ext),
.rxdata7_ext (rxdata7_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxdatak4_ext (rxdatak4_ext),
.rxdatak5_ext (rxdatak5_ext),
.rxdatak6_ext (rxdatak6_ext),
.rxdatak7_ext (rxdatak7_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxelecidle4_ext (rxelecidle4_ext),
.rxelecidle5_ext (rxelecidle5_ext),
.rxelecidle6_ext (rxelecidle6_ext),
.rxelecidle7_ext (rxelecidle7_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxpolarity4_ext (rxpolarity4_ext),
.rxpolarity5_ext (rxpolarity5_ext),
.rxpolarity6_ext (rxpolarity6_ext),
.rxpolarity7_ext (rxpolarity7_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxstatus4_ext (rxstatus4_ext),
.rxstatus5_ext (rxstatus5_ext),
.rxstatus6_ext (rxstatus6_ext),
.rxstatus7_ext (rxstatus7_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.rxvalid4_ext (rxvalid4_ext),
.rxvalid5_ext (rxvalid5_ext),
.rxvalid6_ext (rxvalid6_ext),
.rxvalid7_ext (rxvalid7_ext),
.test_in (test_in_int),
.test_out (test_out_int),
.tx_ack0 (tx_ack0),
.tx_cred0 (tx_cred0_int),
.tx_data0 (tx_data0),
.tx_desc0 (tx_desc0),
.tx_dfr0 (tx_dfr0),
.tx_dv0 (tx_dv0),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_out4 (tx_out4),
.tx_out5 (tx_out5),
.tx_out6 (tx_out6),
.tx_out7 (tx_out7),
.tx_req0 (tx_req0),
.tx_ws0 (tx_ws0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txcompl4_ext (txcompl4_ext),
.txcompl5_ext (txcompl5_ext),
.txcompl6_ext (txcompl6_ext),
.txcompl7_ext (txcompl7_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdata4_ext (txdata4_ext),
.txdata5_ext (txdata5_ext),
.txdata6_ext (txdata6_ext),
.txdata7_ext (txdata7_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdatak4_ext (txdatak4_ext),
.txdatak5_ext (txdatak5_ext),
.txdatak6_ext (txdatak6_ext),
.txdatak7_ext (txdatak7_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext),
.txelecidle4_ext (txelecidle4_ext),
.txelecidle5_ext (txelecidle5_ext),
.txelecidle6_ext (txelecidle6_ext),
.txelecidle7_ext (txelecidle7_ext)
);
altpcierd_icm_top icm
(
.app_int_sts (app_int_sts),
.app_int_sts_ack (app_int_ack),
.app_int_sts_ack_icm (app_int_sts_ack_icm),
.app_int_sts_icm (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.cfg_busdev (cfg_busdev),
.cfg_busdev_icm (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr),
.cfg_devcsr_icm (cfg_devcsr_icm),
.cfg_linkcsr (cfg_linkcsr),
.cfg_linkcsr_icm (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_msicsr_icm (cfg_msicsr_icm),
.cfg_prmcsr (cfg_prmcsr),
.cfg_prmcsr_icm (cfg_prmcsr_icm),
.cfg_tcvcmap (cfg_tcvcmap),
.cfg_tcvcmap_icm (open_cfg_tcvcmap_icm),
.clk (clk250_in),
.cpl_err (cpl_err_int),
.cpl_err_icm (cpl_err_icm_int),
.cpl_pending (cpl_pending),
.cpl_pending_icm (cpl_pending_icm),
.msi_stream_data0 (msi_stream_data0),
.msi_stream_ready0 (msi_stream_ready0),
.msi_stream_valid0 (msi_stream_valid0),
.pex_msi_num (pex_msi_num),
.pex_msi_num_icm (pex_msi_num_icm),
.rstn (rstn),
.rx_abort0 (rx_abort0),
.rx_ack0 (rx_ack0),
.rx_be0 (one_rx_be0),
.rx_data0 (rx_data0),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_mask0 (rx_mask0),
.rx_req0 (rx_req0),
.rx_retry0 (rx_retry0),
.rx_stream_data0 (rx_stream_data0),
.rx_stream_mask0 (rx_stream_mask0),
.rx_stream_ready0 (rx_stream_ready0),
.rx_stream_valid0 (rx_stream_valid0),
.rx_ws0 (rx_ws0),
.test_out (test_out_wire),
.test_out_icm (test_out_icm),
.tx_ack0 (tx_ack0),
.tx_cred0 (tx_cred0_int),
.tx_data0 (tx_data0),
.tx_desc0 (tx_desc0),
.tx_dfr0 (tx_dfr0),
.tx_dv0 (tx_dv0),
.tx_err0 (open_tx_err0),
.tx_npcredd0 (tx_npcredd0),
.tx_npcredd_inf0 (tx_npcredd_inf0),
.tx_npcredh0 (tx_npcredh0),
.tx_npcredh_inf0 (tx_npcredh_inf0),
.tx_req0 (tx_req0),
.tx_stream_cred0 (tx_stream_cred0),
.tx_stream_data0 (tx_stream_data0),
.tx_stream_mask0 (tx_stream_mask0),
.tx_stream_ready0 (tx_stream_ready0),
.tx_stream_valid0 (tx_stream_valid0),
.tx_ws0 (tx_ws0)
);
defparam icm.TXCRED_WIDTH = 66;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 4.5.2012
// Modified: 4.5.2012
//
// Testbench for button_debounce.v.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(reset_n),
.button(button),
.debounce(debounce)
);
initial begin
clk = 1'bx; reset_n = 1'bx; button = 1'bx;
#10 reset_n = 1;
#10 reset_n = 0; clk = 0;
#10 reset_n = 1;
#10 button = 0;
end
always
#5 clk = ~clk;
always begin
#100 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
end
endmodule
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=32 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:04:27:18:06:48:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgc6m
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [31:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [31:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [31:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 32,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgc6m
//VALID FILE
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
(** %\chapter{Inductive Reasoning in SSReflect}% *)
From mathcomp.ssreflect
Require Import ssreflect eqtype ssrnat ssrbool ssrfun seq.
Module SsrStyle.
(**
In the rest of this lecture we will be constantly relying on a series
of standard SSReflect modules, such as [ssrbool], [ssrnat] and
[eqtype], which we import right away.
*)
(** * Structuring the proof scripts
An important part of the proof process is keeping to an established
proof layout, which helps to maintain the proofs readable and restore
the intuition driving the prover's hand. SSReflect offers a number of
syntactic primitives that help to maintain such a layout, and in this
section we give a short overview of them. As usual, the SSReflect
reference manual provides an exhaustive formal definition of each
primitive's semantics, so we will just cover the base cases here,
hoping that the subsequent proofs will provide more intuition on
typical usage scenarios.
** Bullets and terminators
*)
Lemma andb_true_elim b c: b && c -> c = true.
Proof.
case: c.
(**
[[
true = true
subgoal 2 (ID 15) is:
b && false -> false = true
]]
*)
- by case: b.
(** ** Using selectors and discharging subgoals
Let us restart this proof and show an alternative way to structure the
proof script, which should account for multiple cases.
*)
Restart.
case: c; first by [].
(**
[[
b : bool
============================
b && false -> false = true
]]
*)
Restart.
case:c; [by [] | by case: b].
(**
The script above solves the first generated goal using [by []], and
then solves the second one via [by case: b].
*)
(** ** Iteration and alternatives *)
Restart.
by do ![done | apply: eqxx | case: b | case: c].
Qed.
(** * Inductive predicates that should be functions *)
Inductive isZero (n: nat) : Prop := IsZero of n = 0.
(**
Naturally, such equality can be exploited to derived paradoxes, as the
following lemma shows:
*)
Lemma isZero_paradox: isZero 1 -> False.
Proof. by case. Qed.
(**
However, the equality on natural numbers is, decidable, so the very
same definition can be rewritten as a function employing the boolean
equality [(==)], which will make the proofs of paradoxes even shorter
than they already are:
*)
Definition is_zero n : bool := n == 0.
Lemma is_zero_paradox: is_zero 1 -> False.
Proof. done. Qed.
(**
That is, instead of the unavoidable case-analysis with the first
[Prop]-based definition, the functional definition made Coq compute
the result for us, deriving the falsehood automatically.
The benefits of the computable definitions become even more obvious
when considering the next example, the predicate defining whether a
natural number is even or odd. Again, we define two versions, the
inductive predicate and a boolean function.
*)
Inductive evenP n : Prop :=
Even0 of n = 0 | EvenSS m of n = m.+2 & evenP m.
Fixpoint evenb n := if n is n'.+2 then evenb n' else n == 0.
(**
Let us now prove a simple property: that fact that [(n + 1 + n)] is
even leads to a paradox. We first prove it for the version defined in
[Prop].
*)
Lemma evenP_contra n : evenP (n + 1 + n) -> False.
Proof.
elim: n=>//[| n Hn]; first by rewrite addn0 add0n; case=>//.
(**
[[
n : nat
Hn : evenP (n + 1 + n) -> False
============================
evenP (n.+1 + 1 + n.+1) -> False
]]
*)
rewrite addn1 addnS addnC !addnS.
rewrite addnC addn1 addnS in Hn.
(**
[[
n : nat
Hn : evenP (n + n).+1 -> False
============================
evenP (n + n).+3 -> False
]]
*)
case=>// m /eqP.
(**
[[
n : nat
Hn : evenP (n + n).+1 -> False
m : nat
============================
(n + n).+3 = m.+2 -> evenP m -> False
]]
*)
by rewrite !eqSS; move/eqP=><-.
Qed.
(**
Now, let us take a look at the proof of the same fact, but with the
computable version of the predicate [evenb].
*)
Lemma evenb_contra n: evenb (n + 1 + n) -> False.
Proof.
elim: n=>[|n IH] //.
(**
[[
n : nat
IH : evenb (n + 1 + n) -> False
============================
evenb (n.+1 + 1 + n.+1) -> False
]]
*)
by rewrite addSn addnS.
Qed.
(**
Sometimes, though, the value "orbits", which can be advantageous for
the proofs involving [bool]-returning predicates, might require a bit
trickier induction hypotheses than just the statement required to be
proved. Let us compare the two proofs of the same fact, formulated
with [evenP] and [evennb].
*)
Lemma evenP_plus n m : evenP n -> evenP m -> evenP (n + m).
Proof.
elim=>//n'; first by move=>->; rewrite add0n.
(**
[[
n : nat
m : nat
n' : nat
============================
forall m0 : nat,
n' = m0.+2 ->
evenP m0 -> (evenP m -> evenP (m0 + m)) -> evenP m -> evenP (n' + m)
]]
*)
move=> m'->{n'} H1 H2 H3; rewrite addnC !addnS addnC.
(**
[[
n : nat
m : nat
m' : nat
H1 : evenP m'
H2 : evenP m -> evenP (m' + m)
H3 : evenP m
============================
evenP (m' + m).+2
]]
*)
Check EvenSS.
(**
[[
EvenSS
: forall n m : nat, n = m.+2 -> evenP m -> evenP n
]]
*)
apply: (EvenSS _ (m' + m))=>//.
(**
[[
n : nat
m : nat
m' : nat
H1 : evenP m'
H2 : evenP m -> evenP (m' + m)
H3 : evenP m
============================
evenP (m' + m)
]]
*)
by apply: H2.
Qed.
(**
In this particular case, the resulting proof was quite
straightforward, thanks to the explicit equality [n = m.+2] in the
definition of the [EvenSS] constructor.
In the case of the boolean specification, though, the induction should
be done on the natural argument itself, which makes the first attempt
of the proof to be not entirely trivial.
*)
Lemma evenb_plus n m : evenb n -> evenb m -> evenb (n + m).
Proof.
elim: n=>[|n Hn]; first by rewrite add0n.
(**
[[
m : nat
n : nat
Hn : evenb n -> evenb m -> evenb (n + m)
============================
evenb n.+1 -> evenb m -> evenb (n.+1 + m)
]]
The problem now is that, if we keep building the proof by induction on
[n] or [m], the induction hypothesis and the goal will be always
"mismatched" by one, which will prevent us finishing the proof using
the hypothesis.
There are multiple ways to escape this vicious circle, and one of them
is to _generalize_ the induction hypothesis. To do so, let us restart
the proof.
*)
Restart.
move: (leqnn n).
(**
[[
n : nat
m : nat
============================
n <= n -> evenb n -> evenb m -> evenb (n + m)
]]
Now, we are going to proceed with the proof by _selective_ induction
on [n], such that some of its occurrences in the goal will be a
subject of inductive reasoning (namely, the second one), and some
others will be left generalized (that is, bound by a forall-quantified
variable). We do so by using SSReflect's tactics [elim] with explicit
_occurrence selectors_.
*)
elim: n {-2}n.
(**
[[
m : nat
============================
forall n : nat, n <= 0 -> evenb n -> evenb m -> evenb (n + m)
subgoal 2 (ID 860) is:
forall n : nat,
(forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)) ->
forall n0 : nat, n0 <= n.+1 -> evenb n0 -> evenb m -> evenb (n0 + m)
]]
The same effect could be achieved by using [elim: n {1 3 4}n], that
is, indicating which occurrences of [n] _should_ be generalized,
instead of specifying, which ones should not (as we did by means of
[{-2}n]).
*)
- by case=>//.
(**
For the second goal, we first move some of the assumptions to the context.
*)
move=>n Hn.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
============================
forall n0 : nat, n0 <= n.+1 -> evenb n0 -> evenb m -> evenb (n0 + m)
]]
We then perform the case-analysis on [n0] in the goal, which results
in two goals, one of which is automatically discharged.
*)
case=>//.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
============================
forall n0 : nat, n0 < n.+1 -> evenb n0.+1 -> evenb m -> evenb (n0.+1 + m)
]]
Doing _one more_ case analysis will adde one more [1] to the induction
variable [n0], which will bring us to the desired [(.+2)]-orbit.
*)
case=>// n0.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
n0 : nat
============================
n0.+1 < n.+1 -> evenb n0.+2 -> evenb m -> evenb (n0.+2 + m)
]]
The only thing left to do is to tweak the top assumption (by relaxing
the inequality via the [ltnW] lemma), so we could apply the induction
hypothesis [Hn].
*)
by move/ltnW /Hn=>//.
Qed.
(** ** Eliminating assumptions with a custom induction hypothesis
The functions like [evenb], with specific value orbits, are not
particularly uncommon, and it is useful to understand the key
induction principles to reason about them. In particular, the above
discussed proof could have been much more straightforward if we first
proved a different induction principle [nat2_ind] for natural numbers.
*)
Lemma nat2_ind (P: nat -> Prop):
P 0 -> P 1 -> (forall n, P n -> P (n.+2)) -> forall n, P n.
Proof.
move=> H0 H1 H n.
(**
[[
P : nat -> Prop
H0 : P 0
H1 : P 1
H : forall n : nat, P n -> P n.+2
n : nat
============================
P n
]]
Unsurprisingly, the proof of this induction principle follows the same
pattern as the proof of [evenb_plus]---generalizing the hypothesis. In
this particular case, we generalize it in the way that it would
provide an "impedance matcher" between the 1-step "default" induction
principle on natural numbers and the 2-step induction in the
hypothesis [H]. We show that for the proof it is sufficient to
establish [(P n /\ P (n.+1))]:
*)
suff: (P n /\ P (n.+1)) by case.
(**
The rest of the proof proceeds by the standard induction on [n].
*)
by elim: n=>//n; case=> H2 H3; split=>//; last by apply: H.
Qed.
(**
Now, since the new induction principle [nat2_ind] exactly matches the
2-orbit, we can directly employ it for the proof of the previous result.
*)
Lemma evenb_plus' n m : evenb n -> evenb m -> evenb (n + m).
Proof.
by elim/nat2_ind : n.
Qed.
(**
Notice that we used the version of the [elim] tactics with specific
_elimination view_ [nat2_ind], different from the default one, which
is possible using the view tactical [/]. In this sense, the "standard
induction" [elim: n] would be equivalent to [elim/nat_ind: n].
*)
(** * Inductive predicates that are hard to avoid *)
Inductive beautiful (n: nat) : Prop :=
| b_0 of n = 0
| b_3 of n = 3
| b_5 of n = 5
| b_sum n' m' of beautiful n' & beautiful m' & n = n' + m'.
(**
The number is beautiful if it's either [0], [3], [5] or a sum of two
beautiful numbers. Indeed, there are many ways to decompose some
numbers into the sum $3 * n + 5 * n$. Encoding a function,
which checks whether a number is beautiful or not, although not
impossible, is not entirely trivial (and, in particular, it's not
trivial to prove the correctness of such function with respect to the
definition above). Therefore, if one decides to stick with the
predicate definition, some operations become tedious, as, even for
constants the property should be _inferred_ rather than proved:
*)
Theorem eight_is_beautiful: beautiful 8.
Proof.
apply: (b_sum _ 3 5)=>//; first by apply: b_3.
by apply b_5.
Qed.
Theorem b_times2 n: beautiful n -> beautiful (2 * n).
Proof.
by move=>H; apply: (b_sum _ n n)=>//; rewrite mul2n addnn.
Qed.
(**
In particular, the negation proofs become much less straightforward
than one would expect:
*)
Lemma one_not_beautiful n: n = 1 -> ~ beautiful n.
Proof.
move=>E H.
(**
[[
n : nat
E : n = 1
H : beautiful n
============================
False
]]
*)
elim: H E=>n'; do?[by move=>->].
move=> n1 m' _ H2 _ H4 -> {n' n}.
(**
Notice how the assumptions [n'] and [n] are removed from the context
(since we don't need them any more) by enumerating them using [{n' n}]
notation.
*)
case: n1 H2=>// n'=> H3.
by case: n' H3=>//; case.
Qed.
(** * Working with SSReflect libraries
We conclude this chapter with a short overview of a subset of the
standard SSReflect programming and naming policies, which will,
hopefully, simplify the use of the libraries in a standalone
development.
** Notation and standard operation properties
SSReflect's module [ssrbool] introduces convenient notation for
predicate connectives, such as [/\] and [\/]. In particular, multiple
conjunctions and disjunctions are better to be written as [[ /\ P1, P2
& P3]] and [[ \/ P1, P2 | P3]], respectively, opposed to [P1 /\ P2 /\
P3] and [P1 \/ P2 \/ P3]. The specific notation makes it more
convenient to use such connectives in the proofs that proceed by case
analysis. Compare.
*)
Lemma conj4 P1 P2 P3 P4 : P1 /\ P2 /\ P3 /\ P4 -> P3.
Proof. by case=>p1 [p2][p3]. Qed.
Lemma conj4' P1 P2 P3 P4 : [ /\ P1, P2, P3 & P4] -> P3.
Proof. by case. Qed.
Locate "_ ^~ _".
(**
[[
"f ^~ y" := fun x => f x y : fun_scope
]]
For instance, this is how one can now express the partially applied
function, which applies its argument to the list [[:: 1; 2; 3]]:
*)
Check map ^~ [:: 1; 2; 3].
(**
[[
map^~ [:: 1; 2; 3]
: (nat -> ?2919) -> seq ?2919
]]
Finally, [ssrfun] defines a number of standard operator properties,
such as commutativity, distributivity etc in the form of the
correspondingly defined predicates: [commutative], [right_inverse]
etc. For example, since we have now [ssrbool] and [ssrnat] imported,
we can search for left-distributive operations defined in those two
modules (such that they come with the proofs of the corresponding
predicates):
*)
Search _ (left_distributive _).
(**
[[
andb_orl left_distributive andb orb
orb_andl left_distributive orb andb
andb_addl left_distributive andb addb
addn_maxl left_distributive addn maxn
addn_minl left_distributive addn minn
...
]]
*)
(** ** A library for lists
For instance, properties of some of the functions, such as _list
reversal_ are simpler to prove not by the standard "direct" induction
on the list structure, but rather iterating the list from its last
element, for which the [seq] library provides the necessary definition
and induction principle:
[[
Fixpoint rcons s z := if s is x :: s' then x :: rcons s' z else [:: z].
]]
*)
Check last_ind.
(**
[[
last_ind
: forall (T : Type) (P : seq T -> Type),
P [::] ->
(forall (s : seq T) (x : T), P s -> P (rcons s x)) ->
forall s : seq T, P s
]]
To demonstrate the power of the library for reasoning with lists, let
us prove the following property, known as _Dirichlet's box principle_
(sometimes also referred to as _pigeonhole principle_).
*)
Variable A : eqType.
Fixpoint has_repeats (xs : seq A) :=
if xs is x :: xs' then (x \in xs') || has_repeats xs' else false.
(**
The following lemma states that for two lists [xs1] and [xs2], is the
size [xs2] is strictly smaller than the size of [xs1], but
nevertheless [xs1] as a set is a subset of [xs2] then there ought to
be repetitions in [xs1].
*)
Theorem dirichlet xs1 xs2 :
size xs2 < size xs1 -> {subset xs1 <= xs2} -> has_repeats xs1.
Proof.
(**
First, the proof scripts initiates the induction on the structure of
the first, "longer", list [xs1], simplifying and moving to the context
some hypotheses in the "step" case (as the [nil]-case is proved
automatically).
*)
elim: xs1 xs2=>[|x xs1 IH] xs2 //= H1 H2.
(**
[[
x : A
xs1 : seq A
IH : forall xs2 : seq A,
size xs2 < size xs1 -> {subset xs1 <= xs2} -> has_repeats xs1
xs2 : seq A
H1 : size xs2 < (size xs1).+1
H2 : {subset x :: xs1 <= xs2}
============================
(x \in xs1) || has_repeats xs1
]]
*)
case H3: (x \in xs1) => //=.
(**
[[
...
H3 : (x \in xs1) = false
============================
has_repeats xs1
]]
*)
pose xs2' := filter (predC (pred1 x)) xs2.
apply: (IH xs2'); last first.
(**
[[
...
H2 : {subset x :: xs1 <= xs2}
H3 : (x \in xs1) = false
xs2' := [seq x <- xs2 | (predC (pred1 x)) x0] : seq A
============================
{subset xs1 <= xs2'}
subgoal 2 (ID 5716) is:
size xs2' < size xs1
]]
*)
- move=>y H4; move: (H2 y); rewrite inE H4 orbT mem_filter /=.
by move => -> //; case: eqP H3 H4 => // ->->.
(**
The second goal requires to prove the inequality, which states that
after removal of [x] from [xs2], the length of the resulting list
[xs2] is smaller than the length of [xs1].
*)
rewrite ltnS in H1; apply: leq_trans H1.
rewrite -(count_predC (pred1 x) xs2) -addn1 addnC.
rewrite /xs2' size_filter leq_add2r -has_count.
(**
[[
...
H2 : {subset x :: xs1 <= xs2}
H3 : (x \in xs1) = false
xs2' := [seq x <- xs2 | (predC (pred1 x)) x0] : seq A
============================
has (pred1 x) xs2
]]
*)
by apply/hasP; exists x=>//=; apply: H2; rewrite inE eq_refl.
Qed.
(*******************************************************************)
(** * Exercices * *)
(*******************************************************************)
(**
---------------------------------------------------------------------
Exercise [Integer binary division]
---------------------------------------------------------------------
Let us define the binary division function [div2] as follows.
*)
Fixpoint div2 (n: nat) := if n is p.+2 then (div2 p).+1 else 0.
(**
Prove the following lemma directly by induction on [n], _without_
using the [nat2_ind] induction principle. Then prove it using
[nat2_ind].
*)
Lemma div2_le n: div2 n <= n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Some facts about beautiful numbers]
---------------------------------------------------------------------
Proof the following theorem about beautiful numbers.
Hint: Choose wisely, what to build the induction on.
*)
Lemma b_timesm n m: beautiful n -> beautiful (m * n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Gorgeous numbers]
---------------------------------------------------------------------
To practice with proofs by induction, let us consider yet another
inductive predicate, defining which of natural numbers are _gorgeous_.
*)
Inductive gorgeous (n: nat) : Prop :=
| g_0 of n = 0
| g_plus3 m of gorgeous m & n = m + 3
| g_plus5 m of gorgeous m & n = m + 5.
(**
Prove by induction the following statements about gorgeous numbers.
Hint: As usual, do not hesitate to use the [Search] utility for
finding the necessary rewriting lemmas from the [ssrnat] module.
*)
Lemma gorgeous_plus13 n: gorgeous n -> gorgeous (n + 13).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma beautiful_gorgeous (n: nat) : beautiful n -> gorgeous n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma g_times2 (n: nat): gorgeous n -> gorgeous (n * 2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma gorgeous_beautiful (n: nat) : gorgeous n -> beautiful n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Gorgeous reflection]
---------------------------------------------------------------------
Gorgeous and beautiful numbers, defining, in fact, exactly the same
subset of [nat] are a particular case of Frobenius coin problem, which
asks for the largest integer amount of money, that cannot be obtained
using only coins of specified denominations. In the case of
[beautiful] and [gorgeous] numbers we have two denominations
available, namely 3 and 5. An explicit formula exists for the case
of only two denominations n_1 and n_2, which allows one to compute
the Frobenius number as
g(n_1, n_2) = n_1 * n_2 - n_1 - n_2.
That said, for the case n_1 = 3 and n_2 = 5 the Frobenius number is 7,
which means that all numbers greater or equal than 8 are in fact
beautiful and gorgeous (since the two are equivalent, as was
established by the previous exercise).
In this exercise, we suggest the reader to prove that the efficient
procedure of "checking" for gorgeousness is in fact correct. First,
let us defined the following candidate function.
*)
Fixpoint gorgeous_b n : bool := match n with
| 1 | 2 | 4 | 7 => false
| _ => true
end.
(**
The ultimate goal of this exercise is to prove the proposition
[reflect (gorgeous n) (gorgeous_b n)], which would mean that the two
representations are equivalent. Let us divide the proof into two
stages:
- The first stage is proving that all numbers greater or equal than
8 are gorgeous. To prove thism it might be useful to have the
following two facts established:
Hint: Use the tactic [constructor i] to prove a goal, which is an
n-ary disjunction, which is satisfied if its i-th disjunct is true.
*)
Lemma repr3 n : n >= 8 ->
exists k, [\/ n = 3 * k + 8, n = 3 * k + 9 | n = 3 * k + 10].
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma gorg3 n : gorgeous (3 * n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Next, we can establish by induction the following criteria using the
lemmas [repr3] and [gorg3] in the subgoals of the proof.
*)
Lemma gorg_criteria n : n >= 8 -> gorgeous n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
This makes the proof of the following lemma trivial.
*)
Lemma gorg_refl' n: n >= 8 -> reflect (gorgeous n) true.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
- In the second stage of the proof of reflection, we will
need to prove four totally boring but unavoidable lemmas.
Hint: The rewriting lemmas [addnC] and [eqSS] from the [ssrnat]
module might be particularly useful here.
*)
Lemma not_g1: ~(gorgeous 1).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g2: ~(gorgeous 2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g4: ~(gorgeous 4).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g7: ~(gorgeous 7).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
We can finally provide prove the ultimate reflection predicate,
relating [gorgeous] and [gorgeous_b].
*)
Lemma gorg_refl n : reflect (gorgeous n) (gorgeous_b n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Boolean element inclusion predicate for lists]
---------------------------------------------------------------------
Assuming a type [X] with the boolean equality (i.e., elements of [X]
can be compared for being equal using the [==] operator returning
[true] or [false]), define a recursive funciton [appears_in] on lists
that takes an element [a : X], a list [l : seq X] and returns a
boolean value indicating whether [a] appears in [l] or not.
*)
Section Appears_bool.
Variable X: eqType.
Fixpoint appears_in (a: X) (l: seq X) : bool :=
(* fill in your implemenation istead of the [false] stub *)
false.
(**
Next, prove the following lemma, relating [appears_in] and list
concatenation [++].
*)
Lemma appears_in_app (xs ys : seq X) (x:X):
appears_in x (xs ++ ys) = appears_in x xs || appears_in x ys.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Let us define the functions [disjoint] and [no_repeats] using
[appears_in] as follows:
*)
Fixpoint disjoint (l1 l2: seq X): bool :=
if l1 is x::xs then ~~(appears_in x l2) && disjoint xs l2 else true.
Fixpoint no_repeats (ls : seq X) :=
if ls is x :: xs then ~~ (appears_in x xs) && no_repeats xs else true.
(**
Finally, prove the following lemma, realting [no_repeats] and
[disjoint].
*)
Theorem norep_disj_app l1 l2:
no_repeats l1 -> no_repeats l2 -> disjoint l1 l2 -> no_repeats (l1 ++ l2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End Appears_bool.
Eval compute in appears_in (EqType nat _) 1 [:: 1; 2; 3].
(* true *)
Eval compute in appears_in (EqType nat _) 1 [:: 2; 4; 3].
(* false *)
(**
---------------------------------------------------------------------
Exercise [Element inclusion predicate for lists in Prop]
---------------------------------------------------------------------
For types [Y] with propositional equality, define the [appears_inP]
predicate, which returns [Prop].
*)
Section Appears_Prop.
Variable Y: Type.
Variable appears_inP : forall (a: Y) (l: seq Y), Prop.
(* Replace Variable by the actual implementation *)
(**
Prove the lemma [appears_in_appP]:
*)
Lemma appears_in_appP (xs ys : seq Y) (x:Y):
appears_inP x (xs ++ ys) <-> appears_inP x xs \/ appears_inP x ys.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Finally, define the [Prop]-versions of the [disjoint] and [no_repeat]
predicates: [disjointP] and [no_repeatP] and prove the following lemma
relating them.
*)
Variable disjointP : forall (l1 l2: seq Y), Prop.
(* Replace Variable by the actual implementation *)
Variable no_repeatsP : forall (ls : seq Y), Prop.
(* Replace Variable by the actual implementation *)
Theorem norep_disj_appP l1 l2:
no_repeatsP l1 -> no_repeatsP l2 -> disjointP l1 l2 -> no_repeatsP (l1 ++ l2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End Appears_Prop.
(**
---------------------------------------------------------------------
Exercise ["All" predicate for lists]
---------------------------------------------------------------------
Define two version of version of "all-elements-satisfy" predicate for
lists.
- The version [all] takes a type [X], a predicate [P : X -> Prop] and
a list [ls: seq X] and returns element of sort [Prop] which carries
a proof that all elements of ls satisfy [P].
- The decidable version [allb] takes a type [X], a predicate [test : X
-> bool] and a list [ls: seq X], and returns a boolean result.
Prove the lemma [allP], stating that the two representations are
equivalent whenever [P] and [test] are equivalent.
*)
Variable all : forall {X} (P : X -> Prop) (ls: seq X), Prop.
(* Replace Variable by the actual implementation *)
Variable allb : forall {X : Type} (test : X -> bool) (ls : seq X), bool.
(* Replace Variable by the actual implementation *)
Lemma allP T P test:
(forall x: T, reflect (P x) (test x)) ->
forall ls, reflect (all P ls) (allb test ls).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End SsrStyle.
|
`timescale 1ps / 1ps
module XADC_REG_test (
);
reg DCLK = 1'b0;
reg RESET;
wire [3:0] VAUXP;
wire [3:0] VAUXN; // Auxiliary analog channel inputs
wire VP;
wire VN; // Dedicated and Hardwired Analog Input Pair
wire [15:0] MEASURED_TEMP;
wire [15:0] MEASURED_VCCINT;
wire [15:0] MEASURED_VCCAUX;
wire [15:0] MEASURED_VCCBRAM;
wire [15:0] MEASURED_AUX0;
wire [15:0] MEASURED_AUX1;
wire [15:0] MEASURED_AUX2;
wire [15:0] MEASURED_AUX3;
wire [7:0] ALM;
wire [4:0] CHANNEL;
wire OT;
wire XADC_EOC;
wire XADC_EOS;
XADC_REG XADC_REG_inst (
.DCLK(DCLK), // Clock input for DRP
.RESET(RESET),
.VAUXP(VAUXP),
.VAUXN(VAUXN), // Auxiliary analog channel inputs
.VP(VP),
.VN(VN),
.MEASURED_TEMP(MEASURED_TEMP),
.MEASURED_VCCINT(MEASURED_VCCINT),
.MEASURED_VCCAUX(MEASURED_VCCAUX),
.MEASURED_VCCBRAM(MEASURED_VCCBRAM),
.MEASURED_AUX0(MEASURED_AUX0),
.MEASURED_AUX1(MEASURED_AUX1),
.MEASURED_AUX2(MEASURED_AUX2),
.MEASURED_AUX3(MEASURED_AUX3),
.ALM(ALM),
.CHANNEL(CHANNEL),
.OT(OT),
.XADC_EOC(XADC_EOC),
.XADC_EOS(XADC_EOS)
);
assign VP = 0;
assign VN = 1;
assign VAUXP = 0;
assign VAUXN = 0;
integer PERIOD = 5000 ;
always
begin #(PERIOD/2) DCLK = ~DCLK; end
initial begin
DCLK = 1'b0;
RESET = 1'b1;
#101000;
RESET = 1'b0;
#60000000;
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 50 *) wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
module t #(
parameter int WIDTH /* verilator public_flat_rd */ = 32
) (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
localparam int DEPTH /* verilator public_flat_rd */ = 16;
localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210;
localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'";
reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef IVERILOG
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_param.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
`timescale 1ns/1ns
module ddr2_interface2um(
fpga_resetn, //system reset,active low
sysclk_100m, //system clk=100MHz LVCOMS
ddr2_ck, //DDR2 System Clock Pos
ddr2_ck_n, //DDR2 System Clock Neg
//Address
ddr2_addr, //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_bank_addr, //only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_ras_n, //Row address select
ddr2_cas_n, //Column address select
ddr2_we_n, //Write enable
//command and control
ddr2_cs_n, //Chip Select
ddr2_cke, //Clock Enable
ddr2_odt, //On-die termination enable
//Data Bus
ddr2_dq, //Data
ddr2_dqs, //Strobe Pos
ddr2_dqs_n, //Strobe Neg
ddr2_dm, //Byte write mask
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty
);
input sysclk_100m; //system clk=100MHz LVCOMS
input fpga_resetn; //system reset,active low
//////ddr2 interface/////////////////
inout ddr2_ck; //DDR2 System Clock Pos
inout ddr2_ck_n; //DDR2 System Clock Neg
//Address
output [15:0] ddr2_addr; //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output [2:0] ddr2_bank_addr;
//only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output ddr2_ras_n; //Row address select
output ddr2_cas_n; //Column address select
output ddr2_we_n; //Write enable
//command and control
output ddr2_cs_n; //Chip Select
output ddr2_cke; //Clock Enable
output ddr2_odt; //On-die termination enable
//Data Bus
inout [15:0] ddr2_dq; //Data
inout [1:0] ddr2_dqs; //Strobe Pos
inout [1:0] ddr2_dqs_n; //Strobe Neg
inout [1:0] ddr2_dm; //Byte write mask
///um interface //////////////
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
wire local_ready;
wire [31:0] local_rdata;
wire local_rdata_valid;
wire local_init_done;
wire[23:0] local_address;
wire local_write_req;
wire local_read_req;
wire local_burstbegin;
wire[31:0] local_wdata;
wire[3:0] local_be;
wire[3:0] local_size;
wire phy_clk;
assign ddr2_addr[15:13] = 3'b0;
assign ddr2_bank_addr[2] = 1'b0;
ddr2 ddr2_ctrl_hp_inst
(
.pll_ref_clk(sysclk_100m) , // input pll_ref_clk_sig
.global_reset_n(fpga_resetn) , // input global_reset_n_sig
.soft_reset_n(fpga_resetn) , // input soft_reset_n_sig
.local_address(local_address) , // input [25:0] local_address_sig //by cyj
.local_write_req(local_write_req) , // input local_write_req_sig
.local_wdata_req() , // output local_wdata_req_sig
.local_wdata(local_wdata) , // input [127:0] Write data in fourth
.local_read_req(local_read_req) , // input local_read_req_sig
.local_be(local_be) , // input [15:0] local_be_sig
.local_size(local_size) , // input [1:0] local_size_sig //only 1bits
.local_ready(local_ready) , // output local_ready_sig
.local_rdata(local_rdata) , // output [127:0] local_rdata_sig output 256bits data by cyj
.local_rdata_valid(local_rdata_valid) , // output local_rdata_valid_sig
.local_init_done(local_init_done) , // output local_init_done_sig -- Not used
.local_burstbegin(local_burstbegin),
.reset_request_n() , // output reset_request_n_sig -- Not used
.mem_odt(ddr2_odt) , // output [0:0] mem_odt_sig
.mem_cs_n(ddr2_cs_n) , // output [0:0] mem_cs_n_sig
.mem_cke(ddr2_cke) , // output [0:0] mem_cke_sig
.mem_addr(ddr2_addr[12:0]) , // output [13:0] mem_addr_sig
.mem_ba(ddr2_bank_addr[1:0]) , // output [1:0] mem_ba_sig //by cyj 3 signals
.mem_ras_n(ddr2_ras_n) , // output mem_ras_n_sig
.mem_cas_n(ddr2_cas_n) , // output mem_cas_n_sig
.mem_we_n(ddr2_we_n) , // output mem_we_n_sig
.mem_dm(ddr2_dm) , // output [7:0] mem_dm_sig
.local_refresh_ack() , // output local_refresh_ack_sig -- Not used
.reset_phy_clk_n() , // output reset_phy_clk_n_sig -- Not used
.dll_reference_clk() , // output dll_reference_clk_sig -- Not used
.dqs_delay_ctrl_export() , // output [5:0] dqs_delay_ctrl_export_sig -- Not used
.local_powerdn_ack(), //by cyj
.phy_clk(phy_clk) , // output phy_clk_sig
.aux_full_rate_clk() , // output aux_full_rate_clk_sig -- Not used
.aux_half_rate_clk() , // output aux_half_rate_clk_sig -- Not used
.mem_clk(ddr2_ck) , // inout [1:0] mem_clk_sig
.mem_clk_n(ddr2_ck_n) , // inout [1:0] mem_clk_n_sig
.mem_dq(ddr2_dq) , // inout [63:0] mem_dq_sig
.mem_dqs(ddr2_dqs), // inout [7:0] mem_dqs_sig
.mem_dqsn(ddr2_dqs_n) //by cyj
);
ddr2_ctrl ddr2_ctrl(
.sys_rst_n(fpga_resetn),
.ddr2_clk(phy_clk),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_address(local_address),
.local_read_req(local_read_req),
.local_write_req(local_write_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_burstbegin(local_burstbegin),
.um2ddr_wrclk(um2ddr_wrclk),
.um2ddr_wrreq(um2ddr_wrreq),
.um2ddr_data(um2ddr_data),
.um2ddr_ready(um2ddr_ready),
.um2ddr_command_wrreq(um2ddr_command_wrreq),
.um2ddr_command(um2ddr_command),
.ddr2um_rdclk(ddr2um_rdclk),
.ddr2um_rdreq(ddr2um_rdreq),
.ddr2um_rdata(ddr2um_rdata),
.ddr2um_valid_rdreq(ddr2um_valid_rdreq),
.ddr2um_valid_rdata(ddr2um_valid_rdata),
.ddr2um_valid_empty(ddr2um_valid_empty)
);
endmodule |
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
module priority_encoder255
(
input [ 255 : 0 ] in,
output reg detect,
output reg [ 7 : 0 ] out
);
wire [3:0] detectL;
wire [5:0] preoutL [3:0];
wire [1:0] preoutM;
//1st order entries
priority_encoder64 e10( in[ 63:0 ], detectL[0], preoutL[0] );
priority_encoder64 e11( in[ 127:64 ], detectL[1], preoutL[1] );
priority_encoder64 e12( in[ 191:128 ], detectL[2], preoutL[2] );
priority_encoder64 e13( in[ 255:192 ], detectL[3], preoutL[3] );
always @ (*)
casez(detectL)
default : {detect, out} = 9'b0;
4'b0001 : {detect, out} = { 3'b100, preoutL[0] };
4'b001? : {detect, out} = { 3'b101, preoutL[1] };
4'b01?? : {detect, out} = { 3'b110, preoutL[2] };
4'b1??? : {detect, out} = { 3'b111, preoutL[3] };
endcase
endmodule
module priority_encoder64
(
input [ 63 : 0 ] in,
output detect,
output [ 5 : 0 ] out
);
wire [7:0] detectL;
wire [2:0] preoutL [7:0];
wire [2:0] preoutM;
//3rd order entries
priority_encoder8 e30( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8 e31( in[ 15:8 ], detectL[1], preoutL[1] );
priority_encoder8 e32( in[ 23:16 ], detectL[2], preoutL[2] );
priority_encoder8 e33( in[ 31:24 ], detectL[3], preoutL[3] );
priority_encoder8 e34( in[ 39:32 ], detectL[4], preoutL[4] );
priority_encoder8 e35( in[ 47:40 ], detectL[5], preoutL[5] );
priority_encoder8 e36( in[ 55:48 ], detectL[6], preoutL[6] );
priority_encoder8 e37( in[ 63:56 ], detectL[7], preoutL[7] );
//2nd order entry
priority_encoder8 e20(detectL, detect, preoutM);
assign out = detect ? { preoutM, preoutL[preoutM] } : 6'b0;
endmodule
module priority_encoder8
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
);
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b00000001 : {detect, out} = 4'b1000;
8'b0000001? : {detect, out} = 4'b1001;
8'b000001?? : {detect, out} = 4'b1010;
8'b00001??? : {detect, out} = 4'b1011;
8'b0001???? : {detect, out} = 4'b1100;
8'b001????? : {detect, out} = 4'b1101;
8'b01?????? : {detect, out} = 4'b1110;
8'b1??????? : {detect, out} = 4'b1111;
endcase
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_reg.v
//
// *Module Description:
// Registers for oMSP programming.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_reg (
// OUTPUTs
irq_gfx_o, // Graphic Controller interrupt
gpu_data_o, // GPU data
gpu_data_avail_o, // GPU data available
gpu_enable_o, // GPU enable
lt24_reset_n_o, // LT24 Reset (Active Low)
lt24_on_o, // LT24 on/off
lt24_cfg_clk_o, // LT24 Interface clock configuration
lt24_cfg_refr_o, // LT24 Interface refresh configuration
lt24_cfg_refr_sync_en_o, // LT24 Interface refresh sync enable configuration
lt24_cfg_refr_sync_val_o, // LT24 Interface refresh sync value configuration
lt24_cmd_refr_o, // LT24 Interface refresh command
lt24_cmd_val_o, // LT24 Generic command value
lt24_cmd_has_param_o, // LT24 Generic command has parameters
lt24_cmd_param_o, // LT24 Generic command parameter value
lt24_cmd_param_rdy_o, // LT24 Generic command trigger
lt24_cmd_dfill_o, // LT24 Data fill value
lt24_cmd_dfill_wr_o, // LT24 Data fill trigger
display_width_o, // Display width
display_height_o, // Display height
display_size_o, // Display size (number of pixels)
display_y_swap_o, // Display configuration: swap Y axis (horizontal symmetry)
display_x_swap_o, // Display configuration: swap X axis (vertical symmetry)
display_cl_swap_o, // Display configuration: swap column/lines
gfx_mode_o, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
per_dout_o, // Peripheral data output
refresh_frame_addr_o, // Refresh frame base address
hw_lut_palette_sel_o, // Hardware LUT palette configuration
hw_lut_bgcolor_o, // Hardware LUT background-color selection
hw_lut_fgcolor_o, // Hardware LUT foreground-color selection
sw_lut_enable_o, // Refresh LUT-RAM enable
sw_lut_bank_select_o, // Refresh LUT-RAM bank selection
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_din_o, // LUT-RAM data
lut_ram_wen_o, // LUT-RAM write strobe (active low)
lut_ram_cen_o, // LUT-RAM chip enable (active low)
`endif
vid_ram_addr_o, // Video-RAM address
vid_ram_din_o, // Video-RAM data
vid_ram_wen_o, // Video-RAM write strobe (active low)
vid_ram_cen_o, // Video-RAM chip enable (active low)
// INPUTs
dbg_freeze_i, // Freeze address auto-incr on read
gpu_cmd_done_evt_i, // GPU command done event
gpu_cmd_error_evt_i, // GPU command error event
gpu_dma_busy_i, // GPU DMA execution on going
gpu_get_data_i, // GPU get next data
lt24_status_i, // LT24 FSM Status
lt24_start_evt_i, // LT24 FSM is starting
lt24_done_evt_i, // LT24 FSM is done
mclk, // Main system clock
per_addr_i, // Peripheral address
per_din_i, // Peripheral data input
per_en_i, // Peripheral enable (high active)
per_we_i, // Peripheral write enable (high active)
puc_rst, // Main system reset
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_dout_i, // LUT-RAM data input
`endif
vid_ram_dout_i // Video-RAM data input
);
// PARAMETERs
//============
parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
// - 7 LSBs must stay cleared: 0x0080, 0x0100,
// 0x0180, 0x0200,
// 0x0280, ...
// OUTPUTs
//============
output irq_gfx_o; // Graphic Controller interrupt
output [15:0] gpu_data_o; // GPU data
output gpu_data_avail_o; // GPU data available
output gpu_enable_o; // GPU enable
output lt24_reset_n_o; // LT24 Reset (Active Low)
output lt24_on_o; // LT24 on/off
output [2:0] lt24_cfg_clk_o; // LT24 Interface clock configuration
output [11:0] lt24_cfg_refr_o; // LT24 Interface refresh configuration
output lt24_cfg_refr_sync_en_o; // LT24 Interface refresh sync configuration
output [9:0] lt24_cfg_refr_sync_val_o; // LT24 Interface refresh sync value configuration
output lt24_cmd_refr_o; // LT24 Interface refresh command
output [7:0] lt24_cmd_val_o; // LT24 Generic command value
output lt24_cmd_has_param_o; // LT24 Generic command has parameters
output [15:0] lt24_cmd_param_o; // LT24 Generic command parameter value
output lt24_cmd_param_rdy_o; // LT24 Generic command trigger
output [15:0] lt24_cmd_dfill_o; // LT24 Data fill value
output lt24_cmd_dfill_wr_o; // LT24 Data fill trigger
output [`LPIX_MSB:0] display_width_o; // Display width
output [`LPIX_MSB:0] display_height_o; // Display height
output [`SPIX_MSB:0] display_size_o; // Display size (number of pixels)
output display_y_swap_o; // Display configuration: swap Y axis (horizontal symmetry)
output display_x_swap_o; // Display configuration: swap X axis (vertical symmetry)
output display_cl_swap_o; // Display configuration: swap column/lines
output [2:0] gfx_mode_o; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
output [15:0] per_dout_o; // Peripheral data output
output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
output [2:0] hw_lut_palette_sel_o; // Hardware LUT palette configuration
output [3:0] hw_lut_bgcolor_o; // Hardware LUT background-color selection
output [3:0] hw_lut_fgcolor_o; // Hardware LUT foreground-color selection
output sw_lut_enable_o; // Refresh LUT-RAM enable
output sw_lut_bank_select_o; // Refresh LUT-RAM bank selection
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output [15:0] lut_ram_din_o; // LUT-RAM data
output lut_ram_wen_o; // LUT-RAM write strobe (active low)
output lut_ram_cen_o; // LUT-RAM chip enable (active low)
`endif
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output [15:0] vid_ram_din_o; // Video-RAM data
output vid_ram_wen_o; // Video-RAM write strobe (active low)
output vid_ram_cen_o; // Video-RAM chip enable (active low)
// INPUTs
//============
input dbg_freeze_i; // Freeze address auto-incr on read
input gpu_cmd_done_evt_i; // GPU command done event
input gpu_cmd_error_evt_i; // GPU command error event
input gpu_dma_busy_i; // GPU DMA execution on going
input gpu_get_data_i; // GPU get next data
input [4:0] lt24_status_i; // LT24 FSM Status
input lt24_start_evt_i; // LT24 FSM is starting
input lt24_done_evt_i; // LT24 FSM is done
input mclk; // Main system clock
input [13:0] per_addr_i; // Peripheral address
input [15:0] per_din_i; // Peripheral data input
input per_en_i; // Peripheral enable (high active)
input [1:0] per_we_i; // Peripheral write enable (high active)
input puc_rst; // Main system reset
`ifdef WITH_PROGRAMMABLE_LUT
input [15:0] lut_ram_dout_i; // LUT-RAM data input
`endif
input [15:0] vid_ram_dout_i; // Video-RAM data input
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 7;
// Register addresses offset
parameter [DEC_WD-1:0] GFX_CTRL = 'h00, // General control/status/irq
GFX_STATUS = 'h08,
GFX_IRQ = 'h0A,
DISPLAY_WIDTH = 'h10, // Display configuration
DISPLAY_HEIGHT = 'h12,
DISPLAY_SIZE_LO = 'h14,
DISPLAY_SIZE_HI = 'h16,
DISPLAY_CFG = 'h18,
DISPLAY_REFR_CNT = 'h1A,
LT24_CFG = 'h20, // LT24 configuration and Generic command sending
LT24_REFRESH = 'h22,
LT24_REFRESH_SYNC = 'h24,
LT24_CMD = 'h26,
LT24_CMD_PARAM = 'h28,
LT24_CMD_DFILL = 'h2A,
LT24_STATUS = 'h2C,
LUT_CFG = 'h30, // LUT Configuration & Memory Access Gate
LUT_RAM_ADDR = 'h32,
LUT_RAM_DATA = 'h34,
FRAME_SELECT = 'h3E, // Frame pointers and selection
FRAME0_PTR_LO = 'h40,
FRAME0_PTR_HI = 'h42,
FRAME1_PTR_LO = 'h44,
FRAME1_PTR_HI = 'h46,
FRAME2_PTR_LO = 'h48,
FRAME2_PTR_HI = 'h4A,
FRAME3_PTR_LO = 'h4C,
FRAME3_PTR_HI = 'h4E,
VID_RAM0_CFG = 'h50, // First Video Memory Access Gate
VID_RAM0_WIDTH = 'h52,
VID_RAM0_ADDR_LO = 'h54,
VID_RAM0_ADDR_HI = 'h56,
VID_RAM0_DATA = 'h58,
VID_RAM1_CFG = 'h60, // Second Video Memory Access Gate
VID_RAM1_WIDTH = 'h62,
VID_RAM1_ADDR_LO = 'h64,
VID_RAM1_ADDR_HI = 'h66,
VID_RAM1_DATA = 'h68,
GPU_CMD_LO = 'h70, // Graphic Processing Unit
GPU_CMD_HI = 'h72,
GPU_STAT = 'h74;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] GFX_CTRL_D = (BASE_REG << GFX_CTRL ),
GFX_STATUS_D = (BASE_REG << GFX_STATUS ),
GFX_IRQ_D = (BASE_REG << GFX_IRQ ),
DISPLAY_WIDTH_D = (BASE_REG << DISPLAY_WIDTH ),
DISPLAY_HEIGHT_D = (BASE_REG << DISPLAY_HEIGHT ),
DISPLAY_SIZE_LO_D = (BASE_REG << DISPLAY_SIZE_LO ),
DISPLAY_SIZE_HI_D = (BASE_REG << DISPLAY_SIZE_HI ),
DISPLAY_CFG_D = (BASE_REG << DISPLAY_CFG ),
DISPLAY_REFR_CNT_D = (BASE_REG << DISPLAY_REFR_CNT ),
LT24_CFG_D = (BASE_REG << LT24_CFG ),
LT24_REFRESH_D = (BASE_REG << LT24_REFRESH ),
LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),
LT24_CMD_D = (BASE_REG << LT24_CMD ),
LT24_CMD_PARAM_D = (BASE_REG << LT24_CMD_PARAM ),
LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
LUT_CFG_D = (BASE_REG << LUT_CFG ),
LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
FRAME0_PTR_HI_D = (BASE_REG << FRAME0_PTR_HI ),
FRAME1_PTR_LO_D = (BASE_REG << FRAME1_PTR_LO ),
FRAME1_PTR_HI_D = (BASE_REG << FRAME1_PTR_HI ),
FRAME2_PTR_LO_D = (BASE_REG << FRAME2_PTR_LO ),
FRAME2_PTR_HI_D = (BASE_REG << FRAME2_PTR_HI ),
FRAME3_PTR_LO_D = (BASE_REG << FRAME3_PTR_LO ),
FRAME3_PTR_HI_D = (BASE_REG << FRAME3_PTR_HI ),
VID_RAM0_CFG_D = (BASE_REG << VID_RAM0_CFG ),
VID_RAM0_WIDTH_D = (BASE_REG << VID_RAM0_WIDTH ),
VID_RAM0_ADDR_LO_D = (BASE_REG << VID_RAM0_ADDR_LO ),
VID_RAM0_ADDR_HI_D = (BASE_REG << VID_RAM0_ADDR_HI ),
VID_RAM0_DATA_D = (BASE_REG << VID_RAM0_DATA ),
VID_RAM1_CFG_D = (BASE_REG << VID_RAM1_CFG ),
VID_RAM1_WIDTH_D = (BASE_REG << VID_RAM1_WIDTH ),
VID_RAM1_ADDR_LO_D = (BASE_REG << VID_RAM1_ADDR_LO ),
VID_RAM1_ADDR_HI_D = (BASE_REG << VID_RAM1_ADDR_HI ),
VID_RAM1_DATA_D = (BASE_REG << VID_RAM1_DATA ),
GPU_CMD_LO_D = (BASE_REG << GPU_CMD_LO ),
GPU_CMD_HI_D = (BASE_REG << GPU_CMD_HI ),
GPU_STAT_D = (BASE_REG << GPU_STAT );
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en_i & (per_addr_i[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr_i[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (GFX_CTRL_D & {DEC_SZ{(reg_addr == GFX_CTRL )}}) |
(GFX_STATUS_D & {DEC_SZ{(reg_addr == GFX_STATUS )}}) |
(GFX_IRQ_D & {DEC_SZ{(reg_addr == GFX_IRQ )}}) |
(DISPLAY_WIDTH_D & {DEC_SZ{(reg_addr == DISPLAY_WIDTH )}}) |
(DISPLAY_HEIGHT_D & {DEC_SZ{(reg_addr == DISPLAY_HEIGHT )}}) |
(DISPLAY_SIZE_LO_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO )}}) |
(DISPLAY_SIZE_HI_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI )}}) |
(DISPLAY_CFG_D & {DEC_SZ{(reg_addr == DISPLAY_CFG )}}) |
(DISPLAY_REFR_CNT_D & {DEC_SZ{(reg_addr == DISPLAY_REFR_CNT )}}) |
(LT24_CFG_D & {DEC_SZ{(reg_addr == LT24_CFG )}}) |
(LT24_REFRESH_D & {DEC_SZ{(reg_addr == LT24_REFRESH )}}) |
(LT24_REFRESH_SYNC_D & {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}}) |
(LT24_CMD_D & {DEC_SZ{(reg_addr == LT24_CMD )}}) |
(LT24_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_CMD_PARAM )}}) |
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
(LUT_CFG_D & {DEC_SZ{(reg_addr == LUT_CFG )}}) |
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
(FRAME0_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME0_PTR_HI )}}) |
(FRAME1_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME1_PTR_LO )}}) |
(FRAME1_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME1_PTR_HI )}}) |
(FRAME2_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME2_PTR_LO )}}) |
(FRAME2_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME2_PTR_HI )}}) |
(FRAME3_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME3_PTR_LO )}}) |
(FRAME3_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME3_PTR_HI )}}) |
(VID_RAM0_CFG_D & {DEC_SZ{(reg_addr == VID_RAM0_CFG )}}) |
(VID_RAM0_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM0_WIDTH )}}) |
(VID_RAM0_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO )}}) |
(VID_RAM0_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI )}}) |
(VID_RAM0_DATA_D & {DEC_SZ{(reg_addr == VID_RAM0_DATA )}}) |
(VID_RAM1_CFG_D & {DEC_SZ{(reg_addr == VID_RAM1_CFG )}}) |
(VID_RAM1_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM1_WIDTH )}}) |
(VID_RAM1_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO )}}) |
(VID_RAM1_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI )}}) |
(VID_RAM1_DATA_D & {DEC_SZ{(reg_addr == VID_RAM1_DATA )}}) |
(GPU_CMD_LO_D & {DEC_SZ{(reg_addr == GPU_CMD_LO )}}) |
(GPU_CMD_HI_D & {DEC_SZ{(reg_addr == GPU_CMD_HI )}}) |
(GPU_STAT_D & {DEC_SZ{(reg_addr == GPU_STAT )}});
// Read/Write probes
wire reg_write = |per_we_i & reg_sel;
wire reg_read = ~|per_we_i & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
// Other wire declarations
wire [`APIX_MSB:0] frame0_ptr;
`ifdef WITH_FRAME1_POINTER
wire [`APIX_MSB:0] frame1_ptr;
`endif
`ifdef WITH_FRAME2_POINTER
wire [`APIX_MSB:0] frame2_ptr;
`endif
`ifdef WITH_FRAME3_POINTER
wire [`APIX_MSB:0] frame3_ptr;
`endif
wire [`APIX_MSB:0] vid_ram0_base_addr;
wire [`APIX_MSB:0] vid_ram1_base_addr;
wire refr_cnt_done_evt;
wire gpu_fifo_done_evt;
wire gpu_fifo_ovfl_evt;
//============================================================================
// 3) REGISTERS
//============================================================================
//------------------------------------------------
// GFX_CTRL Register
//------------------------------------------------
reg [15:0] gfx_ctrl;
wire gfx_ctrl_wr = reg_wr[GFX_CTRL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) gfx_ctrl <= 16'h0000;
else if (gfx_ctrl_wr) gfx_ctrl <= per_din_i;
// Bitfield assignments
wire gfx_irq_refr_done_en = gfx_ctrl[0];
wire gfx_irq_refr_start_en = gfx_ctrl[1];
wire gfx_irq_refr_cnt_done_en = gfx_ctrl[2];
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
wire gfx_irq_gpu_cmd_error_en = gfx_ctrl[7];
assign gfx_mode_o = gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel
// 011: 8 bits-per-pixel
// 010: 4 bits-per-pixel
// 001: 2 bits-per-pixel
// 000: 1 bits-per-pixel
wire gpu_enable_o = gfx_ctrl[12];
// Video modes decoding
wire gfx_mode_1_bpp = (gfx_mode_o == 3'b000);
wire gfx_mode_2_bpp = (gfx_mode_o == 3'b001);
wire gfx_mode_4_bpp = (gfx_mode_o == 3'b010);
wire gfx_mode_8_bpp = (gfx_mode_o == 3'b011);
wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
//------------------------------------------------
// GFX_STATUS Register
//------------------------------------------------
wire [15:0] gfx_status;
wire gpu_busy;
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
assign gfx_status[3:1] = 3'b000;
assign gfx_status[4] = gpu_data_avail_o;
assign gfx_status[5] = 1'b0;
assign gfx_status[6] = gpu_busy;
assign gfx_status[7] = 1'b0;
assign gfx_status[15:8] = 15'h0000;
//------------------------------------------------
// GFX_IRQ Register
//------------------------------------------------
wire [15:0] gfx_irq;
// Clear IRQ when 1 is written. Set IRQ when FSM is done
wire gfx_irq_refr_done_clr = per_din_i[0] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_done_set = lt24_done_evt_i;
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_start_set = lt24_start_evt_i;
wire gfx_irq_refr_cnt_done_clr = per_din_i[2] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_cnt_done_set = refr_cnt_done_evt;
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
wire gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;
wire gfx_irq_gpu_cmd_done_clr = per_din_i[6] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_cmd_done_set = gpu_cmd_done_evt_i;
wire gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;
reg gfx_irq_refr_done;
reg gfx_irq_refr_start;
reg gfx_irq_refr_cnt_done;
reg gfx_irq_gpu_fifo_done;
reg gfx_irq_gpu_fifo_ovfl;
reg gfx_irq_gpu_cmd_done;
reg gfx_irq_gpu_cmd_error;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
gfx_irq_refr_done <= 1'b0;
gfx_irq_refr_start <= 1'b0;
gfx_irq_refr_cnt_done <= 1'b0;
gfx_irq_gpu_fifo_done <= 1'b0;
gfx_irq_gpu_fifo_ovfl <= 1'b0;
gfx_irq_gpu_cmd_done <= 1'b0;
gfx_irq_gpu_cmd_error <= 1'b0;
end
else
begin
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
gfx_irq_refr_cnt_done <= (gfx_irq_refr_cnt_done_set | (~gfx_irq_refr_cnt_done_clr & gfx_irq_refr_cnt_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
gfx_irq_gpu_cmd_error <= (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear
end
assign gfx_irq = {8'h00,
gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,
2'h0, gfx_irq_refr_start, gfx_irq_refr_done};
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
(gfx_irq_refr_cnt_done & gfx_irq_refr_cnt_done_en) |
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
(gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en); // Graphic Controller interrupt
//------------------------------------------------
// DISPLAY_WIDTH Register
//------------------------------------------------
reg [`LPIX_MSB:0] display_width_o;
wire display_width_wr = reg_wr[DISPLAY_WIDTH];
wire [`LPIX_MSB:0] display_w_h_nxt = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] :
{{`LPIX_MSB{1'b0}}, 1'b1};
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_width_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
else if (display_width_wr) display_width_o <= display_w_h_nxt;
wire [16:0] display_width_tmp = {{16-`LPIX_MSB{1'b0}}, display_width_o};
wire [15:0] display_width_rd = display_width_tmp[15:0];
//------------------------------------------------
// DISPLAY_HEIGHT Register
//------------------------------------------------
reg [`LPIX_MSB:0] display_height_o;
wire display_height_wr = reg_wr[DISPLAY_HEIGHT];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_height_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
else if (display_height_wr) display_height_o <= display_w_h_nxt;
wire [16:0] display_height_tmp = {{16-`LPIX_MSB{1'b0}}, display_height_o};
wire [15:0] display_height_rd = display_height_tmp[15:0];
//------------------------------------------------
// DISPLAY_SIZE_HI Register
//------------------------------------------------
`ifdef WITH_DISPLAY_SIZE_HI
reg [`SPIX_HI_MSB:0] display_size_hi;
wire display_size_hi_wr = reg_wr[DISPLAY_SIZE_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_size_hi <= {`SPIX_HI_MSB+1{1'h0}};
else if (display_size_hi_wr) display_size_hi <= per_din_i[`SPIX_HI_MSB:0];
wire [16:0] display_size_hi_tmp = {{16-`SPIX_HI_MSB{1'h0}}, display_size_hi};
wire [15:0] display_size_hi_rd = display_size_hi_tmp[15:0];
`endif
//------------------------------------------------
// DISPLAY_SIZE_LO Register
//------------------------------------------------
reg [`SPIX_LO_MSB:0] display_size_lo;
wire display_size_lo_wr = reg_wr[DISPLAY_SIZE_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_size_lo <= {{`SPIX_LO_MSB{1'h0}}, 1'b1};
else if (display_size_lo_wr) display_size_lo <= per_din_i[`SPIX_LO_MSB:0];
wire [16:0] display_size_lo_tmp = {{16-`SPIX_LO_MSB{1'h0}}, display_size_lo};
wire [15:0] display_size_lo_rd = display_size_lo_tmp[15:0];
`ifdef WITH_DISPLAY_SIZE_HI
assign display_size_o = {display_size_hi, display_size_lo};
`else
assign display_size_o = display_size_lo;
`endif
//------------------------------------------------
// DISPLAY_CFG Register
//------------------------------------------------
reg display_x_swap_o;
reg display_y_swap_o;
reg display_cl_swap_o;
wire display_cfg_wr = reg_wr[DISPLAY_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
display_cl_swap_o <= 1'b0;
display_y_swap_o <= 1'b0;
display_x_swap_o <= 1'b0;
end
else if (display_cfg_wr)
begin
display_cl_swap_o <= per_din_i[0];
display_y_swap_o <= per_din_i[1];
display_x_swap_o <= per_din_i[2];
end
wire [15:0] display_cfg = {13'h0000,
display_x_swap_o,
display_y_swap_o,
display_cl_swap_o};
//------------------------------------------------
// DISPLAY_REFR_CNT Register
//------------------------------------------------
reg [15:0] display_refr_cnt;
wire display_refr_cnt_wr = reg_wr[DISPLAY_REFR_CNT];
wire display_refr_cnt_dec = gfx_irq_refr_done_set & (display_refr_cnt != 16'h0000);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_refr_cnt <= 16'h0000;
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
assign refr_cnt_done_evt = (display_refr_cnt==16'h0001) & display_refr_cnt_dec;
//------------------------------------------------
// LT24_CFG Register
//------------------------------------------------
reg [15:0] lt24_cfg;
wire lt24_cfg_wr = reg_wr[LT24_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg <= 16'h0000;
else if (lt24_cfg_wr) lt24_cfg <= per_din_i;
// Bitfield assignments
assign lt24_cfg_clk_o = lt24_cfg[6:4];
assign lt24_reset_n_o = ~lt24_cfg[1];
assign lt24_on_o = lt24_cfg[0];
//------------------------------------------------
// LT24_REFRESH Register
//------------------------------------------------
reg lt24_cmd_refr_o;
reg [11:0] lt24_cfg_refr_o;
wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==12'h000); // Auto-clear in manual refresh mode when done
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_refr_o <= 1'h0;
else if (lt24_refresh_wr) lt24_cmd_refr_o <= per_din_i[0];
else if (lt24_cmd_refr_clr) lt24_cmd_refr_o <= 1'h0;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_o <= 12'h000;
else if (lt24_refresh_wr) lt24_cfg_refr_o <= per_din_i[15:4];
wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
//------------------------------------------------
// LT24_REFRESH_SYNC Register
//------------------------------------------------
reg lt24_cfg_refr_sync_en_o;
reg [9:0] lt24_cfg_refr_sync_val_o;
wire lt24_refresh_sync_wr = reg_wr[LT24_REFRESH_SYNC];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_sync_en_o <= 1'h0;
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_en_o <= per_din_i[15];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_sync_val_o <= 10'h000;
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_val_o <= per_din_i[9:0];
wire [15:0] lt24_refresh_sync = {lt24_cfg_refr_sync_en_o, 5'h00, lt24_cfg_refr_sync_val_o};
//------------------------------------------------
// LT24_CMD Register
//------------------------------------------------
reg [15:0] lt24_cmd;
wire lt24_cmd_wr = reg_wr[LT24_CMD];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd <= 16'h0000;
else if (lt24_cmd_wr) lt24_cmd <= per_din_i;
assign lt24_cmd_val_o = lt24_cmd[7:0];
assign lt24_cmd_has_param_o = lt24_cmd[8];
//------------------------------------------------
// LT24_CMD_PARAM Register
//------------------------------------------------
reg [15:0] lt24_cmd_param_o;
wire lt24_cmd_param_wr = reg_wr[LT24_CMD_PARAM];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_param_o <= 16'h0000;
else if (lt24_cmd_param_wr) lt24_cmd_param_o <= per_din_i;
reg lt24_cmd_param_rdy_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_param_rdy_o <= 1'b0;
else lt24_cmd_param_rdy_o <= lt24_cmd_param_wr;
//------------------------------------------------
// LT24_CMD_DFILL Register
//------------------------------------------------
reg [15:0] lt24_cmd_dfill_o;
assign lt24_cmd_dfill_wr_o = reg_wr[LT24_CMD_DFILL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_dfill_o <= 16'h0000;
else if (lt24_cmd_dfill_wr_o) lt24_cmd_dfill_o <= per_din_i;
//------------------------------------------------
// LT24_STATUS Register
//------------------------------------------------
wire [15:0] lt24_status;
assign lt24_status[0] = lt24_status_i[0]; // FSM_BUSY
assign lt24_status[1] = lt24_status_i[1]; // WAIT_PARAM
assign lt24_status[2] = lt24_status_i[2]; // REFRESH_BUSY
assign lt24_status[3] = lt24_status_i[3]; // WAIT_FOR_SCANLINE
assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
assign lt24_status[15:5] = 11'h000;
//------------------------------------------------
// LUT_CFG Register
//------------------------------------------------
wire lut_cfg_wr = reg_wr[LUT_CFG];
`ifdef WITH_PROGRAMMABLE_LUT
reg sw_lut_enable_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_enable_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
reg sw_lut_ram_rmw_mode;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_ram_rmw_mode <= 1'b0;
else if (lut_cfg_wr) sw_lut_ram_rmw_mode <= per_din_i[1];
`ifdef WITH_EXTRA_LUT_BANK
reg sw_lut_bank_select_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_bank_select_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
`else
assign sw_lut_bank_select_o = 1'b0;
`endif
`else
assign sw_lut_bank_select_o = 1'b0;
assign sw_lut_enable_o = 1'b0;
wire sw_lut_ram_rmw_mode = 1'b0;
`endif
reg [2:0] hw_lut_palette_sel_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
else if (lut_cfg_wr) hw_lut_palette_sel_o <= per_din_i[6:4];
reg [3:0] hw_lut_bgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_bgcolor_o <= 4'h0;
else if (lut_cfg_wr) hw_lut_bgcolor_o <= per_din_i[11:8];
reg [3:0] hw_lut_fgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
1'b0, hw_lut_palette_sel_o,
1'b0, sw_lut_bank_select_o,
sw_lut_ram_rmw_mode, sw_lut_enable_o};
//------------------------------------------------
// LUT_RAM_ADDR Register
//------------------------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
reg [7:0] lut_ram_addr;
wire [8:0] lut_ram_addr_inc;
wire lut_ram_addr_inc_wr;
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_addr <= 8'h00;
else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc[7:0];
`ifdef WITH_EXTRA_LUT_BANK
reg lut_bank_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_bank_select <= 1'b0;
else if (lut_ram_addr_wr) lut_bank_select <= per_din_i[8];
else if (lut_ram_addr_inc_wr) lut_bank_select <= lut_ram_addr_inc[8];
`else
wire lut_bank_select = 1'b0;
`endif
assign lut_ram_addr_inc = {lut_bank_select, lut_ram_addr} + 9'h001;
wire [15:0] lut_ram_addr_rd = {7'h00, lut_bank_select, lut_ram_addr};
`ifdef WITH_EXTRA_LUT_BANK
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
`else
assign lut_ram_addr_o = lut_ram_addr;
`endif
`else
wire [15:0] lut_ram_addr_rd = 16'h0000;
`endif
//------------------------------------------------
// LUT_RAM_DATA Register
//------------------------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
// Update the LUT_RAM_DATA register with regular register write access
wire lut_ram_data_wr = reg_wr[LUT_RAM_DATA];
wire lut_ram_data_rd = reg_rd[LUT_RAM_DATA];
reg lut_ram_dout_rdy;
// LUT-RAM data Register
reg [15:0] lut_ram_data;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_data <= 16'h0000;
else if (lut_ram_data_wr) lut_ram_data <= per_din_i;
else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
// Increment the address after a write or read access to the LUT_RAM_DATA register
// - one clock cycle after a write access
// - with the read access (if not in read-modify-write mode)
assign lut_ram_addr_inc_wr = lut_ram_data_wr | (lut_ram_data_rd & ~dbg_freeze_i & ~sw_lut_ram_rmw_mode);
// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
assign lut_ram_wen_o = ~(|per_we_i & lut_ram_data_wr);
// Trigger a LUT-RAM read access immediately after:
// - a LUT-RAM_ADDR register write access
// - a LUT-RAM_DATA register read access
reg lut_ram_addr_wr_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_addr_wr_dly <= 1'b0;
else lut_ram_addr_wr_dly <= lut_ram_addr_wr;
reg lut_ram_data_rd_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_data_rd_dly <= 1'b0;
else lut_ram_data_rd_dly <= lut_ram_data_rd;
// Chip enable.
// Note: we perform a data read access:
// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
// - one cycle after a VID_RAM_ADDR register write
assign lut_ram_cen_o = ~(lut_ram_addr_wr_dly | lut_ram_data_rd_dly | // Read access
lut_ram_data_wr); // Write access
// Update the VRAM_DATA register one cycle after each memory access
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_dout_rdy <= 1'b0;
else lut_ram_dout_rdy <= ~lut_ram_cen_o;
`else
wire [15:0] lut_ram_data = 16'h0000;
`endif
//------------------------------------------------
// FRAME_SELECT Register
//------------------------------------------------
wire frame_select_wr = reg_wr[FRAME_SELECT];
`ifdef WITH_FRAME1_POINTER
`ifdef WITH_FRAME2_POINTER
reg [1:0] refresh_frame_select;
reg [1:0] vid_ram0_frame_select;
reg [1:0] vid_ram1_frame_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
refresh_frame_select <= 2'h0;
vid_ram0_frame_select <= 2'h0;
vid_ram1_frame_select <= 2'h0;
end
else if (frame_select_wr)
begin
refresh_frame_select <= per_din_i[1:0];
vid_ram0_frame_select <= per_din_i[9:8];
vid_ram1_frame_select <= per_din_i[13:12];
end
wire [15:0] frame_select = {2'h0, vid_ram1_frame_select, 2'h0, vid_ram0_frame_select, 6'h00, refresh_frame_select};
`else
reg refresh_frame_select;
reg vid_ram0_frame_select;
reg vid_ram1_frame_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
refresh_frame_select <= 1'h0;
vid_ram0_frame_select <= 1'h0;
vid_ram1_frame_select <= 1'h0;
end
else if (frame_select_wr)
begin
refresh_frame_select <= per_din_i[0];
vid_ram0_frame_select <= per_din_i[8];
vid_ram1_frame_select <= per_din_i[12];
end
wire [15:0] frame_select = {3'h0, vid_ram1_frame_select, 3'h0, vid_ram0_frame_select, 7'h00, refresh_frame_select};
`endif
`else
wire [15:0] frame_select = 16'h0000;
`endif
// Frame pointer selections
`ifdef WITH_FRAME1_POINTER
assign refresh_frame_addr_o = (refresh_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(refresh_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(refresh_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
assign vid_ram0_base_addr = (vid_ram0_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(vid_ram0_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(vid_ram0_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
assign vid_ram1_base_addr = (vid_ram1_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(vid_ram1_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(vid_ram1_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
`else
assign refresh_frame_addr_o = frame0_ptr;
assign vid_ram0_base_addr = frame0_ptr;
assign vid_ram1_base_addr = frame0_ptr;
`endif
//------------------------------------------------
// FRAME0_PTR_HI Register
//------------------------------------------------
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame0_ptr_hi;
wire frame0_ptr_hi_wr = reg_wr[FRAME0_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame0_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame0_ptr_hi_wr) frame0_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame0_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame0_ptr_hi};
wire [15:0] frame0_ptr_hi_rd = frame0_ptr_hi_tmp[15:0];
`endif
//------------------------------------------------
// FRAME0_PTR_LO Register
//------------------------------------------------
reg [`APIX_LO_MSB:0] frame0_ptr_lo;
wire frame0_ptr_lo_wr = reg_wr[FRAME0_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame0_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame0_ptr_lo_wr) frame0_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame0_ptr = {frame0_ptr_hi[`APIX_HI_MSB:0], frame0_ptr_lo};
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo;
`else
assign frame0_ptr = {frame0_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame0_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame0_ptr_lo};
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo_tmp[15:0];
`endif
//------------------------------------------------
// FRAME1_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME1_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame1_ptr_hi;
wire frame1_ptr_hi_wr = reg_wr[FRAME1_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame1_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame1_ptr_hi_wr) frame1_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame1_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame1_ptr_hi};
wire [15:0] frame1_ptr_hi_rd = frame1_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME1_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME1_POINTER
reg [`APIX_LO_MSB:0] frame1_ptr_lo;
wire frame1_ptr_lo_wr = reg_wr[FRAME1_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame1_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame1_ptr_lo_wr) frame1_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame1_ptr = {frame1_ptr_hi[`APIX_HI_MSB:0], frame1_ptr_lo};
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo;
`else
assign frame1_ptr = {frame1_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame1_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame1_ptr_lo};
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME2_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME2_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame2_ptr_hi;
wire frame2_ptr_hi_wr = reg_wr[FRAME2_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame2_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame2_ptr_hi_wr) frame2_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame2_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame2_ptr_hi};
wire [15:0] frame2_ptr_hi_rd = frame2_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME2_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME2_POINTER
reg [`APIX_LO_MSB:0] frame2_ptr_lo;
wire frame2_ptr_lo_wr = reg_wr[FRAME2_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame2_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame2_ptr_lo_wr) frame2_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame2_ptr = {frame2_ptr_hi[`APIX_HI_MSB:0], frame2_ptr_lo};
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo;
`else
assign frame2_ptr = {frame2_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame2_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame2_ptr_lo};
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME3_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME3_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame3_ptr_hi;
wire frame3_ptr_hi_wr = reg_wr[FRAME3_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame3_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame3_ptr_hi_wr) frame3_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame3_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},frame3_ptr_hi};
wire [15:0] frame3_ptr_hi_rd = frame3_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME3_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME3_POINTER
reg [`APIX_LO_MSB:0] frame3_ptr_lo;
wire frame3_ptr_lo_wr = reg_wr[FRAME3_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame3_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame3_ptr_lo_wr) frame3_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame3_ptr = {frame3_ptr_hi[`APIX_HI_MSB:0], frame3_ptr_lo};
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo;
`else
assign frame3_ptr = {frame3_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame3_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame3_ptr_lo};
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// VID_RAM0 Interface
//------------------------------------------------
wire [15:0] vid_ram0_cfg;
wire [15:0] vid_ram0_width;
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram0_addr_hi;
`endif
wire [15:0] vid_ram0_addr_lo;
wire [15:0] vid_ram0_data;
wire vid_ram0_we;
wire vid_ram0_ce;
wire [15:0] vid_ram0_din;
wire [`APIX_MSB:0] vid_ram0_addr_nxt;
wire vid_ram0_access;
ogfx_reg_vram_if ogfx_reg_vram0_if_inst (
// OUTPUTs
.vid_ram_cfg_o ( vid_ram0_cfg ), // VID_RAM0_CFG Register
.vid_ram_width_o ( vid_ram0_width ), // VID_RAM0_WIDTH Register
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_o ( vid_ram0_addr_hi ), // VID_RAM0_ADDR_HI Register
`endif
.vid_ram_addr_lo_o ( vid_ram0_addr_lo ), // VID_RAM0_ADDR_LO Register
.vid_ram_data_o ( vid_ram0_data ), // VID_RAM0_DATA Register
.vid_ram_we_o ( vid_ram0_we ), // Video-RAM Write strobe
.vid_ram_ce_o ( vid_ram0_ce ), // Video-RAM Chip enable
.vid_ram_din_o ( vid_ram0_din ), // Video-RAM Data input
.vid_ram_addr_nxt_o ( vid_ram0_addr_nxt ), // Video-RAM Next address
.vid_ram_access_o ( vid_ram0_access ), // Video-RAM Access
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM0_CFG] ), // VID_RAM0_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM0_WIDTH] ), // VID_RAM0_WIDTH Write strobe
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM0_ADDR_HI] ), // VID_RAM0_ADDR_HI Write strobe
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM0_ADDR_LO] ), // VID_RAM0_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM0_DATA] ), // VID_RAM0_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM0_DATA] ), // VID_RAM0_DATA Read strobe
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
.display_width_i ( display_width_o ), // Display width
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
.per_din_i ( per_din_i ), // Peripheral data input
.vid_ram_base_addr_i ( vid_ram0_base_addr ), // Video-RAM base address
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
);
//------------------------------------------------
// VID_RAM1 Interface
//------------------------------------------------
wire [15:0] vid_ram1_cfg;
wire [15:0] vid_ram1_width;
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram1_addr_hi;
`endif
wire [15:0] vid_ram1_addr_lo;
wire [15:0] vid_ram1_data;
wire vid_ram1_we;
wire vid_ram1_ce;
wire [15:0] vid_ram1_din;
wire [`APIX_MSB:0] vid_ram1_addr_nxt;
wire vid_ram1_access;
ogfx_reg_vram_if ogfx_reg_vram1_if_inst (
// OUTPUTs
.vid_ram_cfg_o ( vid_ram1_cfg ), // VID_RAM1_CFG Register
.vid_ram_width_o ( vid_ram1_width ), // VID_RAM1_WIDTH Register
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_o ( vid_ram1_addr_hi ), // VID_RAM1_ADDR_HI Register
`endif
.vid_ram_addr_lo_o ( vid_ram1_addr_lo ), // VID_RAM1_ADDR_LO Register
.vid_ram_data_o ( vid_ram1_data ), // VID_RAM1_DATA Register
.vid_ram_we_o ( vid_ram1_we ), // Video-RAM Write strobe
.vid_ram_ce_o ( vid_ram1_ce ), // Video-RAM Chip enable
.vid_ram_din_o ( vid_ram1_din ), // Video-RAM Data input
.vid_ram_addr_nxt_o ( vid_ram1_addr_nxt ), // Video-RAM Next address
.vid_ram_access_o ( vid_ram1_access ), // Video-RAM Access
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM1_CFG] ), // VID_RAM1_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM1_WIDTH] ), // VID_RAM1_WIDTH Write strobe
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM1_ADDR_HI] ), // VID_RAM1_ADDR_HI Write strobe
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM1_ADDR_LO] ), // VID_RAM1_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM1_DATA] ), // VID_RAM1_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM1_DATA] ), // VID_RAM1_DATA Read strobe
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
.display_width_i ( display_width_o ), // Display width
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
.per_din_i ( per_din_i ), // Peripheral data input
.vid_ram_base_addr_i ( vid_ram1_base_addr ), // Video-RAM base address
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
);
//------------------------------------------------
// GPU Interface (GPU_CMD/GPU_STAT) Registers
//------------------------------------------------
wire [3:0] gpu_stat_fifo_cnt;
wire [3:0] gpu_stat_fifo_cnt_empty;
wire gpu_stat_fifo_empty;
wire gpu_stat_fifo_full;
wire gpu_stat_fifo_full_less_2;
wire gpu_stat_fifo_full_less_3;
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
// OUTPUTs
.fifo_cnt_o ( gpu_stat_fifo_cnt ), // Fifo counter
.fifo_data_o ( gpu_data_o ), // Read data output
.fifo_done_evt_o ( gpu_fifo_done_evt ), // Fifo has been emptied
.fifo_empty_o ( gpu_stat_fifo_empty ), // Fifo is currentely empty
.fifo_empty_cnt_o ( gpu_stat_fifo_cnt_empty ), // Fifo empty words counter
.fifo_full_o ( gpu_stat_fifo_full ), // Fifo is currentely full
.fifo_ovfl_evt_o ( gpu_fifo_ovfl_evt ), // Fifo overflow event
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.fifo_data_i ( per_din_i ), // Read data input
.fifo_enable_i ( gpu_enable_o ), // Enable fifo (flushed when disabled)
.fifo_pop_i ( gpu_get_data_i ), // Pop data from the fifo
.fifo_push_i ( reg_wr[GPU_CMD_LO] |
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
);
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
assign gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] gfx_ctrl_read = gfx_ctrl & {16{reg_rd[GFX_CTRL ]}};
wire [15:0] gfx_status_read = gfx_status & {16{reg_rd[GFX_STATUS ]}};
wire [15:0] gfx_irq_read = gfx_irq & {16{reg_rd[GFX_IRQ ]}};
wire [15:0] display_width_read = display_width_rd & {16{reg_rd[DISPLAY_WIDTH ]}};
wire [15:0] display_height_read = display_height_rd & {16{reg_rd[DISPLAY_HEIGHT ]}};
wire [15:0] display_size_lo_read = display_size_lo_rd & {16{reg_rd[DISPLAY_SIZE_LO ]}};
`ifdef WITH_DISPLAY_SIZE_HI
wire [15:0] display_size_hi_read = display_size_hi_rd & {16{reg_rd[DISPLAY_SIZE_HI ]}};
`endif
wire [15:0] display_cfg_read = display_cfg & {16{reg_rd[DISPLAY_CFG ]}};
wire [15:0] display_refr_cnt_read = display_refr_cnt & {16{reg_rd[DISPLAY_REFR_CNT ]}};
wire [15:0] lt24_cfg_read = lt24_cfg & {16{reg_rd[LT24_CFG ]}};
wire [15:0] lt24_refresh_read = lt24_refresh & {16{reg_rd[LT24_REFRESH ]}};
wire [15:0] lt24_refresh_sync_read = lt24_refresh_sync & {16{reg_rd[LT24_REFRESH_SYNC ]}};
wire [15:0] lt24_cmd_read = lt24_cmd & {16{reg_rd[LT24_CMD ]}};
wire [15:0] lt24_cmd_param_read = lt24_cmd_param_o & {16{reg_rd[LT24_CMD_PARAM ]}};
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
wire [15:0] lut_cfg_read = lut_cfg_rd & {16{reg_rd[LUT_CFG ]}};
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame0_ptr_hi_read = frame0_ptr_hi_rd & {16{reg_rd[FRAME0_PTR_HI ]}};
`endif
`ifdef WITH_FRAME1_POINTER
wire [15:0] frame1_ptr_lo_read = frame1_ptr_lo_rd & {16{reg_rd[FRAME1_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame1_ptr_hi_read = frame1_ptr_hi_rd & {16{reg_rd[FRAME1_PTR_HI ]}};
`endif
`endif
`ifdef WITH_FRAME2_POINTER
wire [15:0] frame2_ptr_lo_read = frame2_ptr_lo_rd & {16{reg_rd[FRAME2_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame2_ptr_hi_read = frame2_ptr_hi_rd & {16{reg_rd[FRAME2_PTR_HI ]}};
`endif
`endif
`ifdef WITH_FRAME3_POINTER
wire [15:0] frame3_ptr_lo_read = frame3_ptr_lo_rd & {16{reg_rd[FRAME3_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame3_ptr_hi_read = frame3_ptr_hi_rd & {16{reg_rd[FRAME3_PTR_HI ]}};
`endif
`endif
wire [15:0] vid_ram0_cfg_read = vid_ram0_cfg & {16{reg_rd[VID_RAM0_CFG ]}};
wire [15:0] vid_ram0_width_read = vid_ram0_width & {16{reg_rd[VID_RAM0_WIDTH ]}};
wire [15:0] vid_ram0_addr_lo_read = vid_ram0_addr_lo & {16{reg_rd[VID_RAM0_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram0_addr_hi_read = vid_ram0_addr_hi & {16{reg_rd[VID_RAM0_ADDR_HI ]}};
`endif
wire [15:0] vid_ram0_data_read = vid_ram0_data & {16{reg_rd[VID_RAM0_DATA ]}};
wire [15:0] vid_ram1_cfg_read = vid_ram1_cfg & {16{reg_rd[VID_RAM1_CFG ]}};
wire [15:0] vid_ram1_width_read = vid_ram1_width & {16{reg_rd[VID_RAM1_WIDTH ]}};
wire [15:0] vid_ram1_addr_lo_read = vid_ram1_addr_lo & {16{reg_rd[VID_RAM1_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram1_addr_hi_read = vid_ram1_addr_hi & {16{reg_rd[VID_RAM1_ADDR_HI ]}};
`endif
wire [15:0] vid_ram1_data_read = vid_ram1_data & {16{reg_rd[VID_RAM1_DATA ]}};
wire [15:0] gpu_cmd_lo_read = 16'h0000 & {16{reg_rd[GPU_CMD_LO ]}};
wire [15:0] gpu_cmd_hi_read = 16'h0000 & {16{reg_rd[GPU_CMD_HI ]}};
wire [15:0] gpu_stat_read = gpu_stat & {16{reg_rd[GPU_STAT ]}};
wire [15:0] per_dout_o = gfx_ctrl_read |
gfx_status_read |
gfx_irq_read |
display_width_read |
display_height_read |
display_size_lo_read |
`ifdef WITH_DISPLAY_SIZE_HI
display_size_hi_read |
`endif
display_cfg_read |
display_refr_cnt_read |
lt24_cfg_read |
lt24_refresh_read |
lt24_refresh_sync_read |
lt24_cmd_read |
lt24_cmd_param_read |
lt24_cmd_dfill_read |
lt24_status_read |
lut_cfg_read |
lut_ram_addr_read |
lut_ram_data_read |
frame_select_read |
frame0_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame0_ptr_hi_read |
`endif
`ifdef WITH_FRAME1_POINTER
frame1_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame1_ptr_hi_read |
`endif
`endif
`ifdef WITH_FRAME2_POINTER
frame2_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame2_ptr_hi_read |
`endif
`endif
`ifdef WITH_FRAME3_POINTER
frame3_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame3_ptr_hi_read |
`endif
`endif
vid_ram0_cfg_read |
vid_ram0_width_read |
vid_ram0_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram0_addr_hi_read |
`endif
vid_ram0_data_read |
vid_ram1_cfg_read |
vid_ram1_width_read |
vid_ram1_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram1_addr_hi_read |
`endif
vid_ram1_data_read |
gpu_cmd_lo_read |
gpu_cmd_hi_read |
gpu_stat_read;
//============================================================================
// 5) VIDEO MEMORY INTERFACE
//============================================================================
// Write access strobe
assign vid_ram_wen_o = ~(vid_ram0_we | vid_ram1_we );
// Chip enable.
assign vid_ram_cen_o = ~(vid_ram0_ce | vid_ram1_ce );
// Data to be written
assign vid_ram_din_o = (vid_ram0_din | vid_ram1_din );
// Detect memory accesses for ADDR update
wire vid_ram_access = (vid_ram0_access | vid_ram1_access );
// Next Address
wire [`APIX_MSB:0] vid_ram_addr_nxt = (vid_ram0_addr_nxt | vid_ram1_addr_nxt);
// Align according to graphic mode
wire [`VRAM_MSB:0] vid_ram_addr_align = ({`VRAM_AWIDTH{gfx_mode_1_bpp }} & vid_ram_addr_nxt[`APIX_MSB-0:4]) |
({`VRAM_AWIDTH{gfx_mode_2_bpp }} & vid_ram_addr_nxt[`APIX_MSB-1:3]) |
({`VRAM_AWIDTH{gfx_mode_4_bpp }} & vid_ram_addr_nxt[`APIX_MSB-2:2]) |
({`VRAM_AWIDTH{gfx_mode_8_bpp }} & vid_ram_addr_nxt[`APIX_MSB-3:1]) |
({`VRAM_AWIDTH{gfx_mode_16_bpp}} & vid_ram_addr_nxt[`APIX_MSB-4:0]) ;
// Generate Video RAM address
reg [`VRAM_MSB:0] vid_ram_addr_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_addr_o <= {`VRAM_AWIDTH{1'b0}};
else if (vid_ram_access) vid_ram_addr_o <= vid_ram_addr_align;
endmodule // ogfx_reg
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:22:31 02/18/2016
// Design Name:
// Module Name: sesame
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sesame(
input clk,
input [7:0] sw,
input MISO,
input btnS,
input btnU,
input btnD,
input btnR,
input btnL,
output SS,
output MOSI,
output SCLK,
output reg [2:0] vgaRed,
output reg [2:0] vgaGreen,
output reg [2:1] vgaBlue,
output reg Hsync,
output reg Vsync
);
// Constants
wire [9:0] drawAreaWidth = 240;
wire [9:0] drawAreaHeight = 240;
wire [9:0] drawAreaStartX = 152 + 80;
wire [9:0] drawAreaStartY = 37;
wire [7:0] COLOR_BLACK = 0;
wire [7:0] COLOR_WHITE = 8'b11111111;
wire [7:0] COLOR_PURPLE = 8'b10000010;
wire [7:0] COLOR_PINK = 8'b11101110;
/******************************/
/*********VGA Driver***********/
/******************************/
reg clk_vga = 0;
reg counter_vga = 0;
reg [9:0] vgaX = 0; // VGA Driver's horizontal scanning position, 0-799
reg [9:0] vgaY = 0; // VGA Driver's vertical scanning position, 0-524
wire [9:0] vgaDrawX; // current X position in the draw screen for VGA Driver's scan position, 0-screenWidth
assign vgaDrawX = (vgaX - drawAreaStartX) / 2;
wire [9:0] vgaDrawY; // current Y position in the draw screen for VGA Driver's scan position, 0-screenHeight
assign vgaDrawY = (vgaY - drawAreaStartY) / 2;
// True if VGA scanning position is in the drawing region
wire inDrawArea;
assign inDrawArea = (vgaX >= drawAreaStartX && vgaX < (drawAreaStartX + (drawAreaWidth*2)) &&
vgaY >= drawAreaStartY && vgaY < (drawAreaStartY + (drawAreaHeight*2)));
// True if VGA scanning position is in the screen region
wire inScreenArea;
assign inScreenArea = (vgaX >= 152 && vgaX < 792 && vgaY >= 37 && vgaY < 517);
reg [9:0] cursorX = 100;
reg [9:0] cursorY = 100;
always @(posedge clk)
begin
counter_vga <= ~counter_vga;
end
always @(posedge counter_vga)
begin
clk_vga <= ~clk_vga;
end
// Update Hsync, Vsync, and vga X/Y
always @(posedge clk_vga)
begin
Hsync <= ~(vgaX >= 8 && vgaX < 104);
Vsync <= ~(vgaY >= 2 && vgaY < 4);
vgaX <= vgaX == 799 ? 0 : vgaX + 1; // vgaX goes 0-799 on clk
if (vgaX == 799)
vgaY <= vgaY == 524 ? 0 : vgaY + 1; // vgaY goes 0-524 on ~HSync and clk
end
// Update VGA RGB
always @(posedge clk_vga)
begin
// Feed RGB black when outside screen area
if (~inScreenArea)
begin
update_VGA_RGB(COLOR_BLACK);
end
// When in the draw area, use the pixel map
else if (inDrawArea)
begin
//drawing stamp cursor
if (current_tool == TOOL_STAMP && vgaDrawX >= cursorX - 15 && vgaDrawX < cursorX + 15 && vgaDrawY >= cursorY - 15 && vgaDrawY < cursorY + 15)
begin
stamp_menu_addr <= (vgaDrawX - (cursorX - 15)) + ((vgaDrawY - (cursorY - 15)) * 30);
if (stamp_menu_pixel != 8'b00000011 )
update_VGA_RGB(stamp_menu_pixel);
else
begin
pmop_addr <= vgaDrawX + vgaDrawY * drawAreaWidth;
update_VGA_RGB(pmop_pixel);
end
end
else if (vgaDrawX >= cursorX - pencil_size / 2 && vgaDrawX < cursorX + pencil_size / 2 && vgaDrawY >= cursorY - pencil_size / 2 && vgaDrawY < cursorY + pencil_size / 2)
begin
if (vgaDrawX >= cursorX - (pencil_size-1) / 2 && vgaDrawX < cursorX + (pencil_size-1) / 2 && vgaDrawY >= cursorY - (pencil_size-1) / 2 && vgaDrawY < cursorY + (pencil_size-1) / 2)
update_VGA_RGB(current_tool == TOOL_PENCIL ? sw : COLOR_PINK);
else
update_VGA_RGB(COLOR_BLACK);
end
else
begin
pmop_addr <= vgaDrawX + vgaDrawY * drawAreaWidth;
update_VGA_RGB(pmop_pixel);
end
end
// When outside the draw area, have other logic (draw menus?)
else
begin
// Possibly use vgaX and vgaY to draw menus, with another module to get menu pixels?
update_VGA_RGB(sw);
end
end
// Take in 8 bit color and set VGA colors accordingly
task update_VGA_RGB;
input [7:0] color;
begin
vgaRed = color[7:5];
vgaGreen = color[4:2];
vgaBlue = color[1:0];
end
endtask
/******************************/
/*******Cursor Control*********/
/******************************/
reg [31:0] counter_cursor = 0;
reg clk_cursor = 0; // Ticks at 30 Hz
always @(posedge clk)
begin
counter_cursor <= (counter_cursor == 1666666) ? 0 : counter_cursor + 1;
if (counter_cursor == 0)
clk_cursor <= ~clk_cursor;
end
always @(posedge clk_cursor)
begin
if (joystick_x < 150 && cursorX < drawAreaWidth - 2) cursorX <= cursorX + 2;
else if (joystick_x < 400 && cursorX < drawAreaWidth - 1) cursorX <= cursorX + 1;
if (joystick_x > 850 && cursorX > 2) cursorX <= cursorX - 2;
else if (joystick_x > 600 && cursorX > 1) cursorX <= cursorX - 1;
if (joystick_y < 150 && cursorY > 2) cursorY <= cursorY - 2;
else if (joystick_y < 400 && cursorY > 1) cursorY <= cursorY - 1;
if (joystick_y > 850 && cursorY < drawAreaHeight - 2) cursorY <= cursorY + 2;
else if (joystick_y > 600 && cursorY < drawAreaHeight - 1) cursorY <= cursorY + 1;
end
/******************************/
/********Tool Control**********/
/******************************/
reg [5:0] current_tool = 2;
reg [5:0] old_tool = 0; // Used to go back to current_tool after resetting screen
wire [5:0] TOOL_NONE = 0;
wire [5:0] TOOL_RESET = 1;
wire [5:0] TOOL_PENCIL = 2;
wire [5:0] TOOL_ERASER = 3;
wire [5:0] TOOL_STAMP = 4;
reg is_resetting = 0;
reg is_tool_on = 0;
reg [31:0] reset_counter = 0;
reg [31:0] pencil_size = 4;
reg [31:0] pencil_x = 0;
reg [31:0] pencil_y = 0;
reg [31:0] stamp_size = 30;
reg [31:0] stamp_x = 0;
reg [31:0] stamp_y = 0;
reg [31:0] current_stamp = 4;
reg [31:0] counter_debounce = 0;
wire clk_debounce;
assign clk_debounce = counter_debounce == 166666;
always @(posedge clk)
begin
counter_debounce <= counter_debounce == 166666 ? 0 : counter_debounce + 1;
end
reg btnRdb = 0;
reg btnLdb = 0;
reg btnUdb = 0;
reg btnDdb = 0;
always @(posedge clk_debounce)
begin
btnRdb <= btnR;
btnLdb <= btnL;
btnUdb <= btnU;
btnDdb <= btnD;
end
wire comboLR = btnRdb || btnLdb;
always @(posedge comboLR)
begin
if (btnRdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 6 ? 0 :current_stamp + 1;
end
else
begin
case (pencil_size)
2: pencil_size <= 4;
4: pencil_size <= 6;
endcase
end
end
if (btnLdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 0 ? 6 :current_stamp - 1;
end
else
begin
case (pencil_size)
4: pencil_size <= 2;
6: pencil_size <= 4;
endcase
end
end
end
wire comboUD = btnUdb || btnDdb;
always @(posedge comboUD)
begin
if (btnUdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_PENCIL;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_ERASER;
end
if (btnDdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_ERASER;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_PENCIL;
end
end
always @(posedge clk)
begin
// Set current tool
if (btnS && current_tool != TOOL_RESET)
begin
is_resetting <= 1;
reset_counter <= 0;
end
else if (joystick_btn_left)
is_tool_on <= 1;
if (is_resetting)
begin
if (reset_counter == drawAreaWidth * drawAreaHeight)
begin
is_resetting <= 0;
wea <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= reset_counter;
reset_counter <= reset_counter + 1;
end
end
if (is_tool_on && current_tool == TOOL_PENCIL)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= sw;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_ERASER)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_STAMP)
begin
if (stamp_y == stamp_size)
begin
is_tool_on <= 0;
wea <= 0;
stamp_x <= 0;
stamp_y <= 0;
stamp_draw_addr <= 0;
end
else
begin
stamp_draw_addr <= (stamp_x + (stamp_y * stamp_size));
wea <= stamp_draw_pixel != 8'b00000011;
dina <= stamp_draw_pixel;
pmin_addr <= (cursorX + stamp_x - stamp_size / 2) + (cursorY + stamp_y - stamp_size / 2) * drawAreaWidth;
if (stamp_x == stamp_size)
begin
stamp_x <= 0;
stamp_y <= stamp_y + 1;
end
else
stamp_x <= stamp_x + 1;
end
end
end
/******************************/
/*********Pixel Map ***********/
/******************************/
reg [15:0] pmop_addr;
wire [7:0] pmop_pixel;
reg wea;
reg [15 : 0] pmin_addr;
reg [7 : 0] dina;
pixel_map pixel_map(
.clka(clk), // input clka
.wea(wea), // input [0 : 0] wea
.addra(pmin_addr), // input [15 : 0] addra
.dina(dina), // input [7 : 0] dina
.clkb(clk), // input clkb
.addrb(pmop_addr), // input [15 : 0] addrb
.doutb(pmop_pixel) // output [7 : 0] doutb
);
reg [9:0] stamp_draw_addr = 0;
wire [7:0] stamp_draw_pixel;
reg [9:0] stamp_menu_addr = 0;
wire [7:0] stamp_menu_pixel;
assign stamp_draw_pixel =
current_stamp == 0 ? stamp_draw_pixel_0 :
current_stamp == 1 ? stamp_draw_pixel_1 :
current_stamp == 2 ? stamp_draw_pixel_2 :
current_stamp == 3 ? stamp_draw_pixel_3 :
current_stamp == 4 ? stamp_draw_pixel_4 :
current_stamp == 5 ? stamp_draw_pixel_5 : stamp_draw_pixel_6;
assign stamp_menu_pixel =
current_stamp == 0 ? stamp_menu_pixel_0 :
current_stamp == 1 ? stamp_menu_pixel_1 :
current_stamp == 2 ? stamp_menu_pixel_2 :
current_stamp == 3 ? stamp_menu_pixel_3 :
current_stamp == 4 ? stamp_menu_pixel_4 :
current_stamp == 5 ? stamp_menu_pixel_5 : stamp_menu_pixel_6;
wire [7:0] stamp_draw_pixel_0;
wire [7:0] stamp_menu_pixel_0;
stamp_matt stamp0 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_0), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_0) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_1;
wire [7:0] stamp_menu_pixel_1;
stamp_penguin stamp1 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_1), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_1) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_2;
wire [7:0] stamp_menu_pixel_2;
stamp_jellyfish stamp2 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_2), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_2) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_3;
wire [7:0] stamp_menu_pixel_3;
stamp_cat stamp3 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_3), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_3) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_4;
wire [7:0] stamp_menu_pixel_4;
stamp_taco stamp4 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_4), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_4) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_5;
wire [7:0] stamp_menu_pixel_5;
stamp_mushroom stamp5 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_5), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_5) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_6;
wire [7:0] stamp_menu_pixel_6;
stamp_heart stamp6 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_6), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_6) // output [7 : 0] doutb
);
/******************************/
/*********Joystick ***********/
/******************************/
wire SS; // Active low
wire MOSI; // Data transfer from master to slave
wire SCLK; // Serial clock that controls communication
assign MOSI = 0;
// Data read from PmodJSTK
wire [39:0] jstkData;
wire [9 : 0] joystick_y = {jstkData[9:8], jstkData[23:16]};
wire [9 : 0] joystick_x = {jstkData[25:24], jstkData[39:32]};
wire joystick_btn_right = jstkData[1];
wire joystick_btn_left = jstkData[2];
joy joy(
.CLK(clk),
.sndRec(clk_cursor),
.MISO(MISO),
.SS(SS),
.SCLK(SCLK),
.DOUT(jstkData)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] in;
wire a,y,y_fixed;
wire b = in[0];
wire en = in[1];
pullup(a);
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
initial en=0;
// Test loop
always @ (posedge clk) begin
in <= in + 1;
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
if (en) begin
// driving b
// a should be b
// y and yfix should also be b
if (a!=b || y != b || y_fixed != b) begin
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
$stop;
end
end else begin
// not driving b
// a should be 1 (pullup)
// y and yfix shold be 1
if (a!=1 || y != 1 || y_fixed != 1) begin
$display( "Expected a,y,yfix == 1");
$stop;
end
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ChildA(inout A, input B, input en, output Y, output Yfix);
// workaround
wire a_in = A;
ChildB childB(.A(A), .Y(Y));
assign A = en ? B : 1'bz;
ChildB childBfix(.A(a_in),.Y(Yfix));
endmodule
module ChildB(input A, output Y);
assign Y = A;
endmodule
|
// Test system function calls in constant functions
module constfunc6();
function [7:0] clog2(input [7:0] a);
clog2 = $clog2(a);
endfunction
function real log10(input [7:0] a);
log10 = $log10(a);
endfunction
function real sqrt(input real a);
sqrt = $sqrt(a);
endfunction
function real pow_i(input [7:0] a, input [7:0] b);
pow_i = $pow(a, b);
endfunction
function real pow_r(input real a, input real b);
pow_r = $pow(a, b);
endfunction
function signed [7:0] abs_i(input signed [7:0] a);
abs_i = $abs(a);
endfunction
function real abs_r(input real a);
abs_r = $abs(a);
endfunction
function [7:0] min_i(input [7:0] a, input [7:0] b);
min_i = $min(a, b);
endfunction
function [7:0] max_i(input [7:0] a, input [7:0] b);
max_i = $max(a, b);
endfunction
function real min_r(input real a, input real b);
min_r = $min(a, b);
endfunction
function real max_r(input real a, input real b);
max_r = $max(a, b);
endfunction
localparam [7:0] clog2Result = clog2(25);
localparam real log10Result = log10(100);
localparam real sqrtResult = sqrt(25.0);
localparam [7:0] powIResult = pow_i(4, 3);
localparam [7:0] absIResult = abs_i(-25);
localparam [7:0] minIResult = min_i(25, 30);
localparam [7:0] maxIResult = max_i(25, 30);
localparam real powRResult = pow_r(4.0, 3.0);
localparam real absRResult = abs_r(-25.0);
localparam real minRResult = min_r(25.0, 30.0);
localparam real maxRResult = max_r(25.0, 30.0);
reg failed;
initial begin
failed = 0;
$display("%0d", clog2Result);
$display("%0g", log10Result);
$display("%0g", sqrtResult);
$display("%0d", powIResult);
$display("%0g", powRResult);
$display("%0d", absIResult);
$display("%0g", absRResult);
$display("%0d", minIResult);
$display("%0g", minRResult);
$display("%0d", maxIResult);
$display("%0g", maxRResult);
if (clog2Result !== 8'd5) failed = 1;
if (log10Result != 2.0) failed = 1;
if ( sqrtResult != 5.0) failed = 1;
if ( powIResult !== 8'd64) failed = 1;
if ( powRResult != 64.0) failed = 1;
if ( absIResult !== 8'd25) failed = 1;
if ( absRResult != 25.0) failed = 1;
if ( minIResult !== 8'd25) failed = 1;
if ( minRResult != 25.0) failed = 1;
if ( maxIResult !== 8'd30) failed = 1;
if ( maxRResult != 30.0) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:21:21 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_31_, cordic_FSM_state_next_1_,
add_subt_module_sign_final_result, add_subt_module_intAS,
add_subt_module_FSM_selector_D, add_subt_module_add_overflow_flag,
add_subt_module_FSM_selector_C, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1016, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1182, n1183, n1184, n1186,
n1187, n1188, n1190, n1191, n1192, n1194, n1195, n1196, n1198, n1199,
n1200, n1202, n1203, n1204, n1206, n1207, n1208, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [30:27] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [31:0] result_add_subt;
wire [30:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [25:0] add_subt_module_Sgf_normalized_result;
wire [25:0] add_subt_module_Add_Subt_result;
wire [4:0] add_subt_module_LZA_output;
wire [7:0] add_subt_module_exp_oper_result;
wire [30:0] add_subt_module_DmP;
wire [30:0] add_subt_module_DMP;
wire [31:0] add_subt_module_intDY;
wire [31:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [51:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS cont_iter_count_reg_2_ ( .D(n1502), .CK(clk), .RN(n3120), .Q(n1563),
.QN(n3070) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(n1499), .CK(clk), .RN(n3121), .Q(
d_ff1_shift_region_flag_out[1]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1498), .CK(clk), .RN(n3121), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1497), .CK(clk), .RN(n3121), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1496), .CK(clk), .RN(n3121), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1495), .CK(clk), .RN(n3121), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1494), .CK(clk), .RN(n3121), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1493), .CK(clk), .RN(n3122), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1492), .CK(clk), .RN(n3122), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1491), .CK(clk), .RN(n3122), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1490), .CK(clk), .RN(n3122), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1489), .CK(clk), .RN(n3122), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1488), .CK(clk), .RN(n3122), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1487), .CK(clk), .RN(n3122), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n3122), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1485), .CK(clk), .RN(n3122), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1484), .CK(clk), .RN(n3122), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1483), .CK(clk), .RN(n3123), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1482), .CK(clk), .RN(n3123), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1481), .CK(clk), .RN(n3123), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1480), .CK(clk), .RN(n3123), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1479), .CK(clk), .RN(n3123), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1478), .CK(clk), .RN(n3123), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1477), .CK(clk), .RN(n3123), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1476), .CK(clk), .RN(n3123), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1475), .CK(clk), .RN(n3123), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1474), .CK(clk), .RN(n3123), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1473), .CK(clk), .RN(n3124), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1472), .CK(clk), .RN(n3124), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1471), .CK(clk), .RN(n3124), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1470), .CK(clk), .RN(n3124), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1469), .CK(clk), .RN(n3124), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1468), .CK(clk), .RN(n3124), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1467), .CK(clk), .RN(n3124), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n3124), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n3124), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n1461), .CK(clk), .RN(n3124), .Q(
d_ff3_LUT_out[25]), .QN(n3064) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n1460), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n1458), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[21]), .QN(n3067) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n1456), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n1455), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n1454), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n1453), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n1452), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n1451), .CK(clk), .RN(n3125), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n1450), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n1449), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n1448), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n1447), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n1446), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1444), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n1443), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n1442), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[6]), .QN(n3063) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n1441), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n1440), .CK(clk), .RN(n3127), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(n3127), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n1438), .CK(clk), .RN(n3127), .Q(
d_ff3_LUT_out[2]), .QN(n3065) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n1437), .CK(clk), .RN(n3127), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n1436), .CK(clk), .RN(n3127), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1084), .CK(clk), .RN(n3127), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1085), .CK(clk), .RN(n3127), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1086), .CK(clk), .RN(n3127), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1087), .CK(clk), .RN(n3127), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1088), .CK(clk), .RN(n3127), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1090), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1419), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1420), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1421), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[28]), .QN(n3066) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1422), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1423), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1424), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1425), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n1426), .CK(clk), .RN(n3129), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n1373), .CK(clk), .RN(n3129), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(n1331), .CK(clk), .RN(n3074), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1435), .CK(clk), .RN(n3120), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1082), .CK(clk), .RN(n3120), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1370), .CK(clk), .RN(n3130), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(n1147), .CK(clk), .RN(n1758), .Q(
d_ff3_sign_out) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1300), .CK(clk), .RN(n1751), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1299), .CK(clk), .RN(n3138), .Q(
d_ff_Yn[30]), .QN(n3062) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1020), .CK(clk), .RN(n3139), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1296), .CK(clk), .RN(n3139), .Q(
d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1150), .CK(clk), .RN(n3138),
.Q(d_ff2_Z[29]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1022), .CK(clk), .RN(n3138), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1292), .CK(clk), .RN(n1752), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1151), .CK(clk), .RN(n3139),
.Q(d_ff2_Z[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1094), .CK(clk), .RN(n3139),
.Q(d_ff2_Y[28]), .QN(n3052) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1024), .CK(clk), .RN(n3137), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1288), .CK(clk), .RN(n3137), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1287), .CK(clk), .RN(n3137), .Q(
d_ff_Yn[27]), .QN(n3061) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1026), .CK(clk), .RN(n3137), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1284), .CK(clk), .RN(n3136), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1153), .CK(clk), .RN(n3136),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1028), .CK(clk), .RN(n3136), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n3136), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1154), .CK(clk), .RN(n3136),
.Q(d_ff2_Z[25]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1030), .CK(clk), .RN(n3135), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1276), .CK(clk), .RN(n3135), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1155), .CK(clk), .RN(n3135),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1032), .CK(clk), .RN(n3134), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1272), .CK(clk), .RN(n3134), .Q(
d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1156), .CK(clk), .RN(n3134),
.Q(d_ff2_Z[23]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1034), .CK(clk), .RN(n3133), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1180), .CK(clk), .RN(n3133), .Q(d_ff_Zn[0])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1179), .CK(clk), .RN(n3133), .Q(
d_ff2_Z[0]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n3075), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1268), .CK(clk), .RN(n3133), .Q(
d_ff_Zn[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1100), .CK(clk), .RN(n3132), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1417), .CK(clk), .RN(n3132), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1204), .CK(clk), .RN(n3132), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1132), .CK(clk), .RN(n3132), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n3131), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1192), .CK(clk), .RN(n3131), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1176), .CK(clk), .RN(n3131), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1138), .CK(clk), .RN(n3131), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1379), .CK(clk), .RN(n3130), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1256), .CK(clk), .RN(n3130), .Q(
d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1160), .CK(clk), .RN(n3130),
.Q(d_ff2_Z[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1106), .CK(clk), .RN(n3110), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1411), .CK(clk), .RN(n3101), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1042), .CK(clk), .RN(n3101), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n3101), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1177), .CK(clk), .RN(n3101), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1140), .CK(clk), .RN(n3102), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1377), .CK(clk), .RN(n3102), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1264), .CK(clk), .RN(n3102), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1102), .CK(clk), .RN(n3102), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1415), .CK(clk), .RN(n3103), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1252), .CK(clk), .RN(n3103), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1161), .CK(clk), .RN(n3103),
.Q(d_ff2_Z[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1108), .CK(clk), .RN(n3103), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1409), .CK(clk), .RN(n3103), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1044), .CK(clk), .RN(n3104), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1240), .CK(clk), .RN(n3104), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1164), .CK(clk), .RN(n3104),
.Q(d_ff2_Z[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1114), .CK(clk), .RN(n3104), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(n3104), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1212), .CK(clk), .RN(n3105), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1128), .CK(clk), .RN(n3105), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1389), .CK(clk), .RN(n3105), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1184), .CK(clk), .RN(n3105), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1178), .CK(clk), .RN(n3105), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1142), .CK(clk), .RN(n3106), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1375), .CK(clk), .RN(n3106), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1260), .CK(clk), .RN(n3106), .Q(
d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1159), .CK(clk), .RN(n3106),
.Q(d_ff2_Z[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1104), .CK(clk), .RN(n3107), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1413), .CK(clk), .RN(n3107), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1040), .CK(clk), .RN(n3107), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1232), .CK(clk), .RN(n3107), .Q(
d_ff_Zn[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1118), .CK(clk), .RN(n3108), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n1399), .CK(clk), .RN(n3108), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1054), .CK(clk), .RN(n3108), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(n3108), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(n3108), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1134), .CK(clk), .RN(n3109), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1383), .CK(clk), .RN(n3109), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n3109), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1162), .CK(clk), .RN(n3109),
.Q(d_ff2_Z[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1110), .CK(clk), .RN(n3109), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1407), .CK(clk), .RN(n3110), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1046), .CK(clk), .RN(n3110), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1196), .CK(clk), .RN(n3110), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1175), .CK(clk), .RN(n3110), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1136), .CK(clk), .RN(n3110), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1381), .CK(clk), .RN(n3111), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1244), .CK(clk), .RN(n3111), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1112), .CK(clk), .RN(n3111), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1405), .CK(clk), .RN(n3112), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1048), .CK(clk), .RN(n3112), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1220), .CK(clk), .RN(n3112), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1124), .CK(clk), .RN(n3112), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1393), .CK(clk), .RN(n3113), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1236), .CK(clk), .RN(n3113), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1116), .CK(clk), .RN(n3113), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1401), .CK(clk), .RN(n3113), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1052), .CK(clk), .RN(n3113), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1208), .CK(clk), .RN(n3114), .Q(d_ff_Zn[7])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1172), .CK(clk), .RN(n3114), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n3114), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1387), .CK(clk), .RN(n3114), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1224), .CK(clk), .RN(n3114), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1122), .CK(clk), .RN(n3115), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1395), .CK(clk), .RN(n3115), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1228), .CK(clk), .RN(n3115), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1120), .CK(clk), .RN(n3116), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1397), .CK(clk), .RN(n3116), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1056), .CK(clk), .RN(n3116), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1216), .CK(clk), .RN(n3116), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1170), .CK(clk), .RN(n3116), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1126), .CK(clk), .RN(n3117), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1391), .CK(clk), .RN(n3117), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1062), .CK(clk), .RN(n3117), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1058), .CK(clk), .RN(n3117), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1066), .CK(clk), .RN(n3117), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1060), .CK(clk), .RN(n3118), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1072), .CK(clk), .RN(n3118), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1070), .CK(clk), .RN(n3118), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1078), .CK(clk), .RN(n3118), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1064), .CK(clk), .RN(n3118), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1050), .CK(clk), .RN(n3119), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1038), .CK(clk), .RN(n3119), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1076), .CK(clk), .RN(n3119), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1074), .CK(clk), .RN(n3119), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1068), .CK(clk), .RN(n3119), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1036), .CK(clk), .RN(n3120), .Q(
sign_inv_out[22]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n3079), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1144), .CK(clk), .RN(n3120), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1080), .CK(clk), .RN(n3120), .Q(
sign_inv_out[0]) );
DFFRX4TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n1368), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_D), .QN(n3001) );
DFFRX2TS add_subt_module_XRegister_Q_reg_31_ ( .D(n1003), .CK(clk), .RN(
n3099), .Q(add_subt_module_intDX[31]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n999),
.CK(clk), .RN(n3091), .Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n996),
.CK(clk), .RN(n3091), .Q(add_subt_module_DmP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n993),
.CK(clk), .RN(n3091), .Q(add_subt_module_DmP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n990),
.CK(clk), .RN(n3091), .Q(add_subt_module_DmP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n987),
.CK(clk), .RN(n3086), .Q(add_subt_module_DmP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n984),
.CK(clk), .RN(n3087), .Q(add_subt_module_DmP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n981),
.CK(clk), .RN(n1754), .Q(add_subt_module_DmP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n978),
.CK(clk), .RN(n3088), .Q(add_subt_module_DmP[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n969),
.CK(clk), .RN(n3081), .Q(add_subt_module_DmP[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n966),
.CK(clk), .RN(n3081), .Q(add_subt_module_DmP[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n963),
.CK(clk), .RN(n3082), .Q(add_subt_module_DmP[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n959),
.CK(clk), .RN(n3082), .Q(add_subt_module_DmP[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n953),
.CK(clk), .RN(n3082), .Q(add_subt_module_DmP[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n949),
.CK(clk), .RN(n3083), .Q(add_subt_module_DmP[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n946),
.CK(clk), .RN(n3083), .Q(add_subt_module_DmP[8]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n925),
.CK(clk), .RN(n3084), .Q(add_subt_module_DmP[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n922),
.CK(clk), .RN(n3089), .Q(add_subt_module_DmP[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n918),
.CK(clk), .RN(n3090), .Q(add_subt_module_DmP[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n915),
.CK(clk), .RN(n3084), .Q(add_subt_module_DmP[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n911),
.CK(clk), .RN(n3088), .Q(add_subt_module_DmP[7]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n908),
.CK(clk), .RN(n1754), .Q(add_subt_module_DmP[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n905),
.CK(clk), .RN(n3085), .Q(add_subt_module_DmP[12]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_16_ ( .D(n924), .CK(clk), .RN(n3088), .Q(add_subt_module_intDX[16]), .QN(n3035) );
DFFRX2TS reg_ch_mux_2_Q_reg_1_ ( .D(n1464), .CK(clk), .RN(n3129), .Q(
sel_mux_2_reg[1]), .QN(n3025) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n1507), .CK(clk), .RN(n3121), .Q(
cont_var_out[0]), .QN(n3023) );
DFFRX2TS add_subt_module_XRegister_Q_reg_6_ ( .D(n971), .CK(clk), .RN(n3099),
.Q(add_subt_module_intDX[6]), .QN(n3021) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
n1336), .CK(clk), .RN(n3100), .Q(add_subt_module_Add_Subt_result[3]),
.QN(n3017) );
DFFRX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1008), .CK(clk), .RN(
n3079), .Q(add_subt_module_intDY[26]), .QN(n3016) );
DFFRX2TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1005), .CK(clk), .RN(
n3080), .Q(add_subt_module_intDY[23]), .QN(n3015) );
DFFRX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n979), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[23]), .QN(n3013) );
DFFRX2TS add_subt_module_XRegister_Q_reg_4_ ( .D(n927), .CK(clk), .RN(n3099),
.Q(add_subt_module_intDX[4]), .QN(n3011) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n906), .CK(clk), .RN(n3089), .Q(add_subt_module_intDY[12]), .QN(n3006) );
DFFRX2TS add_subt_module_XRegister_Q_reg_10_ ( .D(n920), .CK(clk), .RN(n3086), .Q(add_subt_module_intDX[10]), .QN(n3005) );
DFFRX2TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1007), .CK(clk), .RN(
n3079), .Q(add_subt_module_intDY[25]), .QN(n3004) );
DFFRX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n947), .CK(clk), .RN(n3083),
.Q(add_subt_module_intDY[8]), .QN(n3000) );
DFFRX2TS add_subt_module_YRegister_Q_reg_18_ ( .D(n954), .CK(clk), .RN(n3082), .Q(add_subt_module_intDY[18]), .QN(n2999) );
DFFRX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n930), .CK(clk), .RN(n1754), .Q(add_subt_module_intDY[17]), .QN(n2998) );
DFFRX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n957), .CK(clk), .RN(n3082), .Q(add_subt_module_intDY[21]), .QN(n2997) );
DFFRX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n937), .CK(clk), .RN(n3100), .Q(add_subt_module_intDY[13]), .QN(n2996) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n994), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[28]), .QN(n2993) );
DFFRX2TS add_subt_module_YRegister_Q_reg_20_ ( .D(n941), .CK(clk), .RN(n3083), .Q(add_subt_module_intDY[20]), .QN(n2991) );
DFFRX2TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1010), .CK(clk), .RN(
n3079), .Q(add_subt_module_intDY[28]), .QN(n2984) );
DFFRX2TS add_subt_module_YRegister_Q_reg_11_ ( .D(n909), .CK(clk), .RN(n1757), .Q(add_subt_module_intDY[11]), .QN(n2979) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n967), .CK(clk), .RN(n3081),
.Q(add_subt_module_intDY[3]), .QN(n2977) );
DFFRX2TS add_subt_module_YRegister_Q_reg_14_ ( .D(n916), .CK(clk), .RN(n3087), .Q(add_subt_module_intDY[14]), .QN(n2976) );
DFFRX2TS cont_var_count_reg_1_ ( .D(n1506), .CK(clk), .RN(n3101), .Q(
cont_var_out[1]), .QN(n2972) );
DFFRX2TS add_subt_module_XRegister_Q_reg_5_ ( .D(n934), .CK(clk), .RN(n3099),
.Q(add_subt_module_intDX[5]), .QN(n2970) );
DFFRX2TS add_subt_module_XRegister_Q_reg_7_ ( .D(n913), .CK(clk), .RN(n3099),
.Q(add_subt_module_intDX[7]), .QN(n2969) );
DFFRX2TS add_subt_module_YRegister_Q_reg_19_ ( .D(n964), .CK(clk), .RN(n3081), .Q(add_subt_module_intDY[19]), .QN(n2967) );
DFFRX2TS add_subt_module_YRegister_Q_reg_22_ ( .D(n973), .CK(clk), .RN(n3081), .Q(add_subt_module_intDY[22]), .QN(n2966) );
DFFRX2TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1009), .CK(clk), .RN(
n3079), .Q(add_subt_module_intDY[27]), .QN(n2960) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n950), .CK(clk), .RN(n3083), .Q(add_subt_module_intDY[15]), .QN(n2956) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1520), .CK(clk), .RN(n3074), .Q(
cordic_FSM_state_reg[2]), .QN(n2953) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1016), .CK(clk), .RN(n3130), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1019), .CK(clk), .RN(n1752), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1021), .CK(clk), .RN(n1752), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1023), .CK(clk), .RN(n3137), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1025), .CK(clk), .RN(n3137), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1027), .CK(clk), .RN(n3136), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1029), .CK(clk), .RN(n3135), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1031), .CK(clk), .RN(n3134), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1033), .CK(clk), .RN(n3133), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1041), .CK(clk), .RN(n3101), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1043), .CK(clk), .RN(n3104), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1039), .CK(clk), .RN(n3107), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1053), .CK(clk), .RN(n3108), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1045), .CK(clk), .RN(n3110), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1047), .CK(clk), .RN(n3112), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1051), .CK(clk), .RN(n3114), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1055), .CK(clk), .RN(n3116), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1061), .CK(clk), .RN(n3117), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1057), .CK(clk), .RN(n3117), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1065), .CK(clk), .RN(n3118), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1059), .CK(clk), .RN(n3118), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1071), .CK(clk), .RN(n3118), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1069), .CK(clk), .RN(n3118), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1077), .CK(clk), .RN(n3118), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1063), .CK(clk), .RN(n3119), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1049), .CK(clk), .RN(n3119), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1037), .CK(clk), .RN(n3119), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1075), .CK(clk), .RN(n3119), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1073), .CK(clk), .RN(n3119), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1067), .CK(clk), .RN(n3120), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1035), .CK(clk), .RN(n3120), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1079), .CK(clk), .RN(n3120), .Q(
data_output[0]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n976), .CK(clk), .RN(n3080),
.Q(add_subt_module_intDX[0]), .QN(n3048) );
DFFRX2TS add_subt_module_YRegister_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n3083),
.Q(add_subt_module_intDY[1]), .QN(n1561) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n1504), .CK(clk), .RN(n3130), .Q(n3071),
.QN(n1562) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n1519), .CK(clk), .RN(n3074), .Q(
cordic_FSM_state_reg[0]), .QN(n2971) );
DFFSX2TS add_subt_module_YRegister_Q_reg_31_ ( .D(n3141), .CK(clk), .SN(
n3099), .QN(add_subt_module_intDY[31]) );
DFFRX2TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n1358), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_C), .QN(n3002) );
DFFRX2TS add_subt_module_YRegister_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(
n3079), .QN(n3073) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n1335), .CK(clk), .RN(n3085), .Q(add_subt_module_Add_Subt_result[2]),
.QN(n3029) );
DFFRX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1011), .CK(clk), .RN(
n3079), .QN(n3072) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(n1511), .CK(clk),
.RN(n3090), .Q(add_subt_module_FS_Module_state_reg[3]), .QN(n3036) );
DFFRX2TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n1369), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_B[0]), .QN(n2980) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(n1510), .CK(clk),
.RN(n3074), .Q(add_subt_module_FS_Module_state_reg[0]), .QN(n2978) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_B[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(
n3053) );
DFFRX1TS add_subt_module_ASRegister_Q_reg_0_ ( .D(n1002), .CK(clk), .RN(
n3099), .Q(add_subt_module_intAS) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n933), .CK(clk), .RN(n3090),
.Q(add_subt_module_intDY[5]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n912), .CK(clk), .RN(n3100),
.Q(add_subt_module_intDY[7]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n985), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[25]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1000), .CK(clk), .RN(
n3080), .Q(add_subt_module_intDX[30]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n997), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[29]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n907), .CK(clk), .RN(n3084), .Q(add_subt_module_intDX[12]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n988), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[26]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n919), .CK(clk), .RN(n3088), .Q(add_subt_module_intDY[10]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_16_ ( .D(n923), .CK(clk), .RN(n1754), .Q(add_subt_module_intDY[16]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n991), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[27]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_9_ ( .D(n902), .CK(clk), .RN(n3085),
.Q(add_subt_module_intDY[9]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n1343), .CK(clk), .RN(n1757), .Q(add_subt_module_Add_Subt_result[10])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
n1339), .CK(clk), .RN(n3088), .Q(add_subt_module_Add_Subt_result[6])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n1334), .CK(clk), .RN(n3087), .Q(add_subt_module_Add_Subt_result[1])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
n1355), .CK(clk), .RN(n1754), .Q(add_subt_module_Add_Subt_result[22])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
n1337), .CK(clk), .RN(n3100), .Q(add_subt_module_Add_Subt_result[4])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
n1346), .CK(clk), .RN(n3087), .Q(add_subt_module_Add_Subt_result[13])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
n1347), .CK(clk), .RN(n3086), .Q(add_subt_module_Add_Subt_result[14])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n1345), .CK(clk), .RN(n3100), .Q(add_subt_module_Add_Subt_result[12])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n1348), .CK(clk), .RN(n3088), .Q(add_subt_module_Add_Subt_result[15])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n1341), .CK(clk), .RN(n1754), .Q(add_subt_module_Add_Subt_result[8])
);
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1095), .CK(clk), .RN(n3137),
.Q(d_ff2_Y[27]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n3091), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1364), .CK(clk), .RN(n3092), .Q(add_subt_module_exp_oper_result[3]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1365), .CK(clk), .RN(n3092), .Q(add_subt_module_exp_oper_result[4]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n3075), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1001), .CK(clk), .RN(n3098), .Q(add_subt_module_sign_final_result) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1093), .CK(clk), .RN(n3140),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1427), .CK(clk), .RN(n3133),
.Q(d_ff2_X[23]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1362), .CK(clk), .RN(n3091), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n3078), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n3078), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n1303), .CK(clk), .RN(n3098), .Q(
add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n3084), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n1311), .CK(clk), .RN(n3094), .Q(
add_subt_module_Sgf_normalized_result[9]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n1310), .CK(clk), .RN(n3094), .Q(
add_subt_module_Sgf_normalized_result[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n3139),
.Q(d_ff2_X[28]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n1304), .CK(clk), .RN(n3093), .Q(
add_subt_module_Sgf_normalized_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n1313), .CK(clk), .RN(n3095), .Q(
add_subt_module_Sgf_normalized_result[11]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n1312), .CK(clk), .RN(n3094), .Q(
add_subt_module_Sgf_normalized_result[10]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n1308), .CK(clk), .RN(n3094), .Q(
add_subt_module_Sgf_normalized_result[6]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n1309), .CK(clk), .RN(n3094), .Q(
add_subt_module_Sgf_normalized_result[7]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n1305), .CK(clk), .RN(n3093), .Q(
add_subt_module_Sgf_normalized_result[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n1307), .CK(clk), .RN(n3093), .Q(
add_subt_module_Sgf_normalized_result[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(n1293), .CK(clk), .RN(n3075), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(n1297), .CK(clk), .RN(n3074), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(n1301), .CK(clk), .RN(n3074), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n3041), .CK(clk), .RN(n3090), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(n1229), .CK(clk), .RN(n3078), .Q(result_add_subt[12]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(n1225), .CK(clk), .RN(n3078), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(n1237), .CK(clk), .RN(n3078), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(n1221), .CK(clk), .RN(n3078), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(n1245), .CK(clk), .RN(n3078), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(n1249), .CK(clk), .RN(n3077), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(n1233), .CK(clk), .RN(n3077), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(n1261), .CK(clk), .RN(n3077), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(n1241), .CK(clk), .RN(n3076), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(n1253), .CK(clk), .RN(n3076), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(n1265), .CK(clk), .RN(n3076), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(n1257), .CK(clk), .RN(n3076), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(n1269), .CK(clk), .RN(n3075), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(n1514), .CK(clk), .RN(n3074), .Q(result_add_subt[31]) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n1503), .CK(clk), .RN(n3120), .Q(
cont_iter_out[1]), .QN(n3143) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1097), .CK(clk), .RN(n3135),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1096), .CK(clk), .RN(n3136),
.Q(d_ff2_Y[26]) );
DFFRX4TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n3074), .Q(cordic_FSM_state_reg[1]), .QN(n2961) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1372), .CK(clk), .RN(n3129), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1148), .CK(clk), .RN(n3138),
.Q(d_ff2_Z[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n1271), .CK(clk), .RN(n3134), .QN(n3167) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n1275), .CK(clk), .RN(n3135), .QN(n3168) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1092), .CK(clk), .RN(n3140),
.Q(d_ff2_Y[30]) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(n1508), .CK(clk),
.RN(n3084), .Q(add_subt_module_FS_Module_state_reg[2]), .QN(n2959) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(n1509), .CK(clk),
.RN(n3074), .Q(add_subt_module_FS_Module_state_reg[1]), .QN(n2974) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n3078), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n3078), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n1215), .CK(clk), .RN(n3116), .QN(n3153) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n1207), .CK(clk), .RN(n3114), .QN(n3151) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n1195), .CK(clk), .RN(n3110), .QN(n3148) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n1199), .CK(clk), .RN(n3108), .QN(n3149) );
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n1183), .CK(clk), .RN(n3106), .QN(n3145) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n1211), .CK(clk), .RN(n3105), .QN(n3152) );
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n1191), .CK(clk), .RN(n3131), .QN(n3147) );
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n1203), .CK(clk), .RN(n3132), .QN(n3150) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n1146), .CK(clk), .RN(n3133), .QN(n3144) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1206), .CK(clk), .RN(n3114), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1198), .CK(clk), .RN(n3109), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1182), .CK(clk), .RN(n3106), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1190), .CK(clk), .RN(n3131), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1202), .CK(clk), .RN(n3131), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1274), .CK(clk), .RN(n3134), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1278), .CK(clk), .RN(n3135), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1282), .CK(clk), .RN(n3136), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1286), .CK(clk), .RN(n3137), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1214), .CK(clk), .RN(n3117), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1194), .CK(clk), .RN(n3111), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1210), .CK(clk), .RN(n3105), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n3129), .Q(d_ff_Xn[0])
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1402), .CK(clk), .RN(n3113),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1394), .CK(clk), .RN(n3112),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1406), .CK(clk), .RN(n3111),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1408), .CK(clk), .RN(n3110),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1400), .CK(clk), .RN(n3108),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1414), .CK(clk), .RN(n3107),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1378), .CK(clk), .RN(n3102), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1412), .CK(clk), .RN(n3101),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1083), .CK(clk), .RN(n3130),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1396), .CK(clk), .RN(n3115),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n3104),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1410), .CK(clk), .RN(n3103),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1416), .CK(clk), .RN(n3103),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1418), .CK(clk), .RN(n3132),
.Q(d_ff2_X[22]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(n1330), .CK(clk), .RN(n1757), .Q(add_subt_module_LZA_output[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1121), .CK(clk), .RN(n3116),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1123), .CK(clk), .RN(n3115),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1117), .CK(clk), .RN(n3113),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1125), .CK(clk), .RN(n3112),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1113), .CK(clk), .RN(n3111),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1111), .CK(clk), .RN(n3109),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1119), .CK(clk), .RN(n3107),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1105), .CK(clk), .RN(n3106),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1115), .CK(clk), .RN(n3104),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1109), .CK(clk), .RN(n3103),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1103), .CK(clk), .RN(n3102),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1141), .CK(clk), .RN(n3101), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1107), .CK(clk), .RN(n3135),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1101), .CK(clk), .RN(n3132),
.Q(d_ff2_Y[22]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n1518), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[25]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1500), .CK(clk), .RN(n3121), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n3174) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n1342), .CK(clk), .RN(n3089), .Q(add_subt_module_Add_Subt_result[9])
);
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1171), .CK(clk), .RN(n3105), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1173), .CK(clk), .RN(n3132), .Q(
d_ff2_Z[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n887),
.CK(clk), .RN(n3097), .Q(add_subt_module_DMP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n890),
.CK(clk), .RN(n3093), .Q(add_subt_module_DMP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n891),
.CK(clk), .RN(n3097), .Q(add_subt_module_DMP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n892),
.CK(clk), .RN(n3096), .Q(add_subt_module_DMP[15]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n899),
.CK(clk), .RN(n3095), .Q(add_subt_module_DMP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n914),
.CK(clk), .RN(n3096), .Q(add_subt_module_DMP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n928),
.CK(clk), .RN(n3096), .Q(add_subt_module_DMP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n935),
.CK(clk), .RN(n3095), .Q(add_subt_module_DMP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n939),
.CK(clk), .RN(n3097), .Q(add_subt_module_DMP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n952),
.CK(clk), .RN(n3096), .Q(add_subt_module_DMP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n992),
.CK(clk), .RN(n3092), .Q(add_subt_module_DMP[28]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n1445), .CK(clk), .RN(n3126), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n1091), .CK(clk), .RN(n3128), .Q(
d_ff3_sh_y_out[23]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_6_ ( .D(n970), .CK(clk), .RN(n3081),
.Q(add_subt_module_intDY[6]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_4_ ( .D(n926), .CK(clk), .RN(n3084),
.Q(add_subt_module_intDY[4]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_24_ ( .D(n982), .CK(clk), .RN(n3080), .Q(add_subt_module_intDX[24]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n960), .CK(clk), .RN(n3082),
.Q(add_subt_module_intDY[2]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1431), .CK(clk), .RN(n3137),
.Q(d_ff2_X[27]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
n1356), .CK(clk), .RN(n3086), .Q(add_subt_module_Add_Subt_result[23])
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n3140),
.Q(d_ff2_X[29]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n1302), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(n1289), .CK(clk), .RN(n3075), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(n1285), .CK(clk), .RN(n3075), .Q(result_add_subt[26]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(n1281), .CK(clk), .RN(n3075), .Q(result_add_subt[25]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(n1277), .CK(clk), .RN(n3075), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(n1273), .CK(clk), .RN(n3075), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n3044), .CK(clk), .RN(n3085), .Q(result_add_subt[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n3043), .CK(clk), .RN(n3084), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n3042), .CK(clk), .RN(n1757), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n1213), .CK(clk), .RN(n3100), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n3040), .CK(clk), .RN(n3089), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n3039), .CK(clk), .RN(n3088), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n3038), .CK(clk), .RN(n1754), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n3037), .CK(clk), .RN(n3089), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(n1217), .CK(clk), .RN(n3090), .Q(result_add_subt[9]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(n1328), .CK(clk), .RN(n3091), .Q(add_subt_module_LZA_output[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1430), .CK(clk), .RN(n3136),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1429), .CK(clk), .RN(n3135),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1098), .CK(clk), .RN(n3134),
.Q(d_ff2_Y[24]), .QN(n3012) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n1235), .CK(clk), .RN(n3113), .QN(n3158) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1466), .CK(clk), .RN(n3129), .Q(
sel_mux_1_reg) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n1371), .CK(clk), .RN(n3130), .QN(n3173) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n1283), .CK(clk), .RN(n3136), .QN(n3170) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n1279), .CK(clk), .RN(n3135), .QN(n3169) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n1255), .CK(clk), .RN(n3130), .QN(n3163) );
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n3101), .QN(n3146) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n1263), .CK(clk), .RN(n3102), .QN(n3165) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n3103), .QN(n3162) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n1239), .CK(clk), .RN(n3104), .QN(n3159) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n1259), .CK(clk), .RN(n3106), .QN(n3164) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n1231), .CK(clk), .RN(n3107), .QN(n3157) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n1247), .CK(clk), .RN(n3109), .QN(n3161) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n1243), .CK(clk), .RN(n3111), .QN(n3160) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n1219), .CK(clk), .RN(n3112), .QN(n3154) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1294), .CK(clk), .RN(n3140), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1290), .CK(clk), .RN(n3140), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1254), .CK(clk), .RN(n3101), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1186), .CK(clk), .RN(n3102), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1258), .CK(clk), .RN(n3107), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1230), .CK(clk), .RN(n3108), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1246), .CK(clk), .RN(n3109), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1242), .CK(clk), .RN(n3111), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1218), .CK(clk), .RN(n3112), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1234), .CK(clk), .RN(n3113), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1226), .CK(clk), .RN(n3116), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1513), .CK(clk), .RN(n3129), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1298), .CK(clk), .RN(n3140), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1270), .CK(clk), .RN(n3134), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n3132), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1262), .CK(clk), .RN(n3102), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n3103), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1238), .CK(clk), .RN(n3104), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1222), .CK(clk), .RN(n3115), .Q(
d_ff_Xn[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n3131), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1380), .CK(clk), .RN(n3131), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1376), .CK(clk), .RN(n3106), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1384), .CK(clk), .RN(n3109), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1388), .CK(clk), .RN(n3114), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1398), .CK(clk), .RN(n3116),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1374), .CK(clk), .RN(n3129), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1512), .CK(clk), .RN(n3129),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1390), .CK(clk), .RN(n3105), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1382), .CK(clk), .RN(n3111), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1392), .CK(clk), .RN(n3117), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1145), .CK(clk), .RN(n3133), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1133), .CK(clk), .RN(n3132), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1139), .CK(clk), .RN(n3131), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n3105), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1143), .CK(clk), .RN(n3106), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1135), .CK(clk), .RN(n3108), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1137), .CK(clk), .RN(n3110), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1131), .CK(clk), .RN(n3114), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1127), .CK(clk), .RN(n3117), .Q(
d_ff2_Y[9]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n1295), .CK(clk), .RN(n3140), .QN(n3172) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n1267), .CK(clk), .RN(n3133), .QN(n3166) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n1223), .CK(clk), .RN(n3115), .QN(n3155) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n1227), .CK(clk), .RN(n3115), .QN(n3156) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(n1329), .CK(clk), .RN(n3099), .Q(add_subt_module_LZA_output[2]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1521), .CK(clk), .RN(n3074), .Q(
cordic_FSM_state_reg[3]), .QN(n3022) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1157), .CK(clk), .RN(n3133),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1158), .CK(clk), .RN(n3102),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1166), .CK(clk), .RN(n3107),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1163), .CK(clk), .RN(n3111),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1169), .CK(clk), .RN(n3112),
.Q(d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1165), .CK(clk), .RN(n3113),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1168), .CK(clk), .RN(n3115),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1167), .CK(clk), .RN(n3115),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1149), .CK(clk), .RN(n1753),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1152), .CK(clk), .RN(n3137),
.Q(d_ff2_Z[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n975),
.CK(clk), .RN(n3081), .Q(add_subt_module_DmP[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n972),
.CK(clk), .RN(n3081), .Q(add_subt_module_DmP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n956),
.CK(clk), .RN(n3082), .Q(add_subt_module_DmP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n943),
.CK(clk), .RN(n3083), .Q(add_subt_module_DmP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n940),
.CK(clk), .RN(n3083), .Q(add_subt_module_DmP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n936),
.CK(clk), .RN(n3086), .Q(add_subt_module_DmP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n932),
.CK(clk), .RN(n3089), .Q(add_subt_module_DmP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n929),
.CK(clk), .RN(n3090), .Q(add_subt_module_DmP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n901),
.CK(clk), .RN(n3087), .Q(add_subt_module_DmP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n998),
.CK(clk), .RN(n3093), .Q(add_subt_module_DMP[30]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n995),
.CK(clk), .RN(n3092), .Q(add_subt_module_DMP[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n989),
.CK(clk), .RN(n3092), .Q(add_subt_module_DMP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n986),
.CK(clk), .RN(n3092), .Q(add_subt_module_DMP[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n983),
.CK(clk), .RN(n3092), .Q(add_subt_module_DMP[25]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n980),
.CK(clk), .RN(n3091), .Q(add_subt_module_DMP[24]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n977),
.CK(clk), .RN(n3091), .Q(add_subt_module_DMP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n962),
.CK(clk), .RN(n3097), .Q(add_subt_module_DMP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n921),
.CK(clk), .RN(n3096), .Q(add_subt_module_DMP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n904),
.CK(clk), .RN(n3095), .Q(add_subt_module_DMP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n900),
.CK(clk), .RN(n3095), .Q(add_subt_module_DMP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n898),
.CK(clk), .RN(n3094), .Q(add_subt_module_DMP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n897),
.CK(clk), .RN(n3095), .Q(add_subt_module_DMP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n896),
.CK(clk), .RN(n3094), .Q(add_subt_module_DMP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n894),
.CK(clk), .RN(n3093), .Q(add_subt_module_DMP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n893),
.CK(clk), .RN(n3094), .Q(add_subt_module_DMP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n889),
.CK(clk), .RN(n3093), .Q(add_subt_module_DMP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n888),
.CK(clk), .RN(n3094), .Q(add_subt_module_DMP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n886),
.CK(clk), .RN(n3093), .Q(add_subt_module_DMP[0]) );
DFFRX1TS d_ff5_Q_reg_31_ ( .D(n1018), .CK(clk), .RN(n3130), .Q(
data_output2_31_) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n3079), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n1291), .CK(clk), .RN(n3138), .QN(n3171) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1434), .CK(clk), .RN(n1752),
.Q(d_ff2_X[30]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1367), .CK(clk), .RN(n3092), .Q(add_subt_module_exp_oper_result[6]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1366), .CK(clk), .RN(n3092), .Q(add_subt_module_exp_oper_result[5]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1360), .CK(clk), .RN(n3092), .Q(add_subt_module_exp_oper_result[7]) );
DFFRX2TS cont_iter_count_reg_3_ ( .D(n1505), .CK(clk), .RN(n3121), .Q(
cont_iter_out[3]), .QN(n2957) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n1350), .CK(clk), .RN(n1757), .Q(add_subt_module_Add_Subt_result[17]),
.QN(n3045) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
n1332), .CK(clk), .RN(n3098), .Q(add_subt_module_Add_Subt_result[25]),
.QN(n3026) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
n1354), .CK(clk), .RN(n3084), .Q(add_subt_module_Add_Subt_result[21]),
.QN(n3024) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n1352), .CK(clk), .RN(n3087), .Q(add_subt_module_Add_Subt_result[19]),
.QN(n2981) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
n1349), .CK(clk), .RN(n3089), .Q(add_subt_module_Add_Subt_result[16]),
.QN(n2973) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
n1351), .CK(clk), .RN(n3085), .Q(add_subt_module_Add_Subt_result[18]),
.QN(n2958) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
n1357), .CK(clk), .RN(n3090), .Q(add_subt_module_Add_Subt_result[24])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(n1517), .CK(clk), .RN(n3093), .Q(add_subt_module_add_overflow_flag),
.QN(n3142) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n1306), .CK(clk), .RN(n3093), .Q(
add_subt_module_Sgf_normalized_result[4]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n1333), .CK(clk), .RN(n3098), .Q(add_subt_module_Add_Subt_result[0]),
.QN(n3027) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1465), .CK(clk), .RN(n3129), .Q(
sel_mux_2_reg[0]), .QN(n3046) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(clk), .RN(n3098), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(
n3051) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1501), .CK(clk), .RN(n3121), .Q(
d_ff1_operation_out), .QN(n3049) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1099), .CK(clk), .RN(n3134),
.Q(d_ff2_Y[23]), .QN(n2975) );
DFFRX1TS add_subt_module_XRegister_Q_reg_14_ ( .D(n917), .CK(clk), .RN(n3085), .Q(add_subt_module_intDX[14]), .QN(n2964) );
DFFRX1TS add_subt_module_XRegister_Q_reg_11_ ( .D(n910), .CK(clk), .RN(n3090), .Q(add_subt_module_intDX[11]), .QN(n2954) );
DFFRX1TS add_subt_module_XRegister_Q_reg_22_ ( .D(n974), .CK(clk), .RN(n3081), .Q(add_subt_module_intDX[22]), .QN(n2985) );
DFFRX1TS add_subt_module_XRegister_Q_reg_21_ ( .D(n958), .CK(clk), .RN(n3082), .Q(add_subt_module_intDX[21]), .QN(n2965) );
DFFRX1TS add_subt_module_XRegister_Q_reg_20_ ( .D(n942), .CK(clk), .RN(n3083), .Q(add_subt_module_intDX[20]), .QN(n2987) );
DFFRX1TS add_subt_module_XRegister_Q_reg_19_ ( .D(n965), .CK(clk), .RN(n3081), .Q(add_subt_module_intDX[19]), .QN(n2989) );
DFFRX1TS add_subt_module_XRegister_Q_reg_18_ ( .D(n955), .CK(clk), .RN(n3082), .Q(add_subt_module_intDX[18]), .QN(n2986) );
DFFRX1TS add_subt_module_XRegister_Q_reg_17_ ( .D(n931), .CK(clk), .RN(n3089), .Q(add_subt_module_intDX[17]), .QN(n2962) );
DFFRX1TS add_subt_module_XRegister_Q_reg_15_ ( .D(n951), .CK(clk), .RN(n3082), .Q(add_subt_module_intDX[15]), .QN(n2963) );
DFFRX1TS add_subt_module_XRegister_Q_reg_13_ ( .D(n938), .CK(clk), .RN(n3083), .Q(add_subt_module_intDX[13]), .QN(n2990) );
DFFRX1TS add_subt_module_XRegister_Q_reg_8_ ( .D(n948), .CK(clk), .RN(n1757),
.Q(add_subt_module_intDX[8]), .QN(n2994) );
DFFRX1TS add_subt_module_XRegister_Q_reg_3_ ( .D(n968), .CK(clk), .RN(n3098),
.Q(add_subt_module_intDX[3]), .QN(n2992) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n961), .CK(clk), .RN(n3098),
.Q(add_subt_module_intDX[2]), .QN(n2995) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n3098),
.Q(add_subt_module_intDX[1]), .QN(n2955) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n903), .CK(clk), .RN(n3099),
.Q(add_subt_module_intDX[9]), .QN(n2968) );
DFFRX1TS add_subt_module_YRegister_Q_reg_24_ ( .D(n1006), .CK(clk), .RN(
n3079), .Q(add_subt_module_intDY[24]), .QN(n2988) );
DFFRX1TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1013), .CK(clk), .RN(n3098), .Q(add_subt_module_intDY[0]), .QN(n3003) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n1340), .CK(clk), .RN(n3088), .Q(add_subt_module_Add_Subt_result[7]),
.QN(n3031) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n3075), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(
n3055) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(
n3054) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(
n3058) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
n1338), .CK(clk), .RN(n1754), .Q(add_subt_module_Add_Subt_result[5]),
.QN(n3030) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(clk), .RN(n3098), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(
n3050) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n3077), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(
n3056) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(clk), .RN(n3076), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(
n3057) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n3078), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(
n3060) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n3079), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(
n3059) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n1326), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[24]), .QN(n3047) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n1314), .CK(clk), .RN(n3095), .Q(
add_subt_module_Sgf_normalized_result[12]), .QN(n2983) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n1317), .CK(clk), .RN(n3095), .Q(
add_subt_module_Sgf_normalized_result[15]), .QN(n3009) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n1319), .CK(clk), .RN(n3096), .Q(
add_subt_module_Sgf_normalized_result[17]), .QN(n3007) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n1318), .CK(clk), .RN(n3096), .Q(
add_subt_module_Sgf_normalized_result[16]), .QN(n3008) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n1344), .CK(clk), .RN(n3085), .Q(add_subt_module_Add_Subt_result[11]),
.QN(n3028) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1428), .CK(clk), .RN(n3134),
.Q(d_ff2_X[24]), .QN(n3014) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n1320), .CK(clk), .RN(n3096), .Q(
add_subt_module_Sgf_normalized_result[18]), .QN(n3020) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n1322), .CK(clk), .RN(n3096), .Q(
add_subt_module_Sgf_normalized_result[20]), .QN(n3018) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n1321), .CK(clk), .RN(n3096), .Q(
add_subt_module_Sgf_normalized_result[19]), .QN(n3019) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n1323), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[21]), .QN(n3034) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n1325), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[23]), .QN(n3032) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n1324), .CK(clk), .RN(n3097), .Q(
add_subt_module_Sgf_normalized_result[22]), .QN(n3033) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1359),
.CK(clk), .RN(n3087), .Q(overflow_flag), .QN(n3068) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1515),
.CK(clk), .RN(n3086), .Q(underflow_flag), .QN(n3069) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
n1353), .CK(clk), .RN(n3086), .Q(add_subt_module_Add_Subt_result[20])
);
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(n1327), .CK(clk), .RN(n3091), .Q(add_subt_module_LZA_output[4]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n1316), .CK(clk), .RN(n3095), .Q(
add_subt_module_Sgf_normalized_result[14]), .QN(n2982) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n895),
.CK(clk), .RN(n3094), .Q(add_subt_module_DMP[5]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n1315), .CK(clk), .RN(n3095), .Q(
add_subt_module_Sgf_normalized_result[13]), .QN(n3010) );
AOI222X1TS U1619 ( .A0(n2065), .A1(d_ff2_Z[25]), .B0(n2064), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2768), .Y(n2028) );
AOI222X1TS U1620 ( .A0(n2065), .A1(d_ff2_Z[26]), .B0(n2064), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2768), .Y(n2053) );
AOI222X1TS U1621 ( .A0(n2065), .A1(d_ff2_Z[18]), .B0(n2059), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2768), .Y(n2030) );
AOI32X1TS U1622 ( .A0(n1848), .A1(n2796), .A2(n1562), .B0(d_ff3_LUT_out[23]),
.B1(n2710), .Y(n1849) );
AOI222X1TS U1623 ( .A0(n2056), .A1(d_ff2_Z[5]), .B0(n2055), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2732), .Y(n2057) );
AOI222X1TS U1624 ( .A0(n2056), .A1(d_ff2_Z[2]), .B0(n2055), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2732), .Y(n2054) );
AOI222X1TS U1625 ( .A0(n2056), .A1(d_ff2_Z[7]), .B0(n2055), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2732), .Y(n2047) );
AOI222X1TS U1626 ( .A0(n2056), .A1(d_ff2_Z[0]), .B0(n2055), .B1(d_ff1_Z[0]),
.C0(d_ff_Zn[0]), .C1(n2732), .Y(n2045) );
AOI222X1TS U1627 ( .A0(n2056), .A1(d_ff2_Z[3]), .B0(n2055), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2732), .Y(n2039) );
AOI222X1TS U1628 ( .A0(n2056), .A1(d_ff2_Z[1]), .B0(n2055), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2732), .Y(n2037) );
AOI222X1TS U1629 ( .A0(n2056), .A1(d_ff2_Z[4]), .B0(n2055), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2732), .Y(n2036) );
AOI222X1TS U1630 ( .A0(n2056), .A1(d_ff2_Z[9]), .B0(n2055), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2058), .Y(n2033) );
AOI222X1TS U1631 ( .A0(n2065), .A1(d_ff2_Z[29]), .B0(n2064), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2063), .Y(n2048) );
AOI222X1TS U1632 ( .A0(n2065), .A1(d_ff2_Z[20]), .B0(n2064), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2063), .Y(n2062) );
AOI222X1TS U1633 ( .A0(n2065), .A1(d_ff2_Z[28]), .B0(n2064), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2063), .Y(n2040) );
AOI222X1TS U1634 ( .A0(n2065), .A1(d_ff2_Z[24]), .B0(n2064), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2063), .Y(n2044) );
AOI222X1TS U1635 ( .A0(n2065), .A1(d_ff2_Z[23]), .B0(n2064), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2063), .Y(n2031) );
AOI222X1TS U1636 ( .A0(n2065), .A1(d_ff2_Z[19]), .B0(n2059), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2063), .Y(n2034) );
AOI222X1TS U1637 ( .A0(n2056), .A1(d_ff2_Z[17]), .B0(n2059), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2058), .Y(n2051) );
AOI222X1TS U1638 ( .A0(n2056), .A1(d_ff2_Z[15]), .B0(n2059), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2058), .Y(n2041) );
AOI32X1TS U1639 ( .A0(d_ff2_X[23]), .A1(n2796), .A2(n1562), .B0(
d_ff3_sh_x_out[23]), .B1(n2710), .Y(n2711) );
CMPR32X2TS U1640 ( .A(d_ff2_Y[26]), .B(n1536), .C(n2786), .CO(n2788), .S(
n2785) );
CMPR32X2TS U1641 ( .A(d_ff2_X[26]), .B(n1536), .C(n2718), .CO(n2721), .S(
n2717) );
NAND2X1TS U1642 ( .A(cont_iter_out[1]), .B(n3071), .Y(n2687) );
CMPR32X2TS U1643 ( .A(d_ff2_X[25]), .B(n2783), .C(n2716), .CO(n2718), .S(
n1769) );
CMPR32X2TS U1644 ( .A(d_ff2_Y[25]), .B(n2783), .C(n2782), .CO(n2786), .S(
n2781) );
NAND2X1TS U1645 ( .A(n1581), .B(n1580), .Y(n1631) );
OAI2BB2XLTS U1646 ( .B0(add_subt_module_intDY[12]), .B1(n2116), .A0N(
add_subt_module_intDX[13]), .A1N(n2996), .Y(n2128) );
NOR2X4TS U1647 ( .A(add_subt_module_FSM_selector_B[1]), .B(n2980), .Y(n1574)
);
NAND2X1TS U1648 ( .A(n2511), .B(n2307), .Y(n2309) );
NAND2X1TS U1649 ( .A(n2561), .B(n2329), .Y(n2583) );
NOR2X1TS U1650 ( .A(n2517), .B(n2519), .Y(n2307) );
INVX2TS U1651 ( .A(n3001), .Y(n2386) );
OAI211XLTS U1652 ( .A0(n2977), .A1(add_subt_module_intDX[3]), .B0(n2107),
.C0(n2106), .Y(n2110) );
NOR2XLTS U1653 ( .A(n3032), .B(add_subt_module_FSM_selector_D), .Y(n2376) );
NAND2X1TS U1654 ( .A(n2585), .B(n2339), .Y(n2341) );
NOR2XLTS U1655 ( .A(n3010), .B(add_subt_module_FSM_selector_D), .Y(n2318) );
INVX2TS U1656 ( .A(n2270), .Y(n2246) );
CLKINVX3TS U1657 ( .A(n2437), .Y(n2388) );
INVX2TS U1658 ( .A(n1730), .Y(n1731) );
NOR2X1TS U1659 ( .A(n1797), .B(n2735), .Y(n2657) );
NOR2XLTS U1660 ( .A(n2466), .B(n2465), .Y(n2471) );
NOR2XLTS U1661 ( .A(add_subt_module_LZA_output[4]), .B(n2454), .Y(n2254) );
AOI31XLTS U1662 ( .A0(n2256), .A1(n2454), .A2(n2255), .B0(n2254), .Y(n1327)
);
OAI211XLTS U1663 ( .A0(n1917), .A1(n1533), .B0(n1911), .C0(n1910), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
OAI211XLTS U1664 ( .A0(n2027), .A1(n3055), .B0(n1994), .C0(n1993), .Y(n1306)
);
OAI211XLTS U1665 ( .A0(n1944), .A1(n2083), .B0(n1933), .C0(n1932), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI21XLTS U1666 ( .A0(n2208), .A1(n2970), .B0(n2174), .Y(n895) );
OAI21XLTS U1667 ( .A0(n2968), .A1(n1540), .B0(n2215), .Y(n901) );
OAI211XLTS U1668 ( .A0(n1938), .A1(n2083), .B0(n1923), .C0(n1922), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
OAI211XLTS U1669 ( .A0(n1858), .A1(n2073), .B0(n2072), .C0(n2071), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI211XLTS U1670 ( .A0(n2073), .A1(n2083), .B0(n1870), .C0(n1869), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI211XLTS U1671 ( .A0(n2027), .A1(n3058), .B0(n1985), .C0(n1984), .Y(n1307)
);
OAI211XLTS U1672 ( .A0(n2073), .A1(n1533), .B0(n1874), .C0(n1873), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NOR2XLTS U1673 ( .A(n2092), .B(n2262), .Y(n1510) );
OAI211X1TS U1674 ( .A0(n2452), .A1(n2451), .B0(n2450), .C0(n2449), .Y(n2455)
);
OAI21X1TS U1675 ( .A0(n1648), .A1(n1647), .B0(n1646), .Y(n1649) );
NAND3BX1TS U1676 ( .AN(n2626), .B(n2625), .C(n2624), .Y(n2628) );
OAI21X1TS U1677 ( .A0(n3073), .A1(n1540), .B0(n2178), .Y(n998) );
INVX4TS U1678 ( .A(n1540), .Y(n2236) );
OAI21X1TS U1679 ( .A0(n2990), .A1(n1541), .B0(n2179), .Y(n936) );
OAI21X1TS U1680 ( .A0(n2995), .A1(n1541), .B0(n2221), .Y(n959) );
INVX4TS U1681 ( .A(n1540), .Y(n2242) );
OAI21X1TS U1682 ( .A0(n3072), .A1(n1541), .B0(n2212), .Y(n995) );
OAI21X1TS U1683 ( .A0(n2985), .A1(n1541), .B0(n2172), .Y(n972) );
OAI21X1TS U1684 ( .A0(n3006), .A1(n1541), .B0(n2177), .Y(n904) );
OAI21X1TS U1685 ( .A0(n2965), .A1(n1541), .B0(n2171), .Y(n956) );
INVX4TS U1686 ( .A(n1540), .Y(n2205) );
OAI211X1TS U1687 ( .A0(n1960), .A1(n2636), .B0(n1959), .C0(n1958), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI21X1TS U1688 ( .A0(n1971), .A1(n1970), .B0(n1969), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
INVX4TS U1689 ( .A(n1539), .Y(n1540) );
OAI211X1TS U1690 ( .A0(n2084), .A1(n2070), .B0(n2069), .C0(n2068), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
CLKXOR2X2TS U1691 ( .A(n1634), .B(n1633), .Y(n2616) );
OAI211X1TS U1692 ( .A0(n1944), .A1(n1533), .B0(n1943), .C0(n1942), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
OAI211X1TS U1693 ( .A0(n1858), .A1(n1944), .B0(n1907), .C0(n1906), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI211X1TS U1694 ( .A0(n1917), .A1(n2083), .B0(n1916), .C0(n1915), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI211X1TS U1695 ( .A0(n1858), .A1(n1917), .B0(n1895), .C0(n1894), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
OAI211X1TS U1696 ( .A0(n1938), .A1(n1533), .B0(n1889), .C0(n1888), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI211X1TS U1697 ( .A0(n1858), .A1(n1938), .B0(n1927), .C0(n1926), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI211X1TS U1698 ( .A0(n1938), .A1(n2070), .B0(n1937), .C0(n1936), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
NAND4BX1TS U1699 ( .AN(n2685), .B(n2796), .C(n2702), .D(n2701), .Y(n2706) );
INVX4TS U1700 ( .A(n2780), .Y(n2796) );
INVX3TS U1701 ( .A(n2764), .Y(n2065) );
NAND3BX1TS U1702 ( .AN(n1647), .B(n1648), .C(
add_subt_module_Add_Subt_result[14]), .Y(n2449) );
INVX3TS U1703 ( .A(n1891), .Y(n1948) );
INVX4TS U1704 ( .A(n2085), .Y(n2241) );
NOR2X1TS U1705 ( .A(n3019), .B(n2385), .Y(n2360) );
NOR2X1TS U1706 ( .A(n3020), .B(n2385), .Y(n2357) );
NAND2BX1TS U1707 ( .AN(add_subt_module_intDX[13]), .B(
add_subt_module_intDY[13]), .Y(n2115) );
OAI21X1TS U1708 ( .A0(add_subt_module_intDX[23]), .A1(n3015), .B0(
add_subt_module_intDX[22]), .Y(n2145) );
NOR2X1TS U1709 ( .A(n3018), .B(add_subt_module_FSM_selector_D), .Y(n2364) );
NOR2X1TS U1710 ( .A(n3034), .B(add_subt_module_FSM_selector_D), .Y(n2367) );
NOR2X1TS U1711 ( .A(add_subt_module_FSM_selector_D), .B(n2983), .Y(n2316) );
AOI21X1TS U1712 ( .A0(n2626), .A1(n1642), .B0(n2629), .Y(n1643) );
NOR3X2TS U1713 ( .A(add_subt_module_Add_Subt_result[3]), .B(
add_subt_module_Add_Subt_result[2]), .C(n2246), .Y(n2253) );
OAI21X1TS U1714 ( .A0(n3035), .A1(n2202), .B0(n2186), .Y(n921) );
OAI21X1TS U1715 ( .A0(n2962), .A1(n2202), .B0(n2200), .Y(n928) );
OAI21X1TS U1716 ( .A0(n2987), .A1(n2202), .B0(n2201), .Y(n939) );
OAI21X1TS U1717 ( .A0(n2965), .A1(n2202), .B0(n2197), .Y(n891) );
OAI21X1TS U1718 ( .A0(n3073), .A1(n2208), .B0(n2192), .Y(n999) );
OAI21X1TS U1719 ( .A0(n2988), .A1(n2208), .B0(n2203), .Y(n981) );
OAI21X1TS U1720 ( .A0(n2244), .A1(n2955), .B0(n2237), .Y(n894) );
OAI21X1TS U1721 ( .A0(n2244), .A1(n3021), .B0(n2233), .Y(n888) );
OAI21X1TS U1722 ( .A0(n2960), .A1(n2208), .B0(n2193), .Y(n990) );
OAI21X1TS U1723 ( .A0(n3072), .A1(n2208), .B0(n2189), .Y(n996) );
OAI21X1TS U1724 ( .A0(n2244), .A1(n3048), .B0(n2230), .Y(n886) );
OAI21X1TS U1725 ( .A0(n2244), .A1(n2994), .B0(n2240), .Y(n893) );
OAI211X1TS U1726 ( .A0(n3054), .A1(n2027), .B0(n1982), .C0(n1981), .Y(n1309)
);
OAI211X1TS U1727 ( .A0(n2027), .A1(n3056), .B0(n2026), .C0(n2025), .Y(n1305)
);
OAI21X1TS U1728 ( .A0(n2987), .A1(n2226), .B0(n2180), .Y(n940) );
OAI211X1TS U1729 ( .A0(n3053), .A1(n2027), .B0(n1979), .C0(n1978), .Y(n1308)
);
OAI211X1TS U1730 ( .A0(n2027), .A1(n3057), .B0(n1997), .C0(n1996), .Y(n1304)
);
OAI21X1TS U1731 ( .A0(n3004), .A1(n2226), .B0(n2214), .Y(n983) );
OAI21X1TS U1732 ( .A0(n2963), .A1(n2226), .B0(n2169), .Y(n949) );
OAI21X1TS U1733 ( .A0(n2986), .A1(n2226), .B0(n2170), .Y(n953) );
OAI21X1TS U1734 ( .A0(n2960), .A1(n2226), .B0(n2209), .Y(n989) );
OAI21X1TS U1735 ( .A0(n2988), .A1(n2226), .B0(n2176), .Y(n980) );
OAI21X1TS U1736 ( .A0(n3016), .A1(n2226), .B0(n2210), .Y(n986) );
OAI21X1TS U1737 ( .A0(n3021), .A1(n2226), .B0(n2225), .Y(n969) );
OAI21X1TS U1738 ( .A0(n3015), .A1(n2226), .B0(n2164), .Y(n977) );
OAI21X1TS U1739 ( .A0(n3013), .A1(n2226), .B0(n2163), .Y(n978) );
OAI21X1TS U1740 ( .A0(n2955), .A1(n1540), .B0(n2220), .Y(n943) );
OAI21X1TS U1741 ( .A0(n3006), .A1(n2160), .B0(n2159), .Y(n905) );
OAI21X1TS U1742 ( .A0(n2970), .A1(n1541), .B0(n2228), .Y(n932) );
OAI211X1TS U1743 ( .A0(n2419), .A1(n3057), .B0(n2418), .C0(n2417), .Y(n2420)
);
OAI211X1TS U1744 ( .A0(n2419), .A1(n3056), .B0(n2414), .C0(n2413), .Y(n2415)
);
OAI21X1TS U1745 ( .A0(n2954), .A1(n2222), .B0(n2162), .Y(n908) );
OAI21X1TS U1746 ( .A0(n3003), .A1(n2202), .B0(n2187), .Y(n975) );
OAI211X1TS U1747 ( .A0(n2398), .A1(n3051), .B0(n2007), .C0(n2006), .Y(n1310)
);
OAI21X1TS U1748 ( .A0(n2992), .A1(n2222), .B0(n2168), .Y(n966) );
OAI21X1TS U1749 ( .A0(n2962), .A1(n2222), .B0(n2173), .Y(n929) );
OAI21X1TS U1750 ( .A0(n2994), .A1(n2222), .B0(n2175), .Y(n946) );
OAI21X1TS U1751 ( .A0(n2989), .A1(n1540), .B0(n2167), .Y(n963) );
OAI21X1TS U1752 ( .A0(n2984), .A1(n2222), .B0(n2165), .Y(n992) );
OAI211X1TS U1753 ( .A0(n2398), .A1(n3050), .B0(n2015), .C0(n2014), .Y(n1311)
);
INVX2TS U1754 ( .A(n2185), .Y(n2202) );
OAI211X1TS U1755 ( .A0(n3050), .A1(n2027), .B0(n1991), .C0(n1990), .Y(n1303)
);
OAI211X1TS U1756 ( .A0(n2084), .A1(n2083), .B0(n2082), .C0(n2081), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI211X1TS U1757 ( .A0(n1858), .A1(n2084), .B0(n1964), .C0(n1963), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
INVX2TS U1758 ( .A(n2229), .Y(n2244) );
INVX2TS U1759 ( .A(n2185), .Y(n2208) );
OAI211X1TS U1760 ( .A0(n2084), .A1(n1533), .B0(n2077), .C0(n2076), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND2X2TS U1761 ( .A(n2245), .B(n2252), .Y(n2248) );
OR2X2TS U1762 ( .A(n2158), .B(n2241), .Y(n2222) );
OR2X2TS U1763 ( .A(n1975), .B(n1974), .Y(n2011) );
INVX1TS U1764 ( .A(n2562), .Y(n2563) );
NAND2BX1TS U1765 ( .AN(n1729), .B(n1728), .Y(n1511) );
AOI222X1TS U1766 ( .A0(n2634), .A1(n1559), .B0(n2632), .B1(n1556), .C0(n2633), .C1(n1547), .Y(n1971) );
OR2X2TS U1767 ( .A(n2021), .B(n1973), .Y(n1531) );
AO22XLTS U1768 ( .A0(n2723), .A1(d_ff2_X[31]), .B0(n2710), .B1(
d_ff3_sh_x_out[31]), .Y(n1435) );
OR2X2TS U1769 ( .A(n1977), .B(n1973), .Y(n1672) );
INVX3TS U1770 ( .A(n2070), .Y(n1548) );
NOR2X1TS U1771 ( .A(n1602), .B(n1601), .Y(n1607) );
NOR2X1TS U1772 ( .A(sel_mux_1_reg), .B(n2770), .Y(n1965) );
INVX2TS U1773 ( .A(n2780), .Y(n2723) );
INVX2TS U1774 ( .A(n2780), .Y(n2792) );
AOI32X2TS U1775 ( .A0(n1884), .A1(n2639), .A2(n1883), .B0(n1925), .B1(n2636),
.Y(n1934) );
INVX3TS U1776 ( .A(n1858), .Y(n1553) );
AND2X2TS U1777 ( .A(n2017), .B(n2008), .Y(n1748) );
OR2X2TS U1778 ( .A(n1862), .B(n1861), .Y(n1533) );
NAND2X4TS U1779 ( .A(n1862), .B(n1861), .Y(n1858) );
AOI31X2TS U1780 ( .A0(cont_iter_out[1]), .A1(n2783), .A2(n2957), .B0(n2679),
.Y(n1839) );
INVX2TS U1781 ( .A(n2764), .Y(n2770) );
NAND2X2TS U1782 ( .A(n1659), .B(n2958), .Y(n1647) );
NAND2BX2TS U1783 ( .AN(n1801), .B(sel_mux_3_reg), .Y(n1799) );
NOR2X2TS U1784 ( .A(sel_mux_3_reg), .B(n1801), .Y(n1787) );
INVX3TS U1785 ( .A(n1998), .Y(n2403) );
NAND3BX1TS U1786 ( .AN(n2737), .B(n2736), .C(n2735), .Y(n2739) );
INVX3TS U1787 ( .A(n2085), .Y(n2238) );
INVX3TS U1788 ( .A(n1877), .Y(n2392) );
OAI211X1TS U1789 ( .A0(n2097), .A1(n2153), .B0(n2096), .C0(n2095), .Y(n2102)
);
OAI2BB2XLTS U1790 ( .B0(n2124), .B1(n2131), .A0N(n2123), .A1N(n2122), .Y(
n2127) );
INVX3TS U1791 ( .A(n2085), .Y(n2224) );
AND2X2TS U1792 ( .A(n2442), .B(n2981), .Y(n1659) );
NOR3X1TS U1793 ( .A(n2642), .B(cordic_FSM_state_reg[2]), .C(
cordic_FSM_state_reg[3]), .Y(n1742) );
AND2X2TS U1794 ( .A(n1668), .B(n1776), .Y(n1998) );
INVX3TS U1795 ( .A(n2085), .Y(n2227) );
NOR2X4TS U1796 ( .A(n2645), .B(n2642), .Y(n1772) );
INVX3TS U1797 ( .A(n1877), .Y(n1962) );
NAND2X2TS U1798 ( .A(n2654), .B(n2641), .Y(n2806) );
NAND3X2TS U1799 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n1794), .Y(n1801) );
OR3X2TS U1800 ( .A(n2971), .B(n2645), .C(cordic_FSM_state_reg[1]), .Y(n2714)
);
NOR2X2TS U1801 ( .A(n2266), .B(n1644), .Y(n2442) );
OAI211XLTS U1802 ( .A0(add_subt_module_intDX[8]), .A1(n3000), .B0(n2119),
.C0(n2122), .Y(n2133) );
CLKAND2X4TS U1803 ( .A(n1676), .B(n1675), .Y(n2456) );
NOR2X4TS U1804 ( .A(n1686), .B(n1685), .Y(n1687) );
OAI211X2TS U1805 ( .A0(add_subt_module_intDX[12]), .A1(n3006), .B0(n2129),
.C0(n2115), .Y(n2131) );
NOR2X1TS U1806 ( .A(n3033), .B(n2385), .Y(n2372) );
OR2X2TS U1807 ( .A(n1778), .B(n2258), .Y(n2655) );
AND2X4TS U1808 ( .A(n1725), .B(n1730), .Y(n2085) );
NAND3X1TS U1809 ( .A(n3016), .B(n2094), .C(add_subt_module_intDX[26]), .Y(
n2096) );
NOR2X4TS U1810 ( .A(n1778), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n2502) );
INVX2TS U1811 ( .A(n2698), .Y(n2783) );
OAI221XLTS U1812 ( .A0(n2970), .A1(add_subt_module_intDY[5]), .B0(n3011),
.B1(add_subt_module_intDY[4]), .C0(n1698), .Y(n1703) );
OAI211X2TS U1813 ( .A0(add_subt_module_sign_final_result), .A1(r_mode[1]),
.B0(n1689), .C0(n1688), .Y(n1781) );
OAI221XLTS U1814 ( .A0(n2986), .A1(add_subt_module_intDY[18]), .B0(n3072),
.B1(add_subt_module_intDX[29]), .C0(n1706), .Y(n1711) );
OAI221XLTS U1815 ( .A0(n3004), .A1(add_subt_module_intDX[25]), .B0(n2988),
.B1(add_subt_module_intDX[24]), .C0(n1708), .Y(n1709) );
OAI221XLTS U1816 ( .A0(n2968), .A1(add_subt_module_intDY[9]), .B0(n2954),
.B1(add_subt_module_intDY[11]), .C0(n1692), .Y(n1693) );
OAI221XLTS U1817 ( .A0(n2985), .A1(add_subt_module_intDY[22]), .B0(n3006),
.B1(add_subt_module_intDX[12]), .C0(n1716), .Y(n1717) );
OAI211X2TS U1818 ( .A0(add_subt_module_intDX[20]), .A1(n2991), .B0(n2149),
.C0(n2134), .Y(n2143) );
INVX4TS U1819 ( .A(n3070), .Y(n2698) );
NAND2BX1TS U1820 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n2095) );
NAND2BX1TS U1821 ( .AN(add_subt_module_intDX[27]), .B(
add_subt_module_intDY[27]), .Y(n2094) );
NOR2X1TS U1822 ( .A(add_subt_module_Add_Subt_result[9]), .B(
add_subt_module_Add_Subt_result[8]), .Y(n2245) );
INVX1TS U1823 ( .A(d_ff1_shift_region_flag_out[1]), .Y(n2661) );
NAND2BX1TS U1824 ( .AN(add_subt_module_intDX[24]), .B(
add_subt_module_intDY[24]), .Y(n2150) );
NAND2BX1TS U1825 ( .AN(add_subt_module_intDX[21]), .B(
add_subt_module_intDY[21]), .Y(n2134) );
NOR2X2TS U1826 ( .A(add_subt_module_Add_Subt_result[25]), .B(
add_subt_module_Add_Subt_result[24]), .Y(n2448) );
NAND2BX1TS U1827 ( .AN(add_subt_module_intDX[19]), .B(
add_subt_module_intDY[19]), .Y(n2140) );
NOR2X2TS U1828 ( .A(add_subt_module_Add_Subt_result[22]), .B(
add_subt_module_Add_Subt_result[23]), .Y(n2441) );
NOR2X1TS U1829 ( .A(n3047), .B(add_subt_module_FSM_selector_D), .Y(n2381) );
OAI21X4TS U1830 ( .A0(n2463), .A1(n2459), .B0(n2460), .Y(n2436) );
NOR3X4TS U1831 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_result[6]), .C(n2248), .Y(n2271) );
NAND2BX2TS U1832 ( .AN(add_subt_module_Add_Subt_result[12]), .B(n1662), .Y(
n2451) );
AOI21X2TS U1833 ( .A0(n1614), .A1(n1564), .B0(n1599), .Y(n1611) );
AOI2BB2XLTS U1834 ( .B0(add_subt_module_intDX[3]), .B1(n2977), .A0N(
add_subt_module_intDY[2]), .A1N(n2108), .Y(n2109) );
OAI21XLTS U1835 ( .A0(add_subt_module_intDX[3]), .A1(n2977), .B0(
add_subt_module_intDX[2]), .Y(n2108) );
INVX2TS U1836 ( .A(n1612), .Y(n1599) );
OAI21X2TS U1837 ( .A0(n1615), .A1(n1595), .B0(n1594), .Y(n1614) );
NAND2X1TS U1838 ( .A(n1566), .B(n1565), .Y(n1595) );
AOI21X1TS U1839 ( .A0(n1565), .A1(n1616), .B0(n1593), .Y(n1594) );
INVX2TS U1840 ( .A(n1617), .Y(n1593) );
OAI21X2TS U1841 ( .A0(n1611), .A1(n1607), .B0(n1608), .Y(n1638) );
AO22XLTS U1842 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[12]), .B0(
add_subt_module_DmP[11]), .B1(n1902), .Y(n1859) );
AO22XLTS U1843 ( .A0(n1545), .A1(add_subt_module_Add_Subt_result[15]), .B0(
add_subt_module_DmP[8]), .B1(n1902), .Y(n1903) );
AO22XLTS U1844 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[13]), .B0(
add_subt_module_DmP[10]), .B1(n1902), .Y(n1871) );
AO22XLTS U1845 ( .A0(n1545), .A1(add_subt_module_Add_Subt_result[9]), .B0(
add_subt_module_DmP[14]), .B1(n1902), .Y(n1863) );
AO22XLTS U1846 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[4]), .B0(
add_subt_module_DmP[19]), .B1(n3002), .Y(n1867) );
NOR3X1TS U1847 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1953), .C(
add_subt_module_add_overflow_flag), .Y(n1669) );
NAND2X2TS U1848 ( .A(n1947), .B(add_subt_module_FSM_selector_C), .Y(n1891)
);
NAND2X1TS U1849 ( .A(n1632), .B(n1631), .Y(n1634) );
XNOR2X2TS U1850 ( .A(n1627), .B(n1626), .Y(n2618) );
NAND2X1TS U1851 ( .A(n1625), .B(n1624), .Y(n1626) );
OAI21X1TS U1852 ( .A0(n1633), .A1(n1630), .B0(n1631), .Y(n1627) );
BUFX3TS U1853 ( .A(n2907), .Y(n2860) );
NOR2XLTS U1854 ( .A(n2152), .B(add_subt_module_intDY[24]), .Y(n2093) );
NAND2BXLTS U1855 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n2119) );
OAI32X1TS U1856 ( .A0(n2114), .A1(n2113), .A2(n2112), .B0(n2111), .B1(n2113),
.Y(n2132) );
XOR2X1TS U1857 ( .A(n1639), .B(n1575), .Y(n1581) );
AO22XLTS U1858 ( .A0(n1852), .A1(add_subt_module_DmP[24]), .B0(n1574), .B1(
add_subt_module_LZA_output[1]), .Y(n1575) );
XOR2X1TS U1859 ( .A(n1639), .B(n1576), .Y(n1583) );
AO22XLTS U1860 ( .A0(n1852), .A1(add_subt_module_DmP[25]), .B0(n1574), .B1(
add_subt_module_LZA_output[2]), .Y(n1576) );
XOR2X1TS U1861 ( .A(n1639), .B(n1588), .Y(n1592) );
AO22XLTS U1862 ( .A0(n1852), .A1(add_subt_module_DmP[27]), .B0(n1574), .B1(
add_subt_module_LZA_output[4]), .Y(n1588) );
XOR2X1TS U1863 ( .A(n1639), .B(n1587), .Y(n1590) );
AO22XLTS U1864 ( .A0(n1852), .A1(add_subt_module_DmP[26]), .B0(n1574), .B1(
add_subt_module_LZA_output[3]), .Y(n1587) );
NOR2X1TS U1865 ( .A(n2589), .B(n2591), .Y(n2339) );
MX2X1TS U1866 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n2317), .Y(n2324) );
MX2X1TS U1867 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n2317), .Y(n2322) );
MX2X1TS U1868 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n2317), .Y(n2332) );
NOR2XLTS U1869 ( .A(n2982), .B(add_subt_module_FSM_selector_D), .Y(n2319) );
MX2X1TS U1870 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n2373), .Y(n2336) );
MX2X1TS U1871 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n2373), .Y(n2334) );
MX2X1TS U1872 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n2317), .Y(n2300) );
MX2X1TS U1873 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n2317), .Y(n2304) );
NOR2X1TS U1874 ( .A(n2325), .B(n2324), .Y(n2565) );
MX2X1TS U1875 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n2317), .Y(n2326) );
INVX2TS U1876 ( .A(n1615), .Y(n1622) );
XOR2X1TS U1877 ( .A(n2368), .B(n2315), .Y(n2331) );
MX2X1TS U1878 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n2317), .Y(n2330) );
NOR2X1TS U1879 ( .A(n2331), .B(n2330), .Y(n2597) );
NOR2X1TS U1880 ( .A(n2637), .B(n1734), .Y(n1736) );
AO22XLTS U1881 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[16]), .B0(
add_subt_module_DmP[7]), .B1(n3002), .Y(n1900) );
NOR2X1TS U1882 ( .A(n2479), .B(n2497), .Y(n2511) );
MX2X1TS U1883 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n2317), .Y(n2302) );
MX2X1TS U1884 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n2317), .Y(n2320) );
MX2X1TS U1885 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n2382), .Y(n2290) );
MX2X1TS U1886 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n2373), .Y(n2358) );
NOR2XLTS U1887 ( .A(n3009), .B(n2385), .Y(n2344) );
MX2X1TS U1888 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n2373), .Y(n2346) );
NOR2XLTS U1889 ( .A(n3008), .B(n2385), .Y(n2345) );
MX2X1TS U1890 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n2373), .Y(n2348) );
MX2X1TS U1891 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n2317), .Y(n2298) );
NOR2XLTS U1892 ( .A(n3007), .B(add_subt_module_FSM_selector_D), .Y(n2353) );
MX2X1TS U1893 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n2373), .Y(n2354) );
AOI32X1TS U1894 ( .A0(n2157), .A1(n2156), .A2(n2155), .B0(n2154), .B1(n2157),
.Y(n2158) );
AO22XLTS U1895 ( .A0(n1545), .A1(add_subt_module_Add_Subt_result[17]), .B0(
add_subt_module_DmP[6]), .B1(n1902), .Y(n1898) );
NAND3XLTS U1896 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.C(n1767), .Y(n1841) );
OR2X1TS U1897 ( .A(n2379), .B(n2378), .Y(n2474) );
INVX2TS U1898 ( .A(n2572), .Y(n2574) );
MX2X1TS U1899 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_exp_oper_result[0]), .S0(n2382), .Y(n1629) );
XOR2X1TS U1900 ( .A(n1639), .B(n1579), .Y(n1628) );
AO21XLTS U1901 ( .A0(add_subt_module_DmP[23]), .A1(n2980), .B0(n1854), .Y(
n1579) );
XNOR2X2TS U1902 ( .A(n1622), .B(n1621), .Y(n2619) );
NAND2X1TS U1903 ( .A(n1566), .B(n1620), .Y(n1621) );
CLKXOR2X2TS U1904 ( .A(n1619), .B(n1618), .Y(n2620) );
NAND2X1TS U1905 ( .A(n1565), .B(n1617), .Y(n1618) );
AOI21X1TS U1906 ( .A0(n1622), .A1(n1566), .B0(n1616), .Y(n1619) );
CLKXOR2X2TS U1907 ( .A(n1611), .B(n1610), .Y(n2623) );
INVX2TS U1908 ( .A(n1607), .Y(n1609) );
XNOR2X2TS U1909 ( .A(n1614), .B(n1613), .Y(n2621) );
NAND2X1TS U1910 ( .A(n1564), .B(n1612), .Y(n1613) );
XNOR2X2TS U1911 ( .A(n1638), .B(n1606), .Y(n2626) );
XOR2X1TS U1912 ( .A(n1641), .B(n1640), .Y(n2629) );
AOI21X1TS U1913 ( .A0(n1638), .A1(n1568), .B0(n1637), .Y(n1641) );
INVX2TS U1914 ( .A(n1636), .Y(n1637) );
CLKAND2X2TS U1915 ( .A(n1674), .B(n1776), .Y(n2089) );
NAND2X1TS U1916 ( .A(n2331), .B(n2330), .Y(n2606) );
NOR2X4TS U1917 ( .A(n2013), .B(n1545), .Y(n2017) );
INVX2TS U1918 ( .A(n2017), .Y(n1977) );
CLKAND2X2TS U1919 ( .A(n2386), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(n2284) );
INVX2TS U1920 ( .A(n2457), .Y(n2466) );
CLKAND2X2TS U1921 ( .A(n1950), .B(n1949), .Y(n2635) );
CLKAND2X2TS U1922 ( .A(n2386), .B(add_subt_module_Sgf_normalized_result[0]),
.Y(n2281) );
NAND3BXLTS U1923 ( .AN(ack_cordic), .B(n2961), .C(n2641), .Y(n2650) );
OR2X1TS U1924 ( .A(n2349), .B(n2348), .Y(n2556) );
OR2X1TS U1925 ( .A(n2362), .B(n2361), .Y(n2526) );
NAND3X2TS U1926 ( .A(cont_iter_out[1]), .B(n3071), .C(n1848), .Y(n2735) );
OR2X1TS U1927 ( .A(n2370), .B(n2369), .Y(n2489) );
OR2X1TS U1928 ( .A(n2355), .B(n2354), .Y(n2541) );
NAND2BXLTS U1929 ( .AN(r_mode[0]), .B(add_subt_module_sign_final_result),
.Y(n1688) );
AOI2BB2XLTS U1930 ( .B0(r_mode[1]), .B1(r_mode[0]), .A0N(
add_subt_module_Sgf_normalized_result[0]), .A1N(
add_subt_module_Sgf_normalized_result[1]), .Y(n1689) );
NAND2BXLTS U1931 ( .AN(add_subt_module_Add_Subt_result[1]), .B(
add_subt_module_Add_Subt_result[0]), .Y(n1654) );
AO22XLTS U1932 ( .A0(n2748), .A1(result_add_subt[15]), .B0(n2746), .B1(
d_ff_Xn[15]), .Y(n1238) );
AO22XLTS U1933 ( .A0(n2748), .A1(result_add_subt[18]), .B0(n2746), .B1(
d_ff_Xn[18]), .Y(n1250) );
AO22XLTS U1934 ( .A0(n2742), .A1(result_add_subt[30]), .B0(n2738), .B1(
d_ff_Xn[30]), .Y(n1298) );
AO22XLTS U1935 ( .A0(n2748), .A1(result_add_subt[14]), .B0(n2746), .B1(
d_ff_Xn[14]), .Y(n1234) );
AO22XLTS U1936 ( .A0(n2755), .A1(result_add_subt[10]), .B0(n2751), .B1(
d_ff_Xn[10]), .Y(n1218) );
AO22XLTS U1937 ( .A0(n2748), .A1(result_add_subt[16]), .B0(n2746), .B1(
d_ff_Xn[16]), .Y(n1242) );
AO22XLTS U1938 ( .A0(n2748), .A1(result_add_subt[17]), .B0(n2746), .B1(
d_ff_Xn[17]), .Y(n1246) );
AO22XLTS U1939 ( .A0(n2748), .A1(result_add_subt[13]), .B0(n2751), .B1(
d_ff_Xn[13]), .Y(n1230) );
AO22XLTS U1940 ( .A0(n2755), .A1(result_add_subt[2]), .B0(n2758), .B1(
d_ff_Xn[2]), .Y(n1186) );
AO22XLTS U1941 ( .A0(n2742), .A1(result_add_subt[27]), .B0(n2738), .B1(
d_ff_Xn[27]), .Y(n1286) );
OAI211XLTS U1942 ( .A0(n2641), .A1(n1846), .B0(n1845), .C0(n1844), .Y(
cordic_FSM_state_next_1_) );
AOI32X1TS U1943 ( .A0(n2639), .A1(n1555), .A2(n2634), .B0(n1968), .B1(n1554),
.Y(n1963) );
OAI211XLTS U1944 ( .A0(n2860), .A1(n3072), .B0(n1783), .C0(n1785), .Y(n1011)
);
OAI211XLTS U1945 ( .A0(n2860), .A1(n2960), .B0(n1786), .C0(n1785), .Y(n1009)
);
AOI221XLTS U1946 ( .A0(cont_var_out[1]), .A1(n1793), .B0(n2972), .B1(n1792),
.C0(n2723), .Y(n1506) );
OAI211XLTS U1947 ( .A0(n2860), .A1(n2984), .B0(n1784), .C0(n1785), .Y(n1010)
);
NAND2BXLTS U1948 ( .AN(add_subt_module_intDX[2]), .B(
add_subt_module_intDY[2]), .Y(n2106) );
NAND2BXLTS U1949 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n2121) );
NAND3XLTS U1950 ( .A(n3000), .B(n2119), .C(add_subt_module_intDX[8]), .Y(
n2120) );
NOR2X1TS U1951 ( .A(n2565), .B(n2572), .Y(n2329) );
MX2X1TS U1952 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_exp_oper_result[1]), .S0(n2382), .Y(n1580) );
MX2X1TS U1953 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_exp_oper_result[2]), .S0(n2382), .Y(n1582) );
MX2X1TS U1954 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_exp_oper_result[4]), .S0(n2382), .Y(n1591) );
MX2X1TS U1955 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_exp_oper_result[3]), .S0(n2382), .Y(n1589) );
XOR2X1TS U1956 ( .A(n1639), .B(n1600), .Y(n1602) );
CLKAND2X2TS U1957 ( .A(n1852), .B(add_subt_module_DmP[29]), .Y(n1600) );
MX2X1TS U1958 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_exp_oper_result[6]), .S0(n2382), .Y(n1601) );
AOI21X2TS U1959 ( .A0(n1586), .A1(n1585), .B0(n1584), .Y(n1615) );
OAI21X1TS U1960 ( .A0(n1623), .A1(n1631), .B0(n1624), .Y(n1584) );
NOR2X1TS U1961 ( .A(n1630), .B(n1623), .Y(n1586) );
XOR2X1TS U1962 ( .A(n1639), .B(n1596), .Y(n1598) );
CLKAND2X2TS U1963 ( .A(n1573), .B(add_subt_module_DmP[28]), .Y(n1596) );
MX2X1TS U1964 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_exp_oper_result[5]), .S0(n2382), .Y(n1597) );
XOR2X1TS U1965 ( .A(n1639), .B(n1603), .Y(n1605) );
CLKAND2X2TS U1966 ( .A(n1852), .B(add_subt_module_DmP[30]), .Y(n1603) );
MX2X1TS U1967 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_exp_oper_result[7]), .S0(n2382), .Y(n1604) );
OAI21XLTS U1968 ( .A0(n2591), .A1(n2601), .B0(n2592), .Y(n2338) );
NAND3BX1TS U1969 ( .AN(n2138), .B(n2136), .C(n2135), .Y(n2156) );
MX2X1TS U1970 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n2373), .Y(n2365) );
MX2X1TS U1971 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n2377), .Y(n2378) );
AO22XLTS U1972 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[8]), .B0(
add_subt_module_DmP[15]), .B1(n3002), .Y(n1860) );
NOR2X1TS U1973 ( .A(n2597), .B(n2610), .Y(n2585) );
MX2X1TS U1974 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n2373), .Y(n2374) );
NOR2X1TS U1975 ( .A(n2546), .B(n2547), .Y(n2561) );
NOR2X2TS U1976 ( .A(n1583), .B(n1582), .Y(n1623) );
NOR2X2TS U1977 ( .A(n1581), .B(n1580), .Y(n1630) );
NAND2X1TS U1978 ( .A(n1583), .B(n1582), .Y(n1624) );
NAND2X1TS U1979 ( .A(n1590), .B(n1589), .Y(n1620) );
NAND2X1TS U1980 ( .A(n1592), .B(n1591), .Y(n1617) );
INVX2TS U1981 ( .A(n1620), .Y(n1616) );
OR2X2TS U1982 ( .A(n1592), .B(n1591), .Y(n1565) );
OR2X2TS U1983 ( .A(n1590), .B(n1589), .Y(n1566) );
NAND2X1TS U1984 ( .A(n1602), .B(n1601), .Y(n1608) );
NAND2X1TS U1985 ( .A(n1598), .B(n1597), .Y(n1612) );
OR2X1TS U1986 ( .A(n1598), .B(n1597), .Y(n1564) );
NAND2X1TS U1987 ( .A(n1605), .B(n1604), .Y(n1636) );
OR2X1TS U1988 ( .A(n1605), .B(n1604), .Y(n1568) );
MX2X1TS U1989 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n2382), .Y(n2383) );
MX2X1TS U1990 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n2373), .Y(n2361) );
MX2X1TS U1991 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n2373), .Y(n2369) );
AND2X2TS U1992 ( .A(n1760), .B(n1759), .Y(n2907) );
AO22XLTS U1993 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[19]), .B0(
add_subt_module_DmP[4]), .B1(n3002), .Y(n1882) );
AO22XLTS U1994 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[20]), .B0(
add_subt_module_DmP[3]), .B1(n3002), .Y(n1879) );
AOI31XLTS U1995 ( .A0(n2981), .A1(n2958), .A2(n2444), .B0(n2443), .Y(n2446)
);
NAND3XLTS U1996 ( .A(n3045), .B(n2973), .C(
add_subt_module_Add_Subt_result[15]), .Y(n2444) );
INVX2TS U1997 ( .A(n2442), .Y(n2443) );
BUFX3TS U1998 ( .A(n2734), .Y(n2757) );
INVX2TS U1999 ( .A(n1534), .Y(n1535) );
NAND3XLTS U2000 ( .A(n2735), .B(cont_var_out[0]), .C(n1790), .Y(n1792) );
NAND2BXLTS U2001 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n2385),
.Y(n2435) );
CLKINVX3TS U2002 ( .A(rst), .Y(n1756) );
AO22XLTS U2003 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[21]), .B0(
add_subt_module_DmP[2]), .B1(n3002), .Y(n1885) );
BUFX3TS U2004 ( .A(n2739), .Y(n2752) );
AND2X2TS U2005 ( .A(n1772), .B(sel_mux_1_reg), .Y(n2768) );
NOR2XLTS U2006 ( .A(n1657), .B(add_subt_module_Add_Subt_result[25]), .Y(
n1658) );
AOI2BB1XLTS U2007 ( .A0N(n1656), .A1N(add_subt_module_Add_Subt_result[23]),
.B0(add_subt_module_Add_Subt_result[24]), .Y(n1657) );
NOR2XLTS U2008 ( .A(n2698), .B(n2687), .Y(n2688) );
MX2X1TS U2009 ( .A(n2626), .B(add_subt_module_exp_oper_result[7]), .S0(n2456), .Y(n1360) );
MX2X1TS U2010 ( .A(n2621), .B(add_subt_module_exp_oper_result[5]), .S0(n2456), .Y(n1366) );
MX2X1TS U2011 ( .A(n2623), .B(add_subt_module_exp_oper_result[6]), .S0(n2456), .Y(n1367) );
AO22XLTS U2012 ( .A0(d_ff_Xn[30]), .A1(n2772), .B0(d_ff2_X[30]), .B1(n2728),
.Y(n1434) );
OAI211XLTS U2013 ( .A0(n1842), .A1(n3022), .B0(n2650), .C0(n1841), .Y(n1521)
);
AO22X1TS U2014 ( .A0(n2276), .A1(n2454), .B0(add_subt_module_LZA_output[2]),
.B1(n2453), .Y(n1329) );
NAND4XLTS U2015 ( .A(n2275), .B(n2274), .C(n2273), .D(n2272), .Y(n2276) );
NOR2XLTS U2016 ( .A(n2269), .B(n2268), .Y(n2274) );
AO22XLTS U2017 ( .A0(d_ff_Xn[9]), .A1(n2775), .B0(d_ff2_X[9]), .B1(n2774),
.Y(n1392) );
AO22XLTS U2018 ( .A0(d_ff_Xn[4]), .A1(n2732), .B0(d_ff2_X[4]), .B1(n2774),
.Y(n1382) );
AO22XLTS U2019 ( .A0(d_ff_Xn[8]), .A1(n2775), .B0(d_ff2_X[8]), .B1(n2774),
.Y(n1390) );
AO22XLTS U2020 ( .A0(d_ff_Xn[31]), .A1(n2775), .B0(d_ff2_X[31]), .B1(n2728),
.Y(n1512) );
AO22XLTS U2021 ( .A0(d_ff_Xn[0]), .A1(n2732), .B0(d_ff2_X[0]), .B1(n2774),
.Y(n1374) );
AO22XLTS U2022 ( .A0(n2755), .A1(result_add_subt[11]), .B0(n2751), .B1(
d_ff_Xn[11]), .Y(n1222) );
AO22XLTS U2023 ( .A0(n2748), .A1(result_add_subt[21]), .B0(n2746), .B1(
d_ff_Xn[21]), .Y(n1262) );
AO22XLTS U2024 ( .A0(n2742), .A1(result_add_subt[22]), .B0(n2746), .B1(
d_ff_Xn[22]), .Y(n1266) );
AO22XLTS U2025 ( .A0(n2742), .A1(result_add_subt[23]), .B0(n2746), .B1(
d_ff_Xn[23]), .Y(n1270) );
AO22XLTS U2026 ( .A0(n2742), .A1(result_add_subt[31]), .B0(n2758), .B1(
d_ff_Xn[31]), .Y(n1513) );
AO22XLTS U2027 ( .A0(n2748), .A1(result_add_subt[12]), .B0(n2751), .B1(
d_ff_Xn[12]), .Y(n1226) );
AO22XLTS U2028 ( .A0(n2748), .A1(result_add_subt[20]), .B0(n2746), .B1(
d_ff_Xn[20]), .Y(n1258) );
AO22XLTS U2029 ( .A0(n2748), .A1(result_add_subt[19]), .B0(n2746), .B1(
d_ff_Xn[19]), .Y(n1254) );
AO22XLTS U2030 ( .A0(n2742), .A1(result_add_subt[28]), .B0(n2738), .B1(
d_ff_Xn[28]), .Y(n1290) );
AO22XLTS U2031 ( .A0(n2742), .A1(result_add_subt[29]), .B0(n2738), .B1(
d_ff_Xn[29]), .Y(n1294) );
AO22X1TS U2032 ( .A0(n1649), .A1(n2454), .B0(n2453), .B1(
add_subt_module_LZA_output[3]), .Y(n1328) );
AO22XLTS U2033 ( .A0(result_add_subt[9]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[11]), .B1(n2265), .Y(n1217) );
AO22XLTS U2034 ( .A0(result_add_subt[7]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[9]), .B1(n2265), .Y(n3037) );
AO22XLTS U2035 ( .A0(result_add_subt[4]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[6]), .B1(n2265), .Y(n3038) );
AO22XLTS U2036 ( .A0(result_add_subt[5]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[7]), .B1(n2265), .Y(n3039) );
AO22XLTS U2037 ( .A0(result_add_subt[1]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[3]), .B1(n2265), .Y(n3040) );
AO22XLTS U2038 ( .A0(result_add_subt[8]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[10]), .B1(n2265), .Y(n1213) );
AO22XLTS U2039 ( .A0(result_add_subt[3]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[5]), .B1(n2265), .Y(n3042) );
AO22XLTS U2040 ( .A0(result_add_subt[6]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[8]), .B1(n2265), .Y(n3043) );
AO22XLTS U2041 ( .A0(result_add_subt[0]), .A1(n2740), .B0(
add_subt_module_Sgf_normalized_result[2]), .B1(n2265), .Y(n3044) );
MX2X1TS U2042 ( .A(add_subt_module_Add_Subt_result[20]), .B(n2509), .S0(
n2559), .Y(n1353) );
MX2X1TS U2043 ( .A(add_subt_module_Add_Subt_result[23]), .B(n2477), .S0(
n2492), .Y(n1356) );
OAI21XLTS U2044 ( .A0(n2986), .A1(n2202), .B0(n2198), .Y(n952) );
OAI21XLTS U2045 ( .A0(n2990), .A1(n2202), .B0(n2196), .Y(n935) );
OAI21XLTS U2046 ( .A0(n2964), .A1(n2202), .B0(n2195), .Y(n914) );
OAI21XLTS U2047 ( .A0(n2963), .A1(n2202), .B0(n2199), .Y(n892) );
MX2X1TS U2048 ( .A(add_subt_module_Add_Subt_result[9]), .B(n2567), .S0(n2502), .Y(n1342) );
AO21XLTS U2049 ( .A0(n1986), .A1(n1670), .B0(n1679), .Y(n1518) );
OAI211XLTS U2050 ( .A0(n2398), .A1(n3059), .B0(n1678), .C0(n1682), .Y(n1679)
);
AO22XLTS U2051 ( .A0(n2455), .A1(n2454), .B0(n2453), .B1(
add_subt_module_LZA_output[1]), .Y(n1330) );
INVX2TS U2052 ( .A(n2441), .Y(n2447) );
AO22XLTS U2053 ( .A0(d_ff_Xn[22]), .A1(n2772), .B0(d_ff2_X[22]), .B1(n2728),
.Y(n1418) );
AO22XLTS U2054 ( .A0(d_ff_Xn[21]), .A1(n2772), .B0(d_ff2_X[21]), .B1(n2774),
.Y(n1416) );
AO22XLTS U2055 ( .A0(d_ff_Xn[18]), .A1(n2772), .B0(d_ff2_X[18]), .B1(n2774),
.Y(n1410) );
AO22XLTS U2056 ( .A0(d_ff_Xn[15]), .A1(n2772), .B0(d_ff2_X[15]), .B1(n2774),
.Y(n1404) );
AO22XLTS U2057 ( .A0(d_ff_Xn[11]), .A1(n2775), .B0(d_ff2_X[11]), .B1(n2774),
.Y(n1396) );
AO22XLTS U2058 ( .A0(n2803), .A1(result_add_subt[0]), .B0(n2738), .B1(
d_ff_Xn[0]), .Y(n1081) );
AO22XLTS U2059 ( .A0(n2755), .A1(result_add_subt[8]), .B0(n2751), .B1(
d_ff_Xn[8]), .Y(n1210) );
AO22XLTS U2060 ( .A0(n2755), .A1(result_add_subt[4]), .B0(n2758), .B1(
d_ff_Xn[4]), .Y(n1194) );
AO22XLTS U2061 ( .A0(n2755), .A1(result_add_subt[9]), .B0(n2751), .B1(
d_ff_Xn[9]), .Y(n1214) );
AO22XLTS U2062 ( .A0(n2742), .A1(result_add_subt[26]), .B0(n2738), .B1(
d_ff_Xn[26]), .Y(n1282) );
AO22XLTS U2063 ( .A0(n2742), .A1(result_add_subt[25]), .B0(n2738), .B1(
d_ff_Xn[25]), .Y(n1278) );
AO22XLTS U2064 ( .A0(n2742), .A1(result_add_subt[24]), .B0(n2738), .B1(
d_ff_Xn[24]), .Y(n1274) );
AO22XLTS U2065 ( .A0(n2755), .A1(result_add_subt[6]), .B0(n2758), .B1(
d_ff_Xn[6]), .Y(n1202) );
AO22XLTS U2066 ( .A0(n2755), .A1(result_add_subt[3]), .B0(n2758), .B1(
d_ff_Xn[3]), .Y(n1190) );
AO22XLTS U2067 ( .A0(n2803), .A1(result_add_subt[1]), .B0(n2758), .B1(
d_ff_Xn[1]), .Y(n1182) );
AO22XLTS U2068 ( .A0(n2755), .A1(result_add_subt[5]), .B0(n2758), .B1(
d_ff_Xn[5]), .Y(n1198) );
AO22XLTS U2069 ( .A0(n2755), .A1(result_add_subt[7]), .B0(n2751), .B1(
d_ff_Xn[7]), .Y(n1206) );
OAI211XLTS U2070 ( .A0(n2257), .A1(n1781), .B0(n2259), .C0(n1780), .Y(n1509)
);
AOI211XLTS U2071 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n2262),
.B0(n2091), .C0(n1779), .Y(n1780) );
OAI211XLTS U2072 ( .A0(n1778), .A1(n1777), .B0(n2241), .C0(n2948), .Y(n1779)
);
NAND2BXLTS U2073 ( .AN(n2264), .B(n2263), .Y(n1508) );
AOI211XLTS U2074 ( .A0(n2262), .A1(add_subt_module_FS_Module_state_reg[2]),
.B0(n2261), .C0(n2260), .Y(n2263) );
AO22XLTS U2075 ( .A0(d_ff_Yn[30]), .A1(n2775), .B0(n2774), .B1(d_ff2_Y[30]),
.Y(n1092) );
NAND3XLTS U2076 ( .A(n1796), .B(sel_mux_3_reg), .C(n3140), .Y(n1795) );
NAND3XLTS U2077 ( .A(cordic_FSM_state_reg[3]), .B(n1794), .C(n2971), .Y(
n1796) );
NAND4XLTS U2078 ( .A(n1790), .B(n3071), .C(n2736), .D(n3143), .Y(n1651) );
OAI2BB2XLTS U2079 ( .B0(n3047), .B1(n1543), .A0N(result_add_subt[22]), .A1N(
n2740), .Y(n1269) );
OAI2BB2XLTS U2080 ( .B0(n2982), .B1(n1544), .A0N(result_add_subt[12]), .A1N(
n2749), .Y(n1229) );
AO22XLTS U2081 ( .A0(result_add_subt[2]), .A1(n1534), .B0(
add_subt_module_Sgf_normalized_result[4]), .B1(n2265), .Y(n3041) );
AO21XLTS U2082 ( .A0(add_subt_module_Sgf_normalized_result[5]), .A1(n2403),
.B0(n2022), .Y(n1983) );
AO21XLTS U2083 ( .A0(add_subt_module_Sgf_normalized_result[3]), .A1(n2403),
.B0(n2022), .Y(n2023) );
AO21XLTS U2084 ( .A0(add_subt_module_Sgf_normalized_result[7]), .A1(n2013),
.B0(n2022), .Y(n1980) );
AO21XLTS U2085 ( .A0(add_subt_module_Sgf_normalized_result[6]), .A1(n2403),
.B0(n2022), .Y(n1976) );
AOI211XLTS U2086 ( .A0(n1550), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(
n2422), .C0(n1745), .Y(n1746) );
AO22XLTS U2087 ( .A0(n2429), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
add_subt_module_Sgf_normalized_result[10]), .B1(n2013), .Y(n1745) );
AOI211XLTS U2088 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(
n2422), .C0(n1749), .Y(n1750) );
AO22XLTS U2089 ( .A0(n1748), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
add_subt_module_Sgf_normalized_result[11]), .B1(n2013), .Y(n1749) );
AO21XLTS U2090 ( .A0(add_subt_module_Sgf_normalized_result[2]), .A1(n2403),
.B0(n2022), .Y(n1995) );
MX2X1TS U2091 ( .A(n2618), .B(add_subt_module_exp_oper_result[2]), .S0(n2456), .Y(n1363) );
MX2X1TS U2092 ( .A(n2616), .B(add_subt_module_exp_oper_result[1]), .S0(n2456), .Y(n1362) );
AO22XLTS U2093 ( .A0(d_ff_Xn[23]), .A1(n2772), .B0(d_ff2_X[23]), .B1(n2728),
.Y(n1427) );
OAI21XLTS U2094 ( .A0(n2184), .A1(n2183), .B0(n2182), .Y(n1001) );
MX2X1TS U2095 ( .A(n2620), .B(add_subt_module_exp_oper_result[4]), .S0(n2456), .Y(n1365) );
MX2X1TS U2096 ( .A(n2619), .B(add_subt_module_exp_oper_result[3]), .S0(n2456), .Y(n1364) );
MX2X1TS U2097 ( .A(n2617), .B(add_subt_module_exp_oper_result[0]), .S0(n2456), .Y(n1361) );
AO22XLTS U2098 ( .A0(d_ff_Yn[27]), .A1(n2772), .B0(n2771), .B1(d_ff2_Y[27]),
.Y(n1095) );
MX2X1TS U2099 ( .A(add_subt_module_Add_Subt_result[8]), .B(n2552), .S0(n2559), .Y(n1341) );
OAI21XLTS U2100 ( .A0(n2584), .A1(n2546), .B0(n2545), .Y(n2551) );
MX2X1TS U2101 ( .A(add_subt_module_Add_Subt_result[15]), .B(n2581), .S0(
n2502), .Y(n1348) );
MX2X1TS U2102 ( .A(add_subt_module_Add_Subt_result[12]), .B(n2615), .S0(
n2502), .Y(n1345) );
MX2X1TS U2103 ( .A(add_subt_module_Add_Subt_result[14]), .B(n2596), .S0(
n2502), .Y(n1347) );
MX2X1TS U2104 ( .A(add_subt_module_Add_Subt_result[13]), .B(n2605), .S0(
n2502), .Y(n1346) );
MX2X1TS U2105 ( .A(add_subt_module_Add_Subt_result[4]), .B(n2503), .S0(n2559), .Y(n1337) );
MX2X1TS U2106 ( .A(add_subt_module_Add_Subt_result[22]), .B(n2487), .S0(
n2492), .Y(n1355) );
MX2X1TS U2107 ( .A(add_subt_module_Add_Subt_result[1]), .B(n2458), .S0(n2492), .Y(n1334) );
MX2X1TS U2108 ( .A(add_subt_module_Add_Subt_result[6]), .B(n2524), .S0(n2559), .Y(n1339) );
OAI21XLTS U2109 ( .A0(n2518), .A1(n2517), .B0(n2516), .Y(n2523) );
MX2X1TS U2110 ( .A(add_subt_module_Add_Subt_result[10]), .B(n2577), .S0(
n2502), .Y(n1343) );
MX2X1TS U2111 ( .A(n2279), .B(add_subt_module_intAS), .S0(n2943), .Y(n1002)
);
OAI211XLTS U2112 ( .A0(n2398), .A1(n3053), .B0(n2001), .C0(n2000), .Y(n1316)
);
OAI21XLTS U2113 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n2087),
.B0(n2086), .Y(n2088) );
OAI21XLTS U2114 ( .A0(n2181), .A1(n2280), .B0(n2085), .Y(n2086) );
MXI2X1TS U2115 ( .A(n1643), .B(n3068), .S0(n2456), .Y(n1359) );
AND4X1TS U2116 ( .A(n2623), .B(n2621), .C(n2620), .D(n1635), .Y(n1642) );
AO21XLTS U2117 ( .A0(n2090), .A1(n1781), .B0(n2264), .Y(n1726) );
AO21XLTS U2118 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n2421), .B0(n2406), .Y(n1324) );
OAI211XLTS U2119 ( .A0(n2419), .A1(n3053), .B0(n2405), .C0(n2404), .Y(n2406)
);
AO21XLTS U2120 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n2421), .B0(n2402), .Y(n1325) );
OAI211XLTS U2121 ( .A0(n2419), .A1(n3054), .B0(n2401), .C0(n2400), .Y(n2402)
);
AO21XLTS U2122 ( .A0(n2421), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(
n2409), .Y(n1323) );
OAI211XLTS U2123 ( .A0(n2419), .A1(n3058), .B0(n2408), .C0(n2407), .Y(n2409)
);
AO21XLTS U2124 ( .A0(n2421), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(
n2415), .Y(n1321) );
AO21XLTS U2125 ( .A0(n2421), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(
n2412), .Y(n1322) );
AO21XLTS U2126 ( .A0(n2421), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(
n2420), .Y(n1320) );
MX2X1TS U2127 ( .A(add_subt_module_Add_Subt_result[11]), .B(n2600), .S0(
n2502), .Y(n1344) );
NAND4XLTS U2128 ( .A(n2433), .B(n2432), .C(n2431), .D(n2430), .Y(n1318) );
NAND4XLTS U2129 ( .A(n2433), .B(n2426), .C(n2425), .D(n2424), .Y(n1319) );
OAI211XLTS U2130 ( .A0(n2398), .A1(n3054), .B0(n2004), .C0(n2003), .Y(n1317)
);
OAI211XLTS U2131 ( .A0(n2021), .A1(n2020), .B0(n2019), .C0(n2018), .Y(n1315)
);
AO21XLTS U2132 ( .A0(n2016), .A1(n1670), .B0(n1739), .Y(n1314) );
AO21XLTS U2133 ( .A0(n1989), .A1(n1670), .B0(n1684), .Y(n1326) );
OAI211XLTS U2134 ( .A0(n2398), .A1(n3060), .B0(n1683), .C0(n1682), .Y(n1684)
);
OAI211XLTS U2135 ( .A0(n1917), .A1(n2070), .B0(n1909), .C0(n1908), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NOR2XLTS U2136 ( .A(n2636), .B(n1555), .Y(n2631) );
AOI222X1TS U2137 ( .A0(n2632), .A1(n1560), .B0(n2635), .B1(n1548), .C0(n2633), .C1(n1552), .Y(n2630) );
MX2X1TS U2138 ( .A(add_subt_module_Add_Subt_result[5]), .B(n2515), .S0(n2559), .Y(n1338) );
MX2X1TS U2139 ( .A(add_subt_module_Add_Subt_result[7]), .B(n2539), .S0(n2559), .Y(n1340) );
MX2X1TS U2140 ( .A(add_subt_module_Add_Subt_result[2]), .B(n2472), .S0(n2492), .Y(n1335) );
NOR2XLTS U2141 ( .A(n2636), .B(n1858), .Y(n2393) );
MX2X1TS U2142 ( .A(add_subt_module_Add_Subt_result[0]), .B(n2283), .S0(n2492), .Y(n1333) );
OAI21XLTS U2143 ( .A0(n2087), .A1(n1778), .B0(n1902), .Y(n1358) );
NAND4XLTS U2144 ( .A(n2651), .B(n2659), .C(n2650), .D(n2649), .Y(n1519) );
AO21XLTS U2145 ( .A0(add_subt_module_Sgf_normalized_result[4]), .A1(n2403),
.B0(n2022), .Y(n1992) );
MX2X1TS U2146 ( .A(add_subt_module_add_overflow_flag), .B(n2439), .S0(n2492),
.Y(n1517) );
AOI21X1TS U2147 ( .A0(n2436), .A1(n2435), .B0(n2434), .Y(n2438) );
MX2X1TS U2148 ( .A(add_subt_module_Add_Subt_result[24]), .B(n2464), .S0(
n2492), .Y(n1357) );
AO22XLTS U2149 ( .A0(n2804), .A1(sign_inv_out[0]), .B0(n2808), .B1(
data_output[0]), .Y(n1079) );
AO22XLTS U2150 ( .A0(n2810), .A1(sign_inv_out[22]), .B0(n2809), .B1(
data_output[22]), .Y(n1035) );
AO22XLTS U2151 ( .A0(n2804), .A1(sign_inv_out[6]), .B0(n2805), .B1(
data_output[6]), .Y(n1067) );
AO22XLTS U2152 ( .A0(n2804), .A1(sign_inv_out[3]), .B0(n2805), .B1(
data_output[3]), .Y(n1073) );
AO22XLTS U2153 ( .A0(n2804), .A1(sign_inv_out[2]), .B0(n2805), .B1(
data_output[2]), .Y(n1075) );
AO22XLTS U2154 ( .A0(n2810), .A1(sign_inv_out[21]), .B0(n2809), .B1(
data_output[21]), .Y(n1037) );
AO22XLTS U2155 ( .A0(n2807), .A1(sign_inv_out[15]), .B0(n2808), .B1(
data_output[15]), .Y(n1049) );
AO22XLTS U2156 ( .A0(n2804), .A1(sign_inv_out[8]), .B0(n2806), .B1(
data_output[8]), .Y(n1063) );
AO22XLTS U2157 ( .A0(n2804), .A1(sign_inv_out[1]), .B0(n2805), .B1(
data_output[1]), .Y(n1077) );
AO22XLTS U2158 ( .A0(n2804), .A1(sign_inv_out[5]), .B0(n2805), .B1(
data_output[5]), .Y(n1069) );
AO22XLTS U2159 ( .A0(n2804), .A1(sign_inv_out[4]), .B0(n2805), .B1(
data_output[4]), .Y(n1071) );
AO22XLTS U2160 ( .A0(n2807), .A1(sign_inv_out[10]), .B0(n2806), .B1(
data_output[10]), .Y(n1059) );
AO22XLTS U2161 ( .A0(n2804), .A1(sign_inv_out[7]), .B0(n2805), .B1(
data_output[7]), .Y(n1065) );
AO22XLTS U2162 ( .A0(n2807), .A1(sign_inv_out[11]), .B0(n2806), .B1(
data_output[11]), .Y(n1057) );
AO22XLTS U2163 ( .A0(n2804), .A1(sign_inv_out[9]), .B0(n2806), .B1(
data_output[9]), .Y(n1061) );
AO22XLTS U2164 ( .A0(n2807), .A1(sign_inv_out[12]), .B0(n2805), .B1(
data_output[12]), .Y(n1055) );
AO22XLTS U2165 ( .A0(n2807), .A1(sign_inv_out[14]), .B0(n2805), .B1(
data_output[14]), .Y(n1051) );
AO22XLTS U2166 ( .A0(n2807), .A1(sign_inv_out[16]), .B0(n2811), .B1(
data_output[16]), .Y(n1047) );
AO22XLTS U2167 ( .A0(n2807), .A1(sign_inv_out[17]), .B0(n2808), .B1(
data_output[17]), .Y(n1045) );
AO22XLTS U2168 ( .A0(n2807), .A1(sign_inv_out[13]), .B0(n2811), .B1(
data_output[13]), .Y(n1053) );
AO22XLTS U2169 ( .A0(n2810), .A1(sign_inv_out[20]), .B0(n2809), .B1(
data_output[20]), .Y(n1039) );
AO22XLTS U2170 ( .A0(n2807), .A1(sign_inv_out[18]), .B0(n2809), .B1(
data_output[18]), .Y(n1043) );
AO22XLTS U2171 ( .A0(n2807), .A1(sign_inv_out[19]), .B0(n2809), .B1(
data_output[19]), .Y(n1041) );
AO22XLTS U2172 ( .A0(n2810), .A1(sign_inv_out[23]), .B0(n2809), .B1(
data_output[23]), .Y(n1033) );
AO22XLTS U2173 ( .A0(n2810), .A1(sign_inv_out[24]), .B0(n2809), .B1(
data_output[24]), .Y(n1031) );
AO22XLTS U2174 ( .A0(n2810), .A1(sign_inv_out[25]), .B0(n2809), .B1(
data_output[25]), .Y(n1029) );
AO22XLTS U2175 ( .A0(n2810), .A1(sign_inv_out[26]), .B0(n2809), .B1(
data_output[26]), .Y(n1027) );
AO22XLTS U2176 ( .A0(n2810), .A1(sign_inv_out[27]), .B0(n2809), .B1(
data_output[27]), .Y(n1025) );
AO22XLTS U2177 ( .A0(n2810), .A1(sign_inv_out[28]), .B0(n2811), .B1(
data_output[28]), .Y(n1023) );
AO22XLTS U2178 ( .A0(n2810), .A1(sign_inv_out[29]), .B0(n2811), .B1(
data_output[29]), .Y(n1021) );
AO22XLTS U2179 ( .A0(n2812), .A1(sign_inv_out[30]), .B0(n2811), .B1(
data_output[30]), .Y(n1019) );
AO22XLTS U2180 ( .A0(n2812), .A1(n1771), .B0(n2811), .B1(data_output[31]),
.Y(n1016) );
XOR2XLTS U2181 ( .A(data_output2_31_), .B(n1770), .Y(n1771) );
MX2X1TS U2182 ( .A(add_subt_module_Add_Subt_result[18]), .B(n2535), .S0(
n2559), .Y(n1351) );
MX2X1TS U2183 ( .A(add_subt_module_Add_Subt_result[16]), .B(n2560), .S0(
n2559), .Y(n1349) );
MX2X1TS U2184 ( .A(add_subt_module_Add_Subt_result[19]), .B(n2529), .S0(
n2559), .Y(n1352) );
MX2X1TS U2185 ( .A(add_subt_module_Add_Subt_result[3]), .B(n2481), .S0(n2492), .Y(n1336) );
NOR3XLTS U2186 ( .A(n2792), .B(n1793), .C(n1791), .Y(n1507) );
MX2X1TS U2187 ( .A(add_subt_module_Add_Subt_result[21]), .B(n2493), .S0(
n2492), .Y(n1354) );
MX2X1TS U2188 ( .A(add_subt_module_Add_Subt_result[25]), .B(n2391), .S0(
n2492), .Y(n1332) );
MX2X1TS U2189 ( .A(add_subt_module_Add_Subt_result[17]), .B(n2544), .S0(
n2559), .Y(n1350) );
OAI21XLTS U2190 ( .A0(n2969), .A1(n1540), .B0(n2219), .Y(n911) );
OAI21XLTS U2191 ( .A0(n2964), .A1(n1540), .B0(n2161), .Y(n915) );
OAI21XLTS U2192 ( .A0(n3005), .A1(n1540), .B0(n2216), .Y(n918) );
OAI21XLTS U2193 ( .A0(n3035), .A1(n2222), .B0(n2217), .Y(n922) );
OAI21XLTS U2194 ( .A0(n3011), .A1(n2222), .B0(n2223), .Y(n925) );
OAI21XLTS U2195 ( .A0(n3004), .A1(n2208), .B0(n2191), .Y(n984) );
OAI21XLTS U2196 ( .A0(n3016), .A1(n2208), .B0(n2190), .Y(n987) );
OAI21XLTS U2197 ( .A0(n2984), .A1(n2208), .B0(n2188), .Y(n993) );
OAI21XLTS U2198 ( .A0(n1781), .A1(n2257), .B0(n3001), .Y(n1368) );
AO22XLTS U2199 ( .A0(n2765), .A1(d_ff2_Y[0]), .B0(n2763), .B1(
d_ff3_sh_y_out[0]), .Y(n1144) );
OAI21XLTS U2200 ( .A0(n3146), .A1(n1825), .B0(n1818), .Y(n1076) );
OAI21XLTS U2201 ( .A0(n3159), .A1(n1832), .B0(n1806), .Y(n1050) );
OAI21XLTS U2202 ( .A0(n3154), .A1(n1832), .B0(n1817), .Y(n1060) );
AO22XLTS U2203 ( .A0(n2731), .A1(d_ff2_X[9]), .B0(n2798), .B1(
d_ff3_sh_x_out[9]), .Y(n1391) );
AO22XLTS U2204 ( .A0(n2765), .A1(d_ff2_Y[9]), .B0(n2766), .B1(
d_ff3_sh_y_out[9]), .Y(n1126) );
AO22XLTS U2205 ( .A0(n2753), .A1(result_add_subt[9]), .B0(n2759), .B1(
d_ff_Zn[9]), .Y(n1216) );
AO22XLTS U2206 ( .A0(n2731), .A1(d_ff2_X[12]), .B0(n2798), .B1(
d_ff3_sh_x_out[12]), .Y(n1397) );
AO22XLTS U2207 ( .A0(n2769), .A1(d_ff2_Y[12]), .B0(n2766), .B1(
d_ff3_sh_y_out[12]), .Y(n1120) );
AO22XLTS U2208 ( .A0(n2747), .A1(result_add_subt[12]), .B0(n2756), .B1(
d_ff_Zn[12]), .Y(n1228) );
AO22XLTS U2209 ( .A0(n2731), .A1(d_ff2_X[11]), .B0(n2798), .B1(
d_ff3_sh_x_out[11]), .Y(n1395) );
AO22XLTS U2210 ( .A0(n2769), .A1(d_ff2_Y[11]), .B0(n2766), .B1(
d_ff3_sh_y_out[11]), .Y(n1122) );
AO22XLTS U2211 ( .A0(n2753), .A1(result_add_subt[11]), .B0(n2756), .B1(
d_ff_Zn[11]), .Y(n1224) );
AO22XLTS U2212 ( .A0(n2800), .A1(d_ff2_X[7]), .B0(n2798), .B1(
d_ff3_sh_x_out[7]), .Y(n1387) );
AO22XLTS U2213 ( .A0(n2765), .A1(d_ff2_Y[7]), .B0(n2766), .B1(
d_ff3_sh_y_out[7]), .Y(n1130) );
AO22XLTS U2214 ( .A0(n2753), .A1(result_add_subt[7]), .B0(n2759), .B1(
d_ff_Zn[7]), .Y(n1208) );
OAI21XLTS U2215 ( .A0(n3158), .A1(n1832), .B0(n1821), .Y(n1052) );
AO22XLTS U2216 ( .A0(n2731), .A1(d_ff2_X[14]), .B0(n2798), .B1(
d_ff3_sh_x_out[14]), .Y(n1401) );
AO22XLTS U2217 ( .A0(n2769), .A1(d_ff2_Y[14]), .B0(n2790), .B1(
d_ff3_sh_y_out[14]), .Y(n1116) );
AO22XLTS U2218 ( .A0(n2747), .A1(result_add_subt[14]), .B0(n2744), .B1(
d_ff_Zn[14]), .Y(n1236) );
AO22XLTS U2219 ( .A0(n2731), .A1(d_ff2_X[10]), .B0(n2798), .B1(
d_ff3_sh_x_out[10]), .Y(n1393) );
AO22XLTS U2220 ( .A0(n2769), .A1(d_ff2_Y[10]), .B0(n2766), .B1(
d_ff3_sh_y_out[10]), .Y(n1124) );
AO22XLTS U2221 ( .A0(n2753), .A1(result_add_subt[10]), .B0(n2759), .B1(
d_ff_Zn[10]), .Y(n1220) );
OAI21XLTS U2222 ( .A0(n3160), .A1(n1832), .B0(n1831), .Y(n1048) );
AO22XLTS U2223 ( .A0(n2731), .A1(d_ff2_X[16]), .B0(n2730), .B1(
d_ff3_sh_x_out[16]), .Y(n1405) );
AO22XLTS U2224 ( .A0(n2769), .A1(d_ff2_Y[16]), .B0(n2790), .B1(
d_ff3_sh_y_out[16]), .Y(n1112) );
AO22XLTS U2225 ( .A0(n2747), .A1(result_add_subt[16]), .B0(n2752), .B1(
d_ff_Zn[16]), .Y(n1244) );
AO22XLTS U2226 ( .A0(n2800), .A1(d_ff2_X[4]), .B0(n2763), .B1(
d_ff3_sh_x_out[4]), .Y(n1381) );
AO22XLTS U2227 ( .A0(n2765), .A1(d_ff2_Y[4]), .B0(n2766), .B1(
d_ff3_sh_y_out[4]), .Y(n1136) );
AO22XLTS U2228 ( .A0(n2753), .A1(result_add_subt[4]), .B0(n2756), .B1(
d_ff_Zn[4]), .Y(n1196) );
OAI21XLTS U2229 ( .A0(n3161), .A1(n1832), .B0(n1813), .Y(n1046) );
AO22XLTS U2230 ( .A0(n2731), .A1(d_ff2_X[17]), .B0(n2730), .B1(
d_ff3_sh_x_out[17]), .Y(n1407) );
AO22XLTS U2231 ( .A0(n2769), .A1(d_ff2_Y[17]), .B0(n2790), .B1(
d_ff3_sh_y_out[17]), .Y(n1110) );
AO22XLTS U2232 ( .A0(n2747), .A1(result_add_subt[17]), .B0(n2752), .B1(
d_ff_Zn[17]), .Y(n1248) );
AO22XLTS U2233 ( .A0(n2800), .A1(d_ff2_X[5]), .B0(n2763), .B1(
d_ff3_sh_x_out[5]), .Y(n1383) );
AO22XLTS U2234 ( .A0(n2765), .A1(d_ff2_Y[5]), .B0(n2766), .B1(
d_ff3_sh_y_out[5]), .Y(n1134) );
AO22XLTS U2235 ( .A0(n2753), .A1(result_add_subt[5]), .B0(n2759), .B1(
d_ff_Zn[5]), .Y(n1200) );
OAI21XLTS U2236 ( .A0(n3157), .A1(n1832), .B0(n1814), .Y(n1054) );
AO22XLTS U2237 ( .A0(n2731), .A1(d_ff2_X[13]), .B0(n2798), .B1(
d_ff3_sh_x_out[13]), .Y(n1399) );
AO22XLTS U2238 ( .A0(n2769), .A1(d_ff2_Y[13]), .B0(n2714), .B1(
d_ff3_sh_y_out[13]), .Y(n1118) );
AO22XLTS U2239 ( .A0(n2747), .A1(result_add_subt[13]), .B0(n2756), .B1(
d_ff_Zn[13]), .Y(n1232) );
AO22XLTS U2240 ( .A0(n2729), .A1(d_ff2_X[20]), .B0(n2730), .B1(
d_ff3_sh_x_out[20]), .Y(n1413) );
AO22XLTS U2241 ( .A0(n2792), .A1(d_ff2_Y[20]), .B0(n2784), .B1(
d_ff3_sh_y_out[20]), .Y(n1104) );
AO22XLTS U2242 ( .A0(n2747), .A1(result_add_subt[20]), .B0(n2752), .B1(
d_ff_Zn[20]), .Y(n1260) );
AO22XLTS U2243 ( .A0(n2800), .A1(d_ff2_X[1]), .B0(n2763), .B1(
d_ff3_sh_x_out[1]), .Y(n1375) );
AO22XLTS U2244 ( .A0(n2765), .A1(d_ff2_Y[1]), .B0(n2763), .B1(
d_ff3_sh_y_out[1]), .Y(n1142) );
AO22XLTS U2245 ( .A0(n2760), .A1(result_add_subt[1]), .B0(n2759), .B1(
d_ff_Zn[1]), .Y(n1184) );
AO22XLTS U2246 ( .A0(n2731), .A1(d_ff2_X[8]), .B0(n2798), .B1(
d_ff3_sh_x_out[8]), .Y(n1389) );
AO22XLTS U2247 ( .A0(n2765), .A1(d_ff2_Y[8]), .B0(n2766), .B1(
d_ff3_sh_y_out[8]), .Y(n1128) );
AO22XLTS U2248 ( .A0(n2753), .A1(result_add_subt[8]), .B0(n2759), .B1(
d_ff_Zn[8]), .Y(n1212) );
AO22XLTS U2249 ( .A0(n2731), .A1(d_ff2_X[15]), .B0(n2730), .B1(
d_ff3_sh_x_out[15]), .Y(n1403) );
AO22XLTS U2250 ( .A0(n2769), .A1(d_ff2_Y[15]), .B0(n2790), .B1(
d_ff3_sh_y_out[15]), .Y(n1114) );
AO22XLTS U2251 ( .A0(n2747), .A1(result_add_subt[15]), .B0(n2744), .B1(
d_ff_Zn[15]), .Y(n1240) );
OAI21XLTS U2252 ( .A0(n3162), .A1(n1832), .B0(n1803), .Y(n1044) );
AO22XLTS U2253 ( .A0(n2729), .A1(d_ff2_X[18]), .B0(n2730), .B1(
d_ff3_sh_x_out[18]), .Y(n1409) );
AO22XLTS U2254 ( .A0(n2769), .A1(d_ff2_Y[18]), .B0(n2780), .B1(
d_ff3_sh_y_out[18]), .Y(n1108) );
AO22XLTS U2255 ( .A0(n2747), .A1(result_add_subt[18]), .B0(n2752), .B1(
d_ff_Zn[18]), .Y(n1252) );
AO22XLTS U2256 ( .A0(n2729), .A1(d_ff2_X[21]), .B0(n2730), .B1(
d_ff3_sh_x_out[21]), .Y(n1415) );
AO22XLTS U2257 ( .A0(n2792), .A1(d_ff2_Y[21]), .B0(n2780), .B1(
d_ff3_sh_y_out[21]), .Y(n1102) );
AO22XLTS U2258 ( .A0(n2747), .A1(result_add_subt[21]), .B0(n2752), .B1(
d_ff_Zn[21]), .Y(n1264) );
AO22XLTS U2259 ( .A0(n2800), .A1(d_ff2_X[2]), .B0(n2763), .B1(
d_ff3_sh_x_out[2]), .Y(n1377) );
AO22XLTS U2260 ( .A0(n2765), .A1(d_ff2_Y[2]), .B0(n2763), .B1(
d_ff3_sh_y_out[2]), .Y(n1140) );
AO22XLTS U2261 ( .A0(n2753), .A1(result_add_subt[2]), .B0(n2759), .B1(
d_ff_Zn[2]), .Y(n1188) );
AO22XLTS U2262 ( .A0(n2729), .A1(d_ff2_X[19]), .B0(n2730), .B1(
d_ff3_sh_x_out[19]), .Y(n1411) );
AO22XLTS U2263 ( .A0(n2769), .A1(d_ff2_Y[19]), .B0(n2780), .B1(
d_ff3_sh_y_out[19]), .Y(n1106) );
AO22XLTS U2264 ( .A0(n2747), .A1(result_add_subt[19]), .B0(n2752), .B1(
d_ff_Zn[19]), .Y(n1256) );
AO22XLTS U2265 ( .A0(n2800), .A1(d_ff2_X[3]), .B0(n2763), .B1(
d_ff3_sh_x_out[3]), .Y(n1379) );
AO22XLTS U2266 ( .A0(n2765), .A1(d_ff2_Y[3]), .B0(n2766), .B1(
d_ff3_sh_y_out[3]), .Y(n1138) );
AO22XLTS U2267 ( .A0(n2753), .A1(result_add_subt[3]), .B0(n2759), .B1(
d_ff_Zn[3]), .Y(n1192) );
AO22XLTS U2268 ( .A0(n2800), .A1(d_ff2_X[6]), .B0(n2798), .B1(
d_ff3_sh_x_out[6]), .Y(n1385) );
AO22XLTS U2269 ( .A0(n2765), .A1(d_ff2_Y[6]), .B0(n2766), .B1(
d_ff3_sh_y_out[6]), .Y(n1132) );
AO22XLTS U2270 ( .A0(n2753), .A1(result_add_subt[6]), .B0(n2752), .B1(
d_ff_Zn[6]), .Y(n1204) );
AO22XLTS U2271 ( .A0(n2729), .A1(d_ff2_X[22]), .B0(n2730), .B1(
d_ff3_sh_x_out[22]), .Y(n1417) );
AO22XLTS U2272 ( .A0(n2723), .A1(d_ff2_Y[22]), .B0(n2780), .B1(
d_ff3_sh_y_out[22]), .Y(n1100) );
AO22XLTS U2273 ( .A0(n2741), .A1(result_add_subt[22]), .B0(n2752), .B1(
d_ff_Zn[22]), .Y(n1268) );
AO22XLTS U2274 ( .A0(n2760), .A1(result_add_subt[0]), .B0(n2759), .B1(
d_ff_Zn[0]), .Y(n1180) );
AO22XLTS U2275 ( .A0(n2741), .A1(result_add_subt[23]), .B0(n2739), .B1(
d_ff_Zn[23]), .Y(n1272) );
AO22XLTS U2276 ( .A0(n2741), .A1(result_add_subt[24]), .B0(n2744), .B1(
d_ff_Zn[24]), .Y(n1276) );
AO22XLTS U2277 ( .A0(n2741), .A1(result_add_subt[25]), .B0(n2744), .B1(
d_ff_Zn[25]), .Y(n1280) );
AO22XLTS U2278 ( .A0(n2741), .A1(result_add_subt[26]), .B0(n2744), .B1(
d_ff_Zn[26]), .Y(n1284) );
OAI21XLTS U2279 ( .A0(n3061), .A1(n1838), .B0(n1798), .Y(n1026) );
AO22XLTS U2280 ( .A0(n2741), .A1(result_add_subt[27]), .B0(n2744), .B1(
d_ff_Zn[27]), .Y(n1288) );
AO22XLTS U2281 ( .A0(n2741), .A1(result_add_subt[28]), .B0(n2744), .B1(
d_ff_Zn[28]), .Y(n1292) );
AO22XLTS U2282 ( .A0(n2741), .A1(result_add_subt[29]), .B0(n2744), .B1(
d_ff_Zn[29]), .Y(n1296) );
OAI21XLTS U2283 ( .A0(n3062), .A1(n1799), .B0(n1788), .Y(n1020) );
AO22XLTS U2284 ( .A0(n2741), .A1(result_add_subt[30]), .B0(n2744), .B1(
d_ff_Zn[30]), .Y(n1300) );
AO22XLTS U2285 ( .A0(n2800), .A1(d_ff2_Z[31]), .B0(n2763), .B1(
d_ff3_sign_out), .Y(n1147) );
AO22XLTS U2286 ( .A0(n2741), .A1(result_add_subt[31]), .B0(n2756), .B1(
d_ff_Zn[31]), .Y(n1370) );
AO22XLTS U2287 ( .A0(n2723), .A1(d_ff2_Y[31]), .B0(n2710), .B1(
d_ff3_sh_y_out[31]), .Y(n1082) );
AO22XLTS U2288 ( .A0(n2454), .A1(n1666), .B0(n2453), .B1(
add_subt_module_LZA_output[0]), .Y(n1331) );
NAND4XLTS U2289 ( .A(n2275), .B(n1665), .C(n1664), .D(n1663), .Y(n1666) );
AOI31XLTS U2290 ( .A0(n1659), .A1(add_subt_module_Add_Subt_result[16]), .A2(
n3045), .B0(n1658), .Y(n1665) );
NAND4BXLTS U2291 ( .AN(add_subt_module_Add_Subt_result[9]), .B(n1662), .C(
add_subt_module_Add_Subt_result[8]), .D(n2452), .Y(n1663) );
AO22XLTS U2292 ( .A0(n2800), .A1(d_ff2_X[0]), .B0(n2763), .B1(
d_ff3_sh_x_out[0]), .Y(n1373) );
AO22XLTS U2293 ( .A0(n2729), .A1(n2715), .B0(n2714), .B1(d_ff3_sh_x_out[24]),
.Y(n1425) );
AO22XLTS U2294 ( .A0(n2729), .A1(n1769), .B0(n2714), .B1(d_ff3_sh_x_out[25]),
.Y(n1424) );
AO22XLTS U2295 ( .A0(n2729), .A1(n2717), .B0(n2730), .B1(d_ff3_sh_x_out[26]),
.Y(n1423) );
AOI2BB2XLTS U2296 ( .B0(n2792), .B1(n2720), .A0N(d_ff3_sh_x_out[27]), .A1N(
n2794), .Y(n1422) );
AOI2BB2XLTS U2297 ( .B0(n2792), .B1(n2725), .A0N(d_ff3_sh_x_out[29]), .A1N(
n2794), .Y(n1420) );
AO22XLTS U2298 ( .A0(n2729), .A1(n2727), .B0(n2730), .B1(d_ff3_sh_x_out[30]),
.Y(n1419) );
AO22XLTS U2299 ( .A0(n2723), .A1(n2777), .B0(n2780), .B1(d_ff3_sh_y_out[24]),
.Y(n1090) );
AO22XLTS U2300 ( .A0(n2792), .A1(n2781), .B0(n2780), .B1(d_ff3_sh_y_out[25]),
.Y(n1089) );
AO22XLTS U2301 ( .A0(n2723), .A1(n2785), .B0(n2784), .B1(d_ff3_sh_y_out[26]),
.Y(n1088) );
AOI2BB2XLTS U2302 ( .B0(n2723), .B1(n2787), .A0N(d_ff3_sh_y_out[27]), .A1N(
n2794), .Y(n1087) );
AO22XLTS U2303 ( .A0(n2792), .A1(n2791), .B0(n2790), .B1(d_ff3_sh_y_out[28]),
.Y(n1086) );
AOI2BB2XLTS U2304 ( .B0(n2723), .B1(n2795), .A0N(d_ff3_sh_y_out[29]), .A1N(
n2794), .Y(n1085) );
AO22XLTS U2305 ( .A0(n2800), .A1(n2799), .B0(n2798), .B1(d_ff3_sh_y_out[30]),
.Y(n1084) );
NOR2XLTS U2306 ( .A(n3143), .B(n2705), .Y(n2707) );
AO21XLTS U2307 ( .A0(d_ff3_LUT_out[1]), .A1(n2704), .B0(n2703), .Y(n1437) );
AO21XLTS U2308 ( .A0(d_ff3_LUT_out[3]), .A1(n2704), .B0(n1839), .Y(n1439) );
AOI32X1TS U2309 ( .A0(n2692), .A1(n2796), .A2(n2701), .B0(n3063), .B1(n2710),
.Y(n1442) );
AOI31XLTS U2310 ( .A0(n3071), .A1(cont_iter_out[3]), .A2(n2691), .B0(n2696),
.Y(n2692) );
AO21XLTS U2311 ( .A0(d_ff3_LUT_out[7]), .A1(n2704), .B0(n2686), .Y(n1443) );
AO21XLTS U2312 ( .A0(d_ff3_LUT_out[11]), .A1(n2704), .B0(n2686), .Y(n1447)
);
AO22XLTS U2313 ( .A0(n2729), .A1(n2682), .B0(n2714), .B1(d_ff3_LUT_out[12]),
.Y(n1448) );
AO21XLTS U2314 ( .A0(d_ff3_LUT_out[13]), .A1(n2704), .B0(n2683), .Y(n1449)
);
AO21XLTS U2315 ( .A0(d_ff3_LUT_out[16]), .A1(n2694), .B0(n1839), .Y(n1452)
);
AO21XLTS U2316 ( .A0(d_ff3_LUT_out[18]), .A1(n2694), .B0(n2683), .Y(n1454)
);
OAI21XLTS U2317 ( .A0(n1562), .A1(n2679), .B0(n1849), .Y(n1459) );
AO22XLTS U2318 ( .A0(n2794), .A1(n2678), .B0(n2790), .B1(d_ff3_LUT_out[24]),
.Y(n1460) );
AOI2BB2XLTS U2319 ( .B0(n2674), .B1(n2680), .A0N(n2723), .A1N(
d_ff3_LUT_out[26]), .Y(n1462) );
OR2X1TS U2320 ( .A(d_ff3_LUT_out[27]), .B(n2794), .Y(n1463) );
AO22XLTS U2321 ( .A0(n2670), .A1(data_in[31]), .B0(n2669), .B1(d_ff1_Z[31]),
.Y(n1467) );
AO22XLTS U2322 ( .A0(n2668), .A1(data_in[0]), .B0(n2667), .B1(d_ff1_Z[0]),
.Y(n1468) );
AO22XLTS U2323 ( .A0(n2668), .A1(data_in[1]), .B0(n2667), .B1(d_ff1_Z[1]),
.Y(n1469) );
AO22XLTS U2324 ( .A0(n2668), .A1(data_in[2]), .B0(n2667), .B1(d_ff1_Z[2]),
.Y(n1470) );
AO22XLTS U2325 ( .A0(n2668), .A1(data_in[3]), .B0(n2666), .B1(d_ff1_Z[3]),
.Y(n1471) );
AO22XLTS U2326 ( .A0(n2668), .A1(data_in[4]), .B0(n2666), .B1(d_ff1_Z[4]),
.Y(n1472) );
AO22XLTS U2327 ( .A0(n2668), .A1(data_in[5]), .B0(n2667), .B1(d_ff1_Z[5]),
.Y(n1473) );
AO22XLTS U2328 ( .A0(n2665), .A1(data_in[6]), .B0(n2667), .B1(d_ff1_Z[6]),
.Y(n1474) );
AO22XLTS U2329 ( .A0(n2665), .A1(data_in[7]), .B0(n2664), .B1(d_ff1_Z[7]),
.Y(n1475) );
AO22XLTS U2330 ( .A0(n2665), .A1(data_in[8]), .B0(n2664), .B1(d_ff1_Z[8]),
.Y(n1476) );
AO22XLTS U2331 ( .A0(n2665), .A1(data_in[9]), .B0(n2663), .B1(d_ff1_Z[9]),
.Y(n1477) );
AO22XLTS U2332 ( .A0(n2665), .A1(data_in[10]), .B0(n2663), .B1(d_ff1_Z[10]),
.Y(n1478) );
AO22XLTS U2333 ( .A0(n2665), .A1(data_in[11]), .B0(n2663), .B1(d_ff1_Z[11]),
.Y(n1479) );
AO22XLTS U2334 ( .A0(n2665), .A1(data_in[12]), .B0(n2663), .B1(d_ff1_Z[12]),
.Y(n1480) );
AO22XLTS U2335 ( .A0(n2665), .A1(data_in[13]), .B0(n2669), .B1(d_ff1_Z[13]),
.Y(n1481) );
AO22XLTS U2336 ( .A0(n2665), .A1(data_in[14]), .B0(n2669), .B1(d_ff1_Z[14]),
.Y(n1482) );
AO22XLTS U2337 ( .A0(n2665), .A1(data_in[15]), .B0(n2669), .B1(d_ff1_Z[15]),
.Y(n1483) );
AO22XLTS U2338 ( .A0(n2670), .A1(data_in[16]), .B0(n2669), .B1(d_ff1_Z[16]),
.Y(n1484) );
AO22XLTS U2339 ( .A0(n2670), .A1(data_in[17]), .B0(n2669), .B1(d_ff1_Z[17]),
.Y(n1485) );
AO22XLTS U2340 ( .A0(n2670), .A1(data_in[18]), .B0(n2669), .B1(d_ff1_Z[18]),
.Y(n1486) );
AO22XLTS U2341 ( .A0(n2670), .A1(data_in[19]), .B0(n2669), .B1(d_ff1_Z[19]),
.Y(n1487) );
AO22XLTS U2342 ( .A0(n2670), .A1(data_in[20]), .B0(n2669), .B1(d_ff1_Z[20]),
.Y(n1488) );
AO22XLTS U2343 ( .A0(n2670), .A1(data_in[21]), .B0(n2669), .B1(d_ff1_Z[21]),
.Y(n1489) );
AO22XLTS U2344 ( .A0(n2670), .A1(data_in[22]), .B0(n2664), .B1(d_ff1_Z[22]),
.Y(n1490) );
AO22XLTS U2345 ( .A0(n2670), .A1(data_in[23]), .B0(n2664), .B1(d_ff1_Z[23]),
.Y(n1491) );
AO22XLTS U2346 ( .A0(n2670), .A1(data_in[24]), .B0(n2664), .B1(d_ff1_Z[24]),
.Y(n1492) );
AO22XLTS U2347 ( .A0(n2662), .A1(data_in[25]), .B0(n2664), .B1(d_ff1_Z[25]),
.Y(n1493) );
AO22XLTS U2348 ( .A0(n2662), .A1(data_in[26]), .B0(n2664), .B1(d_ff1_Z[26]),
.Y(n1494) );
AO22XLTS U2349 ( .A0(n2662), .A1(data_in[27]), .B0(n2664), .B1(d_ff1_Z[27]),
.Y(n1495) );
AO22XLTS U2350 ( .A0(n2662), .A1(data_in[28]), .B0(n2664), .B1(d_ff1_Z[28]),
.Y(n1496) );
AO22XLTS U2351 ( .A0(n2662), .A1(data_in[29]), .B0(n2664), .B1(d_ff1_Z[29]),
.Y(n1497) );
AO22XLTS U2352 ( .A0(n2662), .A1(data_in[30]), .B0(n2663), .B1(d_ff1_Z[30]),
.Y(n1498) );
INVX2TS U2353 ( .A(n1947), .Y(n1954) );
NAND2X4TS U2354 ( .A(n1776), .B(n1669), .Y(n1947) );
NOR2X4TS U2355 ( .A(n2013), .B(n1947), .Y(n1670) );
NOR3X2TS U2356 ( .A(underflow_flag), .B(n2749), .C(overflow_flag), .Y(n1532)
);
AND2X4TS U2357 ( .A(n2158), .B(n2085), .Y(n2166) );
BUFX3TS U2358 ( .A(n2166), .Y(n2229) );
INVX2TS U2359 ( .A(n1687), .Y(n1534) );
OAI22X2TS U2360 ( .A0(n2249), .A1(n2248), .B0(n2247), .B1(n2246), .Y(n2445)
);
NOR3BX2TS U2361 ( .AN(n1648), .B(n1647), .C(
add_subt_module_Add_Subt_result[14]), .Y(n1645) );
INVX2TS U2362 ( .A(cont_iter_out[3]), .Y(n1536) );
INVX2TS U2363 ( .A(n1531), .Y(n1537) );
INVX2TS U2364 ( .A(n1531), .Y(n1538) );
INVX2TS U2365 ( .A(n2222), .Y(n1539) );
INVX2TS U2366 ( .A(n1539), .Y(n1541) );
INVX2TS U2367 ( .A(n1532), .Y(n1542) );
INVX2TS U2368 ( .A(n1532), .Y(n1543) );
INVX2TS U2369 ( .A(n1532), .Y(n1544) );
INVX2TS U2370 ( .A(n1947), .Y(n1545) );
INVX2TS U2371 ( .A(n1947), .Y(n1546) );
OAI21XLTS U2372 ( .A0(n3171), .A1(n1838), .B0(n1834), .Y(n1024) );
NOR3X6TS U2373 ( .A(n2948), .B(sel_mux_2_reg[1]), .C(sel_mux_2_reg[0]), .Y(
n2901) );
NOR3X6TS U2374 ( .A(n2948), .B(sel_mux_2_reg[1]), .C(n3046), .Y(n2949) );
AOI22X2TS U2375 ( .A0(n2392), .A1(n1878), .B0(n1897), .B1(n1970), .Y(n1938)
);
AOI22X2TS U2376 ( .A0(n2392), .A1(n1920), .B0(n1901), .B1(n1904), .Y(n1931)
);
AOI22X2TS U2377 ( .A0(n2392), .A1(n1921), .B0(n1920), .B1(n1970), .Y(n1940)
);
AOI22X2TS U2378 ( .A0(n2392), .A1(n1918), .B0(n1899), .B1(n1904), .Y(n1930)
);
AOI22X2TS U2379 ( .A0(n2392), .A1(n1919), .B0(n1918), .B1(n1970), .Y(n1939)
);
INVX2TS U2380 ( .A(n2070), .Y(n1547) );
OAI211XLTS U2381 ( .A0(n1944), .A1(n2070), .B0(n1929), .C0(n1928), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI21XLTS U2382 ( .A0(n3173), .A1(n1799), .B0(n1789), .Y(n1018) );
OAI21XLTS U2383 ( .A0(n2244), .A1(n2992), .B0(n2239), .Y(n889) );
OAI21XLTS U2384 ( .A0(n2244), .A1(n3011), .B0(n2231), .Y(n896) );
OAI21XLTS U2385 ( .A0(n2244), .A1(n3005), .B0(n2232), .Y(n897) );
OAI21XLTS U2386 ( .A0(n2244), .A1(n2969), .B0(n2234), .Y(n898) );
OAI21XLTS U2387 ( .A0(n2244), .A1(n2968), .B0(n2243), .Y(n900) );
OAI21XLTS U2388 ( .A0(n2989), .A1(n2202), .B0(n2194), .Y(n962) );
INVX2TS U2389 ( .A(n1672), .Y(n1549) );
INVX2TS U2390 ( .A(n1672), .Y(n1550) );
INVX2TS U2391 ( .A(n1672), .Y(n1551) );
OAI32X1TS U2392 ( .A0(cordic_FSM_state_reg[2]), .A1(n2648), .A2(n2647), .B0(
n2654), .B1(n2953), .Y(n2649) );
NOR3X1TS U2393 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.C(beg_fsm_cordic), .Y(n2647) );
NOR2X2TS U2394 ( .A(d_ff2_Y[23]), .B(n1562), .Y(n2779) );
OR2X1TS U2395 ( .A(n2089), .B(n2627), .Y(n1677) );
OAI22X2TS U2396 ( .A0(n1676), .A1(n1953), .B0(n1675), .B1(n3036), .Y(n2627)
);
BUFX3TS U2397 ( .A(n2764), .Y(n2709) );
BUFX3TS U2398 ( .A(n1772), .Y(n2764) );
CLKINVX3TS U2399 ( .A(n2860), .Y(n2943) );
CLKINVX3TS U2400 ( .A(n2907), .Y(n2929) );
CLKINVX3TS U2401 ( .A(n2907), .Y(n2834) );
CLKINVX3TS U2402 ( .A(n2907), .Y(n2857) );
CLKINVX3TS U2403 ( .A(n2907), .Y(n2904) );
NOR2X4TS U2404 ( .A(n1977), .B(n2012), .Y(n2024) );
NAND2X2TS U2405 ( .A(n1975), .B(n1671), .Y(n2012) );
CLKINVX3TS U2406 ( .A(n1858), .Y(n1552) );
AO22X2TS U2407 ( .A0(add_subt_module_LZA_output[2]), .A1(n1574), .B0(
add_subt_module_exp_oper_result[2]), .B1(n1852), .Y(n1877) );
AOI22X2TS U2408 ( .A0(n1962), .A1(n1872), .B0(n1957), .B1(n1904), .Y(n2074)
);
AOI22X2TS U2409 ( .A0(n1962), .A1(n1899), .B0(n1872), .B1(n1904), .Y(n1913)
);
AOI22X2TS U2410 ( .A0(n1962), .A1(n1901), .B0(n1868), .B1(n1904), .Y(n1914)
);
AOI22X2TS U2411 ( .A0(n1962), .A1(n1868), .B0(n1952), .B1(n1904), .Y(n2075)
);
AOI22X2TS U2412 ( .A0(n1962), .A1(n1905), .B0(n2067), .B1(n1904), .Y(n1893)
);
OAI21XLTS U2413 ( .A0(n3164), .A1(n1838), .B0(n1811), .Y(n1040) );
OAI21XLTS U2414 ( .A0(n3165), .A1(n1838), .B0(n1802), .Y(n1038) );
OAI21XLTS U2415 ( .A0(n3163), .A1(n1832), .B0(n1819), .Y(n1042) );
OAI21XLTS U2416 ( .A0(n3169), .A1(n1838), .B0(n1826), .Y(n1030) );
OAI21XLTS U2417 ( .A0(n3170), .A1(n1838), .B0(n1828), .Y(n1028) );
AOI22X4TS U2418 ( .A0(add_subt_module_LZA_output[3]), .A1(n1574), .B0(n1852),
.B1(add_subt_module_exp_oper_result[3]), .Y(n1975) );
INVX2TS U2419 ( .A(n1533), .Y(n1554) );
INVX2TS U2420 ( .A(n1533), .Y(n1555) );
INVX2TS U2421 ( .A(n1533), .Y(n1556) );
INVX4TS U2422 ( .A(n3001), .Y(n2382) );
NAND2X2TS U2423 ( .A(n3071), .B(n2957), .Y(n2681) );
OAI2BB2XLTS U2424 ( .B0(n2761), .B1(n3153), .A0N(n2734), .A1N(
result_add_subt[9]), .Y(n1215) );
OAI2BB2XLTS U2425 ( .B0(n2750), .B1(n3151), .A0N(n2754), .A1N(
result_add_subt[7]), .Y(n1207) );
OAI2BB2XLTS U2426 ( .B0(n2757), .B1(n3148), .A0N(n2754), .A1N(
result_add_subt[4]), .Y(n1195) );
OAI2BB2XLTS U2427 ( .B0(n2757), .B1(n3149), .A0N(n2754), .A1N(
result_add_subt[5]), .Y(n1199) );
OAI2BB2XLTS U2428 ( .B0(n2757), .B1(n3145), .A0N(n2761), .A1N(
result_add_subt[1]), .Y(n1183) );
OAI2BB2XLTS U2429 ( .B0(n2761), .B1(n3152), .A0N(n2734), .A1N(
result_add_subt[8]), .Y(n1211) );
OAI2BB2XLTS U2430 ( .B0(n2757), .B1(n3147), .A0N(n2754), .A1N(
result_add_subt[3]), .Y(n1191) );
OAI2BB2XLTS U2431 ( .B0(n2757), .B1(n3150), .A0N(n2754), .A1N(
result_add_subt[6]), .Y(n1203) );
OAI2BB2XLTS U2432 ( .B0(n2762), .B1(n3144), .A0N(n2761), .A1N(
result_add_subt[0]), .Y(n1146) );
OAI2BB2XLTS U2433 ( .B0(n2743), .B1(n3167), .A0N(n2745), .A1N(
result_add_subt[23]), .Y(n1271) );
OAI2BB2XLTS U2434 ( .B0(n2743), .B1(n3168), .A0N(n2750), .A1N(
result_add_subt[24]), .Y(n1275) );
OAI211XLTS U2435 ( .A0(n2027), .A1(n3051), .B0(n1988), .C0(n1987), .Y(n1302)
);
NOR2XLTS U2436 ( .A(d_ff2_X[27]), .B(n2721), .Y(n2719) );
OAI221X1TS U2437 ( .A0(n3005), .A1(add_subt_module_intDY[10]), .B0(n2995),
.B1(add_subt_module_intDY[2]), .C0(n1691), .Y(n1694) );
AOI222X1TS U2438 ( .A0(add_subt_module_intDY[4]), .A1(n3011), .B0(n2110),
.B1(n2109), .C0(add_subt_module_intDY[5]), .C1(n2970), .Y(n2112) );
OAI221X1TS U2439 ( .A0(n2984), .A1(add_subt_module_intDX[28]), .B0(n3021),
.B1(add_subt_module_intDY[6]), .C0(n1705), .Y(n1712) );
OAI21XLTS U2440 ( .A0(n2954), .A1(n2208), .B0(n2206), .Y(n899) );
OAI21XLTS U2441 ( .A0(n2985), .A1(n2208), .B0(n2207), .Y(n887) );
CLKBUFX3TS U2442 ( .A(n1775), .Y(n1752) );
NOR2X2TS U2443 ( .A(n2301), .B(n2300), .Y(n2497) );
OAI33X4TS U2444 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n3174), .B0(n2661), .B1(n3049), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1770) );
NOR2X2TS U2445 ( .A(n2639), .B(n2637), .Y(n1968) );
NOR2X2TS U2446 ( .A(n2258), .B(n1731), .Y(n2091) );
AOI211X1TS U2447 ( .A0(add_subt_module_intDY[16]), .A1(n3035), .B0(n2143),
.C0(n2144), .Y(n2135) );
CLKINVX3TS U2448 ( .A(n1772), .Y(n2056) );
CLKINVX3TS U2449 ( .A(n1772), .Y(n2060) );
BUFX3TS U2450 ( .A(n1756), .Y(n1754) );
OAI21XLTS U2451 ( .A0(n3144), .A1(n1825), .B0(n1808), .Y(n1080) );
OAI21XLTS U2452 ( .A0(n3150), .A1(n1825), .B0(n1824), .Y(n1068) );
OAI21XLTS U2453 ( .A0(n3147), .A1(n1825), .B0(n1810), .Y(n1074) );
OAI21XLTS U2454 ( .A0(n3152), .A1(n1825), .B0(n1804), .Y(n1064) );
OAI21XLTS U2455 ( .A0(n3145), .A1(n1825), .B0(n1812), .Y(n1078) );
OAI21XLTS U2456 ( .A0(n3149), .A1(n1825), .B0(n1815), .Y(n1070) );
OAI21XLTS U2457 ( .A0(n3148), .A1(n1825), .B0(n1805), .Y(n1072) );
OAI21XLTS U2458 ( .A0(n3151), .A1(n1825), .B0(n1820), .Y(n1066) );
OAI21XLTS U2459 ( .A0(n3153), .A1(n1825), .B0(n1800), .Y(n1062) );
OAI211XLTS U2460 ( .A0(n2073), .A1(n2070), .B0(n1866), .C0(n1865), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NOR2X4TS U2461 ( .A(n2959), .B(add_subt_module_FS_Module_state_reg[1]), .Y(
n1776) );
OAI21XLTS U2462 ( .A0(n3168), .A1(n1838), .B0(n1837), .Y(n1032) );
OAI21XLTS U2463 ( .A0(n3167), .A1(n1838), .B0(n1833), .Y(n1034) );
AOI31XLTS U2464 ( .A0(n2702), .A1(n2705), .A2(n2701), .B0(n2784), .Y(n2703)
);
NAND3X2TS U2465 ( .A(n2691), .B(n1562), .C(n2957), .Y(n2701) );
OAI21XLTS U2466 ( .A0(n1797), .A1(n1796), .B0(n1795), .Y(n1372) );
INVX2TS U2467 ( .A(n2961), .Y(n1557) );
NOR2X4TS U2468 ( .A(n1557), .B(cordic_FSM_state_reg[0]), .Y(n2654) );
AOI22X2TS U2469 ( .A0(n2392), .A1(n1897), .B0(n1896), .B1(n2636), .Y(n1944)
);
OAI21XLTS U2470 ( .A0(n2262), .A1(n1730), .B0(
add_subt_module_FS_Module_state_reg[3]), .Y(n1728) );
OAI22X2TS U2471 ( .A0(n1790), .A1(n2655), .B0(n1727), .B1(n1014), .Y(n2262)
);
CLKBUFX2TS U2472 ( .A(cont_iter_out[1]), .Y(n1558) );
NOR2X2TS U2473 ( .A(n2698), .B(cont_iter_out[1]), .Y(n2691) );
BUFX3TS U2474 ( .A(n1855), .Y(n1559) );
BUFX3TS U2475 ( .A(n1855), .Y(n1560) );
NOR2X2TS U2476 ( .A(n1861), .B(n2395), .Y(n1855) );
NOR3X4TS U2477 ( .A(n2948), .B(sel_mux_2_reg[0]), .C(n3025), .Y(n2891) );
AOI22X2TS U2478 ( .A0(add_subt_module_LZA_output[1]), .A1(n1574), .B0(n1852),
.B1(add_subt_module_exp_oper_result[1]), .Y(n1862) );
NOR2X2TS U2479 ( .A(d_ff2_X[23]), .B(n1562), .Y(n2713) );
AOI32X1TS U2480 ( .A0(add_subt_module_Add_Subt_result[10]), .A1(n1662), .A2(
n3028), .B0(add_subt_module_Add_Subt_result[12]), .B1(n1662), .Y(n2272) );
NOR2BX2TS U2481 ( .AN(n1645), .B(add_subt_module_Add_Subt_result[13]), .Y(
n1662) );
NOR2X2TS U2482 ( .A(n1653), .B(add_subt_module_Add_Subt_result[4]), .Y(n2270) );
OAI21XLTS U2483 ( .A0(add_subt_module_Add_Subt_result[1]), .A1(
add_subt_module_Add_Subt_result[0]), .B0(n2253), .Y(n2255) );
AOI31XLTS U2484 ( .A0(add_subt_module_Add_Subt_result[6]), .A1(n1661), .A2(
n3031), .B0(n1660), .Y(n1664) );
NOR2XLTS U2485 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_result[6]), .Y(n2249) );
OAI221X1TS U2486 ( .A0(n2960), .A1(add_subt_module_intDX[27]), .B0(n2989),
.B1(add_subt_module_intDY[19]), .C0(n1707), .Y(n1710) );
OAI221X1TS U2487 ( .A0(n2962), .A1(add_subt_module_intDY[17]), .B0(n3035),
.B1(add_subt_module_intDY[16]), .C0(n1715), .Y(n1718) );
NOR2XLTS U2488 ( .A(n2117), .B(add_subt_module_intDY[10]), .Y(n2118) );
OAI221X1TS U2489 ( .A0(n2992), .A1(add_subt_module_intDY[3]), .B0(n3016),
.B1(add_subt_module_intDX[26]), .C0(n1699), .Y(n1702) );
OAI21XLTS U2490 ( .A0(add_subt_module_intDX[13]), .A1(n2996), .B0(
add_subt_module_intDX[12]), .Y(n2116) );
NOR2X1TS U2491 ( .A(n3072), .B(add_subt_module_intDX[29]), .Y(n2098) );
AOI221X1TS U2492 ( .A0(add_subt_module_intDX[30]), .A1(n3073), .B0(
add_subt_module_intDX[29]), .B1(n3072), .C0(n2099), .Y(n2101) );
NOR2X1TS U2493 ( .A(n3073), .B(add_subt_module_intDX[30]), .Y(n2100) );
OAI221X1TS U2494 ( .A0(n2987), .A1(add_subt_module_intDY[20]), .B0(n3073),
.B1(add_subt_module_intDX[30]), .C0(n1713), .Y(n1720) );
NOR2X1TS U2495 ( .A(n3004), .B(add_subt_module_intDX[25]), .Y(n2152) );
OAI221X1TS U2496 ( .A0(n2969), .A1(add_subt_module_intDY[7]), .B0(n2964),
.B1(add_subt_module_intDY[14]), .C0(n1697), .Y(n1704) );
NAND3X4TS U2497 ( .A(n1572), .B(n1732), .C(n1571), .Y(n1639) );
OR2X1TS U2498 ( .A(n2347), .B(n2346), .Y(n1567) );
OAI21XLTS U2499 ( .A0(add_subt_module_intDX[1]), .A1(n1561), .B0(
add_subt_module_intDX[0]), .Y(n2105) );
OAI21XLTS U2500 ( .A0(add_subt_module_intDX[15]), .A1(n2956), .B0(
add_subt_module_intDX[14]), .Y(n2125) );
NOR2XLTS U2501 ( .A(n2138), .B(add_subt_module_intDY[16]), .Y(n2139) );
OAI21XLTS U2502 ( .A0(add_subt_module_intDX[21]), .A1(n2997), .B0(
add_subt_module_intDX[20]), .Y(n2137) );
AOI2BB2X1TS U2503 ( .B0(n2102), .B1(n2151), .A0N(n2101), .A1N(n2100), .Y(
n2157) );
CLKINVX3TS U2504 ( .A(n1891), .Y(n1880) );
INVX2TS U2505 ( .A(n2248), .Y(n1661) );
NAND4X1TS U2506 ( .A(n1724), .B(n1723), .C(n1722), .D(n1721), .Y(n2181) );
NAND2X1TS U2507 ( .A(n1568), .B(n1636), .Y(n1606) );
NAND2X1TS U2508 ( .A(n1609), .B(n1608), .Y(n1610) );
OAI211XLTS U2509 ( .A0(n2419), .A1(n3055), .B0(n2411), .C0(n2410), .Y(n2412)
);
OAI211XLTS U2510 ( .A0(n1977), .A1(n2020), .B0(n1738), .C0(n1737), .Y(n1739)
);
NOR2XLTS U2511 ( .A(n2636), .B(n2395), .Y(n2396) );
OAI21XLTS U2512 ( .A0(n2789), .A1(n3052), .B0(n2793), .Y(n2791) );
OAI21XLTS U2513 ( .A0(n2860), .A1(n3073), .B0(n1782), .Y(n1012) );
OAI32X1TS U2514 ( .A0(n1743), .A1(n1742), .A2(n3046), .B0(n2733), .B1(n1741),
.Y(n1465) );
OAI21XLTS U2515 ( .A0(n2244), .A1(n2995), .B0(n2235), .Y(n890) );
OAI21XLTS U2516 ( .A0(n3166), .A1(n1838), .B0(n1809), .Y(n1036) );
OAI21XLTS U2517 ( .A0(n3155), .A1(n1832), .B0(n1807), .Y(n1058) );
OAI21XLTS U2518 ( .A0(n3156), .A1(n1832), .B0(n1827), .Y(n1056) );
OAI21XLTS U2519 ( .A0(n3172), .A1(n1838), .B0(n1816), .Y(n1022) );
NOR2X2TS U2520 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n1760) );
INVX2TS U2521 ( .A(n1760), .Y(n1569) );
NAND2X1TS U2522 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .Y(n1685) );
NOR2X2TS U2523 ( .A(n1569), .B(n1685), .Y(n2090) );
NOR2X2TS U2524 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .Y(n1725) );
INVX2TS U2525 ( .A(n1725), .Y(n2087) );
AOI21X1TS U2526 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(
add_subt_module_FSM_selector_C), .B0(n2087), .Y(n1570) );
NOR2X1TS U2527 ( .A(n2090), .B(n1570), .Y(n1572) );
NAND2X2TS U2528 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n2978), .Y(
n2258) );
NOR2X2TS U2529 ( .A(n2258), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n2440) );
INVX2TS U2530 ( .A(n2440), .Y(n1732) );
NOR2X2TS U2531 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n2978), .Y(
n1759) );
NOR2X1TS U2532 ( .A(n1759), .B(n3142), .Y(n1571) );
NOR2X1TS U2533 ( .A(add_subt_module_FSM_selector_B[0]), .B(
add_subt_module_FSM_selector_B[1]), .Y(n1573) );
BUFX3TS U2534 ( .A(n1573), .Y(n1852) );
NAND2X1TS U2535 ( .A(n1574), .B(add_subt_module_LZA_output[0]), .Y(n1578) );
NAND2X1TS U2536 ( .A(n2980), .B(add_subt_module_FSM_selector_B[1]), .Y(n1577) );
NAND2X1TS U2537 ( .A(n1578), .B(n1577), .Y(n1854) );
INVX2TS U2538 ( .A(n1633), .Y(n1585) );
INVX2TS U2539 ( .A(n1623), .Y(n1625) );
AFHCONX2TS U2540 ( .A(n1629), .B(n1639), .CI(n1628), .CON(n1633), .S(n2617)
);
INVX2TS U2541 ( .A(n1630), .Y(n1632) );
AND4X1TS U2542 ( .A(n2619), .B(n2618), .C(n2617), .D(n2616), .Y(n1635) );
INVX2TS U2543 ( .A(n1639), .Y(n1640) );
NAND2X1TS U2544 ( .A(n1776), .B(n1725), .Y(n1676) );
NOR2X2TS U2545 ( .A(n2974), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n1730) );
NAND2X1TS U2546 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n1730), .Y(
n1675) );
NOR3X2TS U2547 ( .A(add_subt_module_Add_Subt_result[17]), .B(
add_subt_module_Add_Subt_result[16]), .C(
add_subt_module_Add_Subt_result[15]), .Y(n1648) );
NAND2X2TS U2548 ( .A(n2441), .B(n2448), .Y(n2266) );
NOR2X2TS U2549 ( .A(add_subt_module_Add_Subt_result[21]), .B(
add_subt_module_Add_Subt_result[20]), .Y(n2267) );
INVX2TS U2550 ( .A(n2267), .Y(n1644) );
NOR3X2TS U2551 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_result[10]), .C(n2451), .Y(n2252) );
NAND2X2TS U2552 ( .A(n2271), .B(n3030), .Y(n1653) );
OA21XLTS U2553 ( .A0(add_subt_module_Add_Subt_result[11]), .A1(
add_subt_module_Add_Subt_result[13]), .B0(n1645), .Y(n2269) );
NAND2X1TS U2554 ( .A(n2449), .B(n2272), .Y(n1660) );
AOI211X1TS U2555 ( .A0(add_subt_module_Add_Subt_result[1]), .A1(n2253), .B0(
n2269), .C0(n1660), .Y(n1646) );
NAND2X2TS U2556 ( .A(n2974), .B(n2440), .Y(n2453) );
INVX2TS U2557 ( .A(n2453), .Y(n2454) );
INVX2TS U2558 ( .A(n2654), .Y(n2642) );
INVX2TS U2559 ( .A(n1742), .Y(n1775) );
BUFX3TS U2560 ( .A(n1775), .Y(n3140) );
NOR2X2TS U2561 ( .A(n2953), .B(cordic_FSM_state_reg[3]), .Y(n1767) );
NAND3X1TS U2562 ( .A(n2971), .B(cordic_FSM_state_reg[1]), .C(n1767), .Y(
n1741) );
NOR2X2TS U2563 ( .A(n2783), .B(n1536), .Y(n1848) );
INVX2TS U2564 ( .A(n2735), .Y(n2653) );
INVX2TS U2565 ( .A(n1741), .Y(n1743) );
NAND2X1TS U2566 ( .A(sel_mux_2_reg[1]), .B(n3140), .Y(n1650) );
OAI32X1TS U2567 ( .A0(n1741), .A1(n2653), .A2(n2972), .B0(n1743), .B1(n1650),
.Y(n1464) );
NAND2X2TS U2568 ( .A(n1725), .B(n1760), .Y(n1014) );
NAND2X1TS U2569 ( .A(n2953), .B(cordic_FSM_state_reg[1]), .Y(n2671) );
OR3X1TS U2570 ( .A(n2671), .B(cordic_FSM_state_reg[3]), .C(
cordic_FSM_state_reg[0]), .Y(n2666) );
BUFX3TS U2571 ( .A(n2666), .Y(n2667) );
NOR2X2TS U2572 ( .A(cont_var_out[0]), .B(n2972), .Y(n2736) );
NAND4X1TS U2573 ( .A(n2953), .B(n2961), .C(cordic_FSM_state_reg[3]), .D(
cordic_FSM_state_reg[0]), .Y(n1844) );
INVX2TS U2574 ( .A(n1844), .Y(n1790) );
NAND3X2TS U2575 ( .A(n2736), .B(n1790), .C(n2735), .Y(n2659) );
NAND2X1TS U2576 ( .A(n2667), .B(n2659), .Y(n2660) );
NAND2X1TS U2577 ( .A(cont_iter_out[1]), .B(n1562), .Y(n2690) );
OAI2BB1X1TS U2578 ( .A0N(n2690), .A1N(n1651), .B0(n2667), .Y(n1652) );
OAI21XLTS U2579 ( .A0(n2660), .A1(n3143), .B0(n1652), .Y(n1503) );
NOR2BX1TS U2580 ( .AN(add_subt_module_Add_Subt_result[4]), .B(n1653), .Y(
n2250) );
AOI211X1TS U2581 ( .A0(n3029), .A1(n1654), .B0(
add_subt_module_Add_Subt_result[3]), .C0(n2246), .Y(n1655) );
AOI211X4TS U2582 ( .A0(n1659), .A1(add_subt_module_Add_Subt_result[18]),
.B0(n2250), .C0(n1655), .Y(n2275) );
AOI21X1TS U2583 ( .A0(n3024), .A1(add_subt_module_Add_Subt_result[20]), .B0(
add_subt_module_Add_Subt_result[22]), .Y(n1656) );
NOR2X1TS U2584 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_result[10]), .Y(n2452) );
AOI22X2TS U2585 ( .A0(add_subt_module_LZA_output[4]), .A1(n1574), .B0(n1852),
.B1(add_subt_module_exp_oper_result[4]), .Y(n1734) );
NOR2X1TS U2586 ( .A(n1734), .B(n1975), .Y(n1681) );
NAND2X1TS U2587 ( .A(n1975), .B(n1734), .Y(n1973) );
INVX2TS U2588 ( .A(n1973), .Y(n2009) );
INVX2TS U2589 ( .A(n1734), .Y(n1671) );
INVX2TS U2590 ( .A(n2012), .Y(n2399) );
AOI22X1TS U2591 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(
n2399), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n1667) );
OAI2BB1X1TS U2592 ( .A0N(n1681), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
n1667), .Y(n1986) );
INVX2TS U2593 ( .A(n1759), .Y(n1777) );
NAND2X1TS U2594 ( .A(n1777), .B(n2258), .Y(n1668) );
INVX4TS U2595 ( .A(n1998), .Y(n2013) );
BUFX3TS U2596 ( .A(n3002), .Y(n1953) );
NOR2X4TS U2597 ( .A(n1975), .B(n1671), .Y(n2008) );
NAND2X2TS U2598 ( .A(n1670), .B(n2008), .Y(n2398) );
AOI22X1TS U2599 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1551), .B0(add_subt_module_Sgf_normalized_result[25]), .B1(n2403),
.Y(n1678) );
NAND2X1TS U2600 ( .A(n1759), .B(add_subt_module_FSM_selector_C), .Y(n1673)
);
NAND2X1TS U2601 ( .A(n1673), .B(n2258), .Y(n1674) );
NAND2X2TS U2602 ( .A(n1677), .B(add_subt_module_add_overflow_flag), .Y(n2637) );
NOR3X4TS U2603 ( .A(n2403), .B(n2637), .C(n2009), .Y(n2416) );
INVX2TS U2604 ( .A(n2416), .Y(n1682) );
AOI22X1TS U2605 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(
n2399), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n1680) );
OAI2BB1X1TS U2606 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1N(
n1681), .B0(n1680), .Y(n1989) );
AOI22X1TS U2607 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
add_subt_module_Sgf_normalized_result[24]), .B1(n2403), .Y(n1683) );
NAND2X2TS U2608 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n1778) );
INVX2TS U2609 ( .A(n1776), .Y(n1686) );
AOI22X1TS U2610 ( .A0(add_subt_module_intDY[23]), .A1(
add_subt_module_intDX[23]), .B0(n3013), .B1(n3015), .Y(n1696) );
AOI22X1TS U2611 ( .A0(n2963), .A1(add_subt_module_intDY[15]), .B0(n2990),
.B1(add_subt_module_intDY[13]), .Y(n1690) );
OAI221XLTS U2612 ( .A0(n2963), .A1(add_subt_module_intDY[15]), .B0(n2990),
.B1(add_subt_module_intDY[13]), .C0(n1690), .Y(n1695) );
AOI22X1TS U2613 ( .A0(n3005), .A1(add_subt_module_intDY[10]), .B0(n2995),
.B1(add_subt_module_intDY[2]), .Y(n1691) );
AOI22X1TS U2614 ( .A0(n2968), .A1(add_subt_module_intDY[9]), .B0(n2954),
.B1(add_subt_module_intDY[11]), .Y(n1692) );
NOR4X1TS U2615 ( .A(n1696), .B(n1695), .C(n1694), .D(n1693), .Y(n1724) );
AOI22X1TS U2616 ( .A0(n2969), .A1(add_subt_module_intDY[7]), .B0(n2964),
.B1(add_subt_module_intDY[14]), .Y(n1697) );
AOI22X1TS U2617 ( .A0(n2970), .A1(add_subt_module_intDY[5]), .B0(n3011),
.B1(add_subt_module_intDY[4]), .Y(n1698) );
AOI22X1TS U2618 ( .A0(n2992), .A1(add_subt_module_intDY[3]), .B0(n3016),
.B1(add_subt_module_intDX[26]), .Y(n1699) );
AOI22X1TS U2619 ( .A0(n2955), .A1(add_subt_module_intDY[1]), .B0(n3003),
.B1(add_subt_module_intDX[0]), .Y(n1700) );
OAI221XLTS U2620 ( .A0(n2955), .A1(add_subt_module_intDY[1]), .B0(n3003),
.B1(add_subt_module_intDX[0]), .C0(n1700), .Y(n1701) );
NOR4X1TS U2621 ( .A(n1704), .B(n1703), .C(n1702), .D(n1701), .Y(n1723) );
AOI22X1TS U2622 ( .A0(n2984), .A1(add_subt_module_intDX[28]), .B0(n3021),
.B1(add_subt_module_intDY[6]), .Y(n1705) );
AOI22X1TS U2623 ( .A0(n2986), .A1(add_subt_module_intDY[18]), .B0(n3072),
.B1(add_subt_module_intDX[29]), .Y(n1706) );
AOI22X1TS U2624 ( .A0(n2960), .A1(add_subt_module_intDX[27]), .B0(n2989),
.B1(add_subt_module_intDY[19]), .Y(n1707) );
AOI22X1TS U2625 ( .A0(n3004), .A1(add_subt_module_intDX[25]), .B0(n2988),
.B1(add_subt_module_intDX[24]), .Y(n1708) );
NOR4X1TS U2626 ( .A(n1712), .B(n1711), .C(n1710), .D(n1709), .Y(n1722) );
AOI22X1TS U2627 ( .A0(n2987), .A1(add_subt_module_intDY[20]), .B0(n3073),
.B1(add_subt_module_intDX[30]), .Y(n1713) );
AOI22X1TS U2628 ( .A0(n2994), .A1(add_subt_module_intDY[8]), .B0(n2965),
.B1(add_subt_module_intDY[21]), .Y(n1714) );
OAI221XLTS U2629 ( .A0(n2994), .A1(add_subt_module_intDY[8]), .B0(n2965),
.B1(add_subt_module_intDY[21]), .C0(n1714), .Y(n1719) );
AOI22X1TS U2630 ( .A0(n2962), .A1(add_subt_module_intDY[17]), .B0(n3035),
.B1(add_subt_module_intDY[16]), .Y(n1715) );
AOI22X1TS U2631 ( .A0(n2985), .A1(add_subt_module_intDY[22]), .B0(n3006),
.B1(add_subt_module_intDX[12]), .Y(n1716) );
NOR4X1TS U2632 ( .A(n1720), .B(n1719), .C(n1718), .D(n1717), .Y(n1721) );
XNOR2X2TS U2633 ( .A(add_subt_module_intDY[31]), .B(add_subt_module_intAS),
.Y(n2183) );
XOR2X4TS U2634 ( .A(n2183), .B(add_subt_module_intDX[31]), .Y(n2280) );
NOR3X1TS U2635 ( .A(n2181), .B(n2241), .C(n2280), .Y(n2264) );
OR4X2TS U2636 ( .A(n2502), .B(n1687), .C(n2089), .D(n1726), .Y(n1729) );
INVX2TS U2637 ( .A(n1841), .Y(n1727) );
AOI21X1TS U2638 ( .A0(add_subt_module_FSM_selector_B[1]), .A1(n1732), .B0(
n2091), .Y(n1733) );
OAI21XLTS U2639 ( .A0(n2453), .A1(n3142), .B0(n1733), .Y(n1516) );
AOI22X1TS U2640 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(
n2008), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(
n1735) );
INVX2TS U2641 ( .A(n1736), .Y(n1974) );
NAND2X1TS U2642 ( .A(n1735), .B(n1974), .Y(n2016) );
AOI21X1TS U2643 ( .A0(n2008), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(
n1736), .Y(n2020) );
NAND2X1TS U2644 ( .A(n1549), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n1738) );
NAND2X1TS U2645 ( .A(n2013), .B(add_subt_module_Sgf_normalized_result[12]),
.Y(n1737) );
XOR2X1TS U2646 ( .A(n2661), .B(d_ff1_operation_out), .Y(n1740) );
XNOR2X1TS U2647 ( .A(n3174), .B(n1740), .Y(n1797) );
AOI21X1TS U2648 ( .A0(cont_var_out[0]), .A1(n2735), .B0(n2657), .Y(n2733) );
AOI22X1TS U2649 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(
n2008), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(
n1744) );
NAND2X1TS U2650 ( .A(n1744), .B(n1974), .Y(n2002) );
NOR2X2TS U2651 ( .A(n1974), .B(n1977), .Y(n2422) );
CLKBUFX2TS U2652 ( .A(n1748), .Y(n2429) );
OAI2BB1X1TS U2653 ( .A0N(n1670), .A1N(n2002), .B0(n1746), .Y(n1312) );
AOI22X1TS U2654 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(
n2008), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(
n1747) );
NAND2X1TS U2655 ( .A(n1747), .B(n1974), .Y(n1999) );
OAI2BB1X1TS U2656 ( .A0N(n1670), .A1N(n1999), .B0(n1750), .Y(n1313) );
CLKBUFX2TS U2657 ( .A(n1775), .Y(n1753) );
BUFX3TS U2658 ( .A(n3138), .Y(n3131) );
BUFX3TS U2659 ( .A(n3139), .Y(n3132) );
CLKBUFX2TS U2660 ( .A(n1775), .Y(n1751) );
BUFX3TS U2661 ( .A(n3138), .Y(n3109) );
BUFX3TS U2662 ( .A(n1753), .Y(n3106) );
BUFX3TS U2663 ( .A(n3139), .Y(n3105) );
CLKBUFX2TS U2664 ( .A(n1775), .Y(n1758) );
BUFX3TS U2665 ( .A(n3138), .Y(n3111) );
BUFX3TS U2666 ( .A(n1758), .Y(n3103) );
BUFX3TS U2667 ( .A(n1752), .Y(n3113) );
BUFX3TS U2668 ( .A(n1751), .Y(n3102) );
BUFX3TS U2669 ( .A(n1755), .Y(n3115) );
BUFX3TS U2670 ( .A(n1753), .Y(n3127) );
BUFX3TS U2671 ( .A(n3139), .Y(n3126) );
BUFX3TS U2672 ( .A(n1758), .Y(n3125) );
CLKBUFX2TS U2673 ( .A(n1756), .Y(n1757) );
BUFX3TS U2674 ( .A(n3086), .Y(n3081) );
BUFX3TS U2675 ( .A(n3084), .Y(n3082) );
CLKBUFX2TS U2676 ( .A(n1775), .Y(n1755) );
BUFX3TS U2677 ( .A(n1752), .Y(n3124) );
BUFX3TS U2678 ( .A(n1758), .Y(n3136) );
BUFX3TS U2679 ( .A(n1751), .Y(n3135) );
BUFX3TS U2680 ( .A(n1753), .Y(n3133) );
BUFX3TS U2681 ( .A(n1752), .Y(n3101) );
BUFX3TS U2682 ( .A(n1755), .Y(n3123) );
BUFX3TS U2683 ( .A(n1755), .Y(n3104) );
BUFX3TS U2684 ( .A(n3138), .Y(n3107) );
BUFX3TS U2685 ( .A(n1752), .Y(n3110) );
BUFX3TS U2686 ( .A(n3139), .Y(n3112) );
BUFX3TS U2687 ( .A(n1753), .Y(n3114) );
BUFX3TS U2688 ( .A(n3139), .Y(n3116) );
BUFX3TS U2689 ( .A(n1758), .Y(n3117) );
BUFX3TS U2690 ( .A(n3138), .Y(n3122) );
BUFX3TS U2691 ( .A(n1751), .Y(n3118) );
BUFX3TS U2692 ( .A(n1758), .Y(n3119) );
BUFX3TS U2693 ( .A(n1752), .Y(n3137) );
BUFX3TS U2694 ( .A(n3090), .Y(n3083) );
BUFX3TS U2695 ( .A(n1756), .Y(n3085) );
BUFX3TS U2696 ( .A(n1756), .Y(n3086) );
BUFX3TS U2697 ( .A(n1751), .Y(n3130) );
BUFX3TS U2698 ( .A(n1751), .Y(n3120) );
BUFX3TS U2699 ( .A(n3089), .Y(n3094) );
BUFX3TS U2700 ( .A(n1756), .Y(n3087) );
BUFX3TS U2701 ( .A(n3087), .Y(n3078) );
BUFX3TS U2702 ( .A(n3086), .Y(n3091) );
BUFX3TS U2703 ( .A(n3085), .Y(n3076) );
BUFX3TS U2704 ( .A(n3086), .Y(n3075) );
BUFX3TS U2705 ( .A(n3087), .Y(n3077) );
BUFX3TS U2706 ( .A(n3087), .Y(n3092) );
BUFX3TS U2707 ( .A(n1756), .Y(n3084) );
BUFX3TS U2708 ( .A(n1755), .Y(n3134) );
BUFX3TS U2709 ( .A(n1756), .Y(n3088) );
CLKBUFX2TS U2710 ( .A(n1756), .Y(n3100) );
BUFX3TS U2711 ( .A(n3084), .Y(n3097) );
BUFX3TS U2712 ( .A(n3085), .Y(n3079) );
BUFX3TS U2713 ( .A(n3085), .Y(n3095) );
BUFX3TS U2714 ( .A(n1756), .Y(n3090) );
BUFX3TS U2715 ( .A(n3090), .Y(n3098) );
BUFX3TS U2716 ( .A(n1754), .Y(n3093) );
BUFX3TS U2717 ( .A(n3088), .Y(n3096) );
BUFX3TS U2718 ( .A(n1754), .Y(n3074) );
BUFX3TS U2719 ( .A(n1753), .Y(n3121) );
BUFX3TS U2720 ( .A(n1756), .Y(n3089) );
BUFX3TS U2721 ( .A(n3088), .Y(n3080) );
BUFX3TS U2722 ( .A(n1752), .Y(n3129) );
BUFX3TS U2723 ( .A(n1755), .Y(n3108) );
CLKBUFX3TS U2724 ( .A(n3089), .Y(n3099) );
BUFX3TS U2725 ( .A(n1755), .Y(n3128) );
BUFX3TS U2726 ( .A(n2901), .Y(n2852) );
AOI22X1TS U2727 ( .A0(add_subt_module_intDX[24]), .A1(n2929), .B0(n2852),
.B1(d_ff2_X[24]), .Y(n1762) );
BUFX3TS U2728 ( .A(n2891), .Y(n2950) );
BUFX3TS U2729 ( .A(n2949), .Y(n2841) );
AOI22X1TS U2730 ( .A0(n2950), .A1(d_ff2_Z[24]), .B0(n2841), .B1(d_ff2_Y[24]),
.Y(n1761) );
NAND2X1TS U2731 ( .A(n1762), .B(n1761), .Y(n982) );
BUFX3TS U2732 ( .A(n2901), .Y(n2822) );
AOI22X1TS U2733 ( .A0(add_subt_module_intDX[26]), .A1(n2904), .B0(n2822),
.B1(d_ff2_X[26]), .Y(n1764) );
AOI22X1TS U2734 ( .A0(n2950), .A1(d_ff2_Z[26]), .B0(n2841), .B1(d_ff2_Y[26]),
.Y(n1763) );
NAND2X1TS U2735 ( .A(n1764), .B(n1763), .Y(n988) );
AOI22X1TS U2736 ( .A0(add_subt_module_intDX[25]), .A1(n2857), .B0(n2822),
.B1(d_ff2_X[25]), .Y(n1766) );
AOI22X1TS U2737 ( .A0(n2950), .A1(d_ff2_Z[25]), .B0(n2841), .B1(d_ff2_Y[25]),
.Y(n1765) );
NAND2X1TS U2738 ( .A(n1766), .B(n1765), .Y(n985) );
INVX2TS U2739 ( .A(n1767), .Y(n2645) );
BUFX3TS U2740 ( .A(n2714), .Y(n2704) );
OR2X2TS U2741 ( .A(n1848), .B(n2704), .Y(n2679) );
BUFX3TS U2742 ( .A(n2714), .Y(n2694) );
BUFX3TS U2743 ( .A(n2704), .Y(n2790) );
INVX2TS U2744 ( .A(n2790), .Y(n2729) );
NAND2X1TS U2745 ( .A(d_ff2_X[24]), .B(n3143), .Y(n1768) );
AOI22X1TS U2746 ( .A0(cont_iter_out[1]), .A1(n3014), .B0(n2713), .B1(n1768),
.Y(n2716) );
NOR2X2TS U2747 ( .A(n2953), .B(n3022), .Y(n2641) );
CLKBUFX2TS U2748 ( .A(n2806), .Y(n2808) );
INVX2TS U2749 ( .A(n2808), .Y(n2812) );
CLKBUFX2TS U2750 ( .A(n2806), .Y(n2811) );
NOR2X2TS U2751 ( .A(n3143), .B(n2681), .Y(n2685) );
NAND2X1TS U2752 ( .A(n2698), .B(n2685), .Y(n2675) );
OAI221X1TS U2753 ( .A0(cont_iter_out[3]), .A1(n2690), .B0(n2957), .B1(n2698),
.C0(n2675), .Y(n2682) );
BUFX3TS U2754 ( .A(n2790), .Y(n2780) );
BUFX3TS U2755 ( .A(n2780), .Y(n2784) );
OAI2BB2XLTS U2756 ( .B0(n2784), .B1(n2698), .A0N(n2694), .A1N(
d_ff3_LUT_out[8]), .Y(n1444) );
BUFX3TS U2757 ( .A(n2768), .Y(n2772) );
BUFX3TS U2758 ( .A(n2772), .Y(n2775) );
INVX2TS U2759 ( .A(n2775), .Y(n2708) );
OA22X1TS U2760 ( .A0(d_ff2_X[24]), .A1(n2709), .B0(d_ff_Xn[24]), .B1(n2708),
.Y(n1428) );
BUFX3TS U2761 ( .A(n2764), .Y(n1774) );
INVX2TS U2762 ( .A(n2775), .Y(n1773) );
OA22X1TS U2763 ( .A0(d_ff2_X[10]), .A1(n1774), .B0(d_ff_Xn[10]), .B1(n1773),
.Y(n1394) );
OA22X1TS U2764 ( .A0(d_ff2_X[6]), .A1(n1774), .B0(d_ff_Xn[6]), .B1(n1773),
.Y(n1386) );
OA22X1TS U2765 ( .A0(d_ff2_X[3]), .A1(n1774), .B0(d_ff_Xn[3]), .B1(n1773),
.Y(n1380) );
OA22X1TS U2766 ( .A0(d_ff2_X[7]), .A1(n1774), .B0(d_ff_Xn[7]), .B1(n1773),
.Y(n1388) );
OA22X1TS U2767 ( .A0(d_ff2_X[17]), .A1(n2709), .B0(d_ff_Xn[17]), .B1(n2708),
.Y(n1408) );
OA22X1TS U2768 ( .A0(d_ff2_X[25]), .A1(n2709), .B0(d_ff_Xn[25]), .B1(n2708),
.Y(n1429) );
OA22X1TS U2769 ( .A0(d_ff2_X[19]), .A1(n2709), .B0(d_ff_Xn[19]), .B1(n2708),
.Y(n1412) );
OA22X1TS U2770 ( .A0(d_ff2_X[14]), .A1(n1774), .B0(d_ff_Xn[14]), .B1(n1773),
.Y(n1402) );
OA22X1TS U2771 ( .A0(d_ff2_X[1]), .A1(n2764), .B0(d_ff_Xn[1]), .B1(n1773),
.Y(n1376) );
OA22X1TS U2772 ( .A0(d_ff2_X[12]), .A1(n1774), .B0(d_ff_Xn[12]), .B1(n1773),
.Y(n1398) );
OA22X1TS U2773 ( .A0(d_ff2_X[2]), .A1(n1774), .B0(d_ff_Xn[2]), .B1(n1773),
.Y(n1378) );
OA22X1TS U2774 ( .A0(d_ff2_X[26]), .A1(n2709), .B0(d_ff_Xn[26]), .B1(n2708),
.Y(n1430) );
OA22X1TS U2775 ( .A0(d_ff2_X[16]), .A1(n1774), .B0(d_ff_Xn[16]), .B1(n2708),
.Y(n1406) );
OA22X1TS U2776 ( .A0(d_ff2_X[5]), .A1(n1774), .B0(d_ff_Xn[5]), .B1(n1773),
.Y(n1384) );
OA22X1TS U2777 ( .A0(d_ff2_X[20]), .A1(n2709), .B0(d_ff_Xn[20]), .B1(n2708),
.Y(n1414) );
OA22X1TS U2778 ( .A0(d_ff2_X[13]), .A1(n1774), .B0(d_ff_Xn[13]), .B1(n1773),
.Y(n1400) );
OA22X1TS U2779 ( .A0(d_ff2_X[29]), .A1(n2764), .B0(d_ff_Xn[29]), .B1(n2708),
.Y(n1433) );
OA22X1TS U2780 ( .A0(d_ff2_X[28]), .A1(n2709), .B0(d_ff_Xn[28]), .B1(n2708),
.Y(n1432) );
INVX2TS U2781 ( .A(n2775), .Y(n2802) );
OAI2BB2XLTS U2782 ( .B0(n3152), .B1(n2802), .A0N(d_ff2_Y[8]), .A1N(n2770),
.Y(n1129) );
BUFX3TS U2783 ( .A(n1775), .Y(n3138) );
BUFX3TS U2784 ( .A(n1775), .Y(n3139) );
BUFX3TS U2785 ( .A(n3002), .Y(n1902) );
INVX2TS U2786 ( .A(n2090), .Y(n2257) );
OAI211X1TS U2787 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n3002),
.B0(add_subt_module_FS_Module_state_reg[0]), .C0(n1776), .Y(n2259) );
INVX2TS U2788 ( .A(n2860), .Y(n2817) );
AOI222X1TS U2789 ( .A0(n2943), .A1(add_subt_module_intDY[31]), .B0(
d_ff3_sh_x_out[31]), .B1(n2949), .C0(d_ff3_sh_y_out[31]), .C1(n2901),
.Y(n3141) );
BUFX3TS U2790 ( .A(n2949), .Y(n2831) );
AOI22X1TS U2791 ( .A0(d_ff3_sh_x_out[30]), .A1(n2831), .B0(
d_ff3_sh_y_out[30]), .B1(n2901), .Y(n1782) );
AOI22X1TS U2792 ( .A0(n2831), .A1(d_ff3_sh_x_out[29]), .B0(n2822), .B1(
d_ff3_sh_y_out[29]), .Y(n1783) );
BUFX3TS U2793 ( .A(n2891), .Y(n2940) );
NAND2X1TS U2794 ( .A(n2940), .B(d_ff3_LUT_out[27]), .Y(n1785) );
AOI22X1TS U2795 ( .A0(n2831), .A1(d_ff3_sh_x_out[28]), .B0(n2822), .B1(
d_ff3_sh_y_out[28]), .Y(n1784) );
AOI22X1TS U2796 ( .A0(n2831), .A1(d_ff3_sh_x_out[27]), .B0(n2822), .B1(
d_ff3_sh_y_out[27]), .Y(n1786) );
INVX2TS U2797 ( .A(n2671), .Y(n1794) );
BUFX3TS U2798 ( .A(n1801), .Y(n1835) );
AOI22X1TS U2799 ( .A0(d_ff_Xn[30]), .A1(n1787), .B0(sign_inv_out[30]), .B1(
n1835), .Y(n1788) );
AOI22X1TS U2800 ( .A0(d_ff_Xn[31]), .A1(n1787), .B0(data_output2_31_), .B1(
n1835), .Y(n1789) );
INVX2TS U2801 ( .A(n1792), .Y(n1793) );
AOI31XLTS U2802 ( .A0(n1790), .A1(n2972), .A2(n2735), .B0(cont_var_out[0]),
.Y(n1791) );
BUFX3TS U2803 ( .A(n2790), .Y(n2710) );
INVX2TS U2804 ( .A(n2710), .Y(n2794) );
BUFX3TS U2805 ( .A(n1799), .Y(n1838) );
BUFX3TS U2806 ( .A(n1787), .Y(n1836) );
AOI22X1TS U2807 ( .A0(d_ff_Xn[27]), .A1(n1836), .B0(sign_inv_out[27]), .B1(
n1835), .Y(n1798) );
BUFX3TS U2808 ( .A(n1799), .Y(n1825) );
BUFX3TS U2809 ( .A(n1787), .Y(n1823) );
BUFX3TS U2810 ( .A(n1801), .Y(n1822) );
AOI22X1TS U2811 ( .A0(d_ff_Xn[9]), .A1(n1823), .B0(sign_inv_out[9]), .B1(
n1822), .Y(n1800) );
BUFX3TS U2812 ( .A(n1801), .Y(n1829) );
AOI22X1TS U2813 ( .A0(d_ff_Xn[21]), .A1(n1836), .B0(sign_inv_out[21]), .B1(
n1829), .Y(n1802) );
BUFX3TS U2814 ( .A(n1799), .Y(n1832) );
BUFX3TS U2815 ( .A(n1787), .Y(n1830) );
AOI22X1TS U2816 ( .A0(d_ff_Xn[18]), .A1(n1830), .B0(sign_inv_out[18]), .B1(
n1829), .Y(n1803) );
AOI22X1TS U2817 ( .A0(d_ff_Xn[8]), .A1(n1823), .B0(sign_inv_out[8]), .B1(
n1822), .Y(n1804) );
AOI22X1TS U2818 ( .A0(d_ff_Xn[4]), .A1(n1823), .B0(sign_inv_out[4]), .B1(
n1822), .Y(n1805) );
AOI22X1TS U2819 ( .A0(d_ff_Xn[15]), .A1(n1830), .B0(sign_inv_out[15]), .B1(
n1829), .Y(n1806) );
AOI22X1TS U2820 ( .A0(d_ff_Xn[11]), .A1(n1830), .B0(sign_inv_out[11]), .B1(
n1822), .Y(n1807) );
AOI22X1TS U2821 ( .A0(d_ff_Xn[0]), .A1(n1823), .B0(sign_inv_out[0]), .B1(
n1801), .Y(n1808) );
AOI22X1TS U2822 ( .A0(d_ff_Xn[22]), .A1(n1836), .B0(sign_inv_out[22]), .B1(
n1835), .Y(n1809) );
AOI22X1TS U2823 ( .A0(d_ff_Xn[3]), .A1(n1823), .B0(sign_inv_out[3]), .B1(
n1822), .Y(n1810) );
AOI22X1TS U2824 ( .A0(d_ff_Xn[20]), .A1(n1836), .B0(sign_inv_out[20]), .B1(
n1829), .Y(n1811) );
AOI22X1TS U2825 ( .A0(d_ff_Xn[1]), .A1(n1823), .B0(sign_inv_out[1]), .B1(
n1801), .Y(n1812) );
AOI22X1TS U2826 ( .A0(d_ff_Xn[17]), .A1(n1830), .B0(sign_inv_out[17]), .B1(
n1829), .Y(n1813) );
AOI22X1TS U2827 ( .A0(d_ff_Xn[13]), .A1(n1830), .B0(sign_inv_out[13]), .B1(
n1829), .Y(n1814) );
AOI22X1TS U2828 ( .A0(d_ff_Xn[5]), .A1(n1823), .B0(sign_inv_out[5]), .B1(
n1822), .Y(n1815) );
AOI22X1TS U2829 ( .A0(d_ff_Xn[29]), .A1(n1836), .B0(sign_inv_out[29]), .B1(
n1835), .Y(n1816) );
AOI22X1TS U2830 ( .A0(d_ff_Xn[10]), .A1(n1830), .B0(sign_inv_out[10]), .B1(
n1822), .Y(n1817) );
AOI22X1TS U2831 ( .A0(d_ff_Xn[2]), .A1(n1823), .B0(sign_inv_out[2]), .B1(
n1822), .Y(n1818) );
AOI22X1TS U2832 ( .A0(d_ff_Xn[19]), .A1(n1830), .B0(sign_inv_out[19]), .B1(
n1829), .Y(n1819) );
AOI22X1TS U2833 ( .A0(d_ff_Xn[7]), .A1(n1823), .B0(sign_inv_out[7]), .B1(
n1822), .Y(n1820) );
AOI22X1TS U2834 ( .A0(d_ff_Xn[14]), .A1(n1830), .B0(sign_inv_out[14]), .B1(
n1829), .Y(n1821) );
AOI22X1TS U2835 ( .A0(d_ff_Xn[6]), .A1(n1823), .B0(sign_inv_out[6]), .B1(
n1822), .Y(n1824) );
AOI22X1TS U2836 ( .A0(d_ff_Xn[25]), .A1(n1836), .B0(sign_inv_out[25]), .B1(
n1835), .Y(n1826) );
AOI22X1TS U2837 ( .A0(d_ff_Xn[12]), .A1(n1830), .B0(sign_inv_out[12]), .B1(
n1829), .Y(n1827) );
AOI22X1TS U2838 ( .A0(d_ff_Xn[26]), .A1(n1836), .B0(sign_inv_out[26]), .B1(
n1835), .Y(n1828) );
AOI22X1TS U2839 ( .A0(d_ff_Xn[16]), .A1(n1830), .B0(sign_inv_out[16]), .B1(
n1829), .Y(n1831) );
AOI22X1TS U2840 ( .A0(d_ff_Xn[23]), .A1(n1836), .B0(sign_inv_out[23]), .B1(
n1835), .Y(n1833) );
AOI22X1TS U2841 ( .A0(d_ff_Xn[28]), .A1(n1836), .B0(sign_inv_out[28]), .B1(
n1835), .Y(n1834) );
AOI22X1TS U2842 ( .A0(d_ff_Xn[24]), .A1(n1836), .B0(sign_inv_out[24]), .B1(
n1835), .Y(n1837) );
AOI21X1TS U2843 ( .A0(d_ff3_LUT_out[9]), .A1(n2784), .B0(n1839), .Y(n1840)
);
OAI31X1TS U2844 ( .A0(n2698), .A1(n2710), .A2(n2690), .B0(n1840), .Y(n1445)
);
OAI32X1TS U2845 ( .A0(n2654), .A1(cordic_FSM_state_reg[1]), .A2(n2653), .B0(
n2953), .B1(n2654), .Y(n1842) );
NAND2X1TS U2846 ( .A(cordic_FSM_state_reg[1]), .B(n2971), .Y(n1846) );
NOR2XLTS U2847 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.Y(n1843) );
AOI31XLTS U2848 ( .A0(cordic_FSM_state_reg[0]), .A1(beg_fsm_cordic), .A2(
n1843), .B0(n2796), .Y(n1845) );
AOI22X1TS U2849 ( .A0(n2796), .A1(n2779), .B0(d_ff3_sh_y_out[23]), .B1(n2784), .Y(n1847) );
OAI31X1TS U2850 ( .A0(n3071), .A1(n2710), .A2(n2975), .B0(n1847), .Y(n1091)
);
AOI22X1TS U2851 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[10]), .B0(
add_subt_module_DmP[13]), .B1(n1902), .Y(n1850) );
OAI2BB1X1TS U2852 ( .A0N(add_subt_module_Add_Subt_result[15]), .A1N(n1880),
.B0(n1850), .Y(n1892) );
INVX2TS U2853 ( .A(n1891), .Y(n1956) );
AOI22X1TS U2854 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[6]), .B0(
add_subt_module_DmP[17]), .B1(n1953), .Y(n1851) );
OAI2BB1X1TS U2855 ( .A0N(add_subt_module_Add_Subt_result[19]), .A1N(n1956),
.B0(n1851), .Y(n1961) );
BUFX3TS U2856 ( .A(n1877), .Y(n1904) );
AOI22X2TS U2857 ( .A0(n1962), .A1(n1892), .B0(n1961), .B1(n1904), .Y(n2073)
);
INVX2TS U2858 ( .A(n1862), .Y(n2395) );
AOI21X2TS U2859 ( .A0(add_subt_module_exp_oper_result[0]), .A1(n2980), .B0(
n1854), .Y(n1861) );
NAND2X2TS U2860 ( .A(n2395), .B(n1861), .Y(n2070) );
OAI2BB2XLTS U2861 ( .B0(n1947), .B1(n3028), .A0N(add_subt_module_DmP[12]),
.A1N(n1902), .Y(n1856) );
AOI21X1TS U2862 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[14]), .B0(
n1856), .Y(n1905) );
OAI2BB2XLTS U2863 ( .B0(n1947), .B1(n3031), .A0N(add_subt_module_DmP[16]),
.A1N(n1902), .Y(n1857) );
AOI21X1TS U2864 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[18]), .B0(
n1857), .Y(n2067) );
AOI21X1TS U2865 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[13]), .B0(
n1859), .Y(n1901) );
AOI21X1TS U2866 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[17]), .B0(
n1860), .Y(n1868) );
AOI22X1TS U2867 ( .A0(n1560), .A1(n1893), .B0(n1552), .B1(n1914), .Y(n1866)
);
AOI21X1TS U2868 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[16]), .B0(
n1863), .Y(n1872) );
OAI2BB2XLTS U2869 ( .B0(n1947), .B1(n3030), .A0N(add_subt_module_DmP[18]),
.A1N(n1902), .Y(n1864) );
AOI21X1TS U2870 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[20]), .B0(
n1864), .Y(n1957) );
NAND2X1TS U2871 ( .A(n1556), .B(n2074), .Y(n1865) );
INVX2TS U2872 ( .A(n1855), .Y(n2083) );
AOI22X1TS U2873 ( .A0(n1547), .A1(n2074), .B0(n1552), .B1(n1893), .Y(n1870)
);
AOI21X1TS U2874 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[21]), .B0(
n1867), .Y(n1952) );
NAND2X1TS U2875 ( .A(n1555), .B(n2075), .Y(n1869) );
AOI21X1TS U2876 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[12]), .B0(
n1871), .Y(n1899) );
AOI22X1TS U2877 ( .A0(n1559), .A1(n1914), .B0(n1552), .B1(n1913), .Y(n1874)
);
NAND2X1TS U2878 ( .A(n1547), .B(n1893), .Y(n1873) );
AOI22X1TS U2879 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[22]), .B0(
add_subt_module_DmP[1]), .B1(n1953), .Y(n1875) );
OAI21X1TS U2880 ( .A0(n3017), .A1(n1891), .B0(n1875), .Y(n1878) );
AOI22X1TS U2881 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[18]), .B0(
add_subt_module_DmP[5]), .B1(n1953), .Y(n1876) );
OAI21X1TS U2882 ( .A0(n3031), .A1(n1891), .B0(n1876), .Y(n1897) );
BUFX3TS U2883 ( .A(n1877), .Y(n2636) );
BUFX3TS U2884 ( .A(n2636), .Y(n1970) );
AOI22X1TS U2885 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n1546), .B1(add_subt_module_Add_Subt_result[24]), .Y(n1881) );
AOI21X1TS U2886 ( .A0(n1880), .A1(add_subt_module_Add_Subt_result[5]), .B0(
n1879), .Y(n1921) );
AOI22X1TS U2887 ( .A0(n2392), .A1(n1881), .B0(n1921), .B1(n1970), .Y(n1935)
);
AOI22X1TS U2888 ( .A0(n1954), .A1(add_subt_module_Add_Subt_result[23]), .B0(
add_subt_module_DmP[0]), .B1(n1953), .Y(n1884) );
INVX2TS U2889 ( .A(n1970), .Y(n2639) );
NAND2X1TS U2890 ( .A(add_subt_module_Add_Subt_result[2]), .B(n1956), .Y(
n1883) );
AOI21X1TS U2891 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[6]), .B0(
n1882), .Y(n1925) );
AOI22X1TS U2892 ( .A0(n1560), .A1(n1935), .B0(n1548), .B1(n1934), .Y(n1889)
);
AOI22X1TS U2893 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[0]), .B0(
add_subt_module_Add_Subt_result[25]), .B1(n1546), .Y(n1886) );
AOI21X1TS U2894 ( .A0(add_subt_module_Add_Subt_result[4]), .A1(n1948), .B0(
n1885), .Y(n1919) );
AOI22X1TS U2895 ( .A0(n1962), .A1(n1886), .B0(n1919), .B1(n1970), .Y(n1887)
);
NAND2X1TS U2896 ( .A(n1553), .B(n1887), .Y(n1888) );
AOI22X1TS U2897 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[14]), .B0(
add_subt_module_DmP[9]), .B1(n1953), .Y(n1890) );
OAI21X1TS U2898 ( .A0(n3028), .A1(n1891), .B0(n1890), .Y(n1896) );
AOI22X2TS U2899 ( .A0(n1962), .A1(n1896), .B0(n1892), .B1(n1904), .Y(n1917)
);
AOI22X1TS U2900 ( .A0(n1559), .A1(n1913), .B0(n1548), .B1(n1914), .Y(n1895)
);
NAND2X1TS U2901 ( .A(n1556), .B(n1893), .Y(n1894) );
AOI21X1TS U2902 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[8]), .B0(
n1898), .Y(n1918) );
AOI21X1TS U2903 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[9]), .B0(
n1900), .Y(n1920) );
AOI22X1TS U2904 ( .A0(n1560), .A1(n1930), .B0(n1547), .B1(n1931), .Y(n1907)
);
AOI21X1TS U2905 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[10]), .B0(
n1903), .Y(n1924) );
AOI22X2TS U2906 ( .A0(n2392), .A1(n1924), .B0(n1905), .B1(n1904), .Y(n1912)
);
NAND2X1TS U2907 ( .A(n1556), .B(n1912), .Y(n1906) );
AOI22X1TS U2908 ( .A0(n1560), .A1(n1912), .B0(n1553), .B1(n1931), .Y(n1909)
);
NAND2X1TS U2909 ( .A(n1555), .B(n1913), .Y(n1908) );
AOI22X1TS U2910 ( .A0(n1560), .A1(n1931), .B0(n1552), .B1(n1930), .Y(n1911)
);
NAND2X1TS U2911 ( .A(n1548), .B(n1912), .Y(n1910) );
AOI22X1TS U2912 ( .A0(n1548), .A1(n1913), .B0(n1553), .B1(n1912), .Y(n1916)
);
NAND2X1TS U2913 ( .A(n1555), .B(n1914), .Y(n1915) );
AOI22X1TS U2914 ( .A0(n1547), .A1(n1939), .B0(n1552), .B1(n1934), .Y(n1923)
);
NAND2X1TS U2915 ( .A(n1555), .B(n1940), .Y(n1922) );
AOI22X1TS U2916 ( .A0(n1559), .A1(n1939), .B0(n1547), .B1(n1940), .Y(n1927)
);
AOI22X2TS U2917 ( .A0(n2392), .A1(n1925), .B0(n1924), .B1(n1970), .Y(n1941)
);
NAND2X1TS U2918 ( .A(n1556), .B(n1941), .Y(n1926) );
AOI22X1TS U2919 ( .A0(n1559), .A1(n1941), .B0(n1553), .B1(n1940), .Y(n1929)
);
NAND2X1TS U2920 ( .A(n1555), .B(n1930), .Y(n1928) );
AOI22X1TS U2921 ( .A0(n1547), .A1(n1930), .B0(n1552), .B1(n1941), .Y(n1933)
);
NAND2X1TS U2922 ( .A(n1556), .B(n1931), .Y(n1932) );
AOI22X1TS U2923 ( .A0(n1560), .A1(n1934), .B0(n1555), .B1(n1939), .Y(n1937)
);
NAND2X1TS U2924 ( .A(n1553), .B(n1935), .Y(n1936) );
AOI22X1TS U2925 ( .A0(n1559), .A1(n1940), .B0(n1553), .B1(n1939), .Y(n1943)
);
NAND2X1TS U2926 ( .A(n1548), .B(n1941), .Y(n1942) );
AOI22X1TS U2927 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[22]), .B0(
add_subt_module_DmP[20]), .B1(n1953), .Y(n1945) );
OAI21X2TS U2928 ( .A0(n3017), .A1(n1947), .B0(n1945), .Y(n2634) );
AOI22X1TS U2929 ( .A0(n1948), .A1(add_subt_module_Add_Subt_result[23]), .B0(
add_subt_module_DmP[21]), .B1(n1953), .Y(n1946) );
OAI21X2TS U2930 ( .A0(n3029), .A1(n1947), .B0(n1946), .Y(n2633) );
AOI22X1TS U2931 ( .A0(n1547), .A1(n2634), .B0(n1556), .B1(n2633), .Y(n1960)
);
NAND2X1TS U2932 ( .A(n1948), .B(n3026), .Y(n1950) );
NAND2X1TS U2933 ( .A(n1546), .B(n3027), .Y(n1949) );
INVX2TS U2934 ( .A(n2635), .Y(n1951) );
AOI22X2TS U2935 ( .A0(n1962), .A1(n1952), .B0(n1951), .B1(n1970), .Y(n2080)
);
AOI22X1TS U2936 ( .A0(n1546), .A1(add_subt_module_Add_Subt_result[1]), .B0(
add_subt_module_DmP[22]), .B1(n1953), .Y(n1955) );
OAI2BB1X2TS U2937 ( .A0N(add_subt_module_Add_Subt_result[24]), .A1N(n1956),
.B0(n1955), .Y(n2632) );
AOI2BB2X2TS U2938 ( .B0(n2639), .B1(n1957), .A0N(n2632), .A1N(n2639), .Y(
n2079) );
AOI22X1TS U2939 ( .A0(n1559), .A1(n2080), .B0(n1553), .B1(n2079), .Y(n1959)
);
NAND2X1TS U2940 ( .A(n1968), .B(n2395), .Y(n1958) );
AOI22X2TS U2941 ( .A0(n1962), .A1(n1961), .B0(n2633), .B1(n1970), .Y(n2084)
);
AOI22X1TS U2942 ( .A0(n1559), .A1(n2079), .B0(n1548), .B1(n2080), .Y(n1964)
);
CLKBUFX2TS U2943 ( .A(n1965), .Y(n2032) );
BUFX3TS U2944 ( .A(n2768), .Y(n2063) );
AOI222X1TS U2945 ( .A0(n2770), .A1(d_ff2_Z[30]), .B0(n2032), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2063), .Y(n1966) );
INVX2TS U2946 ( .A(n1966), .Y(n1149) );
AOI222X1TS U2947 ( .A0(n2770), .A1(d_ff2_Z[31]), .B0(n2032), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2063), .Y(n1967) );
INVX2TS U2948 ( .A(n1967), .Y(n1148) );
AOI22X1TS U2949 ( .A0(n1553), .A1(n2080), .B0(n1968), .B1(n1858), .Y(n1969)
);
INVX2TS U2950 ( .A(n2660), .Y(n1972) );
AOI21X1TS U2951 ( .A0(n2667), .A1(n2687), .B0(n1972), .Y(n2658) );
OAI32X1TS U2952 ( .A0(n1563), .A1(n2687), .A2(n2659), .B0(n2658), .B1(n2783),
.Y(n1502) );
INVX2TS U2953 ( .A(n1670), .Y(n2021) );
INVX2TS U2954 ( .A(n1537), .Y(n2027) );
NOR2X2TS U2955 ( .A(n1977), .B(n2011), .Y(n2022) );
AOI21X1TS U2956 ( .A0(n1550), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(
n1976), .Y(n1979) );
AOI22X1TS U2957 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(
n2429), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(
n1978) );
AOI21X1TS U2958 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(
n1980), .Y(n1982) );
AOI22X1TS U2959 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(
n1748), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(
n1981) );
AOI21X1TS U2960 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(
n1983), .Y(n1985) );
AOI22X1TS U2961 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(
n1748), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(
n1984) );
NAND2X1TS U2962 ( .A(n1986), .B(n2017), .Y(n1988) );
AOI22X1TS U2963 ( .A0(n2429), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(
add_subt_module_Sgf_normalized_result[0]), .B1(n2013), .Y(n1987) );
NAND2X1TS U2964 ( .A(n1989), .B(n2017), .Y(n1991) );
AOI22X1TS U2965 ( .A0(n1748), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
add_subt_module_Sgf_normalized_result[1]), .B1(n2013), .Y(n1990) );
AOI21X1TS U2966 ( .A0(n1550), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(
n1992), .Y(n1994) );
AOI22X1TS U2967 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(
n2429), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n1993) );
AOI21X1TS U2968 ( .A0(n1550), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(
n1995), .Y(n1997) );
AOI22X1TS U2969 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
n1748), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(
n1996) );
NAND2X1TS U2970 ( .A(n1538), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(
n2001) );
INVX2TS U2971 ( .A(n1998), .Y(n2428) );
AOI22X1TS U2972 ( .A0(n2017), .A1(n1999), .B0(
add_subt_module_Sgf_normalized_result[14]), .B1(n2428), .Y(n2000) );
NAND2X1TS U2973 ( .A(n1538), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(
n2004) );
AOI22X1TS U2974 ( .A0(n2017), .A1(n2002), .B0(
add_subt_module_Sgf_normalized_result[15]), .B1(n2428), .Y(n2003) );
NAND2X1TS U2975 ( .A(n1538), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n2007) );
AOI22X1TS U2976 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(
n2008), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n2005) );
OAI211X1TS U2977 ( .A0(n3050), .A1(n2012), .B0(n2011), .C0(n2005), .Y(n2423)
);
AOI22X1TS U2978 ( .A0(n2017), .A1(n2423), .B0(
add_subt_module_Sgf_normalized_result[8]), .B1(n2013), .Y(n2006) );
NAND2X1TS U2979 ( .A(n1538), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n2015) );
AOI22X1TS U2980 ( .A0(n2009), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
n2008), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n2010) );
OAI211X1TS U2981 ( .A0(n3051), .A1(n2012), .B0(n2011), .C0(n2010), .Y(n2427)
);
AOI22X1TS U2982 ( .A0(n2017), .A1(n2427), .B0(
add_subt_module_Sgf_normalized_result[9]), .B1(n2013), .Y(n2014) );
NAND2X1TS U2983 ( .A(n1538), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n2019) );
AOI22X1TS U2984 ( .A0(n2017), .A1(n2016), .B0(
add_subt_module_Sgf_normalized_result[13]), .B1(n2428), .Y(n2018) );
AOI21X1TS U2985 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(
n2023), .Y(n2026) );
AOI22X1TS U2986 ( .A0(n2024), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(
n2429), .Y(n2025) );
BUFX3TS U2987 ( .A(n2032), .Y(n2064) );
INVX2TS U2988 ( .A(n2028), .Y(n1154) );
BUFX3TS U2989 ( .A(n2032), .Y(n2059) );
BUFX3TS U2990 ( .A(n2772), .Y(n2058) );
AOI222X1TS U2991 ( .A0(n2060), .A1(d_ff2_Z[14]), .B0(n2059), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2058), .Y(n2029) );
INVX2TS U2992 ( .A(n2029), .Y(n1165) );
INVX2TS U2993 ( .A(n2030), .Y(n1161) );
INVX2TS U2994 ( .A(n2031), .Y(n1156) );
BUFX3TS U2995 ( .A(n2032), .Y(n2055) );
INVX2TS U2996 ( .A(n2033), .Y(n1170) );
INVX2TS U2997 ( .A(n2034), .Y(n1160) );
BUFX3TS U2998 ( .A(n2772), .Y(n2732) );
AOI222X1TS U2999 ( .A0(n2060), .A1(d_ff2_Z[6]), .B0(n2055), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2732), .Y(n2035) );
INVX2TS U3000 ( .A(n2035), .Y(n1173) );
INVX2TS U3001 ( .A(n2036), .Y(n1175) );
INVX2TS U3002 ( .A(n2037), .Y(n1178) );
AOI222X1TS U3003 ( .A0(n2060), .A1(d_ff2_Z[11]), .B0(n2059), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2058), .Y(n2038) );
INVX2TS U3004 ( .A(n2038), .Y(n1168) );
INVX2TS U3005 ( .A(n2039), .Y(n1176) );
INVX2TS U3006 ( .A(n2040), .Y(n1151) );
INVX2TS U3007 ( .A(n2041), .Y(n1164) );
AOI222X1TS U3008 ( .A0(n2060), .A1(d_ff2_Z[8]), .B0(n2055), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2058), .Y(n2042) );
INVX2TS U3009 ( .A(n2042), .Y(n1171) );
AOI222X1TS U3010 ( .A0(n2060), .A1(d_ff2_Z[21]), .B0(n2064), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2063), .Y(n2043) );
INVX2TS U3011 ( .A(n2043), .Y(n1158) );
INVX2TS U3012 ( .A(n2044), .Y(n1155) );
INVX2TS U3013 ( .A(n2045), .Y(n1179) );
AOI222X1TS U3014 ( .A0(n2060), .A1(d_ff2_Z[27]), .B0(n2064), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2768), .Y(n2046) );
INVX2TS U3015 ( .A(n2046), .Y(n1152) );
INVX2TS U3016 ( .A(n2047), .Y(n1172) );
INVX2TS U3017 ( .A(n2048), .Y(n1150) );
AOI222X1TS U3018 ( .A0(n2060), .A1(d_ff2_Z[16]), .B0(n2059), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2058), .Y(n2049) );
INVX2TS U3019 ( .A(n2049), .Y(n1163) );
AOI222X1TS U3020 ( .A0(n2060), .A1(d_ff2_Z[12]), .B0(n2059), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2058), .Y(n2050) );
INVX2TS U3021 ( .A(n2050), .Y(n1167) );
INVX2TS U3022 ( .A(n2051), .Y(n1162) );
AOI222X1TS U3023 ( .A0(n2060), .A1(d_ff2_Z[13]), .B0(n2059), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2058), .Y(n2052) );
INVX2TS U3024 ( .A(n2052), .Y(n1166) );
INVX2TS U3025 ( .A(n2053), .Y(n1153) );
INVX2TS U3026 ( .A(n2054), .Y(n1177) );
INVX2TS U3027 ( .A(n2057), .Y(n1174) );
AOI222X1TS U3028 ( .A0(n2060), .A1(d_ff2_Z[10]), .B0(n2059), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2058), .Y(n2061) );
INVX2TS U3029 ( .A(n2061), .Y(n1169) );
INVX2TS U3030 ( .A(n2062), .Y(n1159) );
AOI222X1TS U3031 ( .A0(n2065), .A1(d_ff2_Z[22]), .B0(n2064), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2063), .Y(n2066) );
INVX2TS U3032 ( .A(n2066), .Y(n1157) );
AOI2BB2X2TS U3033 ( .B0(n2639), .B1(n2067), .A0N(n2634), .A1N(n2639), .Y(
n2078) );
AOI22X1TS U3034 ( .A0(n1560), .A1(n2078), .B0(n1552), .B1(n2075), .Y(n2069)
);
NAND2X1TS U3035 ( .A(n1556), .B(n2079), .Y(n2068) );
AOI22X1TS U3036 ( .A0(n1560), .A1(n2074), .B0(n1547), .B1(n2075), .Y(n2072)
);
NAND2X1TS U3037 ( .A(n1555), .B(n2078), .Y(n2071) );
AOI22X1TS U3038 ( .A0(n1559), .A1(n2075), .B0(n1552), .B1(n2074), .Y(n2077)
);
NAND2X1TS U3039 ( .A(n1548), .B(n2078), .Y(n2076) );
AOI22X1TS U3040 ( .A0(n1548), .A1(n2079), .B0(n1553), .B1(n2078), .Y(n2082)
);
NAND2X1TS U3041 ( .A(n1556), .B(n2080), .Y(n2081) );
NOR4X1TS U3042 ( .A(n2091), .B(n2090), .C(n2089), .D(n2088), .Y(n2092) );
AOI22X1TS U3043 ( .A0(add_subt_module_intDX[25]), .A1(n3004), .B0(
add_subt_module_intDX[24]), .B1(n2093), .Y(n2097) );
OAI21X1TS U3044 ( .A0(add_subt_module_intDX[26]), .A1(n3016), .B0(n2094),
.Y(n2153) );
AOI211X1TS U3045 ( .A0(add_subt_module_intDY[28]), .A1(n2993), .B0(n2100),
.C0(n2098), .Y(n2151) );
NOR3X1TS U3046 ( .A(n2993), .B(n2098), .C(add_subt_module_intDY[28]), .Y(
n2099) );
NOR2X1TS U3047 ( .A(n2998), .B(add_subt_module_intDX[17]), .Y(n2138) );
NOR2X1TS U3048 ( .A(n2979), .B(add_subt_module_intDX[11]), .Y(n2117) );
AOI21X1TS U3049 ( .A0(add_subt_module_intDY[10]), .A1(n3005), .B0(n2117),
.Y(n2122) );
OAI2BB1X1TS U3050 ( .A0N(n2970), .A1N(add_subt_module_intDY[5]), .B0(
add_subt_module_intDX[4]), .Y(n2103) );
OAI22X1TS U3051 ( .A0(add_subt_module_intDY[4]), .A1(n2103), .B0(n2970),
.B1(add_subt_module_intDY[5]), .Y(n2114) );
OAI2BB1X1TS U3052 ( .A0N(n2969), .A1N(add_subt_module_intDY[7]), .B0(
add_subt_module_intDX[6]), .Y(n2104) );
OAI22X1TS U3053 ( .A0(add_subt_module_intDY[6]), .A1(n2104), .B0(n2969),
.B1(add_subt_module_intDY[7]), .Y(n2113) );
OAI2BB2XLTS U3054 ( .B0(add_subt_module_intDY[0]), .B1(n2105), .A0N(
add_subt_module_intDX[1]), .A1N(n1561), .Y(n2107) );
AOI22X1TS U3055 ( .A0(add_subt_module_intDY[7]), .A1(n2969), .B0(
add_subt_module_intDY[6]), .B1(n3021), .Y(n2111) );
OA22X1TS U3056 ( .A0(n2976), .A1(add_subt_module_intDX[14]), .B0(n2956),
.B1(add_subt_module_intDX[15]), .Y(n2129) );
AOI22X1TS U3057 ( .A0(add_subt_module_intDX[11]), .A1(n2979), .B0(
add_subt_module_intDX[10]), .B1(n2118), .Y(n2124) );
AOI21X1TS U3058 ( .A0(n2121), .A1(n2120), .B0(n2131), .Y(n2123) );
OAI2BB2XLTS U3059 ( .B0(add_subt_module_intDY[14]), .B1(n2125), .A0N(
add_subt_module_intDX[15]), .A1N(n2956), .Y(n2126) );
AOI211X1TS U3060 ( .A0(n2129), .A1(n2128), .B0(n2127), .C0(n2126), .Y(n2130)
);
OAI31X1TS U3061 ( .A0(n2133), .A1(n2132), .A2(n2131), .B0(n2130), .Y(n2136)
);
OA22X1TS U3062 ( .A0(n2966), .A1(add_subt_module_intDX[22]), .B0(n3015),
.B1(add_subt_module_intDX[23]), .Y(n2149) );
OAI21X1TS U3063 ( .A0(add_subt_module_intDX[18]), .A1(n2999), .B0(n2140),
.Y(n2144) );
OAI2BB2XLTS U3064 ( .B0(add_subt_module_intDY[20]), .B1(n2137), .A0N(
add_subt_module_intDX[21]), .A1N(n2997), .Y(n2148) );
AOI22X1TS U3065 ( .A0(add_subt_module_intDX[17]), .A1(n2998), .B0(
add_subt_module_intDX[16]), .B1(n2139), .Y(n2142) );
AOI32X1TS U3066 ( .A0(n2999), .A1(n2140), .A2(add_subt_module_intDX[18]),
.B0(add_subt_module_intDX[19]), .B1(n2967), .Y(n2141) );
OAI32X1TS U3067 ( .A0(n2144), .A1(n2143), .A2(n2142), .B0(n2141), .B1(n2143),
.Y(n2147) );
OAI2BB2XLTS U3068 ( .B0(add_subt_module_intDY[22]), .B1(n2145), .A0N(
add_subt_module_intDX[23]), .A1N(n3015), .Y(n2146) );
AOI211X1TS U3069 ( .A0(n2149), .A1(n2148), .B0(n2147), .C0(n2146), .Y(n2155)
);
NAND4BBX1TS U3070 ( .AN(n2153), .BN(n2152), .C(n2151), .D(n2150), .Y(n2154)
);
BUFX3TS U3071 ( .A(n2166), .Y(n2185) );
INVX2TS U3072 ( .A(n2185), .Y(n2160) );
AOI22X1TS U3073 ( .A0(add_subt_module_DmP[12]), .A1(n2227), .B0(
add_subt_module_intDX[12]), .B1(n1539), .Y(n2159) );
BUFX3TS U3074 ( .A(n2166), .Y(n2218) );
AOI22X1TS U3075 ( .A0(add_subt_module_DmP[14]), .A1(n2238), .B0(
add_subt_module_intDY[14]), .B1(n2218), .Y(n2161) );
AOI22X1TS U3076 ( .A0(add_subt_module_DmP[11]), .A1(n2224), .B0(
add_subt_module_intDY[11]), .B1(n2218), .Y(n2162) );
BUFX3TS U3077 ( .A(n1541), .Y(n2226) );
INVX2TS U3078 ( .A(n2085), .Y(n2213) );
AOI22X1TS U3079 ( .A0(n2166), .A1(add_subt_module_intDY[23]), .B0(
add_subt_module_DmP[23]), .B1(n2213), .Y(n2163) );
AOI22X1TS U3080 ( .A0(n2166), .A1(add_subt_module_intDX[23]), .B0(
add_subt_module_DMP[23]), .B1(n2238), .Y(n2164) );
INVX2TS U3081 ( .A(n2085), .Y(n2211) );
AOI22X1TS U3082 ( .A0(n2229), .A1(add_subt_module_intDX[28]), .B0(
add_subt_module_DMP[28]), .B1(n2213), .Y(n2165) );
AOI22X1TS U3083 ( .A0(add_subt_module_DmP[19]), .A1(n2224), .B0(
add_subt_module_intDY[19]), .B1(n2166), .Y(n2167) );
AOI22X1TS U3084 ( .A0(add_subt_module_DmP[3]), .A1(n2238), .B0(
add_subt_module_intDY[3]), .B1(n2166), .Y(n2168) );
AOI22X1TS U3085 ( .A0(add_subt_module_DmP[15]), .A1(n2238), .B0(
add_subt_module_intDY[15]), .B1(n2229), .Y(n2169) );
AOI22X1TS U3086 ( .A0(add_subt_module_DmP[18]), .A1(n2224), .B0(
add_subt_module_intDY[18]), .B1(n2185), .Y(n2170) );
AOI22X1TS U3087 ( .A0(add_subt_module_DmP[21]), .A1(n2238), .B0(
add_subt_module_intDY[21]), .B1(n2229), .Y(n2171) );
AOI22X1TS U3088 ( .A0(add_subt_module_DmP[22]), .A1(n2241), .B0(
add_subt_module_intDY[22]), .B1(n2229), .Y(n2172) );
AOI22X1TS U3089 ( .A0(add_subt_module_DmP[17]), .A1(n2227), .B0(
add_subt_module_intDY[17]), .B1(n2166), .Y(n2173) );
AOI22X1TS U3090 ( .A0(n2242), .A1(add_subt_module_intDY[5]), .B0(
add_subt_module_DMP[5]), .B1(n2241), .Y(n2174) );
AOI22X1TS U3091 ( .A0(add_subt_module_DmP[8]), .A1(n2227), .B0(
add_subt_module_intDY[8]), .B1(n2166), .Y(n2175) );
AOI22X1TS U3092 ( .A0(n2166), .A1(add_subt_module_intDX[24]), .B0(
add_subt_module_DMP[24]), .B1(n2213), .Y(n2176) );
INVX2TS U3093 ( .A(n2085), .Y(n2204) );
AOI22X1TS U3094 ( .A0(n2218), .A1(add_subt_module_intDX[12]), .B0(
add_subt_module_DMP[12]), .B1(n2213), .Y(n2177) );
AOI22X1TS U3095 ( .A0(n2218), .A1(add_subt_module_intDX[30]), .B0(
add_subt_module_DMP[30]), .B1(n2211), .Y(n2178) );
AOI22X1TS U3096 ( .A0(add_subt_module_DmP[13]), .A1(n2227), .B0(
add_subt_module_intDY[13]), .B1(n2185), .Y(n2179) );
AOI22X1TS U3097 ( .A0(add_subt_module_DmP[20]), .A1(n2238), .B0(
add_subt_module_intDY[20]), .B1(n2218), .Y(n2180) );
AOI22X1TS U3098 ( .A0(n2242), .A1(n2181), .B0(n2085), .B1(
add_subt_module_intDX[31]), .Y(n2184) );
AOI22X1TS U3099 ( .A0(n2229), .A1(add_subt_module_intDX[31]), .B0(
add_subt_module_sign_final_result), .B1(n2224), .Y(n2182) );
AOI22X1TS U3100 ( .A0(n2205), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_DMP[16]), .B1(n2213), .Y(n2186) );
AOI22X1TS U3101 ( .A0(add_subt_module_DmP[0]), .A1(n2241), .B0(
add_subt_module_intDX[0]), .B1(n1539), .Y(n2187) );
AOI22X1TS U3102 ( .A0(n2236), .A1(add_subt_module_intDX[28]), .B0(
add_subt_module_DmP[28]), .B1(n2211), .Y(n2188) );
AOI22X1TS U3103 ( .A0(n2236), .A1(add_subt_module_intDX[29]), .B0(
add_subt_module_DmP[29]), .B1(n2204), .Y(n2189) );
AOI22X1TS U3104 ( .A0(n2236), .A1(add_subt_module_intDX[26]), .B0(
add_subt_module_DmP[26]), .B1(n2213), .Y(n2190) );
AOI22X1TS U3105 ( .A0(n2236), .A1(add_subt_module_intDX[25]), .B0(
add_subt_module_DmP[25]), .B1(n2211), .Y(n2191) );
AOI22X1TS U3106 ( .A0(n2205), .A1(add_subt_module_intDX[30]), .B0(
add_subt_module_DmP[30]), .B1(n2204), .Y(n2192) );
AOI22X1TS U3107 ( .A0(n2236), .A1(add_subt_module_intDX[27]), .B0(
add_subt_module_DmP[27]), .B1(n2204), .Y(n2193) );
AOI22X1TS U3108 ( .A0(n2236), .A1(add_subt_module_intDY[19]), .B0(
add_subt_module_DMP[19]), .B1(n2241), .Y(n2194) );
AOI22X1TS U3109 ( .A0(n2205), .A1(add_subt_module_intDY[14]), .B0(
add_subt_module_DMP[14]), .B1(n2204), .Y(n2195) );
AOI22X1TS U3110 ( .A0(n2205), .A1(add_subt_module_intDY[13]), .B0(
add_subt_module_DMP[13]), .B1(n2213), .Y(n2196) );
AOI22X1TS U3111 ( .A0(n2205), .A1(add_subt_module_intDY[21]), .B0(
add_subt_module_DMP[21]), .B1(n2211), .Y(n2197) );
AOI22X1TS U3112 ( .A0(n2205), .A1(add_subt_module_intDY[18]), .B0(
add_subt_module_DMP[18]), .B1(n2204), .Y(n2198) );
AOI22X1TS U3113 ( .A0(n2205), .A1(add_subt_module_intDY[15]), .B0(
add_subt_module_DMP[15]), .B1(n2213), .Y(n2199) );
AOI22X1TS U3114 ( .A0(n2205), .A1(add_subt_module_intDY[17]), .B0(
add_subt_module_DMP[17]), .B1(n2211), .Y(n2200) );
AOI22X1TS U3115 ( .A0(n2205), .A1(add_subt_module_intDY[20]), .B0(
add_subt_module_DMP[20]), .B1(n2211), .Y(n2201) );
AOI22X1TS U3116 ( .A0(n2236), .A1(add_subt_module_intDX[24]), .B0(
add_subt_module_DmP[24]), .B1(n2211), .Y(n2203) );
AOI22X1TS U3117 ( .A0(n2205), .A1(add_subt_module_intDY[11]), .B0(
add_subt_module_DMP[11]), .B1(n2213), .Y(n2206) );
AOI22X1TS U3118 ( .A0(n2236), .A1(add_subt_module_intDY[22]), .B0(
add_subt_module_DMP[22]), .B1(n2204), .Y(n2207) );
AOI22X1TS U3119 ( .A0(n2229), .A1(add_subt_module_intDX[27]), .B0(
add_subt_module_DMP[27]), .B1(n2211), .Y(n2209) );
AOI22X1TS U3120 ( .A0(n2229), .A1(add_subt_module_intDX[26]), .B0(
add_subt_module_DMP[26]), .B1(n2204), .Y(n2210) );
AOI22X1TS U3121 ( .A0(n2229), .A1(add_subt_module_intDX[29]), .B0(
add_subt_module_DMP[29]), .B1(n2204), .Y(n2212) );
AOI22X1TS U3122 ( .A0(n2229), .A1(add_subt_module_intDX[25]), .B0(
add_subt_module_DMP[25]), .B1(n2211), .Y(n2214) );
AOI22X1TS U3123 ( .A0(add_subt_module_DmP[9]), .A1(n2241), .B0(
add_subt_module_intDY[9]), .B1(n2218), .Y(n2215) );
AOI22X1TS U3124 ( .A0(add_subt_module_DmP[10]), .A1(n2227), .B0(
add_subt_module_intDY[10]), .B1(n2218), .Y(n2216) );
AOI22X1TS U3125 ( .A0(add_subt_module_DmP[16]), .A1(n2238), .B0(
add_subt_module_intDY[16]), .B1(n2218), .Y(n2217) );
AOI22X1TS U3126 ( .A0(add_subt_module_DmP[7]), .A1(n2224), .B0(
add_subt_module_intDY[7]), .B1(n2218), .Y(n2219) );
AOI22X1TS U3127 ( .A0(add_subt_module_DmP[1]), .A1(n2224), .B0(
add_subt_module_intDY[1]), .B1(n2185), .Y(n2220) );
AOI22X1TS U3128 ( .A0(add_subt_module_DmP[2]), .A1(n2227), .B0(
add_subt_module_intDY[2]), .B1(n2185), .Y(n2221) );
AOI22X1TS U3129 ( .A0(add_subt_module_DmP[4]), .A1(n2224), .B0(
add_subt_module_intDY[4]), .B1(n2185), .Y(n2223) );
AOI22X1TS U3130 ( .A0(add_subt_module_DmP[6]), .A1(n2238), .B0(
add_subt_module_intDY[6]), .B1(n2185), .Y(n2225) );
AOI22X1TS U3131 ( .A0(add_subt_module_DmP[5]), .A1(n2238), .B0(
add_subt_module_intDY[5]), .B1(n2218), .Y(n2228) );
AOI22X1TS U3132 ( .A0(n2236), .A1(add_subt_module_intDY[0]), .B0(
add_subt_module_DMP[0]), .B1(n2241), .Y(n2230) );
AOI22X1TS U3133 ( .A0(n2242), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_DMP[4]), .B1(n2224), .Y(n2231) );
AOI22X1TS U3134 ( .A0(n2242), .A1(add_subt_module_intDY[10]), .B0(
add_subt_module_DMP[10]), .B1(n2227), .Y(n2232) );
AOI22X1TS U3135 ( .A0(n2242), .A1(add_subt_module_intDY[6]), .B0(
add_subt_module_DMP[6]), .B1(n2227), .Y(n2233) );
AOI22X1TS U3136 ( .A0(n2242), .A1(add_subt_module_intDY[7]), .B0(
add_subt_module_DMP[7]), .B1(n2227), .Y(n2234) );
AOI22X1TS U3137 ( .A0(n2242), .A1(add_subt_module_intDY[2]), .B0(
add_subt_module_DMP[2]), .B1(n2227), .Y(n2235) );
AOI22X1TS U3138 ( .A0(n2236), .A1(add_subt_module_intDY[1]), .B0(
add_subt_module_DMP[1]), .B1(n2224), .Y(n2237) );
AOI22X1TS U3139 ( .A0(n2242), .A1(add_subt_module_intDY[3]), .B0(
add_subt_module_DMP[3]), .B1(n2241), .Y(n2239) );
AOI22X1TS U3140 ( .A0(n2242), .A1(add_subt_module_intDY[8]), .B0(
add_subt_module_DMP[8]), .B1(n2224), .Y(n2240) );
AOI22X1TS U3141 ( .A0(n2242), .A1(add_subt_module_intDY[9]), .B0(
add_subt_module_DMP[9]), .B1(n2238), .Y(n2243) );
NAND2X1TS U3142 ( .A(n2245), .B(n3030), .Y(n2251) );
NOR2X1TS U3143 ( .A(add_subt_module_Add_Subt_result[3]), .B(
add_subt_module_Add_Subt_result[2]), .Y(n2247) );
AOI211X1TS U3144 ( .A0(n2252), .A1(n2251), .B0(n2250), .C0(n2445), .Y(n2256)
);
INVX2TS U3145 ( .A(n1687), .Y(n2740) );
CLKBUFX2TS U3146 ( .A(n2740), .Y(n2749) );
INVX2TS U3147 ( .A(n1542), .Y(n2265) );
OAI211XLTS U3148 ( .A0(n2258), .A1(add_subt_module_FS_Module_state_reg[1]),
.B0(n2257), .C0(n2456), .Y(n2261) );
INVX2TS U3149 ( .A(n2259), .Y(n2260) );
AOI21X1TS U3150 ( .A0(n2267), .A1(n2981), .B0(n2266), .Y(n2268) );
AOI22X1TS U3151 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n2271), .B0(
add_subt_module_Add_Subt_result[3]), .B1(n2270), .Y(n2273) );
AOI22X1TS U3152 ( .A0(d_ff2_Y[31]), .A1(n2831), .B0(n2822), .B1(d_ff2_X[31]),
.Y(n2278) );
AOI22X1TS U3153 ( .A0(n2950), .A1(d_ff2_Z[31]), .B0(
add_subt_module_intDX[31]), .B1(n2817), .Y(n2277) );
NAND2X1TS U3154 ( .A(n2278), .B(n2277), .Y(n1003) );
XNOR2X1TS U3155 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(n2279) );
OR2X6TS U3156 ( .A(n2280), .B(add_subt_module_FSM_selector_D), .Y(n2437) );
NOR2X1TS U3157 ( .A(n2388), .B(n2281), .Y(n2288) );
INVX2TS U3158 ( .A(n3001), .Y(n2385) );
NOR2BX1TS U3159 ( .AN(add_subt_module_Sgf_normalized_result[0]), .B(n2385),
.Y(n2282) );
XOR2X1TS U3160 ( .A(n2388), .B(n2282), .Y(n2287) );
XNOR2X1TS U3161 ( .A(n2288), .B(n2287), .Y(n2283) );
BUFX3TS U3162 ( .A(n2502), .Y(n2492) );
INVX4TS U3163 ( .A(n2437), .Y(n2312) );
XOR2X1TS U3164 ( .A(n2312), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(n2285) );
NOR2X2TS U3165 ( .A(n2285), .B(n2284), .Y(n2465) );
OR2X1TS U3166 ( .A(add_subt_module_FSM_selector_D), .B(
add_subt_module_Sgf_normalized_result[2]), .Y(n2286) );
XOR2X1TS U3167 ( .A(n2312), .B(n2286), .Y(n2291) );
NOR2X1TS U3168 ( .A(n2291), .B(n2290), .Y(n2467) );
NOR2X1TS U3169 ( .A(n2465), .B(n2467), .Y(n2293) );
INVX2TS U3170 ( .A(n2287), .Y(n2289) );
NOR2X1TS U3171 ( .A(n2289), .B(n2288), .Y(n2457) );
NAND2X1TS U3172 ( .A(n2291), .B(n2290), .Y(n2468) );
INVX2TS U3173 ( .A(n2468), .Y(n2292) );
AOI21X2TS U3174 ( .A0(n2293), .A1(n2457), .B0(n2292), .Y(n2478) );
NOR2BX1TS U3175 ( .AN(add_subt_module_Sgf_normalized_result[3]), .B(n2386),
.Y(n2294) );
XOR2X1TS U3176 ( .A(n2312), .B(n2294), .Y(n2299) );
INVX4TS U3177 ( .A(n3001), .Y(n2317) );
NOR2X1TS U3178 ( .A(n2299), .B(n2298), .Y(n2479) );
NOR2BX1TS U3179 ( .AN(add_subt_module_Sgf_normalized_result[4]), .B(n2385),
.Y(n2295) );
XOR2X1TS U3180 ( .A(n2312), .B(n2295), .Y(n2301) );
NOR2BX1TS U3181 ( .AN(add_subt_module_Sgf_normalized_result[5]), .B(n2385),
.Y(n2296) );
XOR2X1TS U3182 ( .A(n2312), .B(n2296), .Y(n2303) );
NOR2X2TS U3183 ( .A(n2303), .B(n2302), .Y(n2517) );
NOR2BX1TS U3184 ( .AN(add_subt_module_Sgf_normalized_result[6]), .B(n2386),
.Y(n2297) );
XOR2X1TS U3185 ( .A(n2312), .B(n2297), .Y(n2305) );
NOR2X2TS U3186 ( .A(n2305), .B(n2304), .Y(n2519) );
NAND2X2TS U3187 ( .A(n2299), .B(n2298), .Y(n2494) );
NAND2X1TS U3188 ( .A(n2301), .B(n2300), .Y(n2498) );
OAI21X1TS U3189 ( .A0(n2497), .A1(n2494), .B0(n2498), .Y(n2510) );
NAND2X1TS U3190 ( .A(n2303), .B(n2302), .Y(n2516) );
NAND2X1TS U3191 ( .A(n2305), .B(n2304), .Y(n2520) );
OAI21X1TS U3192 ( .A0(n2519), .A1(n2516), .B0(n2520), .Y(n2306) );
AOI21X2TS U3193 ( .A0(n2510), .A1(n2307), .B0(n2306), .Y(n2308) );
OAI21X4TS U3194 ( .A0(n2478), .A1(n2309), .B0(n2308), .Y(n2536) );
NOR2BX1TS U3195 ( .AN(add_subt_module_Sgf_normalized_result[7]), .B(n2386),
.Y(n2310) );
XOR2X1TS U3196 ( .A(n2312), .B(n2310), .Y(n2321) );
NOR2X2TS U3197 ( .A(n2321), .B(n2320), .Y(n2546) );
NOR2BX1TS U3198 ( .AN(add_subt_module_Sgf_normalized_result[8]), .B(n2386),
.Y(n2311) );
XOR2X1TS U3199 ( .A(n2312), .B(n2311), .Y(n2323) );
NOR2X2TS U3200 ( .A(n2323), .B(n2322), .Y(n2547) );
INVX8TS U3201 ( .A(n2437), .Y(n2368) );
NOR2BX1TS U3202 ( .AN(add_subt_module_Sgf_normalized_result[9]), .B(n2386),
.Y(n2313) );
XOR2X1TS U3203 ( .A(n2368), .B(n2313), .Y(n2325) );
NOR2BX1TS U3204 ( .AN(add_subt_module_Sgf_normalized_result[10]), .B(n2386),
.Y(n2314) );
XOR2X1TS U3205 ( .A(n2368), .B(n2314), .Y(n2327) );
NOR2X2TS U3206 ( .A(n2327), .B(n2326), .Y(n2572) );
NOR2BX1TS U3207 ( .AN(add_subt_module_Sgf_normalized_result[11]), .B(n2386),
.Y(n2315) );
XOR2X1TS U3208 ( .A(n2368), .B(n2316), .Y(n2333) );
NOR2X2TS U3209 ( .A(n2333), .B(n2332), .Y(n2610) );
XOR2X1TS U3210 ( .A(n2368), .B(n2318), .Y(n2335) );
INVX4TS U3211 ( .A(n3001), .Y(n2373) );
NOR2X1TS U3212 ( .A(n2335), .B(n2334), .Y(n2589) );
XOR2X1TS U3213 ( .A(n2368), .B(n2319), .Y(n2337) );
NOR2X2TS U3214 ( .A(n2337), .B(n2336), .Y(n2591) );
NOR2X2TS U3215 ( .A(n2583), .B(n2341), .Y(n2343) );
NAND2X2TS U3216 ( .A(n2321), .B(n2320), .Y(n2545) );
NAND2X1TS U3217 ( .A(n2323), .B(n2322), .Y(n2548) );
OAI21X1TS U3218 ( .A0(n2547), .A1(n2545), .B0(n2548), .Y(n2562) );
NAND2X1TS U3219 ( .A(n2325), .B(n2324), .Y(n2568) );
NAND2X1TS U3220 ( .A(n2327), .B(n2326), .Y(n2573) );
OAI21X1TS U3221 ( .A0(n2572), .A1(n2568), .B0(n2573), .Y(n2328) );
AOI21X2TS U3222 ( .A0(n2562), .A1(n2329), .B0(n2328), .Y(n2582) );
NAND2X1TS U3223 ( .A(n2333), .B(n2332), .Y(n2611) );
OAI21X1TS U3224 ( .A0(n2610), .A1(n2606), .B0(n2611), .Y(n2586) );
NAND2X1TS U3225 ( .A(n2335), .B(n2334), .Y(n2601) );
NAND2X1TS U3226 ( .A(n2337), .B(n2336), .Y(n2592) );
AOI21X1TS U3227 ( .A0(n2586), .A1(n2339), .B0(n2338), .Y(n2340) );
OAI21X2TS U3228 ( .A0(n2582), .A1(n2341), .B0(n2340), .Y(n2342) );
AOI21X4TS U3229 ( .A0(n2536), .A1(n2343), .B0(n2342), .Y(n2553) );
XOR2X1TS U3230 ( .A(n2368), .B(n2344), .Y(n2347) );
XOR2X1TS U3231 ( .A(n2368), .B(n2345), .Y(n2349) );
NAND2X1TS U3232 ( .A(n1567), .B(n2556), .Y(n2352) );
NAND2X1TS U3233 ( .A(n2347), .B(n2346), .Y(n2578) );
INVX2TS U3234 ( .A(n2578), .Y(n2554) );
NAND2X1TS U3235 ( .A(n2349), .B(n2348), .Y(n2555) );
INVX2TS U3236 ( .A(n2555), .Y(n2350) );
AOI21X1TS U3237 ( .A0(n2556), .A1(n2554), .B0(n2350), .Y(n2351) );
OAI21X4TS U3238 ( .A0(n2553), .A1(n2352), .B0(n2351), .Y(n2543) );
XOR2X1TS U3239 ( .A(n2368), .B(n2353), .Y(n2355) );
NAND2X1TS U3240 ( .A(n2355), .B(n2354), .Y(n2540) );
INVX2TS U3241 ( .A(n2540), .Y(n2356) );
AOI21X4TS U3242 ( .A0(n2543), .A1(n2541), .B0(n2356), .Y(n2534) );
XOR2X1TS U3243 ( .A(n2388), .B(n2357), .Y(n2359) );
NOR2X1TS U3244 ( .A(n2359), .B(n2358), .Y(n2530) );
NAND2X1TS U3245 ( .A(n2359), .B(n2358), .Y(n2531) );
OAI21X4TS U3246 ( .A0(n2534), .A1(n2530), .B0(n2531), .Y(n2528) );
XOR2X1TS U3247 ( .A(n2388), .B(n2360), .Y(n2362) );
NAND2X1TS U3248 ( .A(n2362), .B(n2361), .Y(n2525) );
INVX2TS U3249 ( .A(n2525), .Y(n2363) );
AOI21X4TS U3250 ( .A0(n2528), .A1(n2526), .B0(n2363), .Y(n2508) );
XOR2X1TS U3251 ( .A(n2388), .B(n2364), .Y(n2366) );
NOR2X1TS U3252 ( .A(n2366), .B(n2365), .Y(n2504) );
NAND2X1TS U3253 ( .A(n2366), .B(n2365), .Y(n2505) );
OAI21X4TS U3254 ( .A0(n2508), .A1(n2504), .B0(n2505), .Y(n2491) );
XOR2X1TS U3255 ( .A(n2368), .B(n2367), .Y(n2370) );
NAND2X1TS U3256 ( .A(n2370), .B(n2369), .Y(n2488) );
INVX2TS U3257 ( .A(n2488), .Y(n2371) );
AOI21X4TS U3258 ( .A0(n2491), .A1(n2489), .B0(n2371), .Y(n2486) );
XOR2X1TS U3259 ( .A(n2388), .B(n2372), .Y(n2375) );
NOR2X1TS U3260 ( .A(n2375), .B(n2374), .Y(n2482) );
NAND2X1TS U3261 ( .A(n2375), .B(n2374), .Y(n2483) );
OAI21X4TS U3262 ( .A0(n2486), .A1(n2482), .B0(n2483), .Y(n2476) );
XOR2X1TS U3263 ( .A(n2388), .B(n2376), .Y(n2379) );
INVX2TS U3264 ( .A(n3001), .Y(n2377) );
NAND2X1TS U3265 ( .A(n2379), .B(n2378), .Y(n2473) );
INVX2TS U3266 ( .A(n2473), .Y(n2380) );
AOI21X4TS U3267 ( .A0(n2476), .A1(n2474), .B0(n2380), .Y(n2463) );
XOR2X1TS U3268 ( .A(n2388), .B(n2381), .Y(n2384) );
NOR2X1TS U3269 ( .A(n2384), .B(n2383), .Y(n2459) );
NAND2X1TS U3270 ( .A(n2384), .B(n2383), .Y(n2460) );
NOR2BX1TS U3271 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n2386),
.Y(n2387) );
XOR2X1TS U3272 ( .A(n2388), .B(n2387), .Y(n2434) );
INVX2TS U3273 ( .A(n2434), .Y(n2389) );
NAND2X1TS U3274 ( .A(n2435), .B(n2389), .Y(n2390) );
XNOR2X1TS U3275 ( .A(n2436), .B(n2390), .Y(n2391) );
NAND2X1TS U3276 ( .A(n2635), .B(n2392), .Y(n2394) );
OAI22X1TS U3277 ( .A0(n1858), .A1(n2394), .B0(n2393), .B1(n2637), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U3278 ( .A0(n1559), .A1(n2635), .B0(n1553), .B1(n2632), .Y(n2397)
);
OAI22X1TS U3279 ( .A0(n2397), .A1(n2636), .B0(n2396), .B1(n2637), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
INVX2TS U3280 ( .A(n2398), .Y(n2421) );
NAND2X2TS U3281 ( .A(n1670), .B(n2399), .Y(n2419) );
AOI21X1TS U3282 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n1538), .B0(n2416), .Y(n2401) );
AOI22X1TS U3283 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(
n1549), .B0(add_subt_module_Sgf_normalized_result[23]), .B1(n2403),
.Y(n2400) );
AOI21X1TS U3284 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n1537), .B0(n2416), .Y(n2405) );
AOI22X1TS U3285 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n1549), .B0(add_subt_module_Sgf_normalized_result[22]), .B1(n2403),
.Y(n2404) );
AOI21X1TS U3286 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(
n1538), .B0(n2416), .Y(n2408) );
AOI22X1TS U3287 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1549), .B0(add_subt_module_Sgf_normalized_result[21]), .B1(n2428),
.Y(n2407) );
AOI21X1TS U3288 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n1537), .B0(n2416), .Y(n2411) );
AOI22X1TS U3289 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1549), .B0(add_subt_module_Sgf_normalized_result[20]), .B1(n2428),
.Y(n2410) );
AOI21X1TS U3290 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(
n1538), .B0(n2416), .Y(n2414) );
AOI22X1TS U3291 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1550), .B0(add_subt_module_Sgf_normalized_result[19]), .B1(n2428),
.Y(n2413) );
AOI21X1TS U3292 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1550), .B0(n2416), .Y(n2418) );
AOI22X1TS U3293 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n1537), .B0(add_subt_module_Sgf_normalized_result[18]), .B1(n2428),
.Y(n2417) );
INVX2TS U3294 ( .A(n2422), .Y(n2433) );
NAND2X1TS U3295 ( .A(n1670), .B(n2423), .Y(n2426) );
AOI22X1TS U3296 ( .A0(n1551), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
add_subt_module_Sgf_normalized_result[17]), .B1(n2428), .Y(n2425) );
NAND2X1TS U3297 ( .A(n1748), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(
n2424) );
NAND2X1TS U3298 ( .A(n1670), .B(n2427), .Y(n2432) );
AOI22X1TS U3299 ( .A0(n1550), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
add_subt_module_Sgf_normalized_result[16]), .B1(n2428), .Y(n2431) );
NAND2X1TS U3300 ( .A(n2429), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .Y(
n2430) );
XOR2X1TS U3301 ( .A(n2438), .B(n2437), .Y(n2439) );
MXI2X1TS U3302 ( .A(n2980), .B(add_subt_module_add_overflow_flag), .S0(n2440), .Y(n1369) );
AOI211X1TS U3303 ( .A0(n2448), .A1(n2447), .B0(n2446), .C0(n2445), .Y(n2450)
);
XOR2X1TS U3304 ( .A(n2465), .B(n2466), .Y(n2458) );
INVX2TS U3305 ( .A(n2459), .Y(n2461) );
NAND2X1TS U3306 ( .A(n2461), .B(n2460), .Y(n2462) );
XOR2X1TS U3307 ( .A(n2463), .B(n2462), .Y(n2464) );
INVX2TS U3308 ( .A(n2467), .Y(n2469) );
NAND2X1TS U3309 ( .A(n2469), .B(n2468), .Y(n2470) );
XNOR2X1TS U3310 ( .A(n2471), .B(n2470), .Y(n2472) );
NAND2X1TS U3311 ( .A(n2474), .B(n2473), .Y(n2475) );
XNOR2X1TS U3312 ( .A(n2476), .B(n2475), .Y(n2477) );
INVX2TS U3313 ( .A(n2478), .Y(n2512) );
INVX2TS U3314 ( .A(n2479), .Y(n2496) );
NAND2X1TS U3315 ( .A(n2496), .B(n2494), .Y(n2480) );
XNOR2X1TS U3316 ( .A(n2512), .B(n2480), .Y(n2481) );
INVX2TS U3317 ( .A(n2482), .Y(n2484) );
NAND2X1TS U3318 ( .A(n2484), .B(n2483), .Y(n2485) );
XOR2X1TS U3319 ( .A(n2486), .B(n2485), .Y(n2487) );
NAND2X1TS U3320 ( .A(n2489), .B(n2488), .Y(n2490) );
XNOR2X1TS U3321 ( .A(n2491), .B(n2490), .Y(n2493) );
INVX2TS U3322 ( .A(n2494), .Y(n2495) );
AOI21X1TS U3323 ( .A0(n2512), .A1(n2496), .B0(n2495), .Y(n2501) );
INVX2TS U3324 ( .A(n2497), .Y(n2499) );
NAND2X1TS U3325 ( .A(n2499), .B(n2498), .Y(n2500) );
XOR2X1TS U3326 ( .A(n2501), .B(n2500), .Y(n2503) );
BUFX3TS U3327 ( .A(n2502), .Y(n2559) );
INVX2TS U3328 ( .A(n2504), .Y(n2506) );
NAND2X1TS U3329 ( .A(n2506), .B(n2505), .Y(n2507) );
XOR2X1TS U3330 ( .A(n2508), .B(n2507), .Y(n2509) );
AOI21X1TS U3331 ( .A0(n2512), .A1(n2511), .B0(n2510), .Y(n2518) );
INVX2TS U3332 ( .A(n2517), .Y(n2513) );
NAND2X1TS U3333 ( .A(n2513), .B(n2516), .Y(n2514) );
XOR2X1TS U3334 ( .A(n2518), .B(n2514), .Y(n2515) );
INVX2TS U3335 ( .A(n2519), .Y(n2521) );
NAND2X1TS U3336 ( .A(n2521), .B(n2520), .Y(n2522) );
XNOR2X1TS U3337 ( .A(n2523), .B(n2522), .Y(n2524) );
NAND2X1TS U3338 ( .A(n2526), .B(n2525), .Y(n2527) );
XNOR2X1TS U3339 ( .A(n2528), .B(n2527), .Y(n2529) );
INVX2TS U3340 ( .A(n2530), .Y(n2532) );
NAND2X1TS U3341 ( .A(n2532), .B(n2531), .Y(n2533) );
XOR2X1TS U3342 ( .A(n2534), .B(n2533), .Y(n2535) );
INVX2TS U3343 ( .A(n2536), .Y(n2584) );
INVX2TS U3344 ( .A(n2546), .Y(n2537) );
NAND2X1TS U3345 ( .A(n2537), .B(n2545), .Y(n2538) );
XOR2X1TS U3346 ( .A(n2584), .B(n2538), .Y(n2539) );
NAND2X1TS U3347 ( .A(n2541), .B(n2540), .Y(n2542) );
XNOR2X1TS U3348 ( .A(n2543), .B(n2542), .Y(n2544) );
INVX2TS U3349 ( .A(n2547), .Y(n2549) );
NAND2X1TS U3350 ( .A(n2549), .B(n2548), .Y(n2550) );
XNOR2X1TS U3351 ( .A(n2551), .B(n2550), .Y(n2552) );
INVX2TS U3352 ( .A(n2553), .Y(n2580) );
AOI21X1TS U3353 ( .A0(n2580), .A1(n1567), .B0(n2554), .Y(n2558) );
NAND2X1TS U3354 ( .A(n2556), .B(n2555), .Y(n2557) );
XOR2X1TS U3355 ( .A(n2558), .B(n2557), .Y(n2560) );
INVX2TS U3356 ( .A(n2561), .Y(n2564) );
OAI21X1TS U3357 ( .A0(n2584), .A1(n2564), .B0(n2563), .Y(n2571) );
INVX2TS U3358 ( .A(n2565), .Y(n2570) );
NAND2X1TS U3359 ( .A(n2570), .B(n2568), .Y(n2566) );
XNOR2X1TS U3360 ( .A(n2571), .B(n2566), .Y(n2567) );
INVX2TS U3361 ( .A(n2568), .Y(n2569) );
AOI21X1TS U3362 ( .A0(n2571), .A1(n2570), .B0(n2569), .Y(n2576) );
NAND2X1TS U3363 ( .A(n2574), .B(n2573), .Y(n2575) );
XOR2X1TS U3364 ( .A(n2576), .B(n2575), .Y(n2577) );
NAND2X1TS U3365 ( .A(n1567), .B(n2578), .Y(n2579) );
XNOR2X1TS U3366 ( .A(n2580), .B(n2579), .Y(n2581) );
OAI21X1TS U3367 ( .A0(n2584), .A1(n2583), .B0(n2582), .Y(n2609) );
INVX2TS U3368 ( .A(n2609), .Y(n2599) );
INVX2TS U3369 ( .A(n2585), .Y(n2588) );
INVX2TS U3370 ( .A(n2586), .Y(n2587) );
OAI21X1TS U3371 ( .A0(n2599), .A1(n2588), .B0(n2587), .Y(n2604) );
INVX2TS U3372 ( .A(n2589), .Y(n2602) );
INVX2TS U3373 ( .A(n2601), .Y(n2590) );
AOI21X1TS U3374 ( .A0(n2604), .A1(n2602), .B0(n2590), .Y(n2595) );
INVX2TS U3375 ( .A(n2591), .Y(n2593) );
NAND2X1TS U3376 ( .A(n2593), .B(n2592), .Y(n2594) );
XOR2X1TS U3377 ( .A(n2595), .B(n2594), .Y(n2596) );
INVX2TS U3378 ( .A(n2597), .Y(n2608) );
NAND2X1TS U3379 ( .A(n2608), .B(n2606), .Y(n2598) );
XOR2X1TS U3380 ( .A(n2599), .B(n2598), .Y(n2600) );
NAND2X1TS U3381 ( .A(n2602), .B(n2601), .Y(n2603) );
XNOR2X1TS U3382 ( .A(n2604), .B(n2603), .Y(n2605) );
INVX2TS U3383 ( .A(n2606), .Y(n2607) );
AOI21X1TS U3384 ( .A0(n2609), .A1(n2608), .B0(n2607), .Y(n2614) );
INVX2TS U3385 ( .A(n2610), .Y(n2612) );
NAND2X1TS U3386 ( .A(n2612), .B(n2611), .Y(n2613) );
XOR2X1TS U3387 ( .A(n2614), .B(n2613), .Y(n2615) );
NOR4BX1TS U3388 ( .AN(n2627), .B(n2618), .C(n2617), .D(n2616), .Y(n2622) );
NOR4BX1TS U3389 ( .AN(n2622), .B(n2621), .C(n2620), .D(n2619), .Y(n2625) );
INVX2TS U3390 ( .A(n2623), .Y(n2624) );
OAI22X1TS U3391 ( .A0(n2629), .A1(n2628), .B0(n3069), .B1(n2627), .Y(n1515)
);
OAI22X1TS U3392 ( .A0(n2637), .A1(n2631), .B0(n2630), .B1(n2636), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U3393 ( .A0(n1560), .A1(n2633), .B0(n1548), .B1(n2632), .Y(n2640)
);
AOI22X1TS U3394 ( .A0(n2635), .A1(n1554), .B0(n1552), .B1(n2634), .Y(n2638)
);
AOI32X1TS U3395 ( .A0(n2640), .A1(n2639), .A2(n2638), .B0(n2637), .B1(n2636),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AND3X1TS U3396 ( .A(n2641), .B(n2961), .C(cordic_FSM_state_reg[0]), .Y(
ready_cordic) );
OAI211X1TS U3397 ( .A0(cordic_FSM_state_reg[1]), .A1(ack_cordic), .B0(
cordic_FSM_state_reg[2]), .C0(n2642), .Y(n2644) );
OAI31X1TS U3398 ( .A0(n2736), .A1(n2653), .A2(n3022), .B0(n2961), .Y(n2643)
);
AOI32X1TS U3399 ( .A0(cordic_FSM_state_reg[0]), .A1(n2644), .A2(n2643), .B0(
cordic_FSM_state_reg[2]), .B1(n2644), .Y(n2646) );
AOI32X1TS U3400 ( .A0(cordic_FSM_state_reg[0]), .A1(n2646), .A2(
cordic_FSM_state_reg[1]), .B0(n2645), .B1(n2646), .Y(n1520) );
NAND2X1TS U3401 ( .A(n3022), .B(n2971), .Y(n2651) );
AOI21X1TS U3402 ( .A0(n2655), .A1(n2961), .B0(cordic_FSM_state_reg[0]), .Y(
n2648) );
OAI211XLTS U3403 ( .A0(add_subt_module_sign_final_result), .A1(
underflow_flag), .B0(n1687), .C0(n3068), .Y(n2652) );
OAI2BB1X1TS U3404 ( .A0N(n2749), .A1N(result_add_subt[31]), .B0(n2652), .Y(
n1514) );
AOI21X1TS U3405 ( .A0(n3023), .A1(n2972), .B0(n2653), .Y(n2656) );
NAND4BX1TS U3406 ( .AN(n2655), .B(n2953), .C(cordic_FSM_state_reg[3]), .D(
n2654), .Y(n2737) );
OR3X2TS U3407 ( .A(n2657), .B(n2656), .C(n2737), .Y(n2751) );
BUFX3TS U3408 ( .A(n2751), .Y(n2738) );
INVX2TS U3409 ( .A(n2738), .Y(n2742) );
BUFX3TS U3410 ( .A(n2751), .Y(n2758) );
INVX2TS U3411 ( .A(n2764), .Y(n2728) );
NAND2X1TS U3412 ( .A(cont_iter_out[3]), .B(n2783), .Y(n2702) );
INVX2TS U3413 ( .A(n2667), .Y(n2668) );
OAI222X1TS U3414 ( .A0(n2659), .A1(n2675), .B0(n2702), .B1(n2668), .C0(n2957), .C1(n2658), .Y(n1505) );
AOI22X1TS U3415 ( .A0(n3071), .A1(n2660), .B0(n2659), .B1(n1562), .Y(n1504)
);
BUFX3TS U3416 ( .A(n2667), .Y(n2663) );
INVX2TS U3417 ( .A(n2663), .Y(n2662) );
OAI2BB2XLTS U3418 ( .B0(n2668), .B1(n3049), .A0N(n2662), .A1N(operation),
.Y(n1501) );
OAI2BB2XLTS U3419 ( .B0(n2668), .B1(n3174), .A0N(n2662), .A1N(
shift_region_flag[0]), .Y(n1500) );
OAI2BB2XLTS U3420 ( .B0(n2668), .B1(n2661), .A0N(n2662), .A1N(
shift_region_flag[1]), .Y(n1499) );
BUFX3TS U3421 ( .A(n2663), .Y(n2664) );
INVX2TS U3422 ( .A(n2663), .Y(n2670) );
BUFX3TS U3423 ( .A(n2663), .Y(n2669) );
INVX2TS U3424 ( .A(n2663), .Y(n2665) );
NOR3X1TS U3425 ( .A(cordic_FSM_state_reg[3]), .B(n2971), .C(n2671), .Y(n2673) );
NAND2X1TS U3426 ( .A(sel_mux_1_reg), .B(n3140), .Y(n2672) );
OAI2BB2XLTS U3427 ( .B0(n2673), .B1(n2672), .A0N(n2673), .A1N(n2701), .Y(
n1466) );
OAI21X1TS U3428 ( .A0(n3143), .A1(n1562), .B0(n2783), .Y(n2676) );
OAI21X1TS U3429 ( .A0(cont_iter_out[3]), .A1(n2676), .B0(n2796), .Y(n2695)
);
INVX2TS U3430 ( .A(n2695), .Y(n2674) );
NAND2X1TS U3431 ( .A(n2957), .B(n2698), .Y(n2705) );
INVX2TS U3432 ( .A(n2705), .Y(n2689) );
AOI22X1TS U3433 ( .A0(n2689), .A1(n2687), .B0(n2685), .B1(n2783), .Y(n2680)
);
AOI32X1TS U3434 ( .A0(n2676), .A1(n2723), .A2(n2675), .B0(n3064), .B1(n2710),
.Y(n1461) );
OAI21XLTS U3435 ( .A0(n2783), .A1(n2957), .B0(n3071), .Y(n2677) );
XOR2X1TS U3436 ( .A(n1558), .B(n2677), .Y(n2678) );
OAI2BB1X1TS U3437 ( .A0N(d_ff3_LUT_out[22]), .A1N(n2694), .B0(n2679), .Y(
n1458) );
AO21X2TS U3438 ( .A0(n2691), .A1(n2957), .B0(n2679), .Y(n2684) );
OAI221XLTS U3439 ( .A0(n2796), .A1(n3067), .B0(n2784), .B1(n2681), .C0(n2684), .Y(n1457) );
OAI2BB1X1TS U3440 ( .A0N(d_ff3_LUT_out[20]), .A1N(n2694), .B0(n2684), .Y(
n1456) );
OAI2BB1X1TS U3441 ( .A0N(d_ff3_LUT_out[19]), .A1N(n2694), .B0(n2679), .Y(
n1455) );
AOI31X1TS U3442 ( .A0(n2680), .A1(n2681), .A2(n2702), .B0(n2784), .Y(n2683)
);
OAI2BB1X1TS U3443 ( .A0N(d_ff3_LUT_out[17]), .A1N(n2694), .B0(n2684), .Y(
n1453) );
OAI2BB1X1TS U3444 ( .A0N(d_ff3_LUT_out[15]), .A1N(n2694), .B0(n2684), .Y(
n1451) );
NOR2X1TS U3445 ( .A(cont_iter_out[1]), .B(n2681), .Y(n2697) );
OAI21X1TS U3446 ( .A0(n2697), .A1(n2682), .B0(n2796), .Y(n2693) );
OAI2BB1X1TS U3447 ( .A0N(d_ff3_LUT_out[14]), .A1N(n2694), .B0(n2693), .Y(
n1450) );
OAI21X1TS U3448 ( .A0(n2701), .A1(n2784), .B0(n2684), .Y(n2686) );
OA21XLTS U3449 ( .A0(n2794), .A1(d_ff3_LUT_out[10]), .B0(n2706), .Y(n1446)
);
AOI31X1TS U3450 ( .A0(n2689), .A1(n3143), .A2(n1562), .B0(n2688), .Y(n2700)
);
OAI31X1TS U3451 ( .A0(n2698), .A1(n2957), .A2(n2690), .B0(n2700), .Y(n2696)
);
OAI2BB1X1TS U3452 ( .A0N(d_ff3_LUT_out[5]), .A1N(n2694), .B0(n2693), .Y(
n1441) );
OA22X1TS U3453 ( .A0(n2696), .A1(n2695), .B0(n2796), .B1(d_ff3_LUT_out[4]),
.Y(n1440) );
NAND2X1TS U3454 ( .A(n2698), .B(n2697), .Y(n2699) );
AOI32X1TS U3455 ( .A0(n2700), .A1(n2792), .A2(n2699), .B0(n3065), .B1(n2710),
.Y(n1438) );
OA22X1TS U3456 ( .A0(n2707), .A1(n2706), .B0(n2792), .B1(d_ff3_LUT_out[0]),
.Y(n1436) );
OA22X1TS U3457 ( .A0(d_ff2_X[27]), .A1(n2709), .B0(d_ff_Xn[27]), .B1(n2708),
.Y(n1431) );
OAI2BB1X1TS U3458 ( .A0N(n2794), .A1N(n2713), .B0(n2711), .Y(n1426) );
AOI22X1TS U3459 ( .A0(cont_iter_out[1]), .A1(n3014), .B0(d_ff2_X[24]), .B1(
n3143), .Y(n2712) );
XNOR2X1TS U3460 ( .A(n2713), .B(n2712), .Y(n2715) );
BUFX3TS U3461 ( .A(n2714), .Y(n2730) );
AOI21X1TS U3462 ( .A0(n2721), .A1(d_ff2_X[27]), .B0(n2719), .Y(n2720) );
OR3X1TS U3463 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(n2721), .Y(n2724) );
OAI21XLTS U3464 ( .A0(d_ff2_X[27]), .A1(n2721), .B0(d_ff2_X[28]), .Y(n2722)
);
AOI32X1TS U3465 ( .A0(n2724), .A1(n2792), .A2(n2722), .B0(n3066), .B1(n2784),
.Y(n1421) );
NOR2X1TS U3466 ( .A(d_ff2_X[29]), .B(n2724), .Y(n2726) );
AOI21X1TS U3467 ( .A0(d_ff2_X[29]), .A1(n2724), .B0(n2726), .Y(n2725) );
XOR2X1TS U3468 ( .A(d_ff2_X[30]), .B(n2726), .Y(n2727) );
INVX2TS U3469 ( .A(n2764), .Y(n2774) );
INVX2TS U3470 ( .A(n2790), .Y(n2731) );
BUFX3TS U3471 ( .A(n2714), .Y(n2798) );
INVX2TS U3472 ( .A(n2704), .Y(n2800) );
BUFX3TS U3473 ( .A(n2714), .Y(n2763) );
NOR2X2TS U3474 ( .A(n2733), .B(n2737), .Y(n2734) );
BUFX3TS U3475 ( .A(n2757), .Y(n2745) );
BUFX3TS U3476 ( .A(n2757), .Y(n2750) );
CLKBUFX2TS U3477 ( .A(n2750), .Y(n2761) );
OAI2BB2XLTS U3478 ( .B0(n2745), .B1(n3173), .A0N(n2761), .A1N(
result_add_subt[31]), .Y(n1371) );
BUFX3TS U3479 ( .A(n2752), .Y(n2744) );
INVX2TS U3480 ( .A(n2744), .Y(n2741) );
BUFX3TS U3481 ( .A(n2752), .Y(n2759) );
BUFX3TS U3482 ( .A(n2759), .Y(n2756) );
OA22X1TS U3483 ( .A0(n1535), .A1(result_add_subt[30]), .B0(
add_subt_module_exp_oper_result[7]), .B1(n1544), .Y(n1301) );
BUFX3TS U3484 ( .A(n2757), .Y(n2743) );
OAI2BB2XLTS U3485 ( .B0(n2743), .B1(n3062), .A0N(n2761), .A1N(
result_add_subt[30]), .Y(n1299) );
OA22X1TS U3486 ( .A0(n1687), .A1(result_add_subt[29]), .B0(
add_subt_module_exp_oper_result[6]), .B1(n1543), .Y(n1297) );
BUFX3TS U3487 ( .A(n2750), .Y(n2754) );
OAI2BB2XLTS U3488 ( .B0(n2745), .B1(n3172), .A0N(n2754), .A1N(
result_add_subt[29]), .Y(n1295) );
OA22X1TS U3489 ( .A0(n1687), .A1(result_add_subt[28]), .B0(
add_subt_module_exp_oper_result[5]), .B1(n1544), .Y(n1293) );
OAI2BB2XLTS U3490 ( .B0(n2743), .B1(n3171), .A0N(n2754), .A1N(
result_add_subt[28]), .Y(n1291) );
OA22X1TS U3491 ( .A0(n1535), .A1(result_add_subt[27]), .B0(
add_subt_module_exp_oper_result[4]), .B1(n1543), .Y(n1289) );
OAI2BB2XLTS U3492 ( .B0(n2743), .B1(n3061), .A0N(n2754), .A1N(
result_add_subt[27]), .Y(n1287) );
OA22X1TS U3493 ( .A0(n1535), .A1(result_add_subt[26]), .B0(
add_subt_module_exp_oper_result[3]), .B1(n1544), .Y(n1285) );
OAI2BB2XLTS U3494 ( .B0(n2743), .B1(n3170), .A0N(n2734), .A1N(
result_add_subt[26]), .Y(n1283) );
OA22X1TS U3495 ( .A0(n1687), .A1(result_add_subt[25]), .B0(
add_subt_module_exp_oper_result[2]), .B1(n1543), .Y(n1281) );
OAI2BB2XLTS U3496 ( .B0(n2743), .B1(n3169), .A0N(n2750), .A1N(
result_add_subt[25]), .Y(n1279) );
OA22X1TS U3497 ( .A0(n1687), .A1(result_add_subt[24]), .B0(
add_subt_module_exp_oper_result[1]), .B1(n1543), .Y(n1277) );
OA22X1TS U3498 ( .A0(n1535), .A1(result_add_subt[23]), .B0(
add_subt_module_exp_oper_result[0]), .B1(n1544), .Y(n1273) );
BUFX3TS U3499 ( .A(n2751), .Y(n2746) );
OAI2BB2XLTS U3500 ( .B0(n2743), .B1(n3166), .A0N(n2750), .A1N(
result_add_subt[22]), .Y(n1267) );
OAI2BB2XLTS U3501 ( .B0(n3032), .B1(n1542), .A0N(result_add_subt[21]), .A1N(
n2740), .Y(n1265) );
INVX2TS U3502 ( .A(n2756), .Y(n2747) );
OAI2BB2XLTS U3503 ( .B0(n2743), .B1(n3165), .A0N(n2745), .A1N(
result_add_subt[21]), .Y(n1263) );
INVX2TS U3504 ( .A(n2758), .Y(n2748) );
OAI2BB2XLTS U3505 ( .B0(n3033), .B1(n1542), .A0N(result_add_subt[20]), .A1N(
n2740), .Y(n1261) );
BUFX3TS U3506 ( .A(n2757), .Y(n2762) );
OAI2BB2XLTS U3507 ( .B0(n2762), .B1(n3164), .A0N(n2745), .A1N(
result_add_subt[20]), .Y(n1259) );
OAI2BB2XLTS U3508 ( .B0(n3034), .B1(n1544), .A0N(result_add_subt[19]), .A1N(
n2740), .Y(n1257) );
OAI2BB2XLTS U3509 ( .B0(n2762), .B1(n3163), .A0N(n2745), .A1N(
result_add_subt[19]), .Y(n1255) );
OAI2BB2XLTS U3510 ( .B0(n3018), .B1(n1544), .A0N(result_add_subt[18]), .A1N(
n2740), .Y(n1253) );
OAI2BB2XLTS U3511 ( .B0(n2762), .B1(n3162), .A0N(n2745), .A1N(
result_add_subt[18]), .Y(n1251) );
OAI2BB2XLTS U3512 ( .B0(n3019), .B1(n1543), .A0N(result_add_subt[17]), .A1N(
n2740), .Y(n1249) );
OAI2BB2XLTS U3513 ( .B0(n2762), .B1(n3161), .A0N(n2745), .A1N(
result_add_subt[17]), .Y(n1247) );
OAI2BB2XLTS U3514 ( .B0(n3020), .B1(n1544), .A0N(result_add_subt[16]), .A1N(
n2740), .Y(n1245) );
OAI2BB2XLTS U3515 ( .B0(n2743), .B1(n3160), .A0N(n2750), .A1N(
result_add_subt[16]), .Y(n1243) );
OAI2BB2XLTS U3516 ( .B0(n3007), .B1(n1543), .A0N(result_add_subt[15]), .A1N(
n2740), .Y(n1241) );
OAI2BB2XLTS U3517 ( .B0(n2762), .B1(n3159), .A0N(n2745), .A1N(
result_add_subt[15]), .Y(n1239) );
OAI2BB2XLTS U3518 ( .B0(n3008), .B1(n1544), .A0N(result_add_subt[14]), .A1N(
n2749), .Y(n1237) );
OAI2BB2XLTS U3519 ( .B0(n2762), .B1(n3158), .A0N(n2745), .A1N(
result_add_subt[14]), .Y(n1235) );
OAI2BB2XLTS U3520 ( .B0(n3009), .B1(n1543), .A0N(result_add_subt[13]), .A1N(
n2749), .Y(n1233) );
OAI2BB2XLTS U3521 ( .B0(n2762), .B1(n3157), .A0N(n2750), .A1N(
result_add_subt[13]), .Y(n1231) );
OAI2BB2XLTS U3522 ( .B0(n2762), .B1(n3156), .A0N(n2750), .A1N(
result_add_subt[12]), .Y(n1227) );
OAI2BB2XLTS U3523 ( .B0(n3010), .B1(n1544), .A0N(result_add_subt[11]), .A1N(
n2749), .Y(n1225) );
INVX2TS U3524 ( .A(n2756), .Y(n2753) );
OAI2BB2XLTS U3525 ( .B0(n2762), .B1(n3155), .A0N(n2734), .A1N(
result_add_subt[11]), .Y(n1223) );
INVX2TS U3526 ( .A(n2758), .Y(n2755) );
OAI2BB2XLTS U3527 ( .B0(n2983), .B1(n1543), .A0N(result_add_subt[10]), .A1N(
n2749), .Y(n1221) );
OAI2BB2XLTS U3528 ( .B0(n2761), .B1(n3154), .A0N(n2754), .A1N(
result_add_subt[10]), .Y(n1219) );
OAI2BB2XLTS U3529 ( .B0(n2757), .B1(n3146), .A0N(n2754), .A1N(
result_add_subt[2]), .Y(n1187) );
INVX2TS U3530 ( .A(n2756), .Y(n2760) );
INVX2TS U3531 ( .A(n2758), .Y(n2803) );
INVX2TS U3532 ( .A(n2764), .Y(n2801) );
OAI2BB2XLTS U3533 ( .B0(n3144), .B1(n2802), .A0N(d_ff2_Y[0]), .A1N(n2801),
.Y(n1145) );
INVX2TS U3534 ( .A(n2704), .Y(n2765) );
OAI2BB2XLTS U3535 ( .B0(n3145), .B1(n2802), .A0N(d_ff2_Y[1]), .A1N(n2801),
.Y(n1143) );
OAI2BB2XLTS U3536 ( .B0(n3146), .B1(n2802), .A0N(d_ff2_Y[2]), .A1N(n2801),
.Y(n1141) );
OAI2BB2XLTS U3537 ( .B0(n3147), .B1(n2802), .A0N(d_ff2_Y[3]), .A1N(n2801),
.Y(n1139) );
BUFX3TS U3538 ( .A(n2714), .Y(n2766) );
OAI2BB2XLTS U3539 ( .B0(n3148), .B1(n2802), .A0N(d_ff2_Y[4]), .A1N(n2801),
.Y(n1137) );
OAI2BB2XLTS U3540 ( .B0(n3149), .B1(n2802), .A0N(d_ff2_Y[5]), .A1N(n2801),
.Y(n1135) );
OAI2BB2XLTS U3541 ( .B0(n3150), .B1(n2802), .A0N(d_ff2_Y[6]), .A1N(n2801),
.Y(n1133) );
OAI2BB2XLTS U3542 ( .B0(n3151), .B1(n2802), .A0N(d_ff2_Y[7]), .A1N(n2801),
.Y(n1131) );
INVX2TS U3543 ( .A(n2768), .Y(n2767) );
INVX2TS U3544 ( .A(n2764), .Y(n2771) );
OAI2BB2XLTS U3545 ( .B0(n3153), .B1(n2767), .A0N(d_ff2_Y[9]), .A1N(n2771),
.Y(n1127) );
OAI2BB2XLTS U3546 ( .B0(n3154), .B1(n2767), .A0N(d_ff2_Y[10]), .A1N(n2771),
.Y(n1125) );
INVX2TS U3547 ( .A(n2704), .Y(n2769) );
OAI2BB2XLTS U3548 ( .B0(n3155), .B1(n2767), .A0N(d_ff2_Y[11]), .A1N(n2771),
.Y(n1123) );
OAI2BB2XLTS U3549 ( .B0(n3156), .B1(n2767), .A0N(d_ff2_Y[12]), .A1N(n2771),
.Y(n1121) );
OAI2BB2XLTS U3550 ( .B0(n3157), .B1(n2767), .A0N(d_ff2_Y[13]), .A1N(n2771),
.Y(n1119) );
OAI2BB2XLTS U3551 ( .B0(n3158), .B1(n2767), .A0N(d_ff2_Y[14]), .A1N(n2771),
.Y(n1117) );
OAI2BB2XLTS U3552 ( .B0(n3159), .B1(n2767), .A0N(d_ff2_Y[15]), .A1N(n2801),
.Y(n1115) );
OAI2BB2XLTS U3553 ( .B0(n3160), .B1(n2767), .A0N(d_ff2_Y[16]), .A1N(n2770),
.Y(n1113) );
OAI2BB2XLTS U3554 ( .B0(n3161), .B1(n2767), .A0N(d_ff2_Y[17]), .A1N(n2770),
.Y(n1111) );
OAI2BB2XLTS U3555 ( .B0(n3162), .B1(n2767), .A0N(d_ff2_Y[18]), .A1N(n2771),
.Y(n1109) );
INVX2TS U3556 ( .A(n2768), .Y(n2773) );
OAI2BB2XLTS U3557 ( .B0(n3163), .B1(n2773), .A0N(d_ff2_Y[19]), .A1N(n2770),
.Y(n1107) );
OAI2BB2XLTS U3558 ( .B0(n3164), .B1(n2773), .A0N(d_ff2_Y[20]), .A1N(n2770),
.Y(n1105) );
OAI2BB2XLTS U3559 ( .B0(n3165), .B1(n2773), .A0N(d_ff2_Y[21]), .A1N(n2770),
.Y(n1103) );
OAI2BB2XLTS U3560 ( .B0(n3166), .B1(n2773), .A0N(d_ff2_Y[22]), .A1N(n2771),
.Y(n1101) );
OAI22X1TS U3561 ( .A0(n1772), .A1(n2975), .B0(n3167), .B1(n2773), .Y(n1099)
);
OAI22X1TS U3562 ( .A0(n1772), .A1(n3012), .B0(n3168), .B1(n2773), .Y(n1098)
);
OAI2BB2XLTS U3563 ( .B0(n3169), .B1(n2773), .A0N(d_ff2_Y[25]), .A1N(n2770),
.Y(n1097) );
OAI2BB2XLTS U3564 ( .B0(n3170), .B1(n2773), .A0N(d_ff2_Y[26]), .A1N(n2771),
.Y(n1096) );
OAI22X1TS U3565 ( .A0(n1772), .A1(n3052), .B0(n3171), .B1(n2773), .Y(n1094)
);
OAI2BB2XLTS U3566 ( .B0(n3172), .B1(n2773), .A0N(n2774), .A1N(d_ff2_Y[29]),
.Y(n1093) );
AOI22X1TS U3567 ( .A0(n1558), .A1(n3012), .B0(d_ff2_Y[24]), .B1(n3143), .Y(
n2776) );
XNOR2X1TS U3568 ( .A(n2779), .B(n2776), .Y(n2777) );
NAND2X1TS U3569 ( .A(d_ff2_Y[24]), .B(n3143), .Y(n2778) );
AOI22X1TS U3570 ( .A0(cont_iter_out[1]), .A1(n3012), .B0(n2779), .B1(n2778),
.Y(n2782) );
NOR2X1TS U3571 ( .A(d_ff2_Y[27]), .B(n2788), .Y(n2789) );
AOI21X1TS U3572 ( .A0(n2788), .A1(d_ff2_Y[27]), .B0(n2789), .Y(n2787) );
OR3X1TS U3573 ( .A(n2788), .B(d_ff2_Y[28]), .C(d_ff2_Y[27]), .Y(n2793) );
NOR2X1TS U3574 ( .A(d_ff2_Y[29]), .B(n2793), .Y(n2797) );
AOI21X1TS U3575 ( .A0(d_ff2_Y[29]), .A1(n2793), .B0(n2797), .Y(n2795) );
XOR2X1TS U3576 ( .A(d_ff2_Y[30]), .B(n2797), .Y(n2799) );
OAI2BB2XLTS U3577 ( .B0(n3173), .B1(n2802), .A0N(d_ff2_Y[31]), .A1N(n2801),
.Y(n1083) );
BUFX3TS U3578 ( .A(n2806), .Y(n2805) );
INVX2TS U3579 ( .A(n2805), .Y(n2804) );
INVX2TS U3580 ( .A(n2808), .Y(n2807) );
BUFX3TS U3581 ( .A(n2806), .Y(n2809) );
INVX2TS U3582 ( .A(n2808), .Y(n2810) );
BUFX3TS U3583 ( .A(n2901), .Y(n2875) );
AOI22X1TS U3584 ( .A0(add_subt_module_intDY[0]), .A1(n2817), .B0(n2875),
.B1(d_ff3_sh_y_out[0]), .Y(n2814) );
BUFX3TS U3585 ( .A(n2891), .Y(n2937) );
BUFX3TS U3586 ( .A(n2949), .Y(n2886) );
AOI22X1TS U3587 ( .A0(d_ff3_LUT_out[0]), .A1(n2937), .B0(n2886), .B1(
d_ff3_sh_x_out[0]), .Y(n2813) );
NAND2X1TS U3588 ( .A(n2814), .B(n2813), .Y(n1013) );
AOI22X1TS U3589 ( .A0(add_subt_module_intDY[26]), .A1(n2943), .B0(n2822),
.B1(d_ff3_sh_y_out[26]), .Y(n2816) );
AOI22X1TS U3590 ( .A0(d_ff3_LUT_out[26]), .A1(n2940), .B0(n2841), .B1(
d_ff3_sh_x_out[26]), .Y(n2815) );
NAND2X1TS U3591 ( .A(n2816), .B(n2815), .Y(n1008) );
AOI22X1TS U3592 ( .A0(add_subt_module_intDY[25]), .A1(n2817), .B0(n2822),
.B1(d_ff3_sh_y_out[25]), .Y(n2819) );
AOI22X1TS U3593 ( .A0(n2950), .A1(d_ff3_LUT_out[25]), .B0(n2831), .B1(
d_ff3_sh_x_out[25]), .Y(n2818) );
NAND2X1TS U3594 ( .A(n2819), .B(n2818), .Y(n1007) );
AOI22X1TS U3595 ( .A0(add_subt_module_intDY[24]), .A1(n2929), .B0(n2822),
.B1(d_ff3_sh_y_out[24]), .Y(n2821) );
AOI22X1TS U3596 ( .A0(d_ff3_LUT_out[24]), .A1(n2940), .B0(n2841), .B1(
d_ff3_sh_x_out[24]), .Y(n2820) );
NAND2X1TS U3597 ( .A(n2821), .B(n2820), .Y(n1006) );
AOI22X1TS U3598 ( .A0(add_subt_module_intDY[23]), .A1(n2834), .B0(n2822),
.B1(d_ff3_sh_y_out[23]), .Y(n2824) );
AOI22X1TS U3599 ( .A0(n2950), .A1(d_ff3_LUT_out[23]), .B0(n2841), .B1(
d_ff3_sh_x_out[23]), .Y(n2823) );
NAND2X1TS U3600 ( .A(n2824), .B(n2823), .Y(n1005) );
BUFX3TS U3601 ( .A(n2901), .Y(n2947) );
AOI22X1TS U3602 ( .A0(add_subt_module_intDX[30]), .A1(n2929), .B0(
d_ff2_X[30]), .B1(n2947), .Y(n2826) );
AOI22X1TS U3603 ( .A0(d_ff2_Y[30]), .A1(n2831), .B0(n2940), .B1(d_ff2_Z[30]),
.Y(n2825) );
NAND2X1TS U3604 ( .A(n2826), .B(n2825), .Y(n1000) );
AOI22X1TS U3605 ( .A0(add_subt_module_intDX[29]), .A1(n2929), .B0(
d_ff2_X[29]), .B1(n2901), .Y(n2828) );
AOI22X1TS U3606 ( .A0(d_ff2_Y[29]), .A1(n2831), .B0(n2940), .B1(d_ff2_Z[29]),
.Y(n2827) );
NAND2X1TS U3607 ( .A(n2828), .B(n2827), .Y(n997) );
AOI22X1TS U3608 ( .A0(add_subt_module_intDX[28]), .A1(n2929), .B0(
d_ff2_X[28]), .B1(n2947), .Y(n2830) );
AOI22X1TS U3609 ( .A0(d_ff2_Y[28]), .A1(n2831), .B0(n2940), .B1(d_ff2_Z[28]),
.Y(n2829) );
NAND2X1TS U3610 ( .A(n2830), .B(n2829), .Y(n994) );
AOI22X1TS U3611 ( .A0(add_subt_module_intDX[27]), .A1(n2929), .B0(
d_ff2_X[27]), .B1(n2901), .Y(n2833) );
AOI22X1TS U3612 ( .A0(d_ff2_Y[27]), .A1(n2831), .B0(n2940), .B1(d_ff2_Z[27]),
.Y(n2832) );
NAND2X1TS U3613 ( .A(n2833), .B(n2832), .Y(n991) );
AOI22X1TS U3614 ( .A0(add_subt_module_intDX[23]), .A1(n2904), .B0(n2852),
.B1(d_ff2_X[23]), .Y(n2836) );
AOI22X1TS U3615 ( .A0(n2950), .A1(d_ff2_Z[23]), .B0(n2841), .B1(d_ff2_Y[23]),
.Y(n2835) );
NAND2X1TS U3616 ( .A(n2836), .B(n2835), .Y(n979) );
AOI22X1TS U3617 ( .A0(add_subt_module_intDX[0]), .A1(n2904), .B0(n2852),
.B1(d_ff2_X[0]), .Y(n2838) );
AOI22X1TS U3618 ( .A0(n2950), .A1(d_ff2_Z[0]), .B0(n2841), .B1(d_ff2_Y[0]),
.Y(n2837) );
NAND2X1TS U3619 ( .A(n2838), .B(n2837), .Y(n976) );
AOI22X1TS U3620 ( .A0(add_subt_module_intDX[22]), .A1(n2857), .B0(n2852),
.B1(d_ff2_X[22]), .Y(n2840) );
AOI22X1TS U3621 ( .A0(n2950), .A1(d_ff2_Z[22]), .B0(n2841), .B1(d_ff2_Y[22]),
.Y(n2839) );
NAND2X1TS U3622 ( .A(n2840), .B(n2839), .Y(n974) );
AOI22X1TS U3623 ( .A0(add_subt_module_intDY[22]), .A1(n2834), .B0(n2852),
.B1(d_ff3_sh_y_out[22]), .Y(n2843) );
BUFX3TS U3624 ( .A(n2891), .Y(n2866) );
AOI22X1TS U3625 ( .A0(n2866), .A1(d_ff3_LUT_out[22]), .B0(n2841), .B1(
d_ff3_sh_x_out[22]), .Y(n2842) );
NAND2X1TS U3626 ( .A(n2843), .B(n2842), .Y(n973) );
AOI22X1TS U3627 ( .A0(add_subt_module_intDX[6]), .A1(n2834), .B0(n2852),
.B1(d_ff2_X[6]), .Y(n2845) );
BUFX3TS U3628 ( .A(n2949), .Y(n2865) );
AOI22X1TS U3629 ( .A0(n2866), .A1(d_ff2_Z[6]), .B0(n2865), .B1(d_ff2_Y[6]),
.Y(n2844) );
NAND2X1TS U3630 ( .A(n2845), .B(n2844), .Y(n971) );
AOI22X1TS U3631 ( .A0(add_subt_module_intDY[6]), .A1(n2904), .B0(n2852),
.B1(d_ff3_sh_y_out[6]), .Y(n2847) );
AOI22X1TS U3632 ( .A0(d_ff3_LUT_out[6]), .A1(n2940), .B0(n2865), .B1(
d_ff3_sh_x_out[6]), .Y(n2846) );
NAND2X1TS U3633 ( .A(n2847), .B(n2846), .Y(n970) );
AOI22X1TS U3634 ( .A0(add_subt_module_intDX[3]), .A1(n2904), .B0(n2852),
.B1(d_ff2_X[3]), .Y(n2849) );
AOI22X1TS U3635 ( .A0(n2866), .A1(d_ff2_Z[3]), .B0(n2865), .B1(d_ff2_Y[3]),
.Y(n2848) );
NAND2X1TS U3636 ( .A(n2849), .B(n2848), .Y(n968) );
AOI22X1TS U3637 ( .A0(add_subt_module_intDY[3]), .A1(n2857), .B0(n2852),
.B1(d_ff3_sh_y_out[3]), .Y(n2851) );
AOI22X1TS U3638 ( .A0(n2866), .A1(d_ff3_LUT_out[3]), .B0(n2865), .B1(
d_ff3_sh_x_out[3]), .Y(n2850) );
NAND2X1TS U3639 ( .A(n2851), .B(n2850), .Y(n967) );
AOI22X1TS U3640 ( .A0(add_subt_module_intDX[19]), .A1(n2857), .B0(n2852),
.B1(d_ff2_X[19]), .Y(n2854) );
AOI22X1TS U3641 ( .A0(n2866), .A1(d_ff2_Z[19]), .B0(n2865), .B1(d_ff2_Y[19]),
.Y(n2853) );
NAND2X1TS U3642 ( .A(n2854), .B(n2853), .Y(n965) );
AOI22X1TS U3643 ( .A0(add_subt_module_intDY[19]), .A1(n2834), .B0(n2875),
.B1(d_ff3_sh_y_out[19]), .Y(n2856) );
AOI22X1TS U3644 ( .A0(n2866), .A1(d_ff3_LUT_out[19]), .B0(n2865), .B1(
d_ff3_sh_x_out[19]), .Y(n2855) );
NAND2X1TS U3645 ( .A(n2856), .B(n2855), .Y(n964) );
AOI22X1TS U3646 ( .A0(add_subt_module_intDX[2]), .A1(n2834), .B0(n2875),
.B1(d_ff2_X[2]), .Y(n2859) );
AOI22X1TS U3647 ( .A0(n2866), .A1(d_ff2_Z[2]), .B0(n2865), .B1(d_ff2_Y[2]),
.Y(n2858) );
NAND2X1TS U3648 ( .A(n2859), .B(n2858), .Y(n961) );
INVX2TS U3649 ( .A(n2860), .Y(n2948) );
AOI22X1TS U3650 ( .A0(add_subt_module_intDY[2]), .A1(n2943), .B0(n2875),
.B1(d_ff3_sh_y_out[2]), .Y(n2862) );
AOI22X1TS U3651 ( .A0(n2866), .A1(d_ff3_LUT_out[2]), .B0(n2865), .B1(
d_ff3_sh_x_out[2]), .Y(n2861) );
NAND2X1TS U3652 ( .A(n2862), .B(n2861), .Y(n960) );
AOI22X1TS U3653 ( .A0(add_subt_module_intDX[21]), .A1(n2817), .B0(n2875),
.B1(d_ff2_X[21]), .Y(n2864) );
AOI22X1TS U3654 ( .A0(n2866), .A1(d_ff2_Z[21]), .B0(n2865), .B1(d_ff2_Y[21]),
.Y(n2863) );
NAND2X1TS U3655 ( .A(n2864), .B(n2863), .Y(n958) );
AOI22X1TS U3656 ( .A0(add_subt_module_intDY[21]), .A1(n2817), .B0(n2875),
.B1(d_ff3_sh_y_out[21]), .Y(n2868) );
AOI22X1TS U3657 ( .A0(n2866), .A1(d_ff3_LUT_out[21]), .B0(n2865), .B1(
d_ff3_sh_x_out[21]), .Y(n2867) );
NAND2X1TS U3658 ( .A(n2868), .B(n2867), .Y(n957) );
AOI22X1TS U3659 ( .A0(add_subt_module_intDX[18]), .A1(n2817), .B0(n2875),
.B1(d_ff2_X[18]), .Y(n2870) );
BUFX3TS U3660 ( .A(n2891), .Y(n2913) );
AOI22X1TS U3661 ( .A0(n2913), .A1(d_ff2_Z[18]), .B0(n2886), .B1(d_ff2_Y[18]),
.Y(n2869) );
NAND2X1TS U3662 ( .A(n2870), .B(n2869), .Y(n955) );
AOI22X1TS U3663 ( .A0(add_subt_module_intDY[18]), .A1(n2948), .B0(n2875),
.B1(d_ff3_sh_y_out[18]), .Y(n2872) );
AOI22X1TS U3664 ( .A0(d_ff3_LUT_out[18]), .A1(n2937), .B0(n2886), .B1(
d_ff3_sh_x_out[18]), .Y(n2871) );
NAND2X1TS U3665 ( .A(n2872), .B(n2871), .Y(n954) );
AOI22X1TS U3666 ( .A0(add_subt_module_intDX[15]), .A1(n2817), .B0(n2875),
.B1(d_ff2_X[15]), .Y(n2874) );
AOI22X1TS U3667 ( .A0(n2913), .A1(d_ff2_Z[15]), .B0(n2886), .B1(d_ff2_Y[15]),
.Y(n2873) );
NAND2X1TS U3668 ( .A(n2874), .B(n2873), .Y(n951) );
AOI22X1TS U3669 ( .A0(add_subt_module_intDY[15]), .A1(n2943), .B0(n2875),
.B1(d_ff3_sh_y_out[15]), .Y(n2877) );
AOI22X1TS U3670 ( .A0(n2913), .A1(d_ff3_LUT_out[15]), .B0(n2886), .B1(
d_ff3_sh_x_out[15]), .Y(n2876) );
NAND2X1TS U3671 ( .A(n2877), .B(n2876), .Y(n950) );
BUFX3TS U3672 ( .A(n2901), .Y(n2898) );
AOI22X1TS U3673 ( .A0(add_subt_module_intDX[8]), .A1(n2817), .B0(n2898),
.B1(d_ff2_X[8]), .Y(n2879) );
AOI22X1TS U3674 ( .A0(n2913), .A1(d_ff2_Z[8]), .B0(n2886), .B1(d_ff2_Y[8]),
.Y(n2878) );
NAND2X1TS U3675 ( .A(n2879), .B(n2878), .Y(n948) );
AOI22X1TS U3676 ( .A0(add_subt_module_intDY[8]), .A1(n2943), .B0(n2898),
.B1(d_ff3_sh_y_out[8]), .Y(n2881) );
AOI22X1TS U3677 ( .A0(n2913), .A1(d_ff3_LUT_out[8]), .B0(n2886), .B1(
d_ff3_sh_x_out[8]), .Y(n2880) );
NAND2X1TS U3678 ( .A(n2881), .B(n2880), .Y(n947) );
AOI22X1TS U3679 ( .A0(add_subt_module_intDX[1]), .A1(n2857), .B0(n2898),
.B1(d_ff2_X[1]), .Y(n2883) );
AOI22X1TS U3680 ( .A0(n2913), .A1(d_ff2_Z[1]), .B0(n2886), .B1(d_ff2_Y[1]),
.Y(n2882) );
NAND2X1TS U3681 ( .A(n2883), .B(n2882), .Y(n945) );
AOI22X1TS U3682 ( .A0(add_subt_module_intDY[1]), .A1(n2834), .B0(n2898),
.B1(d_ff3_sh_y_out[1]), .Y(n2885) );
AOI22X1TS U3683 ( .A0(n2913), .A1(d_ff3_LUT_out[1]), .B0(n2886), .B1(
d_ff3_sh_x_out[1]), .Y(n2884) );
NAND2X1TS U3684 ( .A(n2885), .B(n2884), .Y(n944) );
AOI22X1TS U3685 ( .A0(add_subt_module_intDX[20]), .A1(n2834), .B0(n2898),
.B1(d_ff2_X[20]), .Y(n2888) );
AOI22X1TS U3686 ( .A0(n2913), .A1(d_ff2_Z[20]), .B0(n2886), .B1(d_ff2_Y[20]),
.Y(n2887) );
NAND2X1TS U3687 ( .A(n2888), .B(n2887), .Y(n942) );
AOI22X1TS U3688 ( .A0(add_subt_module_intDY[20]), .A1(n2904), .B0(n2898),
.B1(d_ff3_sh_y_out[20]), .Y(n2890) );
BUFX3TS U3689 ( .A(n2949), .Y(n2912) );
AOI22X1TS U3690 ( .A0(n2913), .A1(d_ff3_LUT_out[20]), .B0(n2912), .B1(
d_ff3_sh_x_out[20]), .Y(n2889) );
NAND2X1TS U3691 ( .A(n2890), .B(n2889), .Y(n941) );
AOI22X1TS U3692 ( .A0(add_subt_module_intDX[13]), .A1(n2904), .B0(n2898),
.B1(d_ff2_X[13]), .Y(n2893) );
BUFX3TS U3693 ( .A(n2891), .Y(n2944) );
AOI22X1TS U3694 ( .A0(n2944), .A1(d_ff2_Z[13]), .B0(n2912), .B1(d_ff2_Y[13]),
.Y(n2892) );
NAND2X1TS U3695 ( .A(n2893), .B(n2892), .Y(n938) );
AOI22X1TS U3696 ( .A0(add_subt_module_intDY[13]), .A1(n2929), .B0(n2898),
.B1(d_ff3_sh_y_out[13]), .Y(n2895) );
AOI22X1TS U3697 ( .A0(d_ff3_LUT_out[13]), .A1(n2937), .B0(n2912), .B1(
d_ff3_sh_x_out[13]), .Y(n2894) );
NAND2X1TS U3698 ( .A(n2895), .B(n2894), .Y(n937) );
AOI22X1TS U3699 ( .A0(add_subt_module_intDX[5]), .A1(n2857), .B0(n2898),
.B1(d_ff2_X[5]), .Y(n2897) );
AOI22X1TS U3700 ( .A0(n2944), .A1(d_ff2_Z[5]), .B0(n2912), .B1(d_ff2_Y[5]),
.Y(n2896) );
NAND2X1TS U3701 ( .A(n2897), .B(n2896), .Y(n934) );
AOI22X1TS U3702 ( .A0(add_subt_module_intDY[5]), .A1(n2929), .B0(n2898),
.B1(d_ff3_sh_y_out[5]), .Y(n2900) );
AOI22X1TS U3703 ( .A0(d_ff3_LUT_out[5]), .A1(n2937), .B0(n2912), .B1(
d_ff3_sh_x_out[5]), .Y(n2899) );
NAND2X1TS U3704 ( .A(n2900), .B(n2899), .Y(n933) );
BUFX3TS U3705 ( .A(n2901), .Y(n2924) );
AOI22X1TS U3706 ( .A0(add_subt_module_intDX[17]), .A1(n2834), .B0(n2924),
.B1(d_ff2_X[17]), .Y(n2903) );
AOI22X1TS U3707 ( .A0(n2944), .A1(d_ff2_Z[17]), .B0(n2912), .B1(d_ff2_Y[17]),
.Y(n2902) );
NAND2X1TS U3708 ( .A(n2903), .B(n2902), .Y(n931) );
AOI22X1TS U3709 ( .A0(add_subt_module_intDY[17]), .A1(n2857), .B0(n2924),
.B1(d_ff3_sh_y_out[17]), .Y(n2906) );
AOI22X1TS U3710 ( .A0(n2944), .A1(d_ff3_LUT_out[17]), .B0(n2912), .B1(
d_ff3_sh_x_out[17]), .Y(n2905) );
NAND2X1TS U3711 ( .A(n2906), .B(n2905), .Y(n930) );
AOI22X1TS U3712 ( .A0(add_subt_module_intDX[4]), .A1(n2904), .B0(n2924),
.B1(d_ff2_X[4]), .Y(n2909) );
AOI22X1TS U3713 ( .A0(n2944), .A1(d_ff2_Z[4]), .B0(n2912), .B1(d_ff2_Y[4]),
.Y(n2908) );
NAND2X1TS U3714 ( .A(n2909), .B(n2908), .Y(n927) );
AOI22X1TS U3715 ( .A0(add_subt_module_intDY[4]), .A1(n2929), .B0(n2924),
.B1(d_ff3_sh_y_out[4]), .Y(n2911) );
AOI22X1TS U3716 ( .A0(d_ff3_LUT_out[4]), .A1(n2937), .B0(n2912), .B1(
d_ff3_sh_x_out[4]), .Y(n2910) );
NAND2X1TS U3717 ( .A(n2911), .B(n2910), .Y(n926) );
AOI22X1TS U3718 ( .A0(add_subt_module_intDX[16]), .A1(n2857), .B0(n2924),
.B1(d_ff2_X[16]), .Y(n2915) );
AOI22X1TS U3719 ( .A0(n2913), .A1(d_ff2_Z[16]), .B0(n2912), .B1(d_ff2_Y[16]),
.Y(n2914) );
NAND2X1TS U3720 ( .A(n2915), .B(n2914), .Y(n924) );
AOI22X1TS U3721 ( .A0(add_subt_module_intDY[16]), .A1(n2904), .B0(n2924),
.B1(d_ff3_sh_y_out[16]), .Y(n2917) );
BUFX3TS U3722 ( .A(n2949), .Y(n2936) );
AOI22X1TS U3723 ( .A0(n2944), .A1(d_ff3_LUT_out[16]), .B0(n2936), .B1(
d_ff3_sh_x_out[16]), .Y(n2916) );
NAND2X1TS U3724 ( .A(n2917), .B(n2916), .Y(n923) );
AOI22X1TS U3725 ( .A0(add_subt_module_intDX[10]), .A1(n2834), .B0(n2924),
.B1(d_ff2_X[10]), .Y(n2919) );
AOI22X1TS U3726 ( .A0(n2944), .A1(d_ff2_Z[10]), .B0(n2936), .B1(d_ff2_Y[10]),
.Y(n2918) );
NAND2X1TS U3727 ( .A(n2919), .B(n2918), .Y(n920) );
AOI22X1TS U3728 ( .A0(add_subt_module_intDY[10]), .A1(n2857), .B0(n2924),
.B1(d_ff3_sh_y_out[10]), .Y(n2921) );
AOI22X1TS U3729 ( .A0(n2944), .A1(d_ff3_LUT_out[10]), .B0(n2936), .B1(
d_ff3_sh_x_out[10]), .Y(n2920) );
NAND2X1TS U3730 ( .A(n2921), .B(n2920), .Y(n919) );
AOI22X1TS U3731 ( .A0(add_subt_module_intDX[14]), .A1(n2904), .B0(n2924),
.B1(d_ff2_X[14]), .Y(n2923) );
AOI22X1TS U3732 ( .A0(n2937), .A1(d_ff2_Z[14]), .B0(n2936), .B1(d_ff2_Y[14]),
.Y(n2922) );
NAND2X1TS U3733 ( .A(n2923), .B(n2922), .Y(n917) );
AOI22X1TS U3734 ( .A0(add_subt_module_intDY[14]), .A1(n2929), .B0(n2924),
.B1(d_ff3_sh_y_out[14]), .Y(n2926) );
AOI22X1TS U3735 ( .A0(d_ff3_LUT_out[14]), .A1(n2940), .B0(n2936), .B1(
d_ff3_sh_x_out[14]), .Y(n2925) );
NAND2X1TS U3736 ( .A(n2926), .B(n2925), .Y(n916) );
AOI22X1TS U3737 ( .A0(add_subt_module_intDX[7]), .A1(n2857), .B0(n2947),
.B1(d_ff2_X[7]), .Y(n2928) );
AOI22X1TS U3738 ( .A0(n2937), .A1(d_ff2_Z[7]), .B0(n2936), .B1(d_ff2_Y[7]),
.Y(n2927) );
NAND2X1TS U3739 ( .A(n2928), .B(n2927), .Y(n913) );
AOI22X1TS U3740 ( .A0(add_subt_module_intDY[7]), .A1(n2834), .B0(n2947),
.B1(d_ff3_sh_y_out[7]), .Y(n2931) );
AOI22X1TS U3741 ( .A0(n2944), .A1(d_ff3_LUT_out[7]), .B0(n2936), .B1(
d_ff3_sh_x_out[7]), .Y(n2930) );
NAND2X1TS U3742 ( .A(n2931), .B(n2930), .Y(n912) );
AOI22X1TS U3743 ( .A0(add_subt_module_intDX[11]), .A1(n2817), .B0(n2947),
.B1(d_ff2_X[11]), .Y(n2933) );
AOI22X1TS U3744 ( .A0(n2937), .A1(d_ff2_Z[11]), .B0(n2936), .B1(d_ff2_Y[11]),
.Y(n2932) );
NAND2X1TS U3745 ( .A(n2933), .B(n2932), .Y(n910) );
AOI22X1TS U3746 ( .A0(add_subt_module_intDY[11]), .A1(n2943), .B0(n2947),
.B1(d_ff3_sh_y_out[11]), .Y(n2935) );
AOI22X1TS U3747 ( .A0(n2937), .A1(d_ff3_LUT_out[11]), .B0(n2936), .B1(
d_ff3_sh_x_out[11]), .Y(n2934) );
NAND2X1TS U3748 ( .A(n2935), .B(n2934), .Y(n909) );
AOI22X1TS U3749 ( .A0(add_subt_module_intDX[12]), .A1(n2943), .B0(n2947),
.B1(d_ff2_X[12]), .Y(n2939) );
AOI22X1TS U3750 ( .A0(n2937), .A1(d_ff2_Z[12]), .B0(n2936), .B1(d_ff2_Y[12]),
.Y(n2938) );
NAND2X1TS U3751 ( .A(n2939), .B(n2938), .Y(n907) );
AOI22X1TS U3752 ( .A0(add_subt_module_intDY[12]), .A1(n2943), .B0(n2947),
.B1(d_ff3_sh_y_out[12]), .Y(n2942) );
AOI22X1TS U3753 ( .A0(d_ff3_LUT_out[12]), .A1(n2940), .B0(n2949), .B1(
d_ff3_sh_x_out[12]), .Y(n2941) );
NAND2X1TS U3754 ( .A(n2942), .B(n2941), .Y(n906) );
AOI22X1TS U3755 ( .A0(add_subt_module_intDX[9]), .A1(n2943), .B0(n2947),
.B1(d_ff2_X[9]), .Y(n2946) );
AOI22X1TS U3756 ( .A0(n2944), .A1(d_ff2_Z[9]), .B0(n2949), .B1(d_ff2_Y[9]),
.Y(n2945) );
NAND2X1TS U3757 ( .A(n2946), .B(n2945), .Y(n903) );
AOI22X1TS U3758 ( .A0(add_subt_module_intDY[9]), .A1(n2948), .B0(n2947),
.B1(d_ff3_sh_y_out[9]), .Y(n2952) );
AOI22X1TS U3759 ( .A0(n2950), .A1(d_ff3_LUT_out[9]), .B0(n2949), .B1(
d_ff3_sh_x_out[9]), .Y(n2951) );
NAND2X1TS U3760 ( .A(n2952), .B(n2951), .Y(n902) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_9_0,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_9_0,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=16,DIN_FROM=15,DIN_TO=15}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_9_0 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/*******************************************************************************
*
* FILENAME: B_DMA_UART_v0_1.v
* COMPONENT NAME: B_DMA_UART_v0_1
* Version `$CY_MAJOR_VERSION`.`$CY_MINOR_VERSION`
*
* Description:
* This file provides a top level model of the Base UART user module
* defining the controller and datapath instances and all of the necessary
* interconnect, for the RX and TX components individually. This allows
* for a lot of flexibility in how big the design can be and puts all of
* the code in a single file for easy maintenance.
*
********************************************************************************
* Control and Status Register definitions
********************************************************************************
* Control Register Definition
* +======+------+------+------+-------+-------+------+----------+--------+
* | Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* +======+------+------+------+-------+-------+------+----------+--------+
* | Desc |ADDRM2|ADDRM1|ADDRM0|PARITY1|PARITY0| MARK |SEND_BREAK| HD_SEND|
* +======+------+------+------+-------+-------+------+----------+--------+
*
* HD_SEND => Used for dynamically reconfiguration RX or TX operation in
* Half Duplex mode.
* 0 = RX operation HD mode
* 1 = TX operation HD mode
* SEND_BREAK => 1 = Sends Break signal in HD mode and release Parity bit
* for Break signal in TX mode.
* MARK => 0 = sets space(0) in Parity bit location.
* 1 = sets mark(1) in Parity bit location.
* PARITY0/1 => 0 = NONE
* 1 = EVEN
* 2 = ODD
* 3 = MRKSPC
* ADDRM0/1/2 => The RX address mode control is a 3-bit field used to define
* the expected hardware addressing operation.
* 0 = NONE
* 1 = SW_BYTE_BYTE
* 2 = SW_DET_BUFFER
* 3 = HW_BYTE_BYTE
* 4 = HW_DET_BUFFER
*
********************************************************************************
* TX Data Path register definitions
********************************************************************************
*
* INSTANCE NAME: dpTXShifter
*
* DESCRIPTION:
* Data Shifter for the TX portion of the UART.
*
* REGISTER USAGE:
* F0 => Data to be sent
* F1 => Unused
* D0 => Unused
* D1 => Unused
* A0 => Data as it is shifted out
* A1 => Unused
*
* Data Path States
* (0bit generated on Count7/DP clock divider, 1,2Bit from Sate Machine)
* 0 0 0 0 Idle
* 0 0 1 1 Idle
* 0 1 0 2 Idle
* 0 1 1 3 Send Start Bit (F0 -> A0)
* 1 0 0 4 Idle
* 1 0 1 5 Send Data Bits (A0>>)
* 1 1 0 6 Idle
* 1 1 1 7 Idle (Send Parity/Stop Bits)
*
********************************************************************************
*
* INSTANCE NAME: dpTXBitClkGen
*
* DESCRIPTION:
* Bit Enable Generator for the TX implemented on Data Path.
*
* REGISTER USAGE:
* F0 => Unused
* F1 => Unused
* D0 => Bit length
* D1 => Period
* A0 => Counter
* A1 => Unused
*
* Data Path States
* 0 0 0 0 Counter load (A0 = 0)
* 0 0 1 1 Count (A0++)
*
********************************************************************************
* TX 7-Bit Counter Implementation Description
********************************************************************************
*
* INSTANCE NAME: TXBitCounter
*
* DESCRIPTION:
* Bit Enable Generator and Bit Counter rolled into a 7-Bit Counter. Requires
* a period of the number of bits (+1 for the start bit) times the oversample
* rate of 8 or 16-bits. It is required to use 8 or 16-bit oversampling
* because the lower 3 or 4 bits of the counter are masked and compared to zero
* to generate the bit enable. Terminal count of the counter defines the end
* of a packet before Parity and Stop Bits are sent.
*
* REGISTER USAGE:
* PERIOD => ((NumBits + 1) * (OverSample Rate)) - 1
*
********************************************************************************
* RX Data Path register definitions
********************************************************************************
*
* INSTANCE NAME: dpRXShifter
*
* DESCRIPTION:
* Data Shifter for the RX portion of the UART. Half Duplex mode is
* implemented on this Data Path.
*
* REGISTER USAGE:
* F0 => Data just received
* F1 => Data to be sent(Half duplex send)
* D0 => Address 1
* D1 => Address 2
* A0 => Data as it is shifted in
* A1 => Data as it is shifted out (Half duplex send)
*
* Data Path States
* (0bit generated on RXBitCounter clock divider, 1,2Bit from Sate Machine)
* ADD 2 1 0 Bits cs_addr
* 0 0 0 0 X Idle
* RX Stages:
* 0 1 0 0 X Check Start
* 0 0 0 1 0 Idle
* 0 0 0 1 1 Get Data Bits (A0>>)
* 1 0 0 0 X Get Parity Bit
* 1 1 0 0 X Check Stop Bit (A0 -> F0)
* 0 1 1 1 X Check Break Signal (A1>> - does not take effect in RX mode)
* TX Stage for Half Duplex mode(HD_SEND = 1):
* 0 0 1 0 0 Idle
* 0 0 1 0 1 Send Start Bit (F1 -> A1)
* 0 0 1 1 0 Idle
* 0 0 1 1 1 Send Data Bits (A1>>)
* 1 0 0 0 X Send Parity Bit
* 0 1 1 1 X Send Stop 1 Bit
* 0 1 0 0 X Send Stop 2 Bit
*
********************************************************************************
* RX 7-Bit Counter Implementation Description
********************************************************************************
*
* INSTANCE NAME: RXBitCounter
*
* DESCRIPTION:
* Bit Enable Generator and Bit Counter rolled into a 7-Bit Counter.
*
* REGISTER USAGE:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
`include "cypress.v"
`ifdef B_DMA_UART_v0_1_V_ALREADY_INCLUDED
`else
`define B_DMA_UART_v0_1_V_ALREADY_INCLUDED
module B_DMA_UART_v0_1
(
input wire clock, /* User Supplied Clock = 8x or 16x the bit-rate depends on OverSampleCount parameter */
input wire reset, /* System Global Reset */
input wire rx, /* Receive: Serial Data Input */
output wire tx, /* Transmit: Serial Data Output */
output wire rx_interrupt, /* Interrupt output from the RX section */
output wire tx_interrupt, /* Interrupt output from the TX section */
output wire rx_drq, /* DMA request output */
output wire tx_drq, /* DMA request output */
output wire rx_break, /* Receive Break Signal output */
output wire tx_complete, /* Transmit Complete Signal output */
output wire rts_n, /* Request to send output for Flow control */
input wire cts_n, /* Clear to send input for Flow control */
output reg tx_en, /* Transmit Enable: Hardware control line output */
output reg tx_data, /* Transmit Data: shift out the TX data to a CRC component or other logic */
output reg tx_clk, /* Transmit Clock: Provides clock edge used to shift out the TX data */
output reg rx_data, /* Receive Data: shift out the RX data to a CRC component or other logic */
output reg rx_clk /* Receive Clock: Provides clock edge used to shift out the RX data */
);
/*************************************************************************
* Parameters *
*************************************************************************/
/* Constants for NumStopBits parameter */
localparam UART_NUM_STOP_BITS_1 = 2'd1;
localparam UART_NUM_STOP_BITS_2 = 2'd2;
/* Constants for OverSampleCount parameter */
localparam UART_OVER_SAMPLE_8 = 7'd8;
localparam UART_OVER_SAMPLE_16 = 7'd16;
/* Constants for ParityType parameter */
localparam UART_PARITY_TYPE_NONE = 2'd0;
localparam UART_PARITY_TYPE_EVEN = 2'd1;
localparam UART_PARITY_TYPE_ODD = 2'd2;
localparam UART_PARITY_TYPE_MRKSPC = 2'd3;
/* Constants for RXAddressMode parameter */
localparam UART_RX_ADDR_MODE_NONE = 3'd0;
localparam UART_RX_ADDR_MODE_SW_BYTE_BYTE = 3'd1;
localparam UART_RX_ADDR_MODE_SW_DET_BUFFER = 3'd2;
localparam UART_RX_ADDR_MODE_HW_BYTE_BYTE = 3'd3;
localparam UART_RX_ADDR_MODE_HW_DET_BUFFER = 3'd4;
localparam NUM_START_BITS = 4'd1; /* UART alwas uses one start bit */
localparam NUM_C7_MAX_BITS_O16 = 4'd8; /* max count for count7 at 16x oversample */
/* These parameters will set by the software */
parameter ParityType = UART_PARITY_TYPE_NONE; /* Set the Parity Type as Odd, Even or Mark/Space */
parameter ParityTypeSw = 1'b0; /* Makes Parity Type changeable by Control Register */
parameter FlowControl = 1'b0; /* Enable Flow Control Signals */
parameter HwTXEnSignal = 1'b0; /* Enable the external TX Enable Signal output */
parameter RXEnable = 1'b1; /* Enable RX portion of the UART */
parameter TXEnable = 1'b1; /* Enable TX portion of the UART */
parameter HalfDuplexEn = 1'b0; /* Enable Half Duplex mode: RX+TX portions on the RX only hardware */
parameter CRCoutputsEn = 1'b0; /* Enable CRC outputs */
parameter RXStatusIntEnable = 1'b0; /* Enable Interrupts from status register: not used */
parameter RXAddressMode = UART_RX_ADDR_MODE_NONE; /* Configure RX Hardware Address Detection Scheme */
parameter Address1 = 8'd0; /* RX Hardware Address #1 */
parameter Address2 = 8'd0; /* RX Hardware Address #2 */
parameter NumDataBits = 4'd8; /* Define the Number of Data Bits 5-9 */
parameter NumStopBits = UART_NUM_STOP_BITS_1; /* Define the Number of Stop Bits 1-2*/
parameter OverSampleCount = UART_OVER_SAMPLE_8; /* Allows Oversampling of 8 or 16 */
parameter Use23Polling = 1'b1; /* Use 2 of 3 polling on the RX UART sampler */
parameter TXBitClkGenDP = 1'b1; /* Use datapath for clock generation if enabled, otherwise Count7 */
parameter BreakDetect = 1'b0; /* Enable Break Signal generation and detection */
parameter BreakBitsTX = 7'd13; /* Set Break signal length in bits for TX */
parameter BreakBitsRX = 7'd13; /* Set Break signal length in bits for RX */
/* Polling require to start sampling on 1 bits before */
localparam [3:0] HalfBitCounts = ((OverSampleCount / 4'd2) + (Use23Polling * 4'd1) - 4'd2);
/* Truncating NumDataBits. UART shifts max 8 bits, Mark/Space functionality working if 9 bits selected */
localparam [3:0] FinalNumDataBits = (NumDataBits > 8) ? 4'd8 : NumDataBits;
/* TX Count7 period: calculated always for oversample 8, enable input used for oversample 16 */
localparam [6:0] txperiod_init = ((FinalNumDataBits + NUM_START_BITS) * UART_OVER_SAMPLE_8) - 7'd1;
/* Init RX counter for break detect time, rewritten @ HD mode by LoadRx(Tx) Cofig API */
/* This parameter is increased on the 2 in 2 out of 3 mode to sample voting in the middle */
localparam [6:0] rxperiod_init = (OverSampleCount == UART_OVER_SAMPLE_8) ?
((BreakBitsRX + NUM_START_BITS) * OverSampleCount) + (HalfBitCounts - 1) :
/* 7bit counter need one more bit for OverSampleCount=16 */
((NUM_C7_MAX_BITS_O16 - 1) * OverSampleCount) + (HalfBitCounts - 1);
/* need to use additional bit for count7 at 16x oversample*/
localparam rxperiod_cmp_need_one_bit = ((OverSampleCount == UART_OVER_SAMPLE_16) && (FinalNumDataBits > 6)) ?
1'd1 : 1'd0;
/* This parameter used in RX State machine to define that all predefined data bits received */
localparam [6:0] rxperiod_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ?
BreakBitsRX + NUM_START_BITS - FinalNumDataBits :
/* for 16 OverSample*/
rxperiod_cmp_need_one_bit ? (NUM_C7_MAX_BITS_O16 - 1) * 2 - FinalNumDataBits
: (NUM_C7_MAX_BITS_O16 - 1) - FinalNumDataBits;
/* This parameter used in RX State machine to define that all predefined break bits detected */
localparam [6:0] rxbreak_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? NUM_START_BITS :
/* Break at 16 OverSample always needs one more bit*/
(NUM_C7_MAX_BITS_O16 - 1) * 2 - BreakBitsRX + NUM_START_BITS;
/* This parameter used in TX State machine in HD mode to define that all predefined data bits received */
localparam [6:0] hd_txperiod_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? BreakBitsTX - FinalNumDataBits :
/* for 16 OverSample*/
rxperiod_cmp_need_one_bit ? NUM_C7_MAX_BITS_O16 * 2 - FinalNumDataBits - NUM_START_BITS
: NUM_C7_MAX_BITS_O16 - FinalNumDataBits - NUM_START_BITS;
/* This parameter used in TX State machine in HD mode to define that all predefined break bits detected */
localparam [6:0] hd_tx_break_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? NUM_START_BITS :
/* Break at 16 OverSample always needs one more bit*/
NUM_C7_MAX_BITS_O16 * 2 - BreakBitsTX;
/* Counter low position for compare */
localparam cl = (OverSampleCount == UART_OVER_SAMPLE_8) ? 3'd3 : 3'd4;
/* Control Register bit locations */
localparam UART_CTRL_HD_SEND = 3'd0;
localparam UART_CTRL_HD_SEND_BREAK = 3'd1; /* HD_SEND_BREAK - sends break bits in HD mode*/
/* HD_SEND_BREAK - skip to send parity bit @ Break signal in Full Duplex mode*/
localparam UART_CTRL_MARK = 3'd2; /* 1 sets mark, 0 sets space */
localparam UART_CTRL_PARITYTYPE0 = 3'd3; /* Defines the type of parity implemented */
localparam UART_CTRL_PARITYTYPE1 = 3'd4; /* Defines the type of parity implemented */
localparam UART_CTRL_RXADDR_MODE0 = 3'd5;
localparam UART_CTRL_RXADDR_MODE1 = 3'd6;
localparam UART_CTRL_RXADDR_MODE2 = 3'd7;
localparam UART_RX_CTRL_ADDR_MODE_NONE = 3'd0;
localparam UART_RX_CTRL_ADDR_MODE_SW_BYTE_BYTE = 3'd1;
localparam UART_RX_CTRL_ADDR_MODE_SW_DET_BUFFER = 3'd2;
localparam UART_RX_CTRL_ADDR_MODE_HW_BYTE_BYTE = 3'd3;
localparam UART_RX_CTRL_ADDR_MODE_HW_DET_BUFFER = 3'd4;
/***************************************************************************
* Instantiation of udb_clock_enable primitive
****************************************************************************
* The udb_clock_enable primitive component allows to support clock enable
* mechanism and specify the intended synchronization behaviour for the clock
* result (operational clock).
* There is no need to reset or enable this component. In this case the
* udb_clock_enable is used only for synchronization. The resulted clock is
* always enabled.
*/
wire clock_op; /* internal clock to drive the component */
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
/* input */ .clock_in(clock),
/* input */ .enable(1'b1),
/* output */ .clock_out(clock_op)
);
/**************************************************************************
* Control Register Implementation
**************************************************************************/
wire [7:0] control; /* UART Control Register */
generate
if( ((ParityType == UART_PARITY_TYPE_MRKSPC) && TXEnable) ||
((ParityType != UART_PARITY_TYPE_NONE) && TXEnable && BreakDetect) || ParityTypeSw ||
((RXAddressMode != UART_RX_ADDR_MODE_NONE) && RXEnable) || HalfDuplexEn )
begin : sCR_SyncCtl
cy_psoc3_control #(.cy_force_order(1), .cy_ctrl_mode_1(8'h0), .cy_ctrl_mode_0(8'hFF)) CtrlReg
(
/* input */ .clock(clock_op),
/* output [07:00] */ .control(control)
);
end /* sCR_SyncCtl */
endgenerate
/**************************************************************************/
/* Reset signal synchronization for Count7 usage */
/**************************************************************************/
reg reset_reg;
always @(posedge clock_op)
begin
reset_reg <= reset;
end
wire tx_hd_send_break =
((((ParityType != UART_PARITY_TYPE_NONE) || ParityTypeSw) && TXEnable && BreakDetect) || HalfDuplexEn) ?
control[UART_CTRL_HD_SEND_BREAK] : 1'b0;
wire HalfDuplexSend = HalfDuplexEn ? control[UART_CTRL_HD_SEND] : 1'b0;
wire [1:0] FinalParityType = ParityTypeSw ?
{control[UART_CTRL_PARITYTYPE1], control[UART_CTRL_PARITYTYPE0]} : ParityType;
wire [2:0] FinalAddrMode = (RXAddressMode != UART_RX_ADDR_MODE_NONE) ?
{control[UART_CTRL_RXADDR_MODE2], control[UART_CTRL_RXADDR_MODE1], control[UART_CTRL_RXADDR_MODE0]} :
RXAddressMode;
reg tx_mark;
reg tx_ctrl_mark_last;
wire tx_ctrl_mark = ((ParityType == UART_PARITY_TYPE_MRKSPC) || ParityTypeSw) ? control[UART_CTRL_MARK] : 1'b0;
/**************************************************************************/
/* Reset signal for DP and Status Register is available from ES3 silicon */
/* It is required to clear SR when direction changed in HD mode */
/**************************************************************************/
reg HalfDuplexSend_last;
wire reset_sr = (HalfDuplexSend ^ HalfDuplexSend_last) | reset_reg;
if(HalfDuplexEn)
begin
always @(posedge clock_op)
begin
HalfDuplexSend_last <= HalfDuplexSend;
end
end
/**************************************************************************
* txn is the inverted version of tx. The default output for a UART should
* be one. In order to get a one value out at time zero when all flip-flops
* are initialized to zero, txn is registered and then inverted when driven
* to the pin.
**************************************************************************/
reg txn;
assign tx = ~txn;
/* interrupts implementation */
wire tx_interrupt_out;
wire rx_interrupt_out;
assign tx_interrupt = TXEnable ? tx_interrupt_out : 1'b0;
assign rx_interrupt = (RXEnable || HalfDuplexEn) ? rx_interrupt_out : 1'b0;
/* DMA implementation */
wire tx_drq_out;
wire rx_drq_out;
assign tx_drq = TXEnable ? tx_drq_out : 1'b0;
assign rx_drq = (RXEnable || HalfDuplexEn) ? rx_drq_out : 1'b0;
/* Status Signal implementation */
wire tx_complete_out;
wire rx_break_out;
assign tx_complete = TXEnable ? tx_complete_out : 1'b0;
assign rx_break = (RXEnable || HalfDuplexEn) ? rx_break_out : 1'b0;
/**************************************************************************
* UART TX Implementation *
**************************************************************************/
generate
if (TXEnable == 1) begin : sTX
wire [6:0] tx_status; /* Transmit portion of the UART Status Register */
wire tx_fifo_empty; /* Transmitter FIFO Empty status line from FIFO -
used for flow control of data ready to send */
wire tx_fifo_notfull; /* Transmitter FIFO not full status line from FIFO -
Firmware should check the status bit FIFO_FULL before writing more data */
reg tx_parity_bit; /* Transmitter Parity Bit container (sent on TX during parity bit state) */
reg tx_bitclk; /* 1/8 or 1/16 of system clock */
wire tx_bitclk_dp;
wire tx_counter_tc; /* End of data shifting */
wire tx_counter_dp;
wire tx_bitclk_enable_pre; /* Transmitter Enable (1/8 or 1/16 system clock) used for cs_addr[0]*/
reg [2:0] tx_state; /* Transmit State Machine State Container */
/* TX State Machine States: */
localparam UART_TX_STATE_IDLE = 3'd0;
localparam UART_TX_STATE_SEND_START = 3'd1;
localparam UART_TX_STATE_SEND_DATA = 3'd2;
localparam UART_TX_STATE_SEND_PARITY = 3'd3;
localparam UART_TX_STATE_SEND_STOP1 = 3'd4;
localparam UART_TX_STATE_SEND_STOP2 = 3'd7;
localparam UART_TX_STATE_SEND_STOP = (NumStopBits == UART_NUM_STOP_BITS_1) ?
UART_TX_STATE_SEND_STOP1 : UART_TX_STATE_SEND_STOP2;
/* TX Shifter Datapath Configuration */
localparam UART_TX_SHIFTER_DP_CONFIG =
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: SEND START */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: SEND DATA (SR) */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: SEND LAST BIT(PARITY/STOP1/2) */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SR, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0_BUS,
`SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* TX Shifter Datapath */
cy_psoc3_dp8 #(.cy_dpconfig_a(UART_TX_SHIFTER_DP_CONFIG)) TxShifter
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({tx_state[1],tx_state[0],tx_bitclk_enable_pre}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(tx_shift_out),
/* output */ .f0_bus_stat(tx_fifo_notfull), /*FIFO is not full when bus_stat = 1;*/
/* output */ .f0_blk_stat(tx_fifo_empty), /*FIFO is empty when blk_stat = 1;*/
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
wire [6:0] txbitcount;
wire tx_bitclk_half;
wire tx_count7_enable;
reg clock2; /* 1/2 system clock for oversample*16 */
/* 8x or 16x clock divider implemented on Count7 */
if(TXBitClkGenDP == 0)
begin : sCLOCK
wire counter_load = (tx_state == UART_TX_STATE_IDLE) || (tx_bitclk && (tx_state == UART_TX_STATE_SEND_STOP));
if( (OverSampleCount == UART_OVER_SAMPLE_16) )
begin
/* Count7 enable implementation to work on 1/2 system clock */
always @(posedge clock_op)
begin
if(counter_load)
begin
clock2 <= 1'b0;
end
else
begin
clock2 <= !clock2;
end
end
assign tx_count7_enable = clock2 | counter_load; /* EN must be high for LD effect */
/* Generate tx_bitclk one clock cycle sooner in STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
assign tx_bitclk_enable_pre = (txbitcount[2:0] == 3'd0) && ((tx_state == UART_TX_STATE_SEND_STOP) ?
(!tx_count7_enable) : (tx_count7_enable));
end
else
begin
assign tx_count7_enable = 1'b1;
assign tx_bitclk_enable_pre = ((tx_state == UART_TX_STATE_SEND_STOP) ?
(txbitcount[2:0] == 3'd1) : (txbitcount[2:0] == 3'd0));
end
cy_psoc3_count7 #(.cy_period(txperiod_init),.cy_route_ld(1),.cy_route_en(1)) TxBitCounter
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input */ .load(counter_load),
/* input */ .enable(tx_count7_enable),
/* output [06:00] */ .count(txbitcount),
/* output */ .tc(tx_counter_tc)
);
if(CRCoutputsEn)
begin
assign tx_bitclk_half = !txbitcount[2]; /* txbitcount[2:0] == 3'd2;*/
end
end
/* 8x or 16x clock divider implemented on Datapath */
else
begin : sCLOCK
wire [7:0] sc_out;
wire counter_load_not = !((tx_state == UART_TX_STATE_IDLE) || (tx_bitclk_enable_pre &&
(tx_state == UART_TX_STATE_SEND_STOP)));
localparam [7:0] dpTXBitClkGenCmask0 = OverSampleCount - 1;
/* TX Bit Clk Datapath Configuration */
localparam UART_TX_BIT_CLK_DP_CONFIG =
{
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Counter load (A0 = 0)*/
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Count (A0++)*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, dpTXBitClkGenCmask0, /*CFG11-10: dpTXBitClkGenCmask0 = OverSampleCount-1 */
`SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_ENBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0__A0,
`SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* TX Bit Clk Datapath */
cy_psoc3_dp #(.cy_dpconfig(UART_TX_BIT_CLK_DP_CONFIG)) TxBitClkGen
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({2'b0,counter_load_not}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0_reg(tx_bitclk_dp),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1_reg(tx_counter_dp),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0), /* Carry in from previous stage */
/* output */ .co(), /* Carry out to next stage */
/* input */ .sir(1'b0), /* Shift in from right side */
/* output */ .sor(), /* Shift out to right side */
/* input */ .sil(1'b0), /* Shift in from left side */
/* output */ .sol(), /* Shift out to left side */
/* input */ .msbi(1'b0), /* MSB chain in */
/* output */ .msbo(), /* MSB chain out */
/* input [01:00] */ .cei(2'b0), /* Compare equal in from prev stage */
/* output [01:00] */ .ceo(), /* Compare equal out to next stage */
/* input [01:00] */ .cli(2'b0), /* Compare less than in from prv stage */
/* output [01:00] */ .clo(), /* Compare less than out to next stage */
/* input [01:00] */ .zi(2'b0), /* Zero detect in from previous stage */
/* output [01:00] */ .zo(), /* Zero detect out to next stage */
/* input [01:00] */ .fi(2'b0), /* 0xFF detect in from previous stage */
/* output [01:00] */ .fo(), /* 0xFF detect out to next stage */
/* input [01:00] */ .capi(2'b0), /* Software capture from previous stage */
/* output [01:00] */ .capo(), /* Software capture to next stage */
/* input */ .cfbi(1'b0), /* CRC Feedback in from previous stage */
/* output */ .cfbo(), /* CRC Feedback out to next stage */
/* input [07:00] */ .pi(8'b0), /* Parallel data port */
/* output [07:00] */ .po(sc_out[7:0]) /* Parallel data port */
);
assign tx_counter_tc = tx_counter_dp;
assign tx_bitclk_enable_pre = tx_bitclk_dp;
if(CRCoutputsEn)
begin
assign tx_bitclk_half = sc_out[cl-1];
end
end
/* TX Status Register bit locations */
localparam UART_TX_STS_TX_COMPLETE = 3'h0;
localparam UART_TX_STS_TX_BUFF_EMPTY = 3'h1;
localparam UART_TX_STS_TX_FIFO_FULL = 3'h2;
localparam UART_TX_STS_TX_FIFO_NOT_FULL = 3'h3;
assign tx_status[6:4] = 3'b0;
if(TXBitClkGenDP == 0)
begin
assign tx_status[UART_TX_STS_TX_COMPLETE] = tx_fifo_empty & tx_bitclk & (tx_state == UART_TX_STATE_SEND_STOP);
end
else
begin
assign tx_status[UART_TX_STS_TX_COMPLETE] = tx_fifo_empty & tx_bitclk_enable_pre &
(tx_state == UART_TX_STATE_SEND_STOP);
end
assign tx_status[UART_TX_STS_TX_BUFF_EMPTY] = tx_fifo_empty;
assign tx_status[UART_TX_STS_TX_FIFO_FULL] = !tx_fifo_notfull;
assign tx_status[UART_TX_STS_TX_FIFO_NOT_FULL] = tx_fifo_notfull;
/* Instantiate the status register and interrupt hook*/
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h01), .cy_int_mask(7'h7F)) TxSts
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input [06:00] */ .status(tx_status),
/* output */ .interrupt(tx_interrupt_out)
);
assign tx_drq_out = tx_status[UART_TX_STS_TX_FIFO_NOT_FULL];
assign tx_complete_out = tx_status[UART_TX_STS_TX_COMPLETE];
/**************************************************************************/
/* Registering tx_en for removing possible glitches */
/**************************************************************************/
always @(posedge clock_op)
begin
if(reset_reg)
begin
tx_en <= 1'b0;
end
else
begin
tx_en <= (HwTXEnSignal & (tx_state != UART_TX_STATE_IDLE)) ? 1'b1 : 1'b0;
end
end
/* CRC outputs implementation
* tx_clk and tx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((tx_state == UART_TX_STATE_SEND_DATA) & !reset_reg)
begin
tx_clk <= tx_bitclk_half;
tx_data <= ~txn;
end
else
begin
tx_clk <= 1'b0;
tx_data <= 1'b0;
end
end
end
always @(posedge clock_op)
begin
if(TXBitClkGenDP == 0)
begin
tx_bitclk <= tx_bitclk_enable_pre;
end
else
/* Do not generate tx_bitclk in last STOP state. Use tx_bitclk_pre instead
* to change state to START without time overhead
*/
begin
tx_bitclk <= tx_bitclk_enable_pre && (tx_state != UART_TX_STATE_SEND_STOP);
end
end
/* TX State machine*/
always @(posedge clock_op)
begin
if(FinalParityType == UART_PARITY_TYPE_MRKSPC)
begin
tx_ctrl_mark_last <= tx_ctrl_mark;
if(tx_ctrl_mark && !tx_ctrl_mark_last) /* Edge detector */
begin
tx_mark <= 1'b1;
end
end
if(reset_reg)
begin
tx_state <= UART_TX_STATE_IDLE;
txn <= 1'b0;
tx_mark <= 1'b0;
end
else
begin
case(tx_state)
UART_TX_STATE_IDLE:
begin
txn <= 1'b0;
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
end
UART_TX_STATE_SEND_START:
begin
txn <= 1'b1;
if(tx_bitclk)
begin
txn <= ~tx_shift_out;
if( (FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD) )
begin
tx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
end
tx_state <= UART_TX_STATE_SEND_DATA;
end
end
UART_TX_STATE_SEND_DATA:
begin
if(tx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD) )
begin
tx_parity_bit <= (tx_parity_bit ^ ~txn);
end
if(tx_counter_tc)
begin
if( ((FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD)) && !tx_hd_send_break )
begin
tx_state <= UART_TX_STATE_SEND_PARITY;
txn <= ~(tx_parity_bit ^ ~txn); /* +last bit */
end
else if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) && !tx_hd_send_break )
begin
tx_state <= UART_TX_STATE_SEND_PARITY;
txn <= ~tx_mark;
if(tx_mark)
begin
tx_mark <= 1'b0;
end
end
else
begin
tx_state <= UART_TX_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
else
begin
txn <= ~tx_shift_out;
end
end
end
UART_TX_STATE_SEND_PARITY:
begin
if(tx_bitclk)
begin
tx_state <= UART_TX_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
UART_TX_STATE_SEND_STOP1:
begin
/* Check tx_bitclk one clock cycle sooner in STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
if((TXBitClkGenDP == 0) ? tx_bitclk : tx_bitclk_enable_pre)
begin
if(NumStopBits == UART_NUM_STOP_BITS_1)
begin
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
else
begin
tx_state <= UART_TX_STATE_IDLE;
end
end
else
begin
tx_state <= UART_TX_STATE_SEND_STOP2;
end
end
end
UART_TX_STATE_SEND_STOP2:
begin
if((TXBitClkGenDP == 0) ? tx_bitclk : tx_bitclk_enable_pre)
begin
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
else
begin
tx_state <= UART_TX_STATE_IDLE;
end
end
end
endcase
end /* end of else statement */
end /* End of always block */
end /* End of TXEnable Generate Statement */
endgenerate /* sTX */
/**************************************************************
* UART RX Implementation *
* HALF DUPLEX mode implemented within RX *
**************************************************************/
/* RX Controller Logic */
generate
if (RXEnable || HalfDuplexEn)
begin:sRX
wire [6:0] rx_status; /* Receive portion of the UART Status Register */
reg [3:0] rx_state; /* Receive State Machine State Container */
reg rx_parity_bit;
reg rx_markspace_pre;
reg rx_markspace_status;
reg rx_address_detected; /* used in ADDR_MODE_HW_ mode for skip not addressed data */
reg rx_parity_error_pre; /* need for delay parity error to byte received interrupt */
reg rx_parity_error_status;
reg rx_break_status;
reg rx_addr_match_status;
reg rx_stop_bit_error;
reg rx_break_detect;
reg rx_last; /* used for start bit falling edge detection */
wire rx_postpoll;
reg rx_load_fifo;
wire rx_fifofull;
wire rx_fifonotempty;
wire rx_addressmatch1;
wire rx_addressmatch2;
wire [6:0] rx_count;
wire rx_counter_load;
wire rx_bitclk_pre;
reg rx_bitclk;
reg rx_state_stop1_reg;
/* Additional bit for count7 at 16xOverSample */
wire rx_count7_tc;
reg rx_count7_bit8;
wire rx_count7_bit8_wire;
wire rx_bitclk_pre16x;
wire rx_bitclk_enable;
wire rx_poll_bit1;
wire rx_poll_bit2;
/* One address supported in Half duplex mode */
wire rx_addressmatch = HalfDuplexEn ? rx_addressmatch1 : (rx_addressmatch1 | rx_addressmatch2);
/* RX State Machine States: */
/* Two low bits go to DP cs_addr[2,1] */
localparam UART_RX_STATE_IDLE = 4'h00;
localparam UART_RX_STATE_CHECK_START = 4'h04;
localparam UART_RX_STATE_GET_DATA = 4'h01;
localparam UART_RX_STATE_GET_PARITY = 4'h08;
localparam UART_RX_STATE_CHECK_STOP1 = 4'h0C;
localparam UART_RX_STATE_CHECK_BREAK = 4'h07;
localparam UART_HD_STATE_SEND_START = 4'h02;
localparam UART_HD_STATE_SEND_DATA = 4'h03;
localparam UART_HD_STATE_SEND_PARITY = UART_RX_STATE_GET_PARITY;
localparam UART_HD_STATE_SEND_STOP1 = UART_RX_STATE_CHECK_BREAK;
localparam UART_HD_STATE_SEND_STOP2 = UART_RX_STATE_CHECK_START;
localparam UART_HD_STATE_SEND_STOP = (NumStopBits == UART_NUM_STOP_BITS_1) ?
UART_HD_STATE_SEND_STOP1 : UART_HD_STATE_SEND_STOP2;
localparam [2:0] rxmsbsel = (FinalNumDataBits == 8) ? 3'd7 :
(FinalNumDataBits == 7) ? 3'd6 :
(FinalNumDataBits == 6) ? 3'd5 :
/*(FinalNumDataBits == 5)*/ 3'd4;
localparam [7:0] addressMask = (FinalNumDataBits == 8) ? 8'hFF :
(FinalNumDataBits == 7) ? 8'h7F :
(FinalNumDataBits == 6) ? 8'h3F :
/*(FinalNumDataBits == 5)*/ 8'h1F;
localparam [7:0] dataMask = (FinalNumDataBits == 8) ? 8'hFF :
(FinalNumDataBits == 7) ? 8'h7F :
(FinalNumDataBits == 6) ? 8'h3F :
/*(FinalNumDataBits == 5)*/ 8'h1F;
/* RX Shifter Datapath Configuration */
localparam UART_RX_SHIFTER_DP_CONFIG =
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: GET DATA (SR) */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: SEND START */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: SEND DATA (SR) */
dataMask, 8'h00, /*CFG9: */
8'hFF, addressMask, /*CFG11-10: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_ENBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: CMP A0 -D1 */
`SC_A0_SRC_ACC, `SC_SHIFT_SR, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_ENBL, rxmsbsel, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
cy_psoc3_dp8 #(.cy_dpconfig_a(UART_RX_SHIFTER_DP_CONFIG)) RxShifter
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({rx_state[1],rx_state[0],rx_bitclk_enable}),
/* input */ .route_si(rx_postpoll),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(rx_load_fifo),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(rx_addressmatch1),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(rx_addressmatch2),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(hd_shift_out),
/* output */ .f0_bus_stat(rx_fifonotempty), /* FIFO is not EMPTY */
/* output */ .f0_blk_stat(rx_fifofull), /* FIFO is FULL */
/* output */ .f1_bus_stat(hd_tx_fifo_notfull), /* FIFO is not full when bus_stat = 1; */
/* output */ .f1_blk_stat(hd_tx_fifo_empty) /* FIFO is empty when blk_stat = 1; */
);
if(HalfDuplexEn)
begin
assign rx_counter_load = (rx_state == UART_RX_STATE_IDLE) ||
(HalfDuplexSend & rx_bitclk & (rx_state == UART_HD_STATE_SEND_STOP));
/* Generate rx_bitclk one clock cycle sooner in HD STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
assign rx_bitclk_pre = ((rx_state == UART_HD_STATE_SEND_STOP) & HalfDuplexSend) ? (rx_count[cl-1:0] == 4'd1) :
(rx_count[cl-1:0] == 4'd0);
end
else
begin
assign rx_counter_load = (rx_state == UART_RX_STATE_IDLE);
assign rx_bitclk_pre = (rx_count[cl-1:0] == 4'd0);
end
assign rx_bitclk_pre16x = (rx_count[cl-1:0] == (HalfBitCounts)) ? 1'b1 : 1'b0;
cy_psoc3_count7 #(.cy_period(rxperiod_init),.cy_route_ld(1),.cy_route_en(1)) RxBitCounter
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input */ .load(rx_counter_load),
/* input */ .enable(1),
/* output [06:00] */ .count(rx_count),
/* output */ .tc(rx_count7_tc)
);
assign rx_count7_bit8_wire = (OverSampleCount == UART_OVER_SAMPLE_16) ? rx_count7_bit8 : 1'd0;
assign rx_bitclk_enable = !HalfDuplexSend ? rx_bitclk : rx_bitclk_pre;
always @(posedge clock_op)
begin
if( (OverSampleCount == UART_OVER_SAMPLE_16) && rx_count7_bit8 && !HalfDuplexSend)
begin
rx_bitclk <= rx_bitclk_pre16x; /* Count7 reloaded to start value and we don't need to skip half bit*/
end
else
begin
rx_bitclk <= rx_bitclk_pre;
end
rx_state_stop1_reg <= (rx_state != UART_RX_STATE_CHECK_STOP1);
end
/* This state machine counts only first two voting, the third goes directly from rx line */
if(Use23Polling)
begin : s23Poll
reg [1:0] pollcount;
wire pollingrange;
assign rx_poll_bit1 = rx_count7_bit8_wire ?
((rx_count[cl-1:0] == (HalfBitCounts + 4'd1)) ? 1'b1 : 1'b0) :
((rx_count[cl-1:0] == 4'd1) ? 1'b1 : 1'b0);
assign rx_poll_bit2 = rx_count7_bit8_wire ? rx_bitclk_pre16x : rx_bitclk_pre;
assign pollingrange = rx_poll_bit1 | rx_poll_bit2;
always @(posedge clock_op)
begin
if(reset_reg)
begin
pollcount <= 2'd0;
end
else
begin
if(pollingrange)
begin
if(rx)
begin
pollcount <= pollcount + 2'd1;
end
end
else
begin
pollcount <= 2'd0;
end
end
end
assign rx_postpoll = (pollcount < 2'd1) ? 1'b0 : ((pollcount < 2'd2) ? rx : 1'b1);
end
else
begin
assign rx_postpoll = rx;
end /* Use23Polling */
/* RX Status Register bit locations */
localparam UART_RX_STS_MRKSPC = 3'd0;
localparam UART_RX_STS_BREAK = 3'd1;
localparam UART_RX_STS_PAR_ERROR = 3'd2;
localparam UART_RX_STS_STOP_ERROR = 3'd3;
localparam UART_RX_STS_OVERRUN = 3'd4;
localparam UART_RX_STS_FIFO_NOTEMPTY = 3'd5;
localparam UART_RX_STS_ADDR_MATCH = 3'd6;
/* Address Modes define when this bit is set */
/* Address Mode 00 = Software Byte by Byte - Generate Interrupt when address byte detected */
/* Address Mode 01 = Software Address To Buffer - Generate Interrupt when Address byte detected */
/* Address mode 10 = Hardware Byte by Byte - Generate Interrupt when address byte is detected and matches
one of the addresses */
/* Address mode 10 = Hardware Address To Buffer - Generate Interrupt when address byte is detected and matches
one of the addresses */
/* BE NOTE: Adress2 not used in Half duplex mode as 6 only outputs per DP available */
if(HalfDuplexEn)
begin
/*UART_RX_STS_MRKSPC for RX or
UART_TX_STS_TX_COMPLETE for TX - generated at the end of Stop Bit */
assign rx_status[UART_RX_STS_MRKSPC] = HalfDuplexSend ? hd_tx_fifo_empty & rx_bitclk &
((NumStopBits == UART_NUM_STOP_BITS_1) ? (rx_state == UART_HD_STATE_SEND_STOP1) :
(rx_state == UART_HD_STATE_SEND_STOP2)) :
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? (1'b0) : rx_markspace_status;
/*UART_RX_STS_BREAK for RX or Break detect
UART_TX_STS_TX_BUFF_EMPTY for TX*/
assign rx_status[UART_RX_STS_BREAK] = HalfDuplexSend ? hd_tx_fifo_empty : BreakDetect ? rx_break_status : 1'b0 ;
/*UART_RX_STS_PAR_ERROR for RX Parity Error */
assign rx_status[UART_RX_STS_PAR_ERROR] = rx_parity_error_status;
/*UART_RX_STS_STOP_ERROR for RX or Framing error
UART_TX_STS_TX_FIFO_NOT_FULL for TX*/
assign rx_status[UART_RX_STS_STOP_ERROR] = rx_stop_bit_error;
assign rx_status[UART_RX_STS_OVERRUN] = rx_fifofull & rx_load_fifo;
/* FIFO_NOTEMPTY delayed to synchronize with errors for RX
UART_TX_STS_TX_FIFO_FULL for TX*/
assign rx_status[UART_RX_STS_FIFO_NOTEMPTY] = HalfDuplexSend ? !hd_tx_fifo_notfull :
rx_fifonotempty & rx_state_stop1_reg;
assign rx_status[UART_RX_STS_ADDR_MATCH] =
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? 1'b0 : rx_addr_match_status;
/**************************************************************************/
/* Registering tx_en for removing possible glitches */
/**************************************************************************/
always @(posedge clock_op)
begin
if(reset_reg)
begin
tx_en <= 1'b0;
end
else
begin
tx_en <= ( HwTXEnSignal && HalfDuplexSend && (rx_state != UART_RX_STATE_IDLE)) ? 1'b1 : 1'b0;
end
end
/* TX CRC outputs implementation
* tx_clk and tx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((rx_state == UART_HD_STATE_SEND_DATA) & !reset_reg)
begin
tx_clk <= (rx_count[cl-1:0] == ((OverSampleCount / 4'd2) - 4'd2));
tx_data <= ~txn;
end
else
begin
tx_clk <= 1'b0;
tx_data <= 1'b0;
end
end
end
end
else
begin
assign rx_status[UART_RX_STS_MRKSPC] = (FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? (1'b0) :
rx_markspace_status;
assign rx_status[UART_RX_STS_BREAK] = BreakDetect ? rx_break_status : 1'b0 ;/* Break detect */
assign rx_status[UART_RX_STS_PAR_ERROR] = rx_parity_error_status; /* Parity Error */
assign rx_status[UART_RX_STS_STOP_ERROR] = rx_stop_bit_error; /* Framing Error */
assign rx_status[UART_RX_STS_OVERRUN] = rx_fifofull & rx_load_fifo;
/* FIFO_NOTEMPTY delayed to synchronize with errors*/
assign rx_status[UART_RX_STS_FIFO_NOTEMPTY] = rx_fifonotempty & rx_state_stop1_reg;
assign rx_status[UART_RX_STS_ADDR_MATCH] =
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? 1'b0 : rx_addr_match_status;
end
assign rts_n = rx_fifofull;
/* RX CRC outputs implementation
* rx_clk and rx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((rx_state == UART_RX_STATE_GET_DATA) & !reset_reg)
begin
rx_clk <= Use23Polling ? rx_poll_bit2 : rx_bitclk;
rx_data <= rx;
end
else
begin
rx_clk <= 1'b0;
rx_data <= 1'b0;
end
end
end
/* Instantiate the status register and interrupt hook */
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h5F), .cy_int_mask(7'h7F)) RxSts
(
/* input */ .clock(clock_op),
/* input */ .reset(HalfDuplexEn ? reset_sr : reset_reg),
/* input [06:00] */ .status(rx_status),
/* output */ .interrupt(rx_interrupt_out)
);
assign rx_drq_out = rx_status[UART_RX_STS_FIFO_NOTEMPTY];
assign rx_break_out = rx_status[UART_RX_STS_BREAK];
/* RX State Machine */
always @(posedge clock_op)
begin
if(HalfDuplexEn && (FinalParityType == UART_PARITY_TYPE_MRKSPC))
begin
tx_ctrl_mark_last <= tx_ctrl_mark;
if(tx_ctrl_mark && !tx_ctrl_mark_last) /* Edge detector */
begin
tx_mark <= 1'b1;
end
end
rx_addr_match_status <= 1'b0;
rx_stop_bit_error <= 1'b0;
rx_markspace_status <= 1'b0;
rx_parity_error_status <= 1'b0;
rx_break_status <= 1'b0;
rx_load_fifo <= 1'b0;
if(reset_reg)
begin
rx_state <= UART_RX_STATE_IDLE;
rx_last <= 1'b0;
rx_address_detected <= 1'b0;
if(HalfDuplexEn)
begin
tx_mark <= 1'b0;
txn <= 1'b0;
end
if(OverSampleCount==UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 1'b0;
end
end
else
begin
rx_last <= rx;
if( (OverSampleCount == UART_OVER_SAMPLE_16) && !rx_count7_bit8 )
begin
if(rx_count7_tc)
begin
rx_count7_bit8 <= 1;
end
end
case(rx_state)
UART_RX_STATE_IDLE:
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
if(HalfDuplexEn)
begin
txn <= 1'b0;
end
if(HalfDuplexSend && HalfDuplexEn)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
rx_state <= UART_HD_STATE_SEND_START;
end
end
else if(~rx & rx_last) /* RX falling edge detection */
begin
rx_state <= UART_RX_STATE_CHECK_START;
end
end
UART_RX_STATE_CHECK_START: /* Check the start bit after 4 cycles */
begin
/*UART_HD_STATE_SEND_STOP2 in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
rx_state <= UART_HD_STATE_SEND_START;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end
else if(rx_bitclk)
begin
if(rx_postpoll)
begin
rx_state <= UART_RX_STATE_IDLE;
end
else
begin
rx_state <= UART_RX_STATE_GET_DATA;
/* init status*/
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
rx_parity_error_pre <= 1'b0;
end
if(BreakDetect)
begin
rx_break_detect <= 1'b0;
rx_break_status <= 1'b0;
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_pre <= 1'b0;
end
rx_stop_bit_error <= 1'b0;
end
end
end
UART_RX_STATE_GET_DATA: /* Get the data bits */
begin
if(rx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= rx_parity_bit ^ rx_postpoll;
end
if(BreakDetect)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
end
end
if( rxperiod_cmp_need_one_bit && !rx_count7_bit8_wire )
begin
rx_state <= UART_RX_STATE_GET_DATA; /* wait on next count7 turn */
end
else if(rx_count[6:cl] < rxperiod_cmp)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) ||
(FinalParityType == UART_PARITY_TYPE_MRKSPC) )
begin
rx_state <= UART_RX_STATE_GET_PARITY;
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
end
UART_RX_STATE_GET_PARITY:
begin
/*UART_HD_STATE_SEND_PARITY in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
txn <= 1'b0;
rx_state <= UART_HD_STATE_SEND_STOP1;
end
end
else if(rx_bitclk)
begin
if(BreakDetect)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
end
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
if(rx_postpoll != rx_parity_bit)
begin
rx_parity_error_pre <= 1'b1;
end
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_pre <= rx_postpoll;
if( (FinalAddrMode == UART_RX_ADDR_MODE_HW_DET_BUFFER) ||
(FinalAddrMode == UART_RX_ADDR_MODE_HW_BYTE_BYTE) )
begin
if(rx_postpoll) /* Address byte received */
begin
rx_address_detected <= rx_addressmatch;
if( (FinalAddrMode == UART_RX_ADDR_MODE_HW_BYTE_BYTE) & rx_addressmatch)
begin /* Address is correct - store it for Byte_Byte mode*/
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
else /* Skip not correct address byte or in DET_BUFFER mode*/
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else /* Data byte received*/
begin
if(rx_address_detected) /* Store data only when correct Addres received */
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
else /* Skip not addresed data */
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
end /* UART_RX_STATE_GET_PARITY*/
UART_RX_STATE_CHECK_STOP1:
begin
/* prepare clear on read errors one clock ahead */
if(rx_bitclk)
begin
if(FinalAddrMode != UART_RX_ADDR_MODE_NONE)
begin
rx_addr_match_status <= rx_addressmatch;
end
if((FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD))
begin
rx_parity_error_status <= rx_parity_error_pre;
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_status <= rx_markspace_pre;
end
if(~rx_postpoll)
begin /* Stop bit = 0 */
rx_stop_bit_error <= 1'b1; /* Set Error Flag */
if( BreakDetect && !rx_break_detect) /* Break detection*/
begin
rx_state <= UART_RX_STATE_CHECK_BREAK;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end /*UART_RX_STATE_CHECK_STOP1 */
UART_RX_STATE_CHECK_BREAK:
begin
/*UART_HD_STATE_SEND_STOP1 in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if(NumStopBits == UART_NUM_STOP_BITS_1)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
rx_state <= UART_HD_STATE_SEND_START;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else
begin
rx_state <= UART_HD_STATE_SEND_STOP2;
end
end
end
else if(BreakDetect)
begin
if(rx_bitclk)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
/* always need one more bit at 16x oversample */
if( ( ((OverSampleCount==UART_OVER_SAMPLE_16) && rx_count7_bit8_wire) ||
(OverSampleCount==UART_OVER_SAMPLE_8) ) && (rx_count[6:cl] < rxbreak_cmp) )
begin
if(~rx_break_detect) /* Break detected*/
begin
rx_break_status <= 1'b1; /* Set set BREAK Flag */
end
rx_break_detect <= 1; /* protect from double detect */
end
if(~rx_break_detect && ~rx_postpoll)
begin /* wait till BREAK release, it can be longer */
rx_state <= UART_RX_STATE_CHECK_BREAK;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end /*BreakDetect*/
end /*UART_RX_STATE_CHECK_BREAK */
UART_HD_STATE_SEND_START:
begin
if(HalfDuplexSend && HalfDuplexEn)
begin
txn <= 1'b1;
if(rx_bitclk)
begin
txn <= ~hd_shift_out;
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
end
rx_state <= UART_HD_STATE_SEND_DATA;
end
else
begin
rx_state <= UART_HD_STATE_SEND_START;
end
end
end
UART_HD_STATE_SEND_DATA:
begin
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (rx_parity_bit ^ ~txn);
end
/* SendBreak always need one more bit */
if((rx_count7_bit8_wire || /* counter second turn */
rx_count7_tc || /* last bit, but rx_count already reloaded*/
(!rxperiod_cmp_need_one_bit && /*data <= 6 bits*/
!(tx_hd_send_break && (OverSampleCount == UART_OVER_SAMPLE_16)))) && /*Break@16x*/
(((rx_count[6:cl] < hd_txperiod_cmp) && !tx_hd_send_break) ||
((rx_count[6:cl] < hd_tx_break_cmp) && tx_hd_send_break)))
begin
if((FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD))
begin
rx_state <= UART_HD_STATE_SEND_PARITY;
txn <= ~(rx_parity_bit ^ ~txn); /*+last bit*/
end
else if (FinalParityType == UART_PARITY_TYPE_MRKSPC)
begin
rx_state <= UART_HD_STATE_SEND_PARITY;
txn <= ~tx_mark;
if(tx_mark)
begin
tx_mark <= 1'b0;
end
end
else
begin
rx_state <= UART_HD_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
else
begin
if(tx_hd_send_break)
begin
txn <= 1'b1;
end
else
begin
txn <= ~hd_shift_out;
end
end
end
end
end
endcase
end /* End of Else Statement */
end /* End of Always Block */
end /* End of RXEnable Generate Statement begin*/
endgenerate /* sRX */
endmodule /* B_DMA_UART_v0_1 */
`endif /* B_DMA_UART_v0_1_V_ALREADY_INCLUDED */
|
(* Copyright (c) 2014, Robert Dockins *)
Require Import Setoid.
Require Import Morphisms.
Require Import Coq.Program.Basics.
Require Import basics.
Require Import categories.
Delimit Scope preord_scope with preord.
Open Scope preord_scope.
(** * Preordered types and monotone functions.
A preorder is a type equipped with a transitive,
reflexive relation. Unlike standard domain theory,
we will be concentrating on preorders rather than
partial orders as the basis of order theory.
As compared to partial orders, preorders lack the
axiom of antisymmetry. Instead, we work (almost) always
up to the equivalence relation induced by the preorder.
On a preorder, we automatically define a setoid
by setting [x ≈ y] iff [x ≤ y /\ y ≤ x]. Thus, we
"recover" antisymmetry by convention.
*)
Module Preord.
Record mixin_of (T:Type) :=
Mixin
{ ord : T -> T -> Prop
; refl : forall x, ord x x
; trans : forall {x y z},
ord x y -> ord y z -> ord x z
}.
Structure type : Type :=
Pack { carrier :> Type ; mixin : mixin_of carrier }.
Definition ord_op T := ord _ (mixin T).
Record hom (X Y:type) := Hom
{ map :> carrier X -> carrier Y
; axiom : forall (a b:carrier X), ord_op X a b -> ord_op Y (map a) (map b)
}.
Program Definition ident (X:type) : hom X X := Hom X X (fun x => x) _.
Program Definition compose (X Y Z:type) (g:hom Y Z) (f:hom X Y)
:= Hom X Z (fun x => g (f x)) _.
Next Obligation.
apply axiom. apply axiom. auto.
Qed.
Definition comp_mixin := Comp.Mixin type hom ident compose.
Definition eq (X:type) (a b:X) := ord_op X a b /\ ord_op X b a.
Definition hom_ord (X Y:type) (f g:hom X Y) := forall x, ord_op Y (f x) (g x).
Definition hom_eq (X Y:type) (f g:hom X Y) := forall x, eq Y (f x) (g x).
Program Definition ord_mixin X Y := Mixin (hom X Y) (hom_ord X Y) _ _.
Next Obligation.
red; intro. apply refl.
Qed.
Next Obligation.
red; intro. eapply trans; eauto.
apply (H x0). apply (H0 x0).
Qed.
Program Definition eq_mixin X Y := Eq.Mixin (hom X Y) (hom_eq X Y) _ _ _.
Next Obligation.
red; intros. red. split; apply refl.
Qed.
Next Obligation.
red; intros. red. split.
- destruct (H x0); auto.
- destruct (H x0); auto.
Qed.
Next Obligation.
intro.
destruct (H x0). destruct (H0 x0).
split; eapply trans; eauto.
Qed.
Lemma cat_axioms : Category.axioms type hom eq_mixin comp_mixin.
constructor.
- repeat intro. split; apply refl.
- repeat intro. split; apply refl.
- repeat intro. split; apply refl.
- repeat intro. split; simpl; red.
+ apply trans with (f (g' x)).
* apply axiom; destruct (H0 x); auto.
* destruct (H (g' x)); auto.
+ apply trans with (f (g' x)).
* destruct (H (g' x)); auto.
* apply axiom; destruct (H0 x); auto.
Qed.
Program Definition ord_eq (T:type) : Eq.mixin_of T :=
Eq.Mixin T (eq T) _ _ _.
Next Obligation.
split; apply refl.
Qed.
Next Obligation.
destruct H; split; auto.
Qed.
Next Obligation.
destruct H; destruct H0.
split; eapply trans; eauto.
Qed.
End Preord.
Notation preord := Preord.type.
Notation "x ≤ y" := (@Preord.ord_op _ x y) : preord_scope.
Notation "y ≥ x" := (@Preord.ord_op _ x y) (only parsing) : preord_scope.
Notation "x ≰ y" := (~ (@Preord.ord_op _ x y)) : preord_scope.
Notation "y ≱ x" := (~ (@Preord.ord_op _ x y)) (only parsing) : preord_scope.
(** Here we set up the category PREORD of preorders with montone functions
and the canonical structure magic that makes notation work.
*)
Coercion Preord.carrier : Preord.type >-> Sortclass.
Coercion Preord.map : Preord.hom >-> Funclass.
Canonical Structure hom_order X Y := Preord.Pack (Preord.hom X Y) (Preord.ord_mixin X Y).
Canonical Structure Preord_Eq (X:preord) : Eq.type :=
Eq.Pack (Preord.carrier X) (Preord.ord_eq X).
Canonical Structure PREORD :=
Category preord Preord.hom _ _ Preord.cat_axioms.
Canonical Structure preord_hom_eq (A B:preord):=
Eq.Pack (Preord.hom A B) (Preord.eq_mixin A B).
Canonical Structure preord_comp :=
Comp.Pack preord Preord.hom Preord.comp_mixin.
(** The preorder axioms and their relation to equality.
*)
Lemma ord_refl : forall (T:preord) (x:T), x ≤ x.
Proof.
intros. destruct T. destruct mixin. apply refl.
Qed.
Lemma ord_trans : forall (T:preord) (x y z:T), x ≤ y -> y ≤ z -> x ≤ z.
Proof.
intros. destruct T. destruct mixin. eapply trans; eauto.
Qed.
Lemma ord_antisym : forall (T:preord) (x y:T), x ≤ y -> y ≤ x -> x ≈ y.
Proof.
intros. split; auto.
Qed.
Lemma eq_ord : forall (T:preord) (x y:T), x ≈ y -> x ≤ y.
Proof.
intros; destruct H; auto.
Qed.
Lemma eq_ord' : forall (T:preord) (x y:T), x ≈ y -> y ≤ x.
Proof.
intros; destruct H; auto.
Qed.
(** Set up setoid rewriting
*)
Add Parametric Relation (A:preord) : (Preord.carrier A) (@Preord.ord_op A)
reflexivity proved by (ord_refl A)
transitivity proved by (ord_trans A)
as ord_rel.
Add Parametric Morphism (A:preord) :
(@Preord.ord_op A)
with signature (Preord.ord_op A) -->
(Preord.ord_op A) ++>
impl
as ord_morphism.
Proof.
repeat intro.
transitivity x; auto.
transitivity x0; auto.
Qed.
Add Parametric Morphism (A:preord) :
(@Preord.ord_op A)
with signature (eq_op (Preord_Eq A)) ==>
(eq_op (Preord_Eq A)) ==>
iff
as ord_eq_morphism.
Proof.
intros.
destruct H; destruct H0.
split; intros.
- transitivity x; auto.
transitivity x0; auto.
- transitivity y; auto.
transitivity y0; auto.
Qed.
Add Parametric Morphism (A B:preord) :
(@Preord.map A B)
with signature (Preord.ord_op (hom_order A B)) ++>
(Preord.ord_op A) ++>
(Preord.ord_op B)
as preord_map_morphism.
Proof.
intros.
transitivity (x y0).
apply Preord.axiom. auto.
apply H.
Qed.
Add Parametric Morphism (A B:preord) :
(@Preord.map A B)
with signature (eq_op (Preord_Eq (hom_order A B))) ==>
(eq_op (Preord_Eq A)) ==>
(eq_op (Preord_Eq B))
as preord_map_eq_morphism.
Proof.
intros.
transitivity (x y0).
- destruct H0; split; apply Preord.axiom; auto.
- destruct H; split; auto.
Qed.
(** This lemma is handy for using an equality in the context to prove a goal
by transitivity on both sides.
*)
Lemma use_ord (A:preord) (a b c d:A) :
b ≤ c -> a ≤ b -> c ≤ d -> a ≤ d.
Proof.
intros.
transitivity b; auto.
transitivity c; auto.
Qed.
Arguments use_ord [A] [a] [b] [c] [d] _ _ _.
(** PREORD is a concrete category.
*)
Program Definition PREORD_concrete : concrete PREORD :=
Concrete PREORD
Preord.carrier
(fun X => Eq.mixin (Preord_Eq X))
Preord.map _ _.
Next Obligation.
split.
- apply ord_trans with (Preord.map A B f y).
+ apply Preord.axiom. destruct H0; auto.
+ destruct (H y); auto.
- apply ord_trans with (Preord.map A B f y).
+ destruct (H y); auto.
+ apply Preord.axiom. destruct H0; auto.
Qed.
Next Obligation.
split; apply Preord.refl.
Qed.
Canonical Structure PREORD_concrete.
(** Monotone functions respect equality and order.
*)
Lemma preord_eq : forall (X Y:preord) (f:X → Y) (x y:X), x ≈ y -> f x ≈ f y.
Proof.
intros. apply preord_map_eq_morphism; auto.
Qed.
Lemma preord_ord : forall (X Y:preord) (f:X → Y) (x y:X), x ≤ y -> f x ≤ f y.
Proof.
intros. apply Preord.axiom. auto.
Qed.
Hint Resolve ord_refl ord_trans ord_antisym preord_ord preord_eq eq_ord eq_ord'.
Add Parametric Morphism (X Y:preord) :
(@hommap PREORD PREORD_concrete X Y)
with signature (eq_op (CAT_EQ PREORD X Y)) ==>
(eq_op (Preord_Eq X)) ==>
(eq_op (Preord_Eq Y))
as preord_apply_eq_morphism.
Proof.
intros.
transitivity (x#y0).
- apply preord_eq; auto.
- apply H.
Qed.
Add Parametric Morphism (X Y:preord) :
(@hommap PREORD PREORD_concrete X Y)
with signature (eq_op (CAT_EQ PREORD X Y)) ++>
(eq_op (Preord_Eq X)) ++>
(Preord.ord_op Y)
as preord_apply_eqord_morphism.
Proof.
intros.
transitivity (x#y0).
- apply preord_eq; auto.
- apply H.
Qed.
Add Parametric Morphism (X Y:preord) :
(@hommap PREORD PREORD_concrete X Y)
with signature (fun (x y:hom PREORD X Y) => Preord.ord_op (hom_order X Y) x y) ==>
(Preord.ord_op X) ==>
(Preord.ord_op Y)
as preord_apply_ord_morphism.
Proof.
intros.
transitivity (x#y0).
- apply preord_ord. auto.
- apply H.
Qed.
(** PREORD is termianted. *)
Program Definition unitpo := Preord.Pack unit (Preord.Mixin _ (fun _ _ => True) _ _).
Canonical Structure unitpo.
Program Definition preord_terminate (A:preord) : A → unitpo :=
Preord.Hom A unitpo (fun x => tt) _.
Program Definition preord_terminated_mixin :=
Terminated.Mixin
preord Preord.hom
Preord.eq_mixin
unitpo preord_terminate
_.
Next Obligation.
split; simpl; hnf; auto.
Qed.
Canonical Structure preord_terminated :=
Terminated
preord Preord.hom
Preord.eq_mixin
Preord.comp_mixin
Preord.cat_axioms
preord_terminated_mixin.
(** PREORD is initialized. *)
Program Definition emptypo :=
Preord.Pack False (Preord.Mixin _ (fun _ _ => False) _ _).
Canonical Structure emptypo.
Program Definition preord_initiate (A:preord) : emptypo → A :=
Preord.Hom emptypo A (fun x => False_rect _ x) _.
Next Obligation. elim a. Qed.
Program Definition preord_initialized_mixin :=
Initialized.Mixin
preord Preord.hom
Preord.eq_mixin
emptypo preord_initiate
_.
Next Obligation.
split; simpl; elim x.
Qed.
Canonical Structure preord_initialized :=
Initialized
preord Preord.hom
Preord.eq_mixin
Preord.comp_mixin
Preord.cat_axioms
preord_initialized_mixin.
(** The preorder on products, defined pointwise. *)
Definition prod_ord (A B:preord) (x y:A*B):=
(fst x) ≤ (fst y) /\ (snd x) ≤ (snd y).
Program Definition prod_preord (A B:preord) : preord :=
Preord.Pack (A*B) (Preord.Mixin _ (prod_ord A B) _ _).
Next Obligation.
hnf. simpl; auto.
Qed.
Next Obligation.
destruct H; destruct H0; split; simpl in *.
eapply ord_trans; eauto.
eapply ord_trans; eauto.
Qed.
Canonical Structure prod_preord.
(** PREORD is a cartesian category. *)
Program Definition pi1 {A B:preord} : prod_preord A B → A :=
Preord.Hom (prod_preord A B) A (fun x => fst x) _.
Next Obligation.
destruct H; simpl; auto.
Qed.
Program Definition pi2 {A B:preord} : prod_preord A B → B :=
Preord.Hom (prod_preord A B) B (fun x => snd x) _.
Next Obligation.
destruct H; simpl; auto.
Qed.
Program Definition mk_pair {C A B:preord} (f:C → A) (g:C → B) : C → prod_preord A B :=
Preord.Hom C (prod_preord A B) (fun c => (f c, g c)) _.
Next Obligation.
intros. split; simpl; apply Preord.axiom; auto.
Qed.
Program Definition preord_cartesian_mixin
:= Cartesian.Mixin
Preord.type Preord.hom
Preord.eq_mixin
Preord.comp_mixin
prod_preord (@pi1) (@pi2) (@mk_pair) _.
Next Obligation.
constructor.
- intros. split; simpl; auto.
- intros. split; simpl; auto.
- intros. intro. split; simpl.
+ split; simpl.
* destruct (H x); auto.
* destruct (H0 x); auto.
+ split; simpl.
* destruct (H x); auto.
* destruct (H0 x); auto.
Qed.
Canonical Structure preord_cartesian : cartesian :=
Cartesian Preord.type Preord.hom
Preord.eq_mixin
Preord.comp_mixin
Preord.cat_axioms
preord_terminated_mixin
preord_cartesian_mixin.
(** Further, PREORD is a cartesian closed category. *)
Program Definition preord_curry (C A B:preord) (f:C×A → B) : C → hom_order A B :=
Preord.Hom C (hom_order A B) (fun c => Preord.Hom A B (fun a => f (c,a)) _) _.
Next Obligation.
apply preord_ord. split; auto.
Qed.
Next Obligation.
intro x. simpl.
apply preord_ord. split; auto.
Qed.
Program Definition preord_apply (A B:preord) : (hom_order A B × A) → B :=
Preord.Hom (hom_order A B × A) B (fun fx => fst fx (snd fx)) _.
Next Obligation.
simpl. destruct H; simpl in *.
apply preord_map_morphism; auto.
Qed.
Program Definition preord_ccc_mixin
:= CartesianClosed.Mixin
Preord.type Preord.hom
Preord.eq_mixin
Preord.comp_mixin
Preord.cat_axioms
preord_terminated_mixin
preord_cartesian_mixin
hom_order preord_curry preord_apply
_.
Next Obligation.
constructor.
- simpl. intros.
split; simpl; destruct x; simpl; auto.
- simpl. intros.
split; intro z; simpl.
+ rewrite <- H. simpl; auto.
+ rewrite <- H. simpl; auto.
Qed.
Canonical Structure preord_ccc : cartesian_closed :=
CartesianClosed
Preord.type Preord.hom
Preord.eq_mixin
Preord.comp_mixin
Preord.cat_axioms
preord_cartesian_mixin
preord_terminated_mixin
preord_ccc_mixin.
(** The preorder on sums, defined in the standard way.
*)
Definition sum_ord (A B:preord) (x y:A+B):=
match x, y with
| inl x', inl y' => x' ≤ y'
| inr x', inr y' => x' ≤ y'
| _, _ => False
end.
Program Definition sum_preord (A B:preord) : preord :=
Preord.Pack (A+B) (Preord.Mixin _ (sum_ord A B) _ _).
Next Obligation.
hnf. destruct x; auto.
Qed.
Next Obligation.
hnf. destruct x; destruct y; destruct z; simpl in *; intuition.
- eapply ord_trans; eauto.
- eapply ord_trans; eauto.
Qed.
Canonical Structure sum_preord.
(** Preorders with an [ord_dec] structure have a decidable order relation.
*)
Record ord_dec (A:preord) :=
OrdDec
{ orddec :> forall x y:A, {x ≤ y}+{x ≰ y} }.
Arguments orddec [A] [o] x y.
(** Preorders with decidable ordering also have decidable equality.
*)
Canonical Structure PREORD_EQ_DEC (A:preord) (OD:ord_dec A) :=
EqDec (Preord_Eq A) (fun (x y:A) =>
match @orddec A OD x y with
| left H1 =>
match @orddec A OD y x with
| left H2 => left _ (conj H1 H2)
| right H => right _ (fun HEQ => H (proj2 HEQ))
end
| right H => right (fun HEQ => H (proj1 HEQ))
end).
(** The "lift" preorder, which adjoins a new bottom element.
The lift construction gives rise to an endofunctor on PREORD.
*)
Definition lift_ord (A:preord) (x:option A) (y:option A) : Prop :=
match x with None => True | Some x' =>
match y with None => False | Some y' => x' ≤ y' end end.
Program Definition lift_mixin (A:preord) : Preord.mixin_of (option A) :=
Preord.Mixin (option A) (lift_ord A) _ _.
Next Obligation.
destruct x; simpl; auto.
Qed.
Next Obligation.
destruct x; destruct y; destruct z; simpl in *; intuition. eauto.
Qed.
Canonical Structure lift (A:preord) : preord :=
Preord.Pack (option A) (lift_mixin A).
Program Definition liftup (A:preord) : A → lift A :=
Preord.Hom A (lift A) (@Some A) _.
Program Definition lift_map {A B:preord} (f:A → B) : lift A → lift B :=
Preord.Hom (lift A) (lift B) (option_map (Preord.map A B f)) _.
Next Obligation.
red; intros. destruct a; destruct b; simpl in *; auto.
Qed.
Lemma lift_map_id (A:preord) : lift_map id(A) ≈ id(lift A).
Proof.
split; hnf; destruct x; simpl; auto.
Qed.
Lemma lift_map_compose (A B C:preord) (g:B → C) (f:A → B) :
lift_map (g ∘ f) ≈ lift_map g ∘ lift_map f.
Proof.
split; hnf; destruct x; simpl; auto.
Qed.
Lemma lift_map_eq (A B:preord) (f f':A → B) : f ≈ f' -> lift_map f ≈ lift_map f'.
Proof.
intros.
split; hnf; destruct x; simpl; auto; apply H.
Qed.
Program Definition liftF : functor PREORD PREORD :=
(Functor PREORD PREORD lift (@lift_map) _ _ _).
Next Obligation.
transitivity (lift_map id(A)).
- apply lift_map_eq; auto.
- apply lift_map_id.
Qed.
Next Obligation.
transitivity (lift_map (f ∘ g)).
- apply lift_map_eq; auto.
- apply lift_map_compose.
Qed.
Next Obligation.
apply lift_map_eq. auto.
Qed.
|
/*
* Titor - Barrel Processor - Easy to replicate register
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Register
`else
`define INC_Register
`timescale 1 ns / 100 ps
// Register module
module Register (
value,
memory,
datapath,
sel_memory,
sel_datapath,
clk,
reset
);
`include "definition/Definition.v"
output reg [WORD-1:0] value; // the value stored in the register
input [WORD-1:0] memory;
input [WORD-1:0] datapath;
input sel_memory;
input sel_datapath;
input clk;
input reset;
always @(posedge clk) begin
if(reset) begin value <= 0; end
else if(sel_memory) begin value <= memory; end
else if(sel_datapath) begin value <= datapath; end
else begin value <= value; end
end
endmodule
`endif
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:47:43 05/19/2015
// Design Name: erosion3x3
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_erosion3x3.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: erosion3x3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_erosion3x3(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
reg [7:0] erosion_r;
reg [7:0] erosion_g;
reg [7:0] erosion_b;
wire erosion;
wire erosion_de;
wire erosion_vsync;
wire erosion_hsync;
erosion3x3 #
(
.H_SIZE(10'd83)
)
erode3
(
.clk(rx_pclk),
.ce(1'b1),
.rst(1'b0),
.mask((rx_red == 8'hFF) ? 1'b1 : 1'b0),
.in_de(rx_de),
.in_vsync(rx_vsync),
.in_hsync(rx_hsync),
.eroded(erosion),
.out_de(erosion_de),
.out_vsync(erosion_vsync),
.out_hsync(erosion_hsync)
);
always @(posedge rx_pclk) begin
erosion_r = (erosion) ? 8'hFF : 8'h00;
erosion_g = (erosion) ? 8'hFF : 8'h00;
erosion_b = (erosion) ? 8'hFF : 8'h00;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = erosion_de;
assign tx_hsync = erosion_hsync;
assign tx_vsync = erosion_vsync;
assign tx_red = erosion_r;
assign tx_green = erosion_g;
assign tx_blue = erosion_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable Setoid DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecide_fun (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts_fun E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Export Decidable.
Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
Ltac abstract_term t :=
tryif (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
tryif (change T with E.t in H) then fail
else tryif (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
tryif prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substFSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_FSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
tryif prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide_fun.
Require Import FSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WS) := !WDecide_fun M.E M.
Module Decide := WDecide.
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:10:23 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n2925, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
shift_value_SHT2_EWR_2_, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
DmP_mant_SFG_SWR_signed_13_, inst_FSM_INPUT_ENABLE_state_next_1_,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n595, n596, n597, n598, n599, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n772, n773,
n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784,
n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n811, n812,
n813, n814, n815, n816, n817, n821, n834, n836, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861,
n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872,
n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883,
n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894,
n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905,
n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916,
n917, n918, n919, n920, n921, n922, n582, DP_OP_301J12_122_1182_n171,
n923, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, n991, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2412, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777,
n2778, n2779, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818,
n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828,
n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838,
n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848,
n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858,
n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868,
n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878,
n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888,
n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898,
n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908,
n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918,
n2919, n2920, n2921, n2922, n2923, n2924;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [29:0] DMP_EXP_EWSW;
wire [26:2] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [3:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [3:2] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n922), .CK(clk), .RN(
n2774), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2528) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n920), .CK(clk), .RN(n2774), .Q(
Shift_reg_FLAGS_7_6), .QN(n2526) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n918), .CK(clk), .RN(n2774), .Q(
n2925), .QN(n2558) );
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n917), .CK(clk), .RN(n2774), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2427) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n915), .CK(clk), .RN(n2774), .Q(
Shift_reg_FLAGS_7[1]), .QN(n2529) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n913), .CK(clk), .RN(n2770), .Q(
intDX_EWSW[0]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n2770), .Q(
intDX_EWSW[1]), .QN(n1253) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n911), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[2]), .QN(n1194) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n909), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n908), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[5]), .QN(n1270) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n907), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[6]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n906), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[7]), .QN(n1267) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n905), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[8]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n904), .CK(clk), .RN(n2771), .Q(
intDX_EWSW[9]), .QN(n1271) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n903), .CK(clk), .RN(n2771),
.Q(intDX_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n902), .CK(clk), .RN(n2771),
.Q(intDX_EWSW[11]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n901), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n900), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[13]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n899), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[14]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n898), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[15]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n897), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[16]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n896), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[17]), .QN(n1248) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n895), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[18]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n894), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[19]), .QN(n1236) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n892), .CK(clk), .RN(n2772),
.Q(intDX_EWSW[21]), .QN(n1272) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n889), .CK(clk), .RN(n2773),
.Q(intDX_EWSW[24]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n885), .CK(clk), .RN(n2773),
.Q(intDX_EWSW[28]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n884), .CK(clk), .RN(n2773),
.Q(intDX_EWSW[29]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n883), .CK(clk), .RN(n2773),
.Q(intDX_EWSW[30]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n879), .CK(clk), .RN(n2767), .Q(
intDY_EWSW[0]), .QN(n2482) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n874), .CK(clk), .RN(n2768), .Q(
intDY_EWSW[5]), .QN(n2477) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n872), .CK(clk), .RN(n2768), .Q(
intDY_EWSW[7]), .QN(n2472) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n870), .CK(clk), .RN(n2768), .Q(
intDY_EWSW[9]), .QN(n2466) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n868), .CK(clk), .RN(n2768),
.Q(intDY_EWSW[11]), .QN(n2471) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n863), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[16]), .QN(n2481) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n862), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[17]), .QN(n2470) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n861), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[18]), .QN(n2480) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n860), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[19]), .QN(n2476) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n859), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[20]), .QN(n2479) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n858), .CK(clk), .RN(n2769),
.Q(intDY_EWSW[21]), .QN(n2469) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n857), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[22]), .QN(n2464) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n856), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[23]), .QN(n2468) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n855), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[24]), .QN(n2463) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n854), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[25]), .QN(n2478) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n853), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[26]), .QN(n2473) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n852), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[27]), .QN(n2467) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n851), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[28]), .QN(n2465) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n850), .CK(clk), .RN(n2770),
.Q(intDY_EWSW[29]), .QN(n2475) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n849), .CK(clk), .RN(n2773),
.Q(intDY_EWSW[30]), .QN(n2474) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n2754), .Q(
shift_value_SHT2_EWR_2_), .QN(n2589) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n817), .CK(clk), .RN(n2762),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2553) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n814), .CK(clk), .RN(n1337),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n781), .CK(clk), .RN(n1312), .Q(
DMP_EXP_EWSW[23]), .QN(n2532) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n773), .CK(clk), .RN(n2764), .Q(
OP_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n770), .CK(clk), .RN(n2759), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n2759), .Q(
DMP_SHT2_EWSW[0]), .QN(n2444) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n2760), .Q(
DMP_SFG[0]), .QN(n2514) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n767), .CK(clk), .RN(n2759), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n766), .CK(clk), .RN(n2759), .Q(
DMP_SHT2_EWSW[1]), .QN(n2508) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n2759), .Q(
DMP_SFG[1]), .QN(n2419) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n2567), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n2563), .Q(
DMP_SHT2_EWSW[2]), .QN(n2509) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n2757), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n2757), .Q(
DMP_SHT2_EWSW[3]), .QN(n2510) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1315), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n757), .CK(clk), .RN(n2763), .Q(
DMP_SHT2_EWSW[4]), .QN(n2445) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n756), .CK(clk), .RN(n1315), .Q(
DMP_SFG[4]), .QN(n2512) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n755), .CK(clk), .RN(n2764), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n754), .CK(clk), .RN(n2764), .Q(
DMP_SHT2_EWSW[5]), .QN(n2506) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n752), .CK(clk), .RN(n2759), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n751), .CK(clk), .RN(n2759), .Q(
DMP_SHT2_EWSW[6]), .QN(n2443) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n750), .CK(clk), .RN(n2759), .Q(
DMP_SFG[6]), .QN(n2513) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n749), .CK(clk), .RN(n2762), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n748), .CK(clk), .RN(n2762), .Q(
DMP_SHT2_EWSW[7]), .QN(n2507) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n746), .CK(clk), .RN(n2757), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n2757), .Q(
DMP_SHT2_EWSW[8]), .QN(n2446) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n743), .CK(clk), .RN(n1321), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n742), .CK(clk), .RN(n1321), .Q(
DMP_SHT2_EWSW[9]), .QN(n2511) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n740), .CK(clk), .RN(n1309), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n739), .CK(clk), .RN(n1310), .Q(
DMP_SHT2_EWSW[10]), .QN(n2442) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n738), .CK(clk), .RN(n1304), .Q(
DMP_SFG[10]), .QN(n2555) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n737), .CK(clk), .RN(n2749), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n736), .CK(clk), .RN(n1327), .Q(
DMP_SHT2_EWSW[11]), .QN(n2441) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n735), .CK(clk), .RN(n1305), .Q(
DMP_SFG[11]), .QN(n2554) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n734), .CK(clk), .RN(n2763), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n732), .CK(clk), .RN(n1323), .Q(
DMP_SFG[12]), .QN(n2519) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n731), .CK(clk), .RN(n2755), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n729), .CK(clk), .RN(n1323), .Q(
DMP_SFG[13]), .QN(n2515) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n728), .CK(clk), .RN(n1313), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n727), .CK(clk), .RN(n1314), .Q(
DMP_SHT2_EWSW[14]), .QN(n2455) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n726), .CK(clk), .RN(n1313), .Q(
DMP_SFG[14]), .QN(n2521) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n725), .CK(clk), .RN(n1313), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n724), .CK(clk), .RN(n1314), .Q(
DMP_SHT2_EWSW[15]), .QN(n2454) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n723), .CK(clk), .RN(n1313), .Q(
DMP_SFG[15]), .QN(n2524) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n722), .CK(clk), .RN(n2774), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n721), .CK(clk), .RN(n2753), .Q(
DMP_SHT2_EWSW[16]), .QN(n2453) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n720), .CK(clk), .RN(n1313), .Q(
DMP_SFG[16]), .QN(n2520) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n719), .CK(clk), .RN(n2775), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n718), .CK(clk), .RN(n2753), .Q(
DMP_SHT2_EWSW[17]), .QN(n2452) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n717), .CK(clk), .RN(n2561), .Q(
DMP_SFG[17]), .QN(n2523) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n716), .CK(clk), .RN(n2775), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n715), .CK(clk), .RN(n2753), .Q(
DMP_SHT2_EWSW[18]), .QN(n2451) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n713), .CK(clk), .RN(n2750), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n712), .CK(clk), .RN(n2750), .Q(
DMP_SHT2_EWSW[19]), .QN(n2450) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n711), .CK(clk), .RN(n2750), .Q(
DMP_SFG[19]), .QN(n2517) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n710), .CK(clk), .RN(n2750), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n709), .CK(clk), .RN(n2750), .Q(
DMP_SHT2_EWSW[20]), .QN(n2449) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n708), .CK(clk), .RN(n2750), .Q(
DMP_SFG[20]), .QN(n2516) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n707), .CK(clk), .RN(n1311), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n706), .CK(clk), .RN(n1312), .Q(
DMP_SHT2_EWSW[21]), .QN(n2448) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n705), .CK(clk), .RN(n2750), .Q(
DMP_SFG[21]), .QN(n2522) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n704), .CK(clk), .RN(n1311), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n703), .CK(clk), .RN(n1312), .Q(
DMP_SHT2_EWSW[22]), .QN(n2447) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n701), .CK(clk), .RN(n1313), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n698), .CK(clk), .RN(n1311), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n697), .CK(clk), .RN(n1310), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n696), .CK(clk), .RN(n2749), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n695), .CK(clk), .RN(n2749), .Q(
DMP_SHT2_EWSW[24]), .QN(n2437) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n1305), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n688), .CK(clk), .RN(n1311), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n2763), .Q(
DMP_exp_NRM2_EW[2]), .QN(n1188) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n686), .CK(clk), .RN(n2765), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n685), .CK(clk), .RN(n2765), .Q(
DMP_SHT2_EWSW[26]), .QN(n2436) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n1310), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n682), .CK(clk), .RN(n1314), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n681), .CK(clk), .RN(n2765), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n680), .CK(clk), .RN(n2765), .Q(
DMP_SHT2_EWSW[27]), .QN(n2435) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n678), .CK(clk), .RN(n2765), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n676), .CK(clk), .RN(n2766), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n675), .CK(clk), .RN(n2766), .Q(
DMP_SHT2_EWSW[28]), .QN(n2434) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n673), .CK(clk), .RN(n2766), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n672), .CK(clk), .RN(n2766), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n671), .CK(clk), .RN(n2767), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n670), .CK(clk), .RN(n2766), .Q(
DMP_SHT2_EWSW[29]), .QN(n2433) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n668), .CK(clk), .RN(n2766), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n667), .CK(clk), .RN(n2766), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n665), .CK(clk), .RN(n2767), .Q(
DMP_SHT2_EWSW[30]), .QN(n2432) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n663), .CK(clk), .RN(n2767), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n662), .CK(clk), .RN(n2767), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n660), .CK(clk), .RN(n2756), .Q(
DmP_mant_SHT1_SW[0]), .QN(n2552) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n656), .CK(clk), .RN(n2568), .Q(
DmP_mant_SHT1_SW[2]), .QN(n2491) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n654), .CK(clk), .RN(n1326), .Q(
DmP_mant_SHT1_SW[3]), .QN(n2495) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n648), .CK(clk), .RN(n2751), .Q(
DmP_mant_SHT1_SW[6]), .QN(n2497) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n646), .CK(clk), .RN(n2761), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2489) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n644), .CK(clk), .RN(n1309), .Q(
DmP_mant_SHT1_SW[8]), .QN(n2505) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n642), .CK(clk), .RN(n1309), .Q(
DmP_mant_SHT1_SW[9]), .QN(n2493) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n640), .CK(clk), .RN(n1309), .Q(
DmP_mant_SHT1_SW[10]), .QN(n2738) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n636), .CK(clk), .RN(n1326), .Q(
DmP_mant_SHT1_SW[12]), .QN(n2496) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n632), .CK(clk), .RN(n2757), .Q(
DmP_mant_SHT1_SW[14]), .QN(n2488) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n628), .CK(clk), .RN(n1315), .Q(
DmP_mant_SHT1_SW[16]), .QN(n2498) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n624), .CK(clk), .RN(n2755), .Q(
DmP_mant_SHT1_SW[18]), .QN(n2504) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n620), .CK(clk), .RN(n2757), .Q(
DmP_mant_SHT1_SW[20]), .QN(n2490) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n2753), .Q(
DmP_mant_SHT1_SW[22]), .QN(n2525) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n2762), .Q(
DmP_EXP_EWSW[23]), .QN(n2531) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n612), .CK(clk), .RN(n2762), .Q(
DmP_EXP_EWSW[26]), .QN(n2527) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n608), .CK(clk), .RN(n2774), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n607), .CK(clk), .RN(n2756), .Q(
ZERO_FLAG_SHT2), .QN(n2456) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1336), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n2567), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n602), .CK(clk), .RN(n2764), .Q(
OP_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n601), .CK(clk), .RN(n2764), .Q(
OP_FLAG_SHT2), .QN(n2431) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n599), .CK(clk), .RN(n2567), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n595), .CK(clk), .RN(n2754), .Q(
SIGN_FLAG_SHT1SHT2), .QN(n2557) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n591), .CK(clk), .RN(n1305), .Q(
Raw_mant_NRM_SWR[16]), .QN(n2740) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n589), .CK(clk), .RN(n1336), .Q(
Raw_mant_NRM_SWR[18]), .QN(n2459) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n583), .CK(clk), .RN(n2747), .Q(
Raw_mant_NRM_SWR[24]), .QN(n2744) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n570), .CK(clk), .RN(n2753), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2537) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n569), .CK(clk), .RN(n2760), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2486) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n568), .CK(clk), .RN(n2756), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2484) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n567), .CK(clk), .RN(n1323), .Q(
LZD_output_NRM2_EW[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n566), .CK(clk), .RN(n2753), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2501) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n565), .CK(clk), .RN(n1315), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2460) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n563), .CK(clk), .RN(n1323), .Q(
Raw_mant_NRM_SWR[7]), .QN(n2734) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n561), .CK(clk), .RN(n2756), .Q(
Raw_mant_NRM_SWR[8]), .QN(n2424) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n559), .CK(clk), .RN(n2568), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2536) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n558), .CK(clk), .RN(n2563), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2458) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n556), .CK(clk), .RN(n1321), .Q(
Raw_mant_NRM_SWR[6]), .QN(n2494) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n552), .CK(clk), .RN(n2568), .Q(
Raw_mant_NRM_SWR[12]), .QN(n2736) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n525), .CK(clk), .RN(n1311), .Q(
DmP_mant_SFG_SWR[14]), .QN(n2545) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n524), .CK(clk), .RN(n1311), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2538) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n523), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2550) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n522), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2549) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n521), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n520), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2548) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n519), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2547) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n518), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2546) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n517), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[22]), .QN(n2540) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n516), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2539) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n514), .CK(clk), .RN(n2748), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2500) );
DFFRXLTS R_33 ( .D(n2815), .CK(clk), .RN(n2568), .Q(n2716) );
DFFSX1TS R_34 ( .D(n2813), .CK(clk), .SN(n2569), .Q(n2715) );
DFFSX1TS R_35 ( .D(n2812), .CK(clk), .SN(n2569), .Q(n2714) );
DFFSX1TS R_37 ( .D(n2858), .CK(clk), .SN(n1312), .Q(n2712) );
DFFSX1TS R_38 ( .D(n2859), .CK(clk), .SN(n1312), .Q(n2711) );
DFFSX1TS R_39 ( .D(n2735), .CK(clk), .SN(n1312), .Q(n2710) );
DFFSX1TS R_45 ( .D(n2797), .CK(clk), .SN(n1305), .Q(n2706) );
DFFSX1TS R_46 ( .D(n2798), .CK(clk), .SN(n1304), .Q(n2705) );
DFFSX1TS R_47 ( .D(n2742), .CK(clk), .SN(n1304), .Q(n2704) );
DFFSX1TS R_48 ( .D(n2796), .CK(clk), .SN(n1304), .Q(n2703) );
DFFSX1TS R_53 ( .D(n2809), .CK(clk), .SN(n1322), .Q(n2700) );
DFFSX1TS R_54 ( .D(n2808), .CK(clk), .SN(n1322), .Q(n2699) );
DFFSX1TS R_55 ( .D(n2807), .CK(clk), .SN(n1322), .Q(n2698) );
DFFSX1TS R_56 ( .D(n2806), .CK(clk), .SN(n1322), .Q(n2697) );
DFFSX1TS R_94 ( .D(n2817), .CK(clk), .SN(n2569), .Q(n2673) );
DFFSX1TS R_95 ( .D(n2816), .CK(clk), .SN(n2570), .Q(n2672) );
DFFSX2TS R_105 ( .D(n2845), .CK(clk), .SN(n2562), .Q(n2666) );
DFFSX2TS R_107 ( .D(n2844), .CK(clk), .SN(n2755), .Q(n2665) );
DFFSX4TS R_117 ( .D(n2660), .CK(clk), .SN(n1324), .Q(n2864) );
DFFSX2TS R_126 ( .D(n2811), .CK(clk), .SN(n1322), .Q(n2655) );
DFFSX2TS R_128 ( .D(n2810), .CK(clk), .SN(n1322), .Q(n2654) );
DFFSX1TS R_134 ( .D(n2868), .CK(clk), .SN(n1324), .Q(n2650) );
DFFRX4TS R_138 ( .D(n1576), .CK(clk), .RN(n1326), .Q(n2776) );
DFFSX2TS R_141 ( .D(n2800), .CK(clk), .SN(n1305), .Q(n2645) );
DFFSX2TS R_142 ( .D(n2799), .CK(clk), .SN(n1305), .Q(n2644) );
DFFSX2TS R_140 ( .D(n2801), .CK(clk), .SN(n1305), .Q(n2646) );
DFFSX1TS R_145 ( .D(n2828), .CK(clk), .SN(n2570), .Q(n2641) );
DFFSX1TS R_146 ( .D(n2827), .CK(clk), .SN(n2569), .Q(n2640) );
DFFSX1TS R_144 ( .D(n2829), .CK(clk), .SN(n2570), .Q(n2642) );
DFFRXLTS R_147 ( .D(n2788), .CK(clk), .RN(n1310), .Q(n2639) );
DFFSX1TS R_148 ( .D(n2787), .CK(clk), .SN(n1310), .Q(n2638) );
DFFSX1TS R_149 ( .D(n2786), .CK(clk), .SN(n1310), .Q(n2637) );
DFFSX1TS R_154 ( .D(n2840), .CK(clk), .SN(n2747), .Q(n2632) );
DFFSX1TS R_155 ( .D(n2839), .CK(clk), .SN(n2758), .Q(n2631) );
DFFSX1TS R_156 ( .D(n2838), .CK(clk), .SN(n2758), .Q(n2630) );
DFFRXLTS R_157 ( .D(n2854), .CK(clk), .RN(n2752), .Q(n2629) );
DFFSX1TS R_161 ( .D(n2836), .CK(clk), .SN(n2758), .Q(n2625) );
DFFSX1TS R_160 ( .D(n2837), .CK(clk), .SN(n2747), .Q(n2626) );
DFFSX1TS R_164 ( .D(n2842), .CK(clk), .SN(n2560), .Q(n2622) );
DFFSX1TS R_163 ( .D(n2843), .CK(clk), .SN(n2756), .Q(n2623) );
DFFSX1TS R_165 ( .D(n2841), .CK(clk), .SN(n2753), .Q(n2621) );
DFFSX1TS R_171 ( .D(n2803), .CK(clk), .SN(n1304), .Q(n2617) );
DFFRXLTS R_169 ( .D(n2805), .CK(clk), .RN(n1326), .Q(n2619) );
DFFSX1TS R_170 ( .D(n2804), .CK(clk), .SN(n1304), .Q(n2618) );
DFFSX1TS R_172 ( .D(n2802), .CK(clk), .SN(n1305), .Q(n2616) );
DFFSX1TS R_173 ( .D(n2791), .CK(clk), .SN(n2749), .Q(n2615) );
DFFSX1TS R_174 ( .D(n2790), .CK(clk), .SN(n1309), .Q(n2614) );
DFFSX1TS R_175 ( .D(n2789), .CK(clk), .SN(n1327), .Q(n2613) );
DFFSX1TS R_177 ( .D(n2833), .CK(clk), .SN(n2758), .Q(n2612) );
DFFSX1TS R_178 ( .D(n2832), .CK(clk), .SN(n2747), .Q(n2611) );
DFFSX1TS R_179 ( .D(n2831), .CK(clk), .SN(n2747), .Q(n2610) );
DFFSX1TS R_186 ( .D(n2825), .CK(clk), .SN(n2570), .Q(n2606) );
DFFSX1TS R_187 ( .D(n2824), .CK(clk), .SN(n2570), .Q(n2605) );
DFFRXLTS R_185 ( .D(n2826), .CK(clk), .RN(n2568), .Q(n2607) );
DFFSX1TS R_188 ( .D(n2823), .CK(clk), .SN(n2569), .Q(n2604) );
DFFSX1TS R_205 ( .D(n2860), .CK(clk), .SN(n1314), .Q(n2594) );
DFFSX1TS R_203 ( .D(n2862), .CK(clk), .SN(n1314), .Q(n2596) );
DFFSX1TS R_204 ( .D(n2861), .CK(clk), .SN(n1314), .Q(n2595) );
DFFRX4TS R_213 ( .D(n1576), .CK(clk), .RN(n2763), .Q(n2598) );
DFFSX4TS R_220 ( .D(n2203), .CK(clk), .SN(n1324), .Q(n2584) );
DFFRX4TS R_219 ( .D(n579), .CK(clk), .RN(n1323), .Q(n2585) );
DFFRXLTS R_6 ( .D(final_result_ieee[31]), .CK(clk), .RN(n2563), .Q(n2730) );
DFFRXLTS R_235 ( .D(final_result_ieee[30]), .CK(clk), .RN(n2748), .Q(n2575)
);
DFFSX1TS R_232 ( .D(n2922), .CK(clk), .SN(n2562), .Q(n2578) );
DFFRXLTS R_20 ( .D(n2586), .CK(clk), .RN(n2559), .Q(n2723) );
DFFRXLTS R_32 ( .D(n2856), .CK(clk), .RN(n2564), .Q(n2717) );
DFFRXLTS R_84 ( .D(n2739), .CK(clk), .RN(n2559), .Q(n2681) );
DFFSX2TS R_233 ( .D(n2921), .CK(clk), .SN(n2567), .Q(n2577) );
DFFSX1TS R_234 ( .D(n2920), .CK(clk), .SN(n1336), .Q(n2576) );
DFFSX1TS R_8 ( .D(n2923), .CK(clk), .SN(n2761), .Q(n2729) );
DFFSX1TS R_237 ( .D(n2919), .CK(clk), .SN(n2567), .Q(n2574) );
DFFSX2TS R_5 ( .D(n2873), .CK(clk), .SN(n2564), .Q(n2731) );
DFFSX2TS R_12 ( .D(n2909), .CK(clk), .SN(n2559), .Q(n2727) );
DFFSX2TS R_16 ( .D(n2879), .CK(clk), .SN(n2565), .Q(n2725) );
DFFSX2TS R_24 ( .D(n2881), .CK(clk), .SN(n2564), .Q(n2721) );
DFFSX2TS R_28 ( .D(n2875), .CK(clk), .SN(n2565), .Q(n2719) );
DFFSX2TS R_44 ( .D(n2903), .CK(clk), .SN(n2760), .Q(n2707) );
DFFSX2TS R_52 ( .D(n2898), .CK(clk), .SN(n2766), .Q(n2701) );
DFFSX2TS R_64 ( .D(n2877), .CK(clk), .SN(n2566), .Q(n2691) );
DFFSX2TS R_68 ( .D(n2886), .CK(clk), .SN(n2767), .Q(n2689) );
DFFSX2TS R_72 ( .D(n2890), .CK(clk), .SN(n1313), .Q(n2687) );
DFFSX2TS R_76 ( .D(n2871), .CK(clk), .SN(n2566), .Q(n2685) );
DFFSX2TS R_80 ( .D(n2892), .CK(clk), .SN(n2753), .Q(n2683) );
DFFSX2TS R_92 ( .D(n2896), .CK(clk), .SN(n2567), .Q(n2675) );
DFFSX2TS R_100 ( .D(n2901), .CK(clk), .SN(n2754), .Q(n2669) );
DFFSX2TS R_104 ( .D(n2883), .CK(clk), .SN(n2567), .Q(n2667) );
DFFSX2TS R_111 ( .D(n2907), .CK(clk), .SN(n2560), .Q(n2663) );
DFFSX2TS R_115 ( .D(n2894), .CK(clk), .SN(n2562), .Q(n2661) );
DFFSX2TS R_121 ( .D(n2888), .CK(clk), .SN(n2765), .Q(n2658) );
DFFSX2TS R_132 ( .D(n2899), .CK(clk), .SN(n2755), .Q(n2652) );
DFFSX2TS R_18 ( .D(n2912), .CK(clk), .SN(n2560), .Q(n2724) );
DFFSX2TS R_30 ( .D(n2885), .CK(clk), .SN(n2566), .Q(n2718) );
DFFSX2TS R_82 ( .D(n2911), .CK(clk), .SN(n2560), .Q(n2682) );
DFFSX2TS R_3 ( .D(n2874), .CK(clk), .SN(n2565), .Q(n2732) );
DFFSX2TS R_10 ( .D(n2910), .CK(clk), .SN(n2559), .Q(n2728) );
DFFSX2TS R_14 ( .D(n2880), .CK(clk), .SN(n2565), .Q(n2726) );
DFFSX2TS R_22 ( .D(n2882), .CK(clk), .SN(n2564), .Q(n2722) );
DFFSX2TS R_26 ( .D(n2876), .CK(clk), .SN(n2565), .Q(n2720) );
DFFSX2TS R_42 ( .D(n2904), .CK(clk), .SN(n1311), .Q(n2708) );
DFFSX2TS R_50 ( .D(n2423), .CK(clk), .SN(n2563), .Q(n2702) );
DFFSX2TS R_62 ( .D(n2878), .CK(clk), .SN(n2566), .Q(n2692) );
DFFSX2TS R_66 ( .D(n2887), .CK(clk), .SN(n2562), .Q(n2690) );
DFFSX2TS R_70 ( .D(n2891), .CK(clk), .SN(n2561), .Q(n2688) );
DFFSX2TS R_74 ( .D(n2872), .CK(clk), .SN(n2566), .Q(n2686) );
DFFSX2TS R_78 ( .D(n2893), .CK(clk), .SN(n2760), .Q(n2684) );
DFFSX2TS R_90 ( .D(n2897), .CK(clk), .SN(n2563), .Q(n2676) );
DFFSX2TS R_98 ( .D(n2902), .CK(clk), .SN(n2567), .Q(n2670) );
DFFSX2TS R_102 ( .D(n2884), .CK(clk), .SN(n2567), .Q(n2668) );
DFFSX2TS R_109 ( .D(n2908), .CK(clk), .SN(n2560), .Q(n2664) );
DFFSX2TS R_113 ( .D(n2895), .CK(clk), .SN(n2760), .Q(n2662) );
DFFSX2TS R_119 ( .D(n2889), .CK(clk), .SN(n2774), .Q(n2659) );
DFFSX2TS R_123 ( .D(n2906), .CK(clk), .SN(n2561), .Q(n2657) );
DFFSX2TS R_130 ( .D(n2900), .CK(clk), .SN(n2563), .Q(n2653) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n2760), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n812), .CK(clk), .RN(n2559), .Q(
final_result_ieee[23]) );
DFFSX1TS R_184 ( .D(n2918), .CK(clk), .SN(n2755), .Q(n2608) );
DFFSX1TS R_194 ( .D(n2917), .CK(clk), .SN(n2775), .Q(n2599) );
DFFSX1TS R_201 ( .D(n2916), .CK(clk), .SN(n2561), .Q(n2597) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n2570), .Q(
zero_flag) );
DFFSX2TS R_227 ( .D(n1413), .CK(clk), .SN(n1322), .Q(n2581) );
DFFSX2TS R_224 ( .D(n834), .CK(clk), .SN(n1322), .Q(n2582) );
DFFSX2TS R_228 ( .D(n836), .CK(clk), .SN(n2754), .Q(n2580) );
DFFSX2TS R_239 ( .D(n2864), .CK(clk), .SN(n1324), .Q(n2573) );
DFFSX2TS R_218 ( .D(n2855), .CK(clk), .SN(n1325), .Q(n1298) );
DFFSX2TS R_216 ( .D(n1334), .CK(clk), .SN(n1325), .Q(n2587) );
DFFSX2TS R_189 ( .D(n2785), .CK(clk), .SN(n2763), .Q(n2603) );
DFFSX2TS R_190 ( .D(n2784), .CK(clk), .SN(n2763), .Q(n2602) );
DFFSX2TS R_191 ( .D(n2783), .CK(clk), .SN(n2763), .Q(n2601) );
DFFSX2TS R_192 ( .D(n2782), .CK(clk), .SN(n2570), .Q(n2600) );
DFFSX2TS R_125 ( .D(n2905), .CK(clk), .SN(n2561), .Q(n2656) );
DFFSX1TS R_240 ( .D(n2863), .CK(clk), .SN(n1324), .Q(n2572) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n577), .CK(clk), .RN(n2752), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2499) );
DFFRX4TS R_150 ( .D(n2795), .CK(clk), .RN(n2757), .Q(n2636) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n2752), .Q(
Raw_mant_NRM_SWR[9]), .QN(n2462) );
DFFRX4TS R_85 ( .D(n2849), .CK(clk), .RN(n2752), .Q(n2680) );
DFFRX4TS R_57 ( .D(n2822), .CK(clk), .RN(n2568), .Q(n2696) );
DFFSX2TS R_153 ( .D(n2792), .CK(clk), .SN(n1315), .Q(n2633) );
DFFSX4TS R_209 ( .D(n2851), .CK(clk), .SN(n1325), .Q(n2591) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n580), .CK(clk), .RN(n2752), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1413) );
DFFSX4TS R_208 ( .D(n2159), .CK(clk), .SN(n1325), .Q(n2592) );
DFFRX4TS R_168 ( .D(n2620), .CK(clk), .RN(n1326), .Q(
DP_OP_301J12_122_1182_n171) );
DFFSX2TS R_152 ( .D(n2793), .CK(clk), .SN(n1315), .Q(n2634) );
DFFSX4TS R_210 ( .D(n2850), .CK(clk), .SN(n2752), .Q(n2590) );
DFFSX2TS R_60 ( .D(n2821), .CK(clk), .SN(n2569), .Q(n2693) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n880), .CK(clk), .RN(n1321), .Q(
left_right_SHT2), .QN(n1281) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n576), .CK(clk), .RN(n1323), .Q(
LZD_output_NRM2_EW[2]), .QN(n970) );
DFFRX2TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n881), .CK(clk), .RN(n2764), .Q(
intAS) );
DFFSX2TS R_88 ( .D(n2848), .CK(clk), .SN(n1325), .Q(n2677) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n582), .CK(clk), .RN(n1313), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1412) );
DFFSX2TS R_59 ( .D(n2820), .CK(clk), .SN(n2569), .Q(n2694) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n759), .CK(clk), .RN(n2757), .Q(
DMP_SFG[3]), .QN(n2420) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n741), .CK(clk), .RN(n1321), .Q(
DMP_SFG[9]), .QN(n2428) );
DFFSX2TS R_40 ( .D(n2857), .CK(clk), .SN(n1312), .Q(n2709) );
DFFSX2TS R_151 ( .D(n2794), .CK(clk), .SN(n1315), .Q(n2635) );
DFFRX4TS R_93 ( .D(n2818), .CK(clk), .RN(n2568), .Q(n2674) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n882), .CK(clk), .RN(n2764),
.Q(intDX_EWSW[31]), .QN(n2503) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n555), .CK(clk), .RN(n2752), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2544) );
DFFSX2TS R_58 ( .D(n2819), .CK(clk), .SN(n2569), .Q(n2695) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n677), .CK(clk), .RN(n2765), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX4TS R_180 ( .D(underflow_flag), .CK(clk), .RN(n2563), .Q(n2609) );
DFFSRHQX8TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n598), .CK(clk), .SN(1'b1), .RN(
n1336), .Q(SIGN_FLAG_SHT2) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n690), .CK(clk), .RN(n1327), .QN(
n2457) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n794), .CK(clk), .RN(n1338), .Q(
DMP_EXP_EWSW[10]) );
DFFSX1TS R_223 ( .D(n2914), .CK(clk), .SN(n2559), .Q(n2583) );
DFFRHQX2TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n691), .CK(clk), .RN(n1336), .Q(
n2412) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n664), .CK(clk), .RN(n1327), .Q(
DMP_SFG[30]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n669), .CK(clk), .RN(n1335), .Q(
DMP_SFG[29]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n674), .CK(clk), .RN(n1337), .Q(
DMP_SFG[28]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n679), .CK(clk), .RN(n2751), .Q(
DMP_SFG[27]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n684), .CK(clk), .RN(n1335), .Q(
DMP_SFG[26]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n689), .CK(clk), .RN(n1338), .Q(
DMP_SFG[25]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n694), .CK(clk), .RN(n1337), .Q(
DMP_SFG[24]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n699), .CK(clk), .RN(n1336), .Q(
DMP_SFG[23]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n702), .CK(clk), .RN(n1337), .Q(
DMP_SFG[22]) );
DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n597), .CK(clk), .RN(n1337), .Q(
SIGN_FLAG_SFG) );
DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n606), .CK(clk), .RN(n1336), .Q(
ZERO_FLAG_SFG) );
DFFRHQX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n919), .CK(clk), .RN(n1336), .Q(
Shift_reg_FLAGS_7_5) );
DFFRHQX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n916), .CK(clk), .RN(n2749), .Q(
Shift_reg_FLAGS_7[2]) );
DFFRHQX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n914), .CK(clk), .RN(n1338), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n553), .CK(clk), .RN(n1335),
.Q(DmP_mant_SFG_SWR[11]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n575), .CK(clk), .RN(n1337), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n557), .CK(clk), .RN(n1338), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRHQX2TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n772), .CK(clk), .RN(n1335), .Q(
ZERO_FLAG_EXP) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n515), .CK(clk), .RN(n1338),
.Q(DmP_mant_SFG_SWR[24]) );
DFFSRHQX8TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .SN(1'b1), .RN(n1336),
.Q(inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFSRHQX8TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n586), .CK(clk), .SN(1'b1),
.RN(n1335), .Q(Raw_mant_NRM_SWR[21]) );
DFFSRHQX8TS R_195_IP ( .D(n1409), .CK(clk), .SN(1'b1), .RN(n1338), .Q(n2746)
);
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n700), .CK(clk), .RN(n1309), .Q(
DMP_SHT2_EWSW[23]), .QN(n2438) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n658), .CK(clk), .RN(n2754), .Q(
DmP_mant_SHT1_SW[1]) );
DFFSHQX8TS R_202 ( .D(n2733), .CK(clk), .SN(n1335), .Q(n2777) );
DFFRX4TS R_212 ( .D(n2588), .CK(clk), .RN(n1321), .Q(
DmP_mant_SFG_SWR_signed_13_) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n551), .CK(clk), .RN(n2758), .Q(
DmP_mant_SFG_SWR[10]), .QN(n2543) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n815), .CK(clk), .RN(n1337),
.QN(n2487) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n2752), .Q(
DmP_mant_SFG_SWR[1]), .QN(n2534) );
DFFSX2TS R_158 ( .D(n2853), .CK(clk), .SN(n1325), .Q(n2628) );
DFFSX2TS R_159 ( .D(n2852), .CK(clk), .SN(n1325), .Q(n2627) );
DFFSX2TS R_87 ( .D(n2847), .CK(clk), .SN(n1325), .Q(n2678) );
DFFSX2TS R_86 ( .D(n2846), .CK(clk), .SN(n1325), .Q(n2679) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n572), .CK(clk), .RN(n1324), .Q(
DmP_mant_SFG_SWR[0]), .QN(n2533) );
DFFRX4TS R_133 ( .D(n2869), .CK(clk), .RN(n1323), .Q(n2651) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n730), .CK(clk), .RN(n2763), .Q(
DMP_SHT2_EWSW[13]), .QN(n2439) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n733), .CK(clk), .RN(n1325), .Q(
DMP_SHT2_EWSW[12]), .QN(n2440) );
DFFSX2TS R_217 ( .D(n1302), .CK(clk), .SN(n2752), .Q(n1297) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n621), .CK(clk), .RN(n1315), .Q(
n1296) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n800), .CK(clk), .RN(n2763), .Q(n1295) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n560), .CK(clk), .RN(n2564),
.Q(n1265) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n617), .CK(clk), .RN(n2756), .Q(
DmP_EXP_EWSW[22]) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n875), .CK(clk), .RN(n2768),
.Q(n1262) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n890), .CK(clk), .RN(n2773),
.Q(n1300) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n877), .CK(clk), .RN(n2768),
.Q(n1260) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n804), .CK(clk), .RN(n2759), .Q(
DMP_EXP_EWSW[0]) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n864), .CK(clk), .RN(n2769),
.Q(n1258) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n866), .CK(clk), .RN(n2769),
.Q(n1256) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n873), .CK(clk), .RN(n2768),
.Q(n1254) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n865), .CK(clk), .RN(n2769),
.Q(n1251) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n867), .CK(clk), .RN(n2769),
.Q(n1249) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n878), .CK(clk), .RN(n2767),
.Q(n1240) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n657), .CK(clk), .RN(n2568), .Q(
DmP_EXP_EWSW[2]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n796), .CK(clk), .RN(n2757), .Q(
DMP_EXP_EWSW[8]) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n1315),
.Q(n1238) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n631), .CK(clk), .RN(n1321), .Q(
DmP_EXP_EWSW[15]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n635), .CK(clk), .RN(n1326), .Q(
DmP_EXP_EWSW[13]) );
DFFRHQX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n910), .CK(clk), .RN(n2771),
.Q(n1237) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n649), .CK(clk), .RN(n1310), .Q(n1234) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n627), .CK(clk), .RN(n2755), .Q(
n1233) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n611), .CK(clk), .RN(n2762), .Q(
n1232) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n584), .CK(clk), .RN(n2758),
.Q(n1230) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n643), .CK(clk), .RN(n1309), .Q(n1229) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n619), .CK(clk), .RN(n2753), .Q(
n1228) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n653), .CK(clk), .RN(n1311), .Q(n1227) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n876), .CK(clk), .RN(n2768),
.Q(n1225) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n625), .CK(clk), .RN(n2562), .Q(
n1224) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n798), .CK(clk), .RN(n2756), .Q(n1223) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n573), .CK(clk), .RN(n2564),
.Q(n1220) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n778), .CK(clk), .RN(n2765), .Q(
n1219) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n2762), .Q(
n1217) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n802), .CK(clk), .RN(n2754), .Q(
DMP_EXP_EWSW[2]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n633), .CK(clk), .RN(n2760), .Q(
n1216) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n783), .CK(clk), .RN(n1311), .Q(
DMP_EXP_EWSW[21]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n2762), .Q(
n1214) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n629), .CK(clk), .RN(n1315), .Q(
n1213) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n651), .CK(clk), .RN(n1327), .Q(n1212) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n623), .CK(clk), .RN(n1312), .Q(
n1211) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n801), .CK(clk), .RN(n1312), .Q(n1210) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n639), .CK(clk), .RN(n1310), .Q(
DmP_EXP_EWSW[11]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n641), .CK(clk), .RN(n1310), .Q(
n1208) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n2750), .Q(
DMP_EXP_EWSW[20]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n791), .CK(clk), .RN(n2763), .Q(
DMP_EXP_EWSW[13]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n790), .CK(clk), .RN(n1314), .Q(
DMP_EXP_EWSW[14]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n789), .CK(clk), .RN(n1313), .Q(
DMP_EXP_EWSW[15]) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n588), .CK(clk), .RN(n1309),
.Q(n1201) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n775), .CK(clk), .RN(n2767), .Q(
DMP_EXP_EWSW[29]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n777), .CK(clk), .RN(n2765), .Q(
DMP_EXP_EWSW[27]) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n816), .CK(clk), .RN(n2559),
.QN(n2542) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n587), .CK(clk), .RN(n1338),
.Q(n1190) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n590), .CK(clk), .RN(n1327),
.Q(n1185) );
DFFSX2TS R_207 ( .D(n2915), .CK(clk), .SN(n2561), .Q(n2593) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n871), .CK(clk), .RN(n2768),
.Q(n1182) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n793), .CK(clk), .RN(n1314), .Q(
n1179) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n2750), .Q(
n1176) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n637), .CK(clk), .RN(n1326), .Q(
n1175) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n661), .CK(clk), .RN(n2562), .Q(n1174) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n645), .CK(clk), .RN(n1310), .Q(n1173) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n788), .CK(clk), .RN(n2562), .Q(
n1170) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n797), .CK(clk), .RN(n2762), .Q(n1169) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n774), .CK(clk), .RN(n2767), .Q(
n1168) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n799), .CK(clk), .RN(n2764), .Q(n1167) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n782), .CK(clk), .RN(n1311), .Q(
n1166) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n786), .CK(clk), .RN(n2750), .Q(
n1165) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n792), .CK(clk), .RN(n2562), .Q(
n1164) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n647), .CK(clk), .RN(n1309), .Q(n1163) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n776), .CK(clk), .RN(n2766), .Q(
n1162) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n655), .CK(clk), .RN(n1326), .Q(n1161) );
DFFSX4TS R_242 ( .D(n2781), .CK(clk), .SN(n1314), .Q(n2571) );
DFFRHQX2TS R_167 ( .D(n549), .CK(clk), .RN(n1322), .Q(n1159) );
DFFSX4TS R_231 ( .D(n931), .CK(clk), .SN(n2755), .Q(n2579) );
DFFSX2TS R_252 ( .D(n986), .CK(clk), .SN(n2559), .Q(n1158) );
DFFSX2TS R_253 ( .D(n2734), .CK(clk), .SN(n2563), .Q(n1157) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n618), .CK(clk), .RN(n2565), .Q(
DmP_mant_SHT1_SW[21]), .QN(n2429) );
DFFSX1TS R_36 ( .D(n2814), .CK(clk), .SN(n2569), .Q(n2713) );
DFFSX2TS R_139 ( .D(n2743), .CK(clk), .SN(n1305), .Q(n2647) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n554), .CK(clk), .RN(n2758), .Q(
Raw_mant_NRM_SWR[11]), .QN(n2737) );
DFFSX2TS R_271 ( .D(n975), .CK(clk), .SN(n2560), .Q(n1150) );
DFFSX2TS R_272 ( .D(n2913), .CK(clk), .SN(n2755), .Q(n1149) );
DFFSX2TS R_273 ( .D(n977), .CK(clk), .SN(n2756), .Q(n1148) );
DFFSX2TS R_274 ( .D(n977), .CK(clk), .SN(n1313), .Q(n1147) );
DFFSX2TS R_275 ( .D(n2924), .CK(clk), .SN(n2567), .Q(n1146) );
DFFSX2TS R_276 ( .D(n2778), .CK(clk), .SN(n2566), .Q(n1145) );
DFFSX2TS R_277 ( .D(n2741), .CK(clk), .SN(n2560), .Q(n1144) );
DFFSX2TS R_278 ( .D(n986), .CK(clk), .SN(n1324), .Q(n1143) );
DFFSX2TS R_279 ( .D(n2779), .CK(clk), .SN(n1337), .Q(n1142) );
DFFSX2TS R_280 ( .D(n1734), .CK(clk), .SN(n1337), .Q(n1141), .QN(ready) );
DFFRX2TS R_281 ( .D(n2745), .CK(clk), .RN(n2756), .Q(n1139) );
DFFSX4TS R_282 ( .D(n2870), .CK(clk), .SN(n1324), .Q(n1138) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n887), .CK(clk), .RN(n2773),
.Q(n1299) );
DFFSX2TS R_136 ( .D(n2866), .CK(clk), .SN(n1324), .Q(n2648) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n714), .CK(clk), .RN(n1327), .Q(
DMP_SFG[18]), .QN(n2518) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n634), .CK(clk), .RN(n1326), .Q(
DmP_mant_SHT1_SW[13]), .QN(n2421) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n888), .CK(clk), .RN(n2773),
.Q(n1244) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n630), .CK(clk), .RN(n1321), .Q(
DmP_mant_SHT1_SW[15]), .QN(n2492) );
DFFSX2TS R_162 ( .D(n2835), .CK(clk), .SN(n2758), .Q(n2624) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n787), .CK(clk), .RN(n2754), .Q(n956) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n869), .CK(clk), .RN(n2768),
.Q(n951) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n659), .CK(clk), .RN(n2755), .Q(n950)
);
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n2759), .Q(n949)
);
DFFSX2TS R_96 ( .D(n2483), .CK(clk), .SN(n2569), .Q(n2671) );
DFFRX4TS R_214 ( .D(n592), .CK(clk), .RN(n1304), .Q(Raw_mant_NRM_SWR[15]) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n585), .CK(clk), .RN(n1323),
.Q(n1196) );
DFFSX2TS R_135 ( .D(n2867), .CK(clk), .SN(n1324), .Q(n2649) );
DFFSX4TS R_255 ( .D(n2426), .CK(clk), .SN(n2566), .Q(n1155) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n893), .CK(clk), .RN(n2772),
.Q(n1247) );
DFFSX4TS R_254 ( .D(n1316), .CK(clk), .SN(n2568), .Q(n1156) );
DFFRX4TS R_143 ( .D(n2830), .CK(clk), .RN(n2568), .Q(n2643) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n564), .CK(clk), .RN(n1326), .Q(
DmP_mant_SFG_SWR[5]), .QN(n2535) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n921), .CK(clk), .RN(
n2774), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2530) );
DFFRHQX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n692), .CK(clk), .RN(n1314),
.Q(n1177) );
DFFRHQX4TS R_215_IP ( .D(n592), .CK(clk), .RN(n1337), .Q(n2461) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n891), .CK(clk), .RN(n2773),
.Q(n1301) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n886), .CK(clk), .RN(n2773),
.Q(n1246) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n747), .CK(clk), .RN(n2762), .Q(
DMP_SFG[7]), .QN(n2430) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n2754), .Q(
DMP_SFG[2]), .QN(n2422) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n779), .CK(clk), .RN(n1312), .Q(
n1180) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n562), .CK(clk), .RN(n1323), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2541) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n848), .CK(clk), .RN(n2764),
.Q(intDY_EWSW[31]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n744), .CK(clk), .RN(n2757), .Q(
DMP_SFG[8]), .QN(n2556) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n780), .CK(clk), .RN(n2775), .Q(n955) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n753), .CK(clk), .RN(n2764), .Q(
DMP_SFG[5]), .QN(n2425) );
DFFRX2TS R_116 ( .D(n571), .CK(clk), .RN(n1323), .Q(Raw_mant_NRM_SWR[0]) );
DFFRX1TS R_211 ( .D(n581), .CK(clk), .RN(n2752), .Q(DmP_mant_SFG_SWR[13]),
.QN(n2502) );
DFFSX4TS R_270 ( .D(n975), .CK(clk), .SN(n1309), .QN(n923) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n622), .CK(clk), .SN(1'b1),
.RN(n1335), .Q(DmP_mant_SHT1_SW[19]) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n650), .CK(clk), .SN(1'b1),
.RN(n1338), .Q(DmP_mant_SHT1_SW[5]) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n638), .CK(clk), .SN(1'b1),
.RN(n1335), .Q(DmP_mant_SHT1_SW[11]) );
DFFRX2TS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n811), .CK(clk), .RN(n2559), .Q(
final_result_ieee[24]), .QN(n1277) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n652), .CK(clk), .RN(n2761), .Q(
DmP_mant_SHT1_SW[4]), .QN(n2551) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n795), .CK(clk), .RN(n1321), .Q(n1242) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n813), .CK(clk), .RN(n1304),
.QN(n2485) );
DFFSRHQX2TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n666), .CK(clk), .SN(1'b1), .RN(
n1338), .Q(DMP_SHT1_EWSW[30]) );
DFFSRHQX2TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n596), .CK(clk), .SN(1'b1), .RN(
n1336), .Q(SIGN_FLAG_NRM) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n626), .CK(clk), .RN(n2562), .Q(
DmP_mant_SHT1_SW[17]), .QN(n2426) );
AO22X2TS U930 ( .A0(n1356), .A1(n2338), .B0(n2200), .B1(n974), .Y(n2788) );
OAI21X2TS U931 ( .A0(n1341), .A1(n990), .B0(n1032), .Y(n2830) );
NAND2X2TS U932 ( .A(n1038), .B(Raw_mant_NRM_SWR[24]), .Y(n2861) );
NAND2X4TS U933 ( .A(n2219), .B(n1044), .Y(n2785) );
NOR2X6TS U934 ( .A(n2286), .B(n2162), .Y(n609) );
NAND2X4TS U935 ( .A(n1037), .B(n2226), .Y(n2852) );
NAND3X4TS U936 ( .A(n2065), .B(n2064), .C(n2063), .Y(n629) );
NAND2X2TS U937 ( .A(n1401), .B(n1254), .Y(n2107) );
NAND2X6TS U938 ( .A(n2128), .B(n1003), .Y(n2052) );
NAND2X4TS U939 ( .A(n954), .B(intDY_EWSW[20]), .Y(n2003) );
NAND2X1TS U940 ( .A(n983), .B(n1196), .Y(n1747) );
NAND2X1TS U941 ( .A(n1629), .B(Raw_mant_NRM_SWR[21]), .Y(n1758) );
NAND2X1TS U942 ( .A(n1331), .B(n1201), .Y(n1535) );
NAND2X4TS U943 ( .A(n1136), .B(n2557), .Y(n1135) );
NAND2X1TS U944 ( .A(n980), .B(DmP_mant_SFG_SWR[24]), .Y(n1344) );
INVX12TS U945 ( .A(n990), .Y(n1038) );
NAND2XLTS U946 ( .A(n1331), .B(n2346), .Y(n1630) );
MXI2X1TS U947 ( .A(n2318), .B(final_result_ieee[23]), .S0(n2779), .Y(n2319)
);
NAND2XLTS U948 ( .A(n2145), .B(DMP_EXP_EWSW[13]), .Y(n2142) );
NAND2XLTS U949 ( .A(n2138), .B(DMP_EXP_EWSW[8]), .Y(n2125) );
NAND2XLTS U950 ( .A(n2130), .B(n1228), .Y(n2081) );
BUFX16TS U951 ( .A(n1171), .Y(n1044) );
OAI22X2TS U952 ( .A0(n2255), .A1(n2504), .B0(n2188), .B1(n2159), .Y(n2189)
);
NOR2X1TS U953 ( .A(n2485), .B(n2343), .Y(n2385) );
NAND2X6TS U954 ( .A(intDY_EWSW[0]), .B(n1360), .Y(n2101) );
NAND2X2TS U955 ( .A(n945), .B(intDY_EWSW[20]), .Y(n2042) );
NAND2XLTS U956 ( .A(n2109), .B(n1169), .Y(n2110) );
NAND2XLTS U957 ( .A(n2145), .B(n1167), .Y(n2119) );
NAND2XLTS U958 ( .A(n2138), .B(n1161), .Y(n2056) );
NAND2XLTS U959 ( .A(n2138), .B(n1174), .Y(n2059) );
NAND2XLTS U960 ( .A(n2130), .B(n1223), .Y(n2106) );
NAND2XLTS U961 ( .A(n2145), .B(n1179), .Y(n2113) );
NAND2XLTS U962 ( .A(n2145), .B(n1164), .Y(n2122) );
NAND2XLTS U963 ( .A(n2130), .B(n1216), .Y(n2087) );
NAND2XLTS U964 ( .A(n2130), .B(n1175), .Y(n2096) );
NAND2XLTS U965 ( .A(n2138), .B(n1166), .Y(n1996) );
NAND2XLTS U966 ( .A(n2130), .B(n1295), .Y(n2131) );
NAND2XLTS U967 ( .A(n2138), .B(n1242), .Y(n2139) );
NAND2X1TS U968 ( .A(n1283), .B(n1284), .Y(n2321) );
NAND2X6TS U969 ( .A(n1761), .B(n1760), .Y(n2177) );
CLKINVX1TS U970 ( .A(n1328), .Y(n961) );
NAND2XLTS U971 ( .A(n2109), .B(DMP_EXP_EWSW[10]), .Y(n2102) );
NAND2XLTS U972 ( .A(n2109), .B(n1224), .Y(n2053) );
NAND2XLTS U973 ( .A(n2109), .B(n1233), .Y(n2084) );
NAND2XLTS U974 ( .A(n2109), .B(n1211), .Y(n2093) );
NAND2X6TS U975 ( .A(n2128), .B(intDY_EWSW[27]), .Y(n2148) );
NAND2X2TS U976 ( .A(n2017), .B(intDY_EWSW[11]), .Y(n2051) );
NAND2X2TS U977 ( .A(n1075), .B(n998), .Y(n2013) );
NAND2X2TS U978 ( .A(n1361), .B(intDX_EWSW[1]), .Y(n1403) );
CLKBUFX2TS U979 ( .A(n2461), .Y(n2338) );
NAND2X2TS U980 ( .A(n954), .B(intDY_EWSW[24]), .Y(n1944) );
XOR2X2TS U981 ( .A(n2272), .B(n1987), .Y(n1988) );
OR2X4TS U982 ( .A(n1358), .B(n1357), .Y(n2324) );
INVX4TS U983 ( .A(n1010), .Y(n1009) );
INVX4TS U984 ( .A(n1017), .Y(n1016) );
NAND2X2TS U985 ( .A(n1364), .B(n995), .Y(n2104) );
NAND2X4TS U986 ( .A(n1402), .B(intDY_EWSW[22]), .Y(n2079) );
NAND2X2TS U987 ( .A(n959), .B(n1109), .Y(n1108) );
XOR2X2TS U988 ( .A(n1292), .B(n1505), .Y(n1506) );
NAND2XLTS U989 ( .A(n964), .B(n939), .Y(n938) );
NOR2X2TS U990 ( .A(n2227), .B(n2489), .Y(n1040) );
NAND2XLTS U991 ( .A(n960), .B(n933), .Y(n932) );
BUFX16TS U992 ( .A(n2258), .Y(n1364) );
INVX12TS U993 ( .A(n2227), .Y(n1339) );
BUFX6TS U994 ( .A(n2062), .Y(n2130) );
BUFX6TS U995 ( .A(n2062), .Y(n2138) );
OAI2BB1X2TS U996 ( .A0N(n1192), .A1N(n1408), .B0(n1742), .Y(n1746) );
BUFX12TS U997 ( .A(n2258), .Y(n1361) );
NOR2X1TS U998 ( .A(n1962), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1963)
);
BUFX4TS U999 ( .A(n2062), .Y(n2109) );
CLKBUFX2TS U1000 ( .A(n1333), .Y(n2022) );
NAND2X6TS U1001 ( .A(n978), .B(n1196), .Y(n1047) );
NAND2X1TS U1002 ( .A(n1333), .B(n2190), .Y(n1583) );
NAND2XLTS U1003 ( .A(n1755), .B(n1754), .Y(n1756) );
CLKBUFX2TS U1004 ( .A(intDX_EWSW[10]), .Y(n995) );
NAND2X1TS U1005 ( .A(n1586), .B(n1608), .Y(n1584) );
NAND2X6TS U1006 ( .A(Raw_mant_NRM_SWR[2]), .B(n1025), .Y(n1027) );
NAND2X1TS U1007 ( .A(n2293), .B(n2292), .Y(n2294) );
NAND2X1TS U1008 ( .A(n2310), .B(n2309), .Y(n2311) );
NOR2X1TS U1009 ( .A(n1981), .B(n1984), .Y(n1729) );
NAND2XLTS U1010 ( .A(n1532), .B(n1617), .Y(n1533) );
NAND2XLTS U1011 ( .A(n1680), .B(n1679), .Y(n1681) );
NAND2XLTS U1012 ( .A(n2745), .B(n2234), .Y(n1065) );
NOR2X1TS U1013 ( .A(n1596), .B(n2134), .Y(n1597) );
NOR2X2TS U1014 ( .A(n1669), .B(n1668), .Y(n1670) );
XOR2X1TS U1015 ( .A(DP_OP_301J12_122_1182_n171), .B(DMP_SFG[10]), .Y(n1987)
);
NOR2X2TS U1016 ( .A(n2246), .B(n2245), .Y(n2248) );
AOI22X1TS U1017 ( .A0(n2021), .A1(n2220), .B0(n1608), .B1(n1607), .Y(n1609)
);
AOI22X1TS U1018 ( .A0(n836), .A1(n1333), .B0(n1935), .B1(n1934), .Y(n1778)
);
NAND2X2TS U1019 ( .A(n2244), .B(n1353), .Y(n2249) );
NAND2X2TS U1020 ( .A(n1092), .B(n1089), .Y(n1088) );
AOI22X1TS U1021 ( .A0(n836), .A1(n1120), .B0(n2021), .B1(n1934), .Y(n1936)
);
AOI21X1TS U1022 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n2203), .B0(n1359), .Y(
n2205) );
NAND2XLTS U1023 ( .A(n2387), .B(n2223), .Y(n1064) );
INVX2TS U1024 ( .A(n2545), .Y(n939) );
INVX2TS U1025 ( .A(n2549), .Y(n933) );
CLKINVX2TS U1026 ( .A(n1328), .Y(n959) );
AOI22X1TS U1027 ( .A0(n1359), .A1(DmP_mant_SHT1_SW[5]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2213) );
NOR2X1TS U1028 ( .A(n1334), .B(n985), .Y(n1357) );
OAI22X2TS U1029 ( .A0(n1764), .A1(n2496), .B0(n2174), .B1(n2421), .Y(n1765)
);
NAND2X2TS U1030 ( .A(n2244), .B(n2149), .Y(n2158) );
NOR4X4TS U1031 ( .A(n1639), .B(n1638), .C(n1637), .D(n1636), .Y(n1673) );
BUFX6TS U1032 ( .A(n2209), .Y(n1046) );
OAI2BB1X2TS U1033 ( .A0N(n2154), .A1N(n2153), .B0(n2152), .Y(n2155) );
BUFX6TS U1034 ( .A(n2062), .Y(n2145) );
BUFX16TS U1035 ( .A(n1352), .Y(n978) );
NAND2X2TS U1036 ( .A(n1989), .B(n2234), .Y(n1092) );
XOR2X1TS U1037 ( .A(n2273), .B(DmP_mant_SFG_SWR[13]), .Y(n2274) );
NAND2X2TS U1038 ( .A(n1120), .B(n2172), .Y(n1111) );
NAND2X6TS U1039 ( .A(n1588), .B(n1320), .Y(n1114) );
NAND3X2TS U1040 ( .A(n2626), .B(n2625), .C(n2624), .Y(n2222) );
NAND2X2TS U1041 ( .A(n1733), .B(n1892), .Y(n1112) );
OR2X2TS U1042 ( .A(n2327), .B(DMP_SFG[6]), .Y(n1923) );
BUFX12TS U1043 ( .A(n1348), .Y(n1024) );
NAND3X2TS U1044 ( .A(n1072), .B(n1061), .C(n1904), .Y(n2243) );
NOR3X1TS U1045 ( .A(n2499), .B(n997), .C(Raw_mant_NRM_SWR[2]), .Y(n2149) );
NOR2X6TS U1046 ( .A(n1764), .B(n974), .Y(n1375) );
OR2X2TS U1047 ( .A(n1134), .B(n1279), .Y(n1130) );
NAND3X6TS U1048 ( .A(n1720), .B(n1721), .C(n1719), .Y(n1136) );
NAND2X2TS U1049 ( .A(n1120), .B(n2190), .Y(n1113) );
NAND2X2TS U1050 ( .A(n1072), .B(n2240), .Y(n2241) );
NAND3X6TS U1051 ( .A(n1080), .B(n1078), .C(n1079), .Y(n944) );
NAND2X2TS U1052 ( .A(n2291), .B(n1274), .Y(n1392) );
OR2X2TS U1053 ( .A(n1581), .B(n1560), .Y(n1562) );
OAI21X2TS U1054 ( .A0(n2197), .A1(n1203), .B0(n1493), .Y(n1548) );
NAND2X4TS U1055 ( .A(n1558), .B(n1892), .Y(n1089) );
NAND2X1TS U1056 ( .A(n1773), .B(n2234), .Y(n1589) );
INVX2TS U1057 ( .A(n1952), .Y(n1328) );
INVX2TS U1058 ( .A(n1615), .Y(n2310) );
NOR2X4TS U1059 ( .A(n1281), .B(n2386), .Y(n1892) );
INVX2TS U1060 ( .A(n1134), .Y(n1132) );
NOR2X6TS U1061 ( .A(n1330), .B(n1931), .Y(n1608) );
NOR3X6TS U1062 ( .A(n1764), .B(n1384), .C(n1385), .Y(n1685) );
NAND2X4TS U1063 ( .A(n1607), .B(n1330), .Y(n1592) );
INVX2TS U1064 ( .A(n1750), .Y(n2293) );
NAND2X4TS U1065 ( .A(n1518), .B(n1931), .Y(n1080) );
NAND2X4TS U1066 ( .A(n1907), .B(n997), .Y(n1387) );
NAND2X2TS U1067 ( .A(n1332), .B(n976), .Y(n1118) );
INVX8TS U1068 ( .A(n1334), .Y(n974) );
NAND2X2TS U1069 ( .A(n1772), .B(n836), .Y(n1510) );
INVX4TS U1070 ( .A(n2174), .Y(n1359) );
NAND2X6TS U1071 ( .A(n1518), .B(n976), .Y(n1127) );
XNOR2X1TS U1072 ( .A(intDY_EWSW[27]), .B(n1246), .Y(n1634) );
XNOR2X1TS U1073 ( .A(intDY_EWSW[23]), .B(n1300), .Y(n1647) );
XNOR2X1TS U1074 ( .A(intDY_EWSW[22]), .B(n1301), .Y(n1646) );
NAND2X4TS U1075 ( .A(n1517), .B(n976), .Y(n1078) );
NAND2X2TS U1076 ( .A(n1914), .B(n1913), .Y(n2152) );
NAND2X2TS U1077 ( .A(n2237), .B(n2419), .Y(n1495) );
BUFX3TS U1078 ( .A(n2377), .Y(n962) );
NAND2X4TS U1079 ( .A(n1983), .B(n1982), .Y(n1986) );
NAND2X4TS U1080 ( .A(n1891), .B(n1330), .Y(n1081) );
XNOR2X1TS U1081 ( .A(n1260), .B(intDX_EWSW[2]), .Y(n1655) );
XNOR2X1TS U1082 ( .A(n1225), .B(n1264), .Y(n1663) );
XNOR2X1TS U1083 ( .A(intDY_EWSW[17]), .B(intDX_EWSW[17]), .Y(n1633) );
NAND2X2TS U1084 ( .A(n1099), .B(n2322), .Y(n1107) );
NAND2X2TS U1085 ( .A(n1098), .B(n1934), .Y(n1093) );
NAND2X2TS U1086 ( .A(n1566), .B(n1927), .Y(n1094) );
BUFX3TS U1087 ( .A(n1199), .Y(n927) );
NAND2X4TS U1088 ( .A(n1098), .B(n2190), .Y(n1087) );
NAND2X1TS U1089 ( .A(n1772), .B(n2253), .Y(n1580) );
INVX2TS U1090 ( .A(n2322), .Y(n985) );
NOR2X4TS U1091 ( .A(DMP_EXP_EWSW[23]), .B(n2531), .Y(n2380) );
INVX8TS U1092 ( .A(n2212), .Y(n1764) );
NAND2X1TS U1093 ( .A(n1577), .B(n834), .Y(n1570) );
INVX6TS U1094 ( .A(n1981), .Y(n1983) );
BUFX6TS U1095 ( .A(n1935), .Y(n1120) );
INVX4TS U1096 ( .A(n2174), .Y(n1374) );
NAND2X6TS U1097 ( .A(n1537), .B(n1410), .Y(n1733) );
NAND2BX2TS U1098 ( .AN(n1429), .B(n2253), .Y(n1085) );
NOR2X2TS U1099 ( .A(n1728), .B(DMP_SFG[9]), .Y(n1984) );
INVX4TS U1100 ( .A(n1616), .Y(n1621) );
NAND2X1TS U1101 ( .A(n1332), .B(n2190), .Y(n1104) );
INVX2TS U1102 ( .A(n1931), .Y(n976) );
BUFX6TS U1103 ( .A(n2386), .Y(n1330) );
OR2X4TS U1104 ( .A(n1503), .B(n2430), .Y(n1293) );
INVX12TS U1105 ( .A(n1199), .Y(n1907) );
NAND3X6TS U1106 ( .A(n1708), .B(n1707), .C(n1706), .Y(n1712) );
NAND2X2TS U1107 ( .A(n1767), .B(n2173), .Y(n1102) );
NAND2X4TS U1108 ( .A(n1098), .B(n2172), .Y(n1100) );
NAND2X2TS U1109 ( .A(n1582), .B(n2201), .Y(n1537) );
NAND2X4TS U1110 ( .A(n1511), .B(n984), .Y(n1410) );
INVX2TS U1111 ( .A(n1559), .Y(n1767) );
NAND2X6TS U1112 ( .A(n979), .B(n1035), .Y(n1199) );
NAND2BX2TS U1113 ( .AN(n2619), .B(n1101), .Y(n2172) );
NAND2X4TS U1114 ( .A(n1106), .B(n1105), .Y(n2190) );
AND4X4TS U1115 ( .A(n2371), .B(n1737), .C(n2389), .D(n1736), .Y(n1738) );
OR2X4TS U1116 ( .A(n1429), .B(n1425), .Y(n1426) );
BUFX12TS U1117 ( .A(n1773), .Y(n1098) );
NAND2BX2TS U1118 ( .AN(n2629), .B(n1103), .Y(n2173) );
NAND2X4TS U1119 ( .A(n1511), .B(n2260), .Y(n1090) );
NAND3X6TS U1120 ( .A(n2655), .B(n1422), .C(n2654), .Y(n834) );
NAND2X2TS U1121 ( .A(n2203), .B(Shift_amount_SHT1_EWR[0]), .Y(n2174) );
NAND2X4TS U1122 ( .A(n2169), .B(n1582), .Y(n1091) );
INVX8TS U1123 ( .A(n1542), .Y(n1511) );
CLKINVX6TS U1124 ( .A(n1302), .Y(n984) );
CLKAND2X2TS U1125 ( .A(n2627), .B(n2628), .Y(n1103) );
NAND4X4TS U1126 ( .A(n2700), .B(n2699), .C(n2698), .D(n2697), .Y(n2175) );
NAND4X4TS U1127 ( .A(n2712), .B(n2711), .C(n2710), .D(n2709), .Y(n2187) );
BUFX6TS U1128 ( .A(n2307), .Y(n1204) );
NAND3X6TS U1129 ( .A(n2851), .B(n1560), .C(n2589), .Y(n1559) );
XOR2X2TS U1130 ( .A(n2273), .B(DmP_mant_SFG_SWR[24]), .Y(n1628) );
NAND4X4TS U1131 ( .A(n2678), .B(n2679), .C(n2677), .D(n1086), .Y(n2253) );
NAND2X4TS U1132 ( .A(n1623), .B(DMP_SFG[19]), .Y(n1754) );
AOI21X2TS U1133 ( .A0(n1521), .A1(n1406), .B0(n1520), .Y(n1235) );
NOR2X6TS U1134 ( .A(n1743), .B(n1678), .Y(n1627) );
INVX3TS U1135 ( .A(n1931), .Y(n2023) );
NOR2X2TS U1136 ( .A(n1735), .B(DMP_exp_NRM2_EW[7]), .Y(n1736) );
INVX12TS U1137 ( .A(n1770), .Y(n1332) );
AND2X6TS U1138 ( .A(n1839), .B(n1876), .Y(n1057) );
CLKINVX2TS U1139 ( .A(n1484), .Y(n1442) );
BUFX16TS U1140 ( .A(n979), .Y(n1072) );
NOR2X6TS U1141 ( .A(n1531), .B(DMP_SFG[17]), .Y(n1618) );
AND2X6TS U1142 ( .A(n1061), .B(n1036), .Y(n1035) );
NOR2X2TS U1143 ( .A(n1480), .B(n2203), .Y(n1482) );
NAND2X4TS U1144 ( .A(n1837), .B(n1871), .Y(n1874) );
NAND3X4TS U1145 ( .A(n1415), .B(n1441), .C(n1202), .Y(n1484) );
NOR2X1TS U1146 ( .A(n1473), .B(n1238), .Y(n1447) );
INVX4TS U1147 ( .A(n1201), .Y(n1202) );
NAND2X4TS U1148 ( .A(n1808), .B(n1825), .Y(n1827) );
NAND2X2TS U1149 ( .A(n2465), .B(intDX_EWSW[28]), .Y(n1868) );
NAND2X4TS U1150 ( .A(n2480), .B(intDX_EWSW[18]), .Y(n1843) );
CLKINVX6TS U1151 ( .A(n1245), .Y(n1137) );
NOR2X6TS U1152 ( .A(n1844), .B(n1288), .Y(n1846) );
OR3X1TS U1153 ( .A(n1185), .B(Raw_mant_NRM_SWR[21]), .C(n1230), .Y(n1206) );
NAND2X2TS U1154 ( .A(n2479), .B(n1071), .Y(n1289) );
BUFX12TS U1155 ( .A(n1423), .Y(n2386) );
NAND2X4TS U1156 ( .A(n1799), .B(n1793), .Y(n1801) );
NAND2X2TS U1157 ( .A(n2478), .B(n1244), .Y(n1858) );
BUFX16TS U1158 ( .A(n2393), .Y(n2203) );
INVX3TS U1159 ( .A(n1268), .Y(n1693) );
NOR2X6TS U1160 ( .A(n1860), .B(n1290), .Y(n1835) );
INVX2TS U1161 ( .A(n1265), .Y(n1266) );
NOR2X6TS U1162 ( .A(n2467), .B(n1246), .Y(n1863) );
NOR2X6TS U1163 ( .A(n1807), .B(n1822), .Y(n1825) );
INVX8TS U1164 ( .A(LZD_output_NRM2_EW[3]), .Y(n1686) );
NOR2X4TS U1165 ( .A(n2463), .B(intDX_EWSW[24]), .Y(n1290) );
NAND2X6TS U1166 ( .A(n2151), .B(n1436), .Y(n1438) );
NOR2X6TS U1167 ( .A(n2478), .B(n1244), .Y(n1860) );
BUFX3TS U1168 ( .A(n1247), .Y(n1071) );
INVX4TS U1169 ( .A(n1238), .Y(n1239) );
NOR2X4TS U1170 ( .A(n952), .B(intDX_EWSW[10]), .Y(n1804) );
NAND2X2TS U1171 ( .A(n2472), .B(intDX_EWSW[7]), .Y(n993) );
NOR2X4TS U1172 ( .A(n1185), .B(Raw_mant_NRM_SWR[15]), .Y(n2151) );
INVX4TS U1173 ( .A(n1230), .Y(n1231) );
NOR2X4TS U1174 ( .A(n2864), .B(Raw_mant_NRM_SWR[1]), .Y(n1351) );
NOR2X6TS U1175 ( .A(n2477), .B(intDX_EWSW[5]), .Y(n1011) );
NOR2X4TS U1176 ( .A(n2346), .B(n1201), .Y(n1448) );
NAND2X2TS U1177 ( .A(n1226), .B(n1264), .Y(n1785) );
NAND2X2TS U1178 ( .A(n1183), .B(intDX_EWSW[8]), .Y(n1286) );
NAND2X4TS U1179 ( .A(intDX_EWSW[6]), .B(n1255), .Y(n994) );
NOR2X4TS U1180 ( .A(n1226), .B(n1264), .Y(n1787) );
NAND2X2TS U1181 ( .A(n952), .B(intDX_EWSW[10]), .Y(n1812) );
INVX2TS U1182 ( .A(n1182), .Y(n1183) );
INVX4TS U1183 ( .A(n1196), .Y(n1197) );
INVX2TS U1184 ( .A(n1256), .Y(n1257) );
INVX2TS U1185 ( .A(n1258), .Y(n1259) );
INVX2TS U1186 ( .A(n1261), .Y(n1193) );
INVX2TS U1187 ( .A(n1251), .Y(n1252) );
INVX2TS U1188 ( .A(n1262), .Y(n1263) );
INVX2TS U1189 ( .A(n1249), .Y(n1250) );
CLKINVX3TS U1190 ( .A(n951), .Y(n952) );
INVX4TS U1191 ( .A(Raw_mant_NRM_SWR[21]), .Y(n1340) );
INVX3TS U1192 ( .A(n1260), .Y(n1261) );
INVX6TS U1193 ( .A(n1190), .Y(n1341) );
NAND3X6TS U1194 ( .A(n2010), .B(n2009), .C(n2008), .Y(n790) );
NAND2X4TS U1195 ( .A(n2470), .B(intDX_EWSW[17]), .Y(n1840) );
NAND4X8TS U1196 ( .A(n1388), .B(n2247), .C(n1273), .D(n2156), .Y(n1386) );
NOR2X6TS U1197 ( .A(n1796), .B(n1791), .Y(n1799) );
INVX8TS U1198 ( .A(n1376), .Y(n2209) );
NAND3X6TS U1199 ( .A(n2100), .B(n2101), .C(n2099), .Y(n804) );
NAND2X6TS U1200 ( .A(n1195), .B(n1256), .Y(n2144) );
NAND2X4TS U1201 ( .A(n1846), .B(n1399), .Y(n1834) );
NAND3X2TS U1202 ( .A(n2074), .B(n2073), .C(n2072), .Y(n611) );
NAND2X4TS U1203 ( .A(n1401), .B(n1262), .Y(n2133) );
NAND3X4TS U1204 ( .A(n2083), .B(n2082), .C(n2081), .Y(n619) );
NAND2X4TS U1205 ( .A(n1074), .B(intDY_EWSW[27]), .Y(n2073) );
INVX16TS U1206 ( .A(n972), .Y(n2255) );
NOR2X4TS U1207 ( .A(n1006), .B(n1005), .Y(n2836) );
NAND2X4TS U1208 ( .A(n1029), .B(Raw_mant_NRM_SWR[5]), .Y(n2831) );
NAND2X4TS U1209 ( .A(n1029), .B(n2338), .Y(n2823) );
XOR2X2TS U1210 ( .A(n2337), .B(n2336), .Y(n2339) );
NAND4X2TS U1211 ( .A(n1653), .B(n1652), .C(n1651), .D(n1650), .Y(n1659) );
INVX16TS U1212 ( .A(n1198), .Y(n979) );
MXI2X4TS U1213 ( .A(n2509), .B(n2422), .S0(n2373), .Y(n762) );
OAI21X4TS U1214 ( .A0(n2237), .A1(n2419), .B0(n1959), .Y(n1496) );
AND2X8TS U1215 ( .A(n1779), .B(n1778), .Y(n2889) );
NAND2X4TS U1216 ( .A(n1990), .B(n1320), .Y(n1991) );
MX2X4TS U1217 ( .A(n2314), .B(LZD_output_NRM2_EW[3]), .S0(n2393), .Y(n567)
);
OAI21X2TS U1218 ( .A0(n2159), .A1(n2197), .B0(n1318), .Y(n2869) );
OR2X4TS U1219 ( .A(n1318), .B(n2490), .Y(n2794) );
MX2X4TS U1220 ( .A(n2330), .B(n2329), .S0(n2328), .Y(n2332) );
NAND2X8TS U1221 ( .A(n1986), .B(n1985), .Y(n2272) );
NOR2X4TS U1222 ( .A(n927), .B(n2486), .Y(n2245) );
OAI21X2TS U1223 ( .A0(n2326), .A1(n2390), .B0(n2325), .Y(n921) );
NAND4X2TS U1224 ( .A(n1635), .B(n1634), .C(n1633), .D(n1632), .Y(n1639) );
XOR2X2TS U1225 ( .A(n940), .B(intDX_EWSW[7]), .Y(n1637) );
NAND2X8TS U1226 ( .A(n2238), .B(DMP_SFG[0]), .Y(n2237) );
AND2X8TS U1227 ( .A(n1992), .B(n1991), .Y(n2874) );
NAND3X2TS U1228 ( .A(n2243), .B(n2242), .C(n2241), .Y(n2250) );
AND2X8TS U1229 ( .A(n1515), .B(n1514), .Y(n2880) );
NAND2X8TS U1230 ( .A(n1083), .B(n1081), .Y(n1732) );
NAND2X8TS U1231 ( .A(n1012), .B(n1375), .Y(n1318) );
AND2X8TS U1232 ( .A(n1613), .B(n1612), .Y(n2884) );
AND2X8TS U1233 ( .A(n1594), .B(n1593), .Y(n2910) );
NAND2X8TS U1234 ( .A(LZD_output_NRM2_EW[2]), .B(n1188), .Y(n1187) );
NAND2X8TS U1235 ( .A(n970), .B(DMP_exp_NRM2_EW[2]), .Y(n1699) );
AOI21X2TS U1236 ( .A0(n1677), .A1(n1274), .B0(n1390), .Y(n1389) );
NAND2X4TS U1237 ( .A(n1391), .B(n1744), .Y(n1390) );
CLKMX2X4TS U1238 ( .A(n2270), .B(Raw_mant_NRM_SWR[6]), .S0(n1629), .Y(n556)
);
OAI21X4TS U1239 ( .A0(n2269), .A1(n2268), .B0(n2267), .Y(n2270) );
NAND3X2TS U1240 ( .A(n2136), .B(n2137), .C(n2135), .Y(n801) );
AND2X4TS U1241 ( .A(n1122), .B(n1121), .Y(n2897) );
NAND2X6TS U1242 ( .A(n1971), .B(n1970), .Y(n1975) );
NAND2X4TS U1243 ( .A(n1332), .B(n2169), .Y(n1366) );
NAND3X6TS U1244 ( .A(n2158), .B(n2157), .C(n2156), .Y(n2314) );
AOI21X4TS U1245 ( .A0(n1072), .A1(n1238), .B0(n2155), .Y(n2157) );
NAND4X6TS U1246 ( .A(n1592), .B(n1591), .C(n1590), .D(n1589), .Y(n1990) );
NAND2X4TS U1247 ( .A(n1401), .B(n1264), .Y(n2058) );
NOR2X6TS U1248 ( .A(n1700), .B(n1701), .Y(n1688) );
CLKINVX12TS U1249 ( .A(n1187), .Y(n1700) );
OAI21X2TS U1250 ( .A0(n2878), .A1(n959), .B0(n1108), .Y(n564) );
NAND3X4TS U1251 ( .A(n1404), .B(n2105), .C(n1403), .Y(n803) );
NAND2X8TS U1252 ( .A(n1975), .B(n1974), .Y(n2263) );
NAND3X4TS U1253 ( .A(n2045), .B(n2046), .C(n2044), .Y(n645) );
NAND3X4TS U1254 ( .A(n2112), .B(n2111), .C(n2110), .Y(n797) );
NAND2X8TS U1255 ( .A(n1513), .B(n1512), .Y(n1607) );
NAND2X4TS U1256 ( .A(n1582), .B(n2187), .Y(n1512) );
NAND2X6TS U1257 ( .A(n978), .B(n997), .Y(n1761) );
NAND3X6TS U1258 ( .A(n2016), .B(n2015), .C(n2014), .Y(n786) );
NAND2X4TS U1259 ( .A(n1074), .B(intDX_EWSW[18]), .Y(n2016) );
AOI2BB2X4TS U1260 ( .B0(n2173), .B1(n2745), .A0N(n1316), .A1N(n2552), .Y(
n2853) );
NAND3X8TS U1261 ( .A(n1128), .B(n1127), .C(n1126), .Y(n1125) );
BUFX20TS U1262 ( .A(n2017), .Y(n945) );
NAND2X4TS U1263 ( .A(n934), .B(n932), .Y(n522) );
BUFX12TS U1264 ( .A(n2776), .Y(n1008) );
NAND2X4TS U1265 ( .A(n1074), .B(intDY_EWSW[16]), .Y(n2064) );
NAND4X4TS U1266 ( .A(n1670), .B(n1672), .C(n1671), .D(n1673), .Y(n2262) );
NOR2X4TS U1267 ( .A(n1659), .B(n1658), .Y(n1671) );
NAND2X4TS U1268 ( .A(n1074), .B(intDY_EWSW[9]), .Y(n2030) );
NAND2X4TS U1269 ( .A(n1075), .B(n1247), .Y(n2004) );
NAND2X4TS U1270 ( .A(n1075), .B(intDX_EWSW[31]), .Y(n2921) );
AOI2BB2X2TS U1271 ( .B0(n1282), .B1(Raw_mant_NRM_SWR[2]), .A0N(n2229), .A1N(
n2429), .Y(n2821) );
BUFX12TS U1272 ( .A(n1603), .Y(n1012) );
NAND2X4TS U1273 ( .A(n1018), .B(n1044), .Y(n2838) );
XNOR2X4TS U1274 ( .A(n1979), .B(n1978), .Y(n1980) );
NAND2X4TS U1275 ( .A(n1976), .B(n2268), .Y(n1979) );
INVX4TS U1276 ( .A(n944), .Y(n2893) );
NAND2X6TS U1277 ( .A(n944), .B(n943), .Y(n942) );
NOR2X2TS U1278 ( .A(n1070), .B(n1069), .Y(n2816) );
NAND2X4TS U1279 ( .A(n945), .B(n1264), .Y(n2137) );
NAND2X6TS U1280 ( .A(n981), .B(n2383), .Y(n1487) );
NAND2X4TS U1281 ( .A(n2194), .B(n1044), .Y(n2835) );
AOI2BB2X4TS U1282 ( .B0(n2252), .B1(DmP_mant_SHT1_SW[12]), .A0N(n2229),
.A1N(n2210), .Y(n2817) );
NAND2X4TS U1283 ( .A(n2252), .B(DmP_mant_SHT1_SW[4]), .Y(n1002) );
NAND2X4TS U1284 ( .A(n2252), .B(DmP_mant_SHT1_SW[7]), .Y(n1017) );
NAND2X4TS U1285 ( .A(n2252), .B(DmP_mant_SHT1_SW[8]), .Y(n1010) );
NAND2X4TS U1286 ( .A(n2252), .B(DmP_mant_SHT1_SW[3]), .Y(n1007) );
INVX16TS U1287 ( .A(n1207), .Y(n2229) );
NAND2X4TS U1288 ( .A(n2207), .B(n1044), .Y(n2855) );
NOR2X4TS U1289 ( .A(n1385), .B(n1384), .Y(n1189) );
NAND2X4TS U1290 ( .A(n2219), .B(n2226), .Y(n2792) );
NOR2X4TS U1291 ( .A(n2324), .B(n1129), .Y(n2799) );
NAND3X6TS U1292 ( .A(n2178), .B(n2180), .C(n2179), .Y(n1018) );
NAND2X8TS U1293 ( .A(n1621), .B(n1677), .Y(n1398) );
NAND2X4TS U1294 ( .A(n1037), .B(n1044), .Y(n2841) );
INVX12TS U1295 ( .A(n1749), .Y(n1192) );
NAND2X8TS U1296 ( .A(n1123), .B(n1342), .Y(n549) );
NAND2X8TS U1297 ( .A(n1125), .B(n1124), .Y(n1123) );
BUFX20TS U1298 ( .A(n1401), .Y(n941) );
AND2X6TS U1299 ( .A(n1930), .B(n1929), .Y(n2872) );
INVX8TS U1300 ( .A(n1352), .Y(n2168) );
NAND2X4TS U1301 ( .A(n1690), .B(n1713), .Y(n1691) );
NAND4X6TS U1302 ( .A(n1539), .B(n1540), .C(n1541), .D(n1538), .Y(n1890) );
INVX12TS U1303 ( .A(n1424), .Y(n1429) );
BUFX8TS U1304 ( .A(n1062), .Y(n1029) );
INVX12TS U1305 ( .A(n1062), .Y(n2198) );
XNOR2X4TS U1306 ( .A(n2327), .B(DMP_SFG[6]), .Y(n2330) );
NAND2X4TS U1307 ( .A(n2327), .B(DMP_SFG[6]), .Y(n1921) );
NAND3X8TS U1308 ( .A(n1572), .B(n1573), .C(n1405), .Y(n1766) );
AND2X4TS U1309 ( .A(n1894), .B(n1893), .Y(n2876) );
NOR2X8TS U1310 ( .A(n1623), .B(DMP_SFG[19]), .Y(n1753) );
BUFX20TS U1311 ( .A(n2227), .Y(n1377) );
OR2X4TS U1312 ( .A(n953), .B(n1341), .Y(n2803) );
OR2X4TS U1313 ( .A(n953), .B(n1340), .Y(n2828) );
OAI21X4TS U1314 ( .A0(n1239), .A1(n953), .B0(n1378), .Y(n2815) );
NAND3X4TS U1315 ( .A(n2144), .B(n2143), .C(n2142), .Y(n791) );
NAND2X4TS U1316 ( .A(n1195), .B(intDY_EWSW[23]), .Y(n1947) );
MX2X4TS U1317 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n2402), .Y(n868) );
NAND2X6TS U1318 ( .A(intDX_EWSW[2]), .B(n1019), .Y(n2071) );
NAND2X6TS U1319 ( .A(n1025), .B(Raw_mant_NRM_SWR[8]), .Y(n1052) );
CLKBUFX2TS U1320 ( .A(intDX_EWSW[8]), .Y(n926) );
NOR2X8TS U1321 ( .A(n1201), .B(n1196), .Y(n1446) );
NOR2X8TS U1322 ( .A(n1445), .B(n1345), .Y(n1454) );
NOR2X6TS U1323 ( .A(n2461), .B(Raw_mant_NRM_SWR[16]), .Y(n1060) );
BUFX16TS U1324 ( .A(n1458), .Y(n928) );
BUFX8TS U1325 ( .A(n2737), .Y(n931) );
CLKINVX12TS U1326 ( .A(n929), .Y(n989) );
NAND4X6TS U1327 ( .A(n991), .B(n1918), .C(n1371), .D(n1470), .Y(n929) );
INVX6TS U1328 ( .A(n930), .Y(n1275) );
OAI21X4TS U1329 ( .A0(n1828), .A1(n1827), .B0(n1826), .Y(n930) );
CLKINVX1TS U1330 ( .A(n936), .Y(n2900) );
NAND2X6TS U1331 ( .A(n936), .B(n935), .Y(n934) );
INVX12TS U1332 ( .A(n960), .Y(n935) );
NAND2X6TS U1333 ( .A(n1575), .B(n1574), .Y(n936) );
BUFX6TS U1334 ( .A(n1571), .Y(n937) );
NAND2X2TS U1335 ( .A(n1332), .B(n2175), .Y(n1569) );
AND2X8TS U1336 ( .A(n1267), .B(intDY_EWSW[7]), .Y(n1796) );
CLKINVX12TS U1337 ( .A(Raw_mant_NRM_SWR[25]), .Y(n1435) );
OAI21X4TS U1338 ( .A0(n2895), .A1(n964), .B0(n938), .Y(n525) );
MXI2X4TS U1339 ( .A(n1565), .B(n2500), .S0(n980), .Y(n514) );
CLKBUFX2TS U1340 ( .A(intDY_EWSW[7]), .Y(n940) );
NAND2X6TS U1341 ( .A(n2128), .B(n998), .Y(n2077) );
OAI21X4TS U1342 ( .A0(n1362), .A1(n1841), .B0(n1840), .Y(n1847) );
AND2X8TS U1343 ( .A(n1248), .B(intDY_EWSW[17]), .Y(n1362) );
NAND3X6TS U1344 ( .A(n2052), .B(n2051), .C(n2050), .Y(n639) );
NAND2X8TS U1345 ( .A(n942), .B(n1076), .Y(n581) );
INVX12TS U1346 ( .A(n962), .Y(n943) );
NAND3X4TS U1347 ( .A(n2077), .B(n2076), .C(n2075), .Y(n631) );
NOR2X8TS U1348 ( .A(n1383), .B(n1461), .Y(n2153) );
INVX8TS U1349 ( .A(n1022), .Y(n2211) );
NOR2X4TS U1350 ( .A(n1522), .B(DMP_SFG[13]), .Y(n2333) );
NAND2X6TS U1351 ( .A(n2306), .B(n1619), .Y(n1620) );
AND3X8TS U1352 ( .A(n1585), .B(n1584), .C(n1583), .Y(n2423) );
NAND2X8TS U1353 ( .A(n1454), .B(n1452), .Y(n1198) );
AND2X8TS U1354 ( .A(n1554), .B(n1553), .Y(n2340) );
NAND2X4TS U1355 ( .A(n1364), .B(intDX_EWSW[0]), .Y(n2100) );
INVX16TS U1356 ( .A(n1429), .Y(n1774) );
AND2X8TS U1357 ( .A(n1382), .B(n1486), .Y(n1243) );
NAND2X4TS U1358 ( .A(n2177), .B(n1171), .Y(n2793) );
OAI21X4TS U1359 ( .A0(n1386), .A1(n1906), .B0(n2343), .Y(n2167) );
MXI2X4TS U1360 ( .A(n1600), .B(n2533), .S0(n1329), .Y(n572) );
INVX6TS U1361 ( .A(n1578), .Y(n1566) );
OAI21X4TS U1362 ( .A0(n947), .A1(n983), .B0(n946), .Y(n583) );
NAND2X1TS U1363 ( .A(n983), .B(Raw_mant_NRM_SWR[24]), .Y(n946) );
XNOR2X4TS U1364 ( .A(n1209), .B(n2316), .Y(n947) );
NAND2X4TS U1365 ( .A(n1451), .B(n1072), .Y(n991) );
NAND3X6TS U1366 ( .A(n1902), .B(n1903), .C(n1901), .Y(n775) );
BUFX16TS U1367 ( .A(n2258), .Y(n1402) );
NAND4BX4TS U1368 ( .AN(n2674), .B(n2673), .C(n2672), .D(n2671), .Y(n1934) );
NOR2X4TS U1369 ( .A(n1022), .B(n2462), .Y(n1051) );
OR2X6TS U1370 ( .A(n1022), .B(n2499), .Y(n2206) );
OR2X6TS U1371 ( .A(n1022), .B(n2459), .Y(n2180) );
NAND2X4TS U1372 ( .A(n2017), .B(intDX_EWSW[29]), .Y(n1903) );
NOR2X4TS U1373 ( .A(n2198), .B(n2736), .Y(n1070) );
CLKINVX12TS U1374 ( .A(n2198), .Y(n1030) );
NAND3X8TS U1375 ( .A(n1381), .B(n1446), .C(n1915), .Y(n1486) );
NOR2X8TS U1376 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[21]), .Y(
n1434) );
BUFX12TS U1377 ( .A(n1045), .Y(n1022) );
NAND3X6TS U1378 ( .A(n1602), .B(n1028), .C(n1601), .Y(n1603) );
INVX12TS U1379 ( .A(n1356), .Y(n953) );
INVX8TS U1380 ( .A(n1356), .Y(n2865) );
BUFX20TS U1381 ( .A(n1063), .Y(n954) );
NAND2X8TS U1382 ( .A(n1456), .B(n1481), .Y(n1457) );
CLKAND2X2TS U1383 ( .A(n2145), .B(n955), .Y(n1280) );
INVX4TS U1384 ( .A(n1207), .Y(n957) );
AND2X8TS U1385 ( .A(n1012), .B(n1375), .Y(n1207) );
NAND2X6TS U1386 ( .A(n954), .B(n1258), .Y(n2012) );
NAND2X4TS U1387 ( .A(n1364), .B(n926), .Y(n2127) );
BUFX12TS U1388 ( .A(n1481), .Y(n1914) );
CLKINVX12TS U1389 ( .A(n990), .Y(n987) );
INVX6TS U1390 ( .A(n1328), .Y(n958) );
INVX4TS U1391 ( .A(n1328), .Y(n960) );
MXI2X4TS U1392 ( .A(n2507), .B(n2430), .S0(n958), .Y(n747) );
BUFX12TS U1393 ( .A(n2377), .Y(n963) );
BUFX12TS U1394 ( .A(n2377), .Y(n964) );
MXI2X4TS U1395 ( .A(n2449), .B(n2516), .S0(n964), .Y(n708) );
MXI2X4TS U1396 ( .A(n2448), .B(n2522), .S0(n963), .Y(n705) );
NAND2X4TS U1397 ( .A(n962), .B(n1077), .Y(n1076) );
BUFX6TS U1398 ( .A(n1952), .Y(n2377) );
INVX2TS U1399 ( .A(n2865), .Y(n1014) );
OAI22X2TS U1400 ( .A0(n1377), .A1(n2492), .B0(n953), .B1(n2424), .Y(n2849)
);
BUFX20TS U1401 ( .A(n2865), .Y(n986) );
INVX16TS U1402 ( .A(n923), .Y(n967) );
NOR2X2TS U1403 ( .A(n2481), .B(intDX_EWSW[16]), .Y(n1400) );
AND2X2TS U1404 ( .A(n2474), .B(intDX_EWSW[30]), .Y(n1870) );
XNOR2X1TS U1405 ( .A(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1644) );
NAND2BX1TS U1406 ( .AN(Raw_mant_NRM_SWR[0]), .B(n2499), .Y(n1353) );
INVX2TS U1407 ( .A(n1197), .Y(n1021) );
AND2X2TS U1408 ( .A(n1359), .B(DmP_mant_SHT1_SW[15]), .Y(n1278) );
NAND2X1TS U1409 ( .A(n2302), .B(n2301), .Y(n2303) );
AND3X6TS U1410 ( .A(n1087), .B(n1085), .C(n1084), .Y(n1083) );
NAND3X1TS U1411 ( .A(n2623), .B(n2622), .C(n2621), .Y(n2223) );
INVX12TS U1412 ( .A(n1425), .Y(n2163) );
NAND2BX1TS U1413 ( .AN(n1334), .B(n2163), .Y(n2164) );
AOI22X1TS U1414 ( .A0(n1120), .A1(n2184), .B0(n1333), .B1(n2200), .Y(n1121)
);
NAND2X2TS U1415 ( .A(n2286), .B(n1135), .Y(n2923) );
XNOR2X1TS U1416 ( .A(n2273), .B(DmP_mant_SFG_SWR[25]), .Y(n968) );
AND2X8TS U1417 ( .A(n2744), .B(n1197), .Y(n969) );
XNOR2X4TS U1418 ( .A(n1718), .B(DMP_exp_NRM2_EW[6]), .Y(n971) );
AND2X8TS U1419 ( .A(n1189), .B(n1359), .Y(n972) );
OR2X8TS U1420 ( .A(n1559), .B(n2023), .Y(n973) );
INVX4TS U1421 ( .A(n2023), .Y(n1319) );
INVX12TS U1422 ( .A(n2529), .Y(n2383) );
INVX2TS U1423 ( .A(n1772), .Y(n1203) );
INVX8TS U1424 ( .A(n2741), .Y(n977) );
NOR2X4TS U1425 ( .A(n1024), .B(n2323), .Y(n1358) );
INVX16TS U1426 ( .A(n1024), .Y(n2226) );
INVX4TS U1427 ( .A(n2586), .Y(n1768) );
INVX4TS U1428 ( .A(n1735), .Y(n1710) );
CLKMX2X3TS U1429 ( .A(Data_X[3]), .B(n1264), .S0(n2398), .Y(n910) );
CLKMX2X3TS U1430 ( .A(Data_Y[3]), .B(n1225), .S0(n2402), .Y(n876) );
CLKMX2X3TS U1431 ( .A(Data_X[23]), .B(n1300), .S0(n2403), .Y(n890) );
INVX4TS U1432 ( .A(n2315), .Y(n1134) );
NAND2X2TS U1433 ( .A(n2349), .B(n2325), .Y(n922) );
OR2X4TS U1434 ( .A(n1628), .B(DMP_SFG[22]), .Y(n1279) );
INVX12TS U1435 ( .A(n1519), .Y(n1520) );
NAND2X1TS U1436 ( .A(n2134), .B(n1163), .Y(n2035) );
BUFX8TS U1437 ( .A(n2348), .Y(n1317) );
INVX12TS U1438 ( .A(n2360), .Y(n2406) );
INVX12TS U1439 ( .A(n2351), .Y(n2352) );
INVX12TS U1440 ( .A(n2360), .Y(n2382) );
INVX12TS U1441 ( .A(n2360), .Y(n2388) );
INVX12TS U1442 ( .A(n2351), .Y(n2407) );
NAND2X4TS U1443 ( .A(n1418), .B(DMP_SFG[12]), .Y(n1519) );
INVX2TS U1444 ( .A(n1240), .Y(n1241) );
BUFX8TS U1445 ( .A(n1237), .Y(n1264) );
NAND2X1TS U1446 ( .A(n2526), .B(n1170), .Y(n1999) );
INVX6TS U1447 ( .A(n1185), .Y(n1186) );
NOR2X6TS U1448 ( .A(n1190), .B(n1230), .Y(n1460) );
INVX2TS U1449 ( .A(n2740), .Y(n1015) );
INVX6TS U1450 ( .A(n1734), .Y(n975) );
INVX2TS U1451 ( .A(n2461), .Y(n2235) );
NAND2X1TS U1452 ( .A(n2526), .B(n1165), .Y(n2014) );
INVX2TS U1453 ( .A(SIGN_FLAG_SHT2), .Y(n2376) );
INVX3TS U1454 ( .A(n1177), .Y(n1178) );
BUFX20TS U1455 ( .A(left_right_SHT2), .Y(n1931) );
INVX4TS U1456 ( .A(n2680), .Y(n1086) );
NAND3X2TS U1457 ( .A(n2124), .B(n2123), .C(n2122), .Y(n792) );
NAND3X2TS U1458 ( .A(n2097), .B(n2098), .C(n2096), .Y(n637) );
NAND3X2TS U1459 ( .A(n2061), .B(n2060), .C(n2059), .Y(n661) );
NAND3X2TS U1460 ( .A(n1998), .B(n1997), .C(n1996), .Y(n782) );
NAND3X2TS U1461 ( .A(n2036), .B(n2037), .C(n2035), .Y(n647) );
INVX8TS U1462 ( .A(n2913), .Y(n2741) );
NAND2X4TS U1463 ( .A(n1339), .B(DmP_mant_SHT1_SW[2]), .Y(n1032) );
NAND2X6TS U1464 ( .A(n1739), .B(n2778), .Y(n1191) );
NOR2X4TS U1465 ( .A(n1023), .B(n2217), .Y(n1026) );
INVX6TS U1466 ( .A(n971), .Y(n1719) );
NAND2X4TS U1467 ( .A(n1112), .B(n1111), .Y(n1110) );
INVX2TS U1468 ( .A(n1307), .Y(n1124) );
BUFX12TS U1469 ( .A(n1935), .Y(n1989) );
NAND2X4TS U1470 ( .A(n1511), .B(n1927), .Y(n1513) );
INVX12TS U1471 ( .A(n2373), .Y(n1306) );
NAND2X4TS U1472 ( .A(n2153), .B(n1462), .Y(n1382) );
BUFX6TS U1473 ( .A(n2399), .Y(n2405) );
INVX4TS U1474 ( .A(n1469), .Y(n1152) );
NAND2X6TS U1475 ( .A(n982), .B(n1448), .Y(n1450) );
CLKMX2X3TS U1476 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(n1317), .Y(
n698) );
NAND2X2TS U1477 ( .A(n2130), .B(DmP_EXP_EWSW[22]), .Y(n2078) );
CLKMX2X3TS U1478 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(n1317), .Y(
n693) );
CLKMX2X3TS U1479 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n1317), .Y(
n673) );
MX2X1TS U1480 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n2778), .Y(n603)
);
CLKMX2X3TS U1481 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n1317), .Y(n605) );
NAND2X4TS U1482 ( .A(n1835), .B(n1865), .Y(n1838) );
CLKMX2X3TS U1483 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n1317), .Y(n596) );
INVX8TS U1484 ( .A(n2331), .Y(n1331) );
CLKMX2X2TS U1485 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(n2348), .Y(
n678) );
CLKMX2X2TS U1486 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n2348), .Y(
n668) );
CLKMX2X2TS U1487 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n2348), .Y(
n663) );
AND2X4TS U1488 ( .A(n1475), .B(n1473), .Y(n1036) );
CLKMX2X2TS U1489 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(n2348), .Y(
n683) );
CLKMX2X2TS U1490 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(n2348), .Y(
n688) );
NAND2X4TS U1491 ( .A(n1239), .B(n1473), .Y(n1474) );
INVX6TS U1492 ( .A(n1423), .Y(n1560) );
INVX2TS U1493 ( .A(n1341), .Y(n1031) );
INVX4TS U1494 ( .A(n1734), .Y(n2778) );
INVX12TS U1495 ( .A(n2558), .Y(n2344) );
INVX2TS U1496 ( .A(n2502), .Y(n1077) );
INVX2TS U1497 ( .A(n1214), .Y(n1215) );
AND2X4TS U1498 ( .A(n2704), .B(n2703), .Y(n1105) );
INVX2TS U1499 ( .A(n2734), .Y(n1042) );
AND2X4TS U1500 ( .A(n2705), .B(n2706), .Y(n1106) );
INVX2TS U1501 ( .A(DmP_mant_SHT1_SW[11]), .Y(n2210) );
NAND3X2TS U1502 ( .A(n2000), .B(n2001), .C(n1999), .Y(n788) );
NAND3X2TS U1503 ( .A(n2020), .B(n2019), .C(n2018), .Y(n785) );
NAND3X2TS U1504 ( .A(n2121), .B(n2120), .C(n2119), .Y(n799) );
NAND3X2TS U1505 ( .A(n2104), .B(n2103), .C(n2102), .Y(n794) );
NAND2X6TS U1506 ( .A(n1007), .B(n1066), .Y(n1006) );
NAND3X2TS U1507 ( .A(n1897), .B(n1896), .C(n1895), .Y(n774) );
NAND3X2TS U1508 ( .A(n1943), .B(n1942), .C(n1941), .Y(n778) );
NAND2X6TS U1509 ( .A(n1002), .B(n1064), .Y(n1001) );
NAND3X2TS U1510 ( .A(n1940), .B(n1939), .C(n1938), .Y(n779) );
NAND3X4TS U1511 ( .A(n1899), .B(n1900), .C(n1898), .Y(n776) );
NAND3X2TS U1512 ( .A(n2057), .B(n2058), .C(n2056), .Y(n655) );
NAND3X2TS U1513 ( .A(n2115), .B(n2114), .C(n2113), .Y(n793) );
NAND2X4TS U1514 ( .A(n2251), .B(n2345), .Y(n2870) );
NAND2X4TS U1515 ( .A(n1018), .B(n2226), .Y(n2802) );
NAND3X2TS U1516 ( .A(n2284), .B(n2283), .C(n2282), .Y(n573) );
INVX6TS U1517 ( .A(n2856), .Y(n2290) );
INVX12TS U1518 ( .A(n1191), .Y(n2286) );
NAND2X4TS U1519 ( .A(n2924), .B(n2321), .Y(n811) );
INVX2TS U1520 ( .A(n1125), .Y(n2891) );
AND2X6TS U1521 ( .A(n1556), .B(n1555), .Y(n2902) );
MX2X2TS U1522 ( .A(n2296), .B(n1190), .S0(n1629), .Y(n587) );
NAND2X4TS U1523 ( .A(n1732), .B(n1931), .Y(n1604) );
NAND2X6TS U1524 ( .A(n1131), .B(n1130), .Y(n1133) );
MX2X2TS U1525 ( .A(n2305), .B(n1185), .S0(n1331), .Y(n590) );
MX2X2TS U1526 ( .A(n2313), .B(Raw_mant_NRM_SWR[18]), .S0(n1629), .Y(n589) );
NAND3X6TS U1527 ( .A(n1097), .B(n1107), .C(n1096), .Y(n2024) );
MX2X2TS U1528 ( .A(n2339), .B(n2338), .S0(n1629), .Y(n592) );
NAND3X6TS U1529 ( .A(n1426), .B(n1428), .C(n1427), .Y(n1517) );
INVX2TS U1530 ( .A(n2263), .Y(n2269) );
NAND2X4TS U1531 ( .A(n1766), .B(n1330), .Y(n1097) );
AND3X6TS U1532 ( .A(n1104), .B(n1100), .C(n1102), .Y(n1096) );
INVX12TS U1533 ( .A(n1306), .Y(n1307) );
OAI2BB1X2TS U1534 ( .A0N(OP_FLAG_EXP), .A1N(n2134), .B0(n1675), .Y(n773) );
INVX12TS U1535 ( .A(n1523), .Y(n2308) );
INVX12TS U1536 ( .A(n1414), .Y(n1717) );
MXI2X2TS U1537 ( .A(n2446), .B(n2556), .S0(n1329), .Y(n744) );
MXI2X2TS U1538 ( .A(n2511), .B(n2428), .S0(n1329), .Y(n741) );
MX2X2TS U1539 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n2400), .Y(n896) );
NAND2X6TS U1540 ( .A(n1544), .B(n1543), .Y(n1891) );
MX2X2TS U1541 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n2398), .Y(n906) );
BUFX12TS U1542 ( .A(n1952), .Y(n1329) );
MX2X2TS U1543 ( .A(n1420), .B(n2746), .S0(n1629), .Y(n1409) );
INVX12TS U1544 ( .A(n1306), .Y(n980) );
AND2X2TS U1545 ( .A(n1374), .B(DmP_mant_SHT1_SW[21]), .Y(n2217) );
NAND2BX1TS U1546 ( .AN(n1160), .B(n1952), .Y(n1342) );
INVX2TS U1547 ( .A(n2320), .Y(n1285) );
MXI2X2TS U1548 ( .A(n2506), .B(n2425), .S0(n2378), .Y(n753) );
INVX3TS U1549 ( .A(n1972), .Y(n1973) );
INVX2TS U1550 ( .A(n1618), .Y(n1532) );
NOR2X4TS U1551 ( .A(n1784), .B(n1787), .Y(n1789) );
NOR2X4TS U1552 ( .A(n1834), .B(n1856), .Y(n1839) );
CLKMX2X3TS U1553 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n2388), .Y(n634) );
CLKMX2X3TS U1554 ( .A(DmP_mant_SHT1_SW[4]), .B(n1227), .S0(n2388), .Y(n652)
);
INVX8TS U1555 ( .A(n1486), .Y(n981) );
INVX12TS U1556 ( .A(n1319), .Y(n1320) );
CLKMX2X2TS U1557 ( .A(DmP_mant_SHT1_SW[7]), .B(n1163), .S0(n2388), .Y(n646)
);
CLKMX2X3TS U1558 ( .A(DmP_mant_SHT1_SW[11]), .B(DmP_EXP_EWSW[11]), .S0(n2388), .Y(n638) );
AND2X2TS U1559 ( .A(n1279), .B(n2315), .Y(n2316) );
NOR2X1TS U1560 ( .A(n975), .B(overflow_flag), .Y(n2162) );
NAND2X4TS U1561 ( .A(n1709), .B(n1713), .Y(n1735) );
CLKMX2X3TS U1562 ( .A(DMP_SHT1_EWSW[30]), .B(n1168), .S0(n2382), .Y(n666) );
CLKMX2X3TS U1563 ( .A(DmP_mant_SHT1_SW[5]), .B(n1212), .S0(n2388), .Y(n650)
);
INVX16TS U1564 ( .A(n1433), .Y(n2159) );
BUFX8TS U1565 ( .A(n1734), .Y(n2779) );
CLKMX2X3TS U1566 ( .A(DmP_mant_SHT1_SW[12]), .B(n1175), .S0(n2407), .Y(n636)
);
CLKMX2X3TS U1567 ( .A(DmP_mant_SHT1_SW[3]), .B(n1161), .S0(n2407), .Y(n654)
);
CLKMX2X3TS U1568 ( .A(DmP_mant_SHT1_SW[19]), .B(n1211), .S0(n2352), .Y(n622)
);
CLKMX2X3TS U1569 ( .A(DmP_mant_SHT1_SW[17]), .B(n1233), .S0(n2352), .Y(n626)
);
NOR2X2TS U1570 ( .A(n1649), .B(n1648), .Y(n1672) );
NOR2X6TS U1571 ( .A(n1964), .B(n1963), .Y(n2396) );
NAND2X4TS U1572 ( .A(n1220), .B(n1178), .Y(n1268) );
INVX12TS U1573 ( .A(n1380), .Y(n982) );
INVX12TS U1574 ( .A(n2331), .Y(n983) );
INVX8TS U1575 ( .A(n2351), .Y(n2350) );
INVX2TS U1576 ( .A(n2220), .Y(n1172) );
BUFX20TS U1577 ( .A(n2062), .Y(n2134) );
BUFX12TS U1578 ( .A(n1530), .Y(n1949) );
INVX2TS U1579 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1962) );
INVX6TS U1580 ( .A(n1254), .Y(n1255) );
INVX3TS U1581 ( .A(n1220), .Y(n1221) );
INVX8TS U1582 ( .A(Shift_reg_FLAGS_7_5), .Y(n2360) );
INVX6TS U1583 ( .A(n1225), .Y(n1226) );
NAND2X6TS U1584 ( .A(n1412), .B(Raw_mant_NRM_SWR[18]), .Y(n1379) );
INVX2TS U1585 ( .A(n1159), .Y(n1160) );
BUFX8TS U1586 ( .A(Shift_reg_FLAGS_7[2]), .Y(n2348) );
BUFX3TS U1587 ( .A(Raw_mant_NRM_SWR[4]), .Y(n997) );
OAI2BB1X2TS U1588 ( .A0N(n2609), .A1N(n1141), .B0(n1146), .Y(underflow_flag)
);
OAI2BB1X2TS U1589 ( .A0N(n2730), .A1N(n1142), .B0(n2729), .Y(
final_result_ieee[31]) );
INVX12TS U1590 ( .A(n2777), .Y(n1530) );
OAI2BB1X2TS U1591 ( .A0N(n2575), .A1N(n1142), .B0(n2574), .Y(
final_result_ieee[30]) );
INVX2TS U1592 ( .A(n2412), .Y(n2361) );
NOR2X4TS U1593 ( .A(n2746), .B(n1230), .Y(n1444) );
AND3X4TS U1594 ( .A(n2618), .B(n2617), .C(n2616), .Y(n1101) );
INVX2TS U1595 ( .A(n2535), .Y(n1109) );
INVX8TS U1596 ( .A(Shift_reg_FLAGS_7_5), .Y(n2351) );
INVX8TS U1597 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1629) );
INVX12TS U1598 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1734) );
INVX2TS U1599 ( .A(n1180), .Y(n1181) );
INVX16TS U1600 ( .A(n987), .Y(n988) );
INVX16TS U1601 ( .A(n989), .Y(n990) );
NOR2X8TS U1602 ( .A(n988), .B(n931), .Y(n1068) );
OAI22X4TS U1603 ( .A0(n2227), .A1(n2495), .B0(n1202), .B1(n990), .Y(n2805)
);
NOR2X8TS U1604 ( .A(n1287), .B(n2529), .Y(n1371) );
AOI2BB2X4TS U1605 ( .B0(n1914), .B1(n2746), .A0N(n1443), .A1N(n1442), .Y(
n1470) );
OAI21X4TS U1606 ( .A0(n1796), .A1(n994), .B0(n993), .Y(n1797) );
NAND2X4TS U1607 ( .A(n2471), .B(intDX_EWSW[11]), .Y(n1811) );
NAND2X8TS U1608 ( .A(n1025), .B(Raw_mant_NRM_SWR[21]), .Y(n2181) );
AOI2BB2X4TS U1609 ( .B0(n2582), .B1(n1139), .A0N(n1143), .A1N(n2581), .Y(
n1422) );
NOR2X8TS U1610 ( .A(n1345), .B(n1445), .Y(n1200) );
NAND3X8TS U1611 ( .A(n969), .B(n1186), .C(n1912), .Y(n1345) );
NAND2X8TS U1612 ( .A(n1025), .B(Raw_mant_NRM_SWR[18]), .Y(n2215) );
NOR2X6TS U1613 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[12]), .Y(
n1372) );
AOI22X4TS U1614 ( .A0(n1349), .A1(n996), .B0(n1014), .B1(n1015), .Y(n2796)
);
XOR2X4TS U1615 ( .A(DmP_mant_SFG_SWR[17]), .B(n1530), .Y(n1525) );
NOR2X2TS U1616 ( .A(n1181), .B(n1217), .Y(n1722) );
OAI21X4TS U1617 ( .A0(n1957), .A1(n1954), .B0(n1953), .Y(n1724) );
NAND3X4TS U1618 ( .A(n1095), .B(n1094), .C(n1093), .Y(n1557) );
BUFX4TS U1619 ( .A(Raw_mant_NRM_SWR[13]), .Y(n996) );
NAND2X8TS U1620 ( .A(n1394), .B(n1275), .Y(n1058) );
OAI22X4TS U1621 ( .A0(n1478), .A1(n2240), .B0(n1476), .B1(n1477), .Y(n1479)
);
BUFX6TS U1622 ( .A(intDX_EWSW[15]), .Y(n998) );
NAND2X4TS U1623 ( .A(n1990), .B(n1931), .Y(n1593) );
BUFX6TS U1624 ( .A(intDX_EWSW[13]), .Y(n999) );
NOR2X4TS U1625 ( .A(n1001), .B(n1000), .Y(n2842) );
NOR2X6TS U1626 ( .A(n1202), .B(n1033), .Y(n1000) );
OAI22X4TS U1627 ( .A0(n2255), .A1(n2498), .B0(n2254), .B1(n1334), .Y(n2256)
);
OAI21X4TS U1628 ( .A0(n1862), .A1(n1863), .B0(n1861), .Y(n1864) );
NOR2X4TS U1629 ( .A(n1068), .B(n1067), .Y(n2743) );
BUFX6TS U1630 ( .A(intDX_EWSW[11]), .Y(n1003) );
BUFX6TS U1631 ( .A(intDX_EWSW[5]), .Y(n1004) );
NOR2X4TS U1632 ( .A(n1341), .B(n1033), .Y(n1005) );
AOI21X4TS U1633 ( .A0(n2308), .A1(n1204), .B0(n2306), .Y(n2312) );
NOR2X4TS U1634 ( .A(n2236), .B(n1009), .Y(n2839) );
NOR2X4TS U1635 ( .A(n1792), .B(n1011), .Y(n1793) );
OAI21X4TS U1636 ( .A0(n1011), .A1(n1795), .B0(n1794), .Y(n1798) );
CLKINVX12TS U1637 ( .A(n1348), .Y(n1013) );
NAND2X8TS U1638 ( .A(n2159), .B(n1603), .Y(n1348) );
NAND2X8TS U1639 ( .A(n1013), .B(n1374), .Y(n1373) );
AOI2BB2X4TS U1640 ( .B0(n1482), .B1(n1481), .A0N(n2542), .A1N(n2345), .Y(
n1601) );
NAND2X8TS U1641 ( .A(n1479), .B(n979), .Y(n1028) );
AND2X8TS U1642 ( .A(n1487), .B(n1488), .Y(n1602) );
NAND3X6TS U1643 ( .A(n1995), .B(n1994), .C(n1993), .Y(n783) );
NAND2X8TS U1644 ( .A(n1300), .B(n1401), .Y(n1885) );
NAND3X6TS U1645 ( .A(n2068), .B(n2067), .C(n2066), .Y(n659) );
NAND3X6TS U1646 ( .A(n2071), .B(n2070), .C(n2069), .Y(n657) );
NAND2X6TS U1647 ( .A(n1019), .B(n1251), .Y(n2009) );
NAND3X6TS U1648 ( .A(n2080), .B(n2079), .C(n2078), .Y(n617) );
NAND3X6TS U1649 ( .A(n2092), .B(n2091), .C(n2090), .Y(n635) );
NAND2X6TS U1650 ( .A(n954), .B(n1182), .Y(n2126) );
NOR2X4TS U1651 ( .A(n2221), .B(n1016), .Y(n2790) );
BUFX20TS U1652 ( .A(n1063), .Y(n1019) );
INVX16TS U1653 ( .A(n1020), .Y(n1063) );
NAND2X8TS U1654 ( .A(n1401), .B(n1260), .Y(n2117) );
OR2X8TS U1655 ( .A(n1877), .B(n2134), .Y(n1020) );
NOR2X8TS U1656 ( .A(n1348), .B(n1045), .Y(n1062) );
NAND2X8TS U1657 ( .A(n2383), .B(n1287), .Y(n1045) );
NAND2BX4TS U1658 ( .AN(n1022), .B(n1021), .Y(n2183) );
NOR2X2TS U1659 ( .A(n1231), .B(n1045), .Y(n1049) );
NOR2X2TS U1660 ( .A(n1045), .B(n2484), .Y(n1023) );
NOR2X8TS U1661 ( .A(n2209), .B(n1045), .Y(n1356) );
BUFX20TS U1662 ( .A(n1352), .Y(n1025) );
NAND2X8TS U1663 ( .A(n1027), .B(n1026), .Y(n2219) );
NAND2X8TS U1664 ( .A(n1602), .B(n1028), .Y(n1384) );
OAI2BB1X4TS U1665 ( .A0N(n1340), .A1N(n1031), .B0(n969), .Y(n1465) );
OAI21X4TS U1666 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[3]), .B0(
n2458), .Y(n1346) );
AOI2BB2X4TS U1667 ( .B0(n1030), .B1(n1190), .A0N(n2229), .A1N(n2495), .Y(
n2843) );
NOR2X4TS U1668 ( .A(n1041), .B(n1040), .Y(n2742) );
NOR2X4TS U1669 ( .A(n2462), .B(n1033), .Y(n1067) );
NOR2X4TS U1670 ( .A(n1033), .B(n931), .Y(n1069) );
OAI22X4TS U1671 ( .A0(n1033), .A1(n2740), .B0(n1172), .B1(n1334), .Y(n2221)
);
OAI21X4TS U1672 ( .A0(n1033), .A1(n2235), .B0(n1065), .Y(n2236) );
NAND2X8TS U1673 ( .A(n1352), .B(n2278), .Y(n1033) );
NOR2X8TS U1674 ( .A(n1034), .B(n981), .Y(n1918) );
INVX12TS U1675 ( .A(n928), .Y(n1034) );
AOI22X4TS U1676 ( .A0(n1349), .A1(Raw_mant_NRM_SWR[3]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1038), .Y(n2857) );
OAI2BB1X4TS U1677 ( .A0N(n1035), .A1N(n2458), .B0(n1152), .Y(n1451) );
OAI22X2TS U1678 ( .A0(n990), .A1(n1231), .B0(n2865), .B1(n2744), .Y(n2854)
);
NAND3X8TS U1679 ( .A(n2181), .B(n2183), .C(n2182), .Y(n1037) );
AOI21X4TS U1680 ( .A0(n2177), .A1(n2226), .B0(n1039), .Y(n2832) );
NOR2X8TS U1681 ( .A(n988), .B(n2494), .Y(n1039) );
AOI2BB2X4TS U1682 ( .B0(n1349), .B1(Raw_mant_NRM_SWR[5]), .A0N(n990), .A1N(
n2734), .Y(n2846) );
NOR2X8TS U1683 ( .A(n988), .B(n2235), .Y(n1041) );
AOI22X4TS U1684 ( .A0(n1349), .A1(n1042), .B0(n1038), .B1(
Raw_mant_NRM_SWR[9]), .Y(n2812) );
NOR2X8TS U1685 ( .A(n1043), .B(n2168), .Y(n2233) );
NOR2X4TS U1686 ( .A(n2278), .B(n2281), .Y(n1043) );
INVX12TS U1687 ( .A(n1046), .Y(n1171) );
NAND2X8TS U1688 ( .A(n1048), .B(n1047), .Y(n2194) );
NOR2BX4TS U1689 ( .AN(n2193), .B(n1049), .Y(n1048) );
NAND2X8TS U1690 ( .A(n1052), .B(n1050), .Y(n2218) );
NOR2X8TS U1691 ( .A(n1051), .B(n1278), .Y(n1050) );
NAND2X8TS U1692 ( .A(n1877), .B(Shift_reg_FLAGS_7_6), .Y(n1073) );
NAND2X8TS U1693 ( .A(n1056), .B(n1053), .Y(n1877) );
AOI21X4TS U1694 ( .A0(n1055), .A1(n1876), .B0(n1054), .Y(n1053) );
OAI21X4TS U1695 ( .A0(n1875), .A1(n1874), .B0(n1873), .Y(n1054) );
OAI21X4TS U1696 ( .A0(n1857), .A1(n1856), .B0(n1855), .Y(n1055) );
NAND2X8TS U1697 ( .A(n1058), .B(n1057), .Y(n1056) );
NOR2X8TS U1698 ( .A(n1863), .B(n1059), .Y(n1865) );
NOR2X4TS U1699 ( .A(n2473), .B(n1299), .Y(n1059) );
AOI2BB2X4TS U1700 ( .B0(n1030), .B1(n1015), .A0N(n957), .A1N(n2489), .Y(
n2840) );
NAND2X8TS U1701 ( .A(n1444), .B(n1060), .Y(n1445) );
NOR2X8TS U1702 ( .A(Raw_mant_NRM_SWR[11]), .B(Raw_mant_NRM_SWR[13]), .Y(
n1912) );
BUFX6TS U1703 ( .A(n1905), .Y(n1061) );
NOR2X8TS U1704 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n1905)
);
AOI2BB2X4TS U1705 ( .B0(n1030), .B1(n1238), .A0N(n2229), .A1N(n2421), .Y(
n2801) );
NAND3X8TS U1706 ( .A(n2462), .B(n2737), .C(Raw_mant_NRM_SWR[8]), .Y(n1455)
);
NAND2X6TS U1707 ( .A(n1019), .B(n1299), .Y(n1888) );
NAND2X8TS U1708 ( .A(n974), .B(n2222), .Y(n1066) );
NAND2X2TS U1709 ( .A(n979), .B(n1469), .Y(n2242) );
INVX16TS U1710 ( .A(n1073), .Y(n2258) );
BUFX20TS U1711 ( .A(n1075), .Y(n1074) );
BUFX20TS U1712 ( .A(n2258), .Y(n1075) );
AOI21X4TS U1713 ( .A0(n1349), .A1(Raw_mant_NRM_SWR[6]), .B0(n1354), .Y(n2808) );
NOR2X8TS U1714 ( .A(n2736), .B(n986), .Y(n1129) );
AOI2BB2X4TS U1715 ( .B0(n1339), .B1(DmP_mant_SHT1_SW[17]), .A0N(n986), .A1N(
n2494), .Y(n2735) );
AOI22X4TS U1716 ( .A0(n2021), .A1(n834), .B0(n1120), .B1(n2322), .Y(n1079)
);
INVX12TS U1717 ( .A(n973), .Y(n2021) );
NAND3X8TS U1718 ( .A(n1430), .B(n1431), .C(n1432), .Y(n1518) );
BUFX20TS U1719 ( .A(n1774), .Y(n1082) );
NAND2X4TS U1720 ( .A(n1332), .B(n2322), .Y(n1084) );
AOI21X4TS U1721 ( .A0(n1557), .A1(n1281), .B0(n1088), .Y(n2882) );
NAND2X8TS U1722 ( .A(n1091), .B(n1090), .Y(n1558) );
AOI22X2TS U1723 ( .A0(n1082), .A1(n2187), .B0(n1332), .B1(n2184), .Y(n1095)
);
AOI22X4TS U1724 ( .A0(n2024), .A1(n1320), .B0(n984), .B1(n2022), .Y(n2025)
);
BUFX12TS U1725 ( .A(n1774), .Y(n1099) );
AOI21X4TS U1726 ( .A0(n1732), .A1(n1320), .B0(n1110), .Y(n2878) );
NAND3X8TS U1727 ( .A(n1587), .B(n1114), .C(n1113), .Y(n2856) );
NAND2X8TS U1728 ( .A(n1115), .B(n1580), .Y(n1588) );
AND2X8TS U1729 ( .A(n1116), .B(n1579), .Y(n1115) );
AOI22X4TS U1730 ( .A0(n1082), .A1(n2230), .B0(n1577), .B1(n2322), .Y(n1116)
);
AND2X8TS U1731 ( .A(n2851), .B(n2589), .Y(n1582) );
NOR2X8TS U1732 ( .A(n1559), .B(n1931), .Y(n1935) );
AOI21X4TS U1733 ( .A0(n1547), .A1(n1319), .B0(n1117), .Y(n1122) );
OAI22X4TS U1734 ( .A0(n1493), .A1(n1319), .B0(n2197), .B1(n1118), .Y(n1117)
);
NAND3X8TS U1735 ( .A(n1119), .B(n1365), .C(n1366), .Y(n1547) );
NAND2X8TS U1736 ( .A(n1099), .B(n2260), .Y(n1119) );
INVX12TS U1737 ( .A(n973), .Y(n1333) );
NOR2X8TS U1738 ( .A(intDX_EWSW[15]), .B(n1259), .Y(n1822) );
INVX12TS U1739 ( .A(n1773), .Y(n1494) );
NOR2X8TS U1740 ( .A(n1542), .B(n2386), .Y(n1773) );
NAND2X8TS U1741 ( .A(n2851), .B(shift_value_SHT2_EWR_2_), .Y(n1542) );
AOI2BB2X4TS U1742 ( .B0(n1989), .B1(n834), .A0N(n973), .A1N(n985), .Y(n1126)
);
NAND2X6TS U1743 ( .A(n1517), .B(n1319), .Y(n1128) );
NAND4X8TS U1744 ( .A(n1395), .B(n1398), .C(n1397), .D(n1132), .Y(n1131) );
XOR2X4TS U1745 ( .A(n1133), .B(n968), .Y(n1631) );
XOR2X4TS U1746 ( .A(DmP_mant_SFG_SWR[16]), .B(n1530), .Y(n1524) );
NAND2X8TS U1747 ( .A(n2286), .B(n1136), .Y(n2913) );
NAND3X8TS U1748 ( .A(n1137), .B(n1200), .C(n982), .Y(n1458) );
NAND2X6TS U1749 ( .A(n1138), .B(n2571), .Y(n1423) );
OAI22X2TS U1750 ( .A0(n1147), .A1(n2686), .B0(n1145), .B1(n2685), .Y(
final_result_ieee[0]) );
OAI22X2TS U1751 ( .A0(n1148), .A1(n2692), .B0(n1145), .B1(n2691), .Y(
final_result_ieee[3]) );
OAI22X2TS U1752 ( .A0(n1148), .A1(n2726), .B0(n1145), .B1(n2725), .Y(
final_result_ieee[4]) );
OAI22X2TS U1753 ( .A0(n1148), .A1(n2732), .B0(n1145), .B1(n2731), .Y(
final_result_ieee[1]) );
OAI22X2TS U1754 ( .A0(n1149), .A1(n2720), .B0(n1145), .B1(n2719), .Y(
final_result_ieee[2]) );
MXI2X2TS U1755 ( .A(n2332), .B(n2424), .S0(n983), .Y(n561) );
MXI2X2TS U1756 ( .A(n1153), .B(n2462), .S0(n1331), .Y(n574) );
AND2X4TS U1757 ( .A(n1905), .B(n2734), .Y(n1184) );
NOR2X4TS U1758 ( .A(n1905), .B(n1238), .Y(n2240) );
AND2X4TS U1759 ( .A(n1447), .B(n1061), .Y(n1469) );
AOI2BB2X2TS U1760 ( .B0(n1282), .B1(Raw_mant_NRM_SWR[8]), .A0N(n1318), .A1N(
n2492), .Y(n2814) );
XOR2X4TS U1761 ( .A(n1926), .B(n1925), .Y(n1153) );
NAND2X4TS U1762 ( .A(n1772), .B(n2230), .Y(n1428) );
INVX2TS U1763 ( .A(n2230), .Y(n1154) );
NAND4BX4TS U1764 ( .AN(n2696), .B(n2695), .C(n2694), .D(n2693), .Y(n2230) );
NAND2X2TS U1765 ( .A(n1360), .B(intDX_EWSW[7]), .Y(n2037) );
NAND2X2TS U1766 ( .A(n954), .B(intDY_EWSW[5]), .Y(n2121) );
NAND2X2TS U1767 ( .A(n1195), .B(intDY_EWSW[19]), .Y(n2019) );
NAND2X2TS U1768 ( .A(n1019), .B(intDY_EWSW[25]), .Y(n1940) );
NAND2X2TS U1769 ( .A(n1019), .B(intDX_EWSW[0]), .Y(n2061) );
NAND2X2TS U1770 ( .A(n954), .B(intDY_EWSW[22]), .Y(n1997) );
NAND2X2TS U1771 ( .A(n1401), .B(intDY_EWSW[16]), .Y(n2000) );
NAND2X2TS U1772 ( .A(n1019), .B(intDY_EWSW[11]), .Y(n2114) );
NAND2X2TS U1773 ( .A(n2128), .B(n926), .Y(n2046) );
NAND2X2TS U1774 ( .A(n954), .B(n940), .Y(n2111) );
NAND2X4TS U1775 ( .A(n2128), .B(intDY_EWSW[17]), .Y(n2006) );
NAND2X2TS U1776 ( .A(n1019), .B(intDY_EWSW[30]), .Y(n1897) );
NAND2X4TS U1777 ( .A(n1019), .B(intDY_EWSW[29]), .Y(n1902) );
NAND2X2TS U1778 ( .A(n1360), .B(n1249), .Y(n2123) );
NAND2X2TS U1779 ( .A(n2128), .B(intDX_EWSW[12]), .Y(n2098) );
OA22X4TS U1780 ( .A0(n1316), .A1(n2738), .B0(n953), .B1(n2199), .Y(n2483) );
NAND2X2TS U1781 ( .A(n1082), .B(n1927), .Y(n1775) );
NOR2X8TS U1782 ( .A(n2466), .B(intDX_EWSW[9]), .Y(n1810) );
NOR2X8TS U1783 ( .A(n1625), .B(DMP_SFG[21]), .Y(n1678) );
INVX16TS U1784 ( .A(n1373), .Y(n2252) );
CLKINVX6TS U1785 ( .A(n2159), .Y(n2387) );
BUFX16TS U1786 ( .A(n2159), .Y(n1334) );
NOR2X8TS U1787 ( .A(n1851), .B(n1832), .Y(n1853) );
NAND2X2TS U1788 ( .A(n1082), .B(n2175), .Y(n1539) );
AND2X8TS U1789 ( .A(n1610), .B(n1609), .Y(n2904) );
NAND3X6TS U1790 ( .A(n1885), .B(n1886), .C(n1884), .Y(n615) );
MXI2X1TS U1791 ( .A(n2371), .B(final_result_ieee[26]), .S0(n2779), .Y(n2915)
);
NAND3X4TS U1792 ( .A(n1888), .B(n1889), .C(n1887), .Y(n612) );
NAND4X4TS U1793 ( .A(n1200), .B(n1452), .C(n1184), .D(n1453), .Y(n1459) );
NAND2X2TS U1794 ( .A(n1019), .B(n951), .Y(n2103) );
NAND2X2TS U1795 ( .A(n1360), .B(n995), .Y(n2028) );
NAND2X6TS U1796 ( .A(n1830), .B(n1829), .Y(n1394) );
CLKINVX6TS U1797 ( .A(n2371), .Y(n1706) );
NAND2X4TS U1798 ( .A(n1099), .B(n836), .Y(n1550) );
NAND2X4TS U1799 ( .A(n1577), .B(n836), .Y(n1365) );
NAND3X8TS U1800 ( .A(n2666), .B(n1492), .C(n2665), .Y(n836) );
OAI22X2TS U1801 ( .A0(n953), .A1(n2460), .B0(n2202), .B1(n2159), .Y(n2795)
);
NOR2X4TS U1802 ( .A(n1231), .B(Raw_mant_NRM_SWR[24]), .Y(n1463) );
NAND2X4TS U1803 ( .A(n2459), .B(n1460), .Y(n1437) );
INVX6TS U1804 ( .A(n1914), .Y(n1911) );
INVX16TS U1805 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2393) );
NAND2X8TS U1806 ( .A(n1601), .B(n2159), .Y(n1385) );
INVX12TS U1807 ( .A(n1685), .Y(n2227) );
NOR2X4TS U1808 ( .A(n1230), .B(n1196), .Y(n1441) );
NOR3X6TS U1809 ( .A(n2589), .B(n2386), .C(n2851), .Y(n1424) );
CLKINVX6TS U1810 ( .A(n982), .Y(n1439) );
NAND2X2TS U1811 ( .A(n1566), .B(n2175), .Y(n1561) );
AND2X4TS U1812 ( .A(n1186), .B(Raw_mant_NRM_SWR[16]), .Y(n1462) );
NAND2BX2TS U1813 ( .AN(n1743), .B(n1740), .Y(n1391) );
NAND2X4TS U1814 ( .A(n1485), .B(n1483), .Y(n1443) );
NOR2X4TS U1815 ( .A(n1965), .B(n2422), .Y(n1971) );
NAND2X2TS U1816 ( .A(n1098), .B(n2184), .Y(n1776) );
NOR2X2TS U1817 ( .A(n2261), .B(intDX_EWSW[31]), .Y(n1596) );
INVX2TS U1818 ( .A(n1217), .Y(n1218) );
NAND2X4TS U1819 ( .A(n2244), .B(n1909), .Y(n1388) );
OAI22X2TS U1820 ( .A0(n1046), .A1(n1355), .B0(n1334), .B1(n2176), .Y(n1354)
);
NAND2X1TS U1821 ( .A(n2212), .B(DmP_mant_SHT1_SW[14]), .Y(n1355) );
NAND2X4TS U1822 ( .A(n1252), .B(intDX_EWSW[14]), .Y(n1821) );
NAND2X4TS U1823 ( .A(n1250), .B(intDX_EWSW[12]), .Y(n1818) );
NAND2X2TS U1824 ( .A(n2468), .B(n1300), .Y(n1849) );
NOR2X4TS U1825 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2530), .Y(n2390) );
INVX6TS U1826 ( .A(n1547), .Y(n1368) );
NAND2X2TS U1827 ( .A(n1577), .B(n2170), .Y(n1538) );
CLKBUFX3TS U1828 ( .A(n2751), .Y(n2259) );
NAND2X4TS U1829 ( .A(n1401), .B(intDY_EWSW[18]), .Y(n2015) );
NAND2X1TS U1830 ( .A(n2526), .B(n1176), .Y(n2018) );
OAI21X2TS U1831 ( .A0(n1536), .A1(n983), .B0(n1535), .Y(n588) );
NAND2X1TS U1832 ( .A(n2109), .B(n1214), .Y(n1881) );
NAND2X4TS U1833 ( .A(n1360), .B(intDY_EWSW[21]), .Y(n1995) );
NAND2X2TS U1834 ( .A(n2130), .B(DMP_EXP_EWSW[2]), .Y(n2116) );
NAND2X1TS U1835 ( .A(n2109), .B(n1217), .Y(n1878) );
NAND2X1TS U1836 ( .A(n1629), .B(n1230), .Y(n1683) );
NAND2X2TS U1837 ( .A(n2138), .B(DmP_EXP_EWSW[13]), .Y(n2090) );
NAND2X2TS U1838 ( .A(n2130), .B(DMP_EXP_EWSW[0]), .Y(n2099) );
OAI22X2TS U1839 ( .A0(n2262), .A1(n1675), .B0(Shift_reg_FLAGS_7_6), .B1(
n1674), .Y(n772) );
OR2X4TS U1840 ( .A(n1377), .B(n2490), .Y(n2782) );
CLKINVX3TS U1841 ( .A(n1303), .Y(n1325) );
AOI2BB2X2TS U1842 ( .B0(n2170), .B1(n2745), .A0N(n1377), .A1N(n2497), .Y(
n2825) );
AOI2BB2X2TS U1843 ( .B0(n2169), .B1(n2745), .A0N(n1377), .A1N(n2498), .Y(
n2833) );
BUFX3TS U1844 ( .A(n2758), .Y(n2752) );
NAND2X2TS U1845 ( .A(n1282), .B(Raw_mant_NRM_SWR[0]), .Y(n2866) );
CLKINVX3TS U1846 ( .A(n1303), .Y(n1324) );
INVX2TS U1847 ( .A(rst), .Y(n1322) );
AOI2BB2X2TS U1848 ( .B0(n1282), .B1(n997), .A0N(n2228), .A1N(n1318), .Y(
n2859) );
NAND2X4TS U1849 ( .A(n1339), .B(DmP_mant_SHT1_SW[13]), .Y(n1378) );
MXI2X2TS U1850 ( .A(n1731), .B(n931), .S0(n983), .Y(n554) );
NAND2X2TS U1851 ( .A(n2109), .B(DmP_EXP_EWSW[26]), .Y(n1887) );
NAND2X2TS U1852 ( .A(n2109), .B(DmP_EXP_EWSW[23]), .Y(n1884) );
CLKBUFX3TS U1853 ( .A(n2259), .Y(n2753) );
INVX3TS U1854 ( .A(n1308), .Y(n1326) );
BUFX3TS U1855 ( .A(n2259), .Y(n2756) );
CLKINVX3TS U1856 ( .A(n1303), .Y(n1314) );
CLKINVX3TS U1857 ( .A(rst), .Y(n1313) );
INVX3TS U1858 ( .A(n1308), .Y(n1323) );
INVX2TS U1859 ( .A(rst), .Y(n1327) );
CLKINVX3TS U1860 ( .A(n1308), .Y(n1309) );
CLKINVX3TS U1861 ( .A(rst), .Y(n1321) );
CLKINVX3TS U1862 ( .A(rst), .Y(n1315) );
CLKBUFX3TS U1863 ( .A(n2259), .Y(n2563) );
NAND2X2TS U1864 ( .A(n2145), .B(n1180), .Y(n1938) );
CLKINVX3TS U1865 ( .A(n1308), .Y(n1312) );
NAND2X2TS U1866 ( .A(n2526), .B(n956), .Y(n2005) );
CLKINVX3TS U1867 ( .A(rst), .Y(n1337) );
CLKBUFX3TS U1868 ( .A(n2259), .Y(n2754) );
MXI2X1TS U1869 ( .A(n2165), .B(shift_value_SHT2_EWR_2_), .S0(n2387), .Y(
n2166) );
NAND2BX2TS U1870 ( .AN(n1578), .B(n2163), .Y(n1579) );
NAND2X6TS U1871 ( .A(n1466), .B(n1243), .Y(n1467) );
INVX8TS U1872 ( .A(n2308), .Y(n1749) );
NAND2X4TS U1873 ( .A(n941), .B(intDX_EWSW[1]), .Y(n2068) );
NAND2X4TS U1874 ( .A(n1195), .B(n999), .Y(n2092) );
AND2X8TS U1875 ( .A(n1193), .B(n1194), .Y(n1784) );
BUFX20TS U1876 ( .A(n1063), .Y(n1195) );
AOI21X4TS U1877 ( .A0(n1352), .A1(n1238), .B0(n1765), .Y(n2208) );
NAND2X6TS U1878 ( .A(n1524), .B(DMP_SFG[14]), .Y(n2297) );
AOI2BB2X4TS U1879 ( .B0(n1465), .B1(n1464), .A0N(n1205), .A1N(n1206), .Y(
n1466) );
OR4X4TS U1880 ( .A(n2199), .B(n2346), .C(n2461), .D(n1201), .Y(n1205) );
AOI22X4TS U1881 ( .A0(n1599), .A1(n1320), .B0(n2163), .B1(n1333), .Y(n1600)
);
NAND3X4TS U1882 ( .A(n1395), .B(n1398), .C(n1397), .Y(n1209) );
NAND4X4TS U1883 ( .A(n1485), .B(n1484), .C(n2383), .D(n1483), .Y(n1488) );
NAND3X2TS U1884 ( .A(n1882), .B(n1883), .C(n1881), .Y(n614) );
NAND3X4TS U1885 ( .A(n2118), .B(n2117), .C(n2116), .Y(n802) );
NAND3X2TS U1886 ( .A(n1879), .B(n1880), .C(n1878), .Y(n613) );
OA21X4TS U1887 ( .A0(n1695), .A1(n1693), .B0(n1694), .Y(n1222) );
NAND3X2TS U1888 ( .A(n2055), .B(n2054), .C(n2053), .Y(n625) );
NAND3X2TS U1889 ( .A(n2107), .B(n2108), .C(n2106), .Y(n798) );
NAND3X4TS U1890 ( .A(n2126), .B(n2127), .C(n2125), .Y(n796) );
NAND2X4TS U1891 ( .A(n1360), .B(n1301), .Y(n2080) );
NAND3X2TS U1892 ( .A(n2086), .B(n2085), .C(n2084), .Y(n627) );
NAND3X2TS U1893 ( .A(n2028), .B(n2027), .C(n2026), .Y(n641) );
NAND2X2TS U1894 ( .A(n2129), .B(n1240), .Y(n2067) );
NAND2X2TS U1895 ( .A(n2129), .B(n1260), .Y(n2070) );
NAND2X2TS U1896 ( .A(n2129), .B(intDY_EWSW[26]), .Y(n1889) );
NAND2X2TS U1897 ( .A(n1402), .B(intDY_EWSW[24]), .Y(n1883) );
NAND2X2TS U1898 ( .A(n2017), .B(intDX_EWSW[14]), .Y(n2010) );
NAND2X2TS U1899 ( .A(n1402), .B(intDY_EWSW[0]), .Y(n2060) );
NAND2X2TS U1900 ( .A(n1361), .B(n1262), .Y(n2048) );
NAND2X2TS U1901 ( .A(n1364), .B(n1004), .Y(n2120) );
NAND2X2TS U1902 ( .A(n2129), .B(n1300), .Y(n1946) );
NAND2X2TS U1903 ( .A(n1361), .B(intDX_EWSW[30]), .Y(n1896) );
NAND2X2TS U1904 ( .A(n1402), .B(intDX_EWSW[28]), .Y(n1899) );
NAND2X2TS U1905 ( .A(n1361), .B(intDX_EWSW[7]), .Y(n2112) );
NAND2X4TS U1906 ( .A(n1246), .B(n1075), .Y(n2147) );
NAND2X2TS U1907 ( .A(n1364), .B(n1244), .Y(n1939) );
NAND2X2TS U1908 ( .A(n1402), .B(intDY_EWSW[25]), .Y(n1880) );
NAND2X2TS U1909 ( .A(n1361), .B(n1003), .Y(n2115) );
NAND2X2TS U1910 ( .A(n1074), .B(intDX_EWSW[12]), .Y(n2124) );
NAND2X2TS U1911 ( .A(n1364), .B(intDY_EWSW[19]), .Y(n2094) );
NAND2X2TS U1912 ( .A(n1361), .B(n1301), .Y(n1998) );
NAND2X2TS U1913 ( .A(n2129), .B(n999), .Y(n2143) );
NAND2X2TS U1914 ( .A(n1074), .B(intDX_EWSW[16]), .Y(n2001) );
NAND2X2TS U1915 ( .A(n945), .B(intDX_EWSW[19]), .Y(n2020) );
NAND2X2TS U1916 ( .A(n2129), .B(intDX_EWSW[21]), .Y(n1994) );
NAND2X2TS U1917 ( .A(intDX_EWSW[6]), .B(n1364), .Y(n2108) );
NAND2X2TS U1918 ( .A(n2017), .B(n951), .Y(n2027) );
NAND2X2TS U1919 ( .A(n1268), .B(n1694), .Y(n1696) );
NAND2X4TS U1920 ( .A(n2211), .B(n1201), .Y(n2214) );
AOI21X1TS U1921 ( .A0(n1521), .A1(n1406), .B0(n1520), .Y(n2336) );
AND2X8TS U1922 ( .A(intDY_EWSW[19]), .B(n1236), .Y(n1844) );
NAND2X8TS U1923 ( .A(n1474), .B(n2383), .Y(n1478) );
NAND2X4TS U1924 ( .A(n1412), .B(n1460), .Y(n1383) );
NOR2X4TS U1925 ( .A(n1230), .B(Raw_mant_NRM_SWR[24]), .Y(n1915) );
INVX6TS U1926 ( .A(n1269), .Y(n1794) );
NAND3X2TS U1927 ( .A(n2031), .B(n2030), .C(n2029), .Y(n643) );
INVX3TS U1928 ( .A(n1470), .Y(n1471) );
NAND3X6TS U1929 ( .A(n1470), .B(n2242), .C(n1918), .Y(n2278) );
OR4X4TS U1930 ( .A(n2346), .B(n1239), .C(Raw_mant_NRM_SWR[12]), .D(n1201),
.Y(n1245) );
NAND2X4TS U1931 ( .A(n2481), .B(intDX_EWSW[16]), .Y(n1841) );
AND2X8TS U1932 ( .A(n1240), .B(n1253), .Y(n1783) );
OA22X4TS U1933 ( .A0(n2198), .A1(n2494), .B0(n1318), .B1(n2426), .Y(n2848)
);
NOR2X4TS U1934 ( .A(n2468), .B(n1300), .Y(n1851) );
NAND2X4TS U1935 ( .A(n1241), .B(intDX_EWSW[1]), .Y(n1781) );
NOR2X6TS U1936 ( .A(intDY_EWSW[5]), .B(n1270), .Y(n1269) );
CLKXOR2X2TS U1937 ( .A(n2776), .B(DmP_mant_SFG_SWR[10]), .Y(n1726) );
CLKBUFX3TS U1938 ( .A(n2758), .Y(n2570) );
INVX2TS U1939 ( .A(n1743), .Y(n1393) );
AND4X8TS U1940 ( .A(n2152), .B(n1387), .C(n1918), .D(n1917), .Y(n1273) );
AND2X4TS U1941 ( .A(n1741), .B(n1393), .Y(n1274) );
OR2X4TS U1942 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[3]), .Y(n1276)
);
INVX8TS U1943 ( .A(n1629), .Y(n2331) );
INVX12TS U1944 ( .A(n2393), .Y(n2345) );
INVX2TS U1945 ( .A(n1576), .Y(n2733) );
CLKBUFX2TS U1946 ( .A(n2259), .Y(n2747) );
CLKBUFX3TS U1947 ( .A(n1335), .Y(n2775) );
CLKBUFX3TS U1948 ( .A(n1338), .Y(n2749) );
BUFX3TS U1949 ( .A(n2760), .Y(n2763) );
CLKINVX3TS U1950 ( .A(n1308), .Y(n1310) );
INVX2TS U1951 ( .A(n1327), .Y(n1303) );
INVX2TS U1952 ( .A(n2751), .Y(n1308) );
INVX2TS U1953 ( .A(n1303), .Y(n1305) );
INVX2TS U1954 ( .A(n1303), .Y(n1304) );
CLKBUFX2TS U1955 ( .A(n2749), .Y(n2751) );
INVX16TS U1956 ( .A(n2198), .Y(n1282) );
NAND2X1TS U1957 ( .A(n1734), .B(n1277), .Y(n1283) );
NAND2X1TS U1958 ( .A(n1285), .B(n975), .Y(n1284) );
OAI22X4TS U1959 ( .A0(n1810), .A1(n1286), .B0(intDY_EWSW[9]), .B1(n1271),
.Y(n1816) );
NOR2X8TS U1960 ( .A(n1468), .B(n1467), .Y(n1287) );
NOR2X8TS U1961 ( .A(n2480), .B(intDX_EWSW[18]), .Y(n1288) );
OAI22X4TS U1962 ( .A0(n1848), .A1(n1289), .B0(intDY_EWSW[21]), .B1(n1272),
.Y(n1854) );
NOR2X8TS U1963 ( .A(n2469), .B(intDX_EWSW[21]), .Y(n1848) );
OAI2BB1X4TS U1964 ( .A0N(n2393), .A1N(LZD_output_NRM2_EW[2]), .B0(n2167),
.Y(n576) );
NOR2X8TS U1965 ( .A(n1450), .B(n1449), .Y(n1452) );
OAI22X4TS U1966 ( .A0(n1158), .A1(n1157), .B0(n1156), .B1(n1155), .Y(n2834)
);
OAI2BB1X4TS U1967 ( .A0N(DMP_SFG[8]), .A1N(n1292), .B0(n1291), .Y(n1730) );
OAI21X4TS U1968 ( .A0(n1292), .A1(DMP_SFG[8]), .B0(n1726), .Y(n1291) );
NAND2X8TS U1969 ( .A(n1294), .B(n1293), .Y(n1292) );
OR2X8TS U1970 ( .A(n1504), .B(n1921), .Y(n1294) );
NAND4X8TS U1971 ( .A(n1720), .B(n1719), .C(n1721), .D(n975), .Y(n2924) );
XOR2X4TS U1972 ( .A(DmP_mant_SFG_SWR[9]), .B(n1008), .Y(n1924) );
NAND2X4TS U1973 ( .A(DP_OP_301J12_122_1182_n171), .B(DMP_SFG[10]), .Y(n2271)
);
NAND2X4TS U1974 ( .A(n1261), .B(intDX_EWSW[2]), .Y(n1786) );
NAND2X6TS U1975 ( .A(n1263), .B(intDX_EWSW[4]), .Y(n1795) );
BUFX20TS U1976 ( .A(n1371), .Y(n1352) );
BUFX20TS U1977 ( .A(n2258), .Y(n2017) );
OA21X4TS U1978 ( .A0(n2587), .A1(n1297), .B0(n1298), .Y(n1302) );
NAND2X4TS U1979 ( .A(n941), .B(n1240), .Y(n1404) );
NAND2X2TS U1980 ( .A(n954), .B(intDY_EWSW[26]), .Y(n1943) );
NOR2X8TS U1981 ( .A(n1252), .B(intDX_EWSW[14]), .Y(n1807) );
BUFX20TS U1982 ( .A(n2258), .Y(n2129) );
INVX12TS U1983 ( .A(n1421), .Y(n2851) );
MXI2X4TS U1984 ( .A(n2887), .B(n2543), .S0(n962), .Y(n551) );
AOI22X2TS U1985 ( .A0(n1989), .A1(n2200), .B0(n2021), .B1(n2184), .Y(n1369)
);
OAI21X2TS U1986 ( .A0(n2384), .A1(n1281), .B0(n2203), .Y(n880) );
BUFX3TS U1987 ( .A(n2749), .Y(n2757) );
CLKINVX3TS U1988 ( .A(rst), .Y(n1336) );
CLKBUFX2TS U1989 ( .A(n2756), .Y(n2761) );
BUFX20TS U1990 ( .A(n1063), .Y(n1401) );
MXI2X4TS U1991 ( .A(n2874), .B(n2501), .S0(n1329), .Y(n566) );
CLKINVX3TS U1992 ( .A(rst), .Y(n1311) );
INVX16TS U1993 ( .A(n972), .Y(n1316) );
OAI22X2TS U1994 ( .A0(n1377), .A1(n2228), .B0(n1316), .B1(n2490), .Y(n2822)
);
MXI2X2TS U1995 ( .A(n2484), .B(n1961), .S0(n1317), .Y(n568) );
AOI2BB2X2TS U1996 ( .B0(n1282), .B1(Raw_mant_NRM_SWR[7]), .A0N(n1318), .A1N(
n2498), .Y(n2809) );
AOI2BB2X2TS U1997 ( .B0(n1282), .B1(Raw_mant_NRM_SWR[21]), .A0N(n2229),
.A1N(n2491), .Y(n2837) );
AOI2BB2X2TS U1998 ( .B0(n1282), .B1(n1185), .A0N(n2229), .A1N(n2497), .Y(
n2791) );
CLKBUFX3TS U1999 ( .A(n2259), .Y(n2755) );
NAND2X2TS U2000 ( .A(n960), .B(DmP_mant_SFG_SWR[18]), .Y(n1343) );
MXI2X2TS U2001 ( .A(n2277), .B(n1413), .S0(n1331), .Y(n580) );
MXI2X2TS U2002 ( .A(n1506), .B(n1239), .S0(n1331), .Y(n550) );
MXI2X2TS U2003 ( .A(n1502), .B(n2460), .S0(n983), .Y(n565) );
MXI2X4TS U2004 ( .A(n1969), .B(n2458), .S0(n1331), .Y(n558) );
NAND2X2TS U2005 ( .A(n1772), .B(n834), .Y(n1540) );
OAI22X2TS U2006 ( .A0(n1024), .A1(n2231), .B0(n1334), .B1(n1154), .Y(n2232)
);
MXI2X2TS U2007 ( .A(n2370), .B(n2487), .S0(n2351), .Y(n815) );
NOR2XLTS U2008 ( .A(n2487), .B(n2383), .Y(n2165) );
MXI2X2TS U2009 ( .A(n1725), .B(n2485), .S0(n2351), .Y(n813) );
CLKINVX3TS U2010 ( .A(rst), .Y(n1335) );
CLKINVX3TS U2011 ( .A(rst), .Y(n1338) );
NAND2X2TS U2012 ( .A(n2130), .B(n1213), .Y(n2063) );
NAND2X2TS U2013 ( .A(n2138), .B(DmP_EXP_EWSW[15]), .Y(n2075) );
NAND2X8TS U2014 ( .A(n1341), .B(n1340), .Y(n1380) );
OAI21X4TS U2015 ( .A0(n2902), .A1(n1329), .B0(n1343), .Y(n521) );
OAI21X4TS U2016 ( .A0(n1768), .A1(n980), .B0(n1344), .Y(n515) );
BUFX20TS U2017 ( .A(n2598), .Y(n2273) );
NOR2X8TS U2018 ( .A(n1257), .B(intDX_EWSW[13]), .Y(n1819) );
MXI2X4TS U2019 ( .A(n2025), .B(n2534), .S0(n963), .Y(n578) );
XOR2X4TS U2020 ( .A(n549), .B(n1576), .Y(n2620) );
INVX16TS U2021 ( .A(n1494), .Y(n1577) );
NOR2X4TS U2022 ( .A(n1250), .B(intDX_EWSW[12]), .Y(n1806) );
OR2X8TS U2023 ( .A(n1346), .B(n2203), .Y(n1477) );
NOR2X8TS U2024 ( .A(n1255), .B(intDX_EWSW[6]), .Y(n1791) );
AOI21X4TS U2025 ( .A0(n1872), .A1(n1871), .B0(n1870), .Y(n1873) );
NOR2X8TS U2026 ( .A(n2851), .B(shift_value_SHT2_EWR_2_), .Y(n1571) );
NAND4BX4TS U2027 ( .AN(n2250), .B(n2249), .C(n2248), .D(n2247), .Y(n2251) );
NAND2X6TS U2028 ( .A(n978), .B(n1185), .Y(n2178) );
NAND2X4TS U2029 ( .A(intDY_EWSW[28]), .B(n1195), .Y(n1900) );
NOR2X8TS U2030 ( .A(n1477), .B(n927), .Y(n2281) );
NAND2X6TS U2031 ( .A(n1439), .B(n1441), .Y(n1485) );
NOR2X8TS U2032 ( .A(n1750), .B(n1753), .Y(n1741) );
NAND2X6TS U2033 ( .A(n1627), .B(n1741), .Y(n1616) );
BUFX20TS U2034 ( .A(n2233), .Y(n1349) );
OAI21X4TS U2035 ( .A0(n1908), .A1(n1276), .B0(n1350), .Y(n1453) );
AOI21X4TS U2036 ( .A0(n2460), .A1(Raw_mant_NRM_SWR[4]), .B0(
Raw_mant_NRM_SWR[6]), .Y(n1350) );
NOR2X8TS U2037 ( .A(n1351), .B(Raw_mant_NRM_SWR[2]), .Y(n1908) );
AND2X8TS U2038 ( .A(n1907), .B(n2484), .Y(n2244) );
NOR2X8TS U2039 ( .A(n1384), .B(n1385), .Y(n1376) );
BUFX20TS U2040 ( .A(n1063), .Y(n1360) );
AOI21X4TS U2041 ( .A0(n1349), .A1(Raw_mant_NRM_SWR[1]), .B0(n2232), .Y(n2820) );
NOR2X4TS U2042 ( .A(n1400), .B(n1362), .Y(n1399) );
NAND2X4TS U2043 ( .A(n1944), .B(n1363), .Y(n780) );
AOI21X4TS U2044 ( .A0(n945), .A1(intDX_EWSW[24]), .B0(n1280), .Y(n1363) );
OAI21X4TS U2045 ( .A0(n1548), .A1(n1281), .B0(n1367), .Y(n1370) );
NAND2X8TS U2046 ( .A(n1368), .B(n1281), .Y(n1367) );
AND2X8TS U2047 ( .A(n1370), .B(n1369), .Y(n2887) );
AOI21X4TS U2048 ( .A0(n1372), .A1(Raw_mant_NRM_SWR[11]), .B0(n2746), .Y(
n1480) );
NOR2X8TS U2049 ( .A(n1380), .B(n1379), .Y(n1381) );
NAND2X8TS U2050 ( .A(n1434), .B(n1446), .Y(n1461) );
NOR2X8TS U2051 ( .A(Raw_mant_NRM_SWR[7]), .B(Raw_mant_NRM_SWR[6]), .Y(n1473)
);
AOI2BB2X2TS U2052 ( .B0(n1282), .B1(n2746), .A0N(n2229), .A1N(n2493), .Y(
n2798) );
INVX2TS U2053 ( .A(n1387), .Y(n2246) );
NAND2X4TS U2054 ( .A(n2280), .B(Raw_mant_NRM_SWR[12]), .Y(n2156) );
OAI21X4TS U2055 ( .A0(n1749), .A1(n1392), .B0(n1389), .Y(n1682) );
NAND2X8TS U2056 ( .A(n2308), .B(n1396), .Y(n1395) );
NOR2X8TS U2057 ( .A(n1616), .B(n1676), .Y(n1396) );
AOI21X4TS U2058 ( .A0(n1740), .A1(n1627), .B0(n1626), .Y(n1397) );
NAND3X6TS U2059 ( .A(n2013), .B(n2012), .C(n2011), .Y(n789) );
NAND3X6TS U2060 ( .A(n2003), .B(n2004), .C(n2002), .Y(n784) );
XNOR2X4TS U2061 ( .A(n1192), .B(n2288), .Y(n2289) );
AOI21X4TS U2062 ( .A0(n1192), .A1(n2299), .B0(n2298), .Y(n2304) );
NAND2X4TS U2063 ( .A(n1606), .B(n1319), .Y(n1610) );
OAI2BB1X4TS U2064 ( .A0N(n1582), .A1N(n2175), .B0(n1581), .Y(n1586) );
NAND2X2TS U2065 ( .A(n1582), .B(n2230), .Y(n1543) );
NAND2X4TS U2066 ( .A(n1582), .B(n2386), .Y(n1578) );
NAND2X4TS U2067 ( .A(n1611), .B(left_right_SHT2), .Y(n1575) );
NAND2X4TS U2068 ( .A(n1577), .B(n2175), .Y(n1431) );
AND2X8TS U2069 ( .A(n1546), .B(n1545), .Y(n2908) );
NAND2X4TS U2070 ( .A(n1890), .B(n1931), .Y(n1546) );
NAND3X6TS U2071 ( .A(n2206), .B(n2205), .C(n2204), .Y(n2207) );
AOI21X4TS U2072 ( .A0(n2308), .A1(n2291), .B0(n1677), .Y(n2295) );
NAND4BX4TS U2073 ( .AN(n2607), .B(n2606), .C(n2605), .D(n2604), .Y(n2170) );
NAND2X4TS U2074 ( .A(n1763), .B(n1762), .Y(n2225) );
NAND3X6TS U2075 ( .A(n1947), .B(n1946), .C(n1945), .Y(n781) );
NAND2X4TS U2076 ( .A(n1098), .B(n2187), .Y(n1493) );
OA22X4TS U2077 ( .A0(n1377), .A1(n2429), .B0(n2525), .B1(n1316), .Y(n2867)
);
OA22X4TS U2078 ( .A0(n1377), .A1(n2210), .B0(n2496), .B1(n1316), .Y(n2800)
);
OAI22X2TS U2079 ( .A0(n953), .A1(n1186), .B0(n2489), .B1(n1316), .Y(n2826)
);
NAND2X4TS U2080 ( .A(n1588), .B(n1319), .Y(n1585) );
OAI22X4TS U2081 ( .A0(n2268), .A1(n1920), .B0(n1919), .B1(n2425), .Y(n2328)
);
NAND2X6TS U2082 ( .A(n2264), .B(DMP_SFG[4]), .Y(n2268) );
NAND4X4TS U2083 ( .A(n1510), .B(n1509), .C(n1508), .D(n1507), .Y(n1606) );
OR2X4TS U2084 ( .A(n1429), .B(n1302), .Y(n1430) );
NAND2X4TS U2085 ( .A(n1890), .B(n1320), .Y(n1894) );
NAND2BX4TS U2086 ( .AN(n1471), .B(n1918), .Y(n1472) );
AOI2BB2X2TS U2087 ( .B0(n1171), .B1(n2225), .A0N(n2208), .A1N(n1024), .Y(
n2811) );
OA22X4TS U2088 ( .A0(n2229), .A1(n2488), .B0(n2208), .B1(n1046), .Y(n2845)
);
AND2X8TS U2089 ( .A(n1937), .B(n1936), .Y(n2895) );
AND2X8TS U2090 ( .A(n2252), .B(DmP_mant_SHT1_SW[18]), .Y(n2257) );
XNOR2X4TS U2091 ( .A(n1530), .B(DmP_mant_SFG_SWR[3]), .Y(n1959) );
NAND2X2TS U2092 ( .A(n1098), .B(n2169), .Y(n1769) );
AOI2BB2X2TS U2093 ( .B0(n2226), .B1(n2224), .A0N(n990), .A1N(n2740), .Y(
n2824) );
NAND4BX4TS U2094 ( .AN(n2636), .B(n2635), .C(n2634), .D(n2633), .Y(n2201) );
NAND3X6TS U2095 ( .A(n2215), .B(n2214), .C(n2213), .Y(n2216) );
NAND4X4TS U2096 ( .A(n1570), .B(n1569), .C(n1568), .D(n1567), .Y(n1611) );
NAND2X2TS U2097 ( .A(n1566), .B(n984), .Y(n1567) );
NAND3X6TS U2098 ( .A(n2007), .B(n2006), .C(n2005), .Y(n787) );
NOR2X2TS U2099 ( .A(n2320), .B(n2318), .Y(n1708) );
OAI22X2TS U2100 ( .A0(n2255), .A1(n2505), .B0(n2191), .B1(n2159), .Y(n2192)
);
AOI22X2TS U2101 ( .A0(n1989), .A1(n2170), .B0(n1892), .B1(n1766), .Y(n1612)
);
OAI22X2TS U2102 ( .A0(n2255), .A1(n2488), .B0(n2185), .B1(n1334), .Y(n2186)
);
NAND3X6TS U2103 ( .A(n2148), .B(n2147), .C(n2146), .Y(n777) );
NAND2X2TS U2104 ( .A(n1352), .B(n2746), .Y(n2196) );
XOR2X4TS U2105 ( .A(n2273), .B(DmP_mant_SFG_SWR[7]), .Y(n1977) );
NAND2X4TS U2106 ( .A(n1402), .B(intDY_EWSW[23]), .Y(n1886) );
NOR2X8TS U2107 ( .A(n1712), .B(n2285), .Y(n1720) );
XNOR2X4TS U2108 ( .A(n1711), .B(DMP_exp_NRM2_EW[7]), .Y(n2285) );
NAND2X2TS U2109 ( .A(n1361), .B(n1299), .Y(n1942) );
BUFX20TS U2110 ( .A(n1063), .Y(n2128) );
NOR2X8TS U2111 ( .A(n1266), .B(DMP_exp_NRM2_EW[0]), .Y(n1695) );
NAND2X4TS U2112 ( .A(n945), .B(intDX_EWSW[17]), .Y(n2007) );
NAND3X4TS U2113 ( .A(n1738), .B(n971), .C(n2404), .Y(n1739) );
NAND2X2TS U2114 ( .A(n937), .B(n2163), .Y(n1405) );
OR2X8TS U2115 ( .A(n1418), .B(DMP_SFG[12]), .Y(n1406) );
AND2X4TS U2116 ( .A(n2291), .B(n2293), .Y(n1407) );
AND2X4TS U2117 ( .A(n2291), .B(n1741), .Y(n1408) );
OA21X4TS U2118 ( .A0(n1618), .A1(n2309), .B0(n1617), .Y(n1411) );
AO21X4TS U2119 ( .A0(n1697), .A1(n1688), .B0(n1687), .Y(n1414) );
NAND2X4TS U2120 ( .A(n1440), .B(n2461), .Y(n1415) );
NOR2X4TS U2121 ( .A(n2465), .B(intDX_EWSW[28]), .Y(n1836) );
NAND2X2TS U2122 ( .A(n1625), .B(DMP_SFG[21]), .Y(n1679) );
NAND2X1TS U2123 ( .A(n1393), .B(n1744), .Y(n1745) );
XNOR2X2TS U2124 ( .A(n1266), .B(DMP_exp_NRM2_EW[0]), .Y(n2318) );
AOI22X2TS U2125 ( .A0(n1685), .A1(DmP_mant_SHT1_SW[9]), .B0(n2745), .B1(
n1934), .Y(n1490) );
INVX2TS U2126 ( .A(DmP_mant_SHT1_SW[19]), .Y(n2228) );
AOI22X1TS U2127 ( .A0(n2280), .A1(n2279), .B0(n1220), .B1(n2393), .Y(n2283)
);
OAI21X2TS U2128 ( .A0(n1684), .A1(n1629), .B0(n1683), .Y(n584) );
NOR2X4TS U2129 ( .A(DmP_mant_SFG_SWR_signed_13_), .B(DMP_SFG[11]), .Y(n1417)
);
NAND2X2TS U2130 ( .A(DmP_mant_SFG_SWR_signed_13_), .B(DMP_SFG[11]), .Y(n1416) );
OAI21X4TS U2131 ( .A0(n2271), .A1(n1417), .B0(n1416), .Y(n1521) );
XOR2X4TS U2132 ( .A(n2776), .B(DmP_mant_SFG_SWR[14]), .Y(n1418) );
NAND2X1TS U2133 ( .A(n1406), .B(n1519), .Y(n1419) );
XNOR2X1TS U2134 ( .A(n1521), .B(n1419), .Y(n1420) );
OAI21X4TS U2144 ( .A0(n2592), .A1(n2591), .B0(n2590), .Y(n1421) );
NAND2X8TS U2145 ( .A(n1571), .B(n1560), .Y(n1770) );
INVX16TS U2146 ( .A(n1770), .Y(n1772) );
NAND2X2TS U2147 ( .A(n1773), .B(n2253), .Y(n1427) );
OA21X4TS U2148 ( .A0(n1143), .A1(n2573), .B0(n2572), .Y(n1425) );
NAND2X4TS U2149 ( .A(n1772), .B(n2201), .Y(n1432) );
NAND4X4TS U2150 ( .A(n2647), .B(n2646), .C(n2645), .D(n2644), .Y(n2322) );
INVX12TS U2151 ( .A(n2925), .Y(n2341) );
INVX16TS U2152 ( .A(n2341), .Y(n2384) );
NOR2X8TS U2153 ( .A(n2383), .B(n2384), .Y(n1433) );
INVX16TS U2154 ( .A(n1435), .Y(n2346) );
NOR2X8TS U2155 ( .A(n2346), .B(Raw_mant_NRM_SWR[16]), .Y(n1436) );
NOR3X8TS U2156 ( .A(n1461), .B(n1438), .C(n1437), .Y(n1481) );
NOR2X4TS U2157 ( .A(n2346), .B(Raw_mant_NRM_SWR[24]), .Y(n1483) );
NOR2X6TS U2158 ( .A(n1185), .B(Raw_mant_NRM_SWR[16]), .Y(n1440) );
NOR2X4TS U2159 ( .A(Raw_mant_NRM_SWR[5]), .B(n1238), .Y(n1475) );
OR2X4TS U2160 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[12]), .Y(n1449) );
OR2X4TS U2161 ( .A(Raw_mant_NRM_SWR[13]), .B(n2746), .Y(n1910) );
AOI21X4TS U2162 ( .A0(n1455), .A1(n2736), .B0(n1910), .Y(n1456) );
NAND3X6TS U2163 ( .A(n1459), .B(n1458), .C(n1457), .Y(n1468) );
INVX2TS U2164 ( .A(n2746), .Y(n2199) );
NOR2X2TS U2165 ( .A(n1463), .B(n2346), .Y(n1464) );
INVX8TS U2166 ( .A(n2159), .Y(n2745) );
NOR2X2TS U2167 ( .A(n1472), .B(n1413), .Y(n1491) );
NAND2X2TS U2168 ( .A(n1905), .B(n1475), .Y(n1476) );
NOR2X4TS U2169 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2383), .Y(n1489) );
BUFX12TS U2170 ( .A(n1489), .Y(n2212) );
OAI2BB1X4TS U2171 ( .A0N(n1025), .A1N(n1491), .B0(n1490), .Y(n2818) );
AOI2BB2X2TS U2172 ( .B0(n2580), .B1(n1139), .A0N(n1143), .A1N(n2579), .Y(
n1492) );
NAND4BX4TS U2173 ( .AN(n2651), .B(n2650), .C(n2649), .D(n2648), .Y(n1927) );
INVX2TS U2174 ( .A(n1927), .Y(n2197) );
NAND4BX4TS U2175 ( .AN(n2834), .B(n2612), .C(n2611), .D(n2610), .Y(n2169) );
NAND4X4TS U2176 ( .A(n2603), .B(n2602), .C(n2601), .D(n2600), .Y(n2260) );
NAND3BX4TS U2177 ( .AN(n2639), .B(n2638), .C(n2637), .Y(n2200) );
NAND4BX4TS U2178 ( .AN(n2716), .B(n2715), .C(n2714), .D(n2713), .Y(n2184) );
XOR2X4TS U2179 ( .A(DmP_mant_SFG_SWR[2]), .B(n1949), .Y(n2238) );
NAND2X4TS U2180 ( .A(n1496), .B(n1495), .Y(n1966) );
XNOR2X4TS U2181 ( .A(n1949), .B(DmP_mant_SFG_SWR[4]), .Y(n1965) );
INVX2TS U2182 ( .A(n1971), .Y(n1499) );
INVX2TS U2183 ( .A(n1965), .Y(n1497) );
NOR2X2TS U2184 ( .A(n1497), .B(DMP_SFG[2]), .Y(n1498) );
AOI21X4TS U2185 ( .A0(n1966), .A1(n1499), .B0(n1498), .Y(n1501) );
XNOR2X4TS U2186 ( .A(n1949), .B(DmP_mant_SFG_SWR[5]), .Y(n1972) );
XOR2X1TS U2187 ( .A(n1972), .B(n2420), .Y(n1500) );
XNOR2X4TS U2188 ( .A(n1501), .B(n1500), .Y(n1502) );
XOR2X4TS U2189 ( .A(n2273), .B(DmP_mant_SFG_SWR[8]), .Y(n2327) );
NOR2X2TS U2190 ( .A(n1924), .B(DMP_SFG[7]), .Y(n1504) );
INVX2TS U2191 ( .A(n1924), .Y(n1503) );
XNOR2X1TS U2192 ( .A(n1726), .B(DMP_SFG[8]), .Y(n1505) );
NAND2X2TS U2193 ( .A(n1566), .B(n2260), .Y(n1509) );
NAND2X1TS U2194 ( .A(n1774), .B(n2169), .Y(n1508) );
NAND2X2TS U2195 ( .A(n1577), .B(n2200), .Y(n1507) );
NAND2X2TS U2196 ( .A(n1606), .B(n1320), .Y(n1515) );
NAND3X2TS U2197 ( .A(n2615), .B(n2614), .C(n2613), .Y(n2220) );
AOI22X1TS U2198 ( .A0(n1989), .A1(n2220), .B0(n1892), .B1(n1607), .Y(n1514)
);
INVX2TS U2199 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1516) );
NAND2X8TS U2200 ( .A(n1734), .B(Shift_reg_FLAGS_7[3]), .Y(n1952) );
MXI2X4TS U2201 ( .A(n2880), .B(n1516), .S0(n961), .Y(n557) );
XOR2X4TS U2202 ( .A(n2273), .B(DmP_mant_SFG_SWR[15]), .Y(n1522) );
NAND2X4TS U2203 ( .A(n1522), .B(DMP_SFG[13]), .Y(n2334) );
OA21X4TS U2204 ( .A0(n1235), .A1(n2333), .B0(n2334), .Y(n1523) );
NOR2X4TS U2205 ( .A(DMP_SFG[14]), .B(n1524), .Y(n2287) );
NOR2X8TS U2206 ( .A(n1525), .B(DMP_SFG[15]), .Y(n2300) );
NOR2X4TS U2207 ( .A(n2287), .B(n2300), .Y(n2307) );
XOR2X4TS U2208 ( .A(n1530), .B(DmP_mant_SFG_SWR[18]), .Y(n1526) );
NOR2X4TS U2209 ( .A(n1526), .B(DMP_SFG[16]), .Y(n1615) );
NAND2X1TS U2210 ( .A(n1204), .B(n2310), .Y(n1529) );
NAND2X4TS U2211 ( .A(n1525), .B(DMP_SFG[15]), .Y(n2301) );
OAI21X4TS U2212 ( .A0(n2300), .A1(n2297), .B0(n2301), .Y(n2306) );
NAND2X4TS U2213 ( .A(n1526), .B(DMP_SFG[16]), .Y(n2309) );
INVX2TS U2214 ( .A(n2309), .Y(n1527) );
AOI21X1TS U2215 ( .A0(n2310), .A1(n2306), .B0(n1527), .Y(n1528) );
OAI21X4TS U2216 ( .A0(n1749), .A1(n1529), .B0(n1528), .Y(n1534) );
XOR2X4TS U2217 ( .A(n1530), .B(DmP_mant_SFG_SWR[19]), .Y(n1531) );
NAND2X2TS U2218 ( .A(n1531), .B(DMP_SFG[17]), .Y(n1617) );
XOR2X4TS U2219 ( .A(n1534), .B(n1533), .Y(n1536) );
NAND2X4TS U2220 ( .A(n1733), .B(n1330), .Y(n1541) );
NAND4BX2TS U2221 ( .AN(n2643), .B(n2642), .C(n2641), .D(n2640), .Y(n2171) );
NAND2BX2TS U2222 ( .AN(n1542), .B(n2163), .Y(n1544) );
AOI22X2TS U2223 ( .A0(n1333), .A1(n2171), .B0(n1608), .B1(n1891), .Y(n1545)
);
AOI22X1TS U2224 ( .A0(n2222), .A1(n1333), .B0(n1989), .B1(n1927), .Y(n1554)
);
NAND2X4TS U2225 ( .A(n1558), .B(n1330), .Y(n1552) );
NAND2X2TS U2226 ( .A(n1332), .B(n2200), .Y(n1551) );
NAND2X2TS U2227 ( .A(n1098), .B(n2220), .Y(n1549) );
NAND4X6TS U2228 ( .A(n1552), .B(n1551), .C(n1550), .D(n1549), .Y(n1928) );
NAND2X2TS U2229 ( .A(n1928), .B(n1931), .Y(n1553) );
BUFX12TS U2230 ( .A(n1952), .Y(n2373) );
MXI2X4TS U2231 ( .A(n2340), .B(n2539), .S0(n980), .Y(n516) );
NAND2X2TS U2232 ( .A(n1557), .B(n1319), .Y(n1556) );
NAND3X2TS U2233 ( .A(n2632), .B(n2631), .C(n2630), .Y(n2234) );
AOI22X1TS U2234 ( .A0(n2021), .A1(n2234), .B0(n1608), .B1(n1558), .Y(n1555)
);
AOI22X2TS U2235 ( .A0(n1332), .A1(n2170), .B0(n1082), .B1(n834), .Y(n1564)
);
NAND3X1TS U2236 ( .A(n2596), .B(n2595), .C(n2594), .Y(n2347) );
AOI22X2TS U2237 ( .A0(n1767), .A1(n2347), .B0(n1577), .B1(n2171), .Y(n1563)
);
AOI22X4TS U2238 ( .A0(n1511), .A1(n2201), .B0(n984), .B1(n937), .Y(n1581) );
NAND4X4TS U2239 ( .A(n1562), .B(n1563), .C(n1564), .D(n1561), .Y(n1599) );
AOI22X4TS U2240 ( .A0(n1599), .A1(left_right_SHT2), .B0(n1989), .B1(n2163),
.Y(n1565) );
NAND2X1TS U2241 ( .A(n1774), .B(n2201), .Y(n1568) );
NAND2X2TS U2242 ( .A(n1511), .B(n2230), .Y(n1573) );
NAND2X2TS U2243 ( .A(n1582), .B(n2253), .Y(n1572) );
AOI22X2TS U2244 ( .A0(n1333), .A1(n2170), .B0(n1608), .B1(n1766), .Y(n1574)
);
BUFX12TS U2245 ( .A(n1952), .Y(n2378) );
MXI2X4TS U2246 ( .A(n2431), .B(n2777), .S0(n2378), .Y(n1576) );
XOR2X4TS U2247 ( .A(n581), .B(n1576), .Y(n2588) );
NAND2X2TS U2248 ( .A(n1586), .B(n1892), .Y(n1587) );
AOI22X1TS U2249 ( .A0(n2260), .A1(n1989), .B0(n2021), .B1(n2223), .Y(n1594)
);
NAND2X2TS U2250 ( .A(n1772), .B(n1934), .Y(n1591) );
NAND2X2TS U2251 ( .A(n1774), .B(n2184), .Y(n1590) );
MXI2X4TS U2252 ( .A(n2910), .B(n2540), .S0(n980), .Y(n517) );
INVX12TS U2253 ( .A(Shift_reg_FLAGS_7_6), .Y(n2062) );
CLKXOR2X2TS U2254 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n2261) );
INVX2TS U2255 ( .A(n2261), .Y(n1595) );
NOR2X2TS U2256 ( .A(n1595), .B(n2503), .Y(n2392) );
INVX2TS U2257 ( .A(n2392), .Y(n1598) );
NAND2X2TS U2258 ( .A(n1598), .B(n1597), .Y(n1675) );
AOI22X2TS U2259 ( .A0(n1333), .A1(n2172), .B0(n1608), .B1(n1733), .Y(n1605)
);
AND2X8TS U2260 ( .A(n1605), .B(n1604), .Y(n2906) );
MXI2X4TS U2261 ( .A(n2904), .B(n2548), .S0(n959), .Y(n520) );
MXI2X4TS U2262 ( .A(n2423), .B(n2550), .S0(n958), .Y(n523) );
NAND2X2TS U2263 ( .A(n1611), .B(n1320), .Y(n1613) );
INVX2TS U2264 ( .A(DmP_mant_SFG_SWR[8]), .Y(n1614) );
MXI2X4TS U2265 ( .A(n2884), .B(n1614), .S0(n963), .Y(n575) );
NOR2X4TS U2266 ( .A(n1615), .B(n1618), .Y(n1619) );
NAND2X4TS U2267 ( .A(n1204), .B(n1619), .Y(n1676) );
XOR2X4TS U2268 ( .A(n2598), .B(DmP_mant_SFG_SWR[20]), .Y(n1622) );
NOR2X4TS U2269 ( .A(n1622), .B(DMP_SFG[18]), .Y(n1750) );
XOR2X4TS U2270 ( .A(n2598), .B(DmP_mant_SFG_SWR[21]), .Y(n1623) );
XOR2X4TS U2271 ( .A(n2598), .B(DmP_mant_SFG_SWR[22]), .Y(n1624) );
NOR2X6TS U2272 ( .A(n1624), .B(DMP_SFG[20]), .Y(n1743) );
XOR2X4TS U2273 ( .A(n2598), .B(DmP_mant_SFG_SWR[23]), .Y(n1625) );
NAND2X8TS U2274 ( .A(n1411), .B(n1620), .Y(n1677) );
NAND2X4TS U2275 ( .A(n1622), .B(DMP_SFG[18]), .Y(n2292) );
OAI21X4TS U2276 ( .A0(n1753), .A1(n2292), .B0(n1754), .Y(n1740) );
NAND2X4TS U2277 ( .A(n1624), .B(DMP_SFG[20]), .Y(n1744) );
OAI21X2TS U2278 ( .A0(n1678), .A1(n1744), .B0(n1679), .Y(n1626) );
NAND2X4TS U2279 ( .A(n1628), .B(DMP_SFG[22]), .Y(n2315) );
OAI21X4TS U2280 ( .A0(n1631), .A1(n1331), .B0(n1630), .Y(n582) );
XNOR2X1TS U2281 ( .A(intDY_EWSW[25]), .B(n1244), .Y(n1635) );
XNOR2X1TS U2282 ( .A(n1240), .B(intDX_EWSW[1]), .Y(n1632) );
XOR2X1TS U2283 ( .A(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n1638) );
XOR2X1TS U2284 ( .A(intDY_EWSW[26]), .B(n1299), .Y(n1636) );
XNOR2X1TS U2285 ( .A(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n1643) );
XNOR2X1TS U2286 ( .A(intDY_EWSW[18]), .B(intDX_EWSW[18]), .Y(n1642) );
XNOR2X1TS U2287 ( .A(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n1641) );
XNOR2X1TS U2288 ( .A(intDY_EWSW[20]), .B(n1247), .Y(n1640) );
NAND4X2TS U2289 ( .A(n1643), .B(n1642), .C(n1641), .D(n1640), .Y(n1649) );
XNOR2X1TS U2290 ( .A(n951), .B(intDX_EWSW[10]), .Y(n1645) );
NAND4X1TS U2291 ( .A(n1647), .B(n1646), .C(n1645), .D(n1644), .Y(n1648) );
XNOR2X1TS U2292 ( .A(n1249), .B(intDX_EWSW[12]), .Y(n1653) );
XNOR2X1TS U2293 ( .A(intDY_EWSW[11]), .B(n1003), .Y(n1652) );
XNOR2X1TS U2294 ( .A(n1251), .B(intDX_EWSW[14]), .Y(n1651) );
XNOR2X1TS U2295 ( .A(n1256), .B(n999), .Y(n1650) );
XNOR2X1TS U2296 ( .A(intDY_EWSW[24]), .B(intDX_EWSW[24]), .Y(n1657) );
XNOR2X1TS U2297 ( .A(n1258), .B(n998), .Y(n1656) );
XNOR2X1TS U2298 ( .A(n1262), .B(intDX_EWSW[4]), .Y(n1654) );
NAND4X1TS U2299 ( .A(n1657), .B(n1656), .C(n1655), .D(n1654), .Y(n1658) );
XNOR2X1TS U2300 ( .A(n1254), .B(intDX_EWSW[6]), .Y(n1662) );
XNOR2X1TS U2301 ( .A(intDY_EWSW[5]), .B(n1004), .Y(n1661) );
XNOR2X1TS U2302 ( .A(intDY_EWSW[16]), .B(intDX_EWSW[16]), .Y(n1660) );
NAND4X2TS U2303 ( .A(n1663), .B(n1662), .C(n1661), .D(n1660), .Y(n1669) );
XNOR2X1TS U2304 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n1667) );
XNOR2X1TS U2305 ( .A(intDY_EWSW[28]), .B(intDX_EWSW[28]), .Y(n1666) );
XNOR2X1TS U2306 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1665) );
XNOR2X1TS U2307 ( .A(n1182), .B(intDX_EWSW[8]), .Y(n1664) );
NAND4X1TS U2308 ( .A(n1667), .B(n1666), .C(n1665), .D(n1664), .Y(n1668) );
INVX2TS U2309 ( .A(ZERO_FLAG_EXP), .Y(n1674) );
INVX6TS U2310 ( .A(n1676), .Y(n2291) );
INVX2TS U2311 ( .A(n1678), .Y(n1680) );
XOR2X4TS U2312 ( .A(n1682), .B(n1681), .Y(n1684) );
OAI2BB1X4TS U2313 ( .A0N(n2585), .A1N(n2584), .B0(n1138), .Y(n579) );
NAND2X4TS U2314 ( .A(n1221), .B(n1177), .Y(n1694) );
OAI21X4TS U2315 ( .A0(n1695), .A1(n1693), .B0(n1694), .Y(n1697) );
NOR2X8TS U2316 ( .A(n1686), .B(DMP_exp_NRM2_EW[3]), .Y(n1701) );
NAND2X4TS U2317 ( .A(n1686), .B(DMP_exp_NRM2_EW[3]), .Y(n1702) );
OAI21X4TS U2318 ( .A0(n1699), .A1(n1701), .B0(n1702), .Y(n1687) );
INVX8TS U2319 ( .A(n579), .Y(n1689) );
NOR2X8TS U2320 ( .A(n1689), .B(DMP_exp_NRM2_EW[4]), .Y(n1716) );
INVX2TS U2321 ( .A(n1716), .Y(n1690) );
NAND2X6TS U2322 ( .A(n1689), .B(DMP_exp_NRM2_EW[4]), .Y(n1713) );
XOR2X4TS U2323 ( .A(n1717), .B(n1691), .Y(n2404) );
OAI21X4TS U2324 ( .A0(n1717), .A1(n1716), .B0(n1713), .Y(n1692) );
XNOR2X4TS U2325 ( .A(n1692), .B(DMP_exp_NRM2_EW[5]), .Y(n2408) );
NOR2X8TS U2326 ( .A(n2404), .B(n2408), .Y(n1721) );
XOR2X4TS U2327 ( .A(n1696), .B(n1695), .Y(n2320) );
NAND2X2TS U2328 ( .A(n1699), .B(n1187), .Y(n1698) );
XOR2X4TS U2329 ( .A(n1222), .B(n1698), .Y(n2389) );
INVX2TS U2330 ( .A(n2389), .Y(n1707) );
OAI21X4TS U2331 ( .A0(n1222), .A1(n1700), .B0(n1699), .Y(n1705) );
INVX2TS U2332 ( .A(n1701), .Y(n1703) );
NAND2X2TS U2333 ( .A(n1703), .B(n1702), .Y(n1704) );
XNOR2X4TS U2334 ( .A(n1705), .B(n1704), .Y(n2371) );
NOR2X2TS U2335 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM2_EW[5]), .Y(n1709)
);
OAI21X4TS U2336 ( .A0(n1717), .A1(n1716), .B0(n1710), .Y(n1711) );
INVX4TS U2337 ( .A(n1713), .Y(n1714) );
NOR2X4TS U2338 ( .A(n1714), .B(DMP_exp_NRM2_EW[5]), .Y(n1715) );
OAI21X4TS U2339 ( .A0(n1717), .A1(n1716), .B0(n1715), .Y(n1718) );
NOR2X2TS U2340 ( .A(n955), .B(n1215), .Y(n2363) );
NAND2X2TS U2341 ( .A(n1215), .B(n955), .Y(n2365) );
OAI21X4TS U2342 ( .A0(n2380), .A1(n2363), .B0(n2365), .Y(n2369) );
OAI22X4TS U2343 ( .A0(n2369), .A1(n1722), .B0(n1180), .B1(n1218), .Y(n1957)
);
NOR2X2TS U2344 ( .A(n1219), .B(n2527), .Y(n1954) );
NAND2X2TS U2345 ( .A(n2527), .B(n1219), .Y(n1953) );
XOR2X1TS U2346 ( .A(DMP_EXP_EWSW[27]), .B(n1232), .Y(n1723) );
XOR2X1TS U2347 ( .A(n1724), .B(n1723), .Y(n1725) );
XOR2X4TS U2348 ( .A(n1008), .B(DmP_mant_SFG_SWR[11]), .Y(n1728) );
INVX4TS U2349 ( .A(n1728), .Y(n1727) );
NOR2X8TS U2350 ( .A(n1727), .B(n2428), .Y(n1981) );
XNOR2X4TS U2351 ( .A(n1730), .B(n1729), .Y(n1731) );
MXI2X4TS U2352 ( .A(n2882), .B(n2541), .S0(n958), .Y(n562) );
MXI2X4TS U2353 ( .A(n2908), .B(n2546), .S0(n1329), .Y(n518) );
AND2X2TS U2354 ( .A(n2320), .B(n2318), .Y(n1737) );
AOI21X1TS U2355 ( .A0(n1677), .A1(n1741), .B0(n1740), .Y(n1742) );
XOR2X4TS U2356 ( .A(n1746), .B(n1745), .Y(n1748) );
OAI21X4TS U2357 ( .A0(n1748), .A1(n1331), .B0(n1747), .Y(n585) );
INVX2TS U2358 ( .A(n2292), .Y(n1751) );
AOI21X1TS U2359 ( .A0(n1677), .A1(n2293), .B0(n1751), .Y(n1752) );
OAI2BB1X4TS U2360 ( .A0N(n1192), .A1N(n1407), .B0(n1752), .Y(n1757) );
INVX2TS U2361 ( .A(n1753), .Y(n1755) );
XOR2X4TS U2362 ( .A(n1757), .B(n1756), .Y(n1759) );
OAI21X4TS U2363 ( .A0(n1759), .A1(n983), .B0(n1758), .Y(n586) );
AOI22X1TS U2364 ( .A0(n1359), .A1(DmP_mant_SHT1_SW[19]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1760) );
NAND2X2TS U2365 ( .A(n1352), .B(Raw_mant_NRM_SWR[12]), .Y(n1763) );
AOI22X1TS U2366 ( .A0(n1359), .A1(DmP_mant_SHT1_SW[11]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1762) );
AO22X4TS U2367 ( .A0(n2024), .A1(left_right_SHT2), .B0(n1935), .B1(n984),
.Y(n2586) );
INVX2TS U2368 ( .A(n2260), .Y(n1771) );
OAI21X4TS U2369 ( .A0(n1771), .A1(n1203), .B0(n1769), .Y(n1933) );
NAND2X1TS U2370 ( .A(n1772), .B(n2187), .Y(n1777) );
NAND3X4TS U2371 ( .A(n1777), .B(n1776), .C(n1775), .Y(n1932) );
MXI2X4TS U2372 ( .A(n1933), .B(n1932), .S0(n1320), .Y(n1779) );
INVX2TS U2373 ( .A(DmP_mant_SFG_SWR[11]), .Y(n1780) );
MXI2X4TS U2374 ( .A(n2889), .B(n1780), .S0(n960), .Y(n553) );
NAND2X4TS U2375 ( .A(n2482), .B(intDX_EWSW[0]), .Y(n1782) );
OAI21X4TS U2376 ( .A0(n1783), .A1(n1782), .B0(n1781), .Y(n1790) );
OAI21X4TS U2377 ( .A0(n1787), .A1(n1786), .B0(n1785), .Y(n1788) );
AOI21X4TS U2378 ( .A0(n1790), .A1(n1789), .B0(n1788), .Y(n1802) );
NOR2X4TS U2379 ( .A(n1263), .B(intDX_EWSW[4]), .Y(n1792) );
AOI21X4TS U2380 ( .A0(n1798), .A1(n1799), .B0(n1797), .Y(n1800) );
OAI21X4TS U2381 ( .A0(n1802), .A1(n1801), .B0(n1800), .Y(n1830) );
NOR2X2TS U2382 ( .A(n1183), .B(intDX_EWSW[8]), .Y(n1803) );
NOR2X4TS U2383 ( .A(n1803), .B(n1810), .Y(n1805) );
NOR2X8TS U2384 ( .A(n2471), .B(intDX_EWSW[11]), .Y(n1813) );
NOR2X8TS U2385 ( .A(n1813), .B(n1804), .Y(n1815) );
NAND2X4TS U2386 ( .A(n1805), .B(n1815), .Y(n1809) );
NOR2X4TS U2387 ( .A(n1806), .B(n1819), .Y(n1808) );
NOR2X4TS U2388 ( .A(n1809), .B(n1827), .Y(n1829) );
OAI21X4TS U2389 ( .A0(n1813), .A1(n1812), .B0(n1811), .Y(n1814) );
AOI21X4TS U2390 ( .A0(n1816), .A1(n1815), .B0(n1814), .Y(n1828) );
NAND2X2TS U2391 ( .A(intDX_EWSW[13]), .B(n1257), .Y(n1817) );
OAI21X4TS U2392 ( .A0(n1819), .A1(n1818), .B0(n1817), .Y(n1824) );
NAND2X2TS U2393 ( .A(n1259), .B(intDX_EWSW[15]), .Y(n1820) );
OAI21X4TS U2394 ( .A0(n1822), .A1(n1821), .B0(n1820), .Y(n1823) );
AOI21X4TS U2395 ( .A0(n1824), .A1(n1825), .B0(n1823), .Y(n1826) );
NOR2X2TS U2396 ( .A(n2479), .B(n1247), .Y(n1831) );
NOR2X4TS U2397 ( .A(n1831), .B(n1848), .Y(n1833) );
NOR2X4TS U2398 ( .A(n2464), .B(n1301), .Y(n1832) );
NAND2X6TS U2399 ( .A(n1833), .B(n1853), .Y(n1856) );
NOR2X8TS U2400 ( .A(n2475), .B(intDX_EWSW[29]), .Y(n1869) );
NOR2X8TS U2401 ( .A(n1869), .B(n1836), .Y(n1837) );
OR2X4TS U2402 ( .A(n2474), .B(intDX_EWSW[30]), .Y(n1871) );
NOR2X8TS U2403 ( .A(n1838), .B(n1874), .Y(n1876) );
NAND2X2TS U2404 ( .A(n2476), .B(intDX_EWSW[19]), .Y(n1842) );
OAI21X4TS U2405 ( .A0(n1844), .A1(n1843), .B0(n1842), .Y(n1845) );
AOI21X4TS U2406 ( .A0(n1847), .A1(n1846), .B0(n1845), .Y(n1857) );
NAND2X2TS U2407 ( .A(n2464), .B(n1301), .Y(n1850) );
OAI21X4TS U2408 ( .A0(n1851), .A1(n1850), .B0(n1849), .Y(n1852) );
AOI21X4TS U2409 ( .A0(n1853), .A1(n1854), .B0(n1852), .Y(n1855) );
NAND2X4TS U2410 ( .A(n2463), .B(intDX_EWSW[24]), .Y(n1859) );
OAI21X4TS U2411 ( .A0(n1860), .A1(n1859), .B0(n1858), .Y(n1866) );
NAND2X2TS U2412 ( .A(n2473), .B(n1299), .Y(n1862) );
NAND2X2TS U2413 ( .A(n2467), .B(n1246), .Y(n1861) );
AOI21X4TS U2414 ( .A0(n1866), .A1(n1865), .B0(n1864), .Y(n1875) );
NAND2X2TS U2415 ( .A(n2475), .B(intDX_EWSW[29]), .Y(n1867) );
OAI21X4TS U2416 ( .A0(n1869), .A1(n1868), .B0(n1867), .Y(n1872) );
NAND2X2TS U2417 ( .A(n1401), .B(n1244), .Y(n1879) );
NAND2X2TS U2418 ( .A(n1019), .B(intDX_EWSW[24]), .Y(n1882) );
MXI2X4TS U2419 ( .A(n2906), .B(n2547), .S0(n1329), .Y(n519) );
AOI22X1TS U2420 ( .A0(n1120), .A1(n2171), .B0(n1892), .B1(n1891), .Y(n1893)
);
MXI2X4TS U2421 ( .A(n2876), .B(n2536), .S0(n961), .Y(n559) );
NAND2X1TS U2422 ( .A(n2134), .B(n1168), .Y(n1895) );
NAND2X2TS U2423 ( .A(n2134), .B(n1162), .Y(n1898) );
NAND2X2TS U2424 ( .A(n2145), .B(DMP_EXP_EWSW[29]), .Y(n1901) );
NOR3X1TS U2425 ( .A(n2460), .B(Raw_mant_NRM_SWR[7]), .C(n1238), .Y(n1904) );
NOR2X4TS U2426 ( .A(n2243), .B(Raw_mant_NRM_SWR[6]), .Y(n1906) );
NAND2X2TS U2427 ( .A(n1907), .B(Raw_mant_NRM_SWR[3]), .Y(n2247) );
INVX2TS U2428 ( .A(n1908), .Y(n1909) );
NOR2X8TS U2429 ( .A(n1911), .B(n1910), .Y(n2280) );
NOR2X1TS U2430 ( .A(n1912), .B(n2746), .Y(n1913) );
NAND2X1TS U2431 ( .A(n982), .B(n1202), .Y(n1916) );
NAND4X1TS U2432 ( .A(n1916), .B(n1915), .C(n1412), .D(n1197), .Y(n1917) );
XOR2X4TS U2433 ( .A(n1008), .B(DmP_mant_SFG_SWR[6]), .Y(n2264) );
NOR2X2TS U2434 ( .A(n1977), .B(DMP_SFG[5]), .Y(n1920) );
INVX2TS U2435 ( .A(n1977), .Y(n1919) );
INVX2TS U2436 ( .A(n1921), .Y(n1922) );
AOI21X4TS U2437 ( .A0(n2328), .A1(n1923), .B0(n1922), .Y(n1926) );
XOR2X1TS U2438 ( .A(n1924), .B(DMP_SFG[7]), .Y(n1925) );
MXI2X4TS U2439 ( .A(n2897), .B(n2538), .S0(n964), .Y(n524) );
AOI22X1TS U2440 ( .A0(n2222), .A1(n1120), .B0(n2021), .B1(n1927), .Y(n1930)
);
NAND2X2TS U2441 ( .A(n1928), .B(n1320), .Y(n1929) );
MXI2X4TS U2442 ( .A(n2872), .B(n2537), .S0(n1329), .Y(n570) );
MXI2X4TS U2443 ( .A(n1933), .B(n1932), .S0(n1319), .Y(n1937) );
NAND2X2TS U2444 ( .A(n2145), .B(n1219), .Y(n1941) );
NAND2X2TS U2445 ( .A(n2145), .B(DMP_EXP_EWSW[23]), .Y(n1945) );
INVX8TS U2446 ( .A(n2341), .Y(busy) );
XNOR2X1TS U2447 ( .A(n1949), .B(DmP_mant_SFG_SWR[1]), .Y(n1948) );
MXI2X1TS U2448 ( .A(n2499), .B(n1948), .S0(n2348), .Y(n577) );
XNOR2X1TS U2449 ( .A(n1949), .B(DmP_mant_SFG_SWR[0]), .Y(n1950) );
MXI2X2TS U2450 ( .A(n2864), .B(n1950), .S0(n2348), .Y(n571) );
INVX2TS U2451 ( .A(n2390), .Y(n2349) );
NOR2X1TS U2452 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n1951) );
NAND2X2TS U2453 ( .A(n1951), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2325) );
MXI2X1TS U2454 ( .A(n2442), .B(n2555), .S0(n2373), .Y(n738) );
MXI2X1TS U2455 ( .A(n2441), .B(n2554), .S0(n2373), .Y(n735) );
INVX2TS U2456 ( .A(n1953), .Y(n1955) );
NOR2X1TS U2457 ( .A(n1955), .B(n1954), .Y(n1956) );
XOR2X1TS U2458 ( .A(n1957), .B(n1956), .Y(n1958) );
INVX2TS U2459 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2160) );
MXI2X2TS U2460 ( .A(n1958), .B(n2160), .S0(n2351), .Y(n814) );
MXI2X1TS U2461 ( .A(n2439), .B(n2515), .S0(n1307), .Y(n729) );
MXI2X1TS U2462 ( .A(n2443), .B(n2513), .S0(n1307), .Y(n750) );
MXI2X1TS U2463 ( .A(n2440), .B(n2519), .S0(n980), .Y(n732) );
MXI2X1TS U2464 ( .A(n2444), .B(n2514), .S0(n980), .Y(n768) );
MXI2X1TS U2465 ( .A(n2445), .B(n2512), .S0(n2373), .Y(n756) );
MXI2X1TS U2466 ( .A(n2508), .B(n2419), .S0(n1307), .Y(n765) );
XOR2X1TS U2467 ( .A(n1959), .B(DMP_SFG[1]), .Y(n1960) );
XNOR2X1TS U2468 ( .A(n1960), .B(n2237), .Y(n1961) );
MXI2X2TS U2469 ( .A(n2528), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n1964) );
MXI2X1TS U2470 ( .A(n2427), .B(n983), .S0(n2396), .Y(n916) );
CLKXOR2X2TS U2471 ( .A(n1965), .B(DMP_SFG[2]), .Y(n1968) );
INVX2TS U2472 ( .A(n1968), .Y(n1967) );
MXI2X4TS U2473 ( .A(n1968), .B(n1967), .S0(n1966), .Y(n1969) );
NAND2X2TS U2474 ( .A(n1972), .B(n2420), .Y(n1970) );
NAND2X2TS U2475 ( .A(n1973), .B(DMP_SFG[3]), .Y(n1974) );
OAI21X2TS U2476 ( .A0(n2264), .A1(DMP_SFG[4]), .B0(n2263), .Y(n1976) );
XOR2X1TS U2477 ( .A(n1977), .B(DMP_SFG[5]), .Y(n1978) );
MXI2X2TS U2478 ( .A(n1980), .B(n2734), .S0(n983), .Y(n563) );
NAND2X2TS U2479 ( .A(n1726), .B(DMP_SFG[8]), .Y(n1982) );
INVX2TS U2480 ( .A(n1984), .Y(n1985) );
MXI2X2TS U2481 ( .A(n1988), .B(n2736), .S0(n983), .Y(n552) );
NAND2X2TS U2482 ( .A(n1146), .B(n2608), .Y(final_result_ieee[29]) );
AOI22X1TS U2483 ( .A0(n2260), .A1(n1333), .B0(n1989), .B1(n2223), .Y(n1992)
);
NAND2X2TS U2484 ( .A(n2138), .B(DMP_EXP_EWSW[21]), .Y(n1993) );
NAND2X2TS U2485 ( .A(n2526), .B(DMP_EXP_EWSW[20]), .Y(n2002) );
NAND2X2TS U2486 ( .A(n2526), .B(DMP_EXP_EWSW[14]), .Y(n2008) );
NAND2X2TS U2487 ( .A(n2526), .B(DMP_EXP_EWSW[15]), .Y(n2011) );
NAND2X1TS U2488 ( .A(n2062), .B(n1208), .Y(n2026) );
NAND2X2TS U2489 ( .A(n1195), .B(intDX_EWSW[9]), .Y(n2031) );
NAND2X1TS U2490 ( .A(n2062), .B(n1229), .Y(n2029) );
NAND2X2TS U2491 ( .A(n1195), .B(n1004), .Y(n2034) );
NAND2X2TS U2492 ( .A(n1402), .B(intDY_EWSW[5]), .Y(n2033) );
NAND2X1TS U2493 ( .A(n2134), .B(n1212), .Y(n2032) );
NAND3X2TS U2494 ( .A(n2034), .B(n2033), .C(n2032), .Y(n651) );
NAND2X2TS U2495 ( .A(n1361), .B(n940), .Y(n2036) );
NAND2X2TS U2496 ( .A(n2128), .B(intDX_EWSW[6]), .Y(n2040) );
NAND2X2TS U2497 ( .A(n1361), .B(n1254), .Y(n2039) );
NAND2X1TS U2498 ( .A(n2134), .B(n1234), .Y(n2038) );
NAND3X2TS U2499 ( .A(n2040), .B(n2039), .C(n2038), .Y(n649) );
NAND2X2TS U2500 ( .A(n1195), .B(n1247), .Y(n2043) );
NAND2X1TS U2501 ( .A(n2062), .B(n1296), .Y(n2041) );
NAND3X2TS U2502 ( .A(n2042), .B(n2043), .C(n2041), .Y(n621) );
NAND2X2TS U2503 ( .A(n1402), .B(n1182), .Y(n2045) );
NAND2X1TS U2504 ( .A(n2062), .B(n1173), .Y(n2044) );
NAND2X2TS U2505 ( .A(n954), .B(intDX_EWSW[4]), .Y(n2049) );
NAND2X1TS U2506 ( .A(n2134), .B(n1227), .Y(n2047) );
NAND3X2TS U2507 ( .A(n2049), .B(n2048), .C(n2047), .Y(n653) );
NAND2X1TS U2508 ( .A(n2062), .B(DmP_EXP_EWSW[11]), .Y(n2050) );
NAND2X2TS U2509 ( .A(n1360), .B(intDX_EWSW[18]), .Y(n2055) );
NAND2X2TS U2510 ( .A(n1361), .B(intDY_EWSW[18]), .Y(n2054) );
NAND2X2TS U2511 ( .A(n1402), .B(n1225), .Y(n2057) );
NAND2X2TS U2512 ( .A(n1195), .B(intDX_EWSW[16]), .Y(n2065) );
NAND2X2TS U2513 ( .A(n2138), .B(n950), .Y(n2066) );
NAND2X2TS U2514 ( .A(n2138), .B(DmP_EXP_EWSW[2]), .Y(n2069) );
NAND2X2TS U2515 ( .A(n954), .B(n1246), .Y(n2074) );
NAND2X1TS U2516 ( .A(n2109), .B(n1232), .Y(n2072) );
NAND2X2TS U2517 ( .A(n2129), .B(n1258), .Y(n2076) );
NAND2X2TS U2518 ( .A(n1195), .B(intDX_EWSW[21]), .Y(n2083) );
NAND2X2TS U2519 ( .A(n945), .B(intDY_EWSW[21]), .Y(n2082) );
NAND2X2TS U2520 ( .A(n2128), .B(intDX_EWSW[17]), .Y(n2086) );
NAND2X2TS U2521 ( .A(n1074), .B(intDY_EWSW[17]), .Y(n2085) );
NAND2X2TS U2522 ( .A(n2128), .B(intDX_EWSW[14]), .Y(n2089) );
NAND2X2TS U2523 ( .A(n1364), .B(n1251), .Y(n2088) );
NAND3X2TS U2524 ( .A(n2089), .B(n2088), .C(n2087), .Y(n633) );
NAND2X2TS U2525 ( .A(n2129), .B(n1256), .Y(n2091) );
NAND2X2TS U2526 ( .A(n2128), .B(intDX_EWSW[19]), .Y(n2095) );
NAND3X2TS U2527 ( .A(n2095), .B(n2094), .C(n2093), .Y(n623) );
NAND2X2TS U2528 ( .A(n1364), .B(n1249), .Y(n2097) );
NAND2X2TS U2529 ( .A(n2130), .B(n949), .Y(n2105) );
NAND2X1TS U2530 ( .A(n2258), .B(intDX_EWSW[2]), .Y(n2118) );
NAND2X2TS U2531 ( .A(n1402), .B(intDX_EWSW[4]), .Y(n2132) );
NAND3X2TS U2532 ( .A(n2132), .B(n2133), .C(n2131), .Y(n800) );
NAND2X2TS U2533 ( .A(n1360), .B(n1225), .Y(n2136) );
NAND2X1TS U2534 ( .A(n2134), .B(n1210), .Y(n2135) );
NAND2X1TS U2535 ( .A(n1364), .B(intDX_EWSW[9]), .Y(n2141) );
NAND2X2TS U2536 ( .A(n1360), .B(intDY_EWSW[9]), .Y(n2140) );
NAND3X2TS U2537 ( .A(n2141), .B(n2140), .C(n2139), .Y(n795) );
NAND2X2TS U2538 ( .A(n2145), .B(DMP_EXP_EWSW[27]), .Y(n2146) );
NOR2X1TS U2539 ( .A(Raw_mant_NRM_SWR[16]), .B(n2746), .Y(n2150) );
AOI21X1TS U2540 ( .A0(n2151), .A1(n2150), .B0(Raw_mant_NRM_SWR[18]), .Y(
n2154) );
NOR2X1TS U2541 ( .A(n2387), .B(n2160), .Y(n2161) );
MXI2X2TS U2542 ( .A(n2314), .B(n2161), .S0(n2393), .Y(n2850) );
AND2X4TS U2543 ( .A(n2227), .B(n2164), .Y(n2863) );
NAND2X4TS U2544 ( .A(n2167), .B(n2166), .Y(n821) );
OAI2BB1X2TS U2545 ( .A0N(n1265), .A1N(n2529), .B0(n2168), .Y(n560) );
AOI2BB2X2TS U2546 ( .B0(n2171), .B1(n2745), .A0N(n1316), .A1N(n2495), .Y(
n2829) );
AOI2BB2X2TS U2547 ( .B0(n2172), .B1(n2745), .A0N(n1316), .A1N(n2551), .Y(
n2804) );
NAND2X2TS U2548 ( .A(n2252), .B(DmP_mant_SHT1_SW[17]), .Y(n2807) );
NAND2X2TS U2549 ( .A(n1282), .B(n996), .Y(n2786) );
NAND2X2TS U2550 ( .A(n1030), .B(Raw_mant_NRM_SWR[11]), .Y(n2810) );
INVX2TS U2551 ( .A(n2175), .Y(n2176) );
AOI22X1TS U2552 ( .A0(n1374), .A1(DmP_mant_SHT1_SW[6]), .B0(
DmP_mant_SHT1_SW[5]), .B1(n2212), .Y(n2179) );
AOI22X1TS U2553 ( .A0(n1359), .A1(DmP_mant_SHT1_SW[2]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2182) );
INVX2TS U2554 ( .A(n2184), .Y(n2185) );
AOI21X2TS U2555 ( .A0(n2252), .A1(DmP_mant_SHT1_SW[16]), .B0(n2186), .Y(
n2813) );
INVX2TS U2556 ( .A(n2187), .Y(n2188) );
AOI21X2TS U2557 ( .A0(n2252), .A1(DmP_mant_SHT1_SW[20]), .B0(n2189), .Y(
n2858) );
INVX2TS U2558 ( .A(n2190), .Y(n2191) );
AOI21X2TS U2559 ( .A0(n2252), .A1(DmP_mant_SHT1_SW[10]), .B0(n2192), .Y(
n2797) );
AOI22X1TS U2560 ( .A0(n1374), .A1(DmP_mant_SHT1_SW[1]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2193) );
NAND2X2TS U2561 ( .A(n2194), .B(n2226), .Y(n2862) );
AOI22X1TS U2562 ( .A0(n1374), .A1(DmP_mant_SHT1_SW[9]), .B0(n2212), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2195) );
NAND2X4TS U2563 ( .A(n2196), .B(n2195), .Y(n2224) );
INVX2TS U2564 ( .A(n2201), .Y(n2202) );
NAND2X2TS U2565 ( .A(n1352), .B(Raw_mant_NRM_SWR[0]), .Y(n2204) );
NAND2X2TS U2566 ( .A(n2207), .B(n2226), .Y(n2784) );
NAND2X2TS U2567 ( .A(n2216), .B(n2226), .Y(n2827) );
NAND2X2TS U2568 ( .A(n2216), .B(n1044), .Y(n2789) );
NAND2X2TS U2569 ( .A(n2218), .B(n1044), .Y(n2806) );
NAND2X2TS U2570 ( .A(n2218), .B(n2226), .Y(n2844) );
AOI22X2TS U2571 ( .A0(n2226), .A1(n2225), .B0(n2224), .B1(n1171), .Y(n2787)
);
AOI2BB2X2TS U2572 ( .B0(Raw_mant_NRM_SWR[1]), .B1(n1038), .A0N(n2486), .A1N(
n953), .Y(n2868) );
NAND2X1TS U2573 ( .A(n1374), .B(DmP_mant_SHT1_SW[22]), .Y(n2231) );
OAI22X2TS U2574 ( .A0(n1149), .A1(n2722), .B0(n967), .B1(n2721), .Y(
final_result_ieee[5]) );
OAI22X2TS U2575 ( .A0(n1149), .A1(n2690), .B0(n967), .B1(n2689), .Y(
final_result_ieee[8]) );
OAI22X2TS U2576 ( .A0(n1149), .A1(n2708), .B0(n1150), .B1(n2707), .Y(
final_result_ieee[17]) );
OAI22X2TS U2577 ( .A0(n1149), .A1(n2702), .B0(n1150), .B1(n2701), .Y(
final_result_ieee[14]) );
OAI22X2TS U2578 ( .A0(n1148), .A1(n2676), .B0(n967), .B1(n2675), .Y(
final_result_ieee[13]) );
OAI22X2TS U2579 ( .A0(n1149), .A1(n2728), .B0(n967), .B1(n2727), .Y(
final_result_ieee[20]) );
OAI22X2TS U2580 ( .A0(n1148), .A1(n2688), .B0(n967), .B1(n2687), .Y(
final_result_ieee[10]) );
OAI22X2TS U2581 ( .A0(n1148), .A1(n2670), .B0(n1150), .B1(n2669), .Y(
final_result_ieee[16]) );
OAI22X2TS U2582 ( .A0(n1148), .A1(n2664), .B0(n1150), .B1(n2663), .Y(
final_result_ieee[19]) );
OAI22X2TS U2583 ( .A0(n1149), .A1(n2684), .B0(n967), .B1(n2683), .Y(
final_result_ieee[11]) );
AOI2BB2X2TS U2584 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1038), .A0N(n2458), .A1N(
n953), .Y(n2819) );
OAI21X1TS U2585 ( .A0(n2238), .A1(DMP_SFG[0]), .B0(n2237), .Y(n2239) );
MXI2X1TS U2586 ( .A(n2486), .B(n2239), .S0(n2348), .Y(n569) );
INVX2TS U2587 ( .A(n2253), .Y(n2254) );
NOR2X4TS U2588 ( .A(n2257), .B(n2256), .Y(n2847) );
CLKBUFX2TS U2589 ( .A(n2563), .Y(n2560) );
CLKBUFX2TS U2590 ( .A(n2755), .Y(n2565) );
CLKBUFX2TS U2591 ( .A(n2562), .Y(n2566) );
CLKBUFX3TS U2592 ( .A(n2747), .Y(n2569) );
BUFX3TS U2593 ( .A(n2761), .Y(n2748) );
CLKBUFX3TS U2594 ( .A(n2760), .Y(n2567) );
BUFX3TS U2595 ( .A(n2775), .Y(n2769) );
BUFX3TS U2596 ( .A(n2754), .Y(n2568) );
BUFX3TS U2597 ( .A(n2775), .Y(n2768) );
BUFX3TS U2598 ( .A(n2749), .Y(n2773) );
BUFX3TS U2599 ( .A(n2761), .Y(n2772) );
BUFX3TS U2600 ( .A(n2570), .Y(n2771) );
BUFX3TS U2601 ( .A(n2751), .Y(n2770) );
CLKBUFX2TS U2602 ( .A(n2563), .Y(n2564) );
CLKBUFX3TS U2603 ( .A(n2259), .Y(n2562) );
CLKBUFX3TS U2604 ( .A(n2760), .Y(n2559) );
BUFX3TS U2605 ( .A(n1304), .Y(n2759) );
CLKBUFX3TS U2606 ( .A(n2775), .Y(n2767) );
CLKBUFX3TS U2607 ( .A(n2775), .Y(n2766) );
CLKBUFX3TS U2608 ( .A(n2775), .Y(n2765) );
BUFX3TS U2609 ( .A(n2570), .Y(n2750) );
BUFX3TS U2610 ( .A(n2761), .Y(n2762) );
CLKBUFX3TS U2611 ( .A(n2259), .Y(n2760) );
BUFX3TS U2612 ( .A(n2570), .Y(n2764) );
BUFX3TS U2613 ( .A(n2259), .Y(n2758) );
CLKBUFX3TS U2614 ( .A(n2775), .Y(n2774) );
OAI22X2TS U2615 ( .A0(n1147), .A1(n2662), .B0(n967), .B1(n2661), .Y(
final_result_ieee[12]) );
OAI22X2TS U2616 ( .A0(n1147), .A1(n2653), .B0(n1150), .B1(n2652), .Y(
final_result_ieee[15]) );
OAI22X2TS U2617 ( .A0(n1147), .A1(n2668), .B0(n967), .B1(n2667), .Y(
final_result_ieee[6]) );
OAI22X2TS U2618 ( .A0(n1147), .A1(n2659), .B0(n967), .B1(n2658), .Y(
final_result_ieee[9]) );
OAI22X2TS U2619 ( .A0(n1147), .A1(n2657), .B0(n1150), .B1(n2656), .Y(
final_result_ieee[18]) );
OAI2BB2X2TS U2620 ( .B0(n1150), .B1(n2724), .A0N(n1144), .A1N(n2723), .Y(
final_result_ieee[22]) );
OAI2BB2X2TS U2621 ( .B0(n1150), .B1(n2682), .A0N(n1144), .A1N(n2681), .Y(
final_result_ieee[21]) );
OAI2BB2X2TS U2622 ( .B0(n967), .B1(n2718), .A0N(n1144), .A1N(n2717), .Y(
final_result_ieee[7]) );
NAND2X2TS U2623 ( .A(n2387), .B(n2260), .Y(n2783) );
NAND3X2TS U2624 ( .A(n1360), .B(n2261), .C(n2262), .Y(n2922) );
XOR2X4TS U2625 ( .A(n2263), .B(DMP_SFG[4]), .Y(n2266) );
NOR2X2TS U2626 ( .A(n2263), .B(DMP_SFG[4]), .Y(n2265) );
MXI2X4TS U2627 ( .A(n2266), .B(n2265), .S0(n2264), .Y(n2267) );
AOI2BB2X4TS U2628 ( .B0(n2272), .B1(n2271), .A0N(DP_OP_301J12_122_1182_n171),
.A1N(DMP_SFG[10]), .Y(n2276) );
XNOR2X1TS U2629 ( .A(n2274), .B(DMP_SFG[11]), .Y(n2275) );
XOR2X4TS U2630 ( .A(n2276), .B(n2275), .Y(n2277) );
NAND2X2TS U2631 ( .A(n2278), .B(n2343), .Y(n2284) );
NOR3X1TS U2632 ( .A(n931), .B(n2529), .C(Raw_mant_NRM_SWR[12]), .Y(n2279) );
INVX2TS U2633 ( .A(n2281), .Y(n2282) );
NAND2X1TS U2634 ( .A(n2286), .B(n2285), .Y(n2919) );
INVX2TS U2635 ( .A(n2287), .Y(n2299) );
NAND2X1TS U2636 ( .A(n2297), .B(n2299), .Y(n2288) );
MX2X4TS U2637 ( .A(n2289), .B(n1015), .S0(n1331), .Y(n591) );
MXI2X4TS U2638 ( .A(n2290), .B(n2544), .S0(n963), .Y(n555) );
XOR2X4TS U2639 ( .A(n2295), .B(n2294), .Y(n2296) );
INVX2TS U2640 ( .A(n2297), .Y(n2298) );
INVX2TS U2641 ( .A(n2300), .Y(n2302) );
XOR2X4TS U2642 ( .A(n2304), .B(n2303), .Y(n2305) );
XOR2X4TS U2643 ( .A(n2312), .B(n2311), .Y(n2313) );
NAND2X4TS U2644 ( .A(n2924), .B(n2319), .Y(n812) );
NAND2X1TS U2645 ( .A(n1374), .B(DmP_mant_SHT1_SW[14]), .Y(n2323) );
CLKBUFX2TS U2646 ( .A(n1335), .Y(n2561) );
INVX2TS U2647 ( .A(final_result_ieee[5]), .Y(n2881) );
INVX2TS U2648 ( .A(final_result_ieee[8]), .Y(n2886) );
INVX2TS U2649 ( .A(final_result_ieee[17]), .Y(n2903) );
INVX2TS U2650 ( .A(final_result_ieee[14]), .Y(n2898) );
INVX2TS U2651 ( .A(final_result_ieee[13]), .Y(n2896) );
INVX2TS U2652 ( .A(final_result_ieee[20]), .Y(n2909) );
INVX2TS U2653 ( .A(final_result_ieee[4]), .Y(n2879) );
INVX2TS U2654 ( .A(final_result_ieee[10]), .Y(n2890) );
INVX2TS U2655 ( .A(final_result_ieee[2]), .Y(n2875) );
INVX2TS U2656 ( .A(final_result_ieee[1]), .Y(n2873) );
INVX2TS U2657 ( .A(final_result_ieee[16]), .Y(n2901) );
INVX2TS U2658 ( .A(final_result_ieee[19]), .Y(n2907) );
INVX2TS U2659 ( .A(final_result_ieee[11]), .Y(n2892) );
INVX2TS U2660 ( .A(final_result_ieee[3]), .Y(n2877) );
INVX2TS U2661 ( .A(final_result_ieee[12]), .Y(n2894) );
INVX2TS U2662 ( .A(final_result_ieee[15]), .Y(n2899) );
INVX2TS U2663 ( .A(final_result_ieee[6]), .Y(n2883) );
INVX2TS U2664 ( .A(final_result_ieee[9]), .Y(n2888) );
INVX2TS U2665 ( .A(final_result_ieee[0]), .Y(n2871) );
INVX2TS U2666 ( .A(final_result_ieee[18]), .Y(n2905) );
INVX2TS U2667 ( .A(final_result_ieee[22]), .Y(n2912) );
INVX2TS U2668 ( .A(final_result_ieee[21]), .Y(n2911) );
INVX2TS U2669 ( .A(final_result_ieee[7]), .Y(n2885) );
INVX2TS U2670 ( .A(n571), .Y(n2660) );
MXI2X1TS U2671 ( .A(beg_OP), .B(n2528), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2326) );
INVX2TS U2672 ( .A(n2330), .Y(n2329) );
INVX2TS U2673 ( .A(n2333), .Y(n2335) );
NAND2X2TS U2674 ( .A(n2335), .B(n2334), .Y(n2337) );
INVX2TS U2675 ( .A(n2340), .Y(n2739) );
NAND2X2TS U2676 ( .A(n1146), .B(n2593), .Y(final_result_ieee[26]) );
NAND2X2TS U2677 ( .A(n1146), .B(n2583), .Y(final_result_ieee[25]) );
NAND2X2TS U2678 ( .A(n1146), .B(n2597), .Y(final_result_ieee[27]) );
NAND2X2TS U2679 ( .A(n1146), .B(n2599), .Y(final_result_ieee[28]) );
CLKMX2X2TS U2680 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(busy),
.Y(n685) );
CLKMX2X2TS U2681 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(busy),
.Y(n754) );
CLKMX2X2TS U2682 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(busy),
.Y(n700) );
CLKMX2X2TS U2683 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(busy),
.Y(n675) );
CLKMX2X2TS U2684 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(busy),
.Y(n680) );
CLKMX2X2TS U2685 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(busy),
.Y(n670) );
CLKMX2X2TS U2686 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(busy),
.Y(n695) );
INVX8TS U2687 ( .A(n2341), .Y(n2342) );
CLKMX2X2TS U2688 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n2342),
.Y(n712) );
CLKMX2X2TS U2689 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n2342),
.Y(n751) );
CLKMX2X2TS U2690 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n2342),
.Y(n769) );
CLKMX2X2TS U2691 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n2342),
.Y(n748) );
CLKMX2X2TS U2692 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n2342),
.Y(n730) );
CLKMX2X2TS U2693 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n2342),
.Y(n739) );
CLKMX2X2TS U2694 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n2342),
.Y(n736) );
CLKMX2X2TS U2695 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n2342),
.Y(n733) );
CLKMX2X2TS U2696 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(n2342), .Y(n601)
);
CLKMX2X2TS U2697 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n2342),
.Y(n766) );
CLKMX2X2TS U2698 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2384),
.Y(n715) );
CLKMX2X2TS U2699 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2384),
.Y(n727) );
CLKMX2X2TS U2700 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2384),
.Y(n721) );
CLKMX2X2TS U2701 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n2384), .Y(
n598) );
CLKMX2X2TS U2702 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2384), .Y(
n607) );
CLKMX2X2TS U2703 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2384),
.Y(n665) );
INVX4TS U2704 ( .A(n2393), .Y(n2343) );
CLKMX2X2TS U2705 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2343),
.Y(n667) );
CLKMX2X2TS U2706 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2343),
.Y(n595) );
CLKMX2X2TS U2707 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2343),
.Y(n662) );
CLKMX2X2TS U2708 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n2344),
.Y(n706) );
CLKMX2X2TS U2709 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2344),
.Y(n703) );
CLKMX2X2TS U2710 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n2344),
.Y(n763) );
CLKMX2X2TS U2711 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n2344),
.Y(n745) );
CLKMX2X2TS U2712 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n2344),
.Y(n757) );
CLKMX2X2TS U2713 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n2344),
.Y(n760) );
CLKMX2X2TS U2714 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n2344),
.Y(n718) );
CLKMX2X2TS U2715 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n2344),
.Y(n709) );
CLKMX2X2TS U2716 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2344),
.Y(n724) );
CLKMX2X2TS U2717 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n2344),
.Y(n742) );
CLKMX2X2TS U2718 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2345),
.Y(n604) );
CLKMX2X2TS U2719 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2345),
.Y(n677) );
CLKMX2X2TS U2720 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2345),
.Y(n697) );
CLKMX2X2TS U2721 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2345),
.Y(n687) );
CLKMX2X2TS U2722 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2345),
.Y(n672) );
CLKMX2X2TS U2723 ( .A(n1177), .B(DMP_exp_NRM_EW[1]), .S0(n2345), .Y(n692) );
CLKMX2X2TS U2724 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2345),
.Y(n682) );
AOI22X1TS U2725 ( .A0(n2745), .A1(n2347), .B0(n2346), .B1(n2345), .Y(n2860)
);
MXI2X1TS U2726 ( .A(n2349), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
CLKMX2X2TS U2727 ( .A(DMP_SHT1_EWSW[26]), .B(n1219), .S0(n2350), .Y(n686) );
CLKMX2X2TS U2728 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(n2350),
.Y(n681) );
CLKMX2X2TS U2729 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n2350),
.Y(n701) );
CLKMX2X2TS U2730 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n2350),
.Y(n671) );
CLKMX2X2TS U2731 ( .A(DMP_SHT1_EWSW[28]), .B(n1162), .S0(n2350), .Y(n676) );
CLKMX2X2TS U2732 ( .A(DMP_SHT1_EWSW[5]), .B(n1167), .S0(n2350), .Y(n755) );
CLKMX2X2TS U2733 ( .A(DMP_SHT1_EWSW[24]), .B(n955), .S0(n2350), .Y(n696) );
CLKMX2X2TS U2734 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2350), .Y(n602)
);
CLKMX2X2TS U2735 ( .A(DMP_SHT1_EWSW[6]), .B(n1223), .S0(n2352), .Y(n752) );
CLKMX2X2TS U2736 ( .A(DMP_SHT1_EWSW[12]), .B(n1164), .S0(n2352), .Y(n734) );
CLKMX2X2TS U2737 ( .A(DMP_SHT1_EWSW[10]), .B(DMP_EXP_EWSW[10]), .S0(n2352),
.Y(n740) );
CLKMX2X2TS U2738 ( .A(DMP_SHT1_EWSW[11]), .B(n1179), .S0(n2352), .Y(n737) );
CLKMX2X2TS U2739 ( .A(DMP_SHT1_EWSW[1]), .B(n949), .S0(n2352), .Y(n767) );
CLKMX2X2TS U2740 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n2352),
.Y(n731) );
CLKMX2X2TS U2741 ( .A(DMP_SHT1_EWSW[7]), .B(n1169), .S0(n2352), .Y(n749) );
CLKMX2X2TS U2742 ( .A(DmP_mant_SHT1_SW[18]), .B(n1224), .S0(n2352), .Y(n624)
);
MXI2X1TS U2743 ( .A(n2457), .B(n2361), .S0(n2384), .Y(n690) );
INVX2TS U2744 ( .A(DMP_SFG[26]), .Y(n2353) );
MXI2X1TS U2745 ( .A(n2436), .B(n2353), .S0(n2378), .Y(n684) );
INVX2TS U2746 ( .A(DMP_SFG[23]), .Y(n2354) );
MXI2X1TS U2747 ( .A(n2438), .B(n2354), .S0(n2378), .Y(n699) );
INVX2TS U2748 ( .A(DMP_SFG[30]), .Y(n2355) );
MXI2X1TS U2749 ( .A(n2432), .B(n2355), .S0(n2378), .Y(n664) );
INVX2TS U2750 ( .A(DMP_SFG[24]), .Y(n2356) );
MXI2X1TS U2751 ( .A(n2437), .B(n2356), .S0(n2378), .Y(n694) );
INVX2TS U2752 ( .A(DMP_SFG[27]), .Y(n2357) );
MXI2X1TS U2753 ( .A(n2435), .B(n2357), .S0(n2378), .Y(n679) );
INVX2TS U2754 ( .A(DMP_SFG[28]), .Y(n2358) );
MXI2X1TS U2755 ( .A(n2434), .B(n2358), .S0(n2378), .Y(n674) );
INVX2TS U2756 ( .A(DMP_SFG[29]), .Y(n2359) );
MXI2X1TS U2757 ( .A(n2433), .B(n2359), .S0(n2378), .Y(n669) );
MXI2X1TS U2758 ( .A(n2361), .B(n1181), .S0(n2382), .Y(n691) );
INVX2TS U2759 ( .A(DMP_SFG[25]), .Y(n2362) );
MXI2X1TS U2760 ( .A(n2457), .B(n2362), .S0(n2378), .Y(n689) );
INVX2TS U2761 ( .A(n2363), .Y(n2364) );
NAND2X1TS U2762 ( .A(n2365), .B(n2364), .Y(n2366) );
XNOR2X1TS U2763 ( .A(n2366), .B(n2380), .Y(n2367) );
MXI2X1TS U2764 ( .A(n2367), .B(n2542), .S0(n2351), .Y(n816) );
XNOR2X1TS U2765 ( .A(n1180), .B(n1217), .Y(n2368) );
XNOR2X1TS U2766 ( .A(n2369), .B(n2368), .Y(n2370) );
INVX2TS U2767 ( .A(DMP_SFG[22]), .Y(n2372) );
MXI2X1TS U2768 ( .A(n2447), .B(n2372), .S0(n964), .Y(n702) );
MXI2X1TS U2769 ( .A(n2510), .B(n2420), .S0(n1307), .Y(n759) );
MXI2X1TS U2770 ( .A(n2454), .B(n2524), .S0(n1307), .Y(n723) );
MXI2X1TS U2771 ( .A(n2452), .B(n2523), .S0(n1307), .Y(n717) );
MXI2X1TS U2772 ( .A(n2453), .B(n2520), .S0(n1307), .Y(n720) );
MXI2X1TS U2773 ( .A(n2455), .B(n2521), .S0(n1307), .Y(n726) );
MXI2X1TS U2774 ( .A(n2451), .B(n2518), .S0(n1307), .Y(n714) );
MXI2X1TS U2775 ( .A(n2450), .B(n2517), .S0(n980), .Y(n711) );
INVX2TS U2776 ( .A(ZERO_FLAG_SFG), .Y(n2374) );
MXI2X1TS U2777 ( .A(n2456), .B(n2374), .S0(n1329), .Y(n606) );
INVX2TS U2778 ( .A(SIGN_FLAG_SFG), .Y(n2375) );
MXI2X1TS U2779 ( .A(n2376), .B(n2375), .S0(n1329), .Y(n597) );
NOR2X1TS U2780 ( .A(n2532), .B(DmP_EXP_EWSW[23]), .Y(n2379) );
NOR2X1TS U2781 ( .A(n2380), .B(n2379), .Y(n2381) );
MXI2X1TS U2782 ( .A(n2553), .B(n2381), .S0(n2382), .Y(n817) );
NAND3X1TS U2783 ( .A(n2578), .B(n2577), .C(n2576), .Y(n2391) );
CLKMX2X2TS U2784 ( .A(SIGN_FLAG_SHT1), .B(n2391), .S0(n2382), .Y(n599) );
CLKMX2X2TS U2785 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n2382),
.Y(n725) );
CLKMX2X2TS U2786 ( .A(DMP_SHT1_EWSW[16]), .B(n1170), .S0(n2382), .Y(n722) );
CLKMX2X2TS U2787 ( .A(DMP_SHT1_EWSW[17]), .B(n956), .S0(n2382), .Y(n719) );
CLKMX2X2TS U2788 ( .A(DMP_SHT1_EWSW[19]), .B(n1176), .S0(n2382), .Y(n713) );
CLKMX2X2TS U2789 ( .A(DMP_SHT1_EWSW[18]), .B(n1165), .S0(n2382), .Y(n716) );
CLKMX2X2TS U2790 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n2382),
.Y(n728) );
CLKMX2X2TS U2791 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2388),
.Y(n746) );
CLKMX2X2TS U2792 ( .A(DMP_SHT1_EWSW[3]), .B(n1210), .S0(n2388), .Y(n761) );
AOI22X1TS U2793 ( .A0(n2387), .A1(n1330), .B0(n2385), .B1(n2384), .Y(n2781)
);
CLKMX2X2TS U2794 ( .A(DmP_mant_SHT1_SW[8]), .B(n1173), .S0(n2388), .Y(n644)
);
CLKMX2X2TS U2795 ( .A(DmP_mant_SHT1_SW[6]), .B(n1234), .S0(n2388), .Y(n648)
);
CLKMX2X2TS U2796 ( .A(DmP_mant_SHT1_SW[9]), .B(n1229), .S0(n2388), .Y(n642)
);
MXI2X1TS U2797 ( .A(n2389), .B(final_result_ieee[25]), .S0(n2779), .Y(n2914)
);
MXI2X4TS U2798 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2390), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2394) );
NAND2X8TS U2799 ( .A(n2394), .B(beg_OP), .Y(n2399) );
CLKMX2X2TS U2800 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2405), .Y(n848)
);
CLKMX2X2TS U2801 ( .A(add_subt), .B(intAS), .S0(n2405), .Y(n881) );
MXI2X1TS U2802 ( .A(n2392), .B(n2391), .S0(n2526), .Y(n2920) );
MXI2X1TS U2803 ( .A(n2526), .B(n2360), .S0(n2396), .Y(n919) );
MXI2X1TS U2804 ( .A(n2393), .B(n1734), .S0(n2396), .Y(n914) );
MXI2X1TS U2805 ( .A(n2360), .B(n2558), .S0(n2396), .Y(n918) );
MXI2X1TS U2806 ( .A(n1629), .B(n2529), .S0(n2396), .Y(n915) );
CLKINVX1TS U2807 ( .A(n2394), .Y(n2395) );
MXI2X1TS U2808 ( .A(n2395), .B(n2526), .S0(n2396), .Y(n920) );
MXI2X1TS U2809 ( .A(n2558), .B(n2427), .S0(n2396), .Y(n917) );
CLKMX2X2TS U2810 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n2405), .Y(n879) );
CLKMX2X2TS U2811 ( .A(Data_Y[1]), .B(n1240), .S0(n2405), .Y(n878) );
BUFX12TS U2812 ( .A(n2399), .Y(n2398) );
CLKMX2X2TS U2813 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n2398), .Y(n909) );
BUFX12TS U2814 ( .A(n2399), .Y(n2397) );
CLKMX2X2TS U2815 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n2397), .Y(n857)
);
CLKMX2X2TS U2816 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n2397), .Y(n913) );
CLKMX2X2TS U2817 ( .A(Data_X[5]), .B(n1004), .S0(n2398), .Y(n908) );
BUFX12TS U2818 ( .A(n2399), .Y(n2401) );
CLKMX2X2TS U2819 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n2401), .Y(n858)
);
CLKMX2X2TS U2820 ( .A(Data_X[6]), .B(intDX_EWSW[6]), .S0(n2398), .Y(n907) );
CLKMX2X2TS U2821 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2397), .Y(n851)
);
BUFX12TS U2822 ( .A(n2399), .Y(n2402) );
CLKMX2X2TS U2823 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n2402), .Y(n874) );
CLKMX2X2TS U2824 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2397), .Y(n852)
);
CLKMX2X2TS U2825 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n2397), .Y(n850)
);
CLKMX2X2TS U2826 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n2401), .Y(n859)
);
CLKMX2X2TS U2827 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n2397), .Y(n856)
);
BUFX12TS U2828 ( .A(n2399), .Y(n2403) );
CLKMX2X2TS U2829 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n2403), .Y(n849)
);
CLKMX2X2TS U2830 ( .A(Data_X[8]), .B(n926), .S0(n2398), .Y(n905) );
CLKMX2X2TS U2831 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n2401), .Y(n860)
);
CLKMX2X2TS U2832 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n2398), .Y(n904) );
CLKMX2X2TS U2833 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n2401), .Y(n861)
);
CLKMX2X2TS U2834 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2397), .Y(n855)
);
CLKMX2X2TS U2835 ( .A(Data_X[1]), .B(intDX_EWSW[1]), .S0(n2397), .Y(n912) );
CLKMX2X2TS U2836 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n2397), .Y(n853)
);
CLKMX2X2TS U2837 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n2398), .Y(n911) );
CLKMX2X2TS U2838 ( .A(Data_X[10]), .B(n995), .S0(n2398), .Y(n903) );
CLKMX2X2TS U2839 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2397), .Y(n854)
);
CLKMX2X2TS U2840 ( .A(Data_X[11]), .B(n1003), .S0(n2398), .Y(n902) );
BUFX12TS U2841 ( .A(n2399), .Y(n2400) );
CLKMX2X2TS U2842 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n2400), .Y(n901)
);
CLKMX2X2TS U2843 ( .A(Data_X[13]), .B(n999), .S0(n2400), .Y(n900) );
CLKMX2X2TS U2844 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n2400), .Y(n899)
);
CLKMX2X2TS U2845 ( .A(Data_X[15]), .B(n998), .S0(n2400), .Y(n898) );
CLKMX2X2TS U2846 ( .A(Data_Y[6]), .B(n1254), .S0(n2402), .Y(n873) );
CLKMX2X2TS U2847 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n2400), .Y(n897)
);
CLKMX2X2TS U2848 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n2400), .Y(n895)
);
CLKMX2X2TS U2849 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n2400), .Y(n894)
);
CLKMX2X2TS U2850 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n2401), .Y(n862)
);
CLKMX2X2TS U2851 ( .A(Data_X[20]), .B(n1071), .S0(n2400), .Y(n893) );
CLKMX2X2TS U2852 ( .A(Data_Y[14]), .B(n1251), .S0(n2401), .Y(n865) );
CLKMX2X2TS U2853 ( .A(Data_X[21]), .B(intDX_EWSW[21]), .S0(n2400), .Y(n892)
);
CLKMX2X2TS U2854 ( .A(Data_X[22]), .B(n1301), .S0(n2403), .Y(n891) );
CLKMX2X2TS U2855 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n2403), .Y(n889)
);
CLKMX2X2TS U2856 ( .A(Data_X[25]), .B(n1244), .S0(n2403), .Y(n888) );
CLKMX2X2TS U2857 ( .A(Data_Y[12]), .B(n1249), .S0(n2401), .Y(n867) );
CLKMX2X2TS U2858 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n2401), .Y(n863)
);
CLKMX2X2TS U2859 ( .A(Data_X[26]), .B(n1299), .S0(n2403), .Y(n887) );
CLKMX2X2TS U2860 ( .A(Data_Y[9]), .B(intDY_EWSW[9]), .S0(n2402), .Y(n870) );
CLKMX2X2TS U2861 ( .A(Data_Y[15]), .B(n1258), .S0(n2401), .Y(n864) );
CLKMX2X2TS U2862 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n2403), .Y(n884)
);
CLKMX2X2TS U2863 ( .A(Data_Y[8]), .B(n1182), .S0(n2402), .Y(n871) );
CLKMX2X2TS U2864 ( .A(Data_Y[2]), .B(n1260), .S0(n2402), .Y(n877) );
CLKMX2X2TS U2865 ( .A(Data_Y[7]), .B(n940), .S0(n2402), .Y(n872) );
CLKMX2X2TS U2866 ( .A(Data_Y[13]), .B(n1256), .S0(n2401), .Y(n866) );
CLKMX2X2TS U2867 ( .A(Data_Y[4]), .B(n1262), .S0(n2402), .Y(n875) );
CLKMX2X2TS U2868 ( .A(Data_X[27]), .B(n1246), .S0(n2403), .Y(n886) );
CLKMX2X2TS U2869 ( .A(Data_Y[10]), .B(n951), .S0(n2402), .Y(n869) );
CLKMX2X2TS U2870 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n2403), .Y(n885)
);
CLKMX2X2TS U2871 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n2403), .Y(n883)
);
MXI2X1TS U2872 ( .A(n2404), .B(final_result_ieee[27]), .S0(n2779), .Y(n2916)
);
CLKMX2X2TS U2873 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2405), .Y(n882)
);
CLKMX2X2TS U2874 ( .A(DMP_SHT1_EWSW[2]), .B(DMP_EXP_EWSW[2]), .S0(n2406),
.Y(n764) );
CLKMX2X2TS U2875 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n2406),
.Y(n770) );
CLKMX2X2TS U2876 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2406), .Y(
n608) );
CLKMX2X2TS U2877 ( .A(DMP_SHT1_EWSW[4]), .B(n1295), .S0(n2406), .Y(n758) );
CLKMX2X2TS U2878 ( .A(DMP_SHT1_EWSW[9]), .B(n1242), .S0(n2407), .Y(n743) );
CLKMX2X2TS U2879 ( .A(DMP_SHT1_EWSW[22]), .B(n1166), .S0(n2407), .Y(n704) );
CLKMX2X2TS U2880 ( .A(DMP_SHT1_EWSW[21]), .B(DMP_EXP_EWSW[21]), .S0(n2407),
.Y(n707) );
CLKMX2X2TS U2881 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n2407),
.Y(n710) );
CLKMX2X2TS U2882 ( .A(DmP_mant_SHT1_SW[21]), .B(n1228), .S0(n2406), .Y(n618)
);
CLKMX2X2TS U2883 ( .A(DmP_mant_SHT1_SW[0]), .B(n1174), .S0(n2407), .Y(n660)
);
CLKMX2X2TS U2884 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n2407),
.Y(n656) );
CLKMX2X2TS U2885 ( .A(DmP_mant_SHT1_SW[10]), .B(n1208), .S0(n2406), .Y(n640)
);
CLKMX2X3TS U2886 ( .A(DmP_mant_SHT1_SW[16]), .B(n1213), .S0(n2406), .Y(n628)
);
CLKMX2X2TS U2887 ( .A(DmP_mant_SHT1_SW[1]), .B(n950), .S0(n2407), .Y(n658)
);
CLKMX2X2TS U2888 ( .A(DmP_mant_SHT1_SW[14]), .B(n1216), .S0(n2406), .Y(n632)
);
CLKMX2X2TS U2889 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n2406), .Y(n616) );
CLKMX2X3TS U2890 ( .A(DmP_mant_SHT1_SW[20]), .B(n1296), .S0(n2406), .Y(n620)
);
CLKMX2X2TS U2891 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n2407), .Y(n630) );
MXI2X1TS U2892 ( .A(n2408), .B(final_result_ieee[28]), .S0(n2779), .Y(n2917)
);
MXI2X1TS U2893 ( .A(n971), .B(final_result_ieee[29]), .S0(n2779), .Y(n2918)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_ETAIIN16Q4_syn.sdf");
endmodule
|
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - Clock divider
Description: This module accepts a 50MHz clock
signal and outputs two clocks: one with a 2 sec
period and the other with a 1kHz frequency.
================================================*/
`timescale 100 ns / 1 ns
module clock_divider(clk, ar, x, y);
/*======================================
Input/Output Declaration
======================================*/
parameter width_x = 26;
parameter halfperiod_x = 26'd50000000;
parameter width_y = 15;
parameter halfperiod_y = 15'd25000;
/*======================================
Input/Output Declaration
======================================*/
input clk, ar;
output reg x, y; // Output clocks
/*======================================
Internal wires/registers
======================================*/
reg [width_x-1:0] ctr_x; // Need a 26 bit counter reg
reg [width_y-1:0] ctr_y;
/*======================================
Synchronous Logic
======================================*/
always @ (posedge clk or negedge ar)
begin
if(~ar) // If reset has negedge down to level 0,
begin
ctr_x <= 0; // Put ctr and output in known state
ctr_y <= 0;
x <= 0;
y <= 0;
end
else
begin
if(ctr_x>=halfperiod_x-1) // If the counter hits 25M
begin
x <= ~x; // Flip output
ctr_x <= 0; // Reset ctr
end
else begin
ctr_x <= ctr_x + 1; // Inc ctr
end
if(ctr_y>=halfperiod_y-1)
begin
y <= ~y;
ctr_y <= 0;
end
else begin
ctr_y <= ctr_y + 1;
end
end
end
endmodule |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// $Id: $
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2014 Dmitry Murzinov ([email protected]) //
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
module gost_28147_89 (clk, rst, mode, load, done, key, pdata, cdata);
input clk; // Input clock signal for synchronous design
input rst; // Syncronous Reset input
input mode; // 0 - encrypt, 1 - decrypt
input load; // load plain text and start cipher cycles
output done; // cipher text ready for output read
//input kload; // load cipher key
input [255:0] key; // cipher key input
input [63:0] pdata; // plain text input
output [63:0] cdata; // cipher text output
//`include "gost-sbox.vh"
`include "sbox.vh"
reg [4:0] i; // cipher cycles counter: 0..31;
always @(posedge clk)
if(rst || load)
i <= 5'h0;
else //if(~&i)
i <= i + 1;
//reg run; //running cipher cycles flag
wire [2:0] enc_index = (&i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for encrypt
wire [2:0] dec_index = (|i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for decrypt
wire [2:0] kindex = mode ? dec_index : enc_index; // cipher key index
wire [31:0] K [0:7]; // cipher key storage
assign {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]} = key;
reg [31:0] b, a; // MSB, LSB of input data
wire [31:0] state_addmod32 = a + K[kindex]; // Adding by module 32
wire [31:0] state_sbox = `Sbox(state_addmod32); // S-box replacing
wire [31:0] state_shift11 = {state_sbox[20:0],state_sbox[31:21]}; // <<11
always @(posedge clk)
if(rst)
{b,a} <= {64{1'b0}};
else if(load)
{b,a} <= pdata;
else /*if(~&i)*/ begin
a <= b ^ state_shift11;
b <= a;
end
reg r_done;
always @(posedge clk)
if(rst)
r_done <= 1'b0;
else
r_done <= &i;
assign done = r_done; //ready flag for output data
assign cdata = {a,b};
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 08:57:14 2017
// Host : Shaun running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_stub.v
// Design : bram_4096
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_4096(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Down-Sizer
// Down-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data, Write Response and Read Data Down-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Down-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// downsizer
// a_downsizer
// axic_fifo
// fifo_gen
// fifo_coregen
// w_downsizer
// b_downsizer
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_7_axi_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_MAX_SPLIT_BEATS = 256
// Max burst length after transaction splitting.
// Range: 0 (no splitting), 1 (convert to singles), 16, 256.
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_S_AXI_DATA_WIDTH / C_M_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam integer P_AXI_ADDR_WIDTH = (C_AXI_ADDR_WIDTH < 13) ? 13 : C_AXI_ADDR_WIDTH;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_araddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i;
assign s_axi_awaddr_i = s_axi_awaddr;
assign s_axi_araddr_i = s_axi_araddr;
assign m_axi_awaddr = m_axi_awaddr_i[0 +: C_AXI_ADDR_WIDTH] ;
assign m_axi_araddr = m_axi_araddr_i[0 +: C_AXI_ADDR_WIDTH];
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_MAX_SPLIT_BEATS = (C_MAX_SPLIT_BEATS >= 16) ? C_MAX_SPLIT_BEATS :
(C_AXI_PROTOCOL == P_AXI4) ? 256 : 16;
localparam integer P_MAX_SPLIT_BEATS_LOG = log2(P_MAX_SPLIT_BEATS);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_split;
wire wr_cmd_mirror;
wire wr_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] wr_cmd_step;
wire [3-1:0] wr_cmd_size;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_b_valid;
wire wr_cmd_b_split;
wire [8-1:0] wr_cmd_b_repeat ;
wire wr_cmd_b_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_b_id;
wire [8-1:0] s_axi_awlen_i;
wire [2-1:0] s_axi_awlock_i;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_awlen[3:0]}: s_axi_awlen;
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_7_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (0),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (W)
.cmd_valid (wr_cmd_valid),
.cmd_split (wr_cmd_split),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Command Interface (B)
.cmd_b_valid (wr_cmd_b_valid),
.cmd_b_split (wr_cmd_b_split),
.cmd_b_repeat (wr_cmd_b_repeat),
.cmd_b_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_awid),
.S_AXI_AADDR (s_axi_awaddr_i),
.S_AXI_ALEN (s_axi_awlen_i),
.S_AXI_ASIZE (s_axi_awsize),
.S_AXI_ABURST (s_axi_awburst),
.S_AXI_ALOCK (s_axi_awlock_i),
.S_AXI_ACACHE (s_axi_awcache),
.S_AXI_APROT (s_axi_awprot),
.S_AXI_AREGION (s_axi_awregion),
.S_AXI_AQOS (s_axi_awqos),
.S_AXI_AVALID (s_axi_awvalid),
.S_AXI_AREADY (s_axi_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i),
.M_AXI_ALEN (m_axi_awlen),
.M_AXI_ASIZE (m_axi_awsize),
.M_AXI_ABURST (m_axi_awburst),
.M_AXI_ALOCK (m_axi_awlock),
.M_AXI_ACACHE (m_axi_awcache),
.M_AXI_APROT (m_axi_awprot),
.M_AXI_AREGION (m_axi_awregion),
.M_AXI_AQOS (m_axi_awqos),
.M_AXI_AVALID (m_axi_awvalid),
.M_AXI_AREADY (m_axi_awready)
);
// Write Data channel.
axi_dwidth_converter_v2_1_7_w_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
// Write Response channel.
if ( P_MAX_SPLIT_BEATS > 0 ) begin : USE_SPLIT
axi_dwidth_converter_v2_1_7_b_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH)
) write_resp_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_b_valid),
.cmd_split (wr_cmd_b_split),
.cmd_repeat (wr_cmd_b_repeat),
.cmd_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Response Ports
.S_AXI_BID (s_axi_bid),
.S_AXI_BRESP (s_axi_bresp),
.S_AXI_BVALID (s_axi_bvalid),
.S_AXI_BREADY (s_axi_bready),
// Master Interface Write Response Ports
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready)
);
end else begin : NO_SPLIT
assign s_axi_bid = wr_cmd_b_id;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
end
end else begin : NO_WRITE
// Slave Interface Write Address Ports
assign s_axi_awready = 1'b0;
// Slave Interface Write Data Ports
assign s_axi_wready = 1'b0;
// Slave Interface Write Response Ports
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
// Master Interface Write Address Port
assign m_axi_awaddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
// Master Interface Write Data Ports
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
// assign m_axi_wuser = {C_AXI_WUSER_WIDTH{1'b0}};
assign m_axi_wvalid = 1'b0;
// Master Interface Write Response Ports
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_split;
wire rd_cmd_mirror;
wire rd_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] rd_cmd_step;
wire [3-1:0] rd_cmd_size;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [8-1:0] s_axi_arlen_i;
wire [2-1:0] s_axi_arlock_i;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_arlen[3:0]}: s_axi_arlen;
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_7_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (1),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (R)
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Command Interface (B)
.cmd_b_valid (),
.cmd_b_split (),
.cmd_b_repeat (),
.cmd_b_ready (1'b0),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_arid),
.S_AXI_AADDR (s_axi_araddr_i),
.S_AXI_ALEN (s_axi_arlen_i),
.S_AXI_ASIZE (s_axi_arsize),
.S_AXI_ABURST (s_axi_arburst),
.S_AXI_ALOCK (s_axi_arlock_i),
.S_AXI_ACACHE (s_axi_arcache),
.S_AXI_APROT (s_axi_arprot),
.S_AXI_AREGION (s_axi_arregion),
.S_AXI_AQOS (s_axi_arqos),
.S_AXI_AVALID (s_axi_arvalid),
.S_AXI_AREADY (s_axi_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i),
.M_AXI_ALEN (m_axi_arlen),
.M_AXI_ASIZE (m_axi_arsize),
.M_AXI_ABURST (m_axi_arburst),
.M_AXI_ALOCK (m_axi_arlock),
.M_AXI_ACACHE (m_axi_arcache),
.M_AXI_APROT (m_axi_arprot),
.M_AXI_AREGION (m_axi_arregion),
.M_AXI_AQOS (m_axi_arqos),
.M_AXI_AVALID (m_axi_arvalid),
.M_AXI_AREADY (m_axi_arready)
);
// Read Data channel.
axi_dwidth_converter_v2_1_7_r_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end else begin : NO_READ
// Slave Interface Read Address Ports
assign s_axi_arready = 1'b0;
// Slave Interface Read Data Ports
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
// assign s_axi_ruser = {C_AXI_RUSER_WIDTH{1'b0}};
assign s_axi_rvalid = 1'b0;
// Master Interface Read Address Port
assign m_axi_araddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
// Master Interface Read Data Ports
assign m_axi_rready = 1'b0;
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
module m;
bit [0:0] a, b, c;
covergroup g;
cp_ab: coverpoint {a,b} {
bins one = {1};
bins two = {2};
}
cp_ab_if_c: coverpoint {a,b} iff c {
bins one = {1};
bins two = {2};
}
cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
bins one = {1};
bins two = {2};
}
cp_a_if_bc: coverpoint {a,b} iff {b,c} {
bins one = {1};
bins two = {2};
}
cp_a_slice : coverpoint a[0] {
bins one = {1};
bins two = {2};
}
cp_a_slice_if_b : coverpoint a[0] iff b {
bins one = {1};
bins two = {2};
}
cp_a_if_b_slice : coverpoint a iff b[0] {
bins one = {1};
bins two = {2};
}
cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
bins one = {1};
bins two = {2};
}
endgroup
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_1_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_1_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_1_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_1_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// acl_staging_reg.v
//
// Module to implement a staging register. Used to pipeline stall signals.
//
module acl_staging_reg
(
clk, reset, i_data, i_valid, o_stall, o_data, o_valid, i_stall
);
/*************
* Parameters *
*************/
parameter WIDTH=32;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
input [WIDTH-1:0] i_data;
input i_valid;
output o_stall;
// Downstream interface
output [WIDTH-1:0] o_data;
output o_valid;
input i_stall;
/***************
* Architecture *
***************/
reg [WIDTH-1:0] r_data;
reg r_valid;
// Upstream
assign o_stall = r_valid;
// Downstream
assign o_data = (r_valid) ? r_data : i_data;
assign o_valid = (r_valid) ? r_valid : i_valid;
// Storage reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_valid <= 1'b0;
r_data <= 'x; // don't need to reset
end
else
begin
if (~r_valid) r_data <= i_data;
r_valid <= i_stall && (r_valid || i_valid);
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
module ad_iqcor (
// data interface
clk,
valid,
data_i,
data_q,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter IQSEL = 0;
// data interface
input clk;
input valid;
input [15:0] data_i;
input [15:0] data_q;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg p2_valid = 'd0;
reg p2_sign_i = 'd0;
reg p2_sign_q = 'd0;
reg [14:0] p2_magn_i = 'd0;
reg [14:0] p2_magn_q = 'd0;
reg p3_valid = 'd0;
reg [15:0] p3_data_i = 'd0;
reg [15:0] p3_data_q = 'd0;
reg p4_valid = 'd0;
reg [15:0] p4_data = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [15:0] p2_data_i_s;
wire [15:0] p2_data_q_s;
wire p3_valid_s;
wire [31:0] p3_magn_i_s;
wire p3_sign_i_s;
wire [31:0] p3_magn_q_s;
wire p3_sign_q_s;
wire [15:0] p3_data_2s_i_p_s;
wire [15:0] p3_data_2s_q_p_s;
wire [15:0] p3_data_2s_i_n_s;
wire [15:0] p3_data_2s_q_n_s;
// apply offsets first
always @(posedge clk) begin
p1_valid <= valid;
p1_data_i <= data_i;
p1_data_q <= data_q;
end
// convert to sign-magnitude
assign p2_data_i_s = ~p1_data_i + 1'b1;
assign p2_data_q_s = ~p1_data_q + 1'b1;
always @(posedge clk) begin
p2_valid <= p1_valid;
p2_sign_i <= p1_data_i[15] ^ iqcor_coeff_1[15];
p2_sign_q <= p1_data_q[15] ^ iqcor_coeff_2[15];
p2_magn_i <= (p1_data_i[15] == 1'b1) ? p2_data_i_s[14:0] : p1_data_i[14:0];
p2_magn_q <= (p1_data_q[15] == 1'b1) ? p2_data_q_s[14:0] : p1_data_q[14:0];
end
// scaling functions - i
mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16_i (
.clk (clk),
.data_a ({1'b0, p2_magn_i}),
.data_b ({1'b0, iqcor_coeff_1[14:0]}),
.data_p (p3_magn_i_s),
.ddata_in ({p2_valid, p2_sign_i}),
.ddata_out ({p3_valid_s, p3_sign_i_s}));
// scaling functions - q
mul_u16 #(.DELAY_DATA_WIDTH(1)) i_mul_u16_q (
.clk (clk),
.data_a ({1'b0, p2_magn_q}),
.data_b ({1'b0, iqcor_coeff_2[14:0]}),
.data_p (p3_magn_q_s),
.ddata_in (p2_sign_q),
.ddata_out (p3_sign_q_s));
// convert to 2s-complements
assign p3_data_2s_i_p_s = {1'b0, p3_magn_i_s[28:14]};
assign p3_data_2s_q_p_s = {1'b0, p3_magn_q_s[28:14]};
assign p3_data_2s_i_n_s = ~p3_data_2s_i_p_s + 1'b1;
assign p3_data_2s_q_n_s = ~p3_data_2s_q_p_s + 1'b1;
always @(posedge clk) begin
p3_valid <= p3_valid_s;
p3_data_i <= (p3_sign_i_s == 1'b1) ? p3_data_2s_i_n_s : p3_data_2s_i_p_s;
p3_data_q <= (p3_sign_q_s == 1'b1) ? p3_data_2s_q_n_s : p3_data_2s_q_p_s;
end
// corrected output is sum of two
always @(posedge clk) begin
p4_valid <= p3_valid;
p4_data <= p3_data_i + p3_data_q;
end
// output registers
always @(posedge clk) begin
if (iqcor_enable == 1'b1) begin
valid_out <= p4_valid;
data_out <= p4_data;
end else if (IQSEL == 1) begin
valid_out <= valid;
data_out <= data_q;
end else begin
valid_out <= valid;
data_out <= data_i;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
v95 v95 ();
v01 v01 ();
v05 v05 ();
s05 s05 ();
s09 s09 ();
a23 a23 ();
s12 s12 ();
initial begin
$finish;
end
endmodule
`begin_keywords "1364-1995"
module v95;
integer signed; initial signed = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001"
module v01;
integer bit; initial bit = 1;
endmodule
`end_keywords
`begin_keywords "1364-2005"
module v05;
integer final; initial final = 1;
endmodule
`end_keywords
`begin_keywords "1800-2005"
module s05;
integer global; initial global = 1;
endmodule
`end_keywords
`begin_keywords "1800-2009"
module s09;
integer soft; initial soft = 1;
endmodule
`end_keywords
`begin_keywords "1800-2012"
module s12;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "VAMS-2.3"
module a23;
real foo; initial foo = sqrt(2.0);
endmodule
`end_keywords
|
module check (input unsigned [22:0] a, b,
input unsigned [45:0] c);
wire unsigned [45:0] int_AB;
assign int_AB = a * b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23'h7fffff;
#1 B = 23'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [45:0] r;
stimulus stim (.A(a), .B(b));
umul23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 2.5
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((done == 1) & (src_response_valid == 0)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:0, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) & (write_complete == 1) & (length_counter < bytes_to_transfer); // packet transfer and the length counter is about to roll over so stop transfering
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [1:0] bus_s [7:0];
wire [15:0] bus_a [7:0];
wire [31:0] bus_d [7:0];
wire [7:0] pll;
wire [31:0] outx [7:0];
wire [31:0] dirx [7:0];
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
genvar i;
generate
for (i=0; i<8; i=i+1)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_bypass_reg2(clock, resetn, i_settings,
i_register_settings,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall);
parameter DATA_WIDTH = 32;
input clock;
input resetn;
input [1:0] i_settings;
input [DATA_WIDTH-1:0] i_register_settings;
input [DATA_WIDTH-1:0] i_dataa, i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataouta, o_dataoutb;
output o_dataouta_valid, o_dataoutb_valid;
input i_dataouta_stall, i_dataoutb_stall;
assign o_dataouta = i_settings[0] ? i_register_settings : i_dataa;
assign o_dataoutb = i_settings[1] ? i_register_settings : i_datab;
assign o_dataouta_valid = i_dataa_valid;
assign o_dataoutb_valid = i_datab_valid;
assign o_dataa_stall = i_dataouta_stall;
assign o_datab_stall = i_dataoutb_stall;
endmodule
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
//-- The module can be configured with these parameters (defaults given in braces):
//--
//-- outputwidth(32) : width of output register
//-- size(31) : Size of counter, set from 5 to outputwidth-1. (overflow bit is extra, so max (outputwidth-1) Bit)
//-- clip_count(1) : sets if the count signal is to be clipped
//-- clip_reset(1 : sets if the reset signal is to be clipped
//--
//-- !!! IMPORTANT !!! Include slimfast_multioption_counter.ucf
module slimfast_multioption_counter (countClock,
count,
reset,
countout);
parameter clip_count = 1;
parameter clip_reset = 1;
parameter size = 31;
parameter outputwidth = 32;
input wire countClock;
input wire count;
input wire reset;
output wire [outputwidth-1:0] countout;
wire [size-3:0] highbits_this;
wire [size-3:0] highbits_next;
//-- Counter
slimfast_multioption_counter_core #(.clip_count(clip_count),.clip_reset(clip_reset),.size(size),.outputwidth(outputwidth)) counter(
.countClock(countClock),
.count(count),
.reset(reset),
.highbits_this(highbits_this),
.highbits_next(highbits_next),
.countout(countout)
);
//-- pure combinatorial +1 operation (multi cycle path, this may take up to 40ns without breaking the counter)
assign highbits_next = highbits_this + 1;
endmodule
module slimfast_multioption_counter_core (countClock,
count,
reset,
highbits_this,
highbits_next,
countout);
parameter clip_count = 1;
parameter clip_reset = 1;
parameter size = 31;
parameter outputwidth = 32;
input wire countClock;
input wire count;
input wire reset;
input wire [size-3:0] highbits_next;
output wire [size-3:0] highbits_this;
output wire [outputwidth-1:0] countout;
wire final_count;
wire final_reset;
reg [2:0] fast_counts = 3'b0;
(* KEEP = "true" *) reg [size-3:0] SFC_slow_counts = 'b0; //SFC_ prefix to make this name unique
wire [size-3:0] slow_counts_next;
//-- if an if-statement compares a value to 1 (not 1'b1), it is a generate-if
generate
//-- this is pure combinatorial
//-- after change of SFC_slow_counts, the update of slow_counts_next is allowed to take
//-- 16clk cycles of countClock
assign highbits_this = SFC_slow_counts;
assign slow_counts_next[size-4:0] = highbits_next[size-4:0];
//the overflow bit is counted like all the other bits, but it cannot fall back to zero
assign slow_counts_next[size-3] = highbits_next[size-3] || highbits_this[size-3];
if (clip_count == 0) assign final_count = count; else
if (clip_count == 1)
begin
wire clipped_count;
signal_clipper countclip ( .sig(count), .CLK(countClock), .clipped_sig(clipped_count));
assign final_count = clipped_count;
end else begin // I added this, so that one could switch from "clipped" to "not clipped" without changing the number of flip flop stages
reg piped_count;
always@(posedge countClock)
begin
piped_count <= count;
end
assign final_count = piped_count;
end
if (clip_reset == 0) assign final_reset = reset; else
begin
wire clipped_reset;
signal_clipper resetclip ( .sig(reset), .CLK(countClock), .clipped_sig(clipped_reset));
assign final_reset = clipped_reset;
end
always@(posedge countClock)
begin
if (final_reset == 1'b1)
begin
fast_counts <= 0;
SFC_slow_counts <= 0;
end else begin
//-- uses overflow as CE, valid only one clock cycle
if (final_count == 1'b1 && fast_counts == 3'b111) begin
SFC_slow_counts <= slow_counts_next;
end
//-- uses final_count as CE
if (final_count == 1'b1) fast_counts <= fast_counts + 1'b1;
end
end
endgenerate
assign countout[outputwidth-1] = SFC_slow_counts[size-3];
assign countout[outputwidth-2:0] = {'b0,SFC_slow_counts[size-4:0],fast_counts};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
/*
* Copyright (c) 2002 Tom Verbeure
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [13:0] myReg14;
reg [15:0] myReg16;
initial begin
$display("============================ myReg14 = 33*256+65");
myReg14 = 33*256 + 65;
$display(">|!A|");
$display("*|%s|", myReg14);
$display(">|!|");
$display("*|%s|", myReg14[13:8]);
$display("============================ myReg16 = 33*512+65*2");
myReg16 = 33*512 + 65*2;
$display(">|!A|");
$display("*|%s|", myReg16[14:1]);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 512 words x 128 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module xs6_sram_1024x128_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
parameter SRAM4_INIT_0 = 256'h0,
parameter SRAM4_INIT_1 = 256'h0,
parameter SRAM4_INIT_2 = 256'h0,
parameter SRAM4_INIT_3 = 256'h0,
parameter SRAM4_INIT_4 = 256'h0,
parameter SRAM4_INIT_5 = 256'h0,
parameter SRAM4_INIT_6 = 256'h0,
parameter SRAM4_INIT_7 = 256'h0,
parameter SRAM4_INIT_8 = 256'h0,
parameter SRAM4_INIT_9 = 256'h0,
parameter SRAM4_INIT_10 = 256'h0,
parameter SRAM4_INIT_11 = 256'h0,
parameter SRAM4_INIT_12 = 256'h0,
parameter SRAM4_INIT_13 = 256'h0,
parameter SRAM4_INIT_14 = 256'h0,
parameter SRAM4_INIT_15 = 256'h0,
parameter SRAM4_INIT_16 = 256'h0,
parameter SRAM4_INIT_17 = 256'h0,
parameter SRAM4_INIT_18 = 256'h0,
parameter SRAM4_INIT_19 = 256'h0,
parameter SRAM4_INIT_20 = 256'h0,
parameter SRAM4_INIT_21 = 256'h0,
parameter SRAM4_INIT_22 = 256'h0,
parameter SRAM4_INIT_23 = 256'h0,
parameter SRAM4_INIT_24 = 256'h0,
parameter SRAM4_INIT_25 = 256'h0,
parameter SRAM4_INIT_26 = 256'h0,
parameter SRAM4_INIT_27 = 256'h0,
parameter SRAM4_INIT_28 = 256'h0,
parameter SRAM4_INIT_29 = 256'h0,
parameter SRAM4_INIT_30 = 256'h0,
parameter SRAM4_INIT_31 = 256'h0,
parameter SRAM4_INIT_32 = 256'h0,
parameter SRAM4_INIT_33 = 256'h0,
parameter SRAM4_INIT_34 = 256'h0,
parameter SRAM4_INIT_35 = 256'h0,
parameter SRAM4_INIT_36 = 256'h0,
parameter SRAM4_INIT_37 = 256'h0,
parameter SRAM4_INIT_38 = 256'h0,
parameter SRAM4_INIT_39 = 256'h0,
parameter SRAM4_INIT_40 = 256'h0,
parameter SRAM4_INIT_41 = 256'h0,
parameter SRAM4_INIT_42 = 256'h0,
parameter SRAM4_INIT_43 = 256'h0,
parameter SRAM4_INIT_44 = 256'h0,
parameter SRAM4_INIT_45 = 256'h0,
parameter SRAM4_INIT_46 = 256'h0,
parameter SRAM4_INIT_47 = 256'h0,
parameter SRAM4_INIT_48 = 256'h0,
parameter SRAM4_INIT_49 = 256'h0,
parameter SRAM4_INIT_50 = 256'h0,
parameter SRAM4_INIT_51 = 256'h0,
parameter SRAM4_INIT_52 = 256'h0,
parameter SRAM4_INIT_53 = 256'h0,
parameter SRAM4_INIT_54 = 256'h0,
parameter SRAM4_INIT_55 = 256'h0,
parameter SRAM4_INIT_56 = 256'h0,
parameter SRAM4_INIT_57 = 256'h0,
parameter SRAM4_INIT_58 = 256'h0,
parameter SRAM4_INIT_59 = 256'h0,
parameter SRAM4_INIT_60 = 256'h0,
parameter SRAM4_INIT_61 = 256'h0,
parameter SRAM4_INIT_62 = 256'h0,
parameter SRAM4_INIT_63 = 256'h0,
parameter SRAM5_INIT_0 = 256'h0,
parameter SRAM5_INIT_1 = 256'h0,
parameter SRAM5_INIT_2 = 256'h0,
parameter SRAM5_INIT_3 = 256'h0,
parameter SRAM5_INIT_4 = 256'h0,
parameter SRAM5_INIT_5 = 256'h0,
parameter SRAM5_INIT_6 = 256'h0,
parameter SRAM5_INIT_7 = 256'h0,
parameter SRAM5_INIT_8 = 256'h0,
parameter SRAM5_INIT_9 = 256'h0,
parameter SRAM5_INIT_10 = 256'h0,
parameter SRAM5_INIT_11 = 256'h0,
parameter SRAM5_INIT_12 = 256'h0,
parameter SRAM5_INIT_13 = 256'h0,
parameter SRAM5_INIT_14 = 256'h0,
parameter SRAM5_INIT_15 = 256'h0,
parameter SRAM5_INIT_16 = 256'h0,
parameter SRAM5_INIT_17 = 256'h0,
parameter SRAM5_INIT_18 = 256'h0,
parameter SRAM5_INIT_19 = 256'h0,
parameter SRAM5_INIT_20 = 256'h0,
parameter SRAM5_INIT_21 = 256'h0,
parameter SRAM5_INIT_22 = 256'h0,
parameter SRAM5_INIT_23 = 256'h0,
parameter SRAM5_INIT_24 = 256'h0,
parameter SRAM5_INIT_25 = 256'h0,
parameter SRAM5_INIT_26 = 256'h0,
parameter SRAM5_INIT_27 = 256'h0,
parameter SRAM5_INIT_28 = 256'h0,
parameter SRAM5_INIT_29 = 256'h0,
parameter SRAM5_INIT_30 = 256'h0,
parameter SRAM5_INIT_31 = 256'h0,
parameter SRAM5_INIT_32 = 256'h0,
parameter SRAM5_INIT_33 = 256'h0,
parameter SRAM5_INIT_34 = 256'h0,
parameter SRAM5_INIT_35 = 256'h0,
parameter SRAM5_INIT_36 = 256'h0,
parameter SRAM5_INIT_37 = 256'h0,
parameter SRAM5_INIT_38 = 256'h0,
parameter SRAM5_INIT_39 = 256'h0,
parameter SRAM5_INIT_40 = 256'h0,
parameter SRAM5_INIT_41 = 256'h0,
parameter SRAM5_INIT_42 = 256'h0,
parameter SRAM5_INIT_43 = 256'h0,
parameter SRAM5_INIT_44 = 256'h0,
parameter SRAM5_INIT_45 = 256'h0,
parameter SRAM5_INIT_46 = 256'h0,
parameter SRAM5_INIT_47 = 256'h0,
parameter SRAM5_INIT_48 = 256'h0,
parameter SRAM5_INIT_49 = 256'h0,
parameter SRAM5_INIT_50 = 256'h0,
parameter SRAM5_INIT_51 = 256'h0,
parameter SRAM5_INIT_52 = 256'h0,
parameter SRAM5_INIT_53 = 256'h0,
parameter SRAM5_INIT_54 = 256'h0,
parameter SRAM5_INIT_55 = 256'h0,
parameter SRAM5_INIT_56 = 256'h0,
parameter SRAM5_INIT_57 = 256'h0,
parameter SRAM5_INIT_58 = 256'h0,
parameter SRAM5_INIT_59 = 256'h0,
parameter SRAM5_INIT_60 = 256'h0,
parameter SRAM5_INIT_61 = 256'h0,
parameter SRAM5_INIT_62 = 256'h0,
parameter SRAM5_INIT_63 = 256'h0,
parameter SRAM6_INIT_0 = 256'h0,
parameter SRAM6_INIT_1 = 256'h0,
parameter SRAM6_INIT_2 = 256'h0,
parameter SRAM6_INIT_3 = 256'h0,
parameter SRAM6_INIT_4 = 256'h0,
parameter SRAM6_INIT_5 = 256'h0,
parameter SRAM6_INIT_6 = 256'h0,
parameter SRAM6_INIT_7 = 256'h0,
parameter SRAM6_INIT_8 = 256'h0,
parameter SRAM6_INIT_9 = 256'h0,
parameter SRAM6_INIT_10 = 256'h0,
parameter SRAM6_INIT_11 = 256'h0,
parameter SRAM6_INIT_12 = 256'h0,
parameter SRAM6_INIT_13 = 256'h0,
parameter SRAM6_INIT_14 = 256'h0,
parameter SRAM6_INIT_15 = 256'h0,
parameter SRAM6_INIT_16 = 256'h0,
parameter SRAM6_INIT_17 = 256'h0,
parameter SRAM6_INIT_18 = 256'h0,
parameter SRAM6_INIT_19 = 256'h0,
parameter SRAM6_INIT_20 = 256'h0,
parameter SRAM6_INIT_21 = 256'h0,
parameter SRAM6_INIT_22 = 256'h0,
parameter SRAM6_INIT_23 = 256'h0,
parameter SRAM6_INIT_24 = 256'h0,
parameter SRAM6_INIT_25 = 256'h0,
parameter SRAM6_INIT_26 = 256'h0,
parameter SRAM6_INIT_27 = 256'h0,
parameter SRAM6_INIT_28 = 256'h0,
parameter SRAM6_INIT_29 = 256'h0,
parameter SRAM6_INIT_30 = 256'h0,
parameter SRAM6_INIT_31 = 256'h0,
parameter SRAM6_INIT_32 = 256'h0,
parameter SRAM6_INIT_33 = 256'h0,
parameter SRAM6_INIT_34 = 256'h0,
parameter SRAM6_INIT_35 = 256'h0,
parameter SRAM6_INIT_36 = 256'h0,
parameter SRAM6_INIT_37 = 256'h0,
parameter SRAM6_INIT_38 = 256'h0,
parameter SRAM6_INIT_39 = 256'h0,
parameter SRAM6_INIT_40 = 256'h0,
parameter SRAM6_INIT_41 = 256'h0,
parameter SRAM6_INIT_42 = 256'h0,
parameter SRAM6_INIT_43 = 256'h0,
parameter SRAM6_INIT_44 = 256'h0,
parameter SRAM6_INIT_45 = 256'h0,
parameter SRAM6_INIT_46 = 256'h0,
parameter SRAM6_INIT_47 = 256'h0,
parameter SRAM6_INIT_48 = 256'h0,
parameter SRAM6_INIT_49 = 256'h0,
parameter SRAM6_INIT_50 = 256'h0,
parameter SRAM6_INIT_51 = 256'h0,
parameter SRAM6_INIT_52 = 256'h0,
parameter SRAM6_INIT_53 = 256'h0,
parameter SRAM6_INIT_54 = 256'h0,
parameter SRAM6_INIT_55 = 256'h0,
parameter SRAM6_INIT_56 = 256'h0,
parameter SRAM6_INIT_57 = 256'h0,
parameter SRAM6_INIT_58 = 256'h0,
parameter SRAM6_INIT_59 = 256'h0,
parameter SRAM6_INIT_60 = 256'h0,
parameter SRAM6_INIT_61 = 256'h0,
parameter SRAM6_INIT_62 = 256'h0,
parameter SRAM6_INIT_63 = 256'h0,
parameter SRAM7_INIT_0 = 256'h0,
parameter SRAM7_INIT_1 = 256'h0,
parameter SRAM7_INIT_2 = 256'h0,
parameter SRAM7_INIT_3 = 256'h0,
parameter SRAM7_INIT_4 = 256'h0,
parameter SRAM7_INIT_5 = 256'h0,
parameter SRAM7_INIT_6 = 256'h0,
parameter SRAM7_INIT_7 = 256'h0,
parameter SRAM7_INIT_8 = 256'h0,
parameter SRAM7_INIT_9 = 256'h0,
parameter SRAM7_INIT_10 = 256'h0,
parameter SRAM7_INIT_11 = 256'h0,
parameter SRAM7_INIT_12 = 256'h0,
parameter SRAM7_INIT_13 = 256'h0,
parameter SRAM7_INIT_14 = 256'h0,
parameter SRAM7_INIT_15 = 256'h0,
parameter SRAM7_INIT_16 = 256'h0,
parameter SRAM7_INIT_17 = 256'h0,
parameter SRAM7_INIT_18 = 256'h0,
parameter SRAM7_INIT_19 = 256'h0,
parameter SRAM7_INIT_20 = 256'h0,
parameter SRAM7_INIT_21 = 256'h0,
parameter SRAM7_INIT_22 = 256'h0,
parameter SRAM7_INIT_23 = 256'h0,
parameter SRAM7_INIT_24 = 256'h0,
parameter SRAM7_INIT_25 = 256'h0,
parameter SRAM7_INIT_26 = 256'h0,
parameter SRAM7_INIT_27 = 256'h0,
parameter SRAM7_INIT_28 = 256'h0,
parameter SRAM7_INIT_29 = 256'h0,
parameter SRAM7_INIT_30 = 256'h0,
parameter SRAM7_INIT_31 = 256'h0,
parameter SRAM7_INIT_32 = 256'h0,
parameter SRAM7_INIT_33 = 256'h0,
parameter SRAM7_INIT_34 = 256'h0,
parameter SRAM7_INIT_35 = 256'h0,
parameter SRAM7_INIT_36 = 256'h0,
parameter SRAM7_INIT_37 = 256'h0,
parameter SRAM7_INIT_38 = 256'h0,
parameter SRAM7_INIT_39 = 256'h0,
parameter SRAM7_INIT_40 = 256'h0,
parameter SRAM7_INIT_41 = 256'h0,
parameter SRAM7_INIT_42 = 256'h0,
parameter SRAM7_INIT_43 = 256'h0,
parameter SRAM7_INIT_44 = 256'h0,
parameter SRAM7_INIT_45 = 256'h0,
parameter SRAM7_INIT_46 = 256'h0,
parameter SRAM7_INIT_47 = 256'h0,
parameter SRAM7_INIT_48 = 256'h0,
parameter SRAM7_INIT_49 = 256'h0,
parameter SRAM7_INIT_50 = 256'h0,
parameter SRAM7_INIT_51 = 256'h0,
parameter SRAM7_INIT_52 = 256'h0,
parameter SRAM7_INIT_53 = 256'h0,
parameter SRAM7_INIT_54 = 256'h0,
parameter SRAM7_INIT_55 = 256'h0,
parameter SRAM7_INIT_56 = 256'h0,
parameter SRAM7_INIT_57 = 256'h0,
parameter SRAM7_INIT_58 = 256'h0,
parameter SRAM7_INIT_59 = 256'h0,
parameter SRAM7_INIT_60 = 256'h0,
parameter SRAM7_INIT_61 = 256'h0,
parameter SRAM7_INIT_62 = 256'h0,
parameter SRAM7_INIT_63 = 256'h0,
parameter UNUSED = 1'd1
)
(
input i_clk,
input [127:0] i_write_data,
input i_write_enable,
input [9:0] i_address,
input [15:0] i_byte_enable,
output [127:0] o_read_data
);
wire [23:0] nc24_00, nc24_01, nc24_02, nc24_03;
wire [15:0] wea_b0;
wire [15:0] wea_b1;
wire [127:0] read_data_b0;
wire [127:0] read_data_b1;
reg address_9_r;
always @(posedge i_clk)
address_9_r <= i_address[9];
assign wea_b0 = {16{i_write_enable & ~i_address[9]}} & i_byte_enable;
assign wea_b1 = {16{i_write_enable & i_address[9]}} & i_byte_enable;
assign o_read_data = address_9_r ? read_data_b1 : read_data_b0;
// -----------------------------------------
// Bank 0 - first 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[3:0] ),
.DOA ( read_data_b0[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram1 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[7:4] ),
.DOA ( read_data_b0[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[11:8] ),
.DOA ( read_data_b0[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[15:12] ),
.DOA ( read_data_b0[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
// -----------------------------------------
// Bank 1 - second 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM4_INIT_0 ),
.INIT_01 ( SRAM4_INIT_1 ),
.INIT_02 ( SRAM4_INIT_2 ),
.INIT_03 ( SRAM4_INIT_3 ),
.INIT_04 ( SRAM4_INIT_4 ),
.INIT_05 ( SRAM4_INIT_5 ),
.INIT_06 ( SRAM4_INIT_6 ),
.INIT_07 ( SRAM4_INIT_7 ),
.INIT_08 ( SRAM4_INIT_8 ),
.INIT_09 ( SRAM4_INIT_9 ),
.INIT_0A ( SRAM4_INIT_10 ),
.INIT_0B ( SRAM4_INIT_11 ),
.INIT_0C ( SRAM4_INIT_12 ),
.INIT_0D ( SRAM4_INIT_13 ),
.INIT_0E ( SRAM4_INIT_14 ),
.INIT_0F ( SRAM4_INIT_15 ),
.INIT_10 ( SRAM4_INIT_16 ),
.INIT_11 ( SRAM4_INIT_17 ),
.INIT_12 ( SRAM4_INIT_18 ),
.INIT_13 ( SRAM4_INIT_19 ),
.INIT_14 ( SRAM4_INIT_20 ),
.INIT_15 ( SRAM4_INIT_21 ),
.INIT_16 ( SRAM4_INIT_22 ),
.INIT_17 ( SRAM4_INIT_23 ),
.INIT_18 ( SRAM4_INIT_24 ),
.INIT_19 ( SRAM4_INIT_25 ),
.INIT_1A ( SRAM4_INIT_26 ),
.INIT_1B ( SRAM4_INIT_27 ),
.INIT_1C ( SRAM4_INIT_28 ),
.INIT_1D ( SRAM4_INIT_29 ),
.INIT_1E ( SRAM4_INIT_30 ),
.INIT_1F ( SRAM4_INIT_31 ),
.INIT_20 ( SRAM4_INIT_32 ),
.INIT_21 ( SRAM4_INIT_33 ),
.INIT_22 ( SRAM4_INIT_34 ),
.INIT_23 ( SRAM4_INIT_35 ),
.INIT_24 ( SRAM4_INIT_36 ),
.INIT_25 ( SRAM4_INIT_37 ),
.INIT_26 ( SRAM4_INIT_38 ),
.INIT_27 ( SRAM4_INIT_39 ),
.INIT_28 ( SRAM4_INIT_40 ),
.INIT_29 ( SRAM4_INIT_41 ),
.INIT_2A ( SRAM4_INIT_42 ),
.INIT_2B ( SRAM4_INIT_43 ),
.INIT_2C ( SRAM4_INIT_44 ),
.INIT_2D ( SRAM4_INIT_45 ),
.INIT_2E ( SRAM4_INIT_46 ),
.INIT_2F ( SRAM4_INIT_47 ),
.INIT_30 ( SRAM4_INIT_48 ),
.INIT_31 ( SRAM4_INIT_49 ),
.INIT_32 ( SRAM4_INIT_50 ),
.INIT_33 ( SRAM4_INIT_51 ),
.INIT_34 ( SRAM4_INIT_52 ),
.INIT_35 ( SRAM4_INIT_53 ),
.INIT_36 ( SRAM4_INIT_54 ),
.INIT_37 ( SRAM4_INIT_55 ),
.INIT_38 ( SRAM4_INIT_56 ),
.INIT_39 ( SRAM4_INIT_57 ),
.INIT_3A ( SRAM4_INIT_58 ),
.INIT_3B ( SRAM4_INIT_59 ),
.INIT_3C ( SRAM4_INIT_60 ),
.INIT_3D ( SRAM4_INIT_61 ),
.INIT_3E ( SRAM4_INIT_62 ),
.INIT_3F ( SRAM4_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram4 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[3:0] ),
.DOA ( read_data_b1[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM5_INIT_0 ),
.INIT_01 ( SRAM5_INIT_1 ),
.INIT_02 ( SRAM5_INIT_2 ),
.INIT_03 ( SRAM5_INIT_3 ),
.INIT_04 ( SRAM5_INIT_4 ),
.INIT_05 ( SRAM5_INIT_5 ),
.INIT_06 ( SRAM5_INIT_6 ),
.INIT_07 ( SRAM5_INIT_7 ),
.INIT_08 ( SRAM5_INIT_8 ),
.INIT_09 ( SRAM5_INIT_9 ),
.INIT_0A ( SRAM5_INIT_10 ),
.INIT_0B ( SRAM5_INIT_11 ),
.INIT_0C ( SRAM5_INIT_12 ),
.INIT_0D ( SRAM5_INIT_13 ),
.INIT_0E ( SRAM5_INIT_14 ),
.INIT_0F ( SRAM5_INIT_15 ),
.INIT_10 ( SRAM5_INIT_16 ),
.INIT_11 ( SRAM5_INIT_17 ),
.INIT_12 ( SRAM5_INIT_18 ),
.INIT_13 ( SRAM5_INIT_19 ),
.INIT_14 ( SRAM5_INIT_20 ),
.INIT_15 ( SRAM5_INIT_21 ),
.INIT_16 ( SRAM5_INIT_22 ),
.INIT_17 ( SRAM5_INIT_23 ),
.INIT_18 ( SRAM5_INIT_24 ),
.INIT_19 ( SRAM5_INIT_25 ),
.INIT_1A ( SRAM5_INIT_26 ),
.INIT_1B ( SRAM5_INIT_27 ),
.INIT_1C ( SRAM5_INIT_28 ),
.INIT_1D ( SRAM5_INIT_29 ),
.INIT_1E ( SRAM5_INIT_30 ),
.INIT_1F ( SRAM5_INIT_31 ),
.INIT_20 ( SRAM5_INIT_32 ),
.INIT_21 ( SRAM5_INIT_33 ),
.INIT_22 ( SRAM5_INIT_34 ),
.INIT_23 ( SRAM5_INIT_35 ),
.INIT_24 ( SRAM5_INIT_36 ),
.INIT_25 ( SRAM5_INIT_37 ),
.INIT_26 ( SRAM5_INIT_38 ),
.INIT_27 ( SRAM5_INIT_39 ),
.INIT_28 ( SRAM5_INIT_40 ),
.INIT_29 ( SRAM5_INIT_41 ),
.INIT_2A ( SRAM5_INIT_42 ),
.INIT_2B ( SRAM5_INIT_43 ),
.INIT_2C ( SRAM5_INIT_44 ),
.INIT_2D ( SRAM5_INIT_45 ),
.INIT_2E ( SRAM5_INIT_46 ),
.INIT_2F ( SRAM5_INIT_47 ),
.INIT_30 ( SRAM5_INIT_48 ),
.INIT_31 ( SRAM5_INIT_49 ),
.INIT_32 ( SRAM5_INIT_50 ),
.INIT_33 ( SRAM5_INIT_51 ),
.INIT_34 ( SRAM5_INIT_52 ),
.INIT_35 ( SRAM5_INIT_53 ),
.INIT_36 ( SRAM5_INIT_54 ),
.INIT_37 ( SRAM5_INIT_55 ),
.INIT_38 ( SRAM5_INIT_56 ),
.INIT_39 ( SRAM5_INIT_57 ),
.INIT_3A ( SRAM5_INIT_58 ),
.INIT_3B ( SRAM5_INIT_59 ),
.INIT_3C ( SRAM5_INIT_60 ),
.INIT_3D ( SRAM5_INIT_61 ),
.INIT_3E ( SRAM5_INIT_62 ),
.INIT_3F ( SRAM5_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram5 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[7:4] ),
.DOA ( read_data_b1[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM6_INIT_0 ),
.INIT_01 ( SRAM6_INIT_1 ),
.INIT_02 ( SRAM6_INIT_2 ),
.INIT_03 ( SRAM6_INIT_3 ),
.INIT_04 ( SRAM6_INIT_4 ),
.INIT_05 ( SRAM6_INIT_5 ),
.INIT_06 ( SRAM6_INIT_6 ),
.INIT_07 ( SRAM6_INIT_7 ),
.INIT_08 ( SRAM6_INIT_8 ),
.INIT_09 ( SRAM6_INIT_9 ),
.INIT_0A ( SRAM6_INIT_10 ),
.INIT_0B ( SRAM6_INIT_11 ),
.INIT_0C ( SRAM6_INIT_12 ),
.INIT_0D ( SRAM6_INIT_13 ),
.INIT_0E ( SRAM6_INIT_14 ),
.INIT_0F ( SRAM6_INIT_15 ),
.INIT_10 ( SRAM6_INIT_16 ),
.INIT_11 ( SRAM6_INIT_17 ),
.INIT_12 ( SRAM6_INIT_18 ),
.INIT_13 ( SRAM6_INIT_19 ),
.INIT_14 ( SRAM6_INIT_20 ),
.INIT_15 ( SRAM6_INIT_21 ),
.INIT_16 ( SRAM6_INIT_22 ),
.INIT_17 ( SRAM6_INIT_23 ),
.INIT_18 ( SRAM6_INIT_24 ),
.INIT_19 ( SRAM6_INIT_25 ),
.INIT_1A ( SRAM6_INIT_26 ),
.INIT_1B ( SRAM6_INIT_27 ),
.INIT_1C ( SRAM6_INIT_28 ),
.INIT_1D ( SRAM6_INIT_29 ),
.INIT_1E ( SRAM6_INIT_30 ),
.INIT_1F ( SRAM6_INIT_31 ),
.INIT_20 ( SRAM6_INIT_32 ),
.INIT_21 ( SRAM6_INIT_33 ),
.INIT_22 ( SRAM6_INIT_34 ),
.INIT_23 ( SRAM6_INIT_35 ),
.INIT_24 ( SRAM6_INIT_36 ),
.INIT_25 ( SRAM6_INIT_37 ),
.INIT_26 ( SRAM6_INIT_38 ),
.INIT_27 ( SRAM6_INIT_39 ),
.INIT_28 ( SRAM6_INIT_40 ),
.INIT_29 ( SRAM6_INIT_41 ),
.INIT_2A ( SRAM6_INIT_42 ),
.INIT_2B ( SRAM6_INIT_43 ),
.INIT_2C ( SRAM6_INIT_44 ),
.INIT_2D ( SRAM6_INIT_45 ),
.INIT_2E ( SRAM6_INIT_46 ),
.INIT_2F ( SRAM6_INIT_47 ),
.INIT_30 ( SRAM6_INIT_48 ),
.INIT_31 ( SRAM6_INIT_49 ),
.INIT_32 ( SRAM6_INIT_50 ),
.INIT_33 ( SRAM6_INIT_51 ),
.INIT_34 ( SRAM6_INIT_52 ),
.INIT_35 ( SRAM6_INIT_53 ),
.INIT_36 ( SRAM6_INIT_54 ),
.INIT_37 ( SRAM6_INIT_55 ),
.INIT_38 ( SRAM6_INIT_56 ),
.INIT_39 ( SRAM6_INIT_57 ),
.INIT_3A ( SRAM6_INIT_58 ),
.INIT_3B ( SRAM6_INIT_59 ),
.INIT_3C ( SRAM6_INIT_60 ),
.INIT_3D ( SRAM6_INIT_61 ),
.INIT_3E ( SRAM6_INIT_62 ),
.INIT_3F ( SRAM6_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram6 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[11:8] ),
.DOA ( read_data_b1[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM7_INIT_0 ),
.INIT_01 ( SRAM7_INIT_1 ),
.INIT_02 ( SRAM7_INIT_2 ),
.INIT_03 ( SRAM7_INIT_3 ),
.INIT_04 ( SRAM7_INIT_4 ),
.INIT_05 ( SRAM7_INIT_5 ),
.INIT_06 ( SRAM7_INIT_6 ),
.INIT_07 ( SRAM7_INIT_7 ),
.INIT_08 ( SRAM7_INIT_8 ),
.INIT_09 ( SRAM7_INIT_9 ),
.INIT_0A ( SRAM7_INIT_10 ),
.INIT_0B ( SRAM7_INIT_11 ),
.INIT_0C ( SRAM7_INIT_12 ),
.INIT_0D ( SRAM7_INIT_13 ),
.INIT_0E ( SRAM7_INIT_14 ),
.INIT_0F ( SRAM7_INIT_15 ),
.INIT_10 ( SRAM7_INIT_16 ),
.INIT_11 ( SRAM7_INIT_17 ),
.INIT_12 ( SRAM7_INIT_18 ),
.INIT_13 ( SRAM7_INIT_19 ),
.INIT_14 ( SRAM7_INIT_20 ),
.INIT_15 ( SRAM7_INIT_21 ),
.INIT_16 ( SRAM7_INIT_22 ),
.INIT_17 ( SRAM7_INIT_23 ),
.INIT_18 ( SRAM7_INIT_24 ),
.INIT_19 ( SRAM7_INIT_25 ),
.INIT_1A ( SRAM7_INIT_26 ),
.INIT_1B ( SRAM7_INIT_27 ),
.INIT_1C ( SRAM7_INIT_28 ),
.INIT_1D ( SRAM7_INIT_29 ),
.INIT_1E ( SRAM7_INIT_30 ),
.INIT_1F ( SRAM7_INIT_31 ),
.INIT_20 ( SRAM7_INIT_32 ),
.INIT_21 ( SRAM7_INIT_33 ),
.INIT_22 ( SRAM7_INIT_34 ),
.INIT_23 ( SRAM7_INIT_35 ),
.INIT_24 ( SRAM7_INIT_36 ),
.INIT_25 ( SRAM7_INIT_37 ),
.INIT_26 ( SRAM7_INIT_38 ),
.INIT_27 ( SRAM7_INIT_39 ),
.INIT_28 ( SRAM7_INIT_40 ),
.INIT_29 ( SRAM7_INIT_41 ),
.INIT_2A ( SRAM7_INIT_42 ),
.INIT_2B ( SRAM7_INIT_43 ),
.INIT_2C ( SRAM7_INIT_44 ),
.INIT_2D ( SRAM7_INIT_45 ),
.INIT_2E ( SRAM7_INIT_46 ),
.INIT_2F ( SRAM7_INIT_47 ),
.INIT_30 ( SRAM7_INIT_48 ),
.INIT_31 ( SRAM7_INIT_49 ),
.INIT_32 ( SRAM7_INIT_50 ),
.INIT_33 ( SRAM7_INIT_51 ),
.INIT_34 ( SRAM7_INIT_52 ),
.INIT_35 ( SRAM7_INIT_53 ),
.INIT_36 ( SRAM7_INIT_54 ),
.INIT_37 ( SRAM7_INIT_55 ),
.INIT_38 ( SRAM7_INIT_56 ),
.INIT_39 ( SRAM7_INIT_57 ),
.INIT_3A ( SRAM7_INIT_58 ),
.INIT_3B ( SRAM7_INIT_59 ),
.INIT_3C ( SRAM7_INIT_60 ),
.INIT_3D ( SRAM7_INIT_61 ),
.INIT_3E ( SRAM7_INIT_62 ),
.INIT_3F ( SRAM7_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram7 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[15:12] ),
.DOA ( read_data_b1[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V |
(*
Copyright © 2006-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export RSetoid.
Require Import Relation_Definitions.
Require Export Qpossec.
Require Import COrdFields2.
Require Import Qordfield.
Require Import QMinMax.
Require Import List.
Require Import CornTac.
Require Import stdlib_omissions.Q.
Require QnnInf.
Import QnnInf.notations.
Open Local Scope Q_scope.
Set Implicit Arguments.
(**
* Metric Space
In this version, a metric space over a setoid X is characterized by a
ball relation B where B e x y is intended to mean that the two points
x and y are within e of each other ( d(x,y)<=e ). This is characterized
by the axioms given in the record structure below.
*)
Record is_MetricSpace (X : RSetoid) (B: Qpos -> relation X) : Prop :=
{ msp_refl: forall e, Reflexive (B e)
; msp_sym: forall e, Symmetric (B e)
; msp_triangle: forall e1 e2 a b c, B e1 a b -> B e2 b c -> B (e1 + e2)%Qpos a c
; msp_closed: forall e a b, (forall d, B (e+d)%Qpos a b) -> B e a b
; msp_eq: forall a b, (forall e, B e a b) -> st_eq a b
}.
Record MetricSpace : Type :=
{ msp_is_setoid :> RSetoid
; ball : Qpos -> msp_is_setoid -> msp_is_setoid -> Prop
; ball_wd : forall (e1 e2:Qpos), (QposEq e1 e2) ->
forall x1 x2, (st_eq x1 x2) ->
forall y1 y2, (st_eq y1 y2) ->
(ball e1 x1 y1 <-> ball e2 x2 y2)
; msp : is_MetricSpace msp_is_setoid ball
}.
(* begin hide *)
Implicit Arguments ball [m].
(*This is intended to be used as a ``type cast'' that Coq won't randomly make disappear.
It is useful when defining setoid rewrite lemmas for st_eq.*)
Definition ms_id (m:MetricSpace) (x:m) : m := x.
Implicit Arguments ms_id [m].
Add Parametric Morphism (m:MetricSpace) : (@ball m) with signature QposEq ==> (@st_eq m) ==> (@st_eq m) ==> iff as ball_compat.
Proof.
exact (@ball_wd m).
Qed.
(* end hide *)
Section Metric_Space.
(*
** Ball lemmas
*)
Variable X : MetricSpace.
(** These lemmas give direct access to the ball axioms of a metric space
*)
Lemma ball_refl : forall e (a:X), ball e a a.
Proof.
apply (msp_refl (msp X)).
Qed.
Lemma ball_sym : forall e (a b:X), ball e a b -> ball e b a.
Proof.
apply (msp_sym (msp X)).
Qed.
Lemma ball_triangle : forall e1 e2 (a b c:X), ball e1 a b -> ball e2 b c -> ball (e1+e2) a c.
Proof.
apply (msp_triangle (msp X)).
Qed.
Lemma ball_closed : forall e (a b:X), (forall d, ball (e+d) a b) -> ball e a b.
Proof.
apply (msp_closed (msp X)).
Qed.
Lemma ball_eq : forall (a b:X), (forall e, ball e a b) -> st_eq a b.
Proof.
apply (msp_eq (msp X)).
Qed.
Lemma ball_eq_iff : forall (a b:X), (forall e, ball e a b) <-> st_eq a b.
Proof.
split.
apply ball_eq.
intros H e.
rewrite -> H.
apply ball_refl.
Qed.
(** The ball constraint on a and b can always be weakened. Here are
two forms of the weakening lemma.
*)
Lemma ball_weak : forall e d (a b:X), ball e a b -> ball (e+d) a b.
Proof.
intros e d a b B1.
eapply ball_triangle.
apply B1.
apply ball_refl.
Qed.
Hint Resolve ball_refl ball_triangle ball_weak : metric.
Lemma ball_weak_le : forall (e d:Qpos) (a b:X), e<=d -> ball e a b -> ball d a b.
Proof.
intros e d a b Hed B1.
destruct (Qle_lt_or_eq _ _ Hed).
destruct (Qpos_lt_plus H) as [c Hc].
rewrite <- Q_Qpos_plus in Hc.
change (QposEq d (e+c)) in Hc.
rewrite -> Hc; clear - B1.
auto with *.
change (QposEq e d) in H.
rewrite <- H.
assumption.
Qed.
End Metric_Space.
(* begin hide *)
Hint Resolve ball_refl ball_sym ball_triangle ball_weak : metric.
(* end hide *)
(** We can easily generalize ball to take the ratio from Q or QnnInf: *)
Section gball.
Context {m: MetricSpace}.
Definition gball (q: Q) (x y: m): Prop :=
match Qdec_sign q with
| inl (inl _) => False (* q < 0, silly *)
| inl (inr p) => ball (exist (Qlt 0) q p) x y (* 0 < q, normal *)
| inr _ => x[=]y (* q == 0 *)
end.
(* Program can make this definition slightly cleaner, but the resulting term is much nastier... *)
Definition gball_ex (e: QnnInf): relation m :=
match e with
| QnnInf.Finite e' => gball (proj1_sig e')
| QnnInf.Infinite => fun _ _ => True
end.
Lemma ball_gball (q: Qpos) (x y: m): gball q x y <-> ball q x y.
Proof with auto.
unfold gball.
revert q x y.
intros [q p] ??. simpl.
destruct Qdec_sign as [[A | A] | A].
exfalso.
apply (Qlt_is_antisymmetric_unfolded q 0)...
apply ball_wd; reflexivity.
exfalso.
apply (Qlt_irrefl 0).
rewrite <- A at 2...
Qed.
Global Instance gball_Proper: Proper (Qeq ==> @st_eq m ==> @st_eq m ==> iff) gball.
Proof with auto.
intros x y E a b F v w G.
unfold gball.
destruct Qdec_sign as [[A | B] | C];
destruct Qdec_sign as [[P | Q] | R].
reflexivity.
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 1. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
apply ball_wd...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 2. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 1. rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 2. rewrite E...
rewrite F, G. reflexivity.
Qed.
Global Instance gball_ex_Proper: Proper (QnnInf.eq ==> @st_eq m ==> @st_eq m ==> iff) gball_ex.
Proof.
repeat intro.
destruct x, y. intuition. intuition. intuition.
apply gball_Proper; assumption.
Qed.
Global Instance gball_refl (e: Q): 0 <= e -> Reflexive (gball e).
Proof with auto.
repeat intro.
unfold gball.
destruct Qdec_sign as [[?|?]|?].
apply (Qlt_not_le e 0)...
apply ball_refl.
reflexivity.
Qed.
Global Instance gball_ex_refl (e: QnnInf): Reflexive (gball_ex e).
Proof.
destruct e. intuition.
apply gball_refl, proj2_sig.
Qed.
Global Instance gball_sym (e: Q): Symmetric (gball e).
Proof with auto.
unfold gball. repeat intro.
destruct Qdec_sign as [[?|?]|?]...
apply ball_sym...
symmetry...
Qed.
Lemma gball_ex_sym (e: QnnInf): Symmetric (gball_ex e).
Proof. destruct e. auto. simpl. apply gball_sym. Qed.
Lemma gball_triangle (e1 e2: Q) (a b c: m):
gball e1 a b -> gball e2 b c -> gball (e1 + e2) a c.
Proof with auto with *.
unfold gball.
intros.
destruct (Qdec_sign e1) as [[A|B]|C].
exfalso...
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. apply Qle_not_lt...
simpl.
setoid_replace (exist (Qlt 0) (e1 + e2) q0) with (exist (Qlt 0) e1 B + exist (Qlt 0) e2 q)%Qpos by reflexivity.
apply ball_triangle with b...
exfalso.
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. rewrite q0.
apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite q. rewrite Qplus_0_r. apply Qle_not_lt...
apply ball_gball. simpl. rewrite q, Qplus_0_r. rewrite <- H0. apply ball_gball in H. assumption.
exfalso.
revert q0. rewrite q. rewrite Qplus_0_r. intro. clear H. revert B. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
apply ball_gball in H0.
simpl in H0.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C. rewrite Qplus_0_l. apply Qle_not_lt...
apply ball_gball. simpl.
rewrite C, Qplus_0_l, H...
exfalso. revert q0. rewrite C, Qplus_0_l. intro. clear H0. revert q. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
exfalso. revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
transitivity b...
Qed. (* TODO: THE HORROR!! *)
Lemma gball_ex_triangle (e1 e2: QnnInf) (a b c: m):
gball_ex e1 a b -> gball_ex e2 b c -> gball_ex (e1 + e2)%QnnInf a c.
Proof. destruct e1, e2; auto. simpl. apply gball_triangle. Qed.
Lemma gball_0 (x y: m): gball 0 x y <-> x [=] y.
Proof. reflexivity. Qed.
Lemma gball_weak_le (q q': Q): q <= q' -> forall x y, gball q x y -> gball q' x y.
Proof with auto.
revert q q'.
intros ?? E ?? F.
unfold gball in F.
destruct Qdec_sign as [[A | B] | C].
intuition.
assert (0 < q') as q'p. apply Qlt_le_trans with q...
apply (ball_gball (exist _ q' q'p)).
apply ball_weak_le with (exist _ q B)...
rewrite F.
apply gball_refl.
rewrite <- C...
Qed.
Lemma gball_pos {e : Q} (e_pos : 0 < e) (x y : m) : ball (exist _ e e_pos) x y <-> gball e x y.
Proof.
unfold gball. destruct (Qsec.Qdec_sign e) as [[e_neg | e_pos'] | e_zero].
+ elim (Qlt_irrefl _ (Qlt_trans _ _ _ e_pos e_neg)).
+ setoid_replace (exist _ e e_pos) with (exist _ e e_pos'); easy.
+ exfalso; rewrite e_zero in e_pos; apply (Qlt_irrefl _ e_pos).
Qed.
Lemma gball_neg (e : Q) (x y : m) : e < 0 -> ~ gball e x y.
Proof.
intro e_neg. unfold gball. destruct (Qsec.Qdec_sign e) as [[E | E] | E]; [easy | |].
+ intros _; apply (Qlt_irrefl _ (Qlt_trans _ _ _ e_neg E)).
+ rewrite E in e_neg. intros _; apply (Qlt_irrefl _ e_neg).
Qed.
Lemma gball_closed (e : Q) (x y : m) :
(forall d : Q, 0 < d -> gball (e + d) x y) -> gball e x y.
Proof.
intro C. (*change (gball e x y).*) unfold gball.
destruct (Qsec.Qdec_sign e) as [[e_neg | e_pos] | e_zero].
+ assert (e / 2 < 0) by now apply Qmult_neg_pos.
apply (@gball_neg (e/2) x y); [easy |].
setoid_replace (e / 2) with (e - e / 2) by (field; discriminate).
apply C; now apply Qopp_Qlt_0_l.
+ apply (msp_closed (msp m)). intros [d d_pos]. now apply gball_pos, C.
+ apply ball_eq. intros [d d_pos]. apply gball_pos.
setoid_replace d with (e + d); [now apply C | rewrite e_zero; symmetry; apply Qplus_0_l].
Qed.
Lemma gball_closed_eq (x y : m) : (forall d : Q, 0 < d -> gball d x y) -> x [=] y.
Proof.
intro C. change (gball 0 x y). apply gball_closed. intro d.
setoid_replace (0 + d)%Q with d by apply Qplus_0_l. apply C.
Qed.
End gball.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-27 18:38:13
// Last Modified : 2016-09-27 20:00:38
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-25 17:59:05
// Last Modified : 2016-09-27 18:36:46
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-25 12:25:16
// Last Modified : 2016-09-25 12:25:16
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-24 01:24:56
// Last Modified : 2016-09-24 01:24:56
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
`timescale 1ns/1ps
module tb_FPU_PIPELINED_FPADDSUB2_vector_testing (); /* this is automatically generated */
localparam PERIOD = 10;
// (*NOTE*) replace reset, clock
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR=26;
parameter EWR = 5; //Single Precision */
// parameter W = 64;
// parameter EW = 11;
// parameter SW = 52;
// parameter SWR = 55;
// parameter EWR = 6;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MODULE SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg beg_OP;
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
wire busy;
wire overflow_flag;
wire underflow_flag;
wire zero_flag;
wire [W-1:0] final_result_ieee;
reg [SW-1:0] final_result_ieee_mantissa;
reg [EW-1:0] final_result_ieee_exponent;
reg final_result_ieee_sign;
wire ready;
//Temps for the testbench and verification
reg [SW-1:0] Data_X_mant;
reg [SW-1:0] Data_Y_mant;
reg [EW-1:0] Data_X_exp;
reg [EW-1:0] Data_Y_exp;
reg Data_X_sign;
reg Data_Y_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS VARIABLES
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] formatted_number_W;
reg overflow_flag_t, underflow_flag_t;
//reg [EWR-1:0] LZD_raw_val_EWR;
reg [W-1:0] Theoretical_result;
reg [SW-1:0] Theoretical_result_mantissa;
reg [EW-1:0] Theoretical_result_exponent;
reg Theoretical_result_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// STIMULI SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_3 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer logVectorReference;
integer Cont_CLK;
integer Recept;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// END OF DECLARATIONS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
FPU_PIPELINED_FPADDSUB #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_uut (
.clk (clk),
.rst (rst),
.beg_OP (beg_OP),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
always begin
#1;
final_result_ieee_mantissa = final_result_ieee[SW-1:0];
final_result_ieee_exponent = final_result_ieee[W-2:SW];
final_result_ieee_sign = final_result_ieee[W-1];
Data_X_mant = Data_X[SW-1:0];
Data_Y_mant = Data_Y[SW-1:0];
Data_X_exp = Data_X[W-2:SW];
Data_Y_exp = Data_Y[W-2:SW];
Data_X_sign = Data_X[W-1];
Data_Y_sign = Data_Y[W-1];
Theoretical_result_mantissa = Theoretical_result[SW-1:0];
Theoretical_result_exponent = Theoretical_result[W-2:SW];
Theoretical_result_sign = Theoretical_result[W-1];
end
// function [EWR-1:0] LZD_raw; // function definition starts here
// input [SWR-1:0] ADD_SUB_RAW;
// integer k;
// begin
// LZD_raw = 0;
// k=SWR-1;
// while(ADD_SUB_RAW[k] == 0) begin
// k = k-1;
// LZD_raw = LZD_raw + 1;
// $display("This is the bit analized %d\n", k);
// $display("This is the bit analized %d\n", ADD_SUB_RAW[k]);
// $display("Number of 0s %d\n", LZD_raw);
// end
// end
// endfunction
initial begin
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
logVectorReference = $fopen("output_log.py","w");
rst = 1;
`ifdef SUB_OPER
add_subt = 1; //Se realiza la operacion de resta
`else
add_subt = 0; //Se realiza la operacion de suma
`endif
beg_OP = 0;
Data_Y = 0;
Data_X = 0;
Data_X_mant = 0;
Data_Y_mant = 0;
Data_X_exp = 0;
Data_Y_exp = 0;
Data_X_sign = 0;
Data_Y_sign = 0;
//Theoretical_result = 32'hbe1abef8;
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
#98 rst = 0;
//FPADD_FPSUB(0, Array_IN[3], Array_IN_2[3], formatted_number_W, overflow_flag_t, underflow_flag_t);
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
$readmemh("Hexadecimal_R.txt", Array_IN_3);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if (contador == (2**PERIOD+6)) begin
$fclose(FileSaveData);
$fclose(logVectorReference);
$finish;
end else if(ready) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
end
end
always @(negedge clk) begin
#(PERIOD/5);
if(~busy & ~rst) begin
beg_OP = 1;
end
end
always @(posedge clk) begin
#(PERIOD/5);
if(rst) begin
contador = 0;
end
else if(~busy & ~rst) begin
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
repeat(3) @(posedge clk);
end
end
// clock
initial begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
task FPADD_FPSUB;
//inputs
input op;
input [W-1:0] Operand1_W;
input [W-1:0] Operand2_W;
//outputs
output [W-1:0] formatted_number_W;
output overflow_flag;
output underflow_flag;
//Temporaries
reg [SW-1:0] Mantissa1_SW;
reg [SW-1:0] Mantissa2_SW;
reg [EW-1:0] Exponent1_EW;
reg [EW-1:0] Exponent2_EW;
reg Sign1;
reg [SW-1:0] Mantissa_M_SW;
reg [EW-1:0] Exponent_M_EW;
reg Sign2;
reg [SW-1:0] Mantissa_m_SW;
reg [EW-1:0] Exponent_m_EW;
reg [SWR-1:0] Mantissa_M_SWR;
reg [SWR-1:0] Mantissa_m_SWR;
reg [SWR-1:0] Mantissa_m_SWR1;
reg [SWR-1:0] norm_Mantissa_SWR;
reg [EW-1:0] Exponent_diff_EW;
reg [SWR:0] raw_Mantissa_SWR1;
reg overflow_flag, underflow_flag;
reg carry_out_exp_oper;
reg gtXY;
reg eqXY;
reg real_sign;
reg real_op;
reg add_overflow;
reg overunder;
reg [SWR-1:0]raw_Mantissa_SWR;
reg [EWR-1:0]LZD_raw_val_EWR;
reg [EW-1:0] U_limit; //Max Normal value of the standar ieee 754
reg [EW-1:0] L_limit; //Min Normal value of the standar ieee 754
reg final_sign;
reg [EW-1:0] exp_mux_D1;
reg [SW-1:0] sgf_mux_D1;
reg [EW-EWR-1:0] LZD_ZFiller;
integer k;
begin
// $display ("%g CPU Write task with address : 0x%h Data : 0x%h",
// $time, address,data);
// $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus",
// $time);
Sign1 = Operand1_W[W-1];
Sign2 = Operand2_W[W-1];
Exponent1_EW = Operand1_W[EW-1+SW:SW];
Exponent2_EW = Operand2_W[EW-1+SW:SW];
Mantissa1_SW = Operand1_W[SW-1:0];
Mantissa2_SW = Operand2_W[SW-1:0];
//LZD_raw_val_EWR = LZD_raw({3'b000,Operand1_W});
if(EW == 8) begin
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
if (EW == 8) begin
LZD_ZFiller = 3'd0;
end else begin
LZD_ZFiller =5'd0;
end
//@ (posedge clk);
#10;
$fwrite(logVectorReference,"=============INIT STAGE: input signals==============\n");
$fwrite(logVectorReference,"---------First Operator------------\n");
$fwrite(logVectorReference,"FP Format = 0x%30h, Mantissa = 0x%21h, Exponent = 0x%6h, sign = %d\n", Operand1_W, Mantissa1_SW, Exponent1_EW, Sign1);
$fwrite(logVectorReference,"FP Format = %b, Mantissa = %b, Exponent = %b, sign = %b\n", Operand1_W, Mantissa1_SW, Exponent1_EW, Sign1);
$fwrite(logVectorReference,"--------Second Operator------------\n");
$fwrite(logVectorReference,"P Format = 0x%30h, Mantissa = 0x%21h, Exponent = 0x%6h, sign = %d\n", Operand2_W, Mantissa2_SW, Exponent2_EW, Sign2);
$fwrite(logVectorReference,"FP Format = %b, Mantissa = %b, Exponent = %b, sign = %b\n", Operand2_W, Mantissa2_SW, Exponent2_EW, Sign2);
gtXY = ({Exponent1_EW, Mantissa1_SW} > {Exponent2_EW, Mantissa2_SW}) ? 1'b1 : 1'b0;
eqXY = ({Exponent1_EW, Mantissa1_SW} == {Exponent2_EW, Mantissa2_SW}) ? 1'b1 : 1'b0;
real_op = op ^ Sign2 ^ Sign1;
real_sign = (gtXY | ((op | Sign2) & (~op | ~Sign2))) & ( Sign1 | ~(eqXY | gtXY));
if(gtXY == 1) begin
{Exponent_M_EW, Mantissa_M_SW} = {Exponent1_EW , Mantissa1_SW};
{Exponent_m_EW, Mantissa_m_SW} = {Exponent2_EW , Mantissa2_SW};
end
else begin
{Exponent_M_EW, Mantissa_M_SW} = {Exponent2_EW , Mantissa2_SW};
{Exponent_m_EW, Mantissa_m_SW} = {Exponent1_EW , Mantissa1_SW};
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============INIT STAGE: output signals==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h, Exponent_m_EW = 0x%6h\n", Mantissa_m_SW, Exponent_m_EW);
$fwrite(logVectorReference,"Mantissa_m_SW = %b, Exponent_m_EW = %b\n", Mantissa_m_SW, Exponent_m_EW);
$fwrite(logVectorReference,"======================== ^ ===================\n");
//$fwrite(logVectorReference,"===============INIT STAGE: FROM THE UUT ============\n");
//$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
//$fwrite(logVectorReference,"SIGN_FLAG_EXP = %d, OP_FLAG_INIT = %d\n", uut.SIGN_FLAG_INIT, uut.OP_FLAG_INIT);
// $fwrite(logVectorReference,"--------Big Number------------\n");
// $fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
// $fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
// $fwrite(logVectorReference,"--------Small Number------------\n");
// $fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h, Exponent_m_EW = 0x%6h\n", Mantissa_m_SW, Exponent_m_EW);
// $fwrite(logVectorReference,"Mantissa_m_SW = %b, Exponent_m_EW = %b\n", Mantissa_m_SW, Exponent_m_EW);
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
@ (posedge clk);
Exponent_diff_EW = Exponent_M_EW - Exponent_m_EW;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============EXP STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h\n", Mantissa_m_SW);
$fwrite(logVectorReference,"Mantissa_m_SW = %b\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Exponent_diff_EW = Exp M - Exp m = 0x%6h\n", Exponent_diff_EW);
$fwrite(logVectorReference,"Exponent_diff_EW = Exp M - Exp m = %b\n", Exponent_diff_EW);
// $fwrite(logVectorReference,"===============EXP STAGE FROM UUT============\n");
// $fwrite(logVectorReference,"--------------------FLAGS------------------\n");
// $fwrite(logVectorReference,"SIGN_FLAG_EXP = %d, OP_FLAG_EXP = %d\n", uut.SIGN_FLAG_EXP, uut.OP_FLAG_EXP);
// $fwrite(logVectorReference,"--------Big Number------------\n");
// $fwrite(logVectorReference,"DMP_mant_EXP_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", uut.DMP_mant_EXP_SW, uut.DMP_exp_EXP_EW);
// $fwrite(logVectorReference,"DMP_mant_EXP_SW = %b, Exponent_M_EW = %b\n", uut.DMP_mant_EXP_SW, uut.DMP_exp_EXP_EW);
// $fwrite(logVectorReference,"--------Small Number------------\n");
// $fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h\n", uut.DmP_mant_EXP_SW);
// $fwrite(logVectorReference,"Mantissa_m_SW = %b\n", uut.DmP_mant_EXP_SW);
// $fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
// $fwrite(logVectorReference,"Shift_amount_EXP_EW = Exp M - Exp m = 0x%6h\n", uut.Exponent_diff_EW);
// $fwrite(logVectorReference,"Shift_amount_EXP_EW = Exp M - Exp m = %b\n", uut.Exponent_diff_EW);
// $fwrite(logVectorReference,"===============EXP STAGE============\n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============EXP STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
Mantissa_m_SWR = {1'b1,Mantissa_m_SW, 2'b0} >> Exponent_diff_EW;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"========== ===SHT1 STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"--------Sign = %d, real_op = %d ----------------\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------------------------------\n");
$fwrite(logVectorReference,"--------------Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h--------\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------------Mantissa_M_SW = %b, Exponent_M_EW = %b--------\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------------Small Number--------------------\n");
$fwrite(logVectorReference,"--------Mantissa_m_SW hex = 0x%21h--------\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------Mantissa_m_SW bin = %b----------\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------------------OPERATION RESULT--------------------\n");
$fwrite(logVectorReference,"--------Shifted mantissa result hex = 0x%24h-------\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"--------Shifted mantissa result bin = %b-------\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"========== ===SHT1 STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
//Our shifter is segmented, hence, the extra clk cycle
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Shifted Mantissa_m_SWR = 0x%24h\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"Shifted Mantissa_m_SWR = %b\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"===================SHT2 STAGE FROM THE UUT================\n");
// $fwrite(logVectorReference,"--------------------FLAGS------------------\n");
// $fwrite(logVectorReference,"Sign = %d, real_op = %d\n", uut.SIGN_FLAG_SHT2, uut.OP_FLAG_SHT2);
// $fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
// $fwrite(logVectorReference,"sftr_idat_SHT2_SWR = 0x%24h\n", uut.sftr_idat_SHT2_SWR);
// $fwrite(logVectorReference,"sftr_odat_SHT2_SWR = %b\n", uut.sftr_odat_SHT2_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
Mantissa_M_SWR = {1'b1,Mantissa_M_SW, 2'b0};
if (real_op == 1) begin
raw_Mantissa_SWR1 = Mantissa_M_SWR - Mantissa_m_SWR;
$display("Se restan las mantisas\n");
end
else begin
raw_Mantissa_SWR1 = Mantissa_M_SWR + Mantissa_m_SWR;
$display("Se suman las mantisas\n");
end
raw_Mantissa_SWR = raw_Mantissa_SWR1[SWR-1:0];
add_overflow = raw_Mantissa_SWR1[SWR-2];
add_overflow = add_overflow&(~real_op);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SGF STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, Sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%24h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %26d, Exponent_M_EW = %8d\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = 0x%24h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = %b, Exponent_M_EW = %b\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = %26d, Exponent_M_EW = %8d\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa hex = 0x%24h\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"Mantissa bin = %b\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"Mantissa bin = %26d\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Mantissa operation result = 0x%24h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %b\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %26d\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SGF STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
LZD_raw_val_EWR = 0;
k=SWR-1;
$display("Mantissa operation result = 0x%h, Mantissa result bin = %b\n", raw_Mantissa_SWR, raw_Mantissa_SWR);
$display("dentro del loop %d, \n", raw_Mantissa_SWR[k]);
while(~raw_Mantissa_SWR[k]) begin
k = k-1;
LZD_raw_val_EWR = LZD_raw_val_EWR + 1;
$display("dentro del loop\n");
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, Sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantisa hex SW = 0x%21h \n", Mantissa_M_SW);
$fwrite(logVectorReference,"Mantisa hex SW = %b\n", Mantissa_M_SW);
$fwrite(logVectorReference,"Mantisa hex SWR = 0x%24h\n", Mantissa_M_SWR);
$fwrite(logVectorReference,"Mantisa hex SWR = %b\n", Mantissa_M_SWR);
$fwrite(logVectorReference,"Exponent = 0x%h\n", Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Mantissa operation result = 0x%24h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = 0x%h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %26d\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"LZD result hex = 0x%h, LZD result hex = %b\n", LZD_raw_val_EWR, LZD_raw_val_EWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
if (add_overflow) begin
//Signed shift
norm_Mantissa_SWR = raw_Mantissa_SWR >>> 1;
end
else begin
norm_Mantissa_SWR = raw_Mantissa_SWR << LZD_raw_val_EWR;
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Exponent = 0x%6h\n", Exponent_M_EW);
$fwrite(logVectorReference,"Exponent = %b\n", Exponent_M_EW);
$fwrite(logVectorReference,"Exponent = %8d\n", Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Normalized mantissa (shifted) = 0x%24h\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"Normalized mantissa (shifted) = %b\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"Normalized mantissa (shifted) = %26d\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"LZD result hex = 0x%h, LZD result bin = %b\n", LZD_raw_val_EWR, LZD_raw_val_EWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
//We do a second shift over here
//We do the xponent compensation
if (add_overflow) begin
{carry_out_exp_oper,Exponent_M_EW} = Exponent_M_EW - 1;
end
else begin
{carry_out_exp_oper,Exponent_M_EW} = Exponent_M_EW + {LZD_ZFiller,LZD_raw_val_EWR};
end
overflow_flag =({carry_out_exp_oper,Exponent_M_EW} > U_limit) ? 1'b1 : 1'b0;
underflow_flag =({carry_out_exp_oper,Exponent_M_EW} < L_limit) ? 1'b1 : 1'b0;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"overflow flag = %d, underflow flag = %d, sign flag = %d\n", overflow_flag, underflow_flag, real_sign);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Compensated Exponent = 0x%6h, Normalized mantissa (shifted) = 0x%24h\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"Compensated Exponent = %b, Normalized mantissa (shifted) = %b\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"Compensated Exponent = %8d, Normalized mantissa (shifted) = %26d\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== FRMT STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"La mantisa final sera: 0x%21h\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"La mantisa final sera: %b\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"La mantisa final sera: %23d\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"El exponente final sera: 0x%6h\n", Exponent_M_EW);
$fwrite(logVectorReference,"El exponente final sera: %b\n", Exponent_M_EW);
$fwrite(logVectorReference,"El exponente final sera: %8d\n", Exponent_M_EW);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== FRMT STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
overunder = overflow_flag | underflow_flag;
case ({overflow_flag,underflow_flag})
2'b00: final_sign=real_sign;
2'b01: final_sign=1'b1;
2'b10: final_sign=1'b0;
default: final_sign=0;
endcase
if (overunder == 0) begin
formatted_number_W = {final_sign, Exponent_M_EW, norm_Mantissa_SWR[SWR-2:2]};
end else begin
formatted_number_W = {final_sign,exp_mux_D1,sgf_mux_D1};
end
$fwrite(logVectorReference,"=================== FRMT STAGE ================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"overflow flag = %d, underflow flag = %d\n", overflow_flag, underflow_flag);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"El resultado final sera: %32h\n", formatted_number_W);
$fwrite(logVectorReference,"El resultado final sera: %b\n", formatted_number_W);
$fwrite(logVectorReference,"El resultado final sera: %32d\n", formatted_number_W);
$fwrite(logVectorReference,"=================== FRMT STAGE ================\n");
end
endtask
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The itcm_ctrl module control the ITCM access requests
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_ITCM //{
module e203_itcm_ctrl(
output itcm_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// ITCM SRAM clock gating for debugging purpose
input tcm_cgstop,
// Note: the ITCM ICB interface only support the single-transaction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// IFU ICB to ITCM
// * Bus cmd channel
input ifu2itcm_icb_cmd_valid, // Handshake valid
output ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
input ifu2itcm_icb_cmd_read, // Read or write
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_cmd_wdata,
input [`E203_ITCM_WMSK_WIDTH-1:0] ifu2itcm_icb_cmd_wmask,
// * Bus RSP channel
output ifu2itcm_icb_rsp_valid, // Response valid
input ifu2itcm_icb_rsp_ready, // Response ready
output ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
output ifu2itcm_holdup,
//output ifu2itcm_replay,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// LSU ICB to ITCM
// * Bus cmd channel
input lsu2itcm_icb_cmd_valid, // Handshake valid
output lsu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr, // Bus transaction start addr
input lsu2itcm_icb_cmd_read, // Read or write
input [32-1:0] lsu2itcm_icb_cmd_wdata,
input [4-1:0] lsu2itcm_icb_cmd_wmask,
// * Bus RSP channel
output lsu2itcm_icb_rsp_valid, // Response valid
input lsu2itcm_icb_rsp_ready, // Response ready
output lsu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] lsu2itcm_icb_rsp_rdata,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid, // Handshake valid
output ext2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr, // Bus transaction start addr
input ext2itcm_icb_cmd_read, // Read or write
input [32-1:0] ext2itcm_icb_cmd_wdata,
input [ 4-1:0] ext2itcm_icb_cmd_wmask,
// * Bus RSP channel
output ext2itcm_icb_rsp_valid, // Response valid
input ext2itcm_icb_rsp_ready, // Response ready
output ext2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
output itcm_ram_cs,
output itcm_ram_we,
output [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
output [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
output clk_itcm_ram,
input test_mode,
input clk,
input rst_n
);
// LSU2ITCM converted to ICM data width
// * Bus cmd channel
wire lsu_icb_cmd_valid;
wire lsu_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] lsu_icb_cmd_addr;
wire lsu_icb_cmd_read;
wire [`E203_ITCM_DATA_WIDTH-1:0] lsu_icb_cmd_wdata;
wire [`E203_ITCM_DATA_WIDTH/8-1:0] lsu_icb_cmd_wmask;
// * Bus RSP channel
wire lsu_icb_rsp_valid;
wire lsu_icb_rsp_ready;
wire lsu_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] lsu_icb_rsp_rdata;
sirv_gnrl_icb_n2w # (
.FIFO_OUTS_NUM (`E203_ITCM_OUTS_NUM),
.FIFO_CUT_READY (0),
.USR_W (1),
.AW (`E203_ITCM_ADDR_WIDTH),
.X_W (32),
.Y_W (`E203_ITCM_DATA_WIDTH)
) u_itcm_icb_lsu2itcm_n2w(
.i_icb_cmd_valid (lsu2itcm_icb_cmd_valid ),
.i_icb_cmd_ready (lsu2itcm_icb_cmd_ready ),
.i_icb_cmd_read (lsu2itcm_icb_cmd_read ) ,
.i_icb_cmd_addr (lsu2itcm_icb_cmd_addr ) ,
.i_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata ),
.i_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask) ,
.i_icb_cmd_burst (2'b0) ,
.i_icb_cmd_beat (2'b0) ,
.i_icb_cmd_lock (1'b0),
.i_icb_cmd_excl (1'b0),
.i_icb_cmd_size (2'b0),
.i_icb_cmd_usr (1'b0),
.i_icb_rsp_valid (lsu2itcm_icb_rsp_valid ),
.i_icb_rsp_ready (lsu2itcm_icb_rsp_ready ),
.i_icb_rsp_err (lsu2itcm_icb_rsp_err) ,
.i_icb_rsp_excl_ok () ,
.i_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata ),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (lsu_icb_cmd_valid ),
.o_icb_cmd_ready (lsu_icb_cmd_ready ),
.o_icb_cmd_read (lsu_icb_cmd_read ) ,
.o_icb_cmd_addr (lsu_icb_cmd_addr ) ,
.o_icb_cmd_wdata (lsu_icb_cmd_wdata ),
.o_icb_cmd_wmask (lsu_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock (),
.o_icb_cmd_excl (),
.o_icb_cmd_size (),
.o_icb_cmd_usr (),
.o_icb_rsp_valid (lsu_icb_rsp_valid ),
.o_icb_rsp_ready (lsu_icb_rsp_ready ),
.o_icb_rsp_err (lsu_icb_rsp_err) ,
.o_icb_rsp_excl_ok (1'b0) ,
.o_icb_rsp_rdata (lsu_icb_rsp_rdata ),
.o_icb_rsp_usr (1'b0),
.clk (clk ) ,
.rst_n (rst_n )
);
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// EXTITF converted to ICM data width
// * Bus cmd channel
wire ext_icb_cmd_valid;
wire ext_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] ext_icb_cmd_addr;
wire ext_icb_cmd_read;
wire [`E203_ITCM_DATA_WIDTH-1:0] ext_icb_cmd_wdata;
wire [`E203_ITCM_WMSK_WIDTH-1:0] ext_icb_cmd_wmask;
// * Bus RSP channel
wire ext_icb_rsp_valid;
wire ext_icb_rsp_ready;
wire ext_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] ext_icb_rsp_rdata;
`ifdef E203_SYSMEM_DATA_WIDTH_IS_32 //{
`ifdef E203_ITCM_DATA_WIDTH_IS_64 //{
sirv_gnrl_icb_n2w # (
.USR_W (1),
.FIFO_OUTS_NUM (`E203_ITCM_OUTS_NUM),
.FIFO_CUT_READY (0),
.AW (`E203_ITCM_ADDR_WIDTH),
.X_W (`E203_SYSMEM_DATA_WIDTH),
.Y_W (`E203_ITCM_DATA_WIDTH)
) u_itcm_icb_ext2itcm_n2w(
.i_icb_cmd_valid (ext2itcm_icb_cmd_valid ),
.i_icb_cmd_ready (ext2itcm_icb_cmd_ready ),
.i_icb_cmd_read (ext2itcm_icb_cmd_read ) ,
.i_icb_cmd_addr (ext2itcm_icb_cmd_addr ) ,
.i_icb_cmd_wdata (ext2itcm_icb_cmd_wdata ),
.i_icb_cmd_wmask (ext2itcm_icb_cmd_wmask) ,
.i_icb_cmd_burst (2'b0) ,
.i_icb_cmd_beat (2'b0) ,
.i_icb_cmd_lock (1'b0),
.i_icb_cmd_excl (1'b0),
.i_icb_cmd_size (2'b0),
.i_icb_cmd_usr (1'b0),
.i_icb_rsp_valid (ext2itcm_icb_rsp_valid ),
.i_icb_rsp_ready (ext2itcm_icb_rsp_ready ),
.i_icb_rsp_err (ext2itcm_icb_rsp_err) ,
.i_icb_rsp_excl_ok () ,
.i_icb_rsp_rdata (ext2itcm_icb_rsp_rdata ),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (ext_icb_cmd_valid ),
.o_icb_cmd_ready (ext_icb_cmd_ready ),
.o_icb_cmd_read (ext_icb_cmd_read ) ,
.o_icb_cmd_addr (ext_icb_cmd_addr ) ,
.o_icb_cmd_wdata (ext_icb_cmd_wdata ),
.o_icb_cmd_wmask (ext_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock (),
.o_icb_cmd_excl (),
.o_icb_cmd_size (),
.o_icb_cmd_usr (),
.o_icb_rsp_valid (ext_icb_rsp_valid ),
.o_icb_rsp_ready (ext_icb_rsp_ready ),
.o_icb_rsp_err (ext_icb_rsp_err) ,
.o_icb_rsp_excl_ok (1'b0),
.o_icb_rsp_rdata (ext_icb_rsp_rdata ),
.o_icb_rsp_usr (1'b0),
.clk (clk ) ,
.rst_n (rst_n)
);
`endif//}
`else//}{
!!! ERROR: There must be something wrong, our System interface
must be 32bits and ITCM must be 64bits to save area and powers!!!
`endif//}
`endif//}
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_ITCM_DATA_WIDTH-1:0] arbt_icb_cmd_wdata;
wire [`E203_ITCM_WMSK_WIDTH-1:0] arbt_icb_cmd_wmask;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] arbt_icb_rsp_rdata;
`ifdef E203_HAS_ITCM_EXTITF //{
localparam ITCM_ARBT_I_NUM = 2;
localparam ITCM_ARBT_I_PTR_W = 1;
`else//}{
localparam ITCM_ARBT_I_NUM = 1;
localparam ITCM_ARBT_I_PTR_W = 1;
`endif//}
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [ITCM_ARBT_I_NUM*`E203_ITCM_ADDR_WIDTH-1:0] arbt_bus_icb_cmd_addr;
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [ITCM_ARBT_I_NUM*`E203_ITCM_DATA_WIDTH-1:0] arbt_bus_icb_cmd_wdata;
wire [ITCM_ARBT_I_NUM*`E203_ITCM_WMSK_WIDTH-1:0] arbt_bus_icb_cmd_wmask;
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [ITCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [ITCM_ARBT_I_NUM*`E203_ITCM_DATA_WIDTH-1:0] arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_cmd_valid =
// LSU take higher priority
{
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_valid,
`endif//}
lsu_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_addr,
`endif//}
lsu_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_read,
`endif//}
lsu_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_wdata,
`endif//}
lsu_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_wmask,
`endif//}
lsu_icb_cmd_wmask
} ;
assign {
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_cmd_ready,
`endif//}
lsu_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
assign {
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_rsp_valid,
`endif//}
lsu_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_rsp_err,
`endif//}
lsu_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_rsp_rdata,
`endif//}
lsu_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_ITCM_EXTITF //{
ext_icb_rsp_ready,
`endif//}
lsu_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because for ITCM and DTCM,
// Dcache, .etc, definitely they cannot reponse as 0 cycle
.FIFO_OUTS_NUM (`E203_ITCM_OUTS_NUM),
.FIFO_CUT_READY(0),
.USR_W (1),
.ARBT_NUM (ITCM_ARBT_I_NUM ),
.ARBT_PTR_W (ITCM_ARBT_I_PTR_W),
.AW (`E203_ITCM_ADDR_WIDTH),
.DW (`E203_ITCM_DATA_WIDTH)
) u_itcm_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock () ,
.o_icb_cmd_excl () ,
.o_icb_cmd_size () ,
.o_icb_cmd_usr () ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0),
.o_icb_rsp_excl_ok (1'b0),
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst ({2*ITCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_beat ({2*ITCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_lock ({1*ITCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_excl ({1*ITCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_size ({2*ITCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_usr ({1*ITCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr (),
.i_bus_icb_rsp_excl_ok (),
.clk (clk ) ,
.rst_n (rst_n)
);
wire sram_ready2ifu = 1'b1
//The EXT and load/store have higher priotry than the ifetch
& (~arbt_icb_cmd_valid)
;
wire sram_ready2arbt = 1'b1
;
wire sram_sel_ifu = sram_ready2ifu & ifu2itcm_icb_cmd_valid;
wire sram_sel_arbt = sram_ready2arbt & arbt_icb_cmd_valid;
wire sram_icb_cmd_ready;
wire sram_icb_cmd_valid;
assign ifu2itcm_icb_cmd_ready = sram_ready2ifu & sram_icb_cmd_ready;
assign arbt_icb_cmd_ready = sram_ready2arbt & sram_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] sram_icb_cmd_addr;
wire sram_icb_cmd_read;
wire [`E203_ITCM_DATA_WIDTH-1:0] sram_icb_cmd_wdata;
wire [`E203_ITCM_WMSK_WIDTH-1:0] sram_icb_cmd_wmask;
assign sram_icb_cmd_valid = (sram_sel_ifu & ifu2itcm_icb_cmd_valid)
| (sram_sel_arbt & arbt_icb_cmd_valid);
assign sram_icb_cmd_addr = ({`E203_ITCM_ADDR_WIDTH{sram_sel_ifu }} & ifu2itcm_icb_cmd_addr)
| ({`E203_ITCM_ADDR_WIDTH{sram_sel_arbt }} & arbt_icb_cmd_addr);
assign sram_icb_cmd_read = (sram_sel_ifu & ifu2itcm_icb_cmd_read)
| (sram_sel_arbt & arbt_icb_cmd_read);
assign sram_icb_cmd_wdata = ({`E203_ITCM_DATA_WIDTH{sram_sel_ifu }} & ifu2itcm_icb_cmd_wdata)
| ({`E203_ITCM_DATA_WIDTH{sram_sel_arbt }} & arbt_icb_cmd_wdata);
assign sram_icb_cmd_wmask = ({`E203_ITCM_WMSK_WIDTH{sram_sel_ifu }} & ifu2itcm_icb_cmd_wmask)
| ({`E203_ITCM_WMSK_WIDTH{sram_sel_arbt }} & arbt_icb_cmd_wmask);
wire sram_icb_cmd_ifu = sram_sel_ifu;
wire [1:0] sram_icb_rsp_usr;
wire [1:0] sram_icb_cmd_usr = {sram_icb_cmd_ifu,sram_icb_cmd_read};
wire sram_icb_rsp_ifu ;
wire sram_icb_rsp_read;
assign {sram_icb_rsp_ifu, sram_icb_rsp_read} = sram_icb_rsp_usr;
wire itcm_sram_ctrl_active;
wire sram_icb_rsp_valid;
wire sram_icb_rsp_ready;
wire [`E203_ITCM_DATA_WIDTH-1:0] sram_icb_rsp_rdata;
wire sram_icb_rsp_err;
`ifndef E203_HAS_ECC //{
sirv_sram_icb_ctrl #(
.DW (`E203_ITCM_DATA_WIDTH),
.AW (`E203_ITCM_ADDR_WIDTH),
.MW (`E203_ITCM_WMSK_WIDTH),
.AW_LSB (3),// ITCM is 64bits wide, so the LSB is 3
.USR_W (2)
) u_sram_icb_ctrl(
.sram_ctrl_active (itcm_sram_ctrl_active),
.tcm_cgstop (tcm_cgstop),
.i_icb_cmd_valid (sram_icb_cmd_valid),
.i_icb_cmd_ready (sram_icb_cmd_ready),
.i_icb_cmd_read (sram_icb_cmd_read ),
.i_icb_cmd_addr (sram_icb_cmd_addr ),
.i_icb_cmd_wdata (sram_icb_cmd_wdata),
.i_icb_cmd_wmask (sram_icb_cmd_wmask),
.i_icb_cmd_usr (sram_icb_cmd_usr ),
.i_icb_rsp_valid (sram_icb_rsp_valid),
.i_icb_rsp_ready (sram_icb_rsp_ready),
.i_icb_rsp_rdata (sram_icb_rsp_rdata),
.i_icb_rsp_usr (sram_icb_rsp_usr ),
.ram_cs (itcm_ram_cs ),
.ram_we (itcm_ram_we ),
.ram_addr (itcm_ram_addr),
.ram_wem (itcm_ram_wem ),
.ram_din (itcm_ram_din ),
.ram_dout (itcm_ram_dout),
.clk_ram (clk_itcm_ram ),
.test_mode(test_mode ),
.clk (clk ),
.rst_n(rst_n)
);
assign sram_icb_rsp_err = 1'b0;
`endif//}
// The E2 pass to IFU RSP channel only when it is IFU access
// The E2 pass to ARBT RSP channel only when it is not IFU access
assign sram_icb_rsp_ready = sram_icb_rsp_ifu ?
ifu2itcm_icb_rsp_ready : arbt_icb_rsp_ready;
assign ifu2itcm_icb_rsp_valid = sram_icb_rsp_valid & sram_icb_rsp_ifu;
assign ifu2itcm_icb_rsp_err = sram_icb_rsp_err;
assign ifu2itcm_icb_rsp_rdata = sram_icb_rsp_rdata;
assign arbt_icb_rsp_valid = sram_icb_rsp_valid & (~sram_icb_rsp_ifu);
assign arbt_icb_rsp_err = sram_icb_rsp_err;
assign arbt_icb_rsp_rdata = sram_icb_rsp_rdata;
// The holdup indicating the target is not accessed by other agents
// since last accessed by IFU, and the output of it is holding up
// last value. Hence,
// * The holdup flag it set when there is a succuess (no-error) ifetch
// accessed this target
// * The holdup flag it clear when when
// ** other agent (non-IFU) accessed this target
// ** other agent (non-IFU) accessed this target
//for example:
// *** The external agent accessed the ITCM
// *** I$ updated by cache maintaineice operation
wire ifu_holdup_r;
// The IFU holdup will be set after last time accessed by a IFU access
wire ifu_holdup_set = sram_icb_cmd_ifu & itcm_ram_cs;
// The IFU holdup will be cleared after last time accessed by a non-IFU access
wire ifu_holdup_clr = (~sram_icb_cmd_ifu) & itcm_ram_cs;
wire ifu_holdup_ena = ifu_holdup_set | ifu_holdup_clr;
wire ifu_holdup_nxt = ifu_holdup_set & (~ifu_holdup_clr);
sirv_gnrl_dfflr #(1)ifu_holdup_dffl(ifu_holdup_ena, ifu_holdup_nxt, ifu_holdup_r, clk, rst_n);
assign ifu2itcm_holdup = ifu_holdup_r
;
assign itcm_active = ifu2itcm_icb_cmd_valid | lsu2itcm_icb_cmd_valid | itcm_sram_ctrl_active
`ifdef E203_HAS_ITCM_EXTITF //{
| ext2itcm_icb_cmd_valid
`endif//}
;
endmodule
`endif//}
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_count_to_128(
input clk,
input rst,
input count,
input ud,
output reg [6:0] counter_value
);
//This module counts up/down between 0 to 128
//input clk, rst, count, ud;
//output [6:0] counter_value;
wire [6:0] counter_value_preserver;
//reg [6:0] counter_value/*synthesis syn_noprune = 1*/;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
counter_value = 7'h00;
else begin
case({count,ud})
2'b00: counter_value = 7'h00;
2'b01: counter_value = counter_value_preserver;
2'b10: counter_value = counter_value_preserver - 1;
2'b11: counter_value = counter_value_preserver + 1;
default: counter_value = 7'h00;
endcase
end
end
assign counter_value_preserver = counter_value;
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.