function
stringlengths 11
56k
| repo_name
stringlengths 5
60
| features
sequence |
|---|---|---|
def test_truncate_function(self):
self.assertEqual(pyrtl.truncate(5, 3), 5)
self.assertEqual(pyrtl.truncate(9, 3), 1)
self.assertEqual(pyrtl.truncate(-1, 3), 7)
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.truncate(5, -1)
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.truncate(29, 0) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_infer_val_and_bitwidth(self):
self.assertEqual(pyrtl.infer_val_and_bitwidth(2, bitwidth=5), (2, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth(3), (3, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(True), (1, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth(False), (0, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth("5'd12"), (12, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth("5'b10"), (2, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth("5'b10"), (2, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth("8'B 0110_1100"), (108, 8))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-3, bitwidth=5), (0b11101, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth(3, signed=True), (3, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-3, signed=True), (5, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-4, signed=True), (4, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-3, bitwidth=5, signed=True), (29, 5))
self.assertEqual(pyrtl.infer_val_and_bitwidth(3, bitwidth=2), (3, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(0), (0, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth(1), (1, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth(2), (2, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(3), (3, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(4), (4, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(0, signed=True), (0, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth(1, signed=True), (1, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(2, signed=True), (2, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(3, signed=True), (3, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(4, signed=True), (4, 4))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-1, signed=True), (1, 1))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-2, signed=True), (2, 2))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-3, signed=True), (5, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-4, signed=True), (4, 3))
self.assertEqual(pyrtl.infer_val_and_bitwidth(-5, signed=True), (11, 4))
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.infer_val_and_bitwidth(-3)
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.infer_val_and_bitwidth(True, signed=True)
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.infer_val_and_bitwidth(3, bitwidth=2, signed=True) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
random.seed(8492049)
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_pattern_type_or_length_mismatch(self):
instr = pyrtl.WireVector(name='instr', bitwidth=8)
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, '000100010')
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, '0001000')
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, '0b00010001')
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, 0b000100010)
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, '')
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, None)
with self.assertRaises(pyrtl.PyrtlError):
o, _ = pyrtl.match_bitpattern(instr, instr) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_simulates_no_ones_in_pattern(self):
r = pyrtl.Register(6, 'r')
r.next <<= r + 3
# 000000 -> 000011 -> 000110 -> 001001 -> 001100 -> 001111 -> 010010 -> 010101
a, _ = pyrtl.match_bitpattern(r, '00??00')
o = pyrtl.Output(name='o')
o <<= a
self.check_trace('o 10001000\nr 036912151821\n') | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_simulates_only_wildcards(self):
r = pyrtl.Register(6, 'r')
r.next <<= r + 3
# 000000 -> 000011 -> 000110 -> 001001 -> 001100 -> 001111 -> 010010 -> 010101
a, _ = pyrtl.match_bitpattern(r, '??????')
o = pyrtl.Output(name='o')
o <<= a
self.check_trace('o 11111111\nr 036912151821\n') | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_with_non_consecutive_field(self):
r = pyrtl.Register(6, 'r')
r.next <<= r + 3
# 000000 -> 000011 -> 000110 -> 001001 -> 001100 -> 001111 -> 010010 -> 010101
m, (b, a) = pyrtl.match_bitpattern(r, 'bb0ab1')
pyrtl.probe(b, 'b')
pyrtl.probe(a, 'a')
o = pyrtl.Output(name='o')
o <<= m
self.check_trace(
'a 00101101\n'
'b 01100132\n'
'o 01000001\n'
'r 036912151821\n'
) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_with_all_fields(self):
r = pyrtl.Register(6, 'r')
r.next <<= r + 3
# 000000 -> 000011 -> 000110 -> 001001 -> 001100 -> 001111 -> 010010 -> 010101
m, (a, b, c, d, e, f) = pyrtl.match_bitpattern(r, 'abcdef')
pyrtl.probe(a, 'a')
pyrtl.probe(b, 'b')
pyrtl.probe(c, 'c')
pyrtl.probe(d, 'd')
pyrtl.probe(e, 'e')
pyrtl.probe(f, 'f')
o = pyrtl.Output(name='o')
o <<= m
self.check_trace(
'a 00000000\n'
'b 00000011\n'
'c 00011100\n'
'd 00101101\n'
'e 01100110\n'
'f 01010101\n'
'o 11111111\n'
'r 036912151821\n'
) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_with_pattern_matched_fields(self):
i = pyrtl.Input(5, 'i')
out = pyrtl.Output(2, 'out')
with pyrtl.conditional_assignment:
with pyrtl.match_bitpattern(i, '1a?a0') as (a,):
out |= a
with pyrtl.match_bitpattern(i, 'b0?1b') as (b,):
out |= b
with pyrtl.match_bitpattern(i, 'ba1ab') as (b, a):
out |= a + b
self.check_all_accesses_valid() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_match_bitwidth_with_pattern_matched_fields_with_field_map(self):
i = pyrtl.Input(5, 'i')
out = pyrtl.Output(2, 'out')
field_map = {'a': 'field1', 'b': 'field2'}
with pyrtl.conditional_assignment:
with pyrtl.match_bitpattern(i, '1a?a0', field_map) as x:
out |= x.field1
with pyrtl.match_bitpattern(i, 'b0?1b', field_map) as x:
out |= x.field2
with pyrtl.match_bitpattern(i, 'ba1ab', field_map) as x:
out |= x.field1 + x.field2
self.check_all_accesses_valid() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def r5_br_immed(x):
# i is the 12th bit, k is the 11th bit, and j is the bottom 10 bits of the immediate field
return {'i': (x >> 11) & 0x1, 'k': (x >> 10) & 0x1, 'j': x & ((1 << 10) - 1)} | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_named_fields(self):
self.assertEqual(
pyrtl.bitpattern_to_val(
'0000000sssssrrrrr000ddddd0110011', s=1, r=2, d=3
), # RISC-V ADD
0b00000000000100010000000110110011
)
self.assertEqual(
pyrtl.bitpattern_to_val('iiiiiiisssssrrrrr010iiiii0100011', i=1, s=3, r=4), # RISC-V SW
0b00000000001100100010000010100011
)
self.assertEqual(
pyrtl.bitpattern_to_val(
'ijjjjjjsssssrrrrr100jjjjk1100011',
s=2, r=3, **TestBitpatternToVal.r5_br_immed(-5)
), # RISC-V BLT
0b11111110001000011100101111100011
) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_fields_all_different(self):
self.assertEqual(
pyrtl.bitpattern_to_val('abcdefg', a=1, b=0, c=1, d=0, e=0, f=1, g=0),
0b1010010
) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_error_both_ordered_and_named_fields(self):
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.bitpattern_to_val('iiiiiiirrrrrsssss010iiiii0100011', 1, r=3, s=4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_error_bitpattern_field_not_provided(self):
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.bitpattern_to_val('iiiiiiirrrrrsssss010iiiii0100011', i=1, r=3, t=4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_error_value_doesnt_fit_in_field(self):
with self.assertRaises(pyrtl.PyrtlError):
pyrtl.bitpattern_to_val('iiiiiiirrrrrsssss010iiiii0100011', 1, 65, 4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
random.seed(8492049)
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_fields_mismatch(self):
instr = pyrtl.WireVector(name='instr', bitwidth=32)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.chop(instr, 10, 10, 10)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.chop(instr, 10, 10, 14)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.chop(instr, 33) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_chop_does_simulation_correct(self):
r = pyrtl.Register(5, 'r')
r.next <<= r + 1
a, b, c = pyrtl.helperfuncs.chop(r, 2, 2, 1)
o = pyrtl.Output(name='o')
o <<= c
self.check_trace('o 01010101\nr 01234567\n') | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
random.seed(8492049)
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_field_too_big(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=3)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.bitfield_update(a, 1, 2, b) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_no_bits_to_update(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=3)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.bitfield_update(a, 1, 1, b, truncating=True) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def ref(i, s, e, u):
mask = ((1 << (e)) - 1) - ((1 << s) - 1)
return (i & ~mask) | ((u << s) & mask) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_bitfield(self):
self.bitfield_update_checker(10, 3, 6, 3) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_bitfield_all_but_msb(self):
a = pyrtl.Const(0, 8)
pyrtl.probe(pyrtl.bitfield_update(a, None, -1, 0b101110), 'out')
sim = pyrtl.Simulation()
sim.step({})
self.assertEqual(sim.inspect('out'), 0b0101110) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_bitfield_all_but_lsb(self):
a = pyrtl.Const(0, 8)
pyrtl.probe(pyrtl.bitfield_update(a, 1, None, 0b1011101), 'out') # TODO
sim = pyrtl.Simulation()
sim.step({})
self.assertEqual(sim.inspect('out'), 0b10111010) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
random.seed(8492049)
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_field_too_big(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=3)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.bitfield_update_set(a, {(1, 2): b}) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_no_bits_to_update(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=3)
with self.assertRaises(pyrtl.PyrtlError):
o = pyrtl.bitfield_update_set(a, {(1, 1): b}, truncating=True) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def bitfield_update_set_checker(self, input_width, update_set_constraints, test_amt=20):
from functools import reduce
from collections import namedtuple
Update_Info = namedtuple('Update_Info', ['range_start', 'range_end',
'update_wire', 'update_vals'])
def ref(i, s, e, u):
mask = ((1 << (e)) - 1) - ((1 << s) - 1)
return (i & ~mask) | ((u << s) & mask)
inp, inp_vals = utils.an_input_and_vals(input_width, test_vals=test_amt, name='inp')
update_set_list = []
for ix, (range_start, range_end, update_width) in enumerate(update_set_constraints):
upd, upd_vals = utils.an_input_and_vals(update_width, test_vals=test_amt,
name='upd%d' % ix)
update_set_list.append(Update_Info(range_start, range_end, upd, upd_vals))
out = pyrtl.Output(input_width, "out")
bfu_out = pyrtl.bitfield_update_set(
inp,
{(ui.range_start, ui.range_end): ui.update_wire for ui in update_set_list}
)
self.assertEqual(len(out), len(bfu_out)) # output should have width of input
out <<= bfu_out
true_result = []
for ix, iv in enumerate(inp_vals):
true_result.append(
reduce(lambda w, ui: ref(w, ui.range_start, ui.range_end, ui.update_vals[ix]),
update_set_list, iv)
)
upd_result = utils.sim_and_ret_out(
out,
[inp] + [ui.update_wire for ui in update_set_list],
[inp_vals] + [ui.update_vals for ui in update_set_list],
)
self.assertEqual(upd_result, true_result) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_any_only_on_1_bit_vectors(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
with self.assertRaises(pyrtl.PyrtlError):
r = pyrtl.corecircuits.rtl_any(a, b) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_any_works_with_consts(self):
a = pyrtl.WireVector(name='a', bitwidth=1)
c = pyrtl.WireVector(name='c', bitwidth=1)
r = pyrtl.corecircuits.rtl_any(a, 1, c) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_any_does_simulation_correct(self):
r = pyrtl.Register(3, 'r')
r.next <<= r + 1
a, b, c = r[0], r[1], r[2]
o = pyrtl.Output(name='o')
o <<= pyrtl.corecircuits.rtl_any(a, b, c)
self.check_trace('o 01111111\nr 01234567\n') | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_empty(self):
with self.assertRaises(pyrtl.PyrtlError):
import operator
pyrtl.tree_reduce(operator.add, []) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_one_wirevector(self):
r = pyrtl.Register(3, 'r')
r.next <<= r + 1
o = pyrtl.Output(name='o')
o <<= pyrtl.corecircuits.xor_all_bits(r)
self.check_trace('o 01101001\nr 01234567\n') | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_list_of_long_wires(self):
in_wires, vals = utils.make_inputs_and_values(4, exact_bitwidth=13)
out = pyrtl.Output(name='o')
out <<= pyrtl.corecircuits.xor_all_bits(in_wires)
expected = [v1 ^ v2 ^ v3 ^ v4 for v1, v2, v3, v4 in zip(*vals)]
self.assertEqual(expected, utils.sim_and_ret_out(out, in_wires, vals)) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_mux_not_enough_inputs(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
c = pyrtl.WireVector(name='c', bitwidth=1)
s = pyrtl.WireVector(name='s', bitwidth=2)
with self.assertRaises(pyrtl.PyrtlError):
r = pyrtl.corecircuits.mux(s, a, b, c) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_mux_enough_inputs_with_default(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
c = pyrtl.WireVector(name='c', bitwidth=1)
d = pyrtl.WireVector(name='d', bitwidth=1)
s = pyrtl.WireVector(name='s', bitwidth=2)
r = pyrtl.corecircuits.mux(s, a, b, c, d, default=0) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_mux_too_many_inputs_with_extra_kwarg(self):
a = pyrtl.WireVector(name='a', bitwidth=3)
b = pyrtl.WireVector(name='b', bitwidth=1)
s = pyrtl.WireVector(name='s', bitwidth=2)
with self.assertRaises(pyrtl.PyrtlError):
r = pyrtl.corecircuits.mux(s, a, b, default=0, foo=1) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUpClass(cls):
random.seed(8492049) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_simple_mux_1(self):
self.mux_t_subprocess(4, 16) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def mux_t_subprocess(self, addr_width, val_width):
mux_ins, vals = utils.make_consts(num_wires=2**addr_width, exact_bitwidth=val_width)
control, testctrl = utils.an_input_and_vals(addr_width, 40, "mux_ctrl")
out = pyrtl.Output(val_width, "mux_out")
out <<= pyrtl.corecircuits.mux(control, *mux_ins)
true_result = [vals[i] for i in testctrl]
mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,))
self.assertEqual(mux_result, true_result) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_select(self):
vals = 12, 27
mux_ins = [pyrtl.Const(x) for x in vals]
control, testctrl = utils.an_input_and_vals(1, 40, "sel_ctrl", utils.uniform_dist)
out = pyrtl.Output(5, "mux_out")
out <<= pyrtl.corecircuits.select(control, falsecase=mux_ins[0], truecase=mux_ins[1])
true_result = [vals[i] for i in testctrl]
mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,))
self.assertEqual(mux_result, true_result) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_simple_probe(self):
i = pyrtl.Input(1)
o = pyrtl.Output(1)
o <<= pyrtl.probe(i + 1) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_simple_probe_debug(self):
pyrtl.set_debug_mode()
i = pyrtl.Input(1)
o = pyrtl.Output(1)
output = six.StringIO()
sys.stdout = output
o <<= pyrtl.probe(i + 1, name="probe0")
sys.stdout = sys.__stdout__
self.assertTrue(output.getvalue().startswith("Probe: probe0"))
pyrtl.set_debug_mode(False) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
random.seed(8492049)
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def sll_checker(self, input_width, shift_width, shift_amount=None):
mask = (1 << input_width) - 1
def ref(i, s):
return (i << s) & mask
self.shift_checker(pyrtl.shift_left_logical, ref, input_width, shift_width, shift_amount) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def ref(i, s):
return (i << s) & mask | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def srl_checker(self, input_width, shift_width, shift_amount=None):
mask = (1 << input_width) - 1
def ref(i, s):
return (i >> s) & mask
self.shift_checker(pyrtl.shift_right_logical, ref, input_width, shift_width, shift_amount) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def ref(i, s):
mask = (1 << input_width) - 1
if (i >> input_width - 1) & 0x1 == 0x1:
return ((~mask | i) >> s) & mask # negative number
else:
return (i >> s) & mask # positive number | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_sll(self):
self.sll_checker(5, 2) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_srl(self):
self.srl_checker(5, 2) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_sll_big(self):
self.sll_checker(10, 3) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_srl_big(self):
self.srl_checker(10, 3) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_sll_over(self):
self.sll_checker(4, 4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_srl_over(self):
self.srl_checker(4, 4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_sll_integer_shift_amount(self):
self.sll_checker(5, 2, 1) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_srl_integer_shift_amount(self):
self.srl_checker(5, 2, 1) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_mult_1(self):
self.mult_t_base(1, 7) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_mult_2(self):
self.mult_t_base(5, 4) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_bad_type(self):
self.bad_rtl_assert(True, self.RTLSampleException())
self.bad_rtl_assert(1, self.RTLSampleException()) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_invalid_exception_type(self):
w = pyrtl.Input(1)
self.bad_rtl_assert(w, 1)
self.bad_rtl_assert(w, "")
self.bad_rtl_assert(w, w)
self.bad_rtl_assert(w, KeyError()) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_wire_from_another_block(self):
w = pyrtl.Input(1)
pyrtl.reset_working_block()
self.bad_rtl_assert(w, self.RTLSampleException()) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_create_assert(self):
w = pyrtl.WireVector(1)
pyrtl.rtl_assert(w, self.RTLSampleException('testing rtl assert')) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_assert_fastsimulation(self):
i = pyrtl.Input(1)
o = pyrtl.rtl_assert(i, self.RTLSampleException('test assertion failed'))
sim = pyrtl.FastSimulation()
sim.step({i: 1})
self.assertEqual(sim.inspect(o), 1)
with self.assertRaises(self.RTLSampleException):
sim.step({i: 0}) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def setUp(self):
pyrtl.reset_working_block()
# Redirect stdout because we don't care to see the specific messages about
# wires being deemed useless by optimization sent to stdout.
f = open(os.devnull, 'w')
sys.stdout = f | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def assert_no_loop(self):
self.assertEqual(pyrtl.find_loop(), None)
pyrtl.synthesize()
self.assertEqual(pyrtl.find_loop(), None)
pyrtl.optimize()
self.assertEqual(pyrtl.find_loop(), None) | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_no_loop_1(self):
ins = [pyrtl.Input(8) for i in range(8)]
outs = [pyrtl.Output(8) for i in range(3)]
x_1 = ins[0] & ins[1]
x_2 = ins[3] & ins[4]
x_3 = ins[0] | ins[4]
x_4 = ins[6] ^ ins[7]
x_5 = ~ ins[2]
x_6 = ~ x_2
x_7 = x_1 ^ x_3 & x_6
outs[0] <<= x_4
outs[2] <<= x_5 | x_7
outs[1] <<= (x_1 & x_7) ^ x_3
self.assert_no_loop() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_no_loop_special_ops(self):
mem1 = pyrtl.MemBlock(4, 4)
ins = [pyrtl.Input(4) for i in range(8)]
outs = [pyrtl.Output(4) for i in range(3)]
reg = pyrtl.Register(4)
x_1 = ins[4] < reg
x_2 = ins[1] * x_1
x_3 = pyrtl.corecircuits.mux(x_1, ins[1], ins[2])
# x_4 = pyrtl.as_wires(mem1[ins[6]])
x_4 = mem1[ins[6]]
x_5 = reg + ins[7]
x_9 = pyrtl.as_wires(x_4)
mem1[pyrtl.as_wires(x_4)] <<= x_9
outs[0] <<= x_2 == x_1
reg.next <<= x_5 & ins[1]
outs[1] <<= reg
outs[2] <<= pyrtl.corecircuits.concat(x_1, x_5[:7])
self.assert_no_loop() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def test_loop_2(self):
in_1 = pyrtl.Input(10)
in_2 = pyrtl.Input(9)
fake_loop_wire = pyrtl.WireVector(1)
# Note the slight difference from the last test case on the next line
comp_wire = pyrtl.corecircuits.concat(in_2[0:6], fake_loop_wire, in_2[6:9])
r_wire = in_1 & comp_wire
fake_loop_wire <<= r_wire[3]
out = pyrtl.Output(10)
out <<= fake_loop_wire
# It causes there to be a real loop
self.assert_has_loop() | UCSBarchlab/PyRTL | [
184,
70,
184,
23,
1393210686
] |
def do_populate_tags(parser,token):
"""
render a list of tags, with it's link.
the token is tag.
Arguments:
- `parser`:
- `token`:
"""
bits = token.split_contents()
print bits
return PopulateTagsNode(bits[1]) | jpartogi/django-job-board | [
36,
10,
36,
9,
1253006304
] |
def __init__(self,tag):
self.tag_tag = Variable(tag) | jpartogi/django-job-board | [
36,
10,
36,
9,
1253006304
] |
def configure(self):
commands = []
commands.extend(self.register.get_commands("ConfMode"))
# C_Low
if "C_Low".lower() in map(lambda x: x.lower(), self.enable_shift_masks):
self.register.set_pixel_register_value('C_Low', 1)
commands.extend(self.register.get_commands("WrFrontEnd", same_mask_for_all_dc=True, name='C_Low'))
else:
self.register.set_pixel_register_value('C_Low', 0)
commands.extend(self.register.get_commands("WrFrontEnd", same_mask_for_all_dc=True, name='C_Low'))
# C_High
if "C_High".lower() in map(lambda x: x.lower(), self.enable_shift_masks):
self.register.set_pixel_register_value('C_High', 1)
commands.extend(self.register.get_commands("WrFrontEnd", same_mask_for_all_dc=True, name='C_High'))
else:
self.register.set_pixel_register_value('C_High', 0)
commands.extend(self.register.get_commands("WrFrontEnd", same_mask_for_all_dc=True, name='C_High'))
commands.extend(self.register.get_commands("RunMode"))
self.register_utils.send_commands(commands) | SiLab-Bonn/pyBAR | [
9,
17,
9,
3,
1422005052
] |
def scan(self):
scan_parameter_range = [0, (2 ** self.register.global_registers['PlsrDAC']['bitlength'])]
if self.scan_parameters.PlsrDAC[0]:
scan_parameter_range[0] = self.scan_parameters.PlsrDAC[0]
if self.scan_parameters.PlsrDAC[1]:
scan_parameter_range[1] = self.scan_parameters.PlsrDAC[1]
scan_parameter_range = range(scan_parameter_range[0], scan_parameter_range[1] + 1, self.step_size)
logging.info("Scanning %s from %d to %d", 'PlsrDAC', scan_parameter_range[0], scan_parameter_range[-1]) | SiLab-Bonn/pyBAR | [
9,
17,
9,
3,
1422005052
] |
def analyze(self):
with AnalyzeRawData(raw_data_file=self.output_filename, create_pdf=True) as analyze_raw_data:
analyze_raw_data.create_tot_hist = False
analyze_raw_data.create_fitted_threshold_hists = True
analyze_raw_data.create_threshold_mask = True
analyze_raw_data.n_injections = 100
analyze_raw_data.interpreter.set_warning_output(False) # so far the data structure in a threshold scan was always bad, too many warnings given
analyze_raw_data.interpret_word_table()
analyze_raw_data.interpreter.print_summary()
analyze_raw_data.plot_histograms() | SiLab-Bonn/pyBAR | [
9,
17,
9,
3,
1422005052
] |
def safe_call(func):
"""
Causes the decorated function to reraise GAE datastore errors as
Django DatabaseErrors.
"""
@wraps(func)
def _func(*args, **kwargs):
try:
return func(*args, **kwargs)
except GAEError, e:
raise DatabaseError, DatabaseError(str(e)), sys.exc_info()[2]
return _func | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def __init__(self, compiler, fields):
super(GAEQuery, self).__init__(compiler, fields)
self.inequality_field = None
self.included_pks = None
self.ancestor_key = None
self.excluded_pks = ()
self.has_negated_exact_filter = False
self.ordering = []
self.db_table = self.query.get_meta().db_table
self.pks_only = (len(fields) == 1 and fields[0].primary_key)
start_cursor = getattr(self.query, '_gae_start_cursor', None)
end_cursor = getattr(self.query, '_gae_end_cursor', None)
self.gae_query = [Query(self.db_table, keys_only=self.pks_only,
cursor=start_cursor, end_cursor=end_cursor)] | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def __repr__(self):
return '<GAEQuery: %r ORDER %r>' % (self.gae_query, self.ordering) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def fetch(self, low_mark=0, high_mark=None):
query = self._build_query()
executed = False
if self.excluded_pks and high_mark is not None:
high_mark += len(self.excluded_pks)
if self.included_pks is not None:
results = self.get_matching_pk(low_mark, high_mark)
else:
if high_mark is None:
kw = {}
if low_mark:
kw['offset'] = low_mark
results = query.Run(**kw)
executed = True
elif high_mark > low_mark:
results = query.Get(high_mark - low_mark, low_mark)
executed = True
else:
results = ()
for entity in results:
if isinstance(entity, Key):
key = entity
else:
key = entity.key()
if key in self.excluded_pks:
continue
yield self._make_entity(entity)
if executed and not isinstance(query, MultiQuery):
try:
self.query._gae_cursor = query.GetCompiledCursor()
except:
pass | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def count(self, limit=NOT_PROVIDED):
if self.included_pks is not None:
return len(self.get_matching_pk(0, limit))
if self.excluded_pks:
return len(list(self.fetch(0, 2000)))
# The datastore's Count() method has a 'limit' kwarg, which has
# a default value (obviously). This value can be overridden to
# anything you like, and importantly can be overridden to
# unlimited by passing a value of None. Hence *this* method
# has a default value of NOT_PROVIDED, rather than a default
# value of None
kw = {}
if limit is not NOT_PROVIDED:
kw['limit'] = limit
return self._build_query().Count(**kw) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def delete(self):
if self.included_pks is not None:
keys = [key for key in self.included_pks if key is not None]
else:
keys = self.fetch()
keys = list(keys)
if keys:
Delete(keys) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def order_by(self, ordering):
# GAE doesn't have any kind of natural ordering?
if not isinstance(ordering, bool):
for field, ascending in ordering:
column = '__key__' if field.primary_key else field.column
direction = Query.ASCENDING if ascending else Query.DESCENDING
self.ordering.append((column, direction)) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def add_filter(self, field, lookup_type, negated, value):
"""
This function is used by the default add_filters()
implementation.
"""
if lookup_type == 'ancestor':
self.ancestor_key = Key.from_path(value._meta.db_table, value.pk)
return
if lookup_type not in OPERATORS_MAP:
raise DatabaseError("Lookup type %r isn't supported." %
lookup_type)
# GAE does not let you store empty lists, so we can tell
# upfront that queriying for one will return nothing.
if value in ([], ()) and not negated:
self.included_pks = []
return
# Optimization: batch-get by key; this is only suitable for
# primary keys, not for anything that uses the key type.
if field.primary_key and lookup_type in ('exact', 'in'):
if self.included_pks is not None:
raise DatabaseError("You can't apply multiple AND "
"filters on the primary key. "
"Did you mean __in=[...]?")
if not isinstance(value, (tuple, list)):
value = [value]
pks = [pk for pk in value if pk is not None]
if field.rel:
pks = [ Key.from_path(self.db_table, pk.id_or_name()) for pk in pks ]
if negated:
self.excluded_pks = pks
else:
self.included_pks = pks
return
# We check for negation after lookup_type isnull because it
# simplifies the code. All following lookup_type checks assume
# that they're not negated.
if lookup_type == 'isnull':
if (negated and value) or not value:
# TODO/XXX: Is everything greater than None?
op = '>'
else:
op = '='
value = None
elif negated and lookup_type == 'exact':
if self.has_negated_exact_filter:
raise DatabaseError("You can't exclude more than one __exact "
"filter.")
self.has_negated_exact_filter = True
self._combine_filters(field, (('<', value), ('>', value)))
return
elif negated:
try:
op = NEGATION_MAP[lookup_type]
except KeyError:
raise DatabaseError("Lookup type %r can't be negated." %
lookup_type)
if self.inequality_field and field != self.inequality_field:
raise DatabaseError("Can't have inequality filters on "
"multiple fields (here: %r and %r)." %
(field, self.inequality_field))
self.inequality_field = field
elif lookup_type == 'in':
# Create sub-query combinations, one for each value.
if len(self.gae_query) * len(value) > 30:
raise DatabaseError("You can't query against more than "
"30 __in filter value combinations.")
op_values = [('=', v) for v in value]
self._combine_filters(field, op_values)
return
elif lookup_type == 'startswith':
# Lookup argument was converted to [arg, arg + u'\ufffd'].
self._add_filter(field, '>=', value[0])
self._add_filter(field, '<=', value[1])
return
elif lookup_type in ('range', 'year'):
self._add_filter(field, '>=', value[0])
op = '<=' if lookup_type == 'range' else '<'
self._add_filter(field, op, value[1])
return
else:
op = OPERATORS_MAP[lookup_type]
self._add_filter(field, op, value) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def _add_filter(self, field, op, value):
for query in self.gae_query:
# GAE uses a special property name for primary key filters.
if field.primary_key:
column = '__key__'
else:
column = field.column
key = '%s %s' % (column, op)
if isinstance(value, Text):
raise DatabaseError("TextField is not indexed, by default, "
"so you can't filter on it. Please add "
"an index definition for the field %s "
"on the model %s.%s as described here:\n"
"http://www.allbuttonspressed.com/blog/django/2010/07/Managing-per-field-indexes-on-App-Engine" %
(column, self.query.model.__module__,
self.query.model.__name__))
if key in query:
existing_value = query[key]
if isinstance(existing_value, list):
existing_value.append(value)
else:
query[key] = [existing_value, value]
else:
query[key] = value | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def _make_entity(self, entity):
if isinstance(entity, Key):
key = entity
entity = {}
else:
key = entity.key()
entity[self.query.get_meta().pk.column] = key
return entity | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def _build_query(self):
for query in self.gae_query:
query.Order(*self.ordering)
#This is an ancestor query
if self.ancestor_key:
query.Ancestor(self.ancestor_key)
if len(self.gae_query) > 1:
return MultiQuery(self.gae_query, self.ordering)
return self.gae_query[0] | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def order_pk_filtered(self, lhs, rhs):
left = dict(lhs)
left[self.query.get_meta().pk.column] = lhs.key().to_path()
right = dict(rhs)
right[self.query.get_meta().pk.column] = rhs.key().to_path()
return self._order_in_memory(left, right) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def __init__(self, where):
self.connector = where.connector
self.children = []
self.negated = where.negated | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def _parse_tree(_where):
if isinstance(_where, tuple):
return self._decode_child(_where)
node = ParseNode(_where)
for child in _where.children:
if isinstance(child, Node) and child.children:
if len(child.children) == 1:
next_level = _parse_tree(child.children[0])
else:
next_level = _parse_tree(child)
else:
next_level = self._decode_child(child)
node.children.append(next_level)
return node | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def matches_filters(self, entity):
"""
Checks if the GAE entity fetched from the database satisfies
the current query's constraints.
"""
item = dict(entity)
item[self.query.get_meta().pk.column] = entity.key()
return self._matches_filters(item, self.query.where) | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def get_count(self, check_exists=False):
try:
return super(SQLCompiler, self).get_count(check_exists)
except InvalidGaeKey:
return 0 | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
def results_iter(self):
try:
for x in super(SQLCompiler, self).results_iter():
yield x
except InvalidGaeKey:
yield iter([]).next() | potatolondon/djangoappengine-1-4 | [
3,
2,
3,
1,
1358943676
] |
Subsets and Splits